Commit Graph

15 Commits

Author SHA1 Message Date
a6c24489f6 Revert "gem5: save/restore moved to Gem5Controller"
This reverts commit d525005990.
2013-05-22 17:38:56 +02:00
d525005990 gem5: save/restore moved to Gem5Controller
Change-Id: I0ce72f04a8de88f4f8b6c1f0bba7a9097c82e107
2013-05-22 13:54:55 +02:00
896d6cc4c1 gem5: added getMnemonic() (requires breakpoints)
Change-Id: I5a2862a0ad3c3d506189a6196682e227205ebe09
2013-04-24 14:14:15 +02:00
08febe5819 gem5 build system improved
Encapsulated gem5-specific code into wrapper functions to separate the
build process (Fail: CMake, gem5: scons). Added some gem5-related FIXMEs.

Another CMake related FIXME added. +some cosmetics.

Change-Id: Id84b480127b1f13aed6a0ee97f3583f410d531c5
2013-04-08 17:57:06 +02:00
39a6415001 T32: Integrated Register read/write calls
* Tested without connected Lauterbach.
  T32_* functions are mocked via aspect.

* New target t32cli, for sending T32 command cia cli. (for testing)

git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2103 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2013-02-15 18:06:02 +00:00
f96f4dd360 typo-fix
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2075 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2013-02-07 10:43:07 +00:00
5c4b132550 ~SimulatorController: do not free ConcreteCPU object ptr in the base class
In fact, delete should be called in the destructor of each derived class (BochsController and Gem5Controller at the moment).

Additionally, this is the reason why ~SimulatorController is declared as virtual.

git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2064 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2013-02-06 15:39:50 +00:00
b052c0494b Architecture changes (only gem5 implementation right now):
- The register manager is gone. It's functionality is now encapsulated in the
  CPU classes.
- For the client, there is the ConcreteCPU class that encapsulates the access
  to the CPU state (including registers) and architecture details. The
  correspondig objects for the CPUs inside the simulator can be accessed
  through the SimulatorController.getCPU() function.
- Listener got a new ConcreteCPU* member to filter for which CPU the events
  should fire. The default NULL is used as wildcard for all aviable CPUs. The
  events respectively got a ConcreteCPU* member to indicate which CPU really
  fired the event.
- For the server, there is CPUArchitecture to access the architecture details.

git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1966 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-12-02 17:50:46 +00:00
247fed5aa7 Gem5: Implemented MemoryManager
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1863 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-10-28 23:50:08 +00:00
e0e95faa5b Restructured the gem5 backend:
- FailGem5Device is gone.
- There are now changes directly made to the gem5 source.
- Gem5Connector is a helper class that is compiled inside the gem5 context to workaround problems with gem5 header in fail.

Things that are working:
- BPSingleListener
- MemAccessListener
- Save and restore simulator state

git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1820 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-10-24 19:19:14 +00:00
171d178309 SimCon interface update: save returns a boolean, now (+ redundant virtual keywords removed).
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1724 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-10-05 12:12:56 +00:00
hsc
2fed94ae49 global interrupt_to_fire seems not to be Bochs-specific at the moment
FIXME: This shouldn't be a global variable (probably a SimulatorController
member?).  Reconsider interrupt generation being part of the generic
interface.

git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1612 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-09-11 17:10:11 +00:00
1403fa3828 Step 1 from experiment hsc-simple is now working with gem5
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1604 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-09-07 22:35:52 +00:00
c30011fc01 Gem5 is now linked against fail (not fully working)
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1466 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-08-01 16:40:16 +00:00
c06565aa4e Basic SAL files and makefile modifications for adding gem5.
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1457 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-07-17 15:35:29 +00:00