2547021e5d
- introduced improved logging in RATFlip
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- adapted the manual
- centralised output conversion
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1988 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-12-24 12:55:20 +00:00
378cabd996
Updated the manual, corrected some terms and found a bug
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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1970 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-12-06 14:47:42 +00:00
1b9583aede
Now the names of the experiments will be consistent with my written work
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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1956 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-11-24 09:37:38 +00:00
ba2c0bb83f
Corrected several bugs in RATFlip
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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1728 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-10-07 19:36:31 +00:00
301dc22494
Updated the L4Sys experiment flow
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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1726 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-10-05 16:20:13 +00:00
fd102c01ea
Important bugfix: passing the instruction cache entry pointer
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does not account for arrays of instructions provided
by one virtual instruction trace cache entry ->
passing the current instruction directly.
ALUInstr not yet completely tested.
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1704 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-10-01 17:51:34 +00:00
ea1c9f5716
First steps to integrate the fourth experiment type, still debugging
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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1587 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-09-02 17:17:39 +00:00
d9b24a7c60
Changes I made in the l4-sys experiment recently, plus one minor style fix
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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1584 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-09-01 16:05:22 +00:00
58822b02f3
Some improvements on L4, and correcting a mistake made in revision 1361 (see mailing list).
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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1377 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-06-21 14:19:21 +00:00
bff60aeae3
Additionally passing the current Bochs CPU context and instruction cache entry to BochsController (enables detailed instruction analysis and modification)
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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1361 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-06-15 16:39:14 +00:00
2575604b41
Fail* directories reorganized, Code-cleanup (-> coding-style), Typos+comments fixed.
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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1321 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-06-08 20:09:43 +00:00
