4d48e0207e
Some improvements in the UDIS86 wrapper
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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1730 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-10-08 08:33:28 +00:00
ba2c0bb83f
Corrected several bugs in RATFlip
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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1728 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-10-07 19:36:31 +00:00
fd102c01ea
Important bugfix: passing the instruction cache entry pointer
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does not account for arrays of instructions provided
by one virtual instruction trace cache entry ->
passing the current instruction directly.
ALUInstr not yet completely tested.
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1704 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-10-01 17:51:34 +00:00
d9b24a7c60
Changes I made in the l4-sys experiment recently, plus one minor style fix
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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1584 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-09-01 16:05:22 +00:00
22c5cdbde2
Adding some code to the L4-Sys experiment, and making it compile again.
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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1385 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-06-26 11:37:21 +00:00
09c3f64d51
Bugfixing in L4-Sys
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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1379 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-06-22 08:56:22 +00:00
