5 Commits

Author SHA1 Message Date
b8e706b1a5 T32SIM: Integrating Tracing feature of the T32SIM.
After each simulator break, T32Tracer retrieves the latest (16)
trace records from the T32. Memory address and value can now
be evaluated easily from the trace record.

TODO:Nevertheless we still have to traverse the trace to
find the instruction causing the access.
2013-03-21 18:57:46 +01:00
96bc39c05d T32 Simulator: Basic Instruction set sim for ARMM3
The T32 can simulate bare instruction sets without periphery.
For the Cortex-M3 we have complete NVIC model including Systick Timer.
Currently a simple CiAO can run on the simulator.

TODO:
 - Let memlogger log all memory accesses.
 - Interact with FailT32 for a complete simulation/FI
2013-03-20 17:17:38 +01:00
010137cf54 T32: Updated to recent T32 API. 2013-03-05 17:29:48 +01:00
d86d18bced T32: Code cleanup.
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2104 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2013-02-16 22:05:00 +00:00
39a6415001 T32: Integrated Register read/write calls
* Tested without connected Lauterbach.
  T32_* functions are mocked via aspect.

* New target t32cli, for sending T32 command cia cli. (for testing)

git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2103 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2013-02-15 18:06:02 +00:00