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Important bugfix: passing the instruction cache entry pointer

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does not account for arrays of instructions provided
by one virtual instruction trace cache entry ->
passing the current instruction directly.
ALUInstr not yet completely tested.


git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1704 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
This commit is contained in:
unzner
2012-10-01 17:51:34 +00:00
parent 1a9a72eaf4
commit fd102c01ea
13 changed files with 329 additions and 166 deletions
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32
src/experiments/l4-sys/l4sys.proto
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@ -11,24 +11,36 @@ message L4SysProtoMsg {
required int32 instr_offset = 2;
required int32 bit_offset = 3;
// registers
enum RegisterType {
EAX = 1;
ECX = 2;
EDX = 3;
EBX = 4;
ESP = 5;
EBP = 6;
ESI = 7;
EDI = 8;
}
optional RegisterType register_offset = 4;
// results
// make these optional to reduce overhead for server->client communication
enum ResultType {
DONE = 1;
TIMEOUT = 2;
TRAP = 3;
INTR = 4;
WRONG = 5;
UNKNOWN = 6;
INCOMPLETE = 2;
TIMEOUT = 3;
WRONG = 4;
UNKNOWN = 5;
}
// instruction pointer where injection was done
optional uint32 injection_ip = 4;
optional uint32 injection_ip = 5;
// result type, see above
optional ResultType resulttype = 5;
optional ResultType resulttype = 6;
// result data, depending on resulttype (see source code)
optional uint32 resultdata = 6;
optional uint32 resultdata = 7;
// generated output
optional string output = 7;
optional string output = 8;
// optional textual description of what happened
optional string details = 8;
optional string details = 9;
}