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tools/tests: small end-to-end test suite for importing/pruning

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As bigger changes lie ahead, we want a small end-to-end test suite
that ensures that our importing and tracing does not fall apart. With
this change, we add the infrastructure and two test-cases (fib, qsort)
including ELFs, traces, and injection results.

In order to run the basic-pruner test cases, one needs to setup a
MySQL table and set the CMake option ENABLE_DATABASE_TESTS.
This commit is contained in:
Christian Dietrich
2020-11-24 19:12:36 +01:00
committed by Horst Schirmeier
parent df44da9f33
commit f92b930acb
65 changed files with 198613 additions and 0 deletions
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488
tools/tests/qsort/state/serial Normal file
View File

@ -0,0 +1,488 @@
serial = {
0 = {
ls_interrupt = false
ms_interrupt = false
rx_interrupt = false
tx_interrupt = false
fifo_interrupt = false
ls_ipending = false
ms_ipending = false
rx_ipending = false
fifo_ipending = false
rx_fifo_end = 0
tx_fifo_end = 0
baudrate = 115200
rx_pollstate = 0
rxbuffer = 0x00
thrbuffer = 0x00
int_enable = {
rxdata_enable = false
txhold_enable = false
rxlstat_enable = false
modstat_enable = false
}
int_ident = {
ipending = false
int_ID = 0x01
}
fifo_cntl = {
enable = false
rxtrigger = 0x00
}
line_cntl = {
wordlen_sel = 0x00
stopbits = false
parity_enable = false
evenparity_sel = false
stick_parity = false
break_cntl = false
dlab = false
}
modem_cntl = {
dtr = false
rts = false
out1 = false
out2 = false
local_loopback = false
}
line_status = {
rxdata_ready = false
overrun_error = false
parity_error = false
framing_error = false
break_int = false
thr_empty = true
tsr_empty = true
fifo_error = false
}
modem_status = {
delta_cts = false
delta_dsr = false
ri_trailedge = false
delta_dcd = false
cts = true
dsr = true
ri = false
dcd = false
}
scratch = 0x00
tsrbuffer = 0x00
rx_fifo = {
0x00 = 0x00
0x01 = 0x00
0x02 = 0x00
0x03 = 0x00
0x04 = 0x00
0x05 = 0x00
0x06 = 0x00
0x07 = 0x00
0x08 = 0x00
0x09 = 0x00
0x0a = 0x00
0x0b = 0x00
0x0c = 0x00
0x0d = 0x00
0x0e = 0x00
0x0f = 0x00
}
tx_fifo = {
0x00 = 0x00
0x01 = 0x00
0x02 = 0x00
0x03 = 0x00
0x04 = 0x00
0x05 = 0x00
0x06 = 0x00
0x07 = 0x00
0x08 = 0x00
0x09 = 0x00
0x0a = 0x00
0x0b = 0x00
0x0c = 0x00
0x0d = 0x00
0x0e = 0x00
0x0f = 0x00
}
divisor_lsb = 0x01
divisor_msb = 0x00
}
1 = {
ls_interrupt = false
ms_interrupt = false
rx_interrupt = false
tx_interrupt = false
fifo_interrupt = false
ls_ipending = false
ms_ipending = false
rx_ipending = false
fifo_ipending = false
rx_fifo_end = 0
tx_fifo_end = 0
baudrate = 0
rx_pollstate = 0
rxbuffer = 0x00
thrbuffer = 0x00
int_enable = {
rxdata_enable = false
txhold_enable = false
rxlstat_enable = false
modstat_enable = false
}
int_ident = {
ipending = false
int_ID = 0x00
}
fifo_cntl = {
enable = false
rxtrigger = 0x00
}
line_cntl = {
wordlen_sel = 0x00
stopbits = false
parity_enable = false
evenparity_sel = false
stick_parity = false
break_cntl = false
dlab = false
}
modem_cntl = {
dtr = false
rts = false
out1 = false
out2 = false
local_loopback = false
}
line_status = {
rxdata_ready = false
overrun_error = false
parity_error = false
framing_error = false
break_int = false
thr_empty = false
tsr_empty = false
fifo_error = false
}
modem_status = {
delta_cts = false
delta_dsr = false
ri_trailedge = false
delta_dcd = false
cts = false
dsr = false
ri = false
dcd = false
}
scratch = 0x00
tsrbuffer = 0x00
rx_fifo = {
0x00 = 0x00
0x01 = 0x00
0x02 = 0x00
0x03 = 0x00
0x04 = 0x00
0x05 = 0x00
0x06 = 0x00
0x07 = 0x00
0x08 = 0x00
0x09 = 0x00
0x0a = 0x00
0x0b = 0x00
0x0c = 0x00
0x0d = 0x00
0x0e = 0x00
0x0f = 0x00
}
tx_fifo = {
0x00 = 0x00
0x01 = 0x00
0x02 = 0x00
0x03 = 0x00
0x04 = 0x00
0x05 = 0x00
0x06 = 0x00
0x07 = 0x00
0x08 = 0x00
0x09 = 0x00
0x0a = 0x00
0x0b = 0x00
0x0c = 0x00
0x0d = 0x00
0x0e = 0x00
0x0f = 0x00
}
divisor_lsb = 0x00
divisor_msb = 0x00
}
2 = {
ls_interrupt = false
ms_interrupt = false
rx_interrupt = false
tx_interrupt = false
fifo_interrupt = false
ls_ipending = false
ms_ipending = false
rx_ipending = false
fifo_ipending = false
rx_fifo_end = 0
tx_fifo_end = 0
baudrate = 0
rx_pollstate = 0
rxbuffer = 0x00
thrbuffer = 0x00
int_enable = {
rxdata_enable = false
txhold_enable = false
rxlstat_enable = false
modstat_enable = false
}
int_ident = {
ipending = false
int_ID = 0x00
}
fifo_cntl = {
enable = false
rxtrigger = 0x00
}
line_cntl = {
wordlen_sel = 0x00
stopbits = false
parity_enable = false
evenparity_sel = false
stick_parity = false
break_cntl = false
dlab = false
}
modem_cntl = {
dtr = false
rts = false
out1 = false
out2 = false
local_loopback = false
}
line_status = {
rxdata_ready = false
overrun_error = false
parity_error = false
framing_error = false
break_int = false
thr_empty = false
tsr_empty = false
fifo_error = false
}
modem_status = {
delta_cts = false
delta_dsr = false
ri_trailedge = false
delta_dcd = false
cts = false
dsr = false
ri = false
dcd = false
}
scratch = 0x00
tsrbuffer = 0x00
rx_fifo = {
0x00 = 0x00
0x01 = 0x00
0x02 = 0x00
0x03 = 0x00
0x04 = 0x00
0x05 = 0x00
0x06 = 0x00
0x07 = 0x00
0x08 = 0x00
0x09 = 0x00
0x0a = 0x00
0x0b = 0x00
0x0c = 0x00
0x0d = 0x00
0x0e = 0x00
0x0f = 0x00
}
tx_fifo = {
0x00 = 0x00
0x01 = 0x00
0x02 = 0x00
0x03 = 0x00
0x04 = 0x00
0x05 = 0x00
0x06 = 0x00
0x07 = 0x00
0x08 = 0x00
0x09 = 0x00
0x0a = 0x00
0x0b = 0x00
0x0c = 0x00
0x0d = 0x00
0x0e = 0x00
0x0f = 0x00
}
divisor_lsb = 0x00
divisor_msb = 0x00
}
3 = {
ls_interrupt = false
ms_interrupt = false
rx_interrupt = false
tx_interrupt = false
fifo_interrupt = false
ls_ipending = false
ms_ipending = false
rx_ipending = false
fifo_ipending = false
rx_fifo_end = 0
tx_fifo_end = 0
baudrate = 0
rx_pollstate = 0
rxbuffer = 0x00
thrbuffer = 0x00
int_enable = {
rxdata_enable = false
txhold_enable = false
rxlstat_enable = false
modstat_enable = false
}
int_ident = {
ipending = false
int_ID = 0x00
}
fifo_cntl = {
enable = false
rxtrigger = 0x00
}
line_cntl = {
wordlen_sel = 0x00
stopbits = false
parity_enable = false
evenparity_sel = false
stick_parity = false
break_cntl = false
dlab = false
}
modem_cntl = {
dtr = false
rts = false
out1 = false
out2 = false
local_loopback = false
}
line_status = {
rxdata_ready = false
overrun_error = false
parity_error = false
framing_error = false
break_int = false
thr_empty = false
tsr_empty = false
fifo_error = false
}
modem_status = {
delta_cts = false
delta_dsr = false
ri_trailedge = false
delta_dcd = false
cts = false
dsr = false
ri = false
dcd = false
}
scratch = 0x00
tsrbuffer = 0x00
rx_fifo = {
0x00 = 0x00
0x01 = 0x00
0x02 = 0x00
0x03 = 0x00
0x04 = 0x00
0x05 = 0x00
0x06 = 0x00
0x07 = 0x00
0x08 = 0x00
0x09 = 0x00
0x0a = 0x00
0x0b = 0x00
0x0c = 0x00
0x0d = 0x00
0x0e = 0x00
0x0f = 0x00
}
tx_fifo = {
0x00 = 0x00
0x01 = 0x00
0x02 = 0x00
0x03 = 0x00
0x04 = 0x00
0x05 = 0x00
0x06 = 0x00
0x07 = 0x00
0x08 = 0x00
0x09 = 0x00
0x0a = 0x00
0x0b = 0x00
0x0c = 0x00
0x0d = 0x00
0x0e = 0x00
0x0f = 0x00
}
divisor_lsb = 0x00
divisor_msb = 0x00
}
detect_mouse = 0
mouse_delayed_dx = 0
mouse_delayed_dy = 0
mouse_delayed_dz = 0
mouse_internal_buffer = {
num_elements = 0
buffer = {
0x00 = 0x00
0x01 = 0x00
0x02 = 0x00
0x03 = 0x00
0x04 = 0x00
0x05 = 0x00
0x06 = 0x00
0x07 = 0x00
0x08 = 0x00
0x09 = 0x00
0x0a = 0x00
0x0b = 0x00
0x0c = 0x00
0x0d = 0x00
0x0e = 0x00
0x0f = 0x00
0x10 = 0x00
0x11 = 0x00
0x12 = 0x00
0x13 = 0x00
0x14 = 0x00
0x15 = 0x00
0x16 = 0x00
0x17 = 0x00
0x18 = 0x00
0x19 = 0x00
0x1a = 0x00
0x1b = 0x00
0x1c = 0x00
0x1d = 0x00
0x1e = 0x00
0x1f = 0x00
0x20 = 0x00
0x21 = 0x00
0x22 = 0x00
0x23 = 0x00
0x24 = 0x00
0x25 = 0x00
0x26 = 0x00
0x27 = 0x00
0x28 = 0x00
0x29 = 0x00
0x2a = 0x00
0x2b = 0x00
0x2c = 0x00
0x2d = 0x00
0x2e = 0x00
0x2f = 0x00
}
head = 0
}
}