(capstone) feat: add capstone disassembler to tools/import-trace/
This commit is contained in:
Robin Thunig
committed by
Robin Thunig
Robin Thunig
parent
d04afaac54
commit
f7f982fec5
@ -3,8 +3,11 @@
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#include "RegisterImporter.hpp"
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#include "util/Logger.hpp"
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#ifdef BUILD_LLVM_DISASSEMBLER
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using namespace llvm;
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using namespace llvm::object;
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#endif
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using namespace fail;
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@ -29,7 +32,214 @@ bool RegisterImporter::cb_commandline_init() {
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return true;
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}
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#if defined(BUILD_CAPSTONE_DISASSEMBLER)
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bool RegisterImporter::addRegisterTrace(simtime_t curtime, instruction_count_t instr,
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Trace_Event &ev,
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const CapstoneToFailTranslator::reginfo_t &info,
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char access_type) {
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address_t from, to;
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int chunk_width;
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if (do_split_registers) {
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/* If we want to split the registers into one byte chunks (to
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enable proper pruning, we use a one byte window register,
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to determine beginning and end address */
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CapstoneToFailTranslator::reginfo_t one_byte_window = info;
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one_byte_window.width = 8;
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from = one_byte_window.toDataAddress();
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to = one_byte_window.toDataAddress() + info.width / 8;
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chunk_width = 1; // One byte chunks
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} else {
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/* We trace whole registers */
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from = info.toDataAddress();
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to = from + 1; /* exactly one trace event per register access*/
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chunk_width = (info.width / 8);
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}
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// Iterate over all accessed bytes
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for (address_t data_address = from; data_address < to; ++data_address) {
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// skip events outside a possibly supplied memory map
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if (m_mm && !m_mm->isMatching(ev.ip())) {
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continue;
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}
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margin_info_t left_margin = getOpenEC(data_address);
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margin_info_t right_margin;
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right_margin.time = curtime;
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right_margin.dyninstr = instr; // !< The current instruction
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right_margin.ip = ev.ip();
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// skip zero-sized intervals: these can occur when an instruction
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// accesses a memory location more than once (e.g., INC, CMPXCHG)
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if (left_margin.dyninstr > right_margin.dyninstr) {
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continue;
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}
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// we now have an interval-terminating R/W event to the memaddr
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// we're currently looking at; the EC is defined by
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// data_address, dynamic instruction start/end, the absolute PC at
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// the end, and time start/end
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// pass through potentially available extended trace information
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ev.set_width(chunk_width);
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ev.set_memaddr(data_address);
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ev.set_accesstype(access_type == 'R' ? ev.READ : ev.WRITE);
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if (!add_trace_event(left_margin, right_margin, ev)) {
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LOG << "add_trace_event failed" << std::endl;
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return false;
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}
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// next interval must start at next instruction; the aforementioned
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// skipping mechanism wouldn't work otherwise
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newOpenEC(data_address, curtime + 1, instr + 1, ev.ip());
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}
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return true;
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}
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bool RegisterImporter::handle_ip_event(fail::simtime_t curtime, instruction_count_t instr,
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Trace_Event &ev) {
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if (!isDisassembled) {
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// Parse command line again, for jump-from and jump-to
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// operations
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CommandLine &cmd = CommandLine::Inst();
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if (!cmd.parse()) {
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std::cerr << "Error parsing arguments." << std::endl;
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return false;
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}
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do_gp = !cmd[NO_GP];
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do_flags = cmd[FLAGS];
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do_ip = cmd[IP];
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do_split_registers = !cmd[NO_SPLIT];
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// retrieve register IDs for general-purpose and flags register(s) for
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// the configured architecture
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fail::Architecture arch;
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m_ip_register_id =
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(*arch.getRegisterSetOfType(RT_IP)->begin())->getId();
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fail::UniformRegisterSet *regset;
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if (do_gp) {
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regset = arch.getRegisterSetOfType(RT_GP);
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for (fail::UniformRegisterSet::iterator it = regset->begin();
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it != regset->end(); ++it) {
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m_register_ids.insert((*it)->getId());
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}
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}
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if (do_flags) {
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regset = arch.getRegisterSetOfType(RT_ST);
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for (fail::UniformRegisterSet::iterator it = regset->begin();
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it != regset->end(); ++it) {
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m_register_ids.insert((*it)->getId());
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}
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}
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if (!m_elf) {
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LOG << "Please give an ELF binary as parameter (-e/--elf)." << std::endl;
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return false;
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}
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disas.reset(new CapstoneDisassembler(m_elf));
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LOG << "Start to dissamble" << std::endl;
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disas->disassemble();
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LOG << "Get instr map" << std::endl;
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CapstoneDisassembler::InstrMap &instr_map = disas->getInstrMap();
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LOG << "instructions disassembled: " << std::dec << instr_map.size() << std::endl;
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m_ctof = disas->getTranslator();
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isDisassembled = true;
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}
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// instruction pointer is read + written at each instruction
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const CapstoneToFailTranslator::reginfo_t info_pc(m_ip_register_id);
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if (do_ip &&
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(!addRegisterTrace(curtime, instr, ev, info_pc, 'R') ||
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!addRegisterTrace(curtime, instr, ev, info_pc, 'W'))) {
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return false;
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}
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const CapstoneDisassembler::InstrMap &instr_map = disas->getInstrMap();
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if (instr_map.find(ev.ip()) == instr_map.end()) {
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LOG << "Could not find instruction for IP " << std::hex << ev.ip()
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<< ", skipping" << std::endl;
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return true;
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}
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const CapstoneDisassembler::Instr &opcode = instr_map.at(ev.ip());
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//const MCRegisterInfo ®_info = disas->getRegisterInfo();
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// LOG << std::hex << "Address: " << opcode.address << " Opcode: " << opcode.opcode << std::endl;
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// std::string log_regs = "Uses: ";
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for (std::vector<CapstoneDisassembler::register_t>::const_iterator it = opcode.reg_uses.begin();
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it != opcode.reg_uses.end(); ++it) {
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// log_regs += std::to_string(*it) + " ";
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const CapstoneToFailTranslator::reginfo_t &info = m_ctof->getFailRegisterInfo(*it);
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if (&info == &m_ctof->notfound) {
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// record failed translation, report later
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m_regnotfound[*it].count++;
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m_regnotfound[*it].address.insert(ev.ip());
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continue;
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}
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/* only proceed if we want to inject into this register */
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if (m_register_ids.find(info.id) == m_register_ids.end()) {
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// log_regs += "n ";
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continue;
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}
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if (!addRegisterTrace(curtime, instr, ev, info, 'R')) {
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return false;
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}
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}
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// log_regs += "Defs: ";
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for (std::vector<CapstoneDisassembler::register_t>::const_iterator it = opcode.reg_defs.begin();
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it != opcode.reg_defs.end(); ++it) {
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// log_regs += std::to_string(*it) + " ";
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const CapstoneToFailTranslator::reginfo_t &info = m_ctof->getFailRegisterInfo(*it);
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if (&info == &m_ctof->notfound) {
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// record failed translation, report later
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m_regnotfound[*it].count++;
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m_regnotfound[*it].address.insert(ev.ip());
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continue;
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}
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/* only proceed if we want to inject into this register */
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if (m_register_ids.find(info.id) == m_register_ids.end()) {
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// log_regs += "n ";
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continue;
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}
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if (!addRegisterTrace(curtime, instr, ev, info, 'W'))
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return false;
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}
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// LOG << log_regs.c_str() << std::endl;
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return true;
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}
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bool RegisterImporter::trace_end_reached()
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{
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// report failed LLVM -> FAIL* register mappings, if any
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if (m_regnotfound.empty()) {
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return true;
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}
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LOG << "WARNING: Some LLVM -> FAIL* register mappings failed during import, these will not be injected into:" << std::endl;
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for (auto it = m_regnotfound.cbegin(); it != m_regnotfound.cend(); ++it) {
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const CapstoneDisassembler::register_t id = it->first;
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const RegNotFound& rnf = it->second;
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LOG << "Capstone register " << std::dec << id
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/* << " \"" << disas->getRegisterInfo().getName(id) << "\": " */
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<< "seen " << rnf.count << " times in the trace" << std::endl;
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std::ostream& o = LOG << " corresponding instruction addresses in ELF binary: " << std::hex;
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for (auto addr_it = rnf.address.cbegin(); addr_it != rnf.address.cend(); ++addr_it) {
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if (addr_it != rnf.address.cbegin()) {
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o << ", ";
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}
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o << "0x" << *addr_it;
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}
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o << std::endl;
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}
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return true;
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}
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#elif defined(BUILD_LLVM_DISASSEMBLER)
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bool RegisterImporter::addRegisterTrace(simtime_t curtime, instruction_count_t instr,
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Trace_Event &ev,
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const LLVMtoFailTranslator::reginfo_t &info,
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@ -177,9 +387,12 @@ bool RegisterImporter::handle_ip_event(fail::simtime_t curtime, instruction_coun
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}
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const LLVMDisassembler::Instr &opcode = instr_map.at(ev.ip());
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//const MCRegisterInfo ®_info = disas->getRegisterInfo();
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// LOG << std::hex << "Address: " << opcode.address << " Opcode: " << opcode.opcode << std::endl;
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// std::string log_regs = "Uses: ";
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for (std::vector<LLVMDisassembler::register_t>::const_iterator it = opcode.reg_uses.begin();
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it != opcode.reg_uses.end(); ++it) {
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// log_regs += std::to_string(*it) + " ";
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const LLVMtoFailTranslator::reginfo_t &info = m_ltof->getFailRegisterInfo(*it);
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if (&info == &m_ltof->notfound) {
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// record failed translation, report later
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@ -198,8 +411,10 @@ bool RegisterImporter::handle_ip_event(fail::simtime_t curtime, instruction_coun
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}
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}
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// log_regs += "Defs: ";
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for (std::vector<LLVMDisassembler::register_t>::const_iterator it = opcode.reg_defs.begin();
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it != opcode.reg_defs.end(); ++it) {
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// log_regs += std::to_string(*it) + " ";
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const LLVMtoFailTranslator::reginfo_t &info = m_ltof->getFailRegisterInfo(*it);
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if (&info == &m_ltof->notfound) {
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// record failed translation, report later
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@ -210,12 +425,14 @@ bool RegisterImporter::handle_ip_event(fail::simtime_t curtime, instruction_coun
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/* only proceed if we want to inject into this register */
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if (m_register_ids.find(info.id) == m_register_ids.end()) {
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// log_regs += "n ";
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continue;
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}
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if (!addRegisterTrace(curtime, instr, ev, info, 'W'))
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return false;
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}
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// LOG << log_regs.c_str() << std::endl;
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return true;
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}
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@ -246,3 +463,4 @@ bool RegisterImporter::trace_end_reached()
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return true;
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}
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#endif
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