qemu: IOPortListener

git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1622 8c4709b5-6ec9-48aa-a5cd-a96041d1645a

src/core/sal/bochs/BochsController.cc

@@ -124,7 +124,7 @@ void BochsController::updateBPEventInfo(BX_CPU_C *context, bxICacheEntry_c *cach
 }
 
 void BochsController::onIOPort(unsigned char data, unsigned port, bool out) {
-	// Check for active breakpoint-events:
+	// Check for active IOPortListeners:
 	io_cache_t &buffer_cache = m_LstList.getIOBuffer();
 	io_cache_t::iterator it = buffer_cache.begin();
 	while (it != buffer_cache.end()) {
@@ -139,8 +139,6 @@ void BochsController::onIOPort(unsigned char data, unsigned port, bool out) {
 		it++;
 	}
 	m_LstList.triggerActiveListeners();
-	// Note: SimulatorController::onBreakpoint will not be invoked in this
-	//       implementation.
 }
 
 void BochsController::save(const std::string& path)

src/core/sal/qemu/QEMUController.cc

@@ -21,4 +21,23 @@ QEMUController::~QEMUController()
 	delete m_Mem;
 }
 
+// FIXME: copied from BochsController; remove redundancy!
+void QEMUController::onIOPort(unsigned char data, unsigned port, bool out) {
+	// Check for active IOPortListeners:
+	io_cache_t &buffer_cache = m_LstList.getIOBuffer();
+	io_cache_t::iterator it = buffer_cache.begin();
+	while (it != buffer_cache.end()) {
+		IOPortListener* pIOPt = (*it);
+		if (pIOPt->isMatching(port, out)) {
+			pIOPt->setData(data);
+			it = buffer_cache.makeActive(m_LstList, it);
+			// "it" has already been set to the next element (by calling
+			// makeActive()):
+			continue; // -> skip iterator increment
+		}
+		it++;
+	}
+	m_LstList.triggerActiveListeners();
+}
+
 } // end-of-namespace: fail

src/core/sal/qemu/QEMUController.hpp

@@ -28,12 +28,15 @@ public:
 	QEMUController();
 	~QEMUController();
 	/**
-	 * I/O port communication handler. This method is called from QEMU.  TODO.
+	 * I/O port communication handler. This method is called from QEMU.
 	 * @param data the data transmitted
 	 * @param port the port it was transmitted on
 	 * @param out true if the I/O traffic has been outbound, false otherwise
+	 * FIXME Should this be part of the generic interface?  Inherited from some generic x86 arch class?
+	 * FIXME Access width should be part of the interface.
+	 * FIXME Read/Write should be separate listeners.
 	 */
-	void onIOPort(unsigned char data, unsigned port, bool out) {}
+	void onIOPort(unsigned char data, unsigned port, bool out);
 	/**
 	 * Static internal handler for TimerListeners.  TODO.
 	 */

src/core/sal/qemu/wrappers.cc

@@ -24,4 +24,10 @@ void fail_watchpoint_hit(struct CPUX86State *env, uint64_t addr, int width, int
 	fail::simulator.onMemoryAccess(addr, width, is_write == 1, 0);
 }
 
+void fail_io(int port, int width, int32_t data, int is_write)
+{
+	// FIXME: width is discarded
+	fail::simulator.onIOPort((unsigned char)data, port, is_write == 1);
+}
+
 }

src/experiments/rampage/experiment.cc

@@ -43,56 +43,42 @@ bool RAMpageExperiment::run()
 
 	MemWriteListener l_mem1(addr1);
 	MemoryManager& mm = simulator.getMemoryManager();
-	while (true) {
+	IOPortListener l_io(0x2f8, true); // ttyS1 aka COM2
-		simulator.addListener(&l_mem1);
-		simulator.resume();
-		unsigned char data = mm.getByte(addr1);
-#if 1
-		//data |= 1 << bit1; // stuck-to-1
-		mm.setByte(addr1, data);
-#elif 0
-		data &= ~(1 << bit1); // stuck-to-0
-		mm.setByte(addr1, data);
-#elif 0
-		data &= ~(1 << bit2); // coupling bit2 := bit1
-		data |= ((data & (1 << bit1)) != 0) << bit2;
-		mm.setByte(addr1, data);
-#elif 0
-		data &= ~(1 << bit2); // coupling bit2 := !bit1
-		data |= ((data & (1 << bit1)) == 0) << bit2;
-		mm.setByte(addr1, data);
-#elif 0
-		unsigned char data2 = mm.getByte(addr2);
-		data2 &= ~(1 << bit2); // coupling addr2:bit2 := !addr1:bit1
-		data2 |= ((data & (1 << bit1)) == 0) << bit2;
-		mm.setByte(addr2, data2);
-#endif
-		log << "access to addr 0x" << std::hex << addr1 << ", FI!" << endl;
-	}
-
-	/*
-	MemWriteListener l_mem2(addr2);
-	
-	log << "startup" << endl;
 
 	simulator.addListener(&l_mem1);
-	simulator.addListener(&l_mem2);
+	simulator.addListener(&l_io);
-
 	while (true) {
-		MemWriteListener *l = static_cast<MemWriteListener*>(simulator.resume());
+		BaseListener *l = simulator.resume();
-		simulator.addListener(l);
-
-		address_t target;
 
 		if (l == &l_mem1) {
-			target = addr2;
+			simulator.addListener(&l_mem1);
-		} else {
+			unsigned char data = mm.getByte(addr1);
-			target = addr1;
+#if 1
+			data |= 1 << bit1; // stuck-to-1
+			mm.setByte(addr1, data);
+#elif 0
+			data &= ~(1 << bit1); // stuck-to-0
+			mm.setByte(addr1, data);
+#elif 0
+			data &= ~(1 << bit2); // coupling bit2 := bit1
+			data |= ((data & (1 << bit1)) != 0) << bit2;
+			mm.setByte(addr1, data);
+#elif 0
+			data &= ~(1 << bit2); // coupling bit2 := !bit1
+			data |= ((data & (1 << bit1)) == 0) << bit2;
+			mm.setByte(addr1, data);
+#elif 0
+			unsigned char data2 = mm.getByte(addr2);
+			data2 &= ~(1 << bit2); // coupling addr2:bit2 := !addr1:bit1
+			data2 |= ((data & (1 << bit1)) == 0) << bit2;
+			mm.setByte(addr2, data2);
+#endif
+			log << "access to addr 0x" << std::hex << addr1 << ", FI!" << endl;
+		} else if (l == &l_io) {
+			simulator.addListener(&l_io);
+			std::cout << l_io.getData() << std::endl;
 		}
-		
-		unsigned char data = simulator.getMemoryManager().getByte(l->getWatchAddress());
-		data ^= (
 	}
-	*/
+
 	return true;
 }