First steps to integrate the fourth experiment type, still debugging
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1587 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
This commit is contained in:
unzner
@ -1,12 +1,14 @@
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#ifndef __L4SYS_ALUINSTR_HPP__
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#define __L4SYS_ALUINSTR_HPP__
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#if 0
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/**
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* Forward declaration of the Bochs instruction decode table.
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* This is necessary because, inconveniently, it is not declared in a header file.
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*/
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#include "cpu/fetchdecode.h"
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static const BxOpcodeInfo_t *BxOpcodeInfo32;
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#endif
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/**
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* Trying to order X86 ALU instructions.
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@ -54,7 +56,10 @@ struct BochsALUInstr {
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Bit8u opcode;
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/**
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* the reg part of the modr/m field (known as nnn in bxInstruction_c)
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* A value of 8 or higher marks this field unused.
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* it is used to
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* a) further subdivide the functionality of a given opcode
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* b) specify a register the instruction is supposed to use
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* In this class, a value of 8 or higher marks this field unused.
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*/
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Bit8u reg;
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/**
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@ -63,7 +68,7 @@ struct BochsALUInstr {
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* to their opcode. It is necessary to store this separately for
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* several reasons, one being the ability to separate
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* ALU input latch faults from ALU instruction latch faults.
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* A value of 8 or higher marks this field unused.
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* In this class, a value of 8 or higher marks this field unused.
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*/
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Bit8u opcodeRegisterOffset;
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/**
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@ -141,90 +146,77 @@ const BochsALUInstr aluInstructions [] = {
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#undef SHIFTOPS
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/* --- \\\ SHIFT OPERATIONS /// --- */
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/**
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*
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* The remaining instructions, roughly ordered,
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* in the form of a (probably obsolete) experiment method
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* /**
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* Assigns a given opcode a class of ALU instructions
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* @param opcode the opcode to examine
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* @returns an enum AluClass object
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/* --- /// BINARY OPERATIONS \\\ --- */
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X86AluClass isALUInstruction(unsigned opcode);
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*
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* X86AluClass L4SysExperiment::isALUInstruction(unsigned opcode) {
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switch (opcode) {
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case BX_IA_ADC_EbGb:
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case BX_IA_ADC_EdGd:
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case BX_IA_ADC_EwGw:
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case BX_IA_ADD_EbGb:
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case BX_IA_ADD_EdGd:
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case BX_IA_ADD_EwGw:
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case BX_IA_AND_EbGb:
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case BX_IA_AND_EdGd:
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case BX_IA_AND_EwGw:
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case BX_IA_CMP_EbGb:
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case BX_IA_CMP_EdGd:
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case BX_IA_CMP_EwGw:
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case BX_IA_OR_EbGb:
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case BX_IA_OR_EdGd:
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case BX_IA_OR_EwGw:
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case BX_IA_SBB_EbGb:
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case BX_IA_SBB_EdGd:
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case BX_IA_SBB_EwGw:
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case BX_IA_SUB_EbGb:
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case BX_IA_SUB_EdGd:
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case BX_IA_SUB_EwGw:
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case BX_IA_XOR_EbGb:
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case BX_IA_XOR_EdGd:
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case BX_IA_XOR_EwGw:
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case BX_IA_ADC_ALIb:
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case BX_IA_ADC_AXIw:
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case BX_IA_ADC_EAXId:
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case BX_IA_ADD_EbIb:
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case BX_IA_OR_EbIb:
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case BX_IA_ADC_EbIb:
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case BX_IA_SBB_EbIb:
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case BX_IA_AND_EbIb:
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case BX_IA_SUB_EbIb:
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case BX_IA_XOR_EbIb:
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case BX_IA_CMP_EbIb:
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case BX_IA_ADD_EwIw:
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case BX_IA_OR_EwIw:
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case BX_IA_ADC_EwIw:
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case BX_IA_SBB_EwIw:
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case BX_IA_AND_EwIw:
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case BX_IA_SUB_EwIw:
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case BX_IA_XOR_EwIw:
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case BX_IA_CMP_EwIw:
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case BX_IA_ADD_EdId:
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case BX_IA_OR_EdId:
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case BX_IA_ADC_EdId:
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case BX_IA_SBB_EdId:
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case BX_IA_AND_EdId:
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case BX_IA_SUB_EdId:
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case BX_IA_XOR_EdId:
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case BX_IA_CMP_EdId:
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case BX_IA_ADC_GbEb:
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case BX_IA_ADC_GwEw:
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case BX_IA_ADC_GdEd:
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case BX_IA_ADD_ALIb:
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case BX_IA_ADD_AXIw:
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case BX_IA_ADD_EAXId:
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case BX_IA_ADD_GbEb:
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case BX_IA_ADD_GwEw:
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case BX_IA_ADD_GdEd:
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case BX_IA_AND_ALIb:
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case BX_IA_AND_AXIw:
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case BX_IA_AND_EAXId:
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case BX_IA_AND_GbEb:
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case BX_IA_AND_GwEw:
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case BX_IA_AND_GdEd:
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default:
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return ALU_UNDEF;
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}
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}
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*
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*/
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// reg, immediate
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// a macro to reduce copy-paste overhead
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#define BINOPS(IACODE, OPCODE8, OPCODE16) \
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{ BX_IA_##IACODE##_ALIb, OPCODE8, 8, 8, ALU_IMM8_REG }, \
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{ BX_IA_##IACODE##_AXIw, OPCODE16, 8, 8, ALU_IMM16_REG }, \
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{ BX_IA_##IACODE##_EAXId, OPCODE16, 8, 8, ALU_IMM32_REG }
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// register ax, immediate
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BINOPS(ADC, 0x14, 0x15),
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BINOPS(ADD, 0x04, 0x05),
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BINOPS(AND, 0x24, 0x25),
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BINOPS(CMP, 0x3C, 0x3D),
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BINOPS(OR, 0x0C, 0x0D),
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BINOPS(SBB, 0x1C, 0x1D),
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BINOPS(SUB, 0x2C, 0x2D),
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BINOPS(XOR, 0x34, 0x35),
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#undef BINOPS
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// a macro to reduce copy-paste overhead
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#define BINOPS(IACODE, OPCODE8, OPCODE16) \
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{ BX_IA_##IACODE##_EbGb, OPCODE8, 7, 8, ALU_IMM8_RM8 }, \
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{ BX_IA_##IACODE##_EwGw, OPCODE16, 7, 8, ALU_IMM16_RM16 }, \
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{ BX_IA_##IACODE##_EdGd, OPCODE16, 7, 8, ALU_IMM32_RM32 }
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// r/m, arbitrary register
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BINOPS(ADC, 0x10, 0x11),
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BINOPS(ADD, 0x00, 0x01),
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BINOPS(AND, 0x20, 0x21),
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BINOPS(CMP, 0x38, 0x39),
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BINOPS(OR, 0x08, 0x09),
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BINOPS(SBB, 0x18, 0x19),
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BINOPS(SUB, 0x28, 0x29),
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BINOPS(XOR, 0x30, 0x31),
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#undef BINOPS
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#define BINOPS(IACODE, OPCODE8, OPCODE16) \
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{ BX_IA_##IACODE##_GbEb, OPCODE8, 7, 8, ALU_IMM8_RM8 }, \
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{ BX_IA_##IACODE##_GwEw, OPCODE16, 7, 8, ALU_IMM16_RM16 }, \
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{ BX_IA_##IACODE##_GdEd, OPCODE16, 7, 8, ALU_IMM32_RM32 }
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// arbitrary register, r/m
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BINOPS(ADC, 0x12, 0x13),
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BINOPS(ADD, 0x02, 0x03),
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BINOPS(AND, 0x22, 0x23),
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BINOPS(CMP, 0x3a, 0x3b),
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BINOPS(OR, 0x0a, 0x0b),
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BINOPS(SBB, 0x1a, 0x1b),
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BINOPS(SUB, 0x2a, 0x2b),
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BINOPS(XOR, 0x32, 0x33),
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#undef BINOPS
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// a macro to reduce copy-paste overhead
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#define BINOPS(OPCODE, WDE, WDI, CLASS) \
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{ BX_IA_ADC_E##WDE##I##WDI, OPCODE, 2, 8, CLASS }, \
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{ BX_IA_ADD_E##WDE##I##WDI, OPCODE, 0, 8, CLASS }, \
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{ BX_IA_AND_E##WDE##I##WDI, OPCODE, 4, 8, CLASS }, \
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{ BX_IA_CMP_E##WDE##I##WDI, OPCODE, 7, 8, CLASS }, \
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{ BX_IA_OR_E##WDE##I##WDI, OPCODE, 1, 8, CLASS }, \
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{ BX_IA_SBB_E##WDE##I##WDI, OPCODE, 3, 8, CLASS }, \
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{ BX_IA_SUB_E##WDE##I##WDI, OPCODE, 5, 8, CLASS }, \
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{ BX_IA_XOR_E##WDE##I##WDI, OPCODE, 6, 8, CLASS }
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BINOPS(80, b, b, ALU_IMM8_RM8),
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BINOPS(81, w, w, ALU_IMM16_RM16),
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BINOPS(81, d, d, ALU_IMM32_RM32),
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BINOPS(83, w, w, ALU_IMM8_RM16),
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BINOPS(83, d, d, ALU_IMM8_RM32),
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#undef BINOPS
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/* --- \\\ BINARY OPERATIONS /// --- */
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};
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#endif // __L4SYS_ALUINSTR_HPP__
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