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fault-coverage fix due to arch. changes

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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2035 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
This commit is contained in:
adrian
2013-01-31 12:18:58 +00:00
parent ec54a1481c
commit e76b7b989b
1 changed files with 12 additions and 13 deletions
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25
src/experiments/fault-coverage/experiment.cc
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@ -5,6 +5,7 @@
#include <time.h> #include <time.h>
#include "experiment.hpp" #include "experiment.hpp"
#include "sal/Listener.hpp"
#include "sal/SALInst.hpp" #include "sal/SALInst.hpp"
#include "util/Logger.hpp" #include "util/Logger.hpp"
@ -51,11 +52,15 @@ bool FaultCoverageExperiment::run()
simulator.save("./bochs_save_point"); simulator.save("./bochs_save_point");
log << "Logging results on std::cout." << endl; log << "Logging results on std::cout." << endl;
RegisterManager& regMan = simulator.getRegisterManager();
// Note: This heavily uses the save-restore feature which causes
// causes a memory leak after several rounds (seg-fault).
// iterate over all registers // iterate over all registers
for (RegisterManager::iterator it = regMan.begin(); it != regMan.end(); it++) { ConcreteCPU cpu = simulator.getCPU(0);
for (ConcreteCPU::iterator it = cpu.begin(); it != cpu.end(); it++) {
Register* pReg = *it; // get a ptr to the current register-object Register* pReg = *it; // get a ptr to the current register-object
// loop over the 32 bits within this register // loop over the 32 (64) bits within this register
for (regwidth_t bitnr = 0; bitnr < pReg->getWidth(); ++bitnr) { for (regwidth_t bitnr = 0; bitnr < pReg->getWidth(); ++bitnr) {
// loop over all instruction addresses of observed function // loop over all instruction addresses of observed function
for (int instr = 0; ; ++instr) { for (int instr = 0; ; ++instr) {
@ -84,9 +89,9 @@ bool FaultCoverageExperiment::run()
} }
// inject bit-flip at bit $bitnr in register $reg // inject bit-flip at bit $bitnr in register $reg
regdata_t data = pReg->getData(); regdata_t data = cpu.getRegisterContent(pReg);
data ^= 1 << bitnr; data ^= 1 << bitnr;
pReg->setData(data); // write back data to register cpu.setRegisterContent(pReg, data); // write back data to register
// catch traps and timeout // catch traps and timeout
TrapListener ev_trap; // any traps TrapListener ev_trap; // any traps
@ -99,14 +104,8 @@ bool FaultCoverageExperiment::run()
BaseListener* ev = simulator.resume(); BaseListener* ev = simulator.resume();
if (ev == &ev_func_end) { if (ev == &ev_func_end) {
// log result // log result
#if BX_SUPPORT_X86_64 Register* pCAX = cpu.getRegister(RID_CAX);
const size_t expected_size = sizeof(uint32_t)*8; regdata_t result = cpu.getRegisterContent(pCAX);
#else
const size_t expected_size = sizeof(uint64_t)*8;
#endif
Register* pCAX = simulator.getRegisterManager().getSetOfType(RT_GP)->getRegister(RID_CAX);
assert(expected_size == pCAX->getWidth()); // we assume to get 32(64) bits...
regdata_t result = pCAX->getData();
log << "Reg: " << pCAX->getName() << ", #Bit: " << bitnr log << "Reg: " << pCAX->getName() << ", #Bit: " << bitnr
<< ", Instr-Idx: " << instr << ", Data: " << result << endl; << ", Instr-Idx: " << instr << ", Data: " << result << endl;
} }