core/sal: interface for backend-specific notion of time

This adds an interface for a backend-specific notion of time, e.g. CPU
cycles since simulator start, and a concrete implementation for the
Bochs backend.  This is needed to record CPU idle times (e.g., HLT
instruction), and for target backends capable of more timing-accurate
execution.

This change also modifies the tracing plugin to add the time to all
trace events.

Change-Id: I93ac1d54c07f32b0b8f84f333417741d8e9c8288
This commit is contained in:
Horst Schirmeier
2013-03-28 19:22:08 +01:00
parent 6b5728ece1
commit e5fe9dd525
6 changed files with 53 additions and 4 deletions

View File

@ -28,6 +28,8 @@ except IOError:
print sys.argv[1] + ": Could not open file."
sys.exit(-1)
acctime = 0
while True:
# Read trace length
try:
@ -45,18 +47,23 @@ while True:
# print trace_event
# More compact dump for traces:
if trace_event.HasField("time_delta"):
acctime += trace_event.time_delta
# As time_delta fields are omitted where the delta is 0, every event
# implicitly has a timestamp.
time = " t={0}".format(acctime)
if not trace_event.HasField("memaddr"):
print "IP {0:x}".format(trace_event.ip)
print "IP {0:x}{1}".format(trace_event.ip, time)
else:
ext = ""
if trace_event.HasField("trace_ext"):
ext = "DATA {0:x}".format(trace_event.trace_ext.data)
ext = " DATA {0:x}".format(trace_event.trace_ext.data)
for reg in trace_event.trace_ext.registers:
ext += " REG: {0} *{1:x}={2:x}".format(reg.id, reg.value, reg.value_deref)
if len(trace_event.trace_ext.stack) > 0:
ext += " STACK: " + "".join(["%x"%x for x in trace_event.trace_ext.stack])
print "MEM {0} {1:x} width {2:d} IP {3:x} {4}".format(
print "MEM {0} {1:x} width {2:d} IP {3:x}{4}{5}".format(
"R" if trace_event.accesstype == trace_event.READ else "W",
trace_event.memaddr, trace_event.width, trace_event.ip, ext)
trace_event.memaddr, trace_event.width, trace_event.ip, ext, time)
f.close()