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Bochs aspects -> BochsController interface renamings

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SimulatorController::on...Listener() does not really make sense: These
functions are called when a specific event occurs in the simulator.  A
"Listener" cannot occur.  Renaming these to "on..." for now; we could
alternatively use "on...Event" later.

git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1455 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
This commit is contained in:
hsc
2012-07-16 18:21:06 +00:00
parent b245327b7e
commit e4570d95bd
10 changed files with 43 additions and 43 deletions
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16
src/core/sal/SimulatorController.cc
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@ -43,10 +43,10 @@ void SimulatorController::initExperiments()
/* empty. */ /* empty. */
} }
void SimulatorController::onBreakpointListener(address_t instrPtr, address_t address_space) void SimulatorController::onBreakpoint(address_t instrPtr, address_t address_space)
{ {
assert(false && assert(false &&
"FIXME: SimulatorController::onBreakpointListener() has not been tested before"); "FIXME: SimulatorController::onBreakpoint() has not been tested before");
// FIXME: Improve performance! // FIXME: Improve performance!
// Loop through all events of type BP*Listener: // Loop through all events of type BP*Listener:
@ -71,8 +71,8 @@ void SimulatorController::onBreakpointListener(address_t instrPtr, address_t add
m_LstList.triggerActiveListeners(); m_LstList.triggerActiveListeners();
} }
void SimulatorController::onMemoryAccessListener(address_t addr, size_t len, void SimulatorController::onMemoryAccess(address_t addr, size_t len,
bool is_write, address_t instrPtr) bool is_write, address_t instrPtr)
{ {
// FIXME: Improve performance! // FIXME: Improve performance!
MemAccessListener::accessType_t accesstype = MemAccessListener::accessType_t accesstype =
@ -97,7 +97,7 @@ void SimulatorController::onMemoryAccessListener(address_t addr, size_t len,
m_LstList.triggerActiveListeners(); m_LstList.triggerActiveListeners();
} }
void SimulatorController::onInterruptListener(unsigned interruptNum, bool nmi) void SimulatorController::onInterrupt(unsigned interruptNum, bool nmi)
{ {
ListenerManager::iterator it = m_LstList.begin(); ListenerManager::iterator it = m_LstList.begin();
while (it != m_LstList.end()) { // check for active events while (it != m_LstList.end()) { // check for active events
@ -155,7 +155,7 @@ bool SimulatorController::removeSuppressedInterrupt(unsigned interruptNum)
return false; return false;
} }
void SimulatorController::onTrapListener(unsigned trapNum) void SimulatorController::onTrap(unsigned trapNum)
{ {
ListenerManager::iterator it = m_LstList.begin(); ListenerManager::iterator it = m_LstList.begin();
while (it != m_LstList.end()) { // check for active events while (it != m_LstList.end()) { // check for active events
@ -171,7 +171,7 @@ void SimulatorController::onTrapListener(unsigned trapNum)
m_LstList.triggerActiveListeners(); m_LstList.triggerActiveListeners();
} }
void SimulatorController::onGuestSystemListener(char data, unsigned port) void SimulatorController::onGuestSystem(char data, unsigned port)
{ {
ListenerManager::iterator it = m_LstList.begin(); ListenerManager::iterator it = m_LstList.begin();
while (it != m_LstList.end()) { // check for active events while (it != m_LstList.end()) { // check for active events
@ -188,7 +188,7 @@ void SimulatorController::onGuestSystemListener(char data, unsigned port)
m_LstList.triggerActiveListeners(); m_LstList.triggerActiveListeners();
} }
void SimulatorController::onJumpListener(bool flagTriggered, unsigned opcode) void SimulatorController::onJump(bool flagTriggered, unsigned opcode)
{ {
ListenerManager::iterator it = m_LstList.begin(); ListenerManager::iterator it = m_LstList.begin();
while (it != m_LstList.end()) { // check for active events while (it != m_LstList.end()) { // check for active events

28
src/core/sal/SimulatorController.hpp
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@ -59,17 +59,17 @@ public:
*/ */
void initExperiments(); void initExperiments();
/* ******************************************************************** /* ********************************************************************
* Standard Listener Handler API * Standard Event Handler API
* ********************************************************************/ * ********************************************************************/
/** /**
* Breakpoint listener handler. This routine needs to be called in the * Breakpoint handler. This routine needs to be called in the simulator
* simulator specific backend each time a breakpoint listener occurs. * specific backend each time a breakpoint occurs.
* @param instrPtr the instruction pointer of the breakpoint listener * @param instrPtr the instruction pointer of the breakpoint
* @param address_space the address space it should occur in * @param address_space the address space it should occur in
*/ */
void onBreakpointListener(address_t instrPtr, address_t address_space); void onBreakpoint(address_t instrPtr, address_t address_space);
/** /**
* Memory access listener handler (read/write). * Memory access handler (read/write).
* @param addr the accessed memory address * @param addr the accessed memory address
* @param len the length of the accessed memory * @param len the length of the accessed memory
* @param is_write \c true if memory is written, \c false if read * @param is_write \c true if memory is written, \c false if read
@ -78,31 +78,31 @@ public:
* *
* FIXME: should instrPtr be part of this interface? * FIXME: should instrPtr be part of this interface?
*/ */
void onMemoryAccessListener(address_t addr, size_t len, bool is_write, address_t instrPtr); void onMemoryAccess(address_t addr, size_t len, bool is_write, address_t instrPtr);
/** /**
* Interrupt listener handler. * Interrupt handler.
* @param interruptNum the interrupt-type id * @param interruptNum the interrupt-type id
* @param nmi nmi-value from guest-system * @param nmi nmi-value from guest-system
*/ */
void onInterruptListener(unsigned interruptNum, bool nmi); void onInterrupt(unsigned interruptNum, bool nmi);
/** /**
* Trap listener handler. * Trap handler.
* @param trapNum the trap-type id * @param trapNum the trap-type id
*/ */
void onTrapListener(unsigned trapNum); void onTrap(unsigned trapNum);
/** /**
* Guest system communication handler. * Guest system communication handler.
* @param data the "message" from the guest system * @param data the "message" from the guest system
* @param port the port of the listener * @param port the port used for communications
*/ */
void onGuestSystemListener(char data, unsigned port); void onGuestSystem(char data, unsigned port);
/** /**
* (Conditional) Jump-instruction handler. * (Conditional) Jump-instruction handler.
* @param flagTriggered \c true if the jump was triggered due to a * @param flagTriggered \c true if the jump was triggered due to a
* specific FLAG (zero/carry/sign/overflow/parity flag) * specific FLAG (zero/carry/sign/overflow/parity flag)
* @param opcode the opcode of the conrecete jump instruction * @param opcode the opcode of the conrecete jump instruction
*/ */
void onJumpListener(bool flagTriggered, unsigned opcode); void onJump(bool flagTriggered, unsigned opcode);
/* ******************************************************************** /* ********************************************************************
* Simulator Controller & Access API: * Simulator Controller & Access API:
* ********************************************************************/ * ********************************************************************/

6
src/core/sal/bochs/BochsController.cc
View File

@ -117,11 +117,11 @@ void BochsController::onInstrPtrChanged(address_t instrPtr, address_t address_sp
} }
if (do_fire) if (do_fire)
m_LstList.triggerActiveListeners(); m_LstList.triggerActiveListeners();
// Note: SimulatorController::onBreakpointListener will not be invoked in this // Note: SimulatorController::onBreakpoint will not be invoked in this
// implementation. // implementation.
} }
void BochsController::onIOPortListener(unsigned char data, unsigned port, bool out) { void BochsController::onIOPort(unsigned char data, unsigned port, bool out) {
// Check for active breakpoint-events: // Check for active breakpoint-events:
io_cache_t &buffer_cache = m_LstList.getIOBuffer(); io_cache_t &buffer_cache = m_LstList.getIOBuffer();
io_cache_t::iterator it = buffer_cache.begin(); io_cache_t::iterator it = buffer_cache.begin();
@ -137,7 +137,7 @@ void BochsController::onIOPortListener(unsigned char data, unsigned port, bool o
it++; it++;
} }
m_LstList.triggerActiveListeners(); m_LstList.triggerActiveListeners();
// Note: SimulatorController::onBreakpointListener will not be invoked in this // Note: SimulatorController::onBreakpoint will not be invoked in this
// implementation. // implementation.
} }

2
src/core/sal/bochs/BochsController.hpp
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@ -57,7 +57,7 @@ public:
* @param port the port it was transmitted on * @param port the port it was transmitted on
* @param out true if the I/O traffic has been outbound, false otherwise * @param out true if the I/O traffic has been outbound, false otherwise
*/ */
void onIOPortListener(unsigned char data, unsigned port, bool out); void onIOPort(unsigned char data, unsigned port, bool out);
/** /**
* Static internal handler for TimerListeners. This static function is * Static internal handler for TimerListeners. This static function is
* called when a previously registered (Bochs) timer triggers. This function * called when a previously registered (Bochs) timer triggers. This function

2
src/core/sal/bochs/GuestSysCom.ah
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@ -24,7 +24,7 @@ aspect GuestSysCom {
unsigned rDX = getCPU(tjp->that())->gen_reg[2].word.rx; // port number unsigned rDX = getCPU(tjp->that())->gen_reg[2].word.rx; // port number
unsigned rAL = getCPU(tjp->that())->gen_reg[0].word.byte.rl; // data unsigned rAL = getCPU(tjp->that())->gen_reg[0].word.byte.rl; // data
if (rDX == BOCHS_COM_PORT) if (rDX == BOCHS_COM_PORT)
fail::simulator.onGuestSystemListener((char)rAL, rDX); fail::simulator.onGuestSystem((char)rAL, rDX);
} }
}; };

4
src/core/sal/bochs/IOPortCom.ah
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@ -21,7 +21,7 @@ aspect IOPortCom {
{ {
unsigned rDX = getCPU(tjp->that())->gen_reg[2].word.rx; // port number unsigned rDX = getCPU(tjp->that())->gen_reg[2].word.rx; // port number
unsigned char rAL = getCPU(tjp->that())->gen_reg[0].word.byte.rl; // data unsigned char rAL = getCPU(tjp->that())->gen_reg[0].word.byte.rl; // data
fail::simulator.onIOPortListener(rAL, rDX, true); fail::simulator.onIOPort(rAL, rDX, true);
} }
pointcut inInstruction() = "% ...::bx_cpu_c::IN_ALDX(...)"; pointcut inInstruction() = "% ...::bx_cpu_c::IN_ALDX(...)";
@ -30,7 +30,7 @@ aspect IOPortCom {
{ {
unsigned rDX = getCPU(tjp->that())->gen_reg[2].word.rx; // port number unsigned rDX = getCPU(tjp->that())->gen_reg[2].word.rx; // port number
unsigned char rAL = getCPU(tjp->that())->gen_reg[0].word.byte.rl; // data unsigned char rAL = getCPU(tjp->that())->gen_reg[0].word.byte.rl; // data
fail::simulator.onIOPortListener(rAL, rDX, false); fail::simulator.onIOPort(rAL, rDX, false);
} }
}; };

4
src/core/sal/bochs/Interrupt.ah
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@ -28,9 +28,9 @@ aspect Interrupt {
unsigned vector = *(tjp->arg<0>()); unsigned vector = *(tjp->arg<0>());
unsigned type = *(tjp->arg<1>()); unsigned type = *(tjp->arg<1>());
if (type == BX_EXTERNAL_INTERRUPT) if (type == BX_EXTERNAL_INTERRUPT)
fail::simulator.onInterruptListener(vector, false); fail::simulator.onInterrupt(vector, false);
else if (type == BX_NMI) else if (type == BX_NMI)
fail::simulator.onInterruptListener(vector, true); fail::simulator.onInterrupt(vector, true);
} }
}; };

4
src/core/sal/bochs/Jump.ah
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@ -60,7 +60,7 @@ aspect Jump {
advice execution (defJumpInstructions()) : around() advice execution (defJumpInstructions()) : around()
{ {
bxInstruction_c* pInstr = *(tjp->arg<0>()); // bxInstruction_c-object bxInstruction_c* pInstr = *(tjp->arg<0>()); // bxInstruction_c-object
fail::simulator.onJumpListener(true, pInstr->getIaOpcode()); fail::simulator.onJump(true, pInstr->getIaOpcode());
/* /*
JoinPoint::That* pThis = tjp->that(); JoinPoint::That* pThis = tjp->that();
if(pThis == NULL) if(pThis == NULL)
@ -109,7 +109,7 @@ aspect Jump {
advice execution (regJumpInstructions()) : around () advice execution (regJumpInstructions()) : around ()
{ {
bxInstruction_c* pInstr = *(tjp->arg<0>()); // bxInstruction_c-object bxInstruction_c* pInstr = *(tjp->arg<0>()); // bxInstruction_c-object
fail::simulator.onJumpListener(false, pInstr->getIaOpcode()); fail::simulator.onJump(false, pInstr->getIaOpcode());
/* /*
JoinPoint::That* pThis = tjp->that(); JoinPoint::That* pThis = tjp->that();

18
src/core/sal/bochs/MemAccess.ah
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@ -61,14 +61,14 @@ aspect MemAccess {
#ifdef CONFIG_EVENT_MEMWRITE #ifdef CONFIG_EVENT_MEMWRITE
advice execution (write_methods()) : after () advice execution (write_methods()) : after ()
{ {
fail::simulator.onMemoryAccessListener( fail::simulator.onMemoryAccess(
*(tjp->arg<1>()), sizeof(*(tjp->arg<2>())), true, *(tjp->arg<1>()), sizeof(*(tjp->arg<2>())), true,
getCPU(tjp->that())->prev_rip); getCPU(tjp->that())->prev_rip);
} }
advice execution (write_methods_RMW()) : after () advice execution (write_methods_RMW()) : after ()
{ {
fail::simulator.onMemoryAccessListener( fail::simulator.onMemoryAccess(
rmw_address, sizeof(*(tjp->arg<0>())), true, rmw_address, sizeof(*(tjp->arg<0>())), true,
getCPU(tjp->that())->prev_rip); getCPU(tjp->that())->prev_rip);
} }
@ -77,7 +77,7 @@ aspect MemAccess {
{ {
std::cerr << "WOOOOOT write_methods_new_stack" << std::endl; std::cerr << "WOOOOOT write_methods_new_stack" << std::endl;
// TODO: Log-level? // TODO: Log-level?
fail::simulator.onMemoryAccessListener( fail::simulator.onMemoryAccess(
*(tjp->arg<1>()), sizeof(*(tjp->arg<3>())), true, *(tjp->arg<1>()), sizeof(*(tjp->arg<3>())), true,
getCPU(tjp->that())->prev_rip); getCPU(tjp->that())->prev_rip);
} }
@ -86,7 +86,7 @@ aspect MemAccess {
{ {
std::cerr << "WOOOOOT write_methods_new_stack_64" << std::endl; std::cerr << "WOOOOOT write_methods_new_stack_64" << std::endl;
// TODO: Log-level? // TODO: Log-level?
fail::simulator.onMemoryAccessListener( fail::simulator.onMemoryAccess(
*(tjp->arg<0>()), sizeof(*(tjp->arg<2>())), true, *(tjp->arg<0>()), sizeof(*(tjp->arg<2>())), true,
getCPU(tjp->that())->prev_rip); getCPU(tjp->that())->prev_rip);
} }
@ -98,7 +98,7 @@ aspect MemAccess {
// memory (e.g., to read vectors from the interrupt vector // memory (e.g., to read vectors from the interrupt vector
// table). // table).
/* /*
fail::simulator.onMemoryAccessListener( fail::simulator.onMemoryAccess(
*(tjp->arg<0>()), sizeof(*(tjp->arg<1>())), true, *(tjp->arg<0>()), sizeof(*(tjp->arg<1>())), true,
getCPU(tjp->that())->prev_rip); getCPU(tjp->that())->prev_rip);
*/ */
@ -114,14 +114,14 @@ aspect MemAccess {
#ifdef CONFIG_EVENT_MEMREAD #ifdef CONFIG_EVENT_MEMREAD
advice execution (read_methods()) : before () advice execution (read_methods()) : before ()
{ {
fail::simulator.onMemoryAccessListener( fail::simulator.onMemoryAccess(
*(tjp->arg<1>()), sizeof(*(tjp->result())), false, *(tjp->arg<1>()), sizeof(*(tjp->result())), false,
getCPU(tjp->that())->prev_rip); getCPU(tjp->that())->prev_rip);
} }
advice execution (read_methods_dqword()) : before () advice execution (read_methods_dqword()) : before ()
{ {
fail::simulator.onMemoryAccessListener( fail::simulator.onMemoryAccess(
*(tjp->arg<1>()), 16, false, *(tjp->arg<1>()), 16, false,
getCPU(tjp->that())->prev_rip); getCPU(tjp->that())->prev_rip);
} }
@ -131,7 +131,7 @@ aspect MemAccess {
{ {
rmw_address = *(tjp->arg<1>()); rmw_address = *(tjp->arg<1>());
#ifdef CONFIG_EVENT_MEMREAD #ifdef CONFIG_EVENT_MEMREAD
fail::simulator.onMemoryAccessListener( fail::simulator.onMemoryAccess(
*(tjp->arg<1>()), sizeof(*(tjp->result())), false, *(tjp->arg<1>()), sizeof(*(tjp->result())), false,
getCPU(tjp->that())->prev_rip); getCPU(tjp->that())->prev_rip);
#endif #endif
@ -145,7 +145,7 @@ aspect MemAccess {
// memory (e.g., to read vectors from the interrupt vector // memory (e.g., to read vectors from the interrupt vector
// table). // table).
/* /*
fail::simulator.onMemoryAccessListener( fail::simulator.onMemoryAccess(
*(tjp->arg<0>()), sizeof(*(tjp->result())), false, *(tjp->arg<0>()), sizeof(*(tjp->result())), false,
getCPU(tjp->that())->prev_rip); getCPU(tjp->that())->prev_rip);
*/ */

2
src/core/sal/bochs/Trap.ah
View File

@ -15,7 +15,7 @@ aspect Trap {
advice execution (exception_method()) : before () advice execution (exception_method()) : before ()
{ {
fail::simulator.onTrapListener(*(tjp->arg<0>())); fail::simulator.onTrap(*(tjp->arg<0>()));
// TODO: There are some different types of exceptions at cpu.h (line 265-281) // TODO: There are some different types of exceptions at cpu.h (line 265-281)
// Which kind of traps are these types? // Which kind of traps are these types?
} }