diff --git a/doc/how-to-build.txt b/doc/how-to-build.txt index 31fdcda4..d1005835 100644 --- a/doc/how-to-build.txt +++ b/doc/how-to-build.txt @@ -213,15 +213,18 @@ Building gem5: Fail* configuration: ------------------------------------------------------------ - BUILD_GEM5 ON + - BUILD_ARM ON - all configuration options specific for other simulators OFF - - COMPILER: gcc (not ag++) + - Release or Debug choice must match gem5 in the following For the first time: ------------------------------------------------------------ 1. Change to the gem5 simulator directory (expects to be in ${FAIL_DIR}): $ cd simulators/gem5 - 2. Get the gem5 sourcecode from the stable repository (Mercurial needed) - $ hg clone http://repo.gem5.org/gem5-stable ./ + 2. Build gem5 using the commands below until it fails finding the fail-libs + 3. Build fail + 4. Select an experiment (see below) + 5. Build gem5 again. THe fail-libs should be found now. Optimized build: ------------------------------------------------------------ @@ -234,3 +237,11 @@ Debug build: $ cd ../simulator/gem5 $ scons EXTRAS=../../src/core/sal/gem5 build/ARM/gem5.debug (add -jN for a parallel build) + +Selecting an experiment: +------------------------------------------------------------ + 1. Edit ../src/core/sal/gem5/SConscript + In line starting with (gStaticLibs = ...) change -lfail-arch-test to + -lfail-EXPERIMENTNAME + + diff --git a/doc/how-to-use.txt b/doc/how-to-use.txt index 133958e1..7b85ae44 100644 --- a/doc/how-to-use.txt +++ b/doc/how-to-use.txt @@ -175,3 +175,13 @@ Some useful things to note: overflow the server with requests. You may need to bundle parameters for more than one experiment if a single experiment only takes a few hundred milliseconds. (See existing experiments for examples.) + +========================================================================================= +Steps to run an experiment with gem5: +========================================================================================= + 1. Create a directory which will be used as gem5 system directory (which + will contain the guest system and boot image). Further called $SYSTEM. + 2. Create two directories $SYSTEM/binaries and $SYSTEM/disks. + 3. Put guestsystem kernel to $SYSTEM/binaries and boot image to $SYSTEM/disks + 4. Run gem5 with: + $ M5_PATH=$SYSTEM build/ARM/gem5.debug configs/example/fs.py --bare-metal --kernel kernelname diff --git a/simulators/gem5/configs/example/fs_profile.py b/simulators/gem5/configs/example/fs_profile.py new file mode 100644 index 00000000..a414c4d8 --- /dev/null +++ b/simulators/gem5/configs/example/fs_profile.py @@ -0,0 +1,192 @@ +# Copyright (c) 2010-2012 ARM Limited +# All rights reserved. +# +# The license below extends only to copyright in the software and shall +# not be construed as granting a license to any other intellectual +# property including but not limited to intellectual property relating +# to a hardware implementation of the functionality of the software +# licensed hereunder. You may use the software subject to the license +# terms below provided that you ensure that this notice is replicated +# unmodified and in its entirety in all distributions of the software, +# modified or unmodified, in source code or in binary form. +# +# Copyright (c) 2006-2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Ali Saidi + +import optparse +import sys +from datetime import datetime + +import m5 +from m5.defines import buildEnv +from m5.objects import * +from m5.util import addToPath, fatal + +addToPath('../common') + +from FSConfig import * +from SysPaths import * +from Benchmarks import * +import Simulation +import CacheConfig +from Caches import * +import Options + +parser = optparse.OptionParser() +Options.addCommonOptions(parser) +Options.addFSOptions(parser) + +(options, args) = parser.parse_args() + +if args: + print "Error: script doesn't take any positional arguments" + sys.exit(1) + +# driver system CPU is always simple... note this is an assignment of +# a class, not an instance. +DriveCPUClass = AtomicSimpleCPU +drive_mem_mode = 'atomic' + +# system under test can be any CPU +(TestCPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options) + +TestCPUClass.clock = '2GHz' +DriveCPUClass.clock = '2GHz' + +if options.benchmark: + try: + bm = Benchmarks[options.benchmark] + except KeyError: + print "Error benchmark %s has not been defined." % options.benchmark + print "Valid benchmarks are: %s" % DefinedBenchmarks + sys.exit(1) +else: + if options.dual: + bm = [SysConfig(disk=options.disk_image, mem=options.mem_size), SysConfig(disk=options.disk_image, mem=options.mem_size)] + else: + bm = [SysConfig(disk=options.disk_image, mem=options.mem_size)] + +np = options.num_cpus + +if buildEnv['TARGET_ISA'] == "alpha": + test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0]) +elif buildEnv['TARGET_ISA'] == "mips": + test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0]) +elif buildEnv['TARGET_ISA'] == "sparc": + test_sys = makeSparcSystem(test_mem_mode, bm[0]) +elif buildEnv['TARGET_ISA'] == "x86": + test_sys = makeLinuxX86System(test_mem_mode, options.num_cpus, bm[0]) +elif buildEnv['TARGET_ISA'] == "arm": + test_sys = makeArmSystem(test_mem_mode, + options.machine_type, bm[0], + bare_metal=options.bare_metal) +else: + fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA']) + +if options.kernel is not None: + test_sys.kernel = binary(options.kernel) + +if options.script is not None: + test_sys.readfile = options.script + +test_sys.init_param = options.init_param + +test_sys.cpu = [TestCPUClass(cpu_id=i) for i in xrange(np)] + +if bm[0]: + mem_size = bm[0].mem() +else: + mem_size = SysConfig().mem() +if options.caches or options.l2cache: + test_sys.iocache = IOCache(addr_ranges=[test_sys.physmem.range]) + test_sys.iocache.cpu_side = test_sys.iobus.master + test_sys.iocache.mem_side = test_sys.membus.slave +else: + test_sys.iobridge = Bridge(delay='50ns', nack_delay='4ns', + ranges = [test_sys.physmem.range]) + test_sys.iobridge.slave = test_sys.iobus.master + test_sys.iobridge.master = test_sys.membus.slave + +# Sanity check +if options.fastmem and (options.caches or options.l2cache): + fatal("You cannot use fastmem in combination with caches!") + +for i in xrange(np): + if options.fastmem: + test_sys.cpu[i].fastmem = True + if options.checker: + test_sys.cpu[i].addCheckerCpu() + +CacheConfig.config_cache(options, test_sys) + +if len(bm) == 2: + if buildEnv['TARGET_ISA'] == 'alpha': + drive_sys = makeLinuxAlphaSystem(drive_mem_mode, bm[1]) + elif buildEnv['TARGET_ISA'] == 'mips': + drive_sys = makeLinuxMipsSystem(drive_mem_mode, bm[1]) + elif buildEnv['TARGET_ISA'] == 'sparc': + drive_sys = makeSparcSystem(drive_mem_mode, bm[1]) + elif buildEnv['TARGET_ISA'] == 'x86': + drive_sys = makeX86System(drive_mem_mode, np, bm[1]) + elif buildEnv['TARGET_ISA'] == 'arm': + drive_sys = makeArmSystem(drive_mem_mode, options.machine_type, bm[1]) + + drive_sys.cpu = DriveCPUClass(cpu_id=0) + drive_sys.cpu.createInterruptController() + drive_sys.cpu.connectAllPorts(drive_sys.membus) + if options.fastmem: + drive_sys.cpu.fastmem = True + if options.kernel is not None: + drive_sys.kernel = binary(options.kernel) + drive_sys.iobridge = Bridge(delay='50ns', nack_delay='4ns', + ranges = [drive_sys.physmem.range]) + drive_sys.iobridge.slave = drive_sys.iobus.master + drive_sys.iobridge.master = drive_sys.membus.slave + + drive_sys.init_param = options.init_param + root = makeDualRoot(True, test_sys, drive_sys, options.etherdump) +elif len(bm) == 1: + root = Root(full_system=True, system=test_sys) +else: + print "Error I don't know how to create more than 2 systems." + sys.exit(1) + +if options.timesync: + root.time_sync_enable = True + +if options.frame_capture: + VncServer.frame_capture = True + +options.maxtick = 50000000000 # 100 million instructions + +time_before = datetime.now() +Simulation.setWorkCountOptions(test_sys, options) +Simulation.run(options, root, test_sys, FutureClass) +time_after = datetime.now() +diff = time_after - time_before +print(diff) diff --git a/src/core/sal/gem5/notes.txt b/src/core/sal/gem5/notes.txt new file mode 100644 index 00000000..5920e896 --- /dev/null +++ b/src/core/sal/gem5/notes.txt @@ -0,0 +1,12 @@ +Working: + - Breakpoints + - MemAccess + - Traps (limited to traps that are triggered in the weather-monitor experiment) + +On Breakpoints: + - BPRangeBreakpoints and BPSingleBreakpoints(ANY_ADDRESS) are only working with + range breakpoints enabled. + +On MemAccess: + - MemAccess is only working on the simple cpu models (atomic simple, + timing simple...)