openocd: added opcode parser
Added opcode parser of the F.E.H.L.E.R-project for analysis of memory access in mmu-abort handling, tracing, etc. Change-Id: I5912fa4a4d51ee0501817c43bae05e87ac0e9b90
This commit is contained in:
Lars Rademacher
481
debuggers/openocd/opcode_parser/arm-opcode-data.c
Normal file
481
debuggers/openocd/opcode_parser/arm-opcode-data.c
Normal file
@ -0,0 +1,481 @@
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/*
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* FAME - Fault Aware Micro-hypervisor Environment
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*
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* Author: Andreas Heinig <andreas.heinig@gmx.de>
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*
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* Copyright (C) 2011,2012 Department of Computer Science,
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* Design Automation of Embedded Systems Group
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* Dortmund University of Technology
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*
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* This program is proprietary software: you must not redistribute it.
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* Using this software is only allowed inside the DFG SPP1500 F.E.H.L.E.R project,
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* ls12-www.cs.tu-dortmund.de/daes/forschung/dependable-embedded-real-time-systems
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*
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* The complete license is depicted in the LICENSE file in the top level folder.
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*/
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#include <stdio.h>
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#include "arm-opcode.h"
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#define UNDEF_INSTRUCTION_MASK 0x0FB00000
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#define UNDEF_INSTRUCTION_SIG 0x03000000
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#define MISC_INSTRUCTION_1_MASK 0x0F900010
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#define MISC_INSTRUCTION_1_SIG 0x01000000
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#define MISC_INSTRUCTION_2_MASK 0x0F900090
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#define MISC_INSTRUCTION_2_SIG 0x01000010
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#define MSR_IMM_INSTRUCTION_MASK 0x0FB00000
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#define MSR_IMM_INSTRUCTION_SIG 0x03200000
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#define MUL_OR_EXTRA_LDSTR_INSTRUCTION_MASK 0x0E000090
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#define MUL_OR_EXTRA_LDSTR_INSTRUCTION_SIG 0x00000090
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#define OP_AND 0
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#define OP_EOR 1
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#define OP_SUB 2
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#define OP_RSB 3
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#define OP_ADD 4
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#define OP_ADC 5
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#define OP_SBC 6
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#define OP_RSC 7
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#define OP_TST 8
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#define OP_TEQ 9
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#define OP_CMP 10
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#define OP_CMN 11
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#define OP_ORR 12
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#define OP_MOV 13
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#define OP_BIC 14
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#define OP_MVN 15
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static const char * alu_op_str[16] = {
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"AND",
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"EOR",
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"SUB",
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"RSB",
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"ADD",
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"ADC",
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"SBC",
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"RSC",
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"TST",
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"TEQ",
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"CMP",
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"CMN",
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"ORR",
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"MOV",
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"BIC",
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"MVN"
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};
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int decode_data_processing(arm_instruction_t * op)
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{
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uint32_t inst = op->inst;
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/* possible registers */
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uint32_t rn = (inst >> 16) & 0xF;
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uint32_t rd = (inst >> 12) & 0xF;
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uint32_t rs = (inst >> 8) & 0xF;
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uint32_t rm = (inst) & 0xF;
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/*
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* Undefined instruction ?
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*/
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if((inst & UNDEF_INSTRUCTION_MASK) == UNDEF_INSTRUCTION_SIG)
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{
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OP_PRINTF("Undefined Instruction\n")
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return 0;
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}
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/*
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* Miscellaneous instructions ?
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*/
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if((inst & MISC_INSTRUCTION_1_MASK) == MISC_INSTRUCTION_1_SIG ||
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(inst & MISC_INSTRUCTION_2_MASK) == MISC_INSTRUCTION_2_SIG)
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{
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uint32_t op1 = (inst >> 21) & 3;
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uint32_t op2 = (inst >> 4) & 0xf;
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if(op2 == 0)
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{
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if(op1 & 1)
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{
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OP_PRINTF("MSR\t")
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if(op1 & 2)
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OP_PRINTF("SPSR, ")
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else
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OP_PRINTF("CPSR, ")
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OP_PRINTF("R%d\n", (int)rm)
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arm_op_add_reg_r(op, rm);
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return 0;
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}
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else
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{
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OP_PRINTF("MRS\tR%d, ", (int)rd)
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if(op1 & 2)
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OP_PRINTF("SPSR\n")
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else
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OP_PRINTF("CPSR\n")
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arm_op_add_reg_w(op, rd);
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return 0;
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}
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}
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if(op2 == 1)
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{
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if(op1 == 1)
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{
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OP_PRINTF("BX\tR%d\n", (int)rm)
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arm_op_add_reg_r(op, rm);
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return 0;
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}
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else if(op1 == 3)
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{
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OP_PRINTF("CLZ\tR%d, R%d\n", (int)rd, (int)rm)
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arm_op_add_reg_r(op, rm);
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arm_op_add_reg_w(op, rd);
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return 0;
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}
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else
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{
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printf("\n%d: CANNOT parse %08x\n", __LINE__, (unsigned int)inst);
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return 1;
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}
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}
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if(op2 == 2)
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{
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if(op1 == 1)
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{
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OP_PRINTF("BXJ\tR%d\n", (int)rm)
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arm_op_add_reg_r(op, rm);
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return 0;
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}
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else
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{
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printf("\n%d: CANNOT parse %08x\n", __LINE__, (unsigned int)inst);
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return 1;
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}
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}
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if(op2 == 3)
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{
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if(op1 == 1)
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{
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OP_PRINTF("BLX\tR%d\n", (int)rm)
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arm_op_add_reg_r(op, rm);
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return 0;
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}
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else
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{
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printf("\n%d: CANNOT parse %08x\n", __LINE__, (unsigned int)inst);
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return 1;
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}
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}
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if(op2 == 5)
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{
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arm_op_add_reg_r(op, rm);
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arm_op_add_reg_r(op, rn);
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arm_op_add_reg_w(op, rd);
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switch(op1)
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{
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case 0:
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OP_PRINTF("QADD\tR%d, R%d, R%d\n", (int)rd, (int)rm, (int)rn)
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return 0;
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case 1:
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OP_PRINTF("QSUB\tR%d, R%d, R%d\n", (int)rd, (int)rm, (int)rn)
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return 0;
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case 2:
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OP_PRINTF("QDADD\tR%d, R%d, R%d\n", (int)rd, (int)rm, (int)rn)
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return 0;
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case 3:
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default:
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OP_PRINTF("QDSUB\tR%d, R%d, R%d\n", (int)rd, (int)rm, (int)rn)
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return 0;
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}
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}
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if(op2 == 7)
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{
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if(op1 == 1)
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{
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OP_PRINTF("BKPT\n")
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return 0;
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}
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else
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{
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printf("\n%d: CANNOT parse %08x\n", __LINE__, (unsigned int)inst);
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return 1;
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}
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}
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if((op2 & 9) == 8)
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{
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char x = BIT_IS_SET(5) ? 'T' : 'B';
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char y = BIT_IS_SET(6) ? 'T' : 'B';
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arm_op_add_reg_w(op, rd);
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switch(op1)
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{
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case 0:
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arm_op_add_reg_r(op, rm);
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arm_op_add_reg_r(op, rn);
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arm_op_add_reg_r(op, rs);
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OP_PRINTF("SMLA%c%c\tR%d, R%d, R%d, R%d\n", x, y, (int)rd, (int)rn, (int)rm, (int)rs)
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return 0;
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case 1:
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if(x == 'B')
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{
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arm_op_add_reg_r(op, rm);
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arm_op_add_reg_r(op, rn);
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arm_op_add_reg_r(op, rs);
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OP_PRINTF("SMLAW%c\tR%d, R%d, R%d, R%d\n", y, (int)rd, (int)rm, (int)rs, (int)rn)
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return 0;
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}
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else
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{
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arm_op_add_reg_r(op, rm);
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arm_op_add_reg_r(op, rs);
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OP_PRINTF("SMULW%c\tR%d, R%d, R%d\n", y, (int)rd, (int)rm, (int)rs)
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return 0;
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}
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case 2:
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arm_op_add_reg_r(op, rm);
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arm_op_add_reg_r(op, rn);
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arm_op_add_reg_r(op, rs);
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OP_PRINTF("SMLAL%c%c\tR%d, R%d, R%d, R%d\n", x, y, (int)rd, (int)rn, (int)rm, (int)rs)
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return 0;
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case 3:
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default:
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arm_op_add_reg_r(op, rm);
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arm_op_add_reg_r(op, rs);
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OP_PRINTF("SMLAL%c%c\tR%d, R%d, R%d\n", x, y, (int)rd, (int)rm, (int)rs)
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return 0;
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}
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}
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printf("\n%d: CANNOT parse %08x\n", __LINE__, (unsigned int)inst);
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return 1;
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}
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/*
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* MSR with immediate ?
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*/
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if((inst & MSR_IMM_INSTRUCTION_MASK) == MSR_IMM_INSTRUCTION_SIG)
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{
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OP_PRINTF("MSR\t")
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if(BIT_IS_SET(22))
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OP_PRINTF("SPSR, immediate\n")
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else
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OP_PRINTF("CPSR, immediate\n")
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return 0;
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}
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/*
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* Multiplies or extra stores ?
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*/
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if((inst & MUL_OR_EXTRA_LDSTR_INSTRUCTION_MASK) == MUL_OR_EXTRA_LDSTR_INSTRUCTION_SIG)
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{
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uint32_t op1 = (inst >> 20) & 0x1F;
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uint32_t op2 = (inst >> 5) & 3;
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if(op2 == 0)
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{
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/* Multiply instructions */
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if((op1 & 0x1C) == 0)
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{
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arm_op_add_reg_w(op, rd);
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if(op1 & 2)
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{
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OP_PRINTF("MLA")
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if(op1 & 1)
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OP_PRINTF("S")
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OP_PRINTF("\tR%d, R%d, R%d, R%d\n", (int)rd, (int)rm, (int)rs, (int)rn)
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arm_op_add_reg_w(op, rd);
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arm_op_add_reg_r(op, rm);
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arm_op_add_reg_r(op, rn);
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arm_op_add_reg_r(op, rs);
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return 0;
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}
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else
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{
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OP_PRINTF("MUL")
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if(op1 & 1)
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OP_PRINTF("S")
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OP_PRINTF("\tR%d, R%d, R%d\n", (int)rd, (int)rm, (int)rs)
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arm_op_add_reg_w(op, rd);
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arm_op_add_reg_r(op, rm);
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arm_op_add_reg_r(op, rs);
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return 0;
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}
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}
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if((op1 & 0x1F) == 4)
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{
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OP_PRINTF("UMAAL\tR%d, R%d, R%d, R%d\n", (int)rd, (int)rn, (int)rm, (int)rs)
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arm_op_add_reg_w(op, rd);
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arm_op_add_reg_r(op, rm);
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arm_op_add_reg_r(op, rn);
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arm_op_add_reg_r(op, rs);
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return 0;
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}
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if((op1 & 0x18) == 8)
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{
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if(op1 & 4)
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OP_PRINTF("S")
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else
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OP_PRINTF("U")
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if(op1 & 2)
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OP_PRINTF("MLAL")
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else
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OP_PRINTF("MULL")
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if(op1 & 1)
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OP_PRINTF("S")
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OP_PRINTF("\tR%d, R%d, R%d, R%d\n", (int)rd, (int)rn, (int)rm, (int)rs)
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arm_op_add_reg_w(op, rd);
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arm_op_add_reg_r(op, rm);
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arm_op_add_reg_r(op, rn);
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arm_op_add_reg_r(op, rs);
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return 0;
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}
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/* Load store */
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if((op1 & 0x1B) == 0x10)
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{
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OP_PRINTF("SWP")
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if(op1 & 4)
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{
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OP_PRINTF("B")
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op->mem_size = 1;
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}
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else
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op->mem_size = 4;
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op->mem_addr = op->regs->r[rn];
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op->flags = OP_FLAG_READ | OP_FLAG_WRITE;
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arm_op_add_reg_w(op, rd);
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arm_op_add_reg_r(op, rm);
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arm_op_add_reg_r(op, rn);
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OP_PRINTF("\tR%d, R%d, R%d [Addr: %08x]\n", (int)rd, (int)rm, (int)rn, (unsigned int)op->mem_addr)
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return 0;
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}
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if((op1 & 0x1E) == 0x18)
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{
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op->mem_size = 4;
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op->mem_addr = op->regs->r[rn];
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arm_op_add_reg_w(op, rd);
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arm_op_add_reg_r(op, rn);
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if(op1 & 1)
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{
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OP_PRINTF("LDREX")
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op->flags = OP_FLAG_READ;
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}
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else
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{
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OP_PRINTF("STREX")
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op->flags = OP_FLAG_WRITE;
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}
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OP_PRINTF("\tR%d, R%d [Addr: %08x]\n", (int)rd, (int)rn, (unsigned int)op->mem_addr)
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return 0;
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}
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printf("\n%d: CANNOT parse %08x\n", __LINE__, (unsigned int)inst);
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return 1;
|
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}
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if(op2 == 1)
|
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{
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if(op1 & 1)
|
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{
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OP_PRINTF("LDRH\tR%d, ", (int)rd)
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op->flags = OP_FLAG_READ;
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}
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else
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{
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OP_PRINTF("STRH\tR%d, ", (int)rd)
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op->flags = OP_FLAG_WRITE;
|
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}
|
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op->mem_size = 2;
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arm_op_add_reg_w(op, rd);
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decode_addressing_mode3(op);
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OP_PRINTF("\n")
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return 0;
|
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|
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}
|
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|
||||
if(op2 & 2)
|
||||
{
|
||||
if(op1 & 1)
|
||||
{
|
||||
if(op2 & 1)
|
||||
{
|
||||
op->mem_size = 2;
|
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OP_PRINTF("LDRSH\tR%d, ", (int)rd)
|
||||
}
|
||||
else
|
||||
{
|
||||
op->mem_size = 1;
|
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OP_PRINTF("LDRSB\tR%d, ", (int)rd)
|
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}
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op->flags = OP_FLAG_READ;
|
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arm_op_add_reg_w(op, rd);
|
||||
decode_addressing_mode3(op);
|
||||
OP_PRINTF("\n")
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||||
return 0;
|
||||
}
|
||||
else
|
||||
{
|
||||
if(op2 & 1)
|
||||
{
|
||||
op->mem_size = 8;
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op->flags = OP_FLAG_WRITE;
|
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OP_PRINTF("STRD\tR%d:%d, ",(int) rd, (int)rd + 1)
|
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}
|
||||
else
|
||||
{
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op->mem_size = 8;
|
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op->flags = OP_FLAG_READ;
|
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OP_PRINTF("LDRD\tR%d:%d, ", (int)rd, (int)rd + 1)
|
||||
}
|
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arm_op_add_reg_w(op, rd);
|
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arm_op_add_reg_w(op, rd + 1);
|
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decode_addressing_mode3(op);
|
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OP_PRINTF("\n")
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
printf("\n%d: CANNOT parse %08x\n", __LINE__, (unsigned int)inst);
|
||||
return 1;
|
||||
}
|
||||
|
||||
/*
|
||||
* The other possible instructions are ALU ?
|
||||
*/
|
||||
|
||||
/* ALU opcode */
|
||||
uint32_t opcode = (inst >> 21) & 0xF;
|
||||
|
||||
|
||||
OP_PRINTF("%s", alu_op_str[opcode])
|
||||
if(ALU_S_SET)
|
||||
OP_PRINTF("S")
|
||||
|
||||
/* possibly normal ALU instructions */
|
||||
if(opcode == OP_MOV || opcode == OP_MVN)
|
||||
{
|
||||
OP_PRINTF("\tR%d, ", (int)rd)
|
||||
arm_op_add_reg_w(op, rd);
|
||||
}
|
||||
else if(opcode == OP_CMP || opcode == OP_CMN || opcode == OP_TST || opcode == OP_TEQ)
|
||||
{
|
||||
OP_PRINTF("\tR%d, ", (int)rn)
|
||||
arm_op_add_reg_r(op, rn);
|
||||
}
|
||||
else
|
||||
{
|
||||
OP_PRINTF("\tR%d, R%d, ", (int)rd, (int)rn)
|
||||
arm_op_add_reg_w(op, rd);
|
||||
arm_op_add_reg_r(op, rn);
|
||||
}
|
||||
|
||||
decode_addressing_mode1(op);
|
||||
OP_PRINTF("\n")
|
||||
return 0;
|
||||
}
|
||||
Reference in New Issue
Block a user