From c03f42db446e5fe16a391abc3b9beca4a4660a87 Mon Sep 17 00:00:00 2001
From: Lars Rademacher <lars.rademacher@udo.edu>
Date: Mon, 21 Oct 2013 01:51:41 +0200
Subject: [PATCH] openocd: config fix

In the OpenOCD config file for omap4460 an old definition of
Cortex-A9 CPUs was used. Without this fix, OpenOCD would not
start up.

Additionally this commit reduces the number of available Cortex-M
debug targets to one for the sake of simplicity.

Change-Id: Ic690bebd3d171ac0773bb0f1a8087ac96127fb6e
---
 debuggers/openocd/tcl/target/omap4460.cfg | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/debuggers/openocd/tcl/target/omap4460.cfg b/debuggers/openocd/tcl/target/omap4460.cfg
index 9c40e62d..25bb44b9 100644
--- a/debuggers/openocd/tcl/target/omap4460.cfg
+++ b/debuggers/openocd/tcl/target/omap4460.cfg
@@ -37,10 +37,10 @@ if { [info exists M3_DAP_TAPID] } {
 	set _M3_DAP_TAPID 0x4BA00477
 }
 
-jtag newtap $_CHIPNAME m31_dap -irlen 4 -ircapture 0x1 -irmask 0xf \
-	-expected-id $_M3_DAP_TAPID -disable
-jtag configure $_CHIPNAME.m31_dap -event tap-enable \
-	"icepick_c_tapenable $_CHIPNAME.jrc 5"
+#jtag newtap $_CHIPNAME m31_dap -irlen 4 -ircapture 0x1 -irmask 0xf \
+#	-expected-id $_M3_DAP_TAPID -disable
+#jtag configure $_CHIPNAME.m31_dap -event tap-enable \
+#	"icepick_c_tapenable $_CHIPNAME.jrc 5"
 
 jtag newtap $_CHIPNAME m30_dap -irlen 4 -ircapture 0x1 -irmask 0xf \
 	-expected-id $_M3_DAP_TAPID -disable
@@ -94,7 +94,7 @@ set _coreid 0
 set _dbgbase [expr 0x80000000 | ($_coreid << 13)]
 echo "Using dbgbase = [format 0x%x $_dbgbase]"
 
-target create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.dap \
+target create $_TARGETNAME cortex_a8 -chain-position $_CHIPNAME.dap \
   -coreid 0 -dbgbase $_dbgbase
 
 # SRAM: 56KiB at 0x4030.0000
@@ -105,14 +105,14 @@ $_TARGETNAME configure -work-area-phys 0x40300000 -work-area-size 0x1000
 # M3 targets, separate TAP/DAP for each core
 #
 target create $_CHIPNAME.m30 cortex_m -chain-position $_CHIPNAME.m30_dap
-target create $_CHIPNAME.m31 cortex_m -chain-position $_CHIPNAME.m31_dap
+#target create $_CHIPNAME.m31 cortex_m -chain-position $_CHIPNAME.m31_dap
 
 
 # Once the JRC is up, enable our TAPs
 jtag configure $_CHIPNAME.jrc -event setup "
 	jtag tapenable $_CHIPNAME.dap
 	jtag tapenable $_CHIPNAME.m30_dap
-	jtag tapenable $_CHIPNAME.m31_dap
+#	jtag tapenable $_CHIPNAME.m31_dap
 "
 
 # Assume SRST is unavailable (e.g. TI-14 JTAG), so we must assert reset
@@ -120,7 +120,7 @@ jtag configure $_CHIPNAME.jrc -event setup "
 set PRM_RSTCTRL 0x4A307B00
 $_TARGETNAME configure -event reset-assert "$_TARGETNAME mww phys $PRM_RSTCTRL 0x1"
 $_CHIPNAME.m30 configure -event reset-assert { }
-$_CHIPNAME.m31 configure -event reset-assert { }
+#$_CHIPNAME.m31 configure -event reset-assert { }
 
 # Soft breakpoints don't currently work due to broken cache handling
 gdb_breakpoint_override hard