Starting support for Lauterbach T32 HW Debugger

git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1740 8c4709b5-6ec9-48aa-a5cd-a96041d1645a

src/core/config/VariantConfig.hpp.in

@@ -5,5 +5,6 @@
 #cmakedefine BUILD_GEM5
 #cmakedefine BUILD_OVP
 #cmakedefine BUILD_QEMU
+#cmakedefine BUILD_T32
 
 #endif // __VARIANT_CONFIG_HPP__

src/core/sal/CMakeLists.txt

@@ -41,6 +41,17 @@ elseif(BUILD_QEMU)
 		qemu/QEMUController.cc
 		qemu/wrappers.cc
 	)
+elseif(BUILD_T32)
+	set(SRCS
+		Listener.cc
+		ListenerManager.cc
+		SALConfig.cc
+		Register.cc
+		perf/BreakpointBuffer.cc
+		SimulatorController.cc
+		t32/T32Controller.cc
+		t32/wrappers.cc
+	)
 endif(BUILD_BOCHS)
 
 add_library(fail-sal ${SRCS})

src/core/sal/SALConfig.cc

@@ -5,7 +5,8 @@ namespace fail {
 // Flag initialization depends on the current selected simulator
 // (For now, the initialization values are all the same):
 #if defined BUILD_BOCHS || defined BUILD_GEM5 || \
-    defined BUILD_OVP   || defined BUILD_QEMU
+    defined BUILD_OVP   || defined BUILD_QEMU || \
+    defined BUILD_T32
 const address_t       ADDR_INV = static_cast<address_t>  (0);
 const address_t       ANY_ADDR = static_cast<address_t> (-1);
 const unsigned       ANY_INSTR = static_cast<unsigned>  (-1);

src/core/sal/SALConfig.hpp

@@ -14,6 +14,8 @@
   #include "ovp/OVPConfig.hpp"
 #elif defined BUILD_QEMU
   #include "qemu/QEMUConfig.hpp"
+#elif defined BUILD_T32
+  #include "t32/T32Config.hpp"
 #else
   #error SAL Config Target not defined
 #endif

src/core/sal/SALInst.hpp

@@ -36,6 +36,15 @@ namespace fail {
 typedef QEMUController ConcreteSimulatorController; //!< concrete simulator (type)
 }
 
+#elif defined BUILD_T32
+
+#include "t32/T32Controller.hpp"
+
+namespace fail {
+typedef T32Controller ConcreteSimulatorController; //!< concrete simulator (type)
+}
+
+
 #else
 #error SAL Instance not defined
 #endif

src/core/sal/t32/T32Config.hpp

@@ -0,0 +1,20 @@
+/**
+ * \brief Type definitions and configuration settings for the
+ * T32 target backend.
+ */
+
+#ifndef __T32_CONFIG_HPP__
+#define __T32_CONFIG_HPP__
+
+struct T32Timer;
+
+namespace fail {
+
+typedef uint32_t guest_address_t; //!< the guest memory address type
+typedef unsigned char* host_address_t;  //!< the host memory address type
+typedef uint32_t register_data_t; //!< register data type (64 bit)
+typedef T32Timer* timer_t;         //!< type of timer IDs
+
+} // end-of-namespace: fail
+
+#endif // __T32_CONFIG_HPP__

src/core/sal/t32/T32Controller.cc

@@ -0,0 +1,24 @@
+#include <sstream>
+
+#include "T32Controller.hpp"
+#include "T32Memory.hpp"
+#include "T32Register.hpp"
+#include "../Register.hpp"
+#include "../SALInst.hpp"
+
+namespace fail {
+
+T32Controller::T32Controller()
+	: SimulatorController(new T32RegisterManager(), new T32MemoryManager())
+{
+	// TODO: probably do additional RegisterManager initializations
+}
+
+T32Controller::~T32Controller()
+{
+	delete m_Regs;
+	delete m_Mem;
+}
+
+
+} // end-of-namespace: fail

src/core/sal/t32/T32Controller.hpp

@@ -0,0 +1,51 @@
+#ifndef __T32_CONTROLLER_HPP__
+	#define __T32_CONTROLLER_HPP__
+
+#include <string>
+#include <cassert>
+#include <iostream>
+#include <iomanip>
+#include <string.h>
+
+#include "../SimulatorController.hpp"
+
+namespace fail {
+
+class ExperimentFlow;
+class TimerListener;
+
+/**
+ * \class T32Controller
+ * Very rudimentary, T32-specific implementation of a SimulatorController.
+ */
+class T32Controller : public SimulatorController {
+public:
+	// Initialize the controller.
+	T32Controller();
+	~T32Controller();
+
+
+	/* ********************************************************************
+	 * Simulator Controller & Access API:
+	 * ********************************************************************/
+	/**
+	 * Save simulator state.  Quite hard on real hardware! Also safe all 
+	 * HW registers!
+	 * @param path Location to store state information
+	 * @return \c true if the state has been successfully saved, \c false otherwise
+	 */
+	bool save(const std::string& path) { return false; }
+	/**
+	 * Restore simulator state. Clears all Listeners.  TODO.
+	 * @param path Location to previously saved state information
+	 */
+	void restore(const std::string& path) {}
+	/**
+	 * Reboot simulator. Clears all Listeners.  TODO.
+	 */
+	void reboot() {}
+};
+
+} // end-of-namespace: fail
+
+#endif // __T32_CONTROLLER_HPP__

src/core/sal/t32/T32Listener.ah

@@ -0,0 +1,35 @@
+#ifndef __T32LISTENER_AH__
+  #define __T32LISTENER_AH__
+
+#include "config/VariantConfig.hpp"
+#include "config/FailConfig.hpp"
+
+#if defined(BUILD_T32) && defined(CONFIG_EVENT_BREAKPOINTS)
+
+#include "../SALInst.hpp"
+
+aspect T32Listener
+
+	advice "fail::MemWriteListener" : slice class
+	{
+	public:
+		bool onAddition()
+		{
+			//std::cout << "T32MemWriteListener::onAddition" << std::endl;
+			//if (failqemu_add_watchpoint(simulator.m_cpuenv, m_WatchAddr, m_WatchWidth, 1) != 0) {
+			//	std::cout << "adding watchpoint failed!" << std::endl;
+				return false;
+			//}
+			//return true;
+		}
+
+		void onDeletion()
+		{
+			//std::cout << "T32MemWriteListener::onDeletion" << std::endl;
+			//failqemu_remove_watchpoint(simulator.m_cpuenv, m_WatchAddr, m_WatchWidth, 1);
+		}
+	};
+};
+
+#endif // BUILD_T32 && CONFIG_EVENT_BREAKPOINTS
+#endif // __T32LISTENER_AH__

src/core/sal/t32/T32Memory.hpp

@@ -0,0 +1,41 @@
+#ifndef __T32_MEMORY_HPP__
+  #define __T32_MEMORY_HPP__
+
+#include "../Memory.hpp"
+
+namespace fail {
+
+/**
+ * \class T32MemoryManager
+ * Represents a concrete implemenation of the abstract
+ * MemoryManager to provide access to T32's memory pool.
+ */
+class T32MemoryManager : public MemoryManager {
+public:
+	size_t getPoolSize() const { return 0; /* TODO */ }
+	host_address_t getStartAddr() const { return 0; }
+	byte_t getByte(guest_address_t addr)
+	{
+		return 0; //failqemu_mem_read_byte(addr);
+	}
+	void getBytes(guest_address_t addr, size_t cnt, void *dest)
+	{
+		char *d = static_cast<char *>(dest);
+		for (size_t i = 0; i < cnt; ++i)
+			d[i] = 0; //getByte(addr + i);
+	}
+	void setByte(guest_address_t addr, byte_t data)
+	{
+		//failqemu_mem_write_byte(addr, data);
+	}
+	void setBytes(guest_address_t addr, size_t cnt, void const *src)
+	{
+		//char const *s = static_cast<char const *>(src);
+		for (size_t i = 0; i < cnt; ++i)
+			; //setByte(addr + i, s[i]);
+	}
+};
+
+} // end-of-namespace: fail
+
+#endif // __T32_MEMORY_HPP__

src/core/sal/t32/T32Register.hpp

@@ -0,0 +1,45 @@
+#ifndef __T32_REGISTER_HPP__
+  #define __T32_REGISTER_HPP__
+
+#include "../Register.hpp"
+
+#include <iostream>
+#include <cassert>
+
+namespace fail {
+
+/**
+ * \class T32Register
+ * T32-specific implementation of ?? registers.  TODO.
+ */
+class T32Register : public Register {
+public:
+	T32Register(unsigned int id, regwidth_t width, regdata_t* link, RegisterType t)
+		: Register(id, t, width) { }
+	regdata_t getData() { return 0; /* TODO */ }
+	void setData(regdata_t data) { /* TODO */ }
+};
+
+/**
+ * \class T32RegisterManager
+ * T32-specific implementation of the RegisterManager.  TODO.
+ */
+class T32RegisterManager : public RegisterManager {
+public:
+	address_t getInstructionPointer()
+	{
+		return static_cast<address_t>(0); /* TODO */
+	}
+	address_t getStackPointer()
+	{
+		return static_cast<address_t>(0); /* TODO */
+	}
+	address_t getBasePointer()
+	{
+		return static_cast<address_t>(0); /* TODO */
+	}
+};
+
+} // end-of-namespace: fail
+
+#endif // __T32_REGISTER_HPP__

src/core/sal/t32/wrappers.cc

@@ -0,0 +1,21 @@
+#include <iostream>
+
+#include "../SALInst.hpp"
+#include "../SALConfig.hpp"
+#include "config/FailConfig.hpp"
+
+extern "C" {
+
+void fail_init(struct CPUX86State *env)
+{
+	std::cout << "FailT32" FAIL_VERSION << std::endl;
+	fail::simulator.startup();
+}
+
+void fail_watchpoint_hit(struct CPUX86State *env, uint64_t addr, int width, int is_write)
+{
+	// FIXME: instruction pointer
+	fail::simulator.onMemoryAccess(addr, width, is_write == 1, 0);
+}
+
+}