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Namespaces unified (sal+fi -> fail), Code cleanups (-> coding-style.txt), Doxygen-comments fixed.

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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1319 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
This commit is contained in:
adrian
2012-06-07 17:47:19 +00:00
parent cdd5379e19
commit b7d904140e
136 changed files with 1487 additions and 1554 deletions
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10
ovp/OVPStatusRegister.hpp
View File

@ -1,5 +1,5 @@
#ifndef __OVPSTATUSREGISTER_HPP__
#define __OVPSTATUSREGISTER_HPP__
#ifndef __OVP_STATUS_REGISTER_HPP__
#define __OVP_STATUS_REGISTER_HPP__
#include "SAL/ovp/OVPRegister.hpp"
@ -7,13 +7,13 @@
* \class OVPStatusRegister
* Abstract class for status register implementation
*/
class OVPStatusRegister : public sal::OVPRegister {
class OVPStatusRegister : public fail::OVPRegister {
protected:
public:
OVPStatusRegister(uint32_t width, void *link)
: sal::OVPRegister(width, 32, link, sal::RT_ST) { }
: fail::OVPRegister(width, 32, link, fail::RT_ST) { }
~OVPStatusRegister() {}
virtual bool getSignFlag() const = 0;
@ -49,4 +49,4 @@ class OVPStatusRegister : public sal::OVPRegister {
}*/
};
#endif
#endif // __OVP_STATUS_REGISTER_HPP__

4
ovp/armmModel/failSALlink.cc
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@ -5,8 +5,8 @@ using namespace std;
void hello(unsigned int p){
cout << "&sal::simulator: " << hex << p << endl;
// sal::SimulatorController * salp = reinterpret_cast<sal::SimulatorController * >(p);
cout << "&fail::simulator: " << hex << p << endl;
// fail::SimulatorController * salp = reinterpret_cast<fail::SimulatorController * >(p);
}

14
ovp/cortexM3/platform/platform.cc
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@ -71,7 +71,7 @@ void ARM_Cortex_M3::init(bool gdb=false) {
attrList->addAttr("compatibility", "nopBKPT");
attrList->addAttr("variant", variant);
attrList->addAttr("UAL", "1");
attrList->addAttr("fail_salp", &sal::simulator);
attrList->addAttr("fail_salp", &fail::simulator);
char cpuname[64];
sprintf(cpuname,"cpu-%s", variant);
@ -146,7 +146,7 @@ static ICM_MEM_READ_FN(extMemRead) {
// icmPrintf("EXTERNAL MEMORY: Reading 0x%08x from 0x%08x\n", *(Int32*)value, (Int32)address);
// *(Int32*) value = (Int32)arm.mem[(address-arm.offset)>>2];
sal::simulator.onMemoryAccessEvent(address, 4, false, ovpplatform.getPC());
fail::simulator.onMemoryAccessEvent(address, 4, false, ovpplatform.getPC());
res[0] = arm.mem[(address-arm.offset)+0];
res[1] = arm.mem[(address-arm.offset)+1];
@ -166,7 +166,7 @@ static ICM_MEM_READ_FN(extMemRead) {
static ICM_MEM_WRITE_FN(extMemWrite) {
// icmPrintf("EXTERNAL MEMORY: Writing 0x%08x to 0x%08x\n", (Int32)value, (Int32)address);
// icmPrintf("Callback: Writing 0x%08x to mem[0x%08x] should be 0x%08x from [0x%08x]\n", *(Int32*)value, (Int32)(address-arm.offset), *(Int32*) value, (Int32) address);
sal::simulator.onMemoryAccessEvent(address, 4, true, ovpplatform.getPC());
fail::simulator.onMemoryAccessEvent(address, 4, true, ovpplatform.getPC());
Int32 val = *(Int32*)value;
@ -266,7 +266,7 @@ void ARM_Cortex_M3::makeGPRegister() {
for(int i = 0; i <= 12; ++i) {
icmRegInfoP reg = icmGetRegByIndex(processorP, i);
sal::simulator.makeGPRegister(32, (void *)reg, names[i]);
fail::simulator.makeGPRegister(32, (void *)reg, names[i]);
}
// set SP pointer
@ -278,13 +278,13 @@ void ARM_Cortex_M3::makeGPRegister() {
void ARM_Cortex_M3::makeSTRegister() {
OVPStatusRegister *streg = new CortexM3StatusRegister();
sal::simulator.makeSTRegister(streg, "sp");
fail::simulator.makeSTRegister(streg, "sp");
}
void ARM_Cortex_M3::makePCRegister() {
// ARM Cortex M3: PC pointer is ID 15
icmRegInfoP pc_reg = icmGetRegByIndex(processorP, 15);
sal::simulator.makePCRegister(32, (void *)pc_reg, "PC");
fail::simulator.makePCRegister(32, (void *)pc_reg, "PC");
}
int ARM_Cortex_M3::startSimulation(const char *app) {
@ -303,7 +303,7 @@ int ARM_Cortex_M3::startSimulation(const char *app) {
// save PC
Addr pc_ptr = cpu->getPC();
sal::simulator.onInstrPtrChanged(pc_ptr);
fail::simulator.onInstrPtrChanged(pc_ptr);
// simulate the platform
icmStopReason stopreason = cpu->simulate(1);

2
ovp/ovpworld.org/mmc/flakyMemory/1.0/model/model.cpp
View File

@ -133,7 +133,7 @@ static VMI_MEM_READ_FN(readNFull)
);
// flipBits(value, bytes, processor, address);
//sal::simulator.onMemoryAccessEvent(address, bytes, false, processor.getPC());
//fail::simulator.onMemoryAccessEvent(address, bytes, false, processor.getPC());
// increment counter of reads and writes:
flaky->count += 1;