another directory rename: failstar -> fail

"failstar" sounds like a name for a cruise liner from the 80s. As "*" isn't a desirable part of directory names, just name the whole thing "fail/", the core parts being stored in "fail/core/". Additionally fixing two build system dependency issues: - missing jobserver -> protomessages dependency - broken bochs -> fail dependency (add_custom_target DEPENDS only allows plain file dependencies ... cmake for the win) git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@956 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-03-08 19:43:02 +00:00
commit b70b6fb43a
921 changed files with 473161 additions and 0 deletions
--- a/core/SAL/CMakeLists.txt
+++ b/core/SAL/CMakeLists.txt
@ -0,0 +1,10 @@
+set(SRCS
+	Memory.cc
+	Register.cc
+	SimulatorController.cc
+	${VARIANT}/Controller.cc
+)
+
+
+add_library(SAL ${SRCS})
+
--- a/core/SAL/Memory.cc
+++ b/core/SAL/Memory.cc
@ -0,0 +1,12 @@
+
+// Author: Adrian Böckenkamp
+// Date:   09.09.2011
+
+#include "Memory.hpp"
+
+#include <cstdlib>
+
+namespace sal
+{
+	const guest_address_t ADDR_INV = NULL;
+}
--- a/core/SAL/Memory.hpp
+++ b/core/SAL/Memory.hpp
@ -0,0 +1,77 @@
+#ifndef __MEMORY_HPP__
+  #define __MEMORY_HPP__
+
+// Author: Adrian Böckenkamp
+// Date:   07.09.2011
+
+#include <vector>
+#include <stdint.h>
+#include <cstring> // Added for size_t support
+
+#include "SALConfig.hpp"
+
+namespace sal
+{
+
+/**
+ * \class MemoryManager
+ * Defines an abstract interface to access the simulated memory pool
+ * and query meta information, e.g. the memory size.
+ */
+class MemoryManager
+{
+	public:
+		virtual ~MemoryManager() { }
+		/**
+		 * Retrieves the size of the available simulated memory.
+		 * @return the size of the memory pool in bytes
+		 */
+		virtual size_t getPoolSize() const = 0;
+		/**
+		 * Retrieves the starting address of the host memory. This is the
+		 * first valid address in memory.
+		 * @return the starting address
+		 */
+		virtual host_address_t getStartAddr() const = 0;
+		/**
+		 * Retrieves the byte at address \a addr in the memory.
+		 * @param addr The guest address where the byte is located.
+		 *        The address is expected to be valid.
+		 * @return the byte at \a addr
+		 */
+		virtual byte_t getByte(guest_address_t addr) = 0;
+		/**
+		 * Retrieves \a cnt bytes at address \a addr in the memory.
+		 * @param addr The guest address where the bytes are located.
+		 *        The address is expected to be valid.
+		 * @param cnt the number of bytes to be retrieved. \a addr + \a cnt
+		 *        is expected to not exceed the memory limit.
+		 * @param dest the destination buffer to write the bytes to
+		 */
+		virtual void getBytes(guest_address_t addr, size_t cnt, std::vector<byte_t>& dest) = 0;
+		/**
+		 * Writes the byte \a data to memory.
+		 * @param addr The guest address to write.
+		 *        The address is expected to be valid.
+		 * @param data The new byte to write
+		 */
+		virtual void setByte(guest_address_t addr, byte_t data) = 0;
+		/**
+		 * Writes the bytes \a data to memory. Consequently data.size() bytes
+		 * will be written.
+		 * @param addr The guest address to write.
+		 *        The address is expected to be valid.
+		 * @param data The new bytes to write
+		 */
+		virtual void setBytes(guest_address_t addr, const std::vector<byte_t>& data) = 0;
+		/**
+		 * Transforms the guest address \a addr to a host address.
+		 * @param addr The guest address to be transformed
+		 * @return the transformed (host) address or \c ADDR_INV on errors
+		 */
+		virtual host_address_t guestToHost(guest_address_t addr) = 0;
+};
+
+} // end-of-namespace: sal
+
+#endif /* __MEMORY_HPP__ */
--- a/core/SAL/Register.cc
+++ b/core/SAL/Register.cc
@ -0,0 +1,72 @@
+
+// Author: Adrian Böckenkamp
+// Date:   07.09.2011
+
+#include "Register.hpp"
+
+namespace sal
+{
+	Register* UniformRegisterSet::getRegister(size_t i)
+	{
+		assert(i < m_Regs.size() && "FATAL ERROR: Invalid index provided!");
+		return (m_Regs[i]);
+	}
+
+	Register* RegisterManager::getRegister(size_t i)
+	{
+		assert(i < m_Registers.size() && "FATAL ERROR: Invalid index provided!");
+		return (m_Registers[i]);
+	}
+	
+	void RegisterManager::add(Register* reg)
+	{
+		assert(!reg->isAssigned() && "FATAL ERROR: The register is already assigned!");
+		m_Registers.push_back(reg);
+
+		UniformRegisterSet* urs = getSetOfType(reg->getType());
+		if(urs == NULL) {
+			urs = new UniformRegisterSet(reg->getType());
+			m_Subsets.push_back(urs);
+		}
+		urs->m_add(reg);
+	}
+	
+	void UniformRegisterSet::m_add(Register* preg)
+	{
+		assert(!preg->m_Assigned &&
+			"FATAL ERROR: The register has already been assigned.");
+		m_Regs.push_back(preg);
+		preg->m_Assigned = true;
+		preg->m_Index = m_Regs.size()-1; // the index within the vector (set)
+	}
+	
+	size_t RegisterManager::count() const
+	{
+		return (m_Registers.size());
+	}
+	
+	UniformRegisterSet& RegisterManager::getSet(size_t i)
+	{
+		assert(i < m_Subsets.size() && "FATAL ERROR: Invalid index provided!");
+		return (*m_Subsets[i]);
+	}
+	
+	UniformRegisterSet* RegisterManager::getSetOfType(RegisterType t)
+	{
+		for(std::vector< UniformRegisterSet* >::iterator it = m_Subsets.begin();
+		    it != m_Subsets.end(); it++)
+		{
+			if((*it)->getType() == t)
+				return (*it);
+		}
+		return (NULL);
+	}
+	
+	void RegisterManager::clear()
+	{
+		for(std::vector< UniformRegisterSet* >::iterator it = m_Subsets.begin();
+		    it != m_Subsets.end(); it++)
+			delete (*it);
+		m_Subsets.clear();
+	}
+}
--- a/core/SAL/Register.hpp
+++ b/core/SAL/Register.hpp
@ -0,0 +1,279 @@
+#ifndef __REGISTER_HPP__
+  #define __REGISTER_HPP__
+
+// Author: Adrian Böckenkamp
+// Date:   06.09.2011
+
+#include <vector>
+#include <cstdlib>
+#include <cassert>
+#include <string>
+#include <stdint.h>
+
+#include "SALConfig.hpp"
+
+namespace sal
+{
+
+/**
+ * \enum RegisterType
+ * Lists the different register types. You need to expand this enumeration
+ * to provide more detailed types for your concrete derived register classes
+ * specific to a simulator.
+ */
+enum RegisterType
+{
+	RT_GP, //!< general purpose
+	RT_PC, //!< program counter / instruction pointer
+	RT_ST  //!< status register
+};
+
+/**
+ * \class Register
+ * Represents the basic generic register class. A set of registers is composed
+ * of classes which had been derived from this class.
+ */
+class Register
+{
+	protected:
+		RegisterType m_Type; //!< the type of this register
+		regwidth_t m_Width; //!< the register width
+		unsigned int m_Id; //!< the unique id of this register
+		//! \c true if register has already been assigned, \c false otherwise
+		bool m_Assigned;
+		//! The index in it's register set if assigned (\c -1 otherwise)
+		size_t m_Index;
+		std::string m_Name; //!< The (optional) name, maybe empty
+		friend class UniformRegisterSet;
+	public:
+		/**
+		 * Creates a new register.
+		 * @param id the unique id of this register (simulator specific)
+		 * @param t the type of the register to be constructed
+		 * @param w the width of the register in bits
+		 */
+		Register(unsigned int id, RegisterType t, regwidth_t w)
+			: m_Type(t), m_Width(w), m_Id(id), m_Assigned(false),
+			  m_Index(static_cast<size_t>(-1)) { }
+		/**
+		 * Returns the (fixed) type of this register.
+		 * @return the type of this register
+		 */
+		RegisterType getType() const { return (m_Type); }
+		/**
+		 * Returns the (fixed) width of this register.
+		 * @return the width in bits
+		 */
+		regwidth_t getWidth() const { return (m_Width); }
+		/**
+		 * Returns the data referenced by this register. In a concrete
+		 * derived class this method has to be defined appropriately.
+		 * @return the current data
+		 */
+		virtual regdata_t getData() /*!const*/ = 0;
+		/**
+		 * Sets new data to be stored in this register.
+		 * @param data the data to be written to the register
+		 */
+		virtual void setData(regdata_t data) = 0;
+		/**
+		 * Sets the (optional) name of this register.
+		 * @param name the textual register name, e.g. "EAX"
+		 */
+		void setName(const std::string& name) { m_Name = name; }
+		/**
+		 * Retrieves the register name.
+		 * @return the name
+		 */
+		const std::string& getName() const { return (m_Name); }
+		/**
+		 * Retrieves the unique index within it's assigned register set.
+		 * If the register has not been assigned, \c (size_t)-1 will be
+		 * returned.
+		 * @return the register index or -1 if not assigned
+		 * @see isAssigned()
+		 */
+		size_t getIndex() const { return (m_Index); }
+		/**
+		 * Checks whether this register has already been assigned. On
+		 * creation the register isn't initially assigned.
+		 * @return \c true if assigned, \c false otherwise
+		 */
+		bool isAssigned() const { return (m_Assigned); }
+		/**
+		 * Returns the unique id of this register.
+		 * @return the unique id
+		 */
+		unsigned int getId() const { return (m_Id); }
+};
+
+/**
+ * \class UniformRegisterSet
+ * Represents a (type-uniform) set of registers, e.g. all general purpose
+ * registers. The granularity of the register type is determined by the
+ * enumeration \c RegisterType. (All registers within this set must be of the
+ * same register type.) The capacity of the set is managed automatically.
+ */
+class UniformRegisterSet
+{
+	private:
+		std::vector< Register* > m_Regs; //!< the unique set of registers
+		RegisterType m_Type; //!< the overall type of this container (set)
+		void m_add(Register* preg);
+		friend class RegisterManager;
+	public:
+		/**
+		 * The iterator of this class used to loop through the list of
+		 * added registers. To retrieve an iterator to the first element, call
+		 * begin(). end() returns the iterator, pointing after the last element.
+		 * (This behaviour equals the STL iterator in C++.)
+		 */
+		typedef std::vector< Register* >::iterator iterator;
+		/**
+		 * Returns an iterator to the beginning of the internal data structure.
+		 * \code
+		 * [1|2| ... |n]
+		 *  ^
+		 * \endcode
+		 */
+		iterator begin() { return (m_Regs.begin()); }
+		/**
+		 * Returns an iterator to the end of the interal data structure.
+		 * \code
+		 * [1|2| ... |n]X
+		 *              ^
+		 * \endcode
+		 */
+		iterator end() { return (m_Regs.end()); }
+		/**
+		 * Constructs a new register set with type \a containerType.
+		 * @param containerType the type of registers which should be stored
+		 *        in this set
+		 */
+		UniformRegisterSet(RegisterType containerType)
+			: m_Type(containerType) { }
+		/**
+		 * Returns the type of this set.
+		 * @return the type
+		 */
+		RegisterType getType() const { return (m_Type); }
+		/**
+		 * Gets the number of registers of this set.
+		 * @return the number of registers
+		 */
+		size_t count() const { return (m_Regs.size()); }
+		/**
+		 * Retrieves the \a i-th register within this set.
+		 * @return a pointer to the \a i-th register; if \a i is invalid, an
+		 *         assertion is thrown
+		 */
+		Register* getRegister(size_t i);
+		/**
+		 * Retrieves the first register within this set (syntactical sugar).
+		 * @return a pointer to the first register (if existing -- otherwise an
+		 *         assertion is thrown)
+		 */
+		virtual Register* first() { return (getRegister(0)); }
+};
+
+/**
+ * \class RegisterManager
+ * Represents a complete set of (inhomogeneous) registers specific to a concrete
+ * architecture, e.g. x86 or ARM.
+ */
+class RegisterManager
+{
+	protected:
+		std::vector< Register* > m_Registers;
+		//!< the managed set of homogeneous sets
+		std::vector< UniformRegisterSet* > m_Subsets;
+	public:
+		/**
+		 * The iterator of this class used to loop through the list of
+		 * added registers. To retrieve an iterator to the first element, call
+		 * begin(). end() returns the iterator, pointing after the last element.
+		 * (This behaviour equals the STL iterator in C++.)
+		 */
+		typedef std::vector< Register* >::iterator iterator;
+		/**
+		 * Returns an iterator to the beginning of the internal data structure.
+		 * \code
+		 * [1|2| ... |n]
+		 *  ^
+		 * \endcode
+		 */
+		iterator begin() { return (m_Registers.begin()); }
+		/**
+		 * Returns an iterator to the end of the interal data structure.
+		 * \code
+		 * [1|2| ... |n]X
+		 *              ^
+		 * \endcode
+		 */
+		iterator end() { return (m_Registers.end()); }
+
+		RegisterManager() { }
+		~RegisterManager() { clear(); }
+		/**
+		 * Retrieves the total number of registers over all homogeneous sets.
+		 * @return the total register count
+		 */
+		virtual size_t count() const;
+		/**
+		 * Retrieves the number of managed homogeneous register sets.
+		 * @return the number of sets
+		 */
+		virtual size_t subsetCount() const { return (m_Subsets.size()); }
+		/**
+		 * Gets the \a i-th register set.
+		 * @param i the index of the set to be returned
+		 * @return a reference to the uniform register set
+		 * @see subsetCount()
+		 */
+		virtual UniformRegisterSet& getSet(size_t i);
+		/**
+		 * Returns the set with register type \a t. The set can be used to
+		 * loop over all registers of type \a t.
+		 * @param t the type to check for
+		 * @return a pointer to the retrieved register set (if found), NULL
+		 *         otherwise
+		 */
+		virtual UniformRegisterSet* getSetOfType(RegisterType t);
+		/**
+		 * Adds a new register to this set. The register object needs to be
+		 * typed (see Register::getType).
+		 * @param reg a pointer to the register object to be added
+		 * @see getType()
+		 */
+		void add(Register* reg);
+		/**
+		 * Retrieves the \a i-th register.
+		 * @return a pointer to the \a i-th register; if \a i is invalid, an
+		 *         assertion is thrown
+		 */
+		Register* getRegister(size_t i);
+		/**
+		 * Removes all registers and sets from the RegisterManager.
+		 */
+		virtual void clear();
+		/**
+		 * Returns the current instruction pointer.
+		 * @return the current eip
+		 */
+		virtual address_t getInstructionPointer() = 0;
+		/**
+		 * Retruns the top address of the stack.
+		 * @return the starting address of the stack
+		 */
+		virtual address_t getStackPointer() = 0;
+		/**
+		 * Retrieves the base ptr (holding the address of the
+		 * current stack frame).
+		 * @return the base pointer
+		 */
+		virtual address_t getBasePointer() = 0;
+};
+
+} // end-of-namespace: sal
+
+#endif /* __REGISTER_HPP__ */
--- a/core/SAL/SALConfig.hpp
+++ b/core/SAL/SALConfig.hpp
@ -0,0 +1,45 @@
+#ifndef __SAL_CONFIG_HPP__
+  #define __SAL_CONFIG_HPP__
+
+
+
+#include <stdint.h>
+#include "../variant_config.h"
+
+#if defined BUILD_BOCHS
+
+#include "bochs/BochsConfig.hpp" // current simulator config
+
+namespace sal
+{
+
+typedef guest_address_t  address_t;   //!< common address type to be used in experiment flows
+typedef uint8_t          byte_t;      //!< 8 bit type for memory access (read or write)
+typedef uint32_t         regwidth_t;  //!< type of register width [bits]
+typedef register_data_t  regdata_t;   //!< type of register data
+
+extern const address_t ADDR_INV; //!< invalid address flag (defined in Memory.cc)
+
+}
+
+#elif defined BUILD_OVP
+
+#include "ovp/OVPConfig.hpp" // current simulator config
+
+namespace sal
+{
+
+typedef guest_address_t  address_t;   //!< common address type to be used in experiment flows
+typedef uint8_t          byte_t;      //!< 8 bit type for memory access (read or write)
+typedef uint32_t         regwidth_t;  //!< type of register width [bits]
+typedef register_data_t  regdata_t;   //!< type of register data
+
+extern const address_t ADDR_INV; //!< invalid address flag (defined in Memory.cc)
+
+}
+#else
+#error SAL Config Target not defined
+#endif
+
+
+#endif // __SAL_CONFIG_HPP__
--- a/core/SAL/SALInst.hpp
+++ b/core/SAL/SALInst.hpp
@ -0,0 +1,35 @@
+#ifndef __SAL_INSTANCE_HPP__
+  #define __SAL_INSTANCE_HPP__
+
+#include "SALConfig.hpp"
+#include "../variant_config.h"
+
+#ifdef BUILD_BOCHS
+
+#include "bochs/BochsController.hpp"
+
+namespace sal
+{
+
+typedef BochsController ConcreteSimulatorController; //!< concrete simulator (type)
+extern ConcreteSimulatorController simulator; //!< the global simulator-controller instance
+
+}
+
+#elif defined BUILD_OVP
+
+#include "ovp/OVPController.hpp"
+
+namespace sal
+{
+
+typedef OVPController ConcreteSimulatorController; //!< concrete simulator (type)
+extern ConcreteSimulatorController simulator; //!< the global simulator-controller instance
+
+}
+
+#else
+#error SAL Instance not defined
+#endif
+
+#endif /* __SAL_INSTANCE_HPP__ */
--- a/core/SAL/SimulatorController.cc
+++ b/core/SAL/SimulatorController.cc
@ -0,0 +1,285 @@
+
+// Author: Adrian Böckenkamp
+// Date:   23.01.2012
+
+#include "SimulatorController.hpp"
+#include "SALInst.hpp"
+#include "../controller/Event.hpp"
+
+namespace sal
+{
+
+// External reference declared in SALInst.hpp
+ConcreteSimulatorController simulator;
+
+fi::EventId SimulatorController::addEvent(fi::BaseEvent* ev)
+{
+	return (m_EvList.add(ev, m_Flows.getCurrent()));
+}
+
+fi::BaseEvent* SimulatorController::waitAny(void)
+{
+	m_Flows.resume();
+	assert(m_EvList.getLastFired() != NULL &&
+		   "FATAL ERROR: getLastFired() expected to be non-NULL!");
+	return (m_EvList.getLastFired());
+}
+
+void SimulatorController::startup()
+{
+	// Some greetings to the user:
+	std::cout << "[SimulatorController] Initializing..." << std::endl;
+	
+	// TODO: Retrieve ExperimentData from the job-server (*before* each
+	//       experiment-routine gets started)...!
+	
+	// Activate previously added experiments to allow initialization:
+	initExperiments();
+}
+
+void SimulatorController::initExperiments()
+{
+	/* empty. */
+}
+
+void SimulatorController::onBreakpointEvent(address_t instrPtr)
+{
+	assert(false &&
+	"FIXME: SimulatorController::onBreakpointEvent() has not been tested before");
+	
+	// FIXME: Performanz verbessern
+
+	// Loop through all events of type BP*Event:
+	fi::EventList::iterator it = m_EvList.begin();
+	while(it != m_EvList.end())
+	{
+		fi::BaseEvent* pev = *it;
+		fi::BPEvent* pbp; fi::BPRangeEvent* pbpr;
+		if((pbp = dynamic_cast<fi::BPEvent*>(pev)) && pbp->isMatching(instrPtr))
+		{
+			pbp->setTriggerInstructionPointer(instrPtr);
+			it = m_EvList.makeActive(it);
+			// "it" has already been set to the next element (by calling
+			// makeActive()):
+			continue; // -> skip iterator increment
+		}
+		else if((pbpr = dynamic_cast<fi::BPRangeEvent*>(pev)) &&
+		        pbpr->isMatching(instrPtr))
+		{
+			pbpr->setTriggerInstructionPointer(instrPtr);
+			it = m_EvList.makeActive(it);
+			continue; // dito
+		}
+		++it;
+	}
+	m_EvList.fireActiveEvents();
+}
+
+void SimulatorController::onMemoryAccessEvent(address_t addr, size_t len,
+                                              bool is_write, address_t instrPtr)
+{
+	// FIXME: Performanz verbessern (falls Iteratorlogik bleibt, wäre
+	//        ein "hasMoreOf(typeid(MemEvents))" denkbar...
+
+	fi::MemAccessEvent::accessType_t accesstype =
+		is_write ? fi::MemAccessEvent::MEM_WRITE
+		         : fi::MemAccessEvent::MEM_READ;
+
+	fi::EventList::iterator it = m_EvList.begin();
+	while(it != m_EvList.end()) // check for active events
+	{
+		fi::BaseEvent* pev = *it;
+		fi::MemAccessEvent* ev = dynamic_cast<fi::MemAccessEvent*>(pev);
+		// Is this a MemAccessEvent? Correct access type?
+		if(!ev || !ev->isMatching(addr, accesstype))
+		{
+			++it;
+			continue; // skip event activation
+		}
+		ev->setTriggerAddress(addr);
+		ev->setTriggerWidth(len);
+		ev->setTriggerInstructionPointer(instrPtr);
+		ev->setTriggerAccessType(accesstype);
+		it = m_EvList.makeActive(it);
+	}
+	m_EvList.fireActiveEvents();
+}
+
+void SimulatorController::onInterruptEvent(unsigned interruptNum, bool nmi)
+{
+	fi::EventList::iterator it = m_EvList.begin();
+	while(it != m_EvList.end()) // check for active events
+	{
+		fi::BaseEvent* pev = *it;
+		fi::InterruptEvent* pie = dynamic_cast<fi::InterruptEvent*>(pev);
+		if(!pie || !pie->isMatching(interruptNum))
+		{
+			++it;
+			continue; // skip event activation
+		}
+		pie->setTriggerNumber(interruptNum);
+		pie->setNMI(nmi);
+		it = m_EvList.makeActive(it);
+	}
+	m_EvList.fireActiveEvents();
+}
+
+bool SimulatorController::isSuppressedInterrupt(unsigned interruptNum)
+{
+	for(size_t i = 0; i < m_SuppressedInterrupts.size(); i++)
+		if(m_SuppressedInterrupts[i] == interruptNum ||
+		   m_SuppressedInterrupts[i] == fi::ANY_INTERRUPT)
+			return (true);
+	return (false);
+}
+
+bool SimulatorController::addSuppressedInterrupt(unsigned interruptNum)
+{
+	// Check if already existing:
+	if(isSuppressedInterrupt(interruptNum))
+		return (false); // already added: nothing to do here
+	m_SuppressedInterrupts.push_back(interruptNum);
+	return (true);
+}
+
+bool SimulatorController::removeSuppressedInterrupt(unsigned interruptNum)
+{
+	for(size_t i = 0; i < m_SuppressedInterrupts.size(); i++)
+	{
+		if(m_SuppressedInterrupts[i] == interruptNum)
+		{
+			m_SuppressedInterrupts.erase(m_SuppressedInterrupts.begin() + i);
+			return (true);
+		}
+	}
+	return (false);
+}
+
+void SimulatorController::onTrapEvent(unsigned trapNum)
+{
+	fi::EventList::iterator it = m_EvList.begin();
+	while(it != m_EvList.end()) // check for active events
+	{
+		fi::BaseEvent* pev = *it;
+		fi::TrapEvent* pte = dynamic_cast<fi::TrapEvent*>(pev);
+		if(!pte || !pte->isMatching(trapNum))
+		{
+			++it;
+			continue; // skip event activation
+		}
+		pte->setTriggerNumber(trapNum);
+		it = m_EvList.makeActive(it);
+	}
+	m_EvList.fireActiveEvents();
+}
+
+void SimulatorController::onGuestSystemEvent(char data, unsigned port)
+{
+	// TODO: Eher ein Entwurf...
+
+	fi::EventList::iterator it = m_EvList.begin();
+	while(it != m_EvList.end()) // check for active events
+	{
+		fi::BaseEvent* pev = *it;
+		fi::GuestEvent* pge = dynamic_cast<fi::GuestEvent*>(pev);
+		if(pge != NULL)
+		{
+			pge->setData(data);
+			pge->setPort(port);
+			it = m_EvList.makeActive(it);
+			continue; // dito.
+		}
+		++it;
+	}
+	m_EvList.fireActiveEvents();
+}
+
+void SimulatorController::onJumpEvent(bool flagTriggered, unsigned opcode)
+{
+	fi::EventList::iterator it = m_EvList.begin();
+	while(it != m_EvList.end()) // check for active events
+	{
+		fi::JumpEvent* pje = dynamic_cast<fi::JumpEvent*>(*it);
+		if(pje != NULL)
+		{
+			pje->setOpcode(opcode);
+			pje->setFlagTriggered(flagTriggered);
+			it = m_EvList.makeActive(it);
+			continue; // dito.
+		}
+		++it;
+	}
+	m_EvList.fireActiveEvents();
+}
+
+void SimulatorController::cleanup(fi::ExperimentFlow* pExp)
+{
+	// remove related events:
+	std::vector<fi::BaseEvent*> evlist;
+	m_EvList.getEventsOf(pExp, evlist);
+	for(size_t i = 0; i < evlist.size(); i++)
+		m_EvList.remove(evlist[i]);
+}
+
+void SimulatorController::addFlow(fi::ExperimentFlow* flow)
+{
+	// Store the (flow,corohandle)-tuple internally and create its coroutine:
+	m_Flows.create(flow);
+	// let it run for the first time
+	m_Flows.toggle(flow);
+}
+
+void SimulatorController::removeFlow(fi::ExperimentFlow* flow)
+{
+	// remove all remaining events of this flow
+	cleanup(flow);
+	// remove coroutine
+	m_Flows.remove(flow);
+}
+
+fi::BaseEvent* SimulatorController::addEventAndWait(fi::BaseEvent* ev)
+{
+	addEvent(ev);
+	return (waitAny());
+}
+
+template <class T>
+T* SimulatorController::getExperimentData()
+{
+	//BEGIN ONLY FOR TESTING------REMOVE--------REMOVE---------REMOVE--------REMOVE-------REMOVE-------
+	//Daten in Struktur schreiben und in Datei speichern
+	ofstream fileWrite;
+	fileWrite.open("test.txt");
+
+	T* faultCovExWrite =  new T();;
+	faultCovExWrite->set_data_name("Testfall 42");
+
+	//Namen setzen
+	faultCovExWrite->set_data_name("Testfall 42");
+	//Instruktionpointer 1
+	faultCovExWrite->set_m_instrptr1(0x4711);
+	//Instruktionpointer 2
+	faultCovExWrite->set_m_instrptr2(0x1122);
+
+	//In ExperimentData verpacken
+	fi::ExperimentData exDaWrite(faultCovExWrite);
+	//Serialisierung ueber Wrapper-Methode in ExperimentData
+	exDaWrite.serialize(&fileWrite);
+
+	//cout << "Ausgabe: " << out << endl;
+
+	fileWrite.close(); 
+	
+	ifstream fileRead;
+	fileRead.open("test.txt");
+	//END ONLY FOR TESTING------REMOVE--------REMOVE---------REMOVE--------REMOVE-------REMOVE-------
+	//TODO: implement server-client communication----------------------------------------------
+	
+	T* concreteExpDat = new T();
+	fi::ExperimentData exDaRead(concreteExpDat);
+	exDaRead.unserialize(&fileRead);
+
+	return (concreteExpDat);
+}
+
+} // end-of-namespace: sal
--- a/core/SAL/SimulatorController.hpp
+++ b/core/SAL/SimulatorController.hpp
@ -0,0 +1,250 @@
+#ifndef __SIMULATOR_CONTROLLER_HPP__
+  #define __SIMULATOR_CONTROLLER_HPP__
+  
+// Author: Adrian Böckenkamp
+// Date:   23.01.2012
+
+#include <iostream>
+#include <string>
+#include <cassert>
+#include <vector>
+
+//<BEGIN ONLY FOR TEST
+#include <fstream>
+//>END ONLY FOR TEST
+
+#include "../controller/Event.hpp"
+#include "../controller/EventList.hpp"
+#include "../controller/CoroutineManager.hpp"
+#include "../controller/ExperimentData.hpp"
+#include "SALConfig.hpp"
+
+using namespace std;
+
+namespace fi {
+class ExperimentFlow;
+}
+
+/// Simulator Abstraction Layer namespace
+namespace sal
+{
+
+// incomplete types suffice here
+class RegisterManager;
+class MemoryManager;
+
+/**
+ * \class SimulatorController
+ *
+ * \brief The abstract interface for controlling simulators and
+ *        accessing experiment data/flows.
+ *
+ * This class manages (1..N) experiments and provides access to the underlying
+ * simulator/debugger system. Experiments can enlist arbritrary events
+ * (Breakpoint, Memory access, Traps, etc.). The SimulatorController then
+ * activates the specific experiment There are further methods to read/write
+ * registers and memory, and control the SUT (save/restore/reset).
+ */
+class SimulatorController
+{
+	protected:
+		fi::EventList m_EvList; //!< storage where events are being buffered
+		fi::CoroutineManager m_Flows; //!< managed experiment flows
+		RegisterManager *m_Regs; //!< access to cpu register
+		MemoryManager *m_Mem; //!< access to memory pool
+		//! list of suppressed interrupts
+		std::vector<unsigned> m_SuppressedInterrupts;
+		friend class fi::EventList; //!< "outsources" the event management
+	public:
+		SimulatorController()
+			: m_Regs(NULL), m_Mem(NULL) { }
+		SimulatorController(RegisterManager* regs, MemoryManager* mem)
+			: m_Regs(regs), m_Mem(mem) { }
+		virtual ~SimulatorController() { }
+		/**
+		 * @brief Global startup function each implementation needs to call
+		 *        on startup
+		 * This static function needs to be invoked once the simulator starts,
+		 * and allows the SimulatorController's member startup() to instantiate
+		 * all needed experiment components.
+		 */
+		virtual void startup();
+		/**
+		 * Experiments need to hook here.
+		 */
+		static void initExperiments();
+		/* ********************************************************************
+		 * Standard Event Handler API (SEH-API):
+		 * ********************************************************************/
+		/**
+		 * Breakpoint event handler. This routine needs to be called in the
+		 * simulator specific backend each time a breakpoint event occurs.
+		 * @param instrPtr the instruction pointer of the breakpoint event
+		 */
+		virtual void onBreakpointEvent(address_t instrPtr);
+		/**
+		 * Memory access event handler (read/write).
+		 * @param addr the accessed memory address
+		 * @param len the length of the accessed memory
+		 * @param is_write \c true if memory is written, \c false if read
+		 * @param instrPtr the address of the instruction causing the memory
+		 *        access
+		 * 
+		 * FIXME: should instrPtr be part of this interface?
+		 */
+		virtual void onMemoryAccessEvent(address_t addr, size_t len,
+										 bool is_write, address_t instrPtr);
+		/**
+		 * Interrupt event handler.
+		 * @param interruptNum the interrupt-type id
+		 * @param nmi nmi-value from guest-system
+		 */
+		virtual void onInterruptEvent(unsigned interruptNum, bool nmi);
+		/**
+		 * Trap event handler.
+		 * @param trapNum the trap-type id
+		 */
+		virtual void onTrapEvent(unsigned trapNum);
+		/**
+		 * Guest system communication handler.
+		 * @param data the "message" from the guest system
+		 * @param port the port of the event
+		 */
+		virtual void onGuestSystemEvent(char data, unsigned port);
+		/**
+		 * (Conditional) Jump-instruction handler.
+		 * @param flagTriggered \c true if the jump was triggered due to a
+		 *        specific FLAG (zero/carry/sign/overflow/parity flag)
+		 * @param opcode the opcode of the conrecete jump instruction
+		 */
+		virtual void onJumpEvent(bool flagTriggered, unsigned opcode);
+		/* ********************************************************************
+		 * Simulator Controller & Access API (SCA-API):
+		 * ********************************************************************/
+		/**
+		 * Save simulator state.
+		 * @param path Location to store state information
+		 */
+		virtual void save(const string& path) = 0;
+		/**
+		 * Restore simulator state.
+		 * @param path Location to previously saved state information
+		 */
+		virtual void restore(const string& path) = 0;
+		/**
+		 * Reboot simulator.
+		 */
+		virtual void reboot() = 0;
+		/**
+		 * Terminate simulator
+		 * @param exCode Individual exit code
+		 */
+		virtual void terminate(int exCode = EXIT_SUCCESS) = 0;
+		/**
+		 * Check whether the interrupt should be suppressed.
+		 * @param interruptNum the interrupt-type id
+		 * @return \c true if the interrupt is suppressed, \c false oterwise
+		 */
+		virtual bool isSuppressedInterrupt(unsigned interruptNum);
+		/**
+		 * Add a Interrupt to the list of suppressed.
+		 * @param interruptNum the interrupt-type id
+		 * @return \c true if sucessfully added, \c false otherwise (already
+		 *         existing)
+		 */
+		virtual bool addSuppressedInterrupt(unsigned interruptNum);
+		/**
+		 * Remove a Interrupt from the list of suppressed.
+		 * @param interruptNum the interrupt-type id
+		 * @return \c true if sucessfully removed, \c false otherwise (not
+		 *         found)
+		 */
+		virtual bool removeSuppressedInterrupt(unsigned interruptNum);
+		/**
+		 * Returns the (constant) initialized register manager.
+		 * @return a reference to the register manager
+		 */
+		RegisterManager& getRegisterManager() { return (*m_Regs); }
+		const RegisterManager& getRegisterManager() const { return (*m_Regs); }
+		/**
+		 * Sets the register manager.
+		 * @param pReg the new register manager (or a concrete derived class of
+		 *        RegisterManager)
+		 */
+		void setRegisterManager(RegisterManager* pReg) { m_Regs = pReg; }
+		/**
+		 * Returns the (constant) initialized memory manager.
+		 * @return a reference to the memory manager
+		 */
+		MemoryManager& getMemoryManager() { return (*m_Mem); }
+		const MemoryManager& getMemoryManager() const { return (*m_Mem); }
+		/**
+		 * Sets the memory manager.
+		 * @param pMem a new concrete memory manager
+		 */
+		void setMemoryManager(MemoryManager* pMem) { m_Mem = pMem; }
+		/* ********************************************************************
+		 * Experiment-Flow & Event Management API (EFEM-API):
+		 * ********************************************************************/
+		/**
+		 * Adds the specified experiment or plugin and creates a coroutine to
+		 * run it in.
+		 * @param flow the experiment flow object to be added
+		 */
+		void addFlow(fi::ExperimentFlow* flow);
+		/**
+		 * Removes the specified experiment or plugin and destroys its coroutine
+		 * and all associated events.
+		 * @param flow the experiment flow object to be removed
+		 */
+		void removeFlow(fi::ExperimentFlow* flow);
+		/**
+		 * Add event ev to the event management. This causes the event to be
+		 * active.
+		 * @param ev the event pointer to be added for the current flow
+		 * @return the id of the event used to identify the object on occurrence
+		 */
+		fi::EventId addEvent(fi::BaseEvent* ev);
+		/**
+		 * Removes the event with the specified id.
+		 * @param ev the pointer of the event-object to be removed; if \a ev is
+		 *        equal to \c NULL all events (for all experiments) will be
+		 *        removed
+		 */
+		void removeEvent(fi::BaseEvent* ev) { m_EvList.remove(ev); }
+		/**
+		 * Removes all previously added events for all experiments. This is
+		 * equal to removeEvent(NULL);
+		 */
+		void clearEvents() { removeEvent(NULL); }
+		/**
+		 * Waits on any events which have been added to the event management. If
+		 * one of those events occour, waitAny() will return the id of that
+		 * event.
+		 * @return the previously occurred event
+		 */
+		fi::BaseEvent* waitAny();
+		/**
+		 * Add event \a ev to the global buffer and wait for it (combines
+		 * \c addEvent() and \c waitAny()).
+		 * @param ev the event pointer to be added
+		 * @return the pointer of the occurred event (it is not guaranteed that
+		 *         this pointer will be equal to ev)
+		 */
+		fi::BaseEvent* addEventAndWait(fi::BaseEvent* ev);
+		/**
+		 * Removes all residual events associated with the specified experiment
+		 * flow \a pExp.
+		 * @param pExp the experiment whose events should be removed
+		 */
+		void cleanup(fi::ExperimentFlow* pExp);
+		/**
+		 * Fetches data for the experiments from the Job-Server. 
+		 * @return the Experiment-Data from the Job-Server.
+		 */
+		template <class T> T* getExperimentData();
+};
+
+} // end-of-namespace: sal
+
+#endif /* __SIMULATOR_CONTROLLER_HPP__ */
--- a/core/SAL/bochs/BochsConfig.hpp
+++ b/core/SAL/bochs/BochsConfig.hpp
@ -0,0 +1,24 @@
+#ifndef __BOCHS_CONFIG_HPP__
+  #define __BOCHS_CONFIG_HPP__
+
+#include "../../../bochs/bochs.h"
+#include "../../../bochs/config.h"
+
+// Type definitions and configuration settings for
+// the Bochs simulator.
+ 
+namespace sal
+{
+
+typedef bx_address guest_address_t; //!< the guest memory address type
+typedef Bit8u*     host_address_t;  //!< the host memory address type
+#if BX_SUPPORT_X86_64
+  typedef Bit64u register_data_t;   //!< register data type (64 bit)
+#else
+  typedef Bit32u register_data_t;   //!< register data type (32 bit)
+#endif
+
+};
+
+#endif /* __BOCHS_CONFIG_HPP__ */
+
--- a/core/SAL/bochs/BochsController.hpp
+++ b/core/SAL/bochs/BochsController.hpp
@ -0,0 +1,106 @@
+#ifndef __BOCHS_CONTROLLER_HPP__
+  #define __BOCHS_CONTROLLER_HPP__
+
+#define DEBUG
+
+#include <string>
+#include <cassert>
+#include <iostream>
+#include <iomanip>
+#include <string.h>
+#include <stdlib.h>
+
+#include "failbochs.hpp"
+
+#include "../SimulatorController.hpp"
+#include "../../controller/Event.hpp"
+
+#include "../../../bochs/bochs.h"
+#include "../../../bochs/cpu/cpu.h"
+#include "../../../bochs/config.h"
+
+using namespace std;
+
+namespace fi { class ExperimentFlow; }
+
+/// Simulator Abstraction Layer namespace
+namespace sal
+{
+	
+/**
+ * \class BochsController
+ * Bochs-specific implementation of a SimulatorController.
+ */
+class BochsController : public SimulatorController
+{
+	private:
+		/**
+		 * stores the current flow for save/restore-operations
+		 */
+		fi::ExperimentFlow* m_CurrFlow;
+	  #ifdef DEBUG
+		unsigned m_Regularity;
+		unsigned m_Counter;
+		std::ostream* m_pDest;
+	  #endif
+	public:
+		// Initialize the controller.
+		BochsController();
+		~BochsController();
+		/* ********************************************************************
+		 * Standard Event Handler API (SEH-API):
+		 * ********************************************************************/
+		/**
+		 * Instruction pointer modification handler. This method is called (from
+		 * the CPULoop aspect) every time when the Bochs-internal IP changes.
+		 * @param instrPtr
+		 */
+		void onInstrPtrChanged(address_t instrPtr);
+		/* ********************************************************************
+		 * Simulator Controller & Access API (SCA-API):
+		 * ********************************************************************/
+		/**
+		 * Save simulator state.
+		 * @param path Location to store state information
+		 */
+		void save(const string& path);
+		/**
+		 * Save finished: Callback from Simulator
+		 */
+		void saveDone();
+		/**
+		 * Restore simulator state. Clears all Events.
+		 * @param path Location to previously saved state information
+		 */
+		void restore(const string& path);
+		/**
+		 * Restore finished: Callback from Simulator
+		 */
+		void restoreDone();
+		/**
+		 * Reboot simulator. Clears all Events.
+		 */
+		void reboot();
+		/**
+		 * Reboot finished: Callback from Simulator
+		 */
+		void rebootDone();
+		/**
+		 * Terminate simulator
+		 * @param exCode Individual exit code
+		 */
+		void terminate(int exCode = EXIT_SUCCESS);
+	  #ifdef DEBUG
+		/**
+		 * Enables instruction pointer debugging output.
+		 * @param regularity the output regularity; 1 to display every
+		 *        instruction pointer, 0 to disable
+		 * @param dest specifies the output destition; defaults to \c std::cout
+		 */
+		void dbgEnableInstrPtrOutput(unsigned regularity, std::ostream* dest = &cout);
+	  #endif
+};
+
+} // end-of-namespace: sal
+
+#endif /* __BOCHS_CONTROLLER_HPP__ */
--- a/core/SAL/bochs/BochsMemory.hpp
+++ b/core/SAL/bochs/BochsMemory.hpp
@ -0,0 +1,115 @@
+#ifndef __BOCHS_MEMORY_HPP__
+  #define __BOCHS_MEMORY_HPP__
+
+#include "../Memory.hpp"
+
+namespace sal
+{
+
+/**
+ * \class BochsMemoryManager
+ * Represents a concrete implemenation of the abstract
+ * MemoryManager to provide access to Bochs' memory pool.
+ */
+class BochsMemoryManager : public MemoryManager
+{
+	public:
+		/**
+		 * Constructs a new MemoryManager object and initializes
+		 * it's attributes appropriately.
+		 */
+		BochsMemoryManager() : MemoryManager() {  }
+		/**
+		 * Retrieves the size of the available simulated memory.
+		 * @return the size of the memory pool in bytes
+		 */
+		size_t getPoolSize() const
+		{
+			return (static_cast<size_t>(BX_MEM(0)->get_memory_len()));
+		}
+		/**
+		 * Retrieves the starting address of the host memory. This is the
+		 * first valid address in memory.
+		 * @return the starting address
+		 */
+		host_address_t getStartAddr() const
+		{
+			return (0);
+		}
+		/**
+		 * Retrieves the byte at address \a addr in the memory.
+		 * @param addr The guest address where the byte is located.
+		 *        The address is expected to be valid.
+		 * @return the byte at \a addr
+		 */
+		byte_t getByte(guest_address_t addr)
+		{
+			host_address_t haddr = guestToHost(addr);
+			assert(haddr != (host_address_t)ADDR_INV && "FATAL ERROR: Invalid guest address provided!");
+			return (static_cast<byte_t>(*reinterpret_cast<Bit8u*>(haddr)));
+		}
+		/**
+		 * Retrieves \a cnt bytes at address \a addr in the memory.
+		 * @param addr The guest address where the bytes are located.
+		 *        The address is expected to be valid.
+		 * @param cnt The number of bytes to be retrieved. \a addr + \a cnt
+		 *        is expected to not exceed the memory limit.
+		 * @param dest The destination buffer to write the bytes to
+		 */
+		void getBytes(guest_address_t addr, size_t cnt, std::vector<byte_t>& dest)
+		{
+			for(size_t i = 0; i < cnt; i++)
+				dest.push_back(getByte(addr+i));
+		}
+		/**
+		 * Writes the byte \a data to memory.
+		 * @param addr The guest address to write.
+		 *        The address is expected to be valid.
+		 * @param data The new byte to write
+		 */
+		void setByte(guest_address_t addr, byte_t data)
+		{
+			host_address_t haddr = guestToHost(addr);
+			assert(haddr != (host_address_t)ADDR_INV &&
+				   "FATAL ERROR: Invalid guest address provided!");
+			*reinterpret_cast<Bit8u*>(haddr) = data;
+		}
+		/**
+		 * Writes the bytes \a data to memory. Consequently \c data.size()
+		 * bytes will be written.
+		 * @param addr The guest address to write.
+		 *        The address is expected to be valid.
+		 * @param data The new bytes to write
+		 */
+		void setBytes(guest_address_t addr, const std::vector<byte_t>& data)
+		{
+			for(size_t i = 0; i < data.size(); i++)
+				setByte(addr+i, data[i]);
+		}
+		/**
+		 * Transforms the guest address \a addr to a host address.
+		 * @param addr The (logical) guest address to be transformed
+		 * @return the transformed (host) address or \c ADDR_INV on errors
+		 */
+		host_address_t guestToHost(guest_address_t addr)
+		{
+			const unsigned SEGMENT_SELECTOR_IDX = 2; // always the code segment
+			const bx_address logicalAddr = static_cast<bx_address>(addr); // offset within the segment
+			// Get the linear address:
+			Bit32u linearAddr = BX_CPU(0)->get_laddr32(SEGMENT_SELECTOR_IDX/*seg*/, logicalAddr/*offset*/);
+			// Map the linear address to the physical address:
+	  		bx_phy_address physicalAddr;
+	  		bx_bool fValid = BX_CPU(0)->dbg_xlate_linear2phy(linearAddr, (bx_phy_address*)&physicalAddr);
+			// Determine the *host* address of the physical address:
+			Bit8u* hostAddr = BX_MEM(0)->getHostMemAddr(BX_CPU(0), physicalAddr, BX_READ);
+			// Now, hostAddr contains the "final" address
+	  		if(!fValid)
+				return ((host_address_t)ADDR_INV); // error
+			else
+				return (reinterpret_cast<host_address_t>(hostAddr)); // okay
+		}
+};
+
+}
+
+#endif
--- a/core/SAL/bochs/BochsRegister.hpp
+++ b/core/SAL/bochs/BochsRegister.hpp
@ -0,0 +1,219 @@
+#ifndef __BOCHS_REGISTER_HPP__
+  #define __BOCHS_REGISTER_HPP__
+
+#include "../Register.hpp"
+
+#include "../../../bochs/bochs.h"
+#include <iostream>
+
+namespace sal {
+
+/**
+ * \class BochsRegister
+ * Bochs-specific implementation of x86 registers.
+ */
+class BochsRegister : public Register
+{
+	protected:
+		regdata_t* m_pData;
+	public:
+		/**
+		 * Constructs a new register object.
+		 * @param id the global unique id
+		 * @param width width of the register (8, 16, 32 or 64 bit should
+		 *        suffice)
+		 * @param link pointer to bochs interal register memory
+		 * @param t type of the register
+		 */
+		BochsRegister(unsigned int id, regwidth_t width, regdata_t* link, RegisterType t)
+			: Register(id, t, width), m_pData(link) { }
+		/**
+		 * Retrieves the data of the register.
+		 * @return the current register data
+		 */
+		regdata_t getData() { return (*m_pData); }
+		/**
+		 * Sets the content of the register.
+		 * @param data the new register data to be written
+		 */
+		virtual void setData(regdata_t data) { *m_pData = data; }
+};
+
+/**
+ *  \class BxGPReg
+ * Bochs-specific implementation of x86 general purpose (GP) registers.
+ */
+class BxGPReg : public BochsRegister
+{
+	public:
+		/**
+		 * Constructs a new general purpose register.
+		 * @param id the global unique id
+		 * @param width width of the register (8, 16, 32 or 64 bit should
+		 *        suffice)
+		 * @param link pointer to bochs interal register memory
+		 */
+		BxGPReg(unsigned int id, regwidth_t width, regdata_t* link)
+			: BochsRegister(id, width, link, RT_GP) { }
+};
+
+/**
+ * \enum GPRegisterId
+ * Symbolic identifier to access Bochs' general purpose register
+ * (within the corresponding GP set), e.g.
+ * \code
+ * // Print %eax register data:
+ * BochsController bc(...);
+ * cout << bc.getRegisterManager().getSetOfType(RT_GP)
+ *           .getRegister(RID_EAX)->getData();
+ * \endcode
+ */
+enum GPRegisterId
+{
+ #if BX_SUPPORT_X86_64 // 64 bit register id's:
+	RID_RAX = 0, RID_RCX, RID_RDX, RID_RBX, RID_RSP, RID_RBP, RID_RSI, RID_RDI,
+	RID_R8, RID_R9, RID_R10, RID_R11, RID_R12, RID_R13, RID_R14, RID_R15,
+ #else // 32 bit register id's:
+	RID_EAX = 0, RID_ECX, RID_EDX, RID_EBX, RID_ESP, RID_EBP, RID_ESI, RID_EDI,
+ #endif
+    RID_LAST_GP_ID
+};
+
+/**
+ * \enum PCRegisterId
+ * Symbolic identifier to access Bochs' program counter register.
+ */
+enum PCRegisterId { RID_PC = RID_LAST_GP_ID, RID_LAST_PC_ID };
+
+/**
+ * \enum FlagsRegisterId
+ * Symbolic identifier to access Bochs' flags register.
+ */
+enum FlagsRegisterId { RID_FLAGS = RID_LAST_PC_ID };
+
+/**
+ *  \class BxPCReg
+ * Bochs-specific implementation of the x86 program counter register.
+ */
+class BxPCReg : public BochsRegister
+{
+	public:
+		/**
+		 * Constructs a new program counter register.
+		 * @param id the global unique id
+		 * @param width width of the register (8, 16, 32 or 64 bit should
+		 *        suffice)
+		 * @param link pointer to bochs internal register memory
+		 */
+		BxPCReg(unsigned int id, regwidth_t width, regdata_t* link)
+			: BochsRegister(id, width, link, RT_PC) { }
+};
+
+/**
+ * \class BxFlagsReg
+ * Bochs-specific implementation of the FLAGS status register.
+ */
+class BxFlagsReg : public BochsRegister
+{
+	public:
+		/**
+		 * Constructs a new FLAGS status register. The refenced FLAGS are
+		 * allocated as follows:
+		 * --------------------------------------------------
+	     * 31|30|29|28| 27|26|25|24| 23|22|21|20| 19|18|17|16
+	     * ==|==|=====| ==|==|==|==| ==|==|==|==| ==|==|==|==
+	     *  0| 0| 0| 0|  0| 0| 0| 0|  0| 0|ID|VP| VF|AC|VM|RF
+	     *
+	     * 15|14|13|12| 11|10| 9| 8|  7| 6| 5| 4|  3| 2| 1| 0
+	     * ==|==|=====| ==|==|==|==| ==|==|==|==| ==|==|==|==
+	     *  0|NT| IOPL| OF|DF|IF|TF| SF|ZF| 0|AF|  0|PF| 1|CF
+	     * --------------------------------------------------
+	     * @param id the global unique id
+		 * @param link pointer to bochs internal register memory
+		 */
+		BxFlagsReg(unsigned int id, regdata_t* link)
+			: BochsRegister(id, 32, link, RT_ST) { }
+
+		/**
+		 * Returns \c true if the corresponding flag is set, or \c false
+		 * otherwise.
+		 */
+		bool getCarryFlag() const    { return (BX_CPU(0)->get_CF()); }
+		bool getParityFlag() const   { return (BX_CPU(0)->get_PF()); }
+		bool getZeroFlag() const     { return (BX_CPU(0)->get_ZF()); }
+		bool getSignFlag() const     { return (BX_CPU(0)->get_SF()); }
+		bool getOverflowFlag() const { return (BX_CPU(0)->get_OF()); }
+
+		/**
+		 * Sets/resets various status FLAGS.
+		 */
+		void setCarryFlag(bool bit)    { BX_CPU(0)->set_CF(bit); }
+		void setParityFlag(bool bit)   { BX_CPU(0)->set_PF(bit); }
+		void setZeroFlag(bool bit)     { BX_CPU(0)->set_ZF(bit); }
+		void setSignFlag(bool bit)     { BX_CPU(0)->set_SF(bit); }
+		void setOverflowFlag(bool bit) { BX_CPU(0)->set_OF(bit); }
+		
+		/**
+		 * Sets the content of the status register.
+		 * @param data the new register data to be written; note that only the
+		 *        32 lower bits are used (bits 32-63 are ignored in 64 bit mode)
+		 */
+		void setData(regdata_t data)
+		{
+		  #ifdef BX_SUPPORT_X86_64
+			// We are in 64 bit mode: Just assign the lower 32 bits!
+			(*m_pData) = ((*m_pData) & 0xFFFFFFFF00000000ULL) |
+			             (data & 0xFFFFFFFFULL);
+		  #else
+			*m_pData = data;
+		  #endif
+		}
+};
+
+/**
+ * \class BochsRegister
+ * Bochs-specific implementation of the RegisterManager.
+ */
+class BochsRegisterManager : public RegisterManager
+{
+	public:
+		/**
+		 * Returns the current instruction pointer.
+		 * @return the current eip
+		 */
+		address_t getInstructionPointer()
+		{
+			return (static_cast<address_t>(
+				getSetOfType(RT_PC)->first()->getData()
+			));
+		}
+		/**
+		 * Retruns the top address of the stack.
+		 * @return the starting address of the stack
+		 */
+		address_t getStackPointer()
+		{
+		  #if BX_SUPPORT_X86_64
+			return (static_cast<address_t>(getRegister(RID_RSP)->getData()));
+		  #else
+			return (static_cast<address_t>(getRegister(RID_ESP)->getData()));
+		  #endif
+		}
+		/**
+		 * Retrieves the base ptr (holding the address of the
+		 * current stack frame).
+		 * @return the base pointer
+		 */
+		address_t getBasePointer()
+		{
+		  #if BX_SUPPORT_X86_64
+			return (static_cast<address_t>(getRegister(RID_RBP)->getData()));
+		  #else
+			return (static_cast<address_t>(getRegister(RID_EBP)->getData()));
+		  #endif
+		}
+};
+
+} // end-of-namespace: sal
+
+#endif /* __BOCHS_REGISTER_HPP__ */
--- a/core/SAL/bochs/CPULoop.ah
+++ b/core/SAL/bochs/CPULoop.ah
@ -0,0 +1,35 @@
+#ifndef __CPU_LOOP_AH__
+  #define __CPU_LOOP_AH__
+
+#include "../../AspectConfig.hpp"
+
+#if CONFIG_EVENT_CPULOOP == 1
+
+#include "../../../bochs/bochs.h" // for "BX_CPU_C"
+#include "../../../bochs/cpu/cpu.h" // for "bxInstruction_c"
+#include "../SALInst.hpp"
+
+aspect CPULoop
+{
+	pointcut cpuLoop() = "void defineCPULoopJoinPoint(...)";
+
+	//
+	// Event source: "instruction pointer"
+	//
+	advice execution (cpuLoop()) : after ()
+	{
+		// Points to the cpu class: "this" if BX_USE_CPU_SMF == 0,
+		// BX_CPU(0) otherwise
+		BX_CPU_C* pThis = *(tjp->arg<0>());
+		// Points to the *current* bxInstruction-object
+		bxInstruction_c* pInstr = *(tjp->arg<1>());
+
+		// report this event to the Bochs controller:
+		sal::simulator.onInstrPtrChanged(pThis->get_instruction_pointer());
+		// Note: get_bx_opcode_name(pInstr->getIaOpcode()) retrieves the mnemonics.
+	}
+};
+
+#endif // CONFIG_EVENT_CPULOOP
+
+#endif /* __CPU_LOOP_AH__ */
--- a/core/SAL/bochs/Controller.cc
+++ b/core/SAL/bochs/Controller.cc
@ -0,0 +1,179 @@
+#include "BochsController.hpp"
+#include "BochsMemory.hpp"
+#include "BochsRegister.hpp"
+#include "../Register.hpp"
+
+namespace sal
+{
+
+bx_bool restore_bochs_request = false;
+bx_bool save_bochs_request = false;
+bx_bool reboot_bochs_request = false;
+std::string  sr_path = "";
+
+BochsController::BochsController()
+	: SimulatorController(new BochsRegisterManager(), new BochsMemoryManager())
+{
+	// -------------------------------------
+	// Add the general purpose register:
+  #if BX_SUPPORT_X86_64
+	// -- 64 bit register --
+  	const string names[] = { "RAX", "RCX", "RDX", "RBX", "RSP", "RBP", "RSI",
+  	                         "RDI", "R8", "R9", "R10", "R11", "R12", "R13",
+  	                         "R14", "R15" };
+	for(unsigned short i = 0; i < 16; i++)
+	{
+		BxGPReg* pReg = new BxGPReg(i, 64, &(BX_CPU(0)->gen_reg[i].rrx));
+		pReg->setName(names[i]);
+		m_Regs->add(pReg);
+	}
+  #else
+  	// -- 32 bit register --
+  	const string names[] = { "EAX", "ECX", "EDX", "EBX", "ESP", "EBP", "ESI",
+							 "EDI" };
+	for(unsigned short i = 0; i < 8; i++)
+	{
+		BxGPReg* pReg = new BxGPReg(i, 32, &(BX_CPU(0)->gen_reg[i].dword.erx));
+		pReg->setName(names[i]);
+		m_Regs->add(pReg);
+	}
+  #endif // BX_SUPPORT_X86_64
+  #ifdef DEBUG
+	m_Regularity = 0; // disabled
+	m_Counter = 0;
+	m_pDest = NULL;
+  #endif
+	// -------------------------------------
+	// Add the Program counter register:
+  #if BX_SUPPORT_X86_64
+	BxPCReg* pPCReg = new BxPCReg(RID_PC, 64, &(BX_CPU(0)->gen_reg[BX_64BIT_REG_RIP].rrx));
+	pPCReg->setName("RIP");
+  #else
+    BxPCReg* pPCReg = new BxPCReg(RID_PC, 32, &(BX_CPU(0)->gen_reg[BX_32BIT_REG_EIP].dword.erx));
+	pFlagReg->setName("EIP");
+  #endif // BX_SUPPORT_X86_64
+    // -------------------------------------
+	// Add the Status register (x86 cpu FLAGS):
+	BxFlagsReg* pFlagReg = new BxFlagsReg(RID_FLAGS, reinterpret_cast<regdata_t*>(&(BX_CPU(0)->eflags)));
+	// Note: "eflags" is (always) of type Bit32u which matches the regdata_t only in
+	//       case of the 32 bit version (id est !BX_SUPPORT_X86_64). Therefor we need
+	//       to ensure to assign only 32 bit to the Bochs internal register variable
+	//       (see SAL/bochs/BochsRegister.hpp, setData) if we are in 64 bit mode.
+	pFlagReg->setName("FLAGS");
+	m_Regs->add(pFlagReg);
+	m_Regs->add(pPCReg);
+}
+
+BochsController::~BochsController()
+{
+	for(RegisterManager::iterator it = m_Regs->begin(); it != m_Regs->end(); it++)
+			delete (*it); // free the memory, allocated in the constructor
+	m_Regs->clear();
+	delete m_Regs;
+	delete m_Mem;
+}
+
+#ifdef DEBUG
+void BochsController::dbgEnableInstrPtrOutput(unsigned regularity, std::ostream* dest)
+{
+	m_Regularity = regularity;
+	m_pDest = dest;
+	m_Counter = 0;
+}
+#endif // DEBUG
+
+void BochsController::onInstrPtrChanged(address_t instrPtr)
+{
+  #ifdef DEBUG
+	if(m_Regularity != 0 && ++m_Counter % m_Regularity == 0)
+		(*m_pDest) << "0x" << std::hex << instrPtr;
+  #endif
+	// Check for active breakpoint-events:
+	fi::EventList::iterator it = m_EvList.begin();
+	while(it != m_EvList.end())
+	{
+		// FIXME: Performance verbessern (dazu muss entsprechend auch die Speicherung
+		// in EventList(.cc|.hpp) angepasst bzw. verbessert werden).
+		fi::BPEvent* pEvBreakpt = dynamic_cast<fi::BPEvent*>(*it);
+		if(pEvBreakpt && (instrPtr == pEvBreakpt->getWatchInstructionPointer() ||
+		   pEvBreakpt->getWatchInstructionPointer() == fi::ANY_ADDR))
+		{
+			pEvBreakpt->setTriggerInstructionPointer(instrPtr);
+			it = m_EvList.makeActive(it);
+			// "it" has already been set to the next element (by calling
+			// makeActive()):
+			continue; // -> skip iterator increment
+		}
+		fi::BPRangeEvent* pEvRange = dynamic_cast<fi::BPRangeEvent*>(*it);
+		if(pEvRange && pEvRange->isMatching(instrPtr))
+		{
+			pEvBreakpt->setTriggerInstructionPointer(instrPtr);
+			it = m_EvList.makeActive(it);
+			continue; // dito.
+		}
+		it++;
+	}
+	m_EvList.fireActiveEvents();
+	// Note: SimulatorController::onBreakpointEvent will not be invoked in this
+	//       implementation.
+}
+
+void BochsController::save(const string& path)
+{
+	int stat;
+	
+	stat = mkdir(path.c_str(), 0777);
+	if(!(stat == 0 || errno == EEXIST))
+		std::cout << "[FAIL] Can not create target-directory to save!" << std::endl;
+		// TODO: (Non-)Verbose-Mode? Maybe better: use return value to indicate failure?
+	
+	save_bochs_request = true;
+	sr_path = path;
+	m_CurrFlow = m_Flows.getCurrent();
+	m_Flows.resume();
+}
+
+void BochsController::saveDone()
+{
+	save_bochs_request = false;
+	m_Flows.toggle(m_CurrFlow);
+}
+
+void BochsController::restore(const string& path)
+{
+	clearEvents();
+	restore_bochs_request = true;
+	sr_path = path;
+	m_CurrFlow = m_Flows.getCurrent();
+	m_Flows.resume();
+}
+
+void BochsController::restoreDone()
+{
+	restore_bochs_request = false;
+	m_Flows.toggle(m_CurrFlow);
+}
+
+void BochsController::reboot()
+{
+	clearEvents();
+	reboot_bochs_request = true;
+	m_CurrFlow = m_Flows.getCurrent();
+	m_Flows.resume();
+}
+
+void BochsController::rebootDone()
+{
+	reboot_bochs_request = false;
+	m_Flows.toggle(m_CurrFlow);
+}
+
+void BochsController::terminate(int exCode)
+{
+	// Attention: This could cause Problems, e.g. because of non-closed sockets
+	std::cout << "[FAIL] Exit called by experiment with exit code: " << exCode << std::endl;
+	// TODO: (Non-)Verbose-Mode?
+	exit(exCode);
+}
+
+} // end-of-namespace: sal
--- a/core/SAL/bochs/GuestSysCom.ah
+++ b/core/SAL/bochs/GuestSysCom.ah
@ -0,0 +1,37 @@
+#ifndef __GUESTSYS_COM_AH__
+  #define __GUESTSYS_COM_AH__
+
+#include "../../AspectConfig.hpp"
+
+#if CONFIG_EVENT_GUESTSYS == 1
+
+#include "../../../bochs/bochs.h"
+#include "../../../bochs/cpu/cpu.h"
+#include "../SALInst.hpp"
+
+#include "bochs_helpers.hpp"
+
+// Fixed "port number" for "Guest system >> Bochs" communication
+#define BOCHS_COM_PORT	0x378
+
+aspect GuestSysCom
+{
+
+	pointcut outInstructions() = "% ...::bx_cpu_c::OUT_DX%(...)";
+
+	advice execution (outInstructions()) : after ()
+	{
+		//
+		// Event source: "guest system"
+		//
+		unsigned rDX = getCPU(tjp->that())->gen_reg[2].word.rx; // port number
+		unsigned rAL = getCPU(tjp->that())->gen_reg[0].word.byte.rl; // data
+		if (rDX == BOCHS_COM_PORT) {
+			sal::simulator.onGuestSystemEvent((char)rAL, rDX);
+		}
+	}
+};
+
+#endif // CONFIG_EVENT_GUESTSYS
+
+#endif /* __GUESTSYS_COM_AH__ */
--- a/core/SAL/bochs/Interrupt.ah
+++ b/core/SAL/bochs/Interrupt.ah
@ -0,0 +1,40 @@
+#ifndef __INTERRUPT_AH__
+  #define __INTERRUPT_AH__
+
+#include "../../AspectConfig.hpp"
+
+#if CONFIG_EVENT_INTERRUPT == 1
+
+#include "../../../bochs/bochs.h"
+#include "../../../bochs/cpu/cpu.h"
+#include "../SALInst.hpp"
+
+aspect Interrupt
+{
+	// cpu/exception.cc
+	pointcut interrupt_method() = "void bx_cpu_c::interrupt(...)";
+
+	advice execution (interrupt_method()) : before ()
+	{
+		// There are six different type-arguments for the interrupt-method
+		// in cpu.h (lines 3867-3872):
+		//    - BX_EXTERNAL_INTERRUPT = 0,
+		//    - BX_NMI = 2,
+		//    - BX_HARDWARE_EXCEPTION = 3,  
+		//    - BX_SOFTWARE_INTERRUPT = 4,
+		//    - BX_PRIVILEGED_SOFTWARE_INTERRUPT = 5,
+		//    - BX_SOFTWARE_EXCEPTION = 6
+		// Only the first and the second types are relevant for this aspect.  
+
+		unsigned vector = *(tjp->arg<0>());
+		unsigned type = *(tjp->arg<1>());
+		if(type == BX_EXTERNAL_INTERRUPT)
+			sal::simulator.onInterruptEvent(vector, false);
+		else if(type == BX_NMI)
+			sal::simulator.onInterruptEvent(vector, true);
+	}
+};
+
+#endif // CONFIG_EVENT_INTERRUPT
+
+#endif /* __INTERRUPT_AH__ */
--- a/core/SAL/bochs/Interrupt_suppression.ah
+++ b/core/SAL/bochs/Interrupt_suppression.ah
@ -0,0 +1,28 @@
+#ifndef __INTERRUPT_SUPPRESSION_AH__
+  #define __INTERRUPT_SUPPRESSION_AH__
+
+#include "../../AspectConfig.hpp"
+
+#if CONFIG_SUPPRESS_INTERRUPTS == 1
+
+#include "../../../bochs/bochs.h"
+#include "../../../bochs/cpu/cpu.h"
+#include "../SALInst.hpp"
+
+aspect Interrupt_FI
+{
+	pointcut interrupt_method() = "void bx_cpu_c::interrupt(...)";
+
+	advice execution (interrupt_method()) : around ()
+	{	
+		unsigned type = *(tjp->arg<1>());
+		
+		if(!sal::simulator.isSuppressedInterrupt(type)){
+			tjp->proceed();
+		}
+	}
+};
+
+#endif // CONFIG_SUPPRESS_INTERRUPTS
+
+#endif /* __INTERRUPT_SUPPRESSION_AH__ */
--- a/core/SAL/bochs/Jump.ah
+++ b/core/SAL/bochs/Jump.ah
@ -0,0 +1,139 @@
+#ifndef __JUMP_AH__
+  #define __JUMP_AH__
+
+#include "../../AspectConfig.hpp"
+
+#if CONFIG_EVENT_JUMP == 1
+
+#include <iostream>
+#include <cstdlib>
+#include <string>
+#include <ctime>
+#include "../../../bochs/bochs.h"
+#include "../SALInst.hpp"
+
+using namespace std;
+
+aspect Jump
+{
+	// Note: Have a look at the Bochs-Code (cpu/cpu.h) and the Intel
+	// Architecture Software Developer's Manual - Instruction Set Reference
+	// p. 3-329 (PDF p. 369) for further information:
+	// http://www.intel.com/design/intarch/manuals/243191.htm
+
+	// Default conditional-jump instructions: they are evaluating the FLAGS,
+	// defined in ctrl_xfer[16 | 32 | 64].cc, Postfix: 16-Bit: w, 32-Bit: d, 64-Bit: q
+	pointcut defJumpInstructions()  =
+		"% ...::bx_cpu_c::JO_J%(...)"   ||
+		"% ...::bx_cpu_c::JNO_J%(...)"  ||
+		"% ...::bx_cpu_c::JB_J%(...)"   ||
+		"% ...::bx_cpu_c::JNB_J%(...)"  ||
+		"% ...::bx_cpu_c::JZ_J%(...)"   ||
+		"% ...::bx_cpu_c::JNZ_J%(...)"  ||
+		"% ...::bx_cpu_c::JBE_J%(...)"  ||
+		"% ...::bx_cpu_c::JNBE_J%(...)" ||
+		"% ...::bx_cpu_c::JS_J%(...)"   ||
+		"% ...::bx_cpu_c::JNS_J%(...)"  ||
+		"% ...::bx_cpu_c::JP_J%(...)"   ||
+		"% ...::bx_cpu_c::JNP_J%(...)"  ||
+		"% ...::bx_cpu_c::JL_J%(...)"   ||
+		"% ...::bx_cpu_c::JNL_J%(...)"  ||
+		"% ...::bx_cpu_c::JLE_J%(...)"  ||
+		"% ...::bx_cpu_c::JNLE_J%(...)";
+
+	// Special cases: they are evaluating the content of the CX-/ECX-/RCX-registers
+	// (NOT the FLAGS):
+	pointcut regJumpInstructions()  =
+		"% ...::bx_cpu_c::JCXZ_Jb(...)"  ||		// ctrl_xfer16.cc
+		"% ...::bx_cpu_c::JECXZ_Jb(...)" ||		// ctrl_xfer32.cc
+		"% ...::bx_cpu_c::JRCXZ_Jb(...)";		// ctrl_xfer64.cc
+
+/* TODO: Loop-Instructions needed?       Example: "LOOPNE16_Jb"
+	pointcut loopInstructions() = ...;
+
+*/
+/* TODO: Conditional-Data-Moves needed?  Example: "CMOVZ_GwEwR"
+	pointcut dataMoveInstructions() = ...;
+
+*/
+	advice execution (defJumpInstructions()) : around()
+	{
+		bxInstruction_c* pInstr = *(tjp->arg<0>()); // bxInstruction_c-object
+		sal::simulator.onJumpEvent(true, pInstr->getIaOpcode());
+/*
+		JoinPoint::That* pThis = tjp->that();
+		if(pThis == NULL)
+			pThis = BX_CPU(0);
+		assert(pThis != NULL && "FATAL ERROR: tjp->that() returned null ptr! (Maybe called on a static instance?)");
+		// According to the Intel-Spec (p. 3-329f), the following flags are relevant:
+		bool fZeroFlag     = pThis->get_ZF();
+		bool fCarryFlag    = pThis->get_CF(); 
+		bool fSignFlag     = pThis->get_SF();
+		bool fOverflowFlag = pThis->get_OF();
+		bool fParityFlag   = pThis->get_PF();
+
+		//
+		// Step-1: Modify one or more of the fxxxFlag according to the error you want to inject
+		//         (using pThis->set_XX(new_val))
+		// Step-2: Call tjp->proceed();
+		// Step-3: Eventually, unwind the changes of Step-1
+		//
+
+		// Example:
+		if(g_fEnableInjection) // event fired?
+		{
+			g_fEnableInjection = false;
+			// Obviously, this advice matches *all* jump-instructions so that it is not clear
+			// which flag have to be modified in order to invert the jump. For simplification,
+			// we will invert *all* flags. This avoids a few case differentiations.
+			cout << ">>> Manipulating jump-destination (inverted)... \"" << tjp->signature() << "\" ";
+			pThis->set_ZF(!fZeroFlag);
+			pThis->set_SF(!fSignFlag);
+			pThis->set_CF(!fCarryFlag);
+			pThis->set_OF(!fOverflowFlag);
+			pThis->set_PF(!fParityFlag);
+			tjp->proceed();
+			pThis->set_ZF(fZeroFlag);
+			pThis->set_SF(fSignFlag);
+			pThis->set_CF(fCarryFlag);
+			pThis->set_OF(fOverflowFlag);
+			pThis->set_PF(fParityFlag);
+			cout << "finished (jump taken)!" << endl;
+		}
+		else
+*/
+			tjp->proceed();
+	}
+
+	advice execution (regJumpInstructions()) : around ()
+	{
+		bxInstruction_c* pInstr = *(tjp->arg<0>()); // bxInstruction_c-object
+		sal::simulator.onJumpEvent(false, pInstr->getIaOpcode());
+/*
+		JoinPoint::That* pThis = tjp->that();
+
+		assert(pThis != NULL && "Unexpected: tjp->that() returned null ptr! (Maybe called on a static instance?)");
+
+		// Note: Direct access to the registers using the bochs-macros (defined in
+		// bochs.h) is not possibly due to the fact that they are using the this-ptr.
+
+		Bit16u CX  = (Bit16u)(pThis->gen_reg[1].word.rx);
+		Bit32u ECX = (Bit32u)(pThis->gen_reg[1].dword.erx);
+     #if BX_SUPPORT_X86_64
+		Bit64u RCX = (Bit64u)(pThis->gen_reg[1].rrx);
+     #endif
+
+		//
+		// Step-1: Modify CX, ECX or RCX according to the error you want to inject
+		// Step-2: Call tjp->proceed();
+		// Step-3: Eventually, unwind the changes of Step-1
+		//
+*/
+		tjp->proceed();
+	}
+};
+
+#endif // CONFIG_EVENT_JUMP
+
+#endif /* __JUMP_AH__ */
+
--- a/core/SAL/bochs/JumpToPreviousCtx.ah
+++ b/core/SAL/bochs/JumpToPreviousCtx.ah
@ -0,0 +1,33 @@
+#ifndef __JUMP_TO_PREVIOUS_CTX_AH__
+  #define __JUMP_TO_PREVIOUS_CTX_AH__
+
+#include "../../AspectConfig.hpp"
+
+#if 0
+// #if CONFIG_SR_RESTORE == 1 || CONFIG_SR_REBOOT == 1
+
+#include "bochs.h"
+#include "../SALInst.hpp"
+
+aspect jumpToPreviousCtx
+{
+	pointcut end_reset_handler()  = "void bx_gui_c::reset_handler(...)";
+									//|| "int bxmain()";
+
+
+	advice execution (end_reset_handler()) : after ()
+	{
+		
+		if (sal::restore_bochs_request || sal::reboot_bochs_request )
+		{
+			sal::restore_bochs_request = false;
+			sal::reboot_bochs_request = false;
+			sal::simulator.toPreviousCtx();
+		}
+
+	}
+};
+
+#endif // CONFIG_SR_RESTORE == 1 || CONFIG_SR_REBOOT
+
+#endif // __JUMP_TO_PREVIOUS_CTX_AH__
--- a/core/SAL/bochs/MemAccessBitFlip.ah
+++ b/core/SAL/bochs/MemAccessBitFlip.ah
@ -0,0 +1,100 @@
+#ifndef __MEM_ACCESS_BIT_FLIP_AH__
+  #define __MEM_ACCESS_BIT_FLIP_AH__
+
+#include "../../AspectConfig.hpp"
+
+#if CONFIG_FI_MEM_ACCESS_BITFLIP == 1
+
+#include <iostream>
+#include <cstdlib>
+#include <ctime>
+#include "bochs.h"
+
+#include "../../controller/EventList.hpp"
+#include "../../controller/Event.hpp"
+
+using namespace std;
+
+// FIXME this code doesn't make any sense for the read_virtual_% functions
+// (the fault would need to be injected into their *return* value)
+
+aspect MemAccessBitFlip
+{
+	pointcut injection_methods() 
+									 = "% ...::bx_cpu_c::read_virtual_%(...)" || 		// -> access32/64.cc
+/*
+										"% ...::bx_cpu_c::read_RMW_virtual_%(...)" ||	// -> access32.cc
+										"% ...::bx_cpu_c::system_read_%(...)" ||			// -> access.cc
+										"% ...::bx_cpu_c::v2h_read_byte(...)" ||			// -> access.cc
+*/
+										"% ...::bx_cpu_c::write_virtual_%(...)"; 			// -> access32/64.cc
+/*
+										"% ...::bx_cpu_c::write_RMW_virtual_%(...)" ||	// -> access32.cc
+										"% ...::bx_cpu_c::write_new_stack_%(...)" ||		// -> access32/64.cc
+										"% ...::bx_cpu_c::system_write_%(...)" ||			// -> access.cc
+										"% ...::bx_cpu_c::v2h_write_byte(...)";			// -> access.cc
+*/
+
+
+	//
+	// Injects a bitflip each time the guest system requests to write/read
+	// data to/from RAM at the (hardcoded) addresses defined above:
+	//
+	// Event source: "memory write/read access"
+	//
+	advice execution (injection_methods()) : before ()
+	{
+		for(size_t i = 0; i < fi::evbuf.getEventCount(); i++) // check for active events
+		{
+			fi::SimpleBitFlip* pEv = dynamic_cast<fi::SimpleBitFlip*>(fi::evbuf.getEvent(i)); // FIXME: Performance verbessern
+			if(pEv && *(tjp->arg<1>())/*typed!*/ == pEv->getAddress())
+			{
+				cout << " " << tjp->signature() << endl;
+
+				// Get a pointer to the data that should be written to RAM
+				// *before* it is actually written:
+				Bit32u* pData = (Bit32u*)(tjp->arg(JoinPoint::ARGS-1));
+
+				// Flip bit at position pEv->getBitPos():
+				char* ptr = (char*)pData; // For simplification we're just looking at the
+						                    // first byte of the data
+				ptr[0] = (ptr[0]) ^ (pEv->getMask() << pEv->getBitPos());
+
+				cout << "  >>> Bit flipped at index " << pEv->getBitPos()
+					  << " at address 0x" << hex << (*(tjp->arg<1>())) << "!" << endl;
+				fi::evbuf.fireEvent(pEv);
+				// Continue... (maybe more events to process)
+			}
+		}
+	}
+/*
+		//
+		// Shows the mapping of a virtual address (within eCos) to a *host* address:
+		//
+		if(g_fEnableInjection) // event fired?
+		{
+			g_fEnableInjection = false;
+			const unsigned SEGMENT_SELECTOR_IDX = 2; // always the code segment (seg-base-addr should be zero)
+			const bx_address logicalAddr = MEM_ADDR_TO_INJECT; // offset within the segment ("local eCos address")
+
+			// Get the linear address:
+			Bit32u linearAddr = pThis->get_laddr32(SEGMENT_SELECTOR_IDX/ *seg* /, logicalAddr/ *offset* /);
+			// Map the linear address to the physical address:
+	  		bx_phy_address physicalAddr;
+	  		bx_bool fValid = pThis->dbg_xlate_linear2phy(linearAddr, (bx_phy_address*)&physicalAddr);
+			// Determine the *host* address of the physical address:
+			Bit8u* hostAddr = BX_MEM(0)->getHostMemAddr(pThis, physicalAddr, BX_READ);
+			// Now, hostAddr contains the "final" address where we are allowed to inject errors:
+			*(unsigned*)hostAddr = BAD_VALUE; // inject error
+	  		if(!fValid)
+				printf("[Error]: Could not map logical address to host address.\n");
+			else
+				printf("[Info]: Error injected at logical addr %p (host addr %p).\n", logicalAddr, hostAddr);
+		}
+*/
+};
+
+#endif // CONFIG_FI_MEM_ACCESS_BITFLIP
+
+#endif // __MEM_ACCESS_BIT_FLIP_AH__
+
--- a/core/SAL/bochs/MemEvents.ah
+++ b/core/SAL/bochs/MemEvents.ah
@ -0,0 +1,146 @@
+#ifndef __MEM_EVENTS_AH__
+  #define __MEM_EVENTS_AH__
+
+#include <iostream>
+#include "../../AspectConfig.hpp"
+
+#if CONFIG_EVENT_MEMREAD == 1 || CONFIG_EVENT_MEMWRITE == 1
+
+#include "../../../bochs/bochs.h"
+#include "../../../bochs/cpu/cpu.h"
+#include "../SALInst.hpp"
+
+#include "bochs_helpers.hpp"
+
+// FIXME we currently assume a "flat" memory model and ignore the segment
+//       parameter of all memory accesses
+// TODO instruction fetch?
+// TODO warn on uncovered memory accesses
+aspect MemEvents
+{
+	sal::address_t rmw_address;
+
+	pointcut write_methods() =
+		"% ...::bx_cpu_c::write_virtual_%(...)" && // -> access32/64.cc
+	// not an actual memory access:
+		!"% ...::bx_cpu_c::write_virtual_checks(...)";
+	pointcut write_methods_RMW() =
+		"% ...::bx_cpu_c::write_RMW_virtual_%(...)";
+	pointcut write_methods_new_stack() =
+		"% ...::bx_cpu_c::write_new_stack_%(...)" &&	// -> access32.cc
+		!"% ...::bx_cpu_c::write_new_stack_%_64(...)";
+	pointcut write_methods_new_stack_64() =
+		"% ...::bx_cpu_c::write_new_stack_%_64(...)";	// -> access64.cc
+	pointcut write_methods_system() =
+		"% ...::bx_cpu_c::system_write_%(...)";		// -> access.cc
+	// FIXME not covered:
+	/* "% ...::bx_cpu_c::v2h_write_byte(...)";		// -> access.cc */
+
+	pointcut read_methods()  =
+		 "% ...::bx_cpu_c::read_virtual_%(...)" &&
+	// sizeof() doesn't work here (see next pointcut)
+		!"% ...::bx_cpu_c::read_virtual_dqword_%(...)" &&	// -> access32/64.cc
+	// not an actual memory access:
+		!"% ...::bx_cpu_c::read_virtual_checks(...)";
+	pointcut read_methods_dqword() =
+		"% ...::bx_cpu_c::read_virtual_dqword_%(...)";	// -> access32/64.cc
+	pointcut read_methods_RMW() =
+		"% ...::bx_cpu_c::read_RMW_virtual_%(...)";
+	pointcut read_methods_system() =
+		"% ...::bx_cpu_c::system_read_%(...)";		// -> access.cc
+	// FIXME not covered:
+	/* "% ...::bx_cpu_c::v2h_read_byte(...)";		// -> access.cc */
+
+	//
+	// Fire a memory-write-event each time the guest system requests
+	// to write data to RAM:
+	//
+	// Event source: "memory write access"
+	//
+#if CONFIG_EVENT_MEMWRITE == 1
+	advice execution (write_methods()) : after () {
+		sal::simulator.onMemoryAccessEvent(
+			*(tjp->arg<1>()), sizeof(*(tjp->arg<2>())), true,
+			getCPU(tjp->that())->prev_rip);
+	}
+
+	advice execution (write_methods_RMW()) : after () {
+		sal::simulator.onMemoryAccessEvent(
+			rmw_address, sizeof(*(tjp->arg<0>())), true,
+			getCPU(tjp->that())->prev_rip);
+	}
+
+	advice execution (write_methods_new_stack()) : after () {
+		std::cerr << "WOOOOOT write_methods_new_stack" << std::endl;
+		sal::simulator.onMemoryAccessEvent(
+			*(tjp->arg<1>()), sizeof(*(tjp->arg<3>())), true,
+			getCPU(tjp->that())->prev_rip);
+	}
+
+	advice execution (write_methods_new_stack_64()) : after () {
+		std::cerr << "WOOOOOT write_methods_new_stack_64" << std::endl;
+		sal::simulator.onMemoryAccessEvent(
+			*(tjp->arg<0>()), sizeof(*(tjp->arg<2>())), true,
+			getCPU(tjp->that())->prev_rip);
+	}
+
+	advice execution (write_methods_system()) : after () {
+		// We don't do anything here for now: This type of memory
+		// access is used when the hardware itself needs to access
+		// memory (e.g., to read vectors from the interrupt vector
+		// table).
+/*
+		sal::simulator.onMemoryAccessEvent(
+			*(tjp->arg<0>()), sizeof(*(tjp->arg<1>())), true,
+			getCPU(tjp->that())->prev_rip);
+*/
+	}
+#endif
+
+	//
+	// Fire a memory-read-event each time the guest system requests
+	// to read data in RAM:
+	//
+	// Event source: "memory read access"
+	//
+#if CONFIG_EVENT_MEMREAD == 1
+	advice execution (read_methods()) : before () {
+		sal::simulator.onMemoryAccessEvent(
+			*(tjp->arg<1>()), sizeof(*(tjp->result())), false,
+			getCPU(tjp->that())->prev_rip);
+	}
+
+	advice execution (read_methods_dqword()) : before () {
+		sal::simulator.onMemoryAccessEvent(
+			*(tjp->arg<1>()), 16, false,
+			getCPU(tjp->that())->prev_rip);
+	}
+#endif
+
+	advice execution (read_methods_RMW()) : before () {
+		rmw_address = *(tjp->arg<1>());
+#if CONFIG_EVENT_MEMREAD == 1
+		sal::simulator.onMemoryAccessEvent(
+			*(tjp->arg<1>()), sizeof(*(tjp->result())), false,
+			getCPU(tjp->that())->prev_rip);
+#endif
+	}
+
+#if CONFIG_EVENT_MEMREAD == 1
+	advice execution (read_methods_system()) : before () {
+		// We don't do anything here for now: This type of memory
+		// access is used when the hardware itself needs to access
+		// memory (e.g., to read vectors from the interrupt vector
+		// table).
+/*
+		sal::simulator.onMemoryAccessEvent(
+			*(tjp->arg<0>()), sizeof(*(tjp->result())), false,
+			getCPU(tjp->that())->prev_rip);
+*/
+	}
+#endif
+};
+
+#endif // CONFIG_EVENT_MEMACCESS
+
+#endif /* __MEM_EVENTS_AH__ */
--- a/core/SAL/bochs/Trap.ah
+++ b/core/SAL/bochs/Trap.ah
@ -0,0 +1,27 @@
+#ifndef __TRAP_AH__
+  #define __TRAP_AH__
+
+#include "../../AspectConfig.hpp"
+
+#if CONFIG_EVENT_TRAP == 1
+
+#include "../../../bochs/bochs.h"
+#include "../../../bochs/cpu/cpu.h"
+
+#include "../SALInst.hpp"
+
+aspect Trap
+{
+	pointcut exception_method() = "void bx_cpu_c::exception(...)";
+
+	advice execution (exception_method()) : before ()
+	{
+		sal::simulator.onTrapEvent(*(tjp->arg<0>()));
+		// TODO: There are some different types of exceptions at cpu.h (line 265-281)
+		//       Which kind of a trap are these types?
+	}
+};
+
+#endif // CONFIG_EVENT_TRAP
+
+#endif /* __TRAP_AH__ */
--- a/core/SAL/bochs/bochs_helpers.hpp
+++ b/core/SAL/bochs/bochs_helpers.hpp
@ -0,0 +1,15 @@
+#ifndef __BOCHS_HELPERS_HPP__
+  #define __BOCHS_HELPERS_HPP__
+
+#include "../../../bochs/cpu/cpu.h"
+
+static inline BX_CPU_C *getCPU(BX_CPU_C *that)
+{
+#if BX_USE_CPU_SMF == 0
+	return that;
+#else
+	return BX_CPU_THIS;
+#endif
+}
+
+#endif
--- a/core/SAL/bochs/credits.ah
+++ b/core/SAL/bochs/credits.ah
@ -0,0 +1,27 @@
+#ifndef __CREDITS_AH__
+  #define __CREDITS_AH__
+
+#include <string.h>
+
+aspect credits {
+	bool first;
+	credits() : first(true) {}
+
+	advice call ("% bx_center_print(...)") 
+	    && within ("void bx_print_header()")
+	    && args(file, line, maxwidth)
+	    : around (FILE *file, const char *line, unsigned maxwidth) {
+		if (!first) {
+			tjp->proceed();
+			return;
+		}
+		// FIXME take version from global configuration
+		char buf[256] = "FailBochs 0.0.1, based on the ";
+		strncat(buf, line, 128);
+		first = false;
+		*(tjp->arg<1>()) = buf;
+		tjp->proceed();
+	}
+};
+
+#endif // __CREDITS_AH__
--- a/core/SAL/bochs/disable_add_remove_logfn.ah
+++ b/core/SAL/bochs/disable_add_remove_logfn.ah
@ -0,0 +1,19 @@
+#ifndef __DISABLE_ADD_REMOVE_LOGFN_AH__
+  #define __DISABLE_ADD_REMOVE_LOGFN_AH__
+
+/* Hack to prevent Bochs' logfunctions list (bochs.h) to overflow if the
+ * experiment restores simulator state more than ~1000 times.
+ *
+ * The "proper" fix would be to completely unregister all log functions before
+ * restore, i.e. to destroy all objects deriving from class logfunctions.  We
+ * decided to simply ignore this tiny memory leak and to hack around the
+ * problem by disabling iofunctions::add/remove_logfn().
+ */
+aspect DisableLogfn {
+	pointcut add_remove_logfn() =
+		"void iofunctions::add_logfn(...)" ||
+		"void iofunctions::remove_logfn(...)";
+	advice execution (add_remove_logfn()) : around () {}
+};
+
+#endif /* __DISABLE_ADD_REMOVE_LOGFN_AH__ */
--- a/core/SAL/bochs/disable_keyboard_interrupt.ah
+++ b/core/SAL/bochs/disable_keyboard_interrupt.ah
@ -0,0 +1,25 @@
+#ifndef __DISABLE_KEYBOARD_INTERRUPT_AH__
+  #define __DISABLE_KEYBOARD_INTERRUPT_AH__
+
+#include "../../AspectConfig.hpp"
+
+#if CONFIG_DISABLE_KEYB_INTERRUPTS
+
+#include "../../../bochs/iodev/keyboard.h"
+
+aspect DisableKeybInt {
+	pointcut heyboard_interrupt() =
+		"void bx_keyb_c::timer_handler(...)";
+		
+	advice execution (heyboard_interrupt()) : around () {
+		
+		bx_keyb_c *class_ptr = (bx_keyb_c *) tjp->arg<0>();
+		unsigned retval;
+
+		retval=class_ptr->periodic(1);
+	}
+};
+
+#endif /* CONFIG_DISABLE_KEYB_INTERRUPTS */
+
+#endif /* __DISABLE_KEYBOARD_INTERRUPT_AH__ */
--- a/core/SAL/bochs/failbochs.hpp
+++ b/core/SAL/bochs/failbochs.hpp
@ -0,0 +1,21 @@
+#ifndef FAILBOCHS_H
+#define FAILBOCHS_H
+
+#include <string>
+#include <string.h>
+
+#include "config.h" 
+
+namespace sal{
+
+  //DanceOS Richard Hellwig
+#ifdef DANCEOS_RESTORE
+  extern bx_bool restore_bochs_request;
+  extern bx_bool save_bochs_request;
+  extern bx_bool reboot_bochs_request;
+  extern std::string sr_path;
+#endif
+
+}
+
+#endif //FAILBOCHS_H
--- a/core/SAL/bochs/fireTimer.ah
+++ b/core/SAL/bochs/fireTimer.ah
@ -0,0 +1,27 @@
+#ifndef __FIRETIMER_AH__
+  #define __FIRETIMER_AH__
+
+#include <iostream>
+
+
+aspect fireTimer {
+	
+	advice "bx_pc_system_c" : slice class {
+		public:
+			void fireTimer(Bit32u timerNum){
+				if(timerNum <= numTimers){
+					if(!timer[timerNum].active){
+						std::cout << "[FAIL] WARNING: The selected timer is actually NOT active!" << std::endl;
+					}
+					currCountdownPeriod = Bit64u(1);
+					timer[timerNum].timeToFire = Bit64u(currCountdownPeriod) + ticksTotal;
+					std::cout << "[FAIL] Timer " << timerNum <<" will fire now!" << std::endl;
+				}else{
+					std::cout << "[FAIL] There are actually only " << numTimers <<" allocated!" << std::endl;
+				}
+			}
+	};
+};
+
+
+#endif // __FIRETIMER_AH__
--- a/core/SAL/bochs/init.ah
+++ b/core/SAL/bochs/init.ah
@ -0,0 +1,12 @@
+#ifndef __BXINIT_AH__
+  #define __BXINIT_AH__
+
+#include "../SALInst.hpp"
+
+aspect BochsInit {
+	advice call("int bxmain()") : before () {
+		sal::simulator.startup();
+	}
+};
+
+#endif // __BXINIT_AH__
--- a/core/SAL/bochs/reboot.ah
+++ b/core/SAL/bochs/reboot.ah
@ -0,0 +1,27 @@
+#ifndef __REBOOT_AH__
+  #define __REBOOT_AH__
+
+#include "../../AspectConfig.hpp"
+#include "../SALInst.hpp"
+
+#if CONFIG_SR_REBOOT == 1
+
+#include "bochs.h"
+
+aspect reboot {
+	pointcut cpuLoop()  = "void defineCPULoopJoinPoint(...)";
+
+	advice execution (cpuLoop()) : after () {
+		if (!sal::reboot_bochs_request) {
+			return;
+		}
+		
+		bx_gui_c::reset_handler();
+		std::cout << "[FAIL] Reboot finished" << std::endl;
+		sal::simulator.rebootDone();
+	}
+};
+
+#endif // CONFIG_SR_REBOOT
+
+#endif // __REBOOT_AH__
--- a/core/SAL/bochs/restore.ah
+++ b/core/SAL/bochs/restore.ah
@ -0,0 +1,23 @@
+#ifndef __RESTORE_AH__
+  #define __RESTORE_AH__
+
+#include <iostream>
+#include "../../AspectConfig.hpp"
+#include "../SALInst.hpp"
+
+#if CONFIG_SR_RESTORE == 1
+
+#include "bochs.h"
+
+aspect restore {
+	pointcut restoreState()  = "void bx_sr_after_restore_state()";
+
+	advice execution (restoreState()) : after () {
+		std::cout << "[FAIL] Restore finished" << std::endl;
+		sal::simulator.restoreDone();
+	}
+};
+
+#endif // CONFIG_SR_RESTORE
+
+#endif // __RESTORE_AH__
--- a/core/SAL/bochs/save.ah
+++ b/core/SAL/bochs/save.ah
@ -0,0 +1,32 @@
+#ifndef __SAVE_AH__
+  #define __SAVE_AH__
+
+#include "../../AspectConfig.hpp"
+
+#if CONFIG_SR_SAVE == 1
+
+#include "bochs.h"
+#include "../SALInst.hpp"
+
+aspect save {
+	pointcut cpuLoop()  = "void defineCPULoopJoinPoint(...)";
+
+	// make sure the "save" aspect comes *after* the breakpoint stuff: In
+	// an "after" advice this means it must get a *higher* precedence,
+	// therefore it's first in the order list.
+	advice execution (cpuLoop()) : order ("save", "CPULoop");
+
+	advice execution (cpuLoop()) : after () {
+		if (!sal::save_bochs_request) {
+			return;
+		}
+		assert(sal::sr_path.size() > 0 && "[FAIL] tried to save state without valid path");
+		SIM->save_state(sal::sr_path.c_str());
+		std::cout << "[FAIL] Save finished" << std::endl;
+		sal::simulator.saveDone();
+	}
+};
+
+#endif // CONFIG_SR_SAVE
+
+#endif // _SAVE_AH__
--- a/core/SAL/bochs/stfu.ah
+++ b/core/SAL/bochs/stfu.ah
@ -0,0 +1,54 @@
+#ifndef __NONVERBOSE_AH__
+  #define __NONVERBOSE_AH__
+
+#include "../../AspectConfig.hpp"
+
+#if CONFIG_STFU == 1
+
+#include "bochs.h"
+
+// Doesn't work because AspectC++ doesn't deal properly with variadic parameter
+// lists:
+/*
+aspect nonverbose {
+	// needed to suppress Bochs output *before* a state restore finished
+	// FIXME ac++ segfaults if we use call() instead of execution()
+	advice execution("% logfunctions::debug(...)")
+	    || execution("% logfunctions::info(...)")
+	    || execution("% logfunctions::pass(...)")
+	    || execution("% logfunctions::error(...)")
+	     : around () {
+	}
+};
+*/
+
+aspect nonverbose {
+	// needed to suppress Bochs output *before* a state restore finished
+	advice call("int logfunctions::get_default_action(int)")
+	     : around () {
+		int action;
+		switch (*(tjp->arg<0>())) {
+		case LOGLEV_DEBUG:
+		case LOGLEV_PASS:
+		case LOGLEV_INFO:
+			action = ACT_IGNORE;
+			break;
+		case LOGLEV_ERROR:
+			action = ACT_REPORT;
+			break;
+		case LOGLEV_PANIC:
+		default:
+			action = ACT_FATAL;
+		}
+		*(tjp->result()) = action;
+	}
+
+	// no credits header
+	advice call("void bx_print_header()")
+	     : around () {
+	}
+};
+
+#endif
+
+#endif
--- a/core/SAL/ovp/Controller.cc
+++ b/core/SAL/ovp/Controller.cc
@ -0,0 +1,139 @@
+#include <iostream>
+#include "OVPController.hpp"
+#include "OVPMemory.hpp"
+#include "OVPRegister.hpp"
+#include "../../../ovp/OVPStatusRegister.hpp"
+
+namespace sal {
+
+OVPController::OVPController()
+	: SimulatorController(new OVPRegisterManager(), new OVPMemoryManager())
+{
+	//FIXME: This should be obsolete now...
+	//set = new UniformRegisterSet(RT_GP);	
+	//setStatus = new UniformRegisterSet(RT_ST);	
+	//setPC= new UniformRegisterSet(RT_PC);	
+}
+
+OVPController::~OVPController()
+{
+	//FIXME: This should be obsolete now...
+	//delete set;
+	//delete setStatus;
+	//delete setPC;
+
+	// Free memory of OVPRegister objects (actually allocated in make*Register):
+	for(RegisterManager::iterator it = m_Regs->begin(); it != m_Regs->end(); it++)
+			delete (*it); // free the memory, allocated in the constructor
+}
+
+void OVPController::makeGPRegister(int width, void *link, const string& name) {
+	// Add general purpose register
+	OVPRegister *reg = new OVPRegister(m_currentRegId++, width, link, RT_GP);
+	reg->setName(name);
+	m_Regs->add(reg);
+	// Note: The RegisterManager (aka m_Regs) automatically assigns the 
+	//       added registers (herein typed OVPRegister) to their matching
+	//       UniformRegisterSet (@see RegisterManager::add).
+}
+
+
+void OVPController::makeSTRegister(Register *reg, const string& name) {
+	// Add status register
+	reg->setName(name);
+	cerr << "Add Status Register: " << reg << endl;
+	m_Regs->add(reg);
+}
+
+void OVPController::makePCRegister(int width, void *link, const string& name) {
+	// Add general purpose register
+	OVPRegister *reg = new OVPRegister(m_currentRegId++, width, link, RT_PC);
+	reg->setName(name);
+	m_Regs->add(reg);
+}
+
+//FIXME: This should be obsolete now...
+//void OVPController::finishedRegisterCreation() {
+//	m_Regs->add(*set);
+//	m_Regs->add(*setStatus);
+//	m_Regs->add(*setPC);
+//}
+
+void OVPController::onInstrPtrChanged(address_t instrPtr)
+{
+	// make some funny outputs
+	unsigned int r0 = m_Regs->getSetOfType(RT_GP)->getRegister(0)->getData();
+	OVPRegisterManager *ovp_Regs = (OVPRegisterManager *) m_Regs;
+	// FIXME: This cast seems to be invalid: RT_GP vs. OVPStatusRegister (= RT_ST)?
+	OVPStatusRegister *rid_st = (OVPStatusRegister *) m_Regs->getSetOfType(RT_GP)->first();
+//	cerr << "Addr: " << rid_st << endl;
+	unsigned int st = rid_st->getData();
+//	cerr << "instrPtr: 0x" << hex << instrPtr << " SP: 0x" << hex << m_Regs->getStackPointer() \
+		<< " R0: 0x" << hex << r0 << " ST: 0x" << hex << st  << endl;
+
+	// Check for active breakpoint-events:
+	fi::EventList::iterator it = m_EvList.begin();
+	while(it != m_EvList.end())
+	{
+		// FIXME: Performance verbessern (dazu muss entsprechend auch die Speicherung
+		// in EventList(.cc|.hpp) angepasst bzw. verbessert werden).
+		fi::BPEvent* pEvBreakpt = dynamic_cast<fi::BPEvent*>(*it);
+		if(pEvBreakpt && (instrPtr == pEvBreakpt->getWatchInstructionPointer() ||
+		   pEvBreakpt->getWatchInstructionPointer() == fi::ANY_ADDR))
+		{
+			pEvBreakpt->setTriggerInstructionPointer(instrPtr);
+			it = m_EvList.makeActive(it);
+			// "it" has already been set to the next element (by calling
+			// makeActive()):
+			continue; // -> skip iterator increment
+		}
+		fi::BPRangeEvent* pEvRange = dynamic_cast<fi::BPRangeEvent*>(*it);
+		if(pEvRange && pEvRange->isMatching(instrPtr))
+		{
+			pEvBreakpt->setTriggerInstructionPointer(instrPtr);
+			it = m_EvList.makeActive(it);
+			continue; // dito.
+		}
+		it++;
+	}
+	m_EvList.fireActiveEvents();
+}
+
+void OVPController::save(const string& path)
+{
+	//TODO
+	//SIM->save_state(path.c_str());
+	//bx_gui_c::power_handler();
+}
+
+void OVPController::restore(const string& path)
+{
+	//TODO
+	//bx_pc_system.restore_bochs_request = true;
+	assert(path.length() > 0 &&
+		"FATAL ERROR: Tried to restore state without valid path!");
+	//strncpy(bx_pc_system.sr_path, path.c_str(), 512 /*CI_PATH_LENGTH, @see gui/textconfig.cc*/);
+}
+
+void OVPController::reboot()
+{
+	//TODO
+	//bx_pc_system.Reset(BX_RESET_HARDWARE);
+	//bx_gui_c::reset_handler();//TODO: leider protected, so geht das also nicht...
+}
+
+void OVPController::toPreviousCtx()
+{
+	// TODO
+}
+
+void OVPController::terminate(int exCode){
+
+}
+
+
+void OVPController::fireTimer(uint32_t){
+
+};
+
+};
--- a/core/SAL/ovp/OVPConfig.hpp
+++ b/core/SAL/ovp/OVPConfig.hpp
@ -0,0 +1,18 @@
+#ifndef __OVP_CONFIG_HPP__
+  #define __OVP_CONFIG_HPP__
+
+
+// Type definitions and configuration settings for
+// the OVP simulator.
+ 
+namespace sal
+{
+
+typedef uint32_t guest_address_t; //!< the guest memory address type
+typedef uint8_t*     host_address_t;  //!< the host memory address type
+typedef uint32_t register_data_t;   //!< register data type (32 bit)
+
+};
+
+#endif /* __OVP_CONFIG_HPP__ */
+
--- a/core/SAL/ovp/OVPController.hpp
+++ b/core/SAL/ovp/OVPController.hpp
@ -0,0 +1,90 @@
+#ifndef __OVP_CONTROLLER_HPP__
+  #define __OVP_CONTROLLER_HPP__
+
+#include <string>
+#include <cassert>
+#include <string.h>
+#include <string>
+
+#include "../SimulatorController.hpp"
+#include "../../controller/Event.hpp"
+
+#include "../../../ovp/OVPPlatform.hpp"
+
+#include "../Register.hpp"
+
+using namespace std;
+
+extern OVPPlatform ovpplatform;
+
+/// Simulator Abstraction Layer namespace
+namespace sal
+{
+
+/**
+ * \class OVPController
+ * OVP-specific implementation of a SimulatorController.
+ */
+class OVPController : public SimulatorController
+{
+	private:
+		//FIXME: This should be obsolete now...
+		//UniformRegisterSet *set; //(RT_GP);
+		//UniformRegisterSet *setStatus;//(RT_ST);
+		//UniformRegisterSet *setPC;//(RT_PC);
+
+		// (FIXME: perhaps this should be declared as a static member)
+		unsigned int m_currentRegId;
+		// NOTE: Constants (such as GPRegisterId in SAL/bochs/BochsRegister.hpp)
+		//       are much easier to read...
+	public:
+		// Initialize the controller.
+		OVPController();
+		virtual ~OVPController();
+		virtual void onInstrPtrChanged(address_t instrPtr); 
+		/**
+		 * Save simulator state.
+		 * @param path Location to store state information
+		 */
+		virtual void save(const string& path);
+		/**
+		 * Restore simulator state.
+		 * @param path Location to previously saved state information
+		 */
+		virtual void restore(const string& path);
+		/**
+		 * Reboot simulator.
+		 */
+		virtual void reboot();
+		/**
+		 * Handles the control back to the previous coroutine which
+		 * triggered the reboot. Need not to be called explicitly.
+		 */
+		void toPreviousCtx();
+		/**
+		 * Returns the current instruction pointer.
+		 * @return the current eip
+		 */
+
+		/**
+		 * Terminate simulator
+		 */
+		 virtual void terminate(int exCode = EXIT_SUCCESS);
+
+		 virtual void fireTimer(uint32_t);		 
+
+		 void makeGPRegister(int, void*, const string&);
+		 void makeSTRegister(Register *, const string&);
+		 void makePCRegister(int, void*, const string&);
+		 
+		 //DELETE-ME:This should be obsolete now...
+		 /**
+		  * Due to empty RegisterSets are not allowed, OVP platform
+		  * must tell OVPController when it is finished
+		  */
+		 //void finishedRegisterCreation();
+
+};
+};
+
+#endif
--- a/core/SAL/ovp/OVPMemory.hpp
+++ b/core/SAL/ovp/OVPMemory.hpp
@ -0,0 +1,92 @@
+#ifndef __OVP_MEMORY_HPP__
+  #define __OVP_MEMORY_HPP__
+
+#include "../Memory.hpp"
+
+namespace sal
+{
+
+/**
+ * \class OVPMemoryManager
+ * Represents a concrete implemenation of the abstract
+ * MemoryManager to provide access to OVP's memory pool.
+ */
+class OVPMemoryManager : public MemoryManager
+{
+	public:
+		/**
+		 * Constructs a new MemoryManager object and initializes
+		 * it's attributes appropriately.
+		 */
+		OVPMemoryManager() : MemoryManager() {  }
+		/**
+		 * Retrieves the size of the available simulated memory.
+		 * @return the size of the memory pool in bytes
+		 */
+		size_t getPoolSize() const
+		{
+			return 0;
+		}
+		/**
+		 * Retrieves the starting address of the host memory. This is the
+		 * first valid address in memory.
+		 * @return the starting address
+		 */
+		host_address_t getStartAddr() const
+		{
+			return (0);
+		}
+		/**
+		 * Retrieves the byte at address \a addr in the memory.
+		 * @param addr The guest address where the byte is located.
+		 *        The address is expected to be valid.
+		 * @return the byte at \a addr
+		 */
+		byte_t getByte(guest_address_t addr)
+		{
+			return (0);
+		}
+		/**
+		 * Retrieves \a cnt bytes at address \a addr in the memory.
+		 * @param addr The guest address where the bytes are located.
+		 *        The address is expected to be valid.
+		 * @param cnt The number of bytes to be retrieved. \a addr + \a cnt
+		 *        is expected to not exceed the memory limit.
+		 * @param dest The destination buffer to write the bytes to
+		 */
+		void getBytes(guest_address_t addr, size_t cnt, std::vector<byte_t>& dest)
+		{
+		}
+		/**
+		 * Writes the byte \a data to memory.
+		 * @param addr The guest address to write.
+		 *        The address is expected to be valid.
+		 * @param data The new byte to write
+		 */
+		void setByte(guest_address_t addr, byte_t data)
+		{
+		}
+		/**
+		 * Writes the bytes \a data to memory. Consequently \c data.size()
+		 * bytes will be written.
+		 * @param addr The guest address to write.
+		 *        The address is expected to be valid.
+		 * @param data The new bytes to write
+		 */
+		void setBytes(guest_address_t addr, const std::vector<byte_t>& data)
+		{
+		}
+		/**
+		 * Transforms the guest address \a addr to a host address.
+		 * @param addr The (logical) guest address to be transformed
+		 * @return the transformed (host) address or \c ADDR_INV on errors
+		 */
+		host_address_t guestToHost(guest_address_t addr)
+		{
+			return (0);		
+		}			
+};
+
+}
+
+#endif
--- a/core/SAL/ovp/OVPRegister.hpp
+++ b/core/SAL/ovp/OVPRegister.hpp
@ -0,0 +1,80 @@
+#ifndef __OVP_REGISTER_HPP__
+  #define __OVP_REGISTER_HPP__
+
+#include "../Register.hpp"
+#include "../../../ovp/OVPPlatform.hpp"
+//#include "../../../ovp/OVPStatusRegister.hpp"
+
+extern OVPPlatform ovpplatform;
+
+namespace sal {
+
+/**
+ * \class OVPRegister
+ * OVP-specific implementation of x86 registers.
+ */
+class OVPRegister : public Register
+{
+	private:
+		void *reg;
+
+	public:
+		/**
+		 * Constructs a new register object.
+		 * @param id the unique id of this register (simulator specific)
+		 * @param width width of the register (8, 16, 32 or 64 bit should suffice)
+		 * @param link pointer to bochs internal register memory
+		 * @param t type of the register
+		 */
+		OVPRegister(unsigned int id, regwidth_t width, void* link, RegisterType t)
+			: Register(id, t, width) { 
+			reg = link;
+		}
+		/**
+		 * Retrieves the data of the register.
+		 * @return the current register data
+		 */
+		regdata_t getData() { return ovpplatform.getRegisterData(reg); }
+		/**
+		 * Sets the content of the register.
+		 * @param data the new register data to be written
+		 */
+		void setData(regdata_t data) { ovpplatform.setRegisterData(reg, data); }
+};
+
+/**
+ * \class OVPRegister
+ * OVP-specific implementation of the RegisterManager.
+ */
+class OVPRegisterManager : public RegisterManager
+{
+	public:
+		/**
+		 * Returns the current instruction pointer.
+		 * @return the current eip
+		 */
+		virtual address_t getInstructionPointer()
+		{
+			return ovpplatform.getPC();
+		}
+		/**
+		 * Retruns the top address of the stack.
+		 * @return the starting address of the stack
+		 */
+		virtual address_t getStackPointer()
+		{
+			return ovpplatform.getSP();
+		}
+		/**
+		 * Retrieves the base ptr (holding the address of the
+		 * current stack frame).
+		 * @return the base pointer
+		 */
+		virtual address_t getBasePointer()
+		{
+			return 0;
+		}
+
+};
+}
+#endif
--- a/core/SAL/ovp/init.ah
+++ b/core/SAL/ovp/init.ah
@ -0,0 +1,13 @@
+#ifndef __OVPINIT_AH__
+  #define __OVPINIT_AH__
+
+#include "../SALInst.hpp"
+
+aspect OVPInit {
+	advice call("% ...::startSimulation(...)") : before () {
+		cout << "OVP init aspect!" << endl;
+		sal::simulator.startup();
+	}
+};
+
+#endif // __OVPINIT_AH__