Adding gem5 source to svn.
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1819 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
This commit is contained in:
friemel
@ -0,0 +1,962 @@
|
||||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
full_system=false
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000
|
||||
time_sync_spin_threshold=100000
|
||||
|
||||
[system]
|
||||
type=System
|
||||
children=cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 dir_cntrl0 funcmem l1_cntrl0 l1_cntrl1 l1_cntrl2 l1_cntrl3 l1_cntrl4 l1_cntrl5 l1_cntrl6 l1_cntrl7 l2_cntrl0 physmem ruby sys_port_proxy
|
||||
boot_osflags=a
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
mem_mode=timing
|
||||
memories=system.funcmem system.physmem
|
||||
num_work_ids=16
|
||||
readfile=
|
||||
symbolfile=
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.sys_port_proxy.slave[0]
|
||||
|
||||
[system.cpu0]
|
||||
type=MemTest
|
||||
atomic=false
|
||||
issue_dmas=false
|
||||
max_loads=100000
|
||||
memory_size=65536
|
||||
percent_dest_unaligned=50
|
||||
percent_functional=50
|
||||
percent_reads=65
|
||||
percent_source_unaligned=50
|
||||
percent_uncacheable=0
|
||||
progress_interval=10000
|
||||
suppress_func_warnings=true
|
||||
sys=system
|
||||
trace_addr=0
|
||||
functional=system.funcmem.port[0]
|
||||
test=system.l1_cntrl0.sequencer.slave[0]
|
||||
|
||||
[system.cpu1]
|
||||
type=MemTest
|
||||
atomic=false
|
||||
issue_dmas=false
|
||||
max_loads=100000
|
||||
memory_size=65536
|
||||
percent_dest_unaligned=50
|
||||
percent_functional=50
|
||||
percent_reads=65
|
||||
percent_source_unaligned=50
|
||||
percent_uncacheable=0
|
||||
progress_interval=10000
|
||||
suppress_func_warnings=true
|
||||
sys=system
|
||||
trace_addr=0
|
||||
functional=system.funcmem.port[1]
|
||||
test=system.l1_cntrl1.sequencer.slave[0]
|
||||
|
||||
[system.cpu2]
|
||||
type=MemTest
|
||||
atomic=false
|
||||
issue_dmas=false
|
||||
max_loads=100000
|
||||
memory_size=65536
|
||||
percent_dest_unaligned=50
|
||||
percent_functional=50
|
||||
percent_reads=65
|
||||
percent_source_unaligned=50
|
||||
percent_uncacheable=0
|
||||
progress_interval=10000
|
||||
suppress_func_warnings=true
|
||||
sys=system
|
||||
trace_addr=0
|
||||
functional=system.funcmem.port[2]
|
||||
test=system.l1_cntrl2.sequencer.slave[0]
|
||||
|
||||
[system.cpu3]
|
||||
type=MemTest
|
||||
atomic=false
|
||||
issue_dmas=false
|
||||
max_loads=100000
|
||||
memory_size=65536
|
||||
percent_dest_unaligned=50
|
||||
percent_functional=50
|
||||
percent_reads=65
|
||||
percent_source_unaligned=50
|
||||
percent_uncacheable=0
|
||||
progress_interval=10000
|
||||
suppress_func_warnings=true
|
||||
sys=system
|
||||
trace_addr=0
|
||||
functional=system.funcmem.port[3]
|
||||
test=system.l1_cntrl3.sequencer.slave[0]
|
||||
|
||||
[system.cpu4]
|
||||
type=MemTest
|
||||
atomic=false
|
||||
issue_dmas=false
|
||||
max_loads=100000
|
||||
memory_size=65536
|
||||
percent_dest_unaligned=50
|
||||
percent_functional=50
|
||||
percent_reads=65
|
||||
percent_source_unaligned=50
|
||||
percent_uncacheable=0
|
||||
progress_interval=10000
|
||||
suppress_func_warnings=true
|
||||
sys=system
|
||||
trace_addr=0
|
||||
functional=system.funcmem.port[4]
|
||||
test=system.l1_cntrl4.sequencer.slave[0]
|
||||
|
||||
[system.cpu5]
|
||||
type=MemTest
|
||||
atomic=false
|
||||
issue_dmas=false
|
||||
max_loads=100000
|
||||
memory_size=65536
|
||||
percent_dest_unaligned=50
|
||||
percent_functional=50
|
||||
percent_reads=65
|
||||
percent_source_unaligned=50
|
||||
percent_uncacheable=0
|
||||
progress_interval=10000
|
||||
suppress_func_warnings=true
|
||||
sys=system
|
||||
trace_addr=0
|
||||
functional=system.funcmem.port[5]
|
||||
test=system.l1_cntrl5.sequencer.slave[0]
|
||||
|
||||
[system.cpu6]
|
||||
type=MemTest
|
||||
atomic=false
|
||||
issue_dmas=false
|
||||
max_loads=100000
|
||||
memory_size=65536
|
||||
percent_dest_unaligned=50
|
||||
percent_functional=50
|
||||
percent_reads=65
|
||||
percent_source_unaligned=50
|
||||
percent_uncacheable=0
|
||||
progress_interval=10000
|
||||
suppress_func_warnings=true
|
||||
sys=system
|
||||
trace_addr=0
|
||||
functional=system.funcmem.port[6]
|
||||
test=system.l1_cntrl6.sequencer.slave[0]
|
||||
|
||||
[system.cpu7]
|
||||
type=MemTest
|
||||
atomic=false
|
||||
issue_dmas=false
|
||||
max_loads=100000
|
||||
memory_size=65536
|
||||
percent_dest_unaligned=50
|
||||
percent_functional=50
|
||||
percent_reads=65
|
||||
percent_source_unaligned=50
|
||||
percent_uncacheable=0
|
||||
progress_interval=10000
|
||||
suppress_func_warnings=true
|
||||
sys=system
|
||||
trace_addr=0
|
||||
functional=system.funcmem.port[7]
|
||||
test=system.l1_cntrl7.sequencer.slave[0]
|
||||
|
||||
[system.dir_cntrl0]
|
||||
type=Directory_Controller
|
||||
children=directory memBuffer
|
||||
buffer_size=0
|
||||
cntrl_id=9
|
||||
directory=system.dir_cntrl0.directory
|
||||
directory_latency=6
|
||||
memBuffer=system.dir_cntrl0.memBuffer
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
ruby_system=system.ruby
|
||||
to_mem_ctrl_latency=1
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.dir_cntrl0.directory]
|
||||
type=RubyDirectoryMemory
|
||||
map_levels=4
|
||||
numa_high_bit=6
|
||||
size=268435456
|
||||
use_map=false
|
||||
version=0
|
||||
|
||||
[system.dir_cntrl0.memBuffer]
|
||||
type=RubyMemoryControl
|
||||
bank_bit_0=8
|
||||
bank_busy_time=11
|
||||
bank_queue_size=12
|
||||
banks_per_rank=8
|
||||
basic_bus_busy_time=2
|
||||
dimm_bit_0=12
|
||||
dimms_per_channel=2
|
||||
mem_bus_cycle_multiplier=10
|
||||
mem_ctl_latency=12
|
||||
mem_fixed_delay=0
|
||||
mem_random_arbitrate=0
|
||||
rank_bit_0=11
|
||||
rank_rank_delay=1
|
||||
ranks_per_dimm=2
|
||||
read_write_delay=2
|
||||
refresh_period=1560
|
||||
tFaw=0
|
||||
version=0
|
||||
|
||||
[system.funcmem]
|
||||
type=SimpleMemory
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=false
|
||||
latency=30
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.cpu0.functional system.cpu1.functional system.cpu2.functional system.cpu3.functional system.cpu4.functional system.cpu5.functional system.cpu6.functional system.cpu7.functional
|
||||
|
||||
[system.l1_cntrl0]
|
||||
type=L1Cache_Controller
|
||||
children=L1DcacheMemory L1IcacheMemory sequencer
|
||||
L1DcacheMemory=system.l1_cntrl0.L1DcacheMemory
|
||||
L1IcacheMemory=system.l1_cntrl0.L1IcacheMemory
|
||||
buffer_size=0
|
||||
cntrl_id=0
|
||||
l1_request_latency=2
|
||||
l1_response_latency=2
|
||||
l2_select_num_bits=0
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
ruby_system=system.ruby
|
||||
send_evictions=false
|
||||
sequencer=system.l1_cntrl0.sequencer
|
||||
to_l2_latency=1
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.l1_cntrl0.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
is_icache=false
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl0.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
is_icache=false
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl0.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=false
|
||||
dcache=system.l1_cntrl0.L1DcacheMemory
|
||||
deadlock_threshold=1000000
|
||||
icache=system.l1_cntrl0.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
ruby_system=system.ruby
|
||||
support_data_reqs=true
|
||||
support_inst_reqs=true
|
||||
system=system
|
||||
using_network_tester=false
|
||||
using_ruby_tester=false
|
||||
version=0
|
||||
slave=system.cpu0.test
|
||||
|
||||
[system.l1_cntrl1]
|
||||
type=L1Cache_Controller
|
||||
children=L1DcacheMemory L1IcacheMemory sequencer
|
||||
L1DcacheMemory=system.l1_cntrl1.L1DcacheMemory
|
||||
L1IcacheMemory=system.l1_cntrl1.L1IcacheMemory
|
||||
buffer_size=0
|
||||
cntrl_id=1
|
||||
l1_request_latency=2
|
||||
l1_response_latency=2
|
||||
l2_select_num_bits=0
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
ruby_system=system.ruby
|
||||
send_evictions=false
|
||||
sequencer=system.l1_cntrl1.sequencer
|
||||
to_l2_latency=1
|
||||
transitions_per_cycle=32
|
||||
version=1
|
||||
|
||||
[system.l1_cntrl1.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
is_icache=false
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl1.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
is_icache=false
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl1.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=false
|
||||
dcache=system.l1_cntrl1.L1DcacheMemory
|
||||
deadlock_threshold=1000000
|
||||
icache=system.l1_cntrl1.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
ruby_system=system.ruby
|
||||
support_data_reqs=true
|
||||
support_inst_reqs=true
|
||||
system=system
|
||||
using_network_tester=false
|
||||
using_ruby_tester=false
|
||||
version=1
|
||||
slave=system.cpu1.test
|
||||
|
||||
[system.l1_cntrl2]
|
||||
type=L1Cache_Controller
|
||||
children=L1DcacheMemory L1IcacheMemory sequencer
|
||||
L1DcacheMemory=system.l1_cntrl2.L1DcacheMemory
|
||||
L1IcacheMemory=system.l1_cntrl2.L1IcacheMemory
|
||||
buffer_size=0
|
||||
cntrl_id=2
|
||||
l1_request_latency=2
|
||||
l1_response_latency=2
|
||||
l2_select_num_bits=0
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
ruby_system=system.ruby
|
||||
send_evictions=false
|
||||
sequencer=system.l1_cntrl2.sequencer
|
||||
to_l2_latency=1
|
||||
transitions_per_cycle=32
|
||||
version=2
|
||||
|
||||
[system.l1_cntrl2.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
is_icache=false
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl2.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
is_icache=false
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl2.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=false
|
||||
dcache=system.l1_cntrl2.L1DcacheMemory
|
||||
deadlock_threshold=1000000
|
||||
icache=system.l1_cntrl2.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
ruby_system=system.ruby
|
||||
support_data_reqs=true
|
||||
support_inst_reqs=true
|
||||
system=system
|
||||
using_network_tester=false
|
||||
using_ruby_tester=false
|
||||
version=2
|
||||
slave=system.cpu2.test
|
||||
|
||||
[system.l1_cntrl3]
|
||||
type=L1Cache_Controller
|
||||
children=L1DcacheMemory L1IcacheMemory sequencer
|
||||
L1DcacheMemory=system.l1_cntrl3.L1DcacheMemory
|
||||
L1IcacheMemory=system.l1_cntrl3.L1IcacheMemory
|
||||
buffer_size=0
|
||||
cntrl_id=3
|
||||
l1_request_latency=2
|
||||
l1_response_latency=2
|
||||
l2_select_num_bits=0
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
ruby_system=system.ruby
|
||||
send_evictions=false
|
||||
sequencer=system.l1_cntrl3.sequencer
|
||||
to_l2_latency=1
|
||||
transitions_per_cycle=32
|
||||
version=3
|
||||
|
||||
[system.l1_cntrl3.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
is_icache=false
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl3.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
is_icache=false
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl3.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=false
|
||||
dcache=system.l1_cntrl3.L1DcacheMemory
|
||||
deadlock_threshold=1000000
|
||||
icache=system.l1_cntrl3.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
ruby_system=system.ruby
|
||||
support_data_reqs=true
|
||||
support_inst_reqs=true
|
||||
system=system
|
||||
using_network_tester=false
|
||||
using_ruby_tester=false
|
||||
version=3
|
||||
slave=system.cpu3.test
|
||||
|
||||
[system.l1_cntrl4]
|
||||
type=L1Cache_Controller
|
||||
children=L1DcacheMemory L1IcacheMemory sequencer
|
||||
L1DcacheMemory=system.l1_cntrl4.L1DcacheMemory
|
||||
L1IcacheMemory=system.l1_cntrl4.L1IcacheMemory
|
||||
buffer_size=0
|
||||
cntrl_id=4
|
||||
l1_request_latency=2
|
||||
l1_response_latency=2
|
||||
l2_select_num_bits=0
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
ruby_system=system.ruby
|
||||
send_evictions=false
|
||||
sequencer=system.l1_cntrl4.sequencer
|
||||
to_l2_latency=1
|
||||
transitions_per_cycle=32
|
||||
version=4
|
||||
|
||||
[system.l1_cntrl4.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
is_icache=false
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl4.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
is_icache=false
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl4.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=false
|
||||
dcache=system.l1_cntrl4.L1DcacheMemory
|
||||
deadlock_threshold=1000000
|
||||
icache=system.l1_cntrl4.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
ruby_system=system.ruby
|
||||
support_data_reqs=true
|
||||
support_inst_reqs=true
|
||||
system=system
|
||||
using_network_tester=false
|
||||
using_ruby_tester=false
|
||||
version=4
|
||||
slave=system.cpu4.test
|
||||
|
||||
[system.l1_cntrl5]
|
||||
type=L1Cache_Controller
|
||||
children=L1DcacheMemory L1IcacheMemory sequencer
|
||||
L1DcacheMemory=system.l1_cntrl5.L1DcacheMemory
|
||||
L1IcacheMemory=system.l1_cntrl5.L1IcacheMemory
|
||||
buffer_size=0
|
||||
cntrl_id=5
|
||||
l1_request_latency=2
|
||||
l1_response_latency=2
|
||||
l2_select_num_bits=0
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
ruby_system=system.ruby
|
||||
send_evictions=false
|
||||
sequencer=system.l1_cntrl5.sequencer
|
||||
to_l2_latency=1
|
||||
transitions_per_cycle=32
|
||||
version=5
|
||||
|
||||
[system.l1_cntrl5.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
is_icache=false
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl5.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
is_icache=false
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl5.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=false
|
||||
dcache=system.l1_cntrl5.L1DcacheMemory
|
||||
deadlock_threshold=1000000
|
||||
icache=system.l1_cntrl5.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
ruby_system=system.ruby
|
||||
support_data_reqs=true
|
||||
support_inst_reqs=true
|
||||
system=system
|
||||
using_network_tester=false
|
||||
using_ruby_tester=false
|
||||
version=5
|
||||
slave=system.cpu5.test
|
||||
|
||||
[system.l1_cntrl6]
|
||||
type=L1Cache_Controller
|
||||
children=L1DcacheMemory L1IcacheMemory sequencer
|
||||
L1DcacheMemory=system.l1_cntrl6.L1DcacheMemory
|
||||
L1IcacheMemory=system.l1_cntrl6.L1IcacheMemory
|
||||
buffer_size=0
|
||||
cntrl_id=6
|
||||
l1_request_latency=2
|
||||
l1_response_latency=2
|
||||
l2_select_num_bits=0
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
ruby_system=system.ruby
|
||||
send_evictions=false
|
||||
sequencer=system.l1_cntrl6.sequencer
|
||||
to_l2_latency=1
|
||||
transitions_per_cycle=32
|
||||
version=6
|
||||
|
||||
[system.l1_cntrl6.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
is_icache=false
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl6.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
is_icache=false
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl6.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=false
|
||||
dcache=system.l1_cntrl6.L1DcacheMemory
|
||||
deadlock_threshold=1000000
|
||||
icache=system.l1_cntrl6.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
ruby_system=system.ruby
|
||||
support_data_reqs=true
|
||||
support_inst_reqs=true
|
||||
system=system
|
||||
using_network_tester=false
|
||||
using_ruby_tester=false
|
||||
version=6
|
||||
slave=system.cpu6.test
|
||||
|
||||
[system.l1_cntrl7]
|
||||
type=L1Cache_Controller
|
||||
children=L1DcacheMemory L1IcacheMemory sequencer
|
||||
L1DcacheMemory=system.l1_cntrl7.L1DcacheMemory
|
||||
L1IcacheMemory=system.l1_cntrl7.L1IcacheMemory
|
||||
buffer_size=0
|
||||
cntrl_id=7
|
||||
l1_request_latency=2
|
||||
l1_response_latency=2
|
||||
l2_select_num_bits=0
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
ruby_system=system.ruby
|
||||
send_evictions=false
|
||||
sequencer=system.l1_cntrl7.sequencer
|
||||
to_l2_latency=1
|
||||
transitions_per_cycle=32
|
||||
version=7
|
||||
|
||||
[system.l1_cntrl7.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
is_icache=false
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl7.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
is_icache=false
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl7.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=false
|
||||
dcache=system.l1_cntrl7.L1DcacheMemory
|
||||
deadlock_threshold=1000000
|
||||
icache=system.l1_cntrl7.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
ruby_system=system.ruby
|
||||
support_data_reqs=true
|
||||
support_inst_reqs=true
|
||||
system=system
|
||||
using_network_tester=false
|
||||
using_ruby_tester=false
|
||||
version=7
|
||||
slave=system.cpu7.test
|
||||
|
||||
[system.l2_cntrl0]
|
||||
type=L2Cache_Controller
|
||||
children=L2cacheMemory
|
||||
L2cacheMemory=system.l2_cntrl0.L2cacheMemory
|
||||
buffer_size=0
|
||||
cntrl_id=8
|
||||
l2_request_latency=2
|
||||
l2_response_latency=2
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
ruby_system=system.ruby
|
||||
to_l1_latency=1
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.l2_cntrl0.L2cacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
is_icache=false
|
||||
latency=15
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=512
|
||||
start_index_bit=6
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=30
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
|
||||
[system.ruby]
|
||||
type=RubySystem
|
||||
children=network profiler
|
||||
block_size_bytes=64
|
||||
clock=1
|
||||
mem_size=268435456
|
||||
no_mem_vec=false
|
||||
random_seed=1234
|
||||
randomization=false
|
||||
stats_filename=ruby.stats
|
||||
|
||||
[system.ruby.network]
|
||||
type=SimpleNetwork
|
||||
children=topology
|
||||
adaptive_routing=false
|
||||
buffer_size=0
|
||||
control_msg_size=8
|
||||
endpoint_bandwidth=1000
|
||||
number_of_virtual_networks=10
|
||||
ruby_system=system.ruby
|
||||
topology=system.ruby.network.topology
|
||||
|
||||
[system.ruby.network.topology]
|
||||
type=Topology
|
||||
children=ext_links0 ext_links1 ext_links2 ext_links3 ext_links4 ext_links5 ext_links6 ext_links7 ext_links8 ext_links9 int_links0 int_links1 int_links2 int_links3 int_links4 int_links5 int_links6 int_links7 int_links8 int_links9 routers00 routers01 routers02 routers03 routers04 routers05 routers06 routers07 routers08 routers09 routers10
|
||||
description=Crossbar
|
||||
ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2 system.ruby.network.topology.ext_links3 system.ruby.network.topology.ext_links4 system.ruby.network.topology.ext_links5 system.ruby.network.topology.ext_links6 system.ruby.network.topology.ext_links7 system.ruby.network.topology.ext_links8 system.ruby.network.topology.ext_links9
|
||||
int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2 system.ruby.network.topology.int_links3 system.ruby.network.topology.int_links4 system.ruby.network.topology.int_links5 system.ruby.network.topology.int_links6 system.ruby.network.topology.int_links7 system.ruby.network.topology.int_links8 system.ruby.network.topology.int_links9
|
||||
print_config=false
|
||||
routers=system.ruby.network.topology.routers00 system.ruby.network.topology.routers01 system.ruby.network.topology.routers02 system.ruby.network.topology.routers03 system.ruby.network.topology.routers04 system.ruby.network.topology.routers05 system.ruby.network.topology.routers06 system.ruby.network.topology.routers07 system.ruby.network.topology.routers08 system.ruby.network.topology.routers09 system.ruby.network.topology.routers10
|
||||
|
||||
[system.ruby.network.topology.ext_links0]
|
||||
type=SimpleExtLink
|
||||
bandwidth_factor=16
|
||||
ext_node=system.l1_cntrl0
|
||||
int_node=system.ruby.network.topology.routers00
|
||||
latency=1
|
||||
link_id=0
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links1]
|
||||
type=SimpleExtLink
|
||||
bandwidth_factor=16
|
||||
ext_node=system.l1_cntrl1
|
||||
int_node=system.ruby.network.topology.routers01
|
||||
latency=1
|
||||
link_id=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links2]
|
||||
type=SimpleExtLink
|
||||
bandwidth_factor=16
|
||||
ext_node=system.l1_cntrl2
|
||||
int_node=system.ruby.network.topology.routers02
|
||||
latency=1
|
||||
link_id=2
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links3]
|
||||
type=SimpleExtLink
|
||||
bandwidth_factor=16
|
||||
ext_node=system.l1_cntrl3
|
||||
int_node=system.ruby.network.topology.routers03
|
||||
latency=1
|
||||
link_id=3
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links4]
|
||||
type=SimpleExtLink
|
||||
bandwidth_factor=16
|
||||
ext_node=system.l1_cntrl4
|
||||
int_node=system.ruby.network.topology.routers04
|
||||
latency=1
|
||||
link_id=4
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links5]
|
||||
type=SimpleExtLink
|
||||
bandwidth_factor=16
|
||||
ext_node=system.l1_cntrl5
|
||||
int_node=system.ruby.network.topology.routers05
|
||||
latency=1
|
||||
link_id=5
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links6]
|
||||
type=SimpleExtLink
|
||||
bandwidth_factor=16
|
||||
ext_node=system.l1_cntrl6
|
||||
int_node=system.ruby.network.topology.routers06
|
||||
latency=1
|
||||
link_id=6
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links7]
|
||||
type=SimpleExtLink
|
||||
bandwidth_factor=16
|
||||
ext_node=system.l1_cntrl7
|
||||
int_node=system.ruby.network.topology.routers07
|
||||
latency=1
|
||||
link_id=7
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links8]
|
||||
type=SimpleExtLink
|
||||
bandwidth_factor=16
|
||||
ext_node=system.l2_cntrl0
|
||||
int_node=system.ruby.network.topology.routers08
|
||||
latency=1
|
||||
link_id=8
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links9]
|
||||
type=SimpleExtLink
|
||||
bandwidth_factor=16
|
||||
ext_node=system.dir_cntrl0
|
||||
int_node=system.ruby.network.topology.routers09
|
||||
latency=1
|
||||
link_id=9
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.int_links0]
|
||||
type=SimpleIntLink
|
||||
bandwidth_factor=16
|
||||
latency=1
|
||||
link_id=10
|
||||
node_a=system.ruby.network.topology.routers00
|
||||
node_b=system.ruby.network.topology.routers10
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.int_links1]
|
||||
type=SimpleIntLink
|
||||
bandwidth_factor=16
|
||||
latency=1
|
||||
link_id=11
|
||||
node_a=system.ruby.network.topology.routers01
|
||||
node_b=system.ruby.network.topology.routers10
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.int_links2]
|
||||
type=SimpleIntLink
|
||||
bandwidth_factor=16
|
||||
latency=1
|
||||
link_id=12
|
||||
node_a=system.ruby.network.topology.routers02
|
||||
node_b=system.ruby.network.topology.routers10
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.int_links3]
|
||||
type=SimpleIntLink
|
||||
bandwidth_factor=16
|
||||
latency=1
|
||||
link_id=13
|
||||
node_a=system.ruby.network.topology.routers03
|
||||
node_b=system.ruby.network.topology.routers10
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.int_links4]
|
||||
type=SimpleIntLink
|
||||
bandwidth_factor=16
|
||||
latency=1
|
||||
link_id=14
|
||||
node_a=system.ruby.network.topology.routers04
|
||||
node_b=system.ruby.network.topology.routers10
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.int_links5]
|
||||
type=SimpleIntLink
|
||||
bandwidth_factor=16
|
||||
latency=1
|
||||
link_id=15
|
||||
node_a=system.ruby.network.topology.routers05
|
||||
node_b=system.ruby.network.topology.routers10
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.int_links6]
|
||||
type=SimpleIntLink
|
||||
bandwidth_factor=16
|
||||
latency=1
|
||||
link_id=16
|
||||
node_a=system.ruby.network.topology.routers06
|
||||
node_b=system.ruby.network.topology.routers10
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.int_links7]
|
||||
type=SimpleIntLink
|
||||
bandwidth_factor=16
|
||||
latency=1
|
||||
link_id=17
|
||||
node_a=system.ruby.network.topology.routers07
|
||||
node_b=system.ruby.network.topology.routers10
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.int_links8]
|
||||
type=SimpleIntLink
|
||||
bandwidth_factor=16
|
||||
latency=1
|
||||
link_id=18
|
||||
node_a=system.ruby.network.topology.routers08
|
||||
node_b=system.ruby.network.topology.routers10
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.int_links9]
|
||||
type=SimpleIntLink
|
||||
bandwidth_factor=16
|
||||
latency=1
|
||||
link_id=19
|
||||
node_a=system.ruby.network.topology.routers09
|
||||
node_b=system.ruby.network.topology.routers10
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.routers00]
|
||||
type=BasicRouter
|
||||
router_id=0
|
||||
|
||||
[system.ruby.network.topology.routers01]
|
||||
type=BasicRouter
|
||||
router_id=1
|
||||
|
||||
[system.ruby.network.topology.routers02]
|
||||
type=BasicRouter
|
||||
router_id=2
|
||||
|
||||
[system.ruby.network.topology.routers03]
|
||||
type=BasicRouter
|
||||
router_id=3
|
||||
|
||||
[system.ruby.network.topology.routers04]
|
||||
type=BasicRouter
|
||||
router_id=4
|
||||
|
||||
[system.ruby.network.topology.routers05]
|
||||
type=BasicRouter
|
||||
router_id=5
|
||||
|
||||
[system.ruby.network.topology.routers06]
|
||||
type=BasicRouter
|
||||
router_id=6
|
||||
|
||||
[system.ruby.network.topology.routers07]
|
||||
type=BasicRouter
|
||||
router_id=7
|
||||
|
||||
[system.ruby.network.topology.routers08]
|
||||
type=BasicRouter
|
||||
router_id=8
|
||||
|
||||
[system.ruby.network.topology.routers09]
|
||||
type=BasicRouter
|
||||
router_id=9
|
||||
|
||||
[system.ruby.network.topology.routers10]
|
||||
type=BasicRouter
|
||||
router_id=10
|
||||
|
||||
[system.ruby.profiler]
|
||||
type=RubyProfiler
|
||||
all_instructions=false
|
||||
hot_lines=false
|
||||
num_of_sequencers=8
|
||||
ruby_system=system.ruby
|
||||
|
||||
[system.sys_port_proxy]
|
||||
type=RubyPortProxy
|
||||
access_phys_mem=true
|
||||
ruby_system=system.ruby
|
||||
support_data_reqs=true
|
||||
support_inst_reqs=true
|
||||
system=system
|
||||
using_network_tester=false
|
||||
using_ruby_tester=false
|
||||
version=0
|
||||
slave=system.system_port
|
||||
|
||||
@ -0,0 +1,905 @@
|
||||
|
||||
================ Begin RubySystem Configuration Print ================
|
||||
|
||||
RubySystem config:
|
||||
random_seed: 1234
|
||||
randomization: 0
|
||||
cycle_period: 1
|
||||
block_size_bytes: 64
|
||||
block_size_bits: 6
|
||||
memory_size_bytes: 268435456
|
||||
memory_size_bits: 28
|
||||
|
||||
Network Configuration
|
||||
---------------------
|
||||
network: SIMPLE_NETWORK
|
||||
topology:
|
||||
|
||||
virtual_net_0: active, unordered
|
||||
virtual_net_1: active, unordered
|
||||
virtual_net_2: active, unordered
|
||||
virtual_net_3: inactive
|
||||
virtual_net_4: inactive
|
||||
virtual_net_5: inactive
|
||||
virtual_net_6: inactive
|
||||
virtual_net_7: inactive
|
||||
virtual_net_8: inactive
|
||||
virtual_net_9: inactive
|
||||
|
||||
|
||||
Profiler Configuration
|
||||
----------------------
|
||||
periodic_stats_period: 1000000
|
||||
|
||||
================ End RubySystem Configuration Print ================
|
||||
|
||||
|
||||
Real time: Jun/04/2012 14:41:50
|
||||
|
||||
Profiler Stats
|
||||
--------------
|
||||
Elapsed_time_in_seconds: 88
|
||||
Elapsed_time_in_minutes: 1.46667
|
||||
Elapsed_time_in_hours: 0.0244444
|
||||
Elapsed_time_in_days: 0.00101852
|
||||
|
||||
Virtual_time_in_seconds: 87.84
|
||||
Virtual_time_in_minutes: 1.464
|
||||
Virtual_time_in_hours: 0.0244
|
||||
Virtual_time_in_days: 0.00101667
|
||||
|
||||
Ruby_current_time: 22495354
|
||||
Ruby_start_time: 0
|
||||
Ruby_cycles: 22495354
|
||||
|
||||
mbytes_resident: 61.2852
|
||||
mbytes_total: 361.766
|
||||
resident_ratio: 0.169406
|
||||
|
||||
ruby_cycles_executed: [ 22495355 22495355 22495355 22495355 22495355 22495355 22495355 22495355 ]
|
||||
|
||||
Busy Controller Counts:
|
||||
L1Cache-0:0 L1Cache-1:0 L1Cache-2:0 L1Cache-3:0 L1Cache-4:0 L1Cache-5:0 L1Cache-6:0 L1Cache-7:0
|
||||
|
||||
L2Cache-0:0
|
||||
Directory-0:0
|
||||
|
||||
|
||||
Busy Bank Count:0
|
||||
|
||||
sequencer_requests_outstanding: [binsize: 1 max: 16 count: 613548 average: 15.9984 | standard deviation: 0.127148 | 0 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 613428 ]
|
||||
|
||||
All Non-Zero Cycle Demand Cache Accesses
|
||||
----------------------------------------
|
||||
miss_latency: [binsize: 128 max: 13760 count: 613420 average: 4693.39 | standard deviation: 2857.78 | 94 8107 8803 9224 9186 10525 10961 11442 11448 10498 11027 10528 10145 9544 8769 9370 9040 8741 8591 7835 8409 8244 8431 8001 7426 7941 7973 7817 7780 7113 7670 7647 7635 7776 6976 7610 7590 7484 7517 7019 7616 7463 7684 7795 7113 7764 7804 7992 7925 7546 8139 8147 8400 8208 7986 8390 8549 8426 8400 7693 8367 8205 8096 7773 6799 7277 6993 6893 6382 5460 5473 5204 4661 4177 3467 3327 2966 2573 2263 1761 1663 1326 1150 948 717 631 469 342 286 220 150 125 96 56 41 36 22 14 12 8 3 7 1 2 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_LD: [binsize: 128 max: 13760 count: 398461 average: 4689.46 | standard deviation: 2856.72 | 72 5284 5756 6047 6025 6856 7148 7398 7440 6842 7162 6943 6556 6164 5710 6049 5875 5695 5624 5114 5411 5296 5403 5181 4802 5110 5252 5041 5021 4659 5089 4909 4962 5082 4482 4914 4844 4859 4886 4553 4946 4845 4968 5042 4606 5005 5029 5181 5176 4969 5367 5331 5542 5351 5247 5408 5581 5501 5512 5015 5431 5333 5242 5034 4435 4767 4539 4418 4177 3498 3544 3320 2976 2691 2251 2175 1943 1649 1439 1171 1031 871 734 599 439 421 289 224 184 143 85 71 64 43 28 23 12 8 8 2 3 4 1 2 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_ST: [binsize: 128 max: 13020 count: 214959 average: 4700.66 | standard deviation: 2859.74 | 22 2823 3047 3177 3161 3669 3813 4044 4008 3656 3865 3585 3589 3380 3059 3321 3165 3046 2967 2721 2998 2948 3028 2820 2624 2831 2721 2776 2759 2454 2581 2738 2673 2694 2494 2696 2746 2625 2631 2466 2670 2618 2716 2753 2507 2759 2775 2811 2749 2577 2772 2816 2858 2857 2739 2982 2968 2925 2888 2678 2936 2872 2854 2739 2364 2510 2454 2475 2205 1962 1929 1884 1685 1486 1216 1152 1023 924 824 590 632 455 416 349 278 210 180 118 102 77 65 54 32 13 13 13 10 6 4 6 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_NULL: [binsize: 128 max: 13760 count: 613420 average: 4693.39 | standard deviation: 2857.78 | 94 8107 8803 9224 9186 10525 10961 11442 11448 10498 11027 10528 10145 9544 8769 9370 9040 8741 8591 7835 8409 8244 8431 8001 7426 7941 7973 7817 7780 7113 7670 7647 7635 7776 6976 7610 7590 7484 7517 7019 7616 7463 7684 7795 7113 7764 7804 7992 7925 7546 8139 8147 8400 8208 7986 8390 8549 8426 8400 7693 8367 8205 8096 7773 6799 7277 6993 6893 6382 5460 5473 5204 4661 4177 3467 3327 2966 2573 2263 1761 1663 1326 1150 948 717 631 469 342 286 220 150 125 96 56 41 36 22 14 12 8 3 7 1 2 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
imcomplete_wCC_Times: 0
|
||||
miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
imcomplete_dir_Times: 0
|
||||
miss_latency_LD_NULL: [binsize: 128 max: 13760 count: 398461 average: 4689.46 | standard deviation: 2856.72 | 72 5284 5756 6047 6025 6856 7148 7398 7440 6842 7162 6943 6556 6164 5710 6049 5875 5695 5624 5114 5411 5296 5403 5181 4802 5110 5252 5041 5021 4659 5089 4909 4962 5082 4482 4914 4844 4859 4886 4553 4946 4845 4968 5042 4606 5005 5029 5181 5176 4969 5367 5331 5542 5351 5247 5408 5581 5501 5512 5015 5431 5333 5242 5034 4435 4767 4539 4418 4177 3498 3544 3320 2976 2691 2251 2175 1943 1649 1439 1171 1031 871 734 599 439 421 289 224 184 143 85 71 64 43 28 23 12 8 8 2 3 4 1 2 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_ST_NULL: [binsize: 128 max: 13020 count: 214959 average: 4700.66 | standard deviation: 2859.74 | 22 2823 3047 3177 3161 3669 3813 4044 4008 3656 3865 3585 3589 3380 3059 3321 3165 3046 2967 2721 2998 2948 3028 2820 2624 2831 2721 2776 2759 2454 2581 2738 2673 2694 2494 2696 2746 2625 2631 2466 2670 2618 2716 2753 2507 2759 2775 2811 2749 2577 2772 2816 2858 2857 2739 2982 2968 2925 2888 2678 2936 2872 2854 2739 2364 2510 2454 2475 2205 1962 1929 1884 1685 1486 1216 1152 1023 924 824 590 632 455 416 349 278 210 180 118 102 77 65 54 32 13 13 13 10 6 4 6 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
|
||||
All Non-Zero Cycle SW Prefetch Requests
|
||||
------------------------------------
|
||||
prefetch_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
prefetch_latency_L2Miss:[binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
Request vs. RubySystem State Profile
|
||||
--------------------------------
|
||||
|
||||
|
||||
filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
||||
Message Delayed Cycles
|
||||
----------------------
|
||||
Total_delay_cycles: [binsize: 64 max: 3179 count: 4811273 average: 127.048 | standard deviation: 323.611 | 4016293 21294 31915 31760 34402 31903 33934 40187 38896 47238 41772 44405 51825 44867 51717 41964 38758 38516 28855 27620 18752 15150 13181 7952 6612 3942 2736 1881 1057 812 372 250 176 94 60 33 19 17 9 12 11 4 7 3 2 1 4 2 0 1 ]
|
||||
Total_nonPF_delay_cycles: [binsize: 1 max: 18 count: 3280807 average: 0.508064 | standard deviation: 1.45159 | 2800178 124575 22976 51320 209007 25390 4707 8014 22215 9190 1858 856 301 130 48 28 7 3 4 ]
|
||||
virtual_network_0_delay_cycles: [binsize: 64 max: 3179 count: 1530466 average: 398.307 | standard deviation: 470.433 | 735486 21294 31915 31760 34402 31903 33934 40187 38896 47238 41772 44405 51825 44867 51717 41964 38758 38516 28855 27620 18752 15150 13181 7952 6612 3942 2736 1881 1057 812 372 250 176 94 60 33 19 17 9 12 11 4 7 3 2 1 4 2 0 1 ]
|
||||
virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_2_delay_cycles: [binsize: 1 max: 16 count: 572178 average: 0.360678 | standard deviation: 1.02424 | 445954 97556 13301 3674 2800 3753 2193 365 365 226 1591 294 33 27 24 19 3 ]
|
||||
virtual_network_3_delay_cycles: [binsize: 1 max: 18 count: 2708629 average: 0.539198 | standard deviation: 1.52481 | 2354224 27019 9675 47646 206207 21637 2514 7649 21850 8964 267 562 268 103 24 9 4 3 4 ]
|
||||
virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_6_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_7_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_8_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_9_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
||||
Resource Usage
|
||||
--------------
|
||||
page_size: 4096
|
||||
user_time: 87
|
||||
system_time: 0
|
||||
page_reclaims: 16135
|
||||
page_faults: 0
|
||||
swaps: 0
|
||||
block_inputs: 0
|
||||
block_outputs: 216
|
||||
|
||||
Network Stats
|
||||
-------------
|
||||
|
||||
total_msg_count_Control: 3663942 29311536
|
||||
total_msg_count_Request_Control: 1712725 13701800
|
||||
total_msg_count_Response_Data: 4307603 310147416
|
||||
total_msg_count_Response_Control: 6353639 50829112
|
||||
total_msg_count_Writeback_Data: 1438122 103544784
|
||||
total_msg_count_Writeback_Control: 598632 4789056
|
||||
total_msgs: 18074663 total_bytes: 512323704
|
||||
|
||||
switch_0_inlinks: 2
|
||||
switch_0_outlinks: 2
|
||||
links_utilized_percent_switch_0: 1.71236
|
||||
links_utilized_percent_switch_0_link_0: 1.77334 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_0_link_1: 1.65137 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_0_link_0_Request_Control: 71340 570720 [ 71340 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Response_Data: 76457 5504904 [ 0 76457 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Response_Control: 38387 307096 [ 0 38387 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Control: 76459 611672 [ 76459 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Response_Data: 495 35640 [ 0 495 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Response_Control: 100727 805816 [ 0 24908 75819 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Writeback_Data: 59608 4291776 [ 13535 46073 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Writeback_Control: 24852 198816 [ 24852 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_1_inlinks: 2
|
||||
switch_1_outlinks: 2
|
||||
links_utilized_percent_switch_1: 1.72774
|
||||
links_utilized_percent_switch_1_link_0: 1.78626 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_1_link_1: 1.66922 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_1_link_0_Request_Control: 71710 573680 [ 71710 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Response_Data: 76990 5543280 [ 0 76990 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Response_Control: 39031 312248 [ 0 39031 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Control: 76993 615944 [ 76993 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Response_Data: 492 35424 [ 0 492 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Response_Control: 101090 808720 [ 0 24786 76304 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Writeback_Data: 60359 4345848 [ 13777 46582 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Writeback_Control: 25254 202032 [ 25254 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_2_inlinks: 2
|
||||
switch_2_outlinks: 2
|
||||
links_utilized_percent_switch_2: 1.71123
|
||||
links_utilized_percent_switch_2_link_0: 1.77117 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_2_link_1: 1.65128 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_2_link_0_Request_Control: 71363 570904 [ 71363 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Response_Data: 76359 5497848 [ 0 76359 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Response_Control: 38270 306160 [ 0 38270 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Control: 76362 610896 [ 76362 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Response_Data: 517 37224 [ 0 517 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Response_Control: 100631 805048 [ 0 24940 75691 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Writeback_Data: 59620 4292640 [ 13569 46051 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Writeback_Control: 24698 197584 [ 24698 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_3_inlinks: 2
|
||||
switch_3_outlinks: 2
|
||||
links_utilized_percent_switch_3: 1.72523
|
||||
links_utilized_percent_switch_3_link_0: 1.78279 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_3_link_1: 1.66767 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_3_link_0_Request_Control: 71726 573808 [ 71726 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_Response_Data: 76841 5532552 [ 0 76841 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_Response_Control: 38801 310408 [ 0 38801 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Control: 76842 614736 [ 76842 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Response_Data: 516 37152 [ 0 516 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Response_Control: 101063 808504 [ 0 24869 76194 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Writeback_Data: 60307 4342104 [ 13816 46491 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Writeback_Control: 24983 199864 [ 24983 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_4_inlinks: 2
|
||||
switch_4_outlinks: 2
|
||||
links_utilized_percent_switch_4: 1.70715
|
||||
links_utilized_percent_switch_4_link_0: 1.76795 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_4_link_1: 1.64635 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_4_link_0_Request_Control: 71024 568192 [ 71024 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_4_link_0_Response_Data: 76231 5488632 [ 0 76231 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_4_link_0_Response_Control: 38311 306488 [ 0 38311 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_4_link_1_Control: 76234 609872 [ 76234 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_4_link_1_Response_Data: 452 32544 [ 0 452 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_4_link_1_Response_Control: 100447 803576 [ 0 24896 75551 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_4_link_1_Writeback_Data: 59480 4282560 [ 13673 45807 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_4_link_1_Writeback_Control: 24637 197096 [ 24637 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_5_inlinks: 2
|
||||
switch_5_outlinks: 2
|
||||
links_utilized_percent_switch_5: 1.71406
|
||||
links_utilized_percent_switch_5_link_0: 1.77633 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_5_link_1: 1.65179 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_5_link_0_Request_Control: 71452 571616 [ 71452 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_0_Response_Data: 76590 5514480 [ 0 76590 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_0_Response_Control: 38423 307384 [ 0 38423 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_1_Control: 76593 612744 [ 76593 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_1_Response_Data: 489 35208 [ 0 489 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_1_Response_Control: 101169 809352 [ 0 25242 75927 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_1_Writeback_Data: 59588 4290336 [ 13727 45861 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_1_Writeback_Control: 24697 197576 [ 24697 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_6_inlinks: 2
|
||||
switch_6_outlinks: 2
|
||||
links_utilized_percent_switch_6: 1.72355
|
||||
links_utilized_percent_switch_6_link_0: 1.78407 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_6_link_1: 1.66303 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_6_link_0_Request_Control: 71663 573304 [ 71663 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_6_link_0_Response_Data: 76911 5537592 [ 0 76911 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_6_link_0_Response_Control: 38805 310440 [ 0 38805 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_6_link_1_Control: 76915 615320 [ 76915 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_6_link_1_Response_Data: 527 37944 [ 0 527 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_6_link_1_Response_Control: 101113 808904 [ 0 24886 76227 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_6_link_1_Writeback_Data: 60030 4322160 [ 13633 46397 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_6_link_1_Writeback_Control: 25170 201360 [ 25170 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_7_inlinks: 2
|
||||
switch_7_outlinks: 2
|
||||
links_utilized_percent_switch_7: 1.72847
|
||||
links_utilized_percent_switch_7_link_0: 1.78743 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_7_link_1: 1.66951 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_7_link_0_Request_Control: 71900 575200 [ 71900 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_7_link_0_Response_Data: 77033 5546376 [ 0 77033 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_7_link_0_Response_Control: 38982 311856 [ 0 38982 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_7_link_1_Control: 77037 616296 [ 77037 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_7_link_1_Response_Data: 460 33120 [ 0 460 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_7_link_1_Response_Control: 101258 810064 [ 0 24915 76343 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_7_link_1_Writeback_Data: 60382 4347504 [ 13729 46653 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_7_link_1_Writeback_Control: 25253 202024 [ 25253 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_8_inlinks: 2
|
||||
switch_8_outlinks: 2
|
||||
links_utilized_percent_switch_8: 23.6747
|
||||
links_utilized_percent_switch_8_link_0: 26.7248 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_8_link_1: 20.6245 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_8_link_0_Control: 613435 4907480 [ 613435 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_8_link_0_Response_Data: 609000 43848000 [ 0 609000 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_8_link_0_Response_Control: 1415348 11322784 [ 0 807292 608056 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_8_link_0_Writeback_Data: 479374 34514928 [ 109459 369915 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_8_link_0_Writeback_Control: 199544 1596352 [ 199544 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_8_link_1_Control: 607879 4863032 [ 607879 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_8_link_1_Request_Control: 568369 4546952 [ 568369 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_8_link_1_Response_Data: 822260 59202720 [ 0 822260 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_8_link_1_Response_Control: 702513 5620104 [ 0 702513 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_9_inlinks: 2
|
||||
switch_9_outlinks: 2
|
||||
links_utilized_percent_switch_9: 10.0124
|
||||
links_utilized_percent_switch_9_link_0: 6.51366 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_9_link_1: 13.5111 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_9_link_0_Control: 607879 4863032 [ 607879 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_0_Response_Data: 214349 15433128 [ 0 214349 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_0_Response_Control: 393521 3148168 [ 0 393521 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_1_Response_Data: 607873 43766856 [ 0 607873 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_1_Response_Control: 607869 4862952 [ 0 607869 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_10_inlinks: 10
|
||||
switch_10_outlinks: 10
|
||||
links_utilized_percent_switch_10: 4.74679
|
||||
links_utilized_percent_switch_10_link_0: 1.77334 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_10_link_1: 1.78626 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_10_link_2: 1.77117 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_10_link_3: 1.7828 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_10_link_4: 1.76795 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_10_link_5: 1.77633 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_10_link_6: 1.78407 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_10_link_7: 1.78743 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_10_link_8: 26.7248 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_10_link_9: 6.51366 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_10_link_0_Request_Control: 71340 570720 [ 71340 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_10_link_0_Response_Data: 76457 5504904 [ 0 76457 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_10_link_0_Response_Control: 38387 307096 [ 0 38387 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_10_link_1_Request_Control: 71710 573680 [ 71710 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_10_link_1_Response_Data: 76990 5543280 [ 0 76990 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_10_link_1_Response_Control: 39031 312248 [ 0 39031 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_10_link_2_Request_Control: 71363 570904 [ 71363 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_10_link_2_Response_Data: 76359 5497848 [ 0 76359 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_10_link_2_Response_Control: 38270 306160 [ 0 38270 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_10_link_3_Request_Control: 71726 573808 [ 71726 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_10_link_3_Response_Data: 76841 5532552 [ 0 76841 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_10_link_3_Response_Control: 38801 310408 [ 0 38801 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_10_link_4_Request_Control: 71024 568192 [ 71024 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_10_link_4_Response_Data: 76231 5488632 [ 0 76231 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_10_link_4_Response_Control: 38311 306488 [ 0 38311 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_10_link_5_Request_Control: 71452 571616 [ 71452 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_10_link_5_Response_Data: 76590 5514480 [ 0 76590 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_10_link_5_Response_Control: 38423 307384 [ 0 38423 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_10_link_6_Request_Control: 71663 573304 [ 71663 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_10_link_6_Response_Data: 76911 5537592 [ 0 76911 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_10_link_6_Response_Control: 38805 310440 [ 0 38805 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_10_link_7_Request_Control: 71900 575200 [ 71900 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_10_link_7_Response_Data: 77033 5546376 [ 0 77033 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_10_link_7_Response_Control: 38982 311856 [ 0 38982 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_10_link_8_Control: 613435 4907480 [ 613435 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_10_link_8_Response_Data: 609000 43848000 [ 0 609000 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_10_link_8_Response_Control: 1415349 11322792 [ 0 807293 608056 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_10_link_8_Writeback_Data: 479374 34514928 [ 109459 369915 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_10_link_8_Writeback_Control: 199544 1596352 [ 199544 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_10_link_9_Control: 607879 4863032 [ 607879 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_10_link_9_Response_Data: 214349 15433128 [ 0 214349 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_10_link_9_Response_Control: 393521 3148168 [ 0 393521 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
Cache Stats: system.l1_cntrl0.L1IcacheMemory
|
||||
system.l1_cntrl0.L1IcacheMemory_total_misses: 0
|
||||
system.l1_cntrl0.L1IcacheMemory_total_demand_misses: 0
|
||||
system.l1_cntrl0.L1IcacheMemory_total_prefetches: 0
|
||||
system.l1_cntrl0.L1IcacheMemory_total_sw_prefetches: 0
|
||||
system.l1_cntrl0.L1IcacheMemory_total_hw_prefetches: 0
|
||||
|
||||
|
||||
Cache Stats: system.l1_cntrl0.L1DcacheMemory
|
||||
system.l1_cntrl0.L1DcacheMemory_total_misses: 76459
|
||||
system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 76459
|
||||
system.l1_cntrl0.L1DcacheMemory_total_prefetches: 0
|
||||
system.l1_cntrl0.L1DcacheMemory_total_sw_prefetches: 0
|
||||
system.l1_cntrl0.L1DcacheMemory_total_hw_prefetches: 0
|
||||
|
||||
system.l1_cntrl0.L1DcacheMemory_request_type_LD: 65.0113%
|
||||
system.l1_cntrl0.L1DcacheMemory_request_type_ST: 34.9887%
|
||||
|
||||
system.l1_cntrl0.L1DcacheMemory_access_mode_type_Supervisor: 76459 100%
|
||||
|
||||
--- L1Cache ---
|
||||
- Event Counts -
|
||||
Load [49473 49872 49991 50118 49708 49965 49568 49786 ] 398481
|
||||
Ifetch [0 0 0 0 0 0 0 0 ] 0
|
||||
Store [26764 26724 26925 26923 26752 27029 26797 27058 ] 214972
|
||||
Inv [70703 71103 71283 71568 70981 71368 70991 71360 ] 569357
|
||||
L1_Replacement [522682 523116 525583 524399 523820 522840 522790 524027 ] 4189257
|
||||
Fwd_GETX [190 209 233 204 223 192 227 216 ] 1694
|
||||
Fwd_GETS [131 140 147 128 136 150 145 150 ] 1127
|
||||
Fwd_GET_INSTR [0 0 0 0 0 0 0 0 ] 0
|
||||
Data [1 1 2 1 0 1 2 1 ] 9
|
||||
Data_Exclusive [48660 49055 49156 49294 48937 49122 48757 48990 ] 391971
|
||||
DataS_fromL1 [129 151 148 128 130 153 141 147 ] 1127
|
||||
Data_all_Acks [27441 27383 27605 27610 27390 27714 27459 27703 ] 220305
|
||||
Ack [1 1 2 1 0 1 2 1 ] 9
|
||||
Ack_all [1 1 2 1 0 1 2 1 ] 9
|
||||
WB_Ack [38309 38421 38801 38980 38387 39029 38266 38799 ] 308992
|
||||
|
||||
- Transitions -
|
||||
NP Load [49459 49861 49979 50103 49696 49955 49563 49781 ] 398397
|
||||
NP Ifetch [0 0 0 0 0 0 0 0 ] 0
|
||||
NP Store [26759 26717 26921 26917 26747 27020 26791 27052 ] 214924
|
||||
NP Inv [382 408 406 403 399 408 401 395 ] 3202
|
||||
NP L1_Replacement [0 0 0 0 0 0 0 0 ] 0
|
||||
|
||||
I Load [12 10 11 11 11 9 4 3 ] 71
|
||||
I Ifetch [0 0 0 0 0 0 0 0 ] 0
|
||||
I Store [4 5 4 6 5 9 4 6 ] 43
|
||||
I Inv [0 0 0 0 0 0 0 0 ] 0
|
||||
I L1_Replacement [37572 37796 37742 37676 37704 37589 37732 37692 ] 301503
|
||||
|
||||
S Load [0 0 0 0 0 0 0 0 ] 0
|
||||
S Ifetch [0 0 0 0 0 0 0 0 ] 0
|
||||
S Store [0 0 0 0 0 0 0 0 ] 0
|
||||
S Inv [546 532 552 529 494 562 534 528 ] 4277
|
||||
S L1_Replacement [332 354 351 358 348 351 351 338 ] 2783
|
||||
|
||||
E Load [1 0 1 0 1 1 1 0 ] 5
|
||||
E Ifetch [0 0 0 0 0 0 0 0 ] 0
|
||||
E Store [0 0 0 0 0 0 0 0 ] 0
|
||||
E Inv [23956 24288 23907 23969 24004 23797 23986 23926 ] 191833
|
||||
E L1_Replacement [24637 24697 25170 25253 24852 25254 24698 24983 ] 199544
|
||||
E Fwd_GETX [54 60 70 62 72 60 66 71 ] 515
|
||||
E Fwd_GETS [13 10 9 10 9 10 7 9 ] 77
|
||||
E Fwd_GET_INSTR [0 0 0 0 0 0 0 0 ] 0
|
||||
|
||||
M Load [1 0 0 1 0 0 0 1 ] 3
|
||||
M Ifetch [0 0 0 0 0 0 0 0 ] 0
|
||||
M Store [0 0 0 0 0 0 0 0 ] 0
|
||||
M Inv [13006 12892 13186 13093 13118 13150 13113 13144 ] 104702
|
||||
M L1_Replacement [13673 13727 13633 13729 13535 13777 13569 13816 ] 109459
|
||||
M Fwd_GETX [27 40 42 40 34 38 42 34 ] 297
|
||||
M Fwd_GETS [56 62 62 59 65 64 69 64 ] 501
|
||||
M Fwd_GET_INSTR [0 0 0 0 0 0 0 0 ] 0
|
||||
|
||||
IS Load [0 0 0 0 0 0 0 0 ] 0
|
||||
IS Ifetch [0 0 0 0 0 0 0 0 ] 0
|
||||
IS Store [0 0 0 0 0 0 0 0 ] 0
|
||||
IS Inv [0 0 0 0 0 0 0 0 ] 0
|
||||
IS L1_Replacement [289783 289443 291226 290374 290759 288658 290058 288425 ] 2318726
|
||||
IS Data_Exclusive [48660 49055 49156 49294 48937 49122 48757 48990 ] 391971
|
||||
IS DataS_fromL1 [129 151 148 128 130 153 141 147 ] 1127
|
||||
IS Data_all_Acks [680 663 684 690 638 686 668 646 ] 5355
|
||||
|
||||
IM Load [0 0 0 0 0 0 0 0 ] 0
|
||||
IM Ifetch [0 0 0 0 0 0 0 0 ] 0
|
||||
IM Store [0 0 0 0 0 0 0 0 ] 0
|
||||
IM Inv [0 0 0 0 0 0 0 0 ] 0
|
||||
IM L1_Replacement [156685 157099 157461 157009 156622 157211 156382 158773 ] 1257242
|
||||
IM Data [1 1 2 1 0 1 2 1 ] 9
|
||||
IM Data_all_Acks [26761 26720 26921 26920 26752 27028 26791 27057 ] 214950
|
||||
IM Ack [0 0 0 0 0 0 0 0 ] 0
|
||||
|
||||
SM Load [0 0 0 0 0 0 0 0 ] 0
|
||||
SM Ifetch [0 0 0 0 0 0 0 0 ] 0
|
||||
SM Store [0 0 0 0 0 0 0 0 ] 0
|
||||
SM Inv [0 0 0 0 0 0 0 0 ] 0
|
||||
SM L1_Replacement [0 0 0 0 0 0 0 0 ] 0
|
||||
SM Ack [1 1 2 1 0 1 2 1 ] 9
|
||||
SM Ack_all [1 1 2 1 0 1 2 1 ] 9
|
||||
|
||||
IS_I Load [0 0 0 0 0 0 0 0 ] 0
|
||||
IS_I Ifetch [0 0 0 0 0 0 0 0 ] 0
|
||||
IS_I Store [0 0 0 0 0 0 0 0 ] 0
|
||||
IS_I Inv [0 0 0 0 0 0 0 0 ] 0
|
||||
IS_I L1_Replacement [0 0 0 0 0 0 0 0 ] 0
|
||||
IS_I Data_Exclusive [0 0 0 0 0 0 0 0 ] 0
|
||||
IS_I DataS_fromL1 [0 0 0 0 0 0 0 0 ] 0
|
||||
IS_I Data_all_Acks [0 0 0 0 0 0 0 0 ] 0
|
||||
|
||||
M_I Load [0 0 0 0 0 0 0 0 ] 0
|
||||
M_I Ifetch [0 0 0 0 0 0 0 0 ] 0
|
||||
M_I Store [0 0 0 0 0 0 0 0 ] 0
|
||||
M_I Inv [32801 32969 33211 33560 32955 33432 32938 33347 ] 265213
|
||||
M_I L1_Replacement [0 0 0 0 0 0 0 0 ] 0
|
||||
M_I Fwd_GETX [109 109 121 102 117 94 119 111 ] 882
|
||||
M_I Fwd_GETS [62 68 76 59 62 76 69 77 ] 549
|
||||
M_I Fwd_GET_INSTR [0 0 0 0 0 0 0 0 ] 0
|
||||
M_I WB_Ack [5338 5278 5395 5261 5253 5429 5141 5264 ] 42359
|
||||
|
||||
SINK_WB_ACK Load [0 1 0 3 0 0 0 1 ] 5
|
||||
SINK_WB_ACK Ifetch [0 0 0 0 0 0 0 0 ] 0
|
||||
SINK_WB_ACK Store [1 2 0 0 0 0 2 0 ] 5
|
||||
SINK_WB_ACK Inv [12 14 21 14 11 19 19 20 ] 130
|
||||
SINK_WB_ACK L1_Replacement [0 0 0 0 0 0 0 0 ] 0
|
||||
SINK_WB_ACK WB_Ack [32971 33143 33406 33719 33134 33600 33125 33535 ] 266633
|
||||
|
||||
Cache Stats: system.l1_cntrl1.L1IcacheMemory
|
||||
system.l1_cntrl1.L1IcacheMemory_total_misses: 0
|
||||
system.l1_cntrl1.L1IcacheMemory_total_demand_misses: 0
|
||||
system.l1_cntrl1.L1IcacheMemory_total_prefetches: 0
|
||||
system.l1_cntrl1.L1IcacheMemory_total_sw_prefetches: 0
|
||||
system.l1_cntrl1.L1IcacheMemory_total_hw_prefetches: 0
|
||||
|
||||
|
||||
Cache Stats: system.l1_cntrl1.L1DcacheMemory
|
||||
system.l1_cntrl1.L1DcacheMemory_total_misses: 76993
|
||||
system.l1_cntrl1.L1DcacheMemory_total_demand_misses: 76993
|
||||
system.l1_cntrl1.L1DcacheMemory_total_prefetches: 0
|
||||
system.l1_cntrl1.L1DcacheMemory_total_sw_prefetches: 0
|
||||
system.l1_cntrl1.L1DcacheMemory_total_hw_prefetches: 0
|
||||
|
||||
system.l1_cntrl1.L1DcacheMemory_request_type_LD: 64.8942%
|
||||
system.l1_cntrl1.L1DcacheMemory_request_type_ST: 35.1058%
|
||||
|
||||
system.l1_cntrl1.L1DcacheMemory_access_mode_type_Supervisor: 76993 100%
|
||||
|
||||
Cache Stats: system.l1_cntrl2.L1IcacheMemory
|
||||
system.l1_cntrl2.L1IcacheMemory_total_misses: 0
|
||||
system.l1_cntrl2.L1IcacheMemory_total_demand_misses: 0
|
||||
system.l1_cntrl2.L1IcacheMemory_total_prefetches: 0
|
||||
system.l1_cntrl2.L1IcacheMemory_total_sw_prefetches: 0
|
||||
system.l1_cntrl2.L1IcacheMemory_total_hw_prefetches: 0
|
||||
|
||||
|
||||
Cache Stats: system.l1_cntrl2.L1DcacheMemory
|
||||
system.l1_cntrl2.L1DcacheMemory_total_misses: 76362
|
||||
system.l1_cntrl2.L1DcacheMemory_total_demand_misses: 76362
|
||||
system.l1_cntrl2.L1DcacheMemory_total_prefetches: 0
|
||||
system.l1_cntrl2.L1DcacheMemory_total_sw_prefetches: 0
|
||||
system.l1_cntrl2.L1DcacheMemory_total_hw_prefetches: 0
|
||||
|
||||
system.l1_cntrl2.L1DcacheMemory_request_type_LD: 64.9106%
|
||||
system.l1_cntrl2.L1DcacheMemory_request_type_ST: 35.0894%
|
||||
|
||||
system.l1_cntrl2.L1DcacheMemory_access_mode_type_Supervisor: 76362 100%
|
||||
|
||||
Cache Stats: system.l1_cntrl3.L1IcacheMemory
|
||||
system.l1_cntrl3.L1IcacheMemory_total_misses: 0
|
||||
system.l1_cntrl3.L1IcacheMemory_total_demand_misses: 0
|
||||
system.l1_cntrl3.L1IcacheMemory_total_prefetches: 0
|
||||
system.l1_cntrl3.L1IcacheMemory_total_sw_prefetches: 0
|
||||
system.l1_cntrl3.L1IcacheMemory_total_hw_prefetches: 0
|
||||
|
||||
|
||||
Cache Stats: system.l1_cntrl3.L1DcacheMemory
|
||||
system.l1_cntrl3.L1DcacheMemory_total_misses: 76842
|
||||
system.l1_cntrl3.L1DcacheMemory_total_demand_misses: 76842
|
||||
system.l1_cntrl3.L1DcacheMemory_total_prefetches: 0
|
||||
system.l1_cntrl3.L1DcacheMemory_total_sw_prefetches: 0
|
||||
system.l1_cntrl3.L1DcacheMemory_total_hw_prefetches: 0
|
||||
|
||||
system.l1_cntrl3.L1DcacheMemory_request_type_LD: 64.7875%
|
||||
system.l1_cntrl3.L1DcacheMemory_request_type_ST: 35.2125%
|
||||
|
||||
system.l1_cntrl3.L1DcacheMemory_access_mode_type_Supervisor: 76842 100%
|
||||
|
||||
Cache Stats: system.l1_cntrl4.L1IcacheMemory
|
||||
system.l1_cntrl4.L1IcacheMemory_total_misses: 0
|
||||
system.l1_cntrl4.L1IcacheMemory_total_demand_misses: 0
|
||||
system.l1_cntrl4.L1IcacheMemory_total_prefetches: 0
|
||||
system.l1_cntrl4.L1IcacheMemory_total_sw_prefetches: 0
|
||||
system.l1_cntrl4.L1IcacheMemory_total_hw_prefetches: 0
|
||||
|
||||
|
||||
Cache Stats: system.l1_cntrl4.L1DcacheMemory
|
||||
system.l1_cntrl4.L1DcacheMemory_total_misses: 76234
|
||||
system.l1_cntrl4.L1DcacheMemory_total_demand_misses: 76234
|
||||
system.l1_cntrl4.L1DcacheMemory_total_prefetches: 0
|
||||
system.l1_cntrl4.L1DcacheMemory_total_sw_prefetches: 0
|
||||
system.l1_cntrl4.L1DcacheMemory_total_hw_prefetches: 0
|
||||
|
||||
system.l1_cntrl4.L1DcacheMemory_request_type_LD: 64.8936%
|
||||
system.l1_cntrl4.L1DcacheMemory_request_type_ST: 35.1064%
|
||||
|
||||
system.l1_cntrl4.L1DcacheMemory_access_mode_type_Supervisor: 76234 100%
|
||||
|
||||
Cache Stats: system.l1_cntrl5.L1IcacheMemory
|
||||
system.l1_cntrl5.L1IcacheMemory_total_misses: 0
|
||||
system.l1_cntrl5.L1IcacheMemory_total_demand_misses: 0
|
||||
system.l1_cntrl5.L1IcacheMemory_total_prefetches: 0
|
||||
system.l1_cntrl5.L1IcacheMemory_total_sw_prefetches: 0
|
||||
system.l1_cntrl5.L1IcacheMemory_total_hw_prefetches: 0
|
||||
|
||||
|
||||
Cache Stats: system.l1_cntrl5.L1DcacheMemory
|
||||
system.l1_cntrl5.L1DcacheMemory_total_misses: 76593
|
||||
system.l1_cntrl5.L1DcacheMemory_total_demand_misses: 76593
|
||||
system.l1_cntrl5.L1DcacheMemory_total_prefetches: 0
|
||||
system.l1_cntrl5.L1DcacheMemory_total_sw_prefetches: 0
|
||||
system.l1_cntrl5.L1DcacheMemory_total_hw_prefetches: 0
|
||||
|
||||
system.l1_cntrl5.L1DcacheMemory_request_type_LD: 65.1117%
|
||||
system.l1_cntrl5.L1DcacheMemory_request_type_ST: 34.8883%
|
||||
|
||||
system.l1_cntrl5.L1DcacheMemory_access_mode_type_Supervisor: 76593 100%
|
||||
|
||||
Cache Stats: system.l1_cntrl6.L1IcacheMemory
|
||||
system.l1_cntrl6.L1IcacheMemory_total_misses: 0
|
||||
system.l1_cntrl6.L1IcacheMemory_total_demand_misses: 0
|
||||
system.l1_cntrl6.L1IcacheMemory_total_prefetches: 0
|
||||
system.l1_cntrl6.L1IcacheMemory_total_sw_prefetches: 0
|
||||
system.l1_cntrl6.L1IcacheMemory_total_hw_prefetches: 0
|
||||
|
||||
|
||||
Cache Stats: system.l1_cntrl6.L1DcacheMemory
|
||||
system.l1_cntrl6.L1DcacheMemory_total_misses: 76915
|
||||
system.l1_cntrl6.L1DcacheMemory_total_demand_misses: 76915
|
||||
system.l1_cntrl6.L1DcacheMemory_total_prefetches: 0
|
||||
system.l1_cntrl6.L1DcacheMemory_total_sw_prefetches: 0
|
||||
system.l1_cntrl6.L1DcacheMemory_total_hw_prefetches: 0
|
||||
|
||||
system.l1_cntrl6.L1DcacheMemory_request_type_LD: 64.9938%
|
||||
system.l1_cntrl6.L1DcacheMemory_request_type_ST: 35.0062%
|
||||
|
||||
system.l1_cntrl6.L1DcacheMemory_access_mode_type_Supervisor: 76915 100%
|
||||
|
||||
Cache Stats: system.l1_cntrl7.L1IcacheMemory
|
||||
system.l1_cntrl7.L1IcacheMemory_total_misses: 0
|
||||
system.l1_cntrl7.L1IcacheMemory_total_demand_misses: 0
|
||||
system.l1_cntrl7.L1IcacheMemory_total_prefetches: 0
|
||||
system.l1_cntrl7.L1IcacheMemory_total_sw_prefetches: 0
|
||||
system.l1_cntrl7.L1IcacheMemory_total_hw_prefetches: 0
|
||||
|
||||
|
||||
Cache Stats: system.l1_cntrl7.L1DcacheMemory
|
||||
system.l1_cntrl7.L1DcacheMemory_total_misses: 77037
|
||||
system.l1_cntrl7.L1DcacheMemory_total_demand_misses: 77037
|
||||
system.l1_cntrl7.L1DcacheMemory_total_prefetches: 0
|
||||
system.l1_cntrl7.L1DcacheMemory_total_sw_prefetches: 0
|
||||
system.l1_cntrl7.L1DcacheMemory_total_hw_prefetches: 0
|
||||
|
||||
system.l1_cntrl7.L1DcacheMemory_request_type_LD: 65.0519%
|
||||
system.l1_cntrl7.L1DcacheMemory_request_type_ST: 34.9481%
|
||||
|
||||
system.l1_cntrl7.L1DcacheMemory_access_mode_type_Supervisor: 77037 100%
|
||||
|
||||
Cache Stats: system.l2_cntrl0.L2cacheMemory
|
||||
system.l2_cntrl0.L2cacheMemory_total_misses: 613380
|
||||
system.l2_cntrl0.L2cacheMemory_total_demand_misses: 613380
|
||||
system.l2_cntrl0.L2cacheMemory_total_prefetches: 0
|
||||
system.l2_cntrl0.L2cacheMemory_total_sw_prefetches: 0
|
||||
system.l2_cntrl0.L2cacheMemory_total_hw_prefetches: 0
|
||||
|
||||
system.l2_cntrl0.L2cacheMemory_request_type_GETS: 64.9578%
|
||||
system.l2_cntrl0.L2cacheMemory_request_type_GETX: 35.0422%
|
||||
|
||||
system.l2_cntrl0.L2cacheMemory_access_mode_type_Supervisor: 613380 100%
|
||||
|
||||
--- L2Cache ---
|
||||
- Event Counts -
|
||||
L1_GET_INSTR [0 ] 0
|
||||
L1_GETS [400269 ] 400269
|
||||
L1_GETX [217488 ] 217488
|
||||
L1_UPGRADE [0 ] 0
|
||||
L1_PUTX [44208 ] 44208
|
||||
L1_PUTX_old [269254 ] 269254
|
||||
Fwd_L1_GETX [0 ] 0
|
||||
Fwd_L1_GETS [0 ] 0
|
||||
Fwd_L1_GET_INSTR [0 ] 0
|
||||
L2_Replacement [16468 ] 16468
|
||||
L2_Replacement_clean [4206008 ] 4206008
|
||||
Mem_Data [607873 ] 607873
|
||||
Mem_Ack [607869 ] 607869
|
||||
WB_Data [199304 ] 199304
|
||||
WB_Data_clean [171738 ] 171738
|
||||
Ack [3800 ] 3800
|
||||
Ack_all [195623 ] 195623
|
||||
Unblock [1127 ] 1127
|
||||
Unblock_Cancel [0 ] 0
|
||||
Exclusive_Unblock [606929 ] 606929
|
||||
MEM_Inv [0 ] 0
|
||||
|
||||
- Transitions -
|
||||
NP L1_GET_INSTR [0 ] 0
|
||||
NP L1_GETS [394631 ] 394631
|
||||
NP L1_GETX [213248 ] 213248
|
||||
NP L1_PUTX [0 ] 0
|
||||
NP L1_PUTX_old [248888 ] 248888
|
||||
|
||||
SS L1_GET_INSTR [0 ] 0
|
||||
SS L1_GETS [2 ] 2
|
||||
SS L1_GETX [9 ] 9
|
||||
SS L1_UPGRADE [0 ] 0
|
||||
SS L1_PUTX [416 ] 416
|
||||
SS L1_PUTX_old [0 ] 0
|
||||
SS L2_Replacement [1048 ] 1048
|
||||
SS L2_Replacement_clean [2743 ] 2743
|
||||
SS MEM_Inv [0 ] 0
|
||||
|
||||
M L1_GET_INSTR [0 ] 0
|
||||
M L1_GETS [19 ] 19
|
||||
M L1_GETX [8 ] 8
|
||||
M L1_PUTX [0 ] 0
|
||||
M L1_PUTX_old [0 ] 0
|
||||
M L2_Replacement [15037 ] 15037
|
||||
M L2_Replacement_clean [27295 ] 27295
|
||||
M MEM_Inv [0 ] 0
|
||||
|
||||
MT L1_GET_INSTR [0 ] 0
|
||||
MT L1_GETS [1127 ] 1127
|
||||
MT L1_GETX [1694 ] 1694
|
||||
MT L1_PUTX [42359 ] 42359
|
||||
MT L1_PUTX_old [642 ] 642
|
||||
MT L2_Replacement [14 ] 14
|
||||
MT L2_Replacement_clean [561734 ] 561734
|
||||
MT MEM_Inv [0 ] 0
|
||||
|
||||
M_I L1_GET_INSTR [0 ] 0
|
||||
M_I L1_GETS [322 ] 322
|
||||
M_I L1_GETX [188 ] 188
|
||||
M_I L1_UPGRADE [0 ] 0
|
||||
M_I L1_PUTX [0 ] 0
|
||||
M_I L1_PUTX_old [16257 ] 16257
|
||||
M_I Mem_Ack [607869 ] 607869
|
||||
M_I MEM_Inv [0 ] 0
|
||||
|
||||
MT_I L1_GET_INSTR [0 ] 0
|
||||
MT_I L1_GETS [0 ] 0
|
||||
MT_I L1_GETX [0 ] 0
|
||||
MT_I L1_UPGRADE [0 ] 0
|
||||
MT_I L1_PUTX [0 ] 0
|
||||
MT_I L1_PUTX_old [0 ] 0
|
||||
MT_I WB_Data [4 ] 4
|
||||
MT_I WB_Data_clean [0 ] 0
|
||||
MT_I Ack_all [10 ] 10
|
||||
MT_I MEM_Inv [0 ] 0
|
||||
|
||||
MCT_I L1_GET_INSTR [0 ] 0
|
||||
MCT_I L1_GETS [46 ] 46
|
||||
MCT_I L1_GETX [87 ] 87
|
||||
MCT_I L1_UPGRADE [0 ] 0
|
||||
MCT_I L1_PUTX [0 ] 0
|
||||
MCT_I L1_PUTX_old [3034 ] 3034
|
||||
MCT_I WB_Data [198250 ] 198250
|
||||
MCT_I WB_Data_clean [171661 ] 171661
|
||||
MCT_I Ack_all [191822 ] 191822
|
||||
|
||||
I_I L1_GET_INSTR [0 ] 0
|
||||
I_I L1_GETS [0 ] 0
|
||||
I_I L1_GETX [0 ] 0
|
||||
I_I L1_UPGRADE [0 ] 0
|
||||
I_I L1_PUTX [0 ] 0
|
||||
I_I L1_PUTX_old [0 ] 0
|
||||
I_I Ack [2751 ] 2751
|
||||
I_I Ack_all [2743 ] 2743
|
||||
|
||||
S_I L1_GET_INSTR [0 ] 0
|
||||
S_I L1_GETS [0 ] 0
|
||||
S_I L1_GETX [0 ] 0
|
||||
S_I L1_UPGRADE [0 ] 0
|
||||
S_I L1_PUTX [0 ] 0
|
||||
S_I L1_PUTX_old [3 ] 3
|
||||
S_I Ack [1049 ] 1049
|
||||
S_I Ack_all [1048 ] 1048
|
||||
S_I MEM_Inv [0 ] 0
|
||||
|
||||
ISS L1_GET_INSTR [0 ] 0
|
||||
ISS L1_GETS [2673 ] 2673
|
||||
ISS L1_GETX [1435 ] 1435
|
||||
ISS L1_PUTX [0 ] 0
|
||||
ISS L1_PUTX_old [151 ] 151
|
||||
ISS L2_Replacement [0 ] 0
|
||||
ISS L2_Replacement_clean [2322371 ] 2322371
|
||||
ISS Mem_Data [391952 ] 391952
|
||||
ISS MEM_Inv [0 ] 0
|
||||
|
||||
IS L1_GET_INSTR [0 ] 0
|
||||
IS L1_GETS [7 ] 7
|
||||
IS L1_GETX [2 ] 2
|
||||
IS L1_PUTX [0 ] 0
|
||||
IS L1_PUTX_old [1 ] 1
|
||||
IS L2_Replacement [0 ] 0
|
||||
IS L2_Replacement_clean [15202 ] 15202
|
||||
IS Mem_Data [2673 ] 2673
|
||||
IS MEM_Inv [0 ] 0
|
||||
|
||||
IM L1_GET_INSTR [0 ] 0
|
||||
IM L1_GETS [1428 ] 1428
|
||||
IM L1_GETX [804 ] 804
|
||||
IM L1_PUTX [0 ] 0
|
||||
IM L1_PUTX_old [275 ] 275
|
||||
IM L2_Replacement [0 ] 0
|
||||
IM L2_Replacement_clean [1265010 ] 1265010
|
||||
IM Mem_Data [213248 ] 213248
|
||||
IM MEM_Inv [0 ] 0
|
||||
|
||||
SS_MB L1_GET_INSTR [0 ] 0
|
||||
SS_MB L1_GETS [0 ] 0
|
||||
SS_MB L1_GETX [0 ] 0
|
||||
SS_MB L1_UPGRADE [0 ] 0
|
||||
SS_MB L1_PUTX [2 ] 2
|
||||
SS_MB L1_PUTX_old [0 ] 0
|
||||
SS_MB L2_Replacement [9 ] 9
|
||||
SS_MB L2_Replacement_clean [0 ] 0
|
||||
SS_MB Unblock_Cancel [0 ] 0
|
||||
SS_MB Exclusive_Unblock [9 ] 9
|
||||
SS_MB MEM_Inv [0 ] 0
|
||||
|
||||
MT_MB L1_GET_INSTR [0 ] 0
|
||||
MT_MB L1_GETS [12 ] 12
|
||||
MT_MB L1_GETX [10 ] 10
|
||||
MT_MB L1_UPGRADE [0 ] 0
|
||||
MT_MB L1_PUTX [882 ] 882
|
||||
MT_MB L1_PUTX_old [3 ] 3
|
||||
MT_MB L2_Replacement [0 ] 0
|
||||
MT_MB L2_Replacement_clean [10256 ] 10256
|
||||
MT_MB Unblock_Cancel [0 ] 0
|
||||
MT_MB Exclusive_Unblock [606920 ] 606920
|
||||
MT_MB MEM_Inv [0 ] 0
|
||||
|
||||
M_MB L1_GET_INSTR [0 ] 0
|
||||
M_MB L1_GETS [0 ] 0
|
||||
M_MB L1_GETX [0 ] 0
|
||||
M_MB L1_UPGRADE [0 ] 0
|
||||
M_MB L1_PUTX [0 ] 0
|
||||
M_MB L1_PUTX_old [0 ] 0
|
||||
M_MB L2_Replacement [0 ] 0
|
||||
M_MB L2_Replacement_clean [0 ] 0
|
||||
M_MB Exclusive_Unblock [0 ] 0
|
||||
M_MB MEM_Inv [0 ] 0
|
||||
|
||||
MT_IIB L1_GET_INSTR [0 ] 0
|
||||
MT_IIB L1_GETS [2 ] 2
|
||||
MT_IIB L1_GETX [3 ] 3
|
||||
MT_IIB L1_UPGRADE [0 ] 0
|
||||
MT_IIB L1_PUTX [549 ] 549
|
||||
MT_IIB L1_PUTX_old [0 ] 0
|
||||
MT_IIB L2_Replacement [0 ] 0
|
||||
MT_IIB L2_Replacement_clean [1396 ] 1396
|
||||
MT_IIB WB_Data [1014 ] 1014
|
||||
MT_IIB WB_Data_clean [49 ] 49
|
||||
MT_IIB Unblock [64 ] 64
|
||||
MT_IIB MEM_Inv [0 ] 0
|
||||
|
||||
MT_IB L1_GET_INSTR [0 ] 0
|
||||
MT_IB L1_GETS [0 ] 0
|
||||
MT_IB L1_GETX [0 ] 0
|
||||
MT_IB L1_UPGRADE [0 ] 0
|
||||
MT_IB L1_PUTX [0 ] 0
|
||||
MT_IB L1_PUTX_old [0 ] 0
|
||||
MT_IB L2_Replacement [0 ] 0
|
||||
MT_IB L2_Replacement_clean [0 ] 0
|
||||
MT_IB WB_Data [36 ] 36
|
||||
MT_IB WB_Data_clean [28 ] 28
|
||||
MT_IB Unblock_Cancel [0 ] 0
|
||||
MT_IB MEM_Inv [0 ] 0
|
||||
|
||||
MT_SB L1_GET_INSTR [0 ] 0
|
||||
MT_SB L1_GETS [0 ] 0
|
||||
MT_SB L1_GETX [0 ] 0
|
||||
MT_SB L1_UPGRADE [0 ] 0
|
||||
MT_SB L1_PUTX [0 ] 0
|
||||
MT_SB L1_PUTX_old [0 ] 0
|
||||
MT_SB L2_Replacement [360 ] 360
|
||||
MT_SB L2_Replacement_clean [1 ] 1
|
||||
MT_SB Unblock [1063 ] 1063
|
||||
MT_SB MEM_Inv [0 ] 0
|
||||
|
||||
Memory controller: system.dir_cntrl0.memBuffer:
|
||||
memory_total_requests: 822228
|
||||
memory_reads: 607877
|
||||
memory_writes: 214348
|
||||
memory_refreshes: 46866
|
||||
memory_total_request_delays: 11056095
|
||||
memory_delays_per_request: 13.4465
|
||||
memory_delays_in_input_queue: 305324
|
||||
memory_delays_behind_head_of_bank_queue: 1501538
|
||||
memory_delays_stalled_at_head_of_bank_queue: 9249233
|
||||
memory_stalls_for_bank_busy: 1604583
|
||||
memory_stalls_for_random_busy: 0
|
||||
memory_stalls_for_anti_starvation: 760549
|
||||
memory_stalls_for_arbitration: 1893614
|
||||
memory_stalls_for_bus: 2911518
|
||||
memory_stalls_for_tfaw: 0
|
||||
memory_stalls_for_read_write_turnaround: 1476231
|
||||
memory_stalls_for_read_read_turnaround: 602738
|
||||
accesses_per_bank: 25852 25458 25588 25863 25866 25734 25935 25720 25907 25655 25734 25844 25494 25550 25672 25550 25617 25674 25773 25682 25816 25648 25748 25552 25632 25308 25669 25310 25655 25850 26059 25813
|
||||
|
||||
--- Directory ---
|
||||
- Event Counts -
|
||||
Fetch [607879 ] 607879
|
||||
Data [214349 ] 214349
|
||||
Memory_Data [607873 ] 607873
|
||||
Memory_Ack [214348 ] 214348
|
||||
DMA_READ [0 ] 0
|
||||
DMA_WRITE [0 ] 0
|
||||
CleanReplacement [393521 ] 393521
|
||||
|
||||
- Transitions -
|
||||
I Fetch [607879 ] 607879
|
||||
I DMA_READ [0 ] 0
|
||||
I DMA_WRITE [0 ] 0
|
||||
|
||||
ID Fetch [0 ] 0
|
||||
ID Data [0 ] 0
|
||||
ID Memory_Data [0 ] 0
|
||||
ID DMA_READ [0 ] 0
|
||||
ID DMA_WRITE [0 ] 0
|
||||
|
||||
ID_W Fetch [0 ] 0
|
||||
ID_W Data [0 ] 0
|
||||
ID_W Memory_Ack [0 ] 0
|
||||
ID_W DMA_READ [0 ] 0
|
||||
ID_W DMA_WRITE [0 ] 0
|
||||
|
||||
M Data [214349 ] 214349
|
||||
M DMA_READ [0 ] 0
|
||||
M DMA_WRITE [0 ] 0
|
||||
M CleanReplacement [393521 ] 393521
|
||||
|
||||
IM Fetch [0 ] 0
|
||||
IM Data [0 ] 0
|
||||
IM Memory_Data [607873 ] 607873
|
||||
IM DMA_READ [0 ] 0
|
||||
IM DMA_WRITE [0 ] 0
|
||||
|
||||
MI Fetch [0 ] 0
|
||||
MI Data [0 ] 0
|
||||
MI Memory_Ack [214348 ] 214348
|
||||
MI DMA_READ [0 ] 0
|
||||
MI DMA_WRITE [0 ] 0
|
||||
|
||||
M_DRD Data [0 ] 0
|
||||
M_DRD DMA_READ [0 ] 0
|
||||
M_DRD DMA_WRITE [0 ] 0
|
||||
|
||||
M_DRDI Fetch [0 ] 0
|
||||
M_DRDI Data [0 ] 0
|
||||
M_DRDI Memory_Ack [0 ] 0
|
||||
M_DRDI DMA_READ [0 ] 0
|
||||
M_DRDI DMA_WRITE [0 ] 0
|
||||
|
||||
M_DWR Data [0 ] 0
|
||||
M_DWR DMA_READ [0 ] 0
|
||||
M_DWR DMA_WRITE [0 ] 0
|
||||
|
||||
M_DWRI Fetch [0 ] 0
|
||||
M_DWRI Data [0 ] 0
|
||||
M_DWRI Memory_Ack [0 ] 0
|
||||
M_DWRI DMA_READ [0 ] 0
|
||||
M_DWRI DMA_WRITE [0 ] 0
|
||||
|
||||
@ -0,0 +1,74 @@
|
||||
system.cpu7: completed 10000 read, 5315 write accesses @2178175
|
||||
system.cpu3: completed 10000 read, 5321 write accesses @2258665
|
||||
system.cpu4: completed 10000 read, 5425 write accesses @2267755
|
||||
system.cpu6: completed 10000 read, 5427 write accesses @2268141
|
||||
system.cpu0: completed 10000 read, 5406 write accesses @2273125
|
||||
system.cpu1: completed 10000 read, 5452 write accesses @2273264
|
||||
system.cpu5: completed 10000 read, 5563 write accesses @2285825
|
||||
system.cpu2: completed 10000 read, 5393 write accesses @2319830
|
||||
system.cpu6: completed 20000 read, 10754 write accesses @4478934
|
||||
system.cpu7: completed 20000 read, 10722 write accesses @4479230
|
||||
system.cpu3: completed 20000 read, 10700 write accesses @4490364
|
||||
system.cpu1: completed 20000 read, 10770 write accesses @4490415
|
||||
system.cpu2: completed 20000 read, 10639 write accesses @4498895
|
||||
system.cpu5: completed 20000 read, 10822 write accesses @4521505
|
||||
system.cpu4: completed 20000 read, 10759 write accesses @4557615
|
||||
system.cpu0: completed 20000 read, 10835 write accesses @4559745
|
||||
system.cpu2: completed 30000 read, 15995 write accesses @6715895
|
||||
system.cpu6: completed 30000 read, 16176 write accesses @6737577
|
||||
system.cpu7: completed 30000 read, 16133 write accesses @6741445
|
||||
system.cpu5: completed 30000 read, 16232 write accesses @6761017
|
||||
system.cpu1: completed 30000 read, 16230 write accesses @6767058
|
||||
system.cpu3: completed 30000 read, 16227 write accesses @6779365
|
||||
system.cpu4: completed 30000 read, 16123 write accesses @6794365
|
||||
system.cpu0: completed 30000 read, 16180 write accesses @6842625
|
||||
system.cpu5: completed 40000 read, 21501 write accesses @9004145
|
||||
system.cpu3: completed 40000 read, 21499 write accesses @9006504
|
||||
system.cpu6: completed 40000 read, 21666 write accesses @9018985
|
||||
system.cpu4: completed 40000 read, 21471 write accesses @9035325
|
||||
system.cpu7: completed 40000 read, 21682 write accesses @9038295
|
||||
system.cpu2: completed 40000 read, 21469 write accesses @9046715
|
||||
system.cpu1: completed 40000 read, 21651 write accesses @9051455
|
||||
system.cpu0: completed 40000 read, 21538 write accesses @9086675
|
||||
system.cpu6: completed 50000 read, 27114 write accesses @11277374
|
||||
system.cpu3: completed 50000 read, 26914 write accesses @11278005
|
||||
system.cpu7: completed 50000 read, 27059 write accesses @11289715
|
||||
system.cpu5: completed 50000 read, 26974 write accesses @11300494
|
||||
system.cpu2: completed 50000 read, 27018 write accesses @11307085
|
||||
system.cpu1: completed 50000 read, 26955 write accesses @11338755
|
||||
system.cpu0: completed 50000 read, 26964 write accesses @11375085
|
||||
system.cpu4: completed 50000 read, 26957 write accesses @11429764
|
||||
system.cpu6: completed 60000 read, 32482 write accesses @13471525
|
||||
system.cpu3: completed 60000 read, 32172 write accesses @13503805
|
||||
system.cpu5: completed 60000 read, 32381 write accesses @13517804
|
||||
system.cpu7: completed 60000 read, 32276 write accesses @13525105
|
||||
system.cpu2: completed 60000 read, 32332 write accesses @13536245
|
||||
system.cpu1: completed 60000 read, 32320 write accesses @13562114
|
||||
system.cpu0: completed 60000 read, 32359 write accesses @13656465
|
||||
system.cpu4: completed 60000 read, 32583 write accesses @13754744
|
||||
system.cpu5: completed 70000 read, 37779 write accesses @15741524
|
||||
system.cpu3: completed 70000 read, 37626 write accesses @15742775
|
||||
system.cpu6: completed 70000 read, 37950 write accesses @15755405
|
||||
system.cpu7: completed 70000 read, 37483 write accesses @15767164
|
||||
system.cpu1: completed 70000 read, 37652 write accesses @15806815
|
||||
system.cpu2: completed 70000 read, 37653 write accesses @15812414
|
||||
system.cpu0: completed 70000 read, 37652 write accesses @15945564
|
||||
system.cpu4: completed 70000 read, 37919 write accesses @15985575
|
||||
system.cpu7: completed 80000 read, 42762 write accesses @17959865
|
||||
system.cpu5: completed 80000 read, 43041 write accesses @17974164
|
||||
system.cpu3: completed 80000 read, 42943 write accesses @17982045
|
||||
system.cpu6: completed 80000 read, 43147 write accesses @17984384
|
||||
system.cpu1: completed 80000 read, 42940 write accesses @18041354
|
||||
system.cpu2: completed 80000 read, 43118 write accesses @18148206
|
||||
system.cpu0: completed 80000 read, 42966 write accesses @18152744
|
||||
system.cpu4: completed 80000 read, 43236 write accesses @18256215
|
||||
system.cpu5: completed 90000 read, 48432 write accesses @20226495
|
||||
system.cpu6: completed 90000 read, 48567 write accesses @20256365
|
||||
system.cpu7: completed 90000 read, 48171 write accesses @20262095
|
||||
system.cpu3: completed 90000 read, 48375 write accesses @20266104
|
||||
system.cpu1: completed 90000 read, 48524 write accesses @20337685
|
||||
system.cpu0: completed 90000 read, 48274 write accesses @20381074
|
||||
system.cpu2: completed 90000 read, 48595 write accesses @20447365
|
||||
system.cpu4: completed 90000 read, 48684 write accesses @20509404
|
||||
system.cpu3: completed 100000 read, 53763 write accesses @22495354
|
||||
hack: be nice to actually delete the event here
|
||||
@ -0,0 +1,10 @@
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jun 4 2012 11:53:20
|
||||
gem5 started Jun 4 2012 14:40:22
|
||||
gem5 executing on zizzer
|
||||
command line: build/ALPHA_MESI_CMP_directory/gem5.opt -d build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MESI_CMP_directory
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 22495354 because maximum number of loads reached
|
||||
@ -0,0 +1,35 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.022495 # Number of seconds simulated
|
||||
sim_ticks 22495354 # Number of ticks simulated
|
||||
final_tick 22495354 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_tick_rate 256726 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 370452 # Number of bytes of host memory used
|
||||
host_seconds 87.62 # Real time elapsed on the host
|
||||
system.cpu0.num_reads 99326 # number of read accesses completed
|
||||
system.cpu0.num_writes 53132 # number of write accesses completed
|
||||
system.cpu0.num_copies 0 # number of copy accesses completed
|
||||
system.cpu1.num_reads 99634 # number of read accesses completed
|
||||
system.cpu1.num_writes 53798 # number of write accesses completed
|
||||
system.cpu1.num_copies 0 # number of copy accesses completed
|
||||
system.cpu2.num_reads 99031 # number of read accesses completed
|
||||
system.cpu2.num_writes 53441 # number of write accesses completed
|
||||
system.cpu2.num_copies 0 # number of copy accesses completed
|
||||
system.cpu3.num_reads 100000 # number of read accesses completed
|
||||
system.cpu3.num_writes 53763 # number of write accesses completed
|
||||
system.cpu3.num_copies 0 # number of copy accesses completed
|
||||
system.cpu4.num_reads 98726 # number of read accesses completed
|
||||
system.cpu4.num_writes 53438 # number of write accesses completed
|
||||
system.cpu4.num_copies 0 # number of copy accesses completed
|
||||
system.cpu5.num_reads 99955 # number of read accesses completed
|
||||
system.cpu5.num_writes 53794 # number of write accesses completed
|
||||
system.cpu5.num_copies 0 # number of copy accesses completed
|
||||
system.cpu6.num_reads 99893 # number of read accesses completed
|
||||
system.cpu6.num_writes 53796 # number of write accesses completed
|
||||
system.cpu6.num_copies 0 # number of copy accesses completed
|
||||
system.cpu7.num_reads 99993 # number of read accesses completed
|
||||
system.cpu7.num_writes 53567 # number of write accesses completed
|
||||
system.cpu7.num_copies 0 # number of copy accesses completed
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
@ -0,0 +1,944 @@
|
||||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
full_system=false
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000
|
||||
time_sync_spin_threshold=100000
|
||||
|
||||
[system]
|
||||
type=System
|
||||
children=cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 dir_cntrl0 funcmem l1_cntrl0 l1_cntrl1 l1_cntrl2 l1_cntrl3 l1_cntrl4 l1_cntrl5 l1_cntrl6 l1_cntrl7 l2_cntrl0 physmem ruby sys_port_proxy
|
||||
boot_osflags=a
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
mem_mode=timing
|
||||
memories=system.physmem system.funcmem
|
||||
num_work_ids=16
|
||||
readfile=
|
||||
symbolfile=
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.sys_port_proxy.slave[0]
|
||||
|
||||
[system.cpu0]
|
||||
type=MemTest
|
||||
atomic=false
|
||||
issue_dmas=false
|
||||
max_loads=100000
|
||||
memory_size=65536
|
||||
percent_dest_unaligned=50
|
||||
percent_functional=50
|
||||
percent_reads=65
|
||||
percent_source_unaligned=50
|
||||
percent_uncacheable=0
|
||||
progress_interval=10000
|
||||
suppress_func_warnings=true
|
||||
sys=system
|
||||
trace_addr=0
|
||||
functional=system.funcmem.port[0]
|
||||
test=system.l1_cntrl0.sequencer.slave[0]
|
||||
|
||||
[system.cpu1]
|
||||
type=MemTest
|
||||
atomic=false
|
||||
issue_dmas=false
|
||||
max_loads=100000
|
||||
memory_size=65536
|
||||
percent_dest_unaligned=50
|
||||
percent_functional=50
|
||||
percent_reads=65
|
||||
percent_source_unaligned=50
|
||||
percent_uncacheable=0
|
||||
progress_interval=10000
|
||||
suppress_func_warnings=true
|
||||
sys=system
|
||||
trace_addr=0
|
||||
functional=system.funcmem.port[1]
|
||||
test=system.l1_cntrl1.sequencer.slave[0]
|
||||
|
||||
[system.cpu2]
|
||||
type=MemTest
|
||||
atomic=false
|
||||
issue_dmas=false
|
||||
max_loads=100000
|
||||
memory_size=65536
|
||||
percent_dest_unaligned=50
|
||||
percent_functional=50
|
||||
percent_reads=65
|
||||
percent_source_unaligned=50
|
||||
percent_uncacheable=0
|
||||
progress_interval=10000
|
||||
suppress_func_warnings=true
|
||||
sys=system
|
||||
trace_addr=0
|
||||
functional=system.funcmem.port[2]
|
||||
test=system.l1_cntrl2.sequencer.slave[0]
|
||||
|
||||
[system.cpu3]
|
||||
type=MemTest
|
||||
atomic=false
|
||||
issue_dmas=false
|
||||
max_loads=100000
|
||||
memory_size=65536
|
||||
percent_dest_unaligned=50
|
||||
percent_functional=50
|
||||
percent_reads=65
|
||||
percent_source_unaligned=50
|
||||
percent_uncacheable=0
|
||||
progress_interval=10000
|
||||
suppress_func_warnings=true
|
||||
sys=system
|
||||
trace_addr=0
|
||||
functional=system.funcmem.port[3]
|
||||
test=system.l1_cntrl3.sequencer.slave[0]
|
||||
|
||||
[system.cpu4]
|
||||
type=MemTest
|
||||
atomic=false
|
||||
issue_dmas=false
|
||||
max_loads=100000
|
||||
memory_size=65536
|
||||
percent_dest_unaligned=50
|
||||
percent_functional=50
|
||||
percent_reads=65
|
||||
percent_source_unaligned=50
|
||||
percent_uncacheable=0
|
||||
progress_interval=10000
|
||||
suppress_func_warnings=true
|
||||
sys=system
|
||||
trace_addr=0
|
||||
functional=system.funcmem.port[4]
|
||||
test=system.l1_cntrl4.sequencer.slave[0]
|
||||
|
||||
[system.cpu5]
|
||||
type=MemTest
|
||||
atomic=false
|
||||
issue_dmas=false
|
||||
max_loads=100000
|
||||
memory_size=65536
|
||||
percent_dest_unaligned=50
|
||||
percent_functional=50
|
||||
percent_reads=65
|
||||
percent_source_unaligned=50
|
||||
percent_uncacheable=0
|
||||
progress_interval=10000
|
||||
suppress_func_warnings=true
|
||||
sys=system
|
||||
trace_addr=0
|
||||
functional=system.funcmem.port[5]
|
||||
test=system.l1_cntrl5.sequencer.slave[0]
|
||||
|
||||
[system.cpu6]
|
||||
type=MemTest
|
||||
atomic=false
|
||||
issue_dmas=false
|
||||
max_loads=100000
|
||||
memory_size=65536
|
||||
percent_dest_unaligned=50
|
||||
percent_functional=50
|
||||
percent_reads=65
|
||||
percent_source_unaligned=50
|
||||
percent_uncacheable=0
|
||||
progress_interval=10000
|
||||
suppress_func_warnings=true
|
||||
sys=system
|
||||
trace_addr=0
|
||||
functional=system.funcmem.port[6]
|
||||
test=system.l1_cntrl6.sequencer.slave[0]
|
||||
|
||||
[system.cpu7]
|
||||
type=MemTest
|
||||
atomic=false
|
||||
issue_dmas=false
|
||||
max_loads=100000
|
||||
memory_size=65536
|
||||
percent_dest_unaligned=50
|
||||
percent_functional=50
|
||||
percent_reads=65
|
||||
percent_source_unaligned=50
|
||||
percent_uncacheable=0
|
||||
progress_interval=10000
|
||||
suppress_func_warnings=true
|
||||
sys=system
|
||||
trace_addr=0
|
||||
functional=system.funcmem.port[7]
|
||||
test=system.l1_cntrl7.sequencer.slave[0]
|
||||
|
||||
[system.dir_cntrl0]
|
||||
type=Directory_Controller
|
||||
children=directory memBuffer
|
||||
buffer_size=0
|
||||
cntrl_id=9
|
||||
directory=system.dir_cntrl0.directory
|
||||
directory_latency=6
|
||||
memBuffer=system.dir_cntrl0.memBuffer
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
ruby_system=system.ruby
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.dir_cntrl0.directory]
|
||||
type=RubyDirectoryMemory
|
||||
map_levels=4
|
||||
numa_high_bit=6
|
||||
size=268435456
|
||||
use_map=false
|
||||
version=0
|
||||
|
||||
[system.dir_cntrl0.memBuffer]
|
||||
type=RubyMemoryControl
|
||||
bank_bit_0=8
|
||||
bank_busy_time=11
|
||||
bank_queue_size=12
|
||||
banks_per_rank=8
|
||||
basic_bus_busy_time=2
|
||||
dimm_bit_0=12
|
||||
dimms_per_channel=2
|
||||
mem_bus_cycle_multiplier=10
|
||||
mem_ctl_latency=12
|
||||
mem_fixed_delay=0
|
||||
mem_random_arbitrate=0
|
||||
rank_bit_0=11
|
||||
rank_rank_delay=1
|
||||
ranks_per_dimm=2
|
||||
read_write_delay=2
|
||||
refresh_period=1560
|
||||
tFaw=0
|
||||
version=0
|
||||
|
||||
[system.funcmem]
|
||||
type=SimpleMemory
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=false
|
||||
latency=30
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.cpu0.functional system.cpu1.functional system.cpu2.functional system.cpu3.functional system.cpu4.functional system.cpu5.functional system.cpu6.functional system.cpu7.functional
|
||||
|
||||
[system.l1_cntrl0]
|
||||
type=L1Cache_Controller
|
||||
children=L1DcacheMemory L1IcacheMemory sequencer
|
||||
L1DcacheMemory=system.l1_cntrl0.L1DcacheMemory
|
||||
L1IcacheMemory=system.l1_cntrl0.L1IcacheMemory
|
||||
buffer_size=0
|
||||
cntrl_id=0
|
||||
l2_select_num_bits=0
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
request_latency=2
|
||||
ruby_system=system.ruby
|
||||
send_evictions=false
|
||||
sequencer=system.l1_cntrl0.sequencer
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.l1_cntrl0.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
is_icache=false
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl0.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
is_icache=false
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl0.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=false
|
||||
dcache=system.l1_cntrl0.L1DcacheMemory
|
||||
deadlock_threshold=1000000
|
||||
icache=system.l1_cntrl0.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
ruby_system=system.ruby
|
||||
support_data_reqs=true
|
||||
support_inst_reqs=true
|
||||
system=system
|
||||
using_network_tester=false
|
||||
using_ruby_tester=false
|
||||
version=0
|
||||
slave=system.cpu0.test
|
||||
|
||||
[system.l1_cntrl1]
|
||||
type=L1Cache_Controller
|
||||
children=L1DcacheMemory L1IcacheMemory sequencer
|
||||
L1DcacheMemory=system.l1_cntrl1.L1DcacheMemory
|
||||
L1IcacheMemory=system.l1_cntrl1.L1IcacheMemory
|
||||
buffer_size=0
|
||||
cntrl_id=1
|
||||
l2_select_num_bits=0
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
request_latency=2
|
||||
ruby_system=system.ruby
|
||||
send_evictions=false
|
||||
sequencer=system.l1_cntrl1.sequencer
|
||||
transitions_per_cycle=32
|
||||
version=1
|
||||
|
||||
[system.l1_cntrl1.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
is_icache=false
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl1.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
is_icache=false
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl1.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=false
|
||||
dcache=system.l1_cntrl1.L1DcacheMemory
|
||||
deadlock_threshold=1000000
|
||||
icache=system.l1_cntrl1.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
ruby_system=system.ruby
|
||||
support_data_reqs=true
|
||||
support_inst_reqs=true
|
||||
system=system
|
||||
using_network_tester=false
|
||||
using_ruby_tester=false
|
||||
version=1
|
||||
slave=system.cpu1.test
|
||||
|
||||
[system.l1_cntrl2]
|
||||
type=L1Cache_Controller
|
||||
children=L1DcacheMemory L1IcacheMemory sequencer
|
||||
L1DcacheMemory=system.l1_cntrl2.L1DcacheMemory
|
||||
L1IcacheMemory=system.l1_cntrl2.L1IcacheMemory
|
||||
buffer_size=0
|
||||
cntrl_id=2
|
||||
l2_select_num_bits=0
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
request_latency=2
|
||||
ruby_system=system.ruby
|
||||
send_evictions=false
|
||||
sequencer=system.l1_cntrl2.sequencer
|
||||
transitions_per_cycle=32
|
||||
version=2
|
||||
|
||||
[system.l1_cntrl2.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
is_icache=false
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl2.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
is_icache=false
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl2.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=false
|
||||
dcache=system.l1_cntrl2.L1DcacheMemory
|
||||
deadlock_threshold=1000000
|
||||
icache=system.l1_cntrl2.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
ruby_system=system.ruby
|
||||
support_data_reqs=true
|
||||
support_inst_reqs=true
|
||||
system=system
|
||||
using_network_tester=false
|
||||
using_ruby_tester=false
|
||||
version=2
|
||||
slave=system.cpu2.test
|
||||
|
||||
[system.l1_cntrl3]
|
||||
type=L1Cache_Controller
|
||||
children=L1DcacheMemory L1IcacheMemory sequencer
|
||||
L1DcacheMemory=system.l1_cntrl3.L1DcacheMemory
|
||||
L1IcacheMemory=system.l1_cntrl3.L1IcacheMemory
|
||||
buffer_size=0
|
||||
cntrl_id=3
|
||||
l2_select_num_bits=0
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
request_latency=2
|
||||
ruby_system=system.ruby
|
||||
send_evictions=false
|
||||
sequencer=system.l1_cntrl3.sequencer
|
||||
transitions_per_cycle=32
|
||||
version=3
|
||||
|
||||
[system.l1_cntrl3.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
is_icache=false
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl3.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
is_icache=false
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl3.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=false
|
||||
dcache=system.l1_cntrl3.L1DcacheMemory
|
||||
deadlock_threshold=1000000
|
||||
icache=system.l1_cntrl3.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
ruby_system=system.ruby
|
||||
support_data_reqs=true
|
||||
support_inst_reqs=true
|
||||
system=system
|
||||
using_network_tester=false
|
||||
using_ruby_tester=false
|
||||
version=3
|
||||
slave=system.cpu3.test
|
||||
|
||||
[system.l1_cntrl4]
|
||||
type=L1Cache_Controller
|
||||
children=L1DcacheMemory L1IcacheMemory sequencer
|
||||
L1DcacheMemory=system.l1_cntrl4.L1DcacheMemory
|
||||
L1IcacheMemory=system.l1_cntrl4.L1IcacheMemory
|
||||
buffer_size=0
|
||||
cntrl_id=4
|
||||
l2_select_num_bits=0
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
request_latency=2
|
||||
ruby_system=system.ruby
|
||||
send_evictions=false
|
||||
sequencer=system.l1_cntrl4.sequencer
|
||||
transitions_per_cycle=32
|
||||
version=4
|
||||
|
||||
[system.l1_cntrl4.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
is_icache=false
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl4.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
is_icache=false
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl4.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=false
|
||||
dcache=system.l1_cntrl4.L1DcacheMemory
|
||||
deadlock_threshold=1000000
|
||||
icache=system.l1_cntrl4.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
ruby_system=system.ruby
|
||||
support_data_reqs=true
|
||||
support_inst_reqs=true
|
||||
system=system
|
||||
using_network_tester=false
|
||||
using_ruby_tester=false
|
||||
version=4
|
||||
slave=system.cpu4.test
|
||||
|
||||
[system.l1_cntrl5]
|
||||
type=L1Cache_Controller
|
||||
children=L1DcacheMemory L1IcacheMemory sequencer
|
||||
L1DcacheMemory=system.l1_cntrl5.L1DcacheMemory
|
||||
L1IcacheMemory=system.l1_cntrl5.L1IcacheMemory
|
||||
buffer_size=0
|
||||
cntrl_id=5
|
||||
l2_select_num_bits=0
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
request_latency=2
|
||||
ruby_system=system.ruby
|
||||
send_evictions=false
|
||||
sequencer=system.l1_cntrl5.sequencer
|
||||
transitions_per_cycle=32
|
||||
version=5
|
||||
|
||||
[system.l1_cntrl5.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
is_icache=false
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl5.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
is_icache=false
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl5.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=false
|
||||
dcache=system.l1_cntrl5.L1DcacheMemory
|
||||
deadlock_threshold=1000000
|
||||
icache=system.l1_cntrl5.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
ruby_system=system.ruby
|
||||
support_data_reqs=true
|
||||
support_inst_reqs=true
|
||||
system=system
|
||||
using_network_tester=false
|
||||
using_ruby_tester=false
|
||||
version=5
|
||||
slave=system.cpu5.test
|
||||
|
||||
[system.l1_cntrl6]
|
||||
type=L1Cache_Controller
|
||||
children=L1DcacheMemory L1IcacheMemory sequencer
|
||||
L1DcacheMemory=system.l1_cntrl6.L1DcacheMemory
|
||||
L1IcacheMemory=system.l1_cntrl6.L1IcacheMemory
|
||||
buffer_size=0
|
||||
cntrl_id=6
|
||||
l2_select_num_bits=0
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
request_latency=2
|
||||
ruby_system=system.ruby
|
||||
send_evictions=false
|
||||
sequencer=system.l1_cntrl6.sequencer
|
||||
transitions_per_cycle=32
|
||||
version=6
|
||||
|
||||
[system.l1_cntrl6.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
is_icache=false
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl6.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
is_icache=false
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl6.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=false
|
||||
dcache=system.l1_cntrl6.L1DcacheMemory
|
||||
deadlock_threshold=1000000
|
||||
icache=system.l1_cntrl6.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
ruby_system=system.ruby
|
||||
support_data_reqs=true
|
||||
support_inst_reqs=true
|
||||
system=system
|
||||
using_network_tester=false
|
||||
using_ruby_tester=false
|
||||
version=6
|
||||
slave=system.cpu6.test
|
||||
|
||||
[system.l1_cntrl7]
|
||||
type=L1Cache_Controller
|
||||
children=L1DcacheMemory L1IcacheMemory sequencer
|
||||
L1DcacheMemory=system.l1_cntrl7.L1DcacheMemory
|
||||
L1IcacheMemory=system.l1_cntrl7.L1IcacheMemory
|
||||
buffer_size=0
|
||||
cntrl_id=7
|
||||
l2_select_num_bits=0
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
request_latency=2
|
||||
ruby_system=system.ruby
|
||||
send_evictions=false
|
||||
sequencer=system.l1_cntrl7.sequencer
|
||||
transitions_per_cycle=32
|
||||
version=7
|
||||
|
||||
[system.l1_cntrl7.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
is_icache=false
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl7.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
is_icache=false
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl7.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=false
|
||||
dcache=system.l1_cntrl7.L1DcacheMemory
|
||||
deadlock_threshold=1000000
|
||||
icache=system.l1_cntrl7.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
ruby_system=system.ruby
|
||||
support_data_reqs=true
|
||||
support_inst_reqs=true
|
||||
system=system
|
||||
using_network_tester=false
|
||||
using_ruby_tester=false
|
||||
version=7
|
||||
slave=system.cpu7.test
|
||||
|
||||
[system.l2_cntrl0]
|
||||
type=L2Cache_Controller
|
||||
children=L2cacheMemory
|
||||
L2cacheMemory=system.l2_cntrl0.L2cacheMemory
|
||||
buffer_size=0
|
||||
cntrl_id=8
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
request_latency=2
|
||||
response_latency=2
|
||||
ruby_system=system.ruby
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.l2_cntrl0.L2cacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
is_icache=false
|
||||
latency=15
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=512
|
||||
start_index_bit=6
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=30
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
|
||||
[system.ruby]
|
||||
type=RubySystem
|
||||
children=network profiler
|
||||
block_size_bytes=64
|
||||
clock=1
|
||||
mem_size=268435456
|
||||
no_mem_vec=false
|
||||
random_seed=1234
|
||||
randomization=false
|
||||
stats_filename=ruby.stats
|
||||
|
||||
[system.ruby.network]
|
||||
type=SimpleNetwork
|
||||
children=topology
|
||||
adaptive_routing=false
|
||||
buffer_size=0
|
||||
control_msg_size=8
|
||||
endpoint_bandwidth=1000
|
||||
number_of_virtual_networks=10
|
||||
ruby_system=system.ruby
|
||||
topology=system.ruby.network.topology
|
||||
|
||||
[system.ruby.network.topology]
|
||||
type=Topology
|
||||
children=ext_links0 ext_links1 ext_links2 ext_links3 ext_links4 ext_links5 ext_links6 ext_links7 ext_links8 ext_links9 int_links0 int_links1 int_links2 int_links3 int_links4 int_links5 int_links6 int_links7 int_links8 int_links9 routers00 routers01 routers02 routers03 routers04 routers05 routers06 routers07 routers08 routers09 routers10
|
||||
description=Crossbar
|
||||
ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2 system.ruby.network.topology.ext_links3 system.ruby.network.topology.ext_links4 system.ruby.network.topology.ext_links5 system.ruby.network.topology.ext_links6 system.ruby.network.topology.ext_links7 system.ruby.network.topology.ext_links8 system.ruby.network.topology.ext_links9
|
||||
int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2 system.ruby.network.topology.int_links3 system.ruby.network.topology.int_links4 system.ruby.network.topology.int_links5 system.ruby.network.topology.int_links6 system.ruby.network.topology.int_links7 system.ruby.network.topology.int_links8 system.ruby.network.topology.int_links9
|
||||
print_config=false
|
||||
routers=system.ruby.network.topology.routers00 system.ruby.network.topology.routers01 system.ruby.network.topology.routers02 system.ruby.network.topology.routers03 system.ruby.network.topology.routers04 system.ruby.network.topology.routers05 system.ruby.network.topology.routers06 system.ruby.network.topology.routers07 system.ruby.network.topology.routers08 system.ruby.network.topology.routers09 system.ruby.network.topology.routers10
|
||||
|
||||
[system.ruby.network.topology.ext_links0]
|
||||
type=SimpleExtLink
|
||||
bandwidth_factor=16
|
||||
ext_node=system.l1_cntrl0
|
||||
int_node=system.ruby.network.topology.routers00
|
||||
latency=1
|
||||
link_id=0
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links1]
|
||||
type=SimpleExtLink
|
||||
bandwidth_factor=16
|
||||
ext_node=system.l1_cntrl1
|
||||
int_node=system.ruby.network.topology.routers01
|
||||
latency=1
|
||||
link_id=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links2]
|
||||
type=SimpleExtLink
|
||||
bandwidth_factor=16
|
||||
ext_node=system.l1_cntrl2
|
||||
int_node=system.ruby.network.topology.routers02
|
||||
latency=1
|
||||
link_id=2
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links3]
|
||||
type=SimpleExtLink
|
||||
bandwidth_factor=16
|
||||
ext_node=system.l1_cntrl3
|
||||
int_node=system.ruby.network.topology.routers03
|
||||
latency=1
|
||||
link_id=3
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links4]
|
||||
type=SimpleExtLink
|
||||
bandwidth_factor=16
|
||||
ext_node=system.l1_cntrl4
|
||||
int_node=system.ruby.network.topology.routers04
|
||||
latency=1
|
||||
link_id=4
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links5]
|
||||
type=SimpleExtLink
|
||||
bandwidth_factor=16
|
||||
ext_node=system.l1_cntrl5
|
||||
int_node=system.ruby.network.topology.routers05
|
||||
latency=1
|
||||
link_id=5
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links6]
|
||||
type=SimpleExtLink
|
||||
bandwidth_factor=16
|
||||
ext_node=system.l1_cntrl6
|
||||
int_node=system.ruby.network.topology.routers06
|
||||
latency=1
|
||||
link_id=6
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links7]
|
||||
type=SimpleExtLink
|
||||
bandwidth_factor=16
|
||||
ext_node=system.l1_cntrl7
|
||||
int_node=system.ruby.network.topology.routers07
|
||||
latency=1
|
||||
link_id=7
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links8]
|
||||
type=SimpleExtLink
|
||||
bandwidth_factor=16
|
||||
ext_node=system.l2_cntrl0
|
||||
int_node=system.ruby.network.topology.routers08
|
||||
latency=1
|
||||
link_id=8
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links9]
|
||||
type=SimpleExtLink
|
||||
bandwidth_factor=16
|
||||
ext_node=system.dir_cntrl0
|
||||
int_node=system.ruby.network.topology.routers09
|
||||
latency=1
|
||||
link_id=9
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.int_links0]
|
||||
type=SimpleIntLink
|
||||
bandwidth_factor=16
|
||||
latency=1
|
||||
link_id=10
|
||||
node_a=system.ruby.network.topology.routers00
|
||||
node_b=system.ruby.network.topology.routers10
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.int_links1]
|
||||
type=SimpleIntLink
|
||||
bandwidth_factor=16
|
||||
latency=1
|
||||
link_id=11
|
||||
node_a=system.ruby.network.topology.routers01
|
||||
node_b=system.ruby.network.topology.routers10
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.int_links2]
|
||||
type=SimpleIntLink
|
||||
bandwidth_factor=16
|
||||
latency=1
|
||||
link_id=12
|
||||
node_a=system.ruby.network.topology.routers02
|
||||
node_b=system.ruby.network.topology.routers10
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.int_links3]
|
||||
type=SimpleIntLink
|
||||
bandwidth_factor=16
|
||||
latency=1
|
||||
link_id=13
|
||||
node_a=system.ruby.network.topology.routers03
|
||||
node_b=system.ruby.network.topology.routers10
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.int_links4]
|
||||
type=SimpleIntLink
|
||||
bandwidth_factor=16
|
||||
latency=1
|
||||
link_id=14
|
||||
node_a=system.ruby.network.topology.routers04
|
||||
node_b=system.ruby.network.topology.routers10
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.int_links5]
|
||||
type=SimpleIntLink
|
||||
bandwidth_factor=16
|
||||
latency=1
|
||||
link_id=15
|
||||
node_a=system.ruby.network.topology.routers05
|
||||
node_b=system.ruby.network.topology.routers10
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.int_links6]
|
||||
type=SimpleIntLink
|
||||
bandwidth_factor=16
|
||||
latency=1
|
||||
link_id=16
|
||||
node_a=system.ruby.network.topology.routers06
|
||||
node_b=system.ruby.network.topology.routers10
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.int_links7]
|
||||
type=SimpleIntLink
|
||||
bandwidth_factor=16
|
||||
latency=1
|
||||
link_id=17
|
||||
node_a=system.ruby.network.topology.routers07
|
||||
node_b=system.ruby.network.topology.routers10
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.int_links8]
|
||||
type=SimpleIntLink
|
||||
bandwidth_factor=16
|
||||
latency=1
|
||||
link_id=18
|
||||
node_a=system.ruby.network.topology.routers08
|
||||
node_b=system.ruby.network.topology.routers10
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.int_links9]
|
||||
type=SimpleIntLink
|
||||
bandwidth_factor=16
|
||||
latency=1
|
||||
link_id=19
|
||||
node_a=system.ruby.network.topology.routers09
|
||||
node_b=system.ruby.network.topology.routers10
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.routers00]
|
||||
type=BasicRouter
|
||||
router_id=0
|
||||
|
||||
[system.ruby.network.topology.routers01]
|
||||
type=BasicRouter
|
||||
router_id=1
|
||||
|
||||
[system.ruby.network.topology.routers02]
|
||||
type=BasicRouter
|
||||
router_id=2
|
||||
|
||||
[system.ruby.network.topology.routers03]
|
||||
type=BasicRouter
|
||||
router_id=3
|
||||
|
||||
[system.ruby.network.topology.routers04]
|
||||
type=BasicRouter
|
||||
router_id=4
|
||||
|
||||
[system.ruby.network.topology.routers05]
|
||||
type=BasicRouter
|
||||
router_id=5
|
||||
|
||||
[system.ruby.network.topology.routers06]
|
||||
type=BasicRouter
|
||||
router_id=6
|
||||
|
||||
[system.ruby.network.topology.routers07]
|
||||
type=BasicRouter
|
||||
router_id=7
|
||||
|
||||
[system.ruby.network.topology.routers08]
|
||||
type=BasicRouter
|
||||
router_id=8
|
||||
|
||||
[system.ruby.network.topology.routers09]
|
||||
type=BasicRouter
|
||||
router_id=9
|
||||
|
||||
[system.ruby.network.topology.routers10]
|
||||
type=BasicRouter
|
||||
router_id=10
|
||||
|
||||
[system.ruby.profiler]
|
||||
type=RubyProfiler
|
||||
all_instructions=false
|
||||
hot_lines=false
|
||||
num_of_sequencers=8
|
||||
ruby_system=system.ruby
|
||||
|
||||
[system.sys_port_proxy]
|
||||
type=RubyPortProxy
|
||||
access_phys_mem=true
|
||||
ruby_system=system.ruby
|
||||
support_data_reqs=true
|
||||
support_inst_reqs=true
|
||||
system=system
|
||||
using_network_tester=false
|
||||
using_ruby_tester=false
|
||||
version=0
|
||||
slave=system.system_port
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,74 @@
|
||||
system.cpu1: completed 10000 read, 5302 write accesses @1928146
|
||||
system.cpu4: completed 10000 read, 5365 write accesses @1942166
|
||||
system.cpu7: completed 10000 read, 5319 write accesses @1965207
|
||||
system.cpu3: completed 10000 read, 5359 write accesses @1968836
|
||||
system.cpu0: completed 10000 read, 5498 write accesses @1974677
|
||||
system.cpu2: completed 10000 read, 5513 write accesses @1977476
|
||||
system.cpu6: completed 10000 read, 5448 write accesses @1980956
|
||||
system.cpu5: completed 10000 read, 5483 write accesses @1995684
|
||||
system.cpu4: completed 20000 read, 10717 write accesses @3830467
|
||||
system.cpu1: completed 20000 read, 10577 write accesses @3871337
|
||||
system.cpu7: completed 20000 read, 10556 write accesses @3902287
|
||||
system.cpu5: completed 20000 read, 10901 write accesses @3923395
|
||||
system.cpu0: completed 20000 read, 10861 write accesses @3926315
|
||||
system.cpu2: completed 20000 read, 10674 write accesses @3934695
|
||||
system.cpu6: completed 20000 read, 10925 write accesses @3939046
|
||||
system.cpu3: completed 20000 read, 10752 write accesses @3981115
|
||||
system.cpu4: completed 30000 read, 16128 write accesses @5754566
|
||||
system.cpu7: completed 30000 read, 16027 write accesses @5841539
|
||||
system.cpu5: completed 30000 read, 16312 write accesses @5857206
|
||||
system.cpu2: completed 30000 read, 16104 write accesses @5869696
|
||||
system.cpu1: completed 30000 read, 16084 write accesses @5872577
|
||||
system.cpu0: completed 30000 read, 16133 write accesses @5895696
|
||||
system.cpu6: completed 30000 read, 16259 write accesses @5909016
|
||||
system.cpu3: completed 30000 read, 16253 write accesses @5970997
|
||||
system.cpu4: completed 40000 read, 21443 write accesses @7732298
|
||||
system.cpu7: completed 40000 read, 21518 write accesses @7817106
|
||||
system.cpu0: completed 40000 read, 21561 write accesses @7817675
|
||||
system.cpu2: completed 40000 read, 21432 write accesses @7822846
|
||||
system.cpu1: completed 40000 read, 21383 write accesses @7845525
|
||||
system.cpu5: completed 40000 read, 21816 write accesses @7858096
|
||||
system.cpu6: completed 40000 read, 21672 write accesses @7885486
|
||||
system.cpu3: completed 40000 read, 21581 write accesses @7941597
|
||||
system.cpu4: completed 50000 read, 26787 write accesses @9651285
|
||||
system.cpu7: completed 50000 read, 26989 write accesses @9793686
|
||||
system.cpu0: completed 50000 read, 26994 write accesses @9797807
|
||||
system.cpu2: completed 50000 read, 26921 write accesses @9830875
|
||||
system.cpu5: completed 50000 read, 27153 write accesses @9839316
|
||||
system.cpu6: completed 50000 read, 27189 write accesses @9858608
|
||||
system.cpu1: completed 50000 read, 26834 write accesses @9863587
|
||||
system.cpu3: completed 50000 read, 27039 write accesses @9921406
|
||||
system.cpu4: completed 60000 read, 32175 write accesses @11605575
|
||||
system.cpu2: completed 60000 read, 32358 write accesses @11729986
|
||||
system.cpu0: completed 60000 read, 32424 write accesses @11735436
|
||||
system.cpu7: completed 60000 read, 32432 write accesses @11778007
|
||||
system.cpu6: completed 60000 read, 32473 write accesses @11788255
|
||||
system.cpu5: completed 60000 read, 32623 write accesses @11789575
|
||||
system.cpu1: completed 60000 read, 32116 write accesses @11821356
|
||||
system.cpu3: completed 60000 read, 32229 write accesses @11884826
|
||||
system.cpu4: completed 70000 read, 37533 write accesses @13546365
|
||||
system.cpu0: completed 70000 read, 37907 write accesses @13701646
|
||||
system.cpu2: completed 70000 read, 37745 write accesses @13708257
|
||||
system.cpu6: completed 70000 read, 37768 write accesses @13710576
|
||||
system.cpu7: completed 70000 read, 37843 write accesses @13719776
|
||||
system.cpu5: completed 70000 read, 37934 write accesses @13770505
|
||||
system.cpu1: completed 70000 read, 37322 write accesses @13773596
|
||||
system.cpu3: completed 70000 read, 37575 write accesses @13859246
|
||||
system.cpu4: completed 80000 read, 42663 write accesses @15468226
|
||||
system.cpu6: completed 80000 read, 43059 write accesses @15617186
|
||||
system.cpu7: completed 80000 read, 43185 write accesses @15635279
|
||||
system.cpu0: completed 80000 read, 43129 write accesses @15668486
|
||||
system.cpu2: completed 80000 read, 43262 write accesses @15680656
|
||||
system.cpu1: completed 80000 read, 42658 write accesses @15703946
|
||||
system.cpu5: completed 80000 read, 43215 write accesses @15712586
|
||||
system.cpu3: completed 80000 read, 42991 write accesses @15858096
|
||||
system.cpu4: completed 90000 read, 48047 write accesses @17468576
|
||||
system.cpu2: completed 90000 read, 48557 write accesses @17581105
|
||||
system.cpu7: completed 90000 read, 48648 write accesses @17584296
|
||||
system.cpu6: completed 90000 read, 48515 write accesses @17584397
|
||||
system.cpu1: completed 90000 read, 48024 write accesses @17672186
|
||||
system.cpu0: completed 90000 read, 48750 write accesses @17683641
|
||||
system.cpu5: completed 90000 read, 48534 write accesses @17695277
|
||||
system.cpu3: completed 90000 read, 48496 write accesses @17843215
|
||||
system.cpu4: completed 100000 read, 53558 write accesses @19400856
|
||||
hack: be nice to actually delete the event here
|
||||
@ -0,0 +1,10 @@
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jun 4 2012 11:54:55
|
||||
gem5 started Jun 4 2012 14:41:26
|
||||
gem5 executing on zizzer
|
||||
command line: build/ALPHA_MOESI_CMP_directory/gem5.opt -d build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_directory
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 19400856 because maximum number of loads reached
|
||||
@ -0,0 +1,35 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.019401 # Number of seconds simulated
|
||||
sim_ticks 19400856 # Number of ticks simulated
|
||||
final_tick 19400856 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_tick_rate 79524 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 370632 # Number of bytes of host memory used
|
||||
host_seconds 243.96 # Real time elapsed on the host
|
||||
system.cpu0.num_reads 98844 # number of read accesses completed
|
||||
system.cpu0.num_writes 53478 # number of write accesses completed
|
||||
system.cpu0.num_copies 0 # number of copy accesses completed
|
||||
system.cpu1.num_reads 98643 # number of read accesses completed
|
||||
system.cpu1.num_writes 52679 # number of write accesses completed
|
||||
system.cpu1.num_copies 0 # number of copy accesses completed
|
||||
system.cpu2.num_reads 99369 # number of read accesses completed
|
||||
system.cpu2.num_writes 53574 # number of write accesses completed
|
||||
system.cpu2.num_copies 0 # number of copy accesses completed
|
||||
system.cpu3.num_reads 97889 # number of read accesses completed
|
||||
system.cpu3.num_writes 52711 # number of write accesses completed
|
||||
system.cpu3.num_copies 0 # number of copy accesses completed
|
||||
system.cpu4.num_reads 100000 # number of read accesses completed
|
||||
system.cpu4.num_writes 53558 # number of write accesses completed
|
||||
system.cpu4.num_copies 0 # number of copy accesses completed
|
||||
system.cpu5.num_reads 98762 # number of read accesses completed
|
||||
system.cpu5.num_writes 53328 # number of write accesses completed
|
||||
system.cpu5.num_copies 0 # number of copy accesses completed
|
||||
system.cpu6.num_reads 99308 # number of read accesses completed
|
||||
system.cpu6.num_writes 53445 # number of write accesses completed
|
||||
system.cpu6.num_copies 0 # number of copy accesses completed
|
||||
system.cpu7.num_reads 99141 # number of read accesses completed
|
||||
system.cpu7.num_writes 53490 # number of write accesses completed
|
||||
system.cpu7.num_copies 0 # number of copy accesses completed
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
@ -0,0 +1,997 @@
|
||||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
full_system=false
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000
|
||||
time_sync_spin_threshold=100000
|
||||
|
||||
[system]
|
||||
type=System
|
||||
children=cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 dir_cntrl0 funcmem l1_cntrl0 l1_cntrl1 l1_cntrl2 l1_cntrl3 l1_cntrl4 l1_cntrl5 l1_cntrl6 l1_cntrl7 l2_cntrl0 physmem ruby sys_port_proxy
|
||||
boot_osflags=a
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
mem_mode=timing
|
||||
memories=system.physmem system.funcmem
|
||||
num_work_ids=16
|
||||
readfile=
|
||||
symbolfile=
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.sys_port_proxy.slave[0]
|
||||
|
||||
[system.cpu0]
|
||||
type=MemTest
|
||||
atomic=false
|
||||
issue_dmas=false
|
||||
max_loads=100000
|
||||
memory_size=65536
|
||||
percent_dest_unaligned=50
|
||||
percent_functional=50
|
||||
percent_reads=65
|
||||
percent_source_unaligned=50
|
||||
percent_uncacheable=0
|
||||
progress_interval=10000
|
||||
suppress_func_warnings=true
|
||||
sys=system
|
||||
trace_addr=0
|
||||
functional=system.funcmem.port[0]
|
||||
test=system.l1_cntrl0.sequencer.slave[0]
|
||||
|
||||
[system.cpu1]
|
||||
type=MemTest
|
||||
atomic=false
|
||||
issue_dmas=false
|
||||
max_loads=100000
|
||||
memory_size=65536
|
||||
percent_dest_unaligned=50
|
||||
percent_functional=50
|
||||
percent_reads=65
|
||||
percent_source_unaligned=50
|
||||
percent_uncacheable=0
|
||||
progress_interval=10000
|
||||
suppress_func_warnings=true
|
||||
sys=system
|
||||
trace_addr=0
|
||||
functional=system.funcmem.port[1]
|
||||
test=system.l1_cntrl1.sequencer.slave[0]
|
||||
|
||||
[system.cpu2]
|
||||
type=MemTest
|
||||
atomic=false
|
||||
issue_dmas=false
|
||||
max_loads=100000
|
||||
memory_size=65536
|
||||
percent_dest_unaligned=50
|
||||
percent_functional=50
|
||||
percent_reads=65
|
||||
percent_source_unaligned=50
|
||||
percent_uncacheable=0
|
||||
progress_interval=10000
|
||||
suppress_func_warnings=true
|
||||
sys=system
|
||||
trace_addr=0
|
||||
functional=system.funcmem.port[2]
|
||||
test=system.l1_cntrl2.sequencer.slave[0]
|
||||
|
||||
[system.cpu3]
|
||||
type=MemTest
|
||||
atomic=false
|
||||
issue_dmas=false
|
||||
max_loads=100000
|
||||
memory_size=65536
|
||||
percent_dest_unaligned=50
|
||||
percent_functional=50
|
||||
percent_reads=65
|
||||
percent_source_unaligned=50
|
||||
percent_uncacheable=0
|
||||
progress_interval=10000
|
||||
suppress_func_warnings=true
|
||||
sys=system
|
||||
trace_addr=0
|
||||
functional=system.funcmem.port[3]
|
||||
test=system.l1_cntrl3.sequencer.slave[0]
|
||||
|
||||
[system.cpu4]
|
||||
type=MemTest
|
||||
atomic=false
|
||||
issue_dmas=false
|
||||
max_loads=100000
|
||||
memory_size=65536
|
||||
percent_dest_unaligned=50
|
||||
percent_functional=50
|
||||
percent_reads=65
|
||||
percent_source_unaligned=50
|
||||
percent_uncacheable=0
|
||||
progress_interval=10000
|
||||
suppress_func_warnings=true
|
||||
sys=system
|
||||
trace_addr=0
|
||||
functional=system.funcmem.port[4]
|
||||
test=system.l1_cntrl4.sequencer.slave[0]
|
||||
|
||||
[system.cpu5]
|
||||
type=MemTest
|
||||
atomic=false
|
||||
issue_dmas=false
|
||||
max_loads=100000
|
||||
memory_size=65536
|
||||
percent_dest_unaligned=50
|
||||
percent_functional=50
|
||||
percent_reads=65
|
||||
percent_source_unaligned=50
|
||||
percent_uncacheable=0
|
||||
progress_interval=10000
|
||||
suppress_func_warnings=true
|
||||
sys=system
|
||||
trace_addr=0
|
||||
functional=system.funcmem.port[5]
|
||||
test=system.l1_cntrl5.sequencer.slave[0]
|
||||
|
||||
[system.cpu6]
|
||||
type=MemTest
|
||||
atomic=false
|
||||
issue_dmas=false
|
||||
max_loads=100000
|
||||
memory_size=65536
|
||||
percent_dest_unaligned=50
|
||||
percent_functional=50
|
||||
percent_reads=65
|
||||
percent_source_unaligned=50
|
||||
percent_uncacheable=0
|
||||
progress_interval=10000
|
||||
suppress_func_warnings=true
|
||||
sys=system
|
||||
trace_addr=0
|
||||
functional=system.funcmem.port[6]
|
||||
test=system.l1_cntrl6.sequencer.slave[0]
|
||||
|
||||
[system.cpu7]
|
||||
type=MemTest
|
||||
atomic=false
|
||||
issue_dmas=false
|
||||
max_loads=100000
|
||||
memory_size=65536
|
||||
percent_dest_unaligned=50
|
||||
percent_functional=50
|
||||
percent_reads=65
|
||||
percent_source_unaligned=50
|
||||
percent_uncacheable=0
|
||||
progress_interval=10000
|
||||
suppress_func_warnings=true
|
||||
sys=system
|
||||
trace_addr=0
|
||||
functional=system.funcmem.port[7]
|
||||
test=system.l1_cntrl7.sequencer.slave[0]
|
||||
|
||||
[system.dir_cntrl0]
|
||||
type=Directory_Controller
|
||||
children=directory memBuffer
|
||||
buffer_size=0
|
||||
cntrl_id=9
|
||||
directory=system.dir_cntrl0.directory
|
||||
directory_latency=5
|
||||
distributed_persistent=true
|
||||
fixed_timeout_latency=100
|
||||
l2_select_num_bits=0
|
||||
memBuffer=system.dir_cntrl0.memBuffer
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
ruby_system=system.ruby
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.dir_cntrl0.directory]
|
||||
type=RubyDirectoryMemory
|
||||
map_levels=4
|
||||
numa_high_bit=6
|
||||
size=268435456
|
||||
use_map=false
|
||||
version=0
|
||||
|
||||
[system.dir_cntrl0.memBuffer]
|
||||
type=RubyMemoryControl
|
||||
bank_bit_0=8
|
||||
bank_busy_time=11
|
||||
bank_queue_size=12
|
||||
banks_per_rank=8
|
||||
basic_bus_busy_time=2
|
||||
dimm_bit_0=12
|
||||
dimms_per_channel=2
|
||||
mem_bus_cycle_multiplier=10
|
||||
mem_ctl_latency=12
|
||||
mem_fixed_delay=0
|
||||
mem_random_arbitrate=0
|
||||
rank_bit_0=11
|
||||
rank_rank_delay=1
|
||||
ranks_per_dimm=2
|
||||
read_write_delay=2
|
||||
refresh_period=1560
|
||||
tFaw=0
|
||||
version=0
|
||||
|
||||
[system.funcmem]
|
||||
type=SimpleMemory
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=false
|
||||
latency=30
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.cpu0.functional system.cpu1.functional system.cpu2.functional system.cpu3.functional system.cpu4.functional system.cpu5.functional system.cpu6.functional system.cpu7.functional
|
||||
|
||||
[system.l1_cntrl0]
|
||||
type=L1Cache_Controller
|
||||
children=L1DcacheMemory L1IcacheMemory sequencer
|
||||
L1DcacheMemory=system.l1_cntrl0.L1DcacheMemory
|
||||
L1IcacheMemory=system.l1_cntrl0.L1IcacheMemory
|
||||
N_tokens=9
|
||||
buffer_size=0
|
||||
cntrl_id=0
|
||||
dynamic_timeout_enabled=true
|
||||
fixed_timeout_latency=300
|
||||
l1_request_latency=2
|
||||
l1_response_latency=2
|
||||
l2_select_num_bits=0
|
||||
no_mig_atomic=true
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
retry_threshold=1
|
||||
ruby_system=system.ruby
|
||||
send_evictions=false
|
||||
sequencer=system.l1_cntrl0.sequencer
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.l1_cntrl0.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
is_icache=false
|
||||
latency=2
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl0.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
is_icache=false
|
||||
latency=2
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl0.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=false
|
||||
dcache=system.l1_cntrl0.L1DcacheMemory
|
||||
deadlock_threshold=1000000
|
||||
icache=system.l1_cntrl0.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
ruby_system=system.ruby
|
||||
support_data_reqs=true
|
||||
support_inst_reqs=true
|
||||
system=system
|
||||
using_network_tester=false
|
||||
using_ruby_tester=false
|
||||
version=0
|
||||
slave=system.cpu0.test
|
||||
|
||||
[system.l1_cntrl1]
|
||||
type=L1Cache_Controller
|
||||
children=L1DcacheMemory L1IcacheMemory sequencer
|
||||
L1DcacheMemory=system.l1_cntrl1.L1DcacheMemory
|
||||
L1IcacheMemory=system.l1_cntrl1.L1IcacheMemory
|
||||
N_tokens=9
|
||||
buffer_size=0
|
||||
cntrl_id=1
|
||||
dynamic_timeout_enabled=true
|
||||
fixed_timeout_latency=300
|
||||
l1_request_latency=2
|
||||
l1_response_latency=2
|
||||
l2_select_num_bits=0
|
||||
no_mig_atomic=true
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
retry_threshold=1
|
||||
ruby_system=system.ruby
|
||||
send_evictions=false
|
||||
sequencer=system.l1_cntrl1.sequencer
|
||||
transitions_per_cycle=32
|
||||
version=1
|
||||
|
||||
[system.l1_cntrl1.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
is_icache=false
|
||||
latency=2
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl1.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
is_icache=false
|
||||
latency=2
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl1.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=false
|
||||
dcache=system.l1_cntrl1.L1DcacheMemory
|
||||
deadlock_threshold=1000000
|
||||
icache=system.l1_cntrl1.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
ruby_system=system.ruby
|
||||
support_data_reqs=true
|
||||
support_inst_reqs=true
|
||||
system=system
|
||||
using_network_tester=false
|
||||
using_ruby_tester=false
|
||||
version=1
|
||||
slave=system.cpu1.test
|
||||
|
||||
[system.l1_cntrl2]
|
||||
type=L1Cache_Controller
|
||||
children=L1DcacheMemory L1IcacheMemory sequencer
|
||||
L1DcacheMemory=system.l1_cntrl2.L1DcacheMemory
|
||||
L1IcacheMemory=system.l1_cntrl2.L1IcacheMemory
|
||||
N_tokens=9
|
||||
buffer_size=0
|
||||
cntrl_id=2
|
||||
dynamic_timeout_enabled=true
|
||||
fixed_timeout_latency=300
|
||||
l1_request_latency=2
|
||||
l1_response_latency=2
|
||||
l2_select_num_bits=0
|
||||
no_mig_atomic=true
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
retry_threshold=1
|
||||
ruby_system=system.ruby
|
||||
send_evictions=false
|
||||
sequencer=system.l1_cntrl2.sequencer
|
||||
transitions_per_cycle=32
|
||||
version=2
|
||||
|
||||
[system.l1_cntrl2.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
is_icache=false
|
||||
latency=2
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl2.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
is_icache=false
|
||||
latency=2
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl2.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=false
|
||||
dcache=system.l1_cntrl2.L1DcacheMemory
|
||||
deadlock_threshold=1000000
|
||||
icache=system.l1_cntrl2.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
ruby_system=system.ruby
|
||||
support_data_reqs=true
|
||||
support_inst_reqs=true
|
||||
system=system
|
||||
using_network_tester=false
|
||||
using_ruby_tester=false
|
||||
version=2
|
||||
slave=system.cpu2.test
|
||||
|
||||
[system.l1_cntrl3]
|
||||
type=L1Cache_Controller
|
||||
children=L1DcacheMemory L1IcacheMemory sequencer
|
||||
L1DcacheMemory=system.l1_cntrl3.L1DcacheMemory
|
||||
L1IcacheMemory=system.l1_cntrl3.L1IcacheMemory
|
||||
N_tokens=9
|
||||
buffer_size=0
|
||||
cntrl_id=3
|
||||
dynamic_timeout_enabled=true
|
||||
fixed_timeout_latency=300
|
||||
l1_request_latency=2
|
||||
l1_response_latency=2
|
||||
l2_select_num_bits=0
|
||||
no_mig_atomic=true
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
retry_threshold=1
|
||||
ruby_system=system.ruby
|
||||
send_evictions=false
|
||||
sequencer=system.l1_cntrl3.sequencer
|
||||
transitions_per_cycle=32
|
||||
version=3
|
||||
|
||||
[system.l1_cntrl3.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
is_icache=false
|
||||
latency=2
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl3.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
is_icache=false
|
||||
latency=2
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl3.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=false
|
||||
dcache=system.l1_cntrl3.L1DcacheMemory
|
||||
deadlock_threshold=1000000
|
||||
icache=system.l1_cntrl3.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
ruby_system=system.ruby
|
||||
support_data_reqs=true
|
||||
support_inst_reqs=true
|
||||
system=system
|
||||
using_network_tester=false
|
||||
using_ruby_tester=false
|
||||
version=3
|
||||
slave=system.cpu3.test
|
||||
|
||||
[system.l1_cntrl4]
|
||||
type=L1Cache_Controller
|
||||
children=L1DcacheMemory L1IcacheMemory sequencer
|
||||
L1DcacheMemory=system.l1_cntrl4.L1DcacheMemory
|
||||
L1IcacheMemory=system.l1_cntrl4.L1IcacheMemory
|
||||
N_tokens=9
|
||||
buffer_size=0
|
||||
cntrl_id=4
|
||||
dynamic_timeout_enabled=true
|
||||
fixed_timeout_latency=300
|
||||
l1_request_latency=2
|
||||
l1_response_latency=2
|
||||
l2_select_num_bits=0
|
||||
no_mig_atomic=true
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
retry_threshold=1
|
||||
ruby_system=system.ruby
|
||||
send_evictions=false
|
||||
sequencer=system.l1_cntrl4.sequencer
|
||||
transitions_per_cycle=32
|
||||
version=4
|
||||
|
||||
[system.l1_cntrl4.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
is_icache=false
|
||||
latency=2
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl4.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
is_icache=false
|
||||
latency=2
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl4.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=false
|
||||
dcache=system.l1_cntrl4.L1DcacheMemory
|
||||
deadlock_threshold=1000000
|
||||
icache=system.l1_cntrl4.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
ruby_system=system.ruby
|
||||
support_data_reqs=true
|
||||
support_inst_reqs=true
|
||||
system=system
|
||||
using_network_tester=false
|
||||
using_ruby_tester=false
|
||||
version=4
|
||||
slave=system.cpu4.test
|
||||
|
||||
[system.l1_cntrl5]
|
||||
type=L1Cache_Controller
|
||||
children=L1DcacheMemory L1IcacheMemory sequencer
|
||||
L1DcacheMemory=system.l1_cntrl5.L1DcacheMemory
|
||||
L1IcacheMemory=system.l1_cntrl5.L1IcacheMemory
|
||||
N_tokens=9
|
||||
buffer_size=0
|
||||
cntrl_id=5
|
||||
dynamic_timeout_enabled=true
|
||||
fixed_timeout_latency=300
|
||||
l1_request_latency=2
|
||||
l1_response_latency=2
|
||||
l2_select_num_bits=0
|
||||
no_mig_atomic=true
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
retry_threshold=1
|
||||
ruby_system=system.ruby
|
||||
send_evictions=false
|
||||
sequencer=system.l1_cntrl5.sequencer
|
||||
transitions_per_cycle=32
|
||||
version=5
|
||||
|
||||
[system.l1_cntrl5.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
is_icache=false
|
||||
latency=2
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl5.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
is_icache=false
|
||||
latency=2
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl5.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=false
|
||||
dcache=system.l1_cntrl5.L1DcacheMemory
|
||||
deadlock_threshold=1000000
|
||||
icache=system.l1_cntrl5.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
ruby_system=system.ruby
|
||||
support_data_reqs=true
|
||||
support_inst_reqs=true
|
||||
system=system
|
||||
using_network_tester=false
|
||||
using_ruby_tester=false
|
||||
version=5
|
||||
slave=system.cpu5.test
|
||||
|
||||
[system.l1_cntrl6]
|
||||
type=L1Cache_Controller
|
||||
children=L1DcacheMemory L1IcacheMemory sequencer
|
||||
L1DcacheMemory=system.l1_cntrl6.L1DcacheMemory
|
||||
L1IcacheMemory=system.l1_cntrl6.L1IcacheMemory
|
||||
N_tokens=9
|
||||
buffer_size=0
|
||||
cntrl_id=6
|
||||
dynamic_timeout_enabled=true
|
||||
fixed_timeout_latency=300
|
||||
l1_request_latency=2
|
||||
l1_response_latency=2
|
||||
l2_select_num_bits=0
|
||||
no_mig_atomic=true
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
retry_threshold=1
|
||||
ruby_system=system.ruby
|
||||
send_evictions=false
|
||||
sequencer=system.l1_cntrl6.sequencer
|
||||
transitions_per_cycle=32
|
||||
version=6
|
||||
|
||||
[system.l1_cntrl6.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
is_icache=false
|
||||
latency=2
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl6.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
is_icache=false
|
||||
latency=2
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl6.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=false
|
||||
dcache=system.l1_cntrl6.L1DcacheMemory
|
||||
deadlock_threshold=1000000
|
||||
icache=system.l1_cntrl6.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
ruby_system=system.ruby
|
||||
support_data_reqs=true
|
||||
support_inst_reqs=true
|
||||
system=system
|
||||
using_network_tester=false
|
||||
using_ruby_tester=false
|
||||
version=6
|
||||
slave=system.cpu6.test
|
||||
|
||||
[system.l1_cntrl7]
|
||||
type=L1Cache_Controller
|
||||
children=L1DcacheMemory L1IcacheMemory sequencer
|
||||
L1DcacheMemory=system.l1_cntrl7.L1DcacheMemory
|
||||
L1IcacheMemory=system.l1_cntrl7.L1IcacheMemory
|
||||
N_tokens=9
|
||||
buffer_size=0
|
||||
cntrl_id=7
|
||||
dynamic_timeout_enabled=true
|
||||
fixed_timeout_latency=300
|
||||
l1_request_latency=2
|
||||
l1_response_latency=2
|
||||
l2_select_num_bits=0
|
||||
no_mig_atomic=true
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
retry_threshold=1
|
||||
ruby_system=system.ruby
|
||||
send_evictions=false
|
||||
sequencer=system.l1_cntrl7.sequencer
|
||||
transitions_per_cycle=32
|
||||
version=7
|
||||
|
||||
[system.l1_cntrl7.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
is_icache=false
|
||||
latency=2
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl7.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
is_icache=false
|
||||
latency=2
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl7.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=false
|
||||
dcache=system.l1_cntrl7.L1DcacheMemory
|
||||
deadlock_threshold=1000000
|
||||
icache=system.l1_cntrl7.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
ruby_system=system.ruby
|
||||
support_data_reqs=true
|
||||
support_inst_reqs=true
|
||||
system=system
|
||||
using_network_tester=false
|
||||
using_ruby_tester=false
|
||||
version=7
|
||||
slave=system.cpu7.test
|
||||
|
||||
[system.l2_cntrl0]
|
||||
type=L2Cache_Controller
|
||||
children=L2cacheMemory
|
||||
L2cacheMemory=system.l2_cntrl0.L2cacheMemory
|
||||
N_tokens=9
|
||||
buffer_size=0
|
||||
cntrl_id=8
|
||||
filtering_enabled=true
|
||||
l2_request_latency=5
|
||||
l2_response_latency=5
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
ruby_system=system.ruby
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.l2_cntrl0.L2cacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
is_icache=false
|
||||
latency=10
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=512
|
||||
start_index_bit=6
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=30
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
|
||||
[system.ruby]
|
||||
type=RubySystem
|
||||
children=network profiler
|
||||
block_size_bytes=64
|
||||
clock=1
|
||||
mem_size=268435456
|
||||
no_mem_vec=false
|
||||
random_seed=1234
|
||||
randomization=false
|
||||
stats_filename=ruby.stats
|
||||
|
||||
[system.ruby.network]
|
||||
type=SimpleNetwork
|
||||
children=topology
|
||||
adaptive_routing=false
|
||||
buffer_size=0
|
||||
control_msg_size=8
|
||||
endpoint_bandwidth=1000
|
||||
number_of_virtual_networks=10
|
||||
ruby_system=system.ruby
|
||||
topology=system.ruby.network.topology
|
||||
|
||||
[system.ruby.network.topology]
|
||||
type=Topology
|
||||
children=ext_links0 ext_links1 ext_links2 ext_links3 ext_links4 ext_links5 ext_links6 ext_links7 ext_links8 ext_links9 int_links0 int_links1 int_links2 int_links3 int_links4 int_links5 int_links6 int_links7 int_links8 int_links9 routers00 routers01 routers02 routers03 routers04 routers05 routers06 routers07 routers08 routers09 routers10
|
||||
description=Crossbar
|
||||
ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2 system.ruby.network.topology.ext_links3 system.ruby.network.topology.ext_links4 system.ruby.network.topology.ext_links5 system.ruby.network.topology.ext_links6 system.ruby.network.topology.ext_links7 system.ruby.network.topology.ext_links8 system.ruby.network.topology.ext_links9
|
||||
int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2 system.ruby.network.topology.int_links3 system.ruby.network.topology.int_links4 system.ruby.network.topology.int_links5 system.ruby.network.topology.int_links6 system.ruby.network.topology.int_links7 system.ruby.network.topology.int_links8 system.ruby.network.topology.int_links9
|
||||
print_config=false
|
||||
routers=system.ruby.network.topology.routers00 system.ruby.network.topology.routers01 system.ruby.network.topology.routers02 system.ruby.network.topology.routers03 system.ruby.network.topology.routers04 system.ruby.network.topology.routers05 system.ruby.network.topology.routers06 system.ruby.network.topology.routers07 system.ruby.network.topology.routers08 system.ruby.network.topology.routers09 system.ruby.network.topology.routers10
|
||||
|
||||
[system.ruby.network.topology.ext_links0]
|
||||
type=SimpleExtLink
|
||||
bandwidth_factor=16
|
||||
ext_node=system.l1_cntrl0
|
||||
int_node=system.ruby.network.topology.routers00
|
||||
latency=1
|
||||
link_id=0
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links1]
|
||||
type=SimpleExtLink
|
||||
bandwidth_factor=16
|
||||
ext_node=system.l1_cntrl1
|
||||
int_node=system.ruby.network.topology.routers01
|
||||
latency=1
|
||||
link_id=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links2]
|
||||
type=SimpleExtLink
|
||||
bandwidth_factor=16
|
||||
ext_node=system.l1_cntrl2
|
||||
int_node=system.ruby.network.topology.routers02
|
||||
latency=1
|
||||
link_id=2
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links3]
|
||||
type=SimpleExtLink
|
||||
bandwidth_factor=16
|
||||
ext_node=system.l1_cntrl3
|
||||
int_node=system.ruby.network.topology.routers03
|
||||
latency=1
|
||||
link_id=3
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links4]
|
||||
type=SimpleExtLink
|
||||
bandwidth_factor=16
|
||||
ext_node=system.l1_cntrl4
|
||||
int_node=system.ruby.network.topology.routers04
|
||||
latency=1
|
||||
link_id=4
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links5]
|
||||
type=SimpleExtLink
|
||||
bandwidth_factor=16
|
||||
ext_node=system.l1_cntrl5
|
||||
int_node=system.ruby.network.topology.routers05
|
||||
latency=1
|
||||
link_id=5
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links6]
|
||||
type=SimpleExtLink
|
||||
bandwidth_factor=16
|
||||
ext_node=system.l1_cntrl6
|
||||
int_node=system.ruby.network.topology.routers06
|
||||
latency=1
|
||||
link_id=6
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links7]
|
||||
type=SimpleExtLink
|
||||
bandwidth_factor=16
|
||||
ext_node=system.l1_cntrl7
|
||||
int_node=system.ruby.network.topology.routers07
|
||||
latency=1
|
||||
link_id=7
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links8]
|
||||
type=SimpleExtLink
|
||||
bandwidth_factor=16
|
||||
ext_node=system.l2_cntrl0
|
||||
int_node=system.ruby.network.topology.routers08
|
||||
latency=1
|
||||
link_id=8
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links9]
|
||||
type=SimpleExtLink
|
||||
bandwidth_factor=16
|
||||
ext_node=system.dir_cntrl0
|
||||
int_node=system.ruby.network.topology.routers09
|
||||
latency=1
|
||||
link_id=9
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.int_links0]
|
||||
type=SimpleIntLink
|
||||
bandwidth_factor=16
|
||||
latency=1
|
||||
link_id=10
|
||||
node_a=system.ruby.network.topology.routers00
|
||||
node_b=system.ruby.network.topology.routers10
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.int_links1]
|
||||
type=SimpleIntLink
|
||||
bandwidth_factor=16
|
||||
latency=1
|
||||
link_id=11
|
||||
node_a=system.ruby.network.topology.routers01
|
||||
node_b=system.ruby.network.topology.routers10
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.int_links2]
|
||||
type=SimpleIntLink
|
||||
bandwidth_factor=16
|
||||
latency=1
|
||||
link_id=12
|
||||
node_a=system.ruby.network.topology.routers02
|
||||
node_b=system.ruby.network.topology.routers10
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.int_links3]
|
||||
type=SimpleIntLink
|
||||
bandwidth_factor=16
|
||||
latency=1
|
||||
link_id=13
|
||||
node_a=system.ruby.network.topology.routers03
|
||||
node_b=system.ruby.network.topology.routers10
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.int_links4]
|
||||
type=SimpleIntLink
|
||||
bandwidth_factor=16
|
||||
latency=1
|
||||
link_id=14
|
||||
node_a=system.ruby.network.topology.routers04
|
||||
node_b=system.ruby.network.topology.routers10
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.int_links5]
|
||||
type=SimpleIntLink
|
||||
bandwidth_factor=16
|
||||
latency=1
|
||||
link_id=15
|
||||
node_a=system.ruby.network.topology.routers05
|
||||
node_b=system.ruby.network.topology.routers10
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.int_links6]
|
||||
type=SimpleIntLink
|
||||
bandwidth_factor=16
|
||||
latency=1
|
||||
link_id=16
|
||||
node_a=system.ruby.network.topology.routers06
|
||||
node_b=system.ruby.network.topology.routers10
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.int_links7]
|
||||
type=SimpleIntLink
|
||||
bandwidth_factor=16
|
||||
latency=1
|
||||
link_id=17
|
||||
node_a=system.ruby.network.topology.routers07
|
||||
node_b=system.ruby.network.topology.routers10
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.int_links8]
|
||||
type=SimpleIntLink
|
||||
bandwidth_factor=16
|
||||
latency=1
|
||||
link_id=18
|
||||
node_a=system.ruby.network.topology.routers08
|
||||
node_b=system.ruby.network.topology.routers10
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.int_links9]
|
||||
type=SimpleIntLink
|
||||
bandwidth_factor=16
|
||||
latency=1
|
||||
link_id=19
|
||||
node_a=system.ruby.network.topology.routers09
|
||||
node_b=system.ruby.network.topology.routers10
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.routers00]
|
||||
type=BasicRouter
|
||||
router_id=0
|
||||
|
||||
[system.ruby.network.topology.routers01]
|
||||
type=BasicRouter
|
||||
router_id=1
|
||||
|
||||
[system.ruby.network.topology.routers02]
|
||||
type=BasicRouter
|
||||
router_id=2
|
||||
|
||||
[system.ruby.network.topology.routers03]
|
||||
type=BasicRouter
|
||||
router_id=3
|
||||
|
||||
[system.ruby.network.topology.routers04]
|
||||
type=BasicRouter
|
||||
router_id=4
|
||||
|
||||
[system.ruby.network.topology.routers05]
|
||||
type=BasicRouter
|
||||
router_id=5
|
||||
|
||||
[system.ruby.network.topology.routers06]
|
||||
type=BasicRouter
|
||||
router_id=6
|
||||
|
||||
[system.ruby.network.topology.routers07]
|
||||
type=BasicRouter
|
||||
router_id=7
|
||||
|
||||
[system.ruby.network.topology.routers08]
|
||||
type=BasicRouter
|
||||
router_id=8
|
||||
|
||||
[system.ruby.network.topology.routers09]
|
||||
type=BasicRouter
|
||||
router_id=9
|
||||
|
||||
[system.ruby.network.topology.routers10]
|
||||
type=BasicRouter
|
||||
router_id=10
|
||||
|
||||
[system.ruby.profiler]
|
||||
type=RubyProfiler
|
||||
all_instructions=false
|
||||
hot_lines=false
|
||||
num_of_sequencers=8
|
||||
ruby_system=system.ruby
|
||||
|
||||
[system.sys_port_proxy]
|
||||
type=RubyPortProxy
|
||||
access_phys_mem=true
|
||||
ruby_system=system.ruby
|
||||
support_data_reqs=true
|
||||
support_inst_reqs=true
|
||||
system=system
|
||||
using_network_tester=false
|
||||
using_ruby_tester=false
|
||||
version=0
|
||||
slave=system.system_port
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,74 @@
|
||||
system.cpu4: completed 10000 read, 5358 write accesses @1929263
|
||||
system.cpu0: completed 10000 read, 5517 write accesses @1938193
|
||||
system.cpu6: completed 10000 read, 5282 write accesses @1960370
|
||||
system.cpu2: completed 10000 read, 5370 write accesses @1983069
|
||||
system.cpu3: completed 10000 read, 5219 write accesses @1986540
|
||||
system.cpu5: completed 10000 read, 5534 write accesses @2010490
|
||||
system.cpu1: completed 10000 read, 5481 write accesses @2016799
|
||||
system.cpu7: completed 10000 read, 5483 write accesses @2027000
|
||||
system.cpu0: completed 20000 read, 10906 write accesses @3889460
|
||||
system.cpu6: completed 20000 read, 10539 write accesses @3890430
|
||||
system.cpu4: completed 20000 read, 10737 write accesses @3908329
|
||||
system.cpu2: completed 20000 read, 10719 write accesses @3939180
|
||||
system.cpu3: completed 20000 read, 10494 write accesses @3943600
|
||||
system.cpu5: completed 20000 read, 10848 write accesses @3948219
|
||||
system.cpu1: completed 20000 read, 10769 write accesses @4005719
|
||||
system.cpu7: completed 20000 read, 10891 write accesses @4012914
|
||||
system.cpu6: completed 30000 read, 15919 write accesses @5839330
|
||||
system.cpu4: completed 30000 read, 15999 write accesses @5874900
|
||||
system.cpu0: completed 30000 read, 16423 write accesses @5898830
|
||||
system.cpu5: completed 30000 read, 16404 write accesses @5936061
|
||||
system.cpu1: completed 30000 read, 16153 write accesses @5948410
|
||||
system.cpu7: completed 30000 read, 16256 write accesses @5950050
|
||||
system.cpu2: completed 30000 read, 16157 write accesses @5958790
|
||||
system.cpu3: completed 30000 read, 15885 write accesses @5959680
|
||||
system.cpu4: completed 40000 read, 21342 write accesses @7808600
|
||||
system.cpu6: completed 40000 read, 21196 write accesses @7836451
|
||||
system.cpu0: completed 40000 read, 21854 write accesses @7880130
|
||||
system.cpu1: completed 40000 read, 21631 write accesses @7920239
|
||||
system.cpu7: completed 40000 read, 21703 write accesses @7933959
|
||||
system.cpu5: completed 40000 read, 21772 write accesses @7955069
|
||||
system.cpu3: completed 40000 read, 21372 write accesses @7959100
|
||||
system.cpu2: completed 40000 read, 21557 write accesses @7981970
|
||||
system.cpu6: completed 50000 read, 26595 write accesses @9809169
|
||||
system.cpu4: completed 50000 read, 26864 write accesses @9817559
|
||||
system.cpu7: completed 50000 read, 27042 write accesses @9902500
|
||||
system.cpu0: completed 50000 read, 27271 write accesses @9906269
|
||||
system.cpu1: completed 50000 read, 27124 write accesses @9934930
|
||||
system.cpu3: completed 50000 read, 26755 write accesses @9946640
|
||||
system.cpu5: completed 50000 read, 27198 write accesses @9946679
|
||||
system.cpu2: completed 50000 read, 27060 write accesses @9974740
|
||||
system.cpu6: completed 60000 read, 32039 write accesses @11769919
|
||||
system.cpu4: completed 60000 read, 32173 write accesses @11822509
|
||||
system.cpu1: completed 60000 read, 32379 write accesses @11844429
|
||||
system.cpu0: completed 60000 read, 32699 write accesses @11852900
|
||||
system.cpu7: completed 60000 read, 32457 write accesses @11873181
|
||||
system.cpu5: completed 60000 read, 32557 write accesses @11887270
|
||||
system.cpu3: completed 60000 read, 32167 write accesses @11912630
|
||||
system.cpu2: completed 60000 read, 32437 write accesses @11967610
|
||||
system.cpu4: completed 70000 read, 37476 write accesses @13774590
|
||||
system.cpu1: completed 70000 read, 37764 write accesses @13776500
|
||||
system.cpu6: completed 70000 read, 37423 write accesses @13811110
|
||||
system.cpu0: completed 70000 read, 38112 write accesses @13822360
|
||||
system.cpu7: completed 70000 read, 37768 write accesses @13852100
|
||||
system.cpu3: completed 70000 read, 37356 write accesses @13890992
|
||||
system.cpu5: completed 70000 read, 38000 write accesses @13891330
|
||||
system.cpu2: completed 70000 read, 37653 write accesses @13903529
|
||||
system.cpu4: completed 80000 read, 42652 write accesses @15714260
|
||||
system.cpu1: completed 80000 read, 43161 write accesses @15743660
|
||||
system.cpu0: completed 80000 read, 43377 write accesses @15747360
|
||||
system.cpu6: completed 80000 read, 42650 write accesses @15761321
|
||||
system.cpu7: completed 80000 read, 43147 write accesses @15846829
|
||||
system.cpu2: completed 80000 read, 42984 write accesses @15878720
|
||||
system.cpu3: completed 80000 read, 42913 write accesses @15881610
|
||||
system.cpu5: completed 80000 read, 43333 write accesses @15910140
|
||||
system.cpu4: completed 90000 read, 48050 write accesses @17730480
|
||||
system.cpu1: completed 90000 read, 48527 write accesses @17731920
|
||||
system.cpu0: completed 90000 read, 48688 write accesses @17739870
|
||||
system.cpu6: completed 90000 read, 48114 write accesses @17751610
|
||||
system.cpu7: completed 90000 read, 48607 write accesses @17816041
|
||||
system.cpu2: completed 90000 read, 48386 write accesses @17847760
|
||||
system.cpu3: completed 90000 read, 48361 write accesses @17860389
|
||||
system.cpu5: completed 90000 read, 48782 write accesses @17871890
|
||||
system.cpu4: completed 100000 read, 53373 write accesses @19665440
|
||||
hack: be nice to actually delete the event here
|
||||
@ -0,0 +1,10 @@
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jun 4 2012 11:56:32
|
||||
gem5 started Jun 4 2012 14:42:33
|
||||
gem5 executing on zizzer
|
||||
command line: build/ALPHA_MOESI_CMP_token/gem5.opt -d build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_token
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 19665440 because maximum number of loads reached
|
||||
@ -0,0 +1,35 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.019665 # Number of seconds simulated
|
||||
sim_ticks 19665440 # Number of ticks simulated
|
||||
final_tick 19665440 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_tick_rate 168119 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 370164 # Number of bytes of host memory used
|
||||
host_seconds 116.97 # Real time elapsed on the host
|
||||
system.cpu0.num_reads 99534 # number of read accesses completed
|
||||
system.cpu0.num_writes 53920 # number of write accesses completed
|
||||
system.cpu0.num_copies 0 # number of copy accesses completed
|
||||
system.cpu1.num_reads 99604 # number of read accesses completed
|
||||
system.cpu1.num_writes 53779 # number of write accesses completed
|
||||
system.cpu1.num_copies 0 # number of copy accesses completed
|
||||
system.cpu2.num_reads 99103 # number of read accesses completed
|
||||
system.cpu2.num_writes 53314 # number of write accesses completed
|
||||
system.cpu2.num_copies 0 # number of copy accesses completed
|
||||
system.cpu3.num_reads 99223 # number of read accesses completed
|
||||
system.cpu3.num_writes 53188 # number of write accesses completed
|
||||
system.cpu3.num_copies 0 # number of copy accesses completed
|
||||
system.cpu4.num_reads 100000 # number of read accesses completed
|
||||
system.cpu4.num_writes 53373 # number of write accesses completed
|
||||
system.cpu4.num_copies 0 # number of copy accesses completed
|
||||
system.cpu5.num_reads 99316 # number of read accesses completed
|
||||
system.cpu5.num_writes 53693 # number of write accesses completed
|
||||
system.cpu5.num_copies 0 # number of copy accesses completed
|
||||
system.cpu6.num_reads 99832 # number of read accesses completed
|
||||
system.cpu6.num_writes 53341 # number of write accesses completed
|
||||
system.cpu6.num_copies 0 # number of copy accesses completed
|
||||
system.cpu7.num_reads 99257 # number of read accesses completed
|
||||
system.cpu7.num_writes 53656 # number of write accesses completed
|
||||
system.cpu7.num_copies 0 # number of copy accesses completed
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,74 @@
|
||||
system.cpu4: completed 10000 read, 5412 write accesses @1871699
|
||||
system.cpu2: completed 10000 read, 5460 write accesses @1893369
|
||||
system.cpu1: completed 10000 read, 5378 write accesses @1906861
|
||||
system.cpu6: completed 10000 read, 5396 write accesses @1925998
|
||||
system.cpu0: completed 10000 read, 5377 write accesses @1932348
|
||||
system.cpu5: completed 10000 read, 5525 write accesses @1940098
|
||||
system.cpu3: completed 10000 read, 5395 write accesses @1950309
|
||||
system.cpu7: completed 10000 read, 5394 write accesses @1966559
|
||||
system.cpu1: completed 20000 read, 10544 write accesses @3781959
|
||||
system.cpu4: completed 20000 read, 10680 write accesses @3792439
|
||||
system.cpu2: completed 20000 read, 10687 write accesses @3801439
|
||||
system.cpu3: completed 20000 read, 10623 write accesses @3813939
|
||||
system.cpu0: completed 20000 read, 10834 write accesses @3843808
|
||||
system.cpu5: completed 20000 read, 10928 write accesses @3845319
|
||||
system.cpu6: completed 20000 read, 10782 write accesses @3845558
|
||||
system.cpu7: completed 20000 read, 10939 write accesses @3904539
|
||||
system.cpu2: completed 30000 read, 15884 write accesses @5673111
|
||||
system.cpu4: completed 30000 read, 16055 write accesses @5692488
|
||||
system.cpu1: completed 30000 read, 16005 write accesses @5703958
|
||||
system.cpu3: completed 30000 read, 16124 write accesses @5726919
|
||||
system.cpu5: completed 30000 read, 16307 write accesses @5771630
|
||||
system.cpu6: completed 30000 read, 16295 write accesses @5776079
|
||||
system.cpu0: completed 30000 read, 16283 write accesses @5776769
|
||||
system.cpu7: completed 30000 read, 16366 write accesses @5874559
|
||||
system.cpu3: completed 40000 read, 21574 write accesses @7627939
|
||||
system.cpu2: completed 40000 read, 21245 write accesses @7628738
|
||||
system.cpu1: completed 40000 read, 21306 write accesses @7628758
|
||||
system.cpu4: completed 40000 read, 21462 write accesses @7660680
|
||||
system.cpu0: completed 40000 read, 21631 write accesses @7675309
|
||||
system.cpu5: completed 40000 read, 21626 write accesses @7680509
|
||||
system.cpu6: completed 40000 read, 21716 write accesses @7696178
|
||||
system.cpu7: completed 40000 read, 21960 write accesses @7863749
|
||||
system.cpu0: completed 50000 read, 26830 write accesses @9562969
|
||||
system.cpu2: completed 50000 read, 26690 write accesses @9565708
|
||||
system.cpu3: completed 50000 read, 26994 write accesses @9575479
|
||||
system.cpu4: completed 50000 read, 26869 write accesses @9589449
|
||||
system.cpu1: completed 50000 read, 26670 write accesses @9611561
|
||||
system.cpu5: completed 50000 read, 27137 write accesses @9617389
|
||||
system.cpu6: completed 50000 read, 27275 write accesses @9658029
|
||||
system.cpu7: completed 50000 read, 27527 write accesses @9814359
|
||||
system.cpu0: completed 60000 read, 32249 write accesses @11423019
|
||||
system.cpu3: completed 60000 read, 32267 write accesses @11433399
|
||||
system.cpu2: completed 60000 read, 32022 write accesses @11474303
|
||||
system.cpu5: completed 60000 read, 32388 write accesses @11521948
|
||||
system.cpu4: completed 60000 read, 32356 write accesses @11528079
|
||||
system.cpu1: completed 60000 read, 32067 write accesses @11544409
|
||||
system.cpu6: completed 60000 read, 32659 write accesses @11548639
|
||||
system.cpu7: completed 60000 read, 32942 write accesses @11779569
|
||||
system.cpu3: completed 70000 read, 37638 write accesses @13336858
|
||||
system.cpu2: completed 70000 read, 37313 write accesses @13368779
|
||||
system.cpu0: completed 70000 read, 37676 write accesses @13377210
|
||||
system.cpu4: completed 70000 read, 37656 write accesses @13416889
|
||||
system.cpu6: completed 70000 read, 38021 write accesses @13465679
|
||||
system.cpu5: completed 70000 read, 37732 write accesses @13467391
|
||||
system.cpu1: completed 70000 read, 37360 write accesses @13477099
|
||||
system.cpu7: completed 70000 read, 38399 write accesses @13717039
|
||||
system.cpu3: completed 80000 read, 42978 write accesses @15269199
|
||||
system.cpu0: completed 80000 read, 42958 write accesses @15278319
|
||||
system.cpu2: completed 80000 read, 42507 write accesses @15310609
|
||||
system.cpu4: completed 80000 read, 42937 write accesses @15325761
|
||||
system.cpu6: completed 80000 read, 43416 write accesses @15354801
|
||||
system.cpu5: completed 80000 read, 43057 write accesses @15376839
|
||||
system.cpu1: completed 80000 read, 42520 write accesses @15380279
|
||||
system.cpu7: completed 80000 read, 43907 write accesses @15634198
|
||||
system.cpu3: completed 90000 read, 48403 write accesses @17192399
|
||||
system.cpu0: completed 90000 read, 48519 write accesses @17230959
|
||||
system.cpu1: completed 90000 read, 47845 write accesses @17249039
|
||||
system.cpu2: completed 90000 read, 47947 write accesses @17255499
|
||||
system.cpu6: completed 90000 read, 48741 write accesses @17263669
|
||||
system.cpu4: completed 90000 read, 48366 write accesses @17269639
|
||||
system.cpu5: completed 90000 read, 48485 write accesses @17297549
|
||||
system.cpu7: completed 90000 read, 49327 write accesses @17576399
|
||||
system.cpu0: completed 100000 read, 53893 write accesses @19129199
|
||||
hack: be nice to actually delete the event here
|
||||
@ -0,0 +1,10 @@
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jun 4 2012 11:51:44
|
||||
gem5 started Jun 4 2012 13:42:34
|
||||
gem5 executing on zizzer
|
||||
command line: build/ALPHA_MOESI_hammer/gem5.opt -d build/ALPHA_MOESI_hammer/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_hammer -re tests/run.py build/ALPHA_MOESI_hammer/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_hammer
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 19129199 because maximum number of loads reached
|
||||
@ -0,0 +1,35 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.019129 # Number of seconds simulated
|
||||
sim_ticks 19129199 # Number of ticks simulated
|
||||
final_tick 19129199 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_tick_rate 171697 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 369968 # Number of bytes of host memory used
|
||||
host_seconds 111.41 # Real time elapsed on the host
|
||||
system.cpu0.num_reads 100000 # number of read accesses completed
|
||||
system.cpu0.num_writes 53893 # number of write accesses completed
|
||||
system.cpu0.num_copies 0 # number of copy accesses completed
|
||||
system.cpu1.num_reads 99845 # number of read accesses completed
|
||||
system.cpu1.num_writes 52936 # number of write accesses completed
|
||||
system.cpu1.num_copies 0 # number of copy accesses completed
|
||||
system.cpu2.num_reads 99959 # number of read accesses completed
|
||||
system.cpu2.num_writes 53318 # number of write accesses completed
|
||||
system.cpu2.num_copies 0 # number of copy accesses completed
|
||||
system.cpu3.num_reads 99709 # number of read accesses completed
|
||||
system.cpu3.num_writes 53594 # number of write accesses completed
|
||||
system.cpu3.num_copies 0 # number of copy accesses completed
|
||||
system.cpu4.num_reads 99622 # number of read accesses completed
|
||||
system.cpu4.num_writes 53609 # number of write accesses completed
|
||||
system.cpu4.num_copies 0 # number of copy accesses completed
|
||||
system.cpu5.num_reads 99608 # number of read accesses completed
|
||||
system.cpu5.num_writes 53591 # number of write accesses completed
|
||||
system.cpu5.num_copies 0 # number of copy accesses completed
|
||||
system.cpu6.num_reads 99715 # number of read accesses completed
|
||||
system.cpu6.num_writes 54030 # number of write accesses completed
|
||||
system.cpu6.num_copies 0 # number of copy accesses completed
|
||||
system.cpu7.num_reads 97913 # number of read accesses completed
|
||||
system.cpu7.num_writes 53717 # number of write accesses completed
|
||||
system.cpu7.num_copies 0 # number of copy accesses completed
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
@ -0,0 +1,819 @@
|
||||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
full_system=false
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000
|
||||
time_sync_spin_threshold=100000
|
||||
|
||||
[system]
|
||||
type=System
|
||||
children=cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 dir_cntrl0 funcmem l1_cntrl0 l1_cntrl1 l1_cntrl2 l1_cntrl3 l1_cntrl4 l1_cntrl5 l1_cntrl6 l1_cntrl7 physmem ruby sys_port_proxy
|
||||
boot_osflags=a
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
mem_mode=timing
|
||||
memories=system.funcmem system.physmem
|
||||
num_work_ids=16
|
||||
readfile=
|
||||
symbolfile=
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.sys_port_proxy.slave[0]
|
||||
|
||||
[system.cpu0]
|
||||
type=MemTest
|
||||
atomic=false
|
||||
issue_dmas=false
|
||||
max_loads=100000
|
||||
memory_size=65536
|
||||
percent_dest_unaligned=50
|
||||
percent_functional=50
|
||||
percent_reads=65
|
||||
percent_source_unaligned=50
|
||||
percent_uncacheable=0
|
||||
progress_interval=10000
|
||||
suppress_func_warnings=true
|
||||
sys=system
|
||||
trace_addr=0
|
||||
functional=system.funcmem.port[0]
|
||||
test=system.l1_cntrl0.sequencer.slave[0]
|
||||
|
||||
[system.cpu1]
|
||||
type=MemTest
|
||||
atomic=false
|
||||
issue_dmas=false
|
||||
max_loads=100000
|
||||
memory_size=65536
|
||||
percent_dest_unaligned=50
|
||||
percent_functional=50
|
||||
percent_reads=65
|
||||
percent_source_unaligned=50
|
||||
percent_uncacheable=0
|
||||
progress_interval=10000
|
||||
suppress_func_warnings=true
|
||||
sys=system
|
||||
trace_addr=0
|
||||
functional=system.funcmem.port[1]
|
||||
test=system.l1_cntrl1.sequencer.slave[0]
|
||||
|
||||
[system.cpu2]
|
||||
type=MemTest
|
||||
atomic=false
|
||||
issue_dmas=false
|
||||
max_loads=100000
|
||||
memory_size=65536
|
||||
percent_dest_unaligned=50
|
||||
percent_functional=50
|
||||
percent_reads=65
|
||||
percent_source_unaligned=50
|
||||
percent_uncacheable=0
|
||||
progress_interval=10000
|
||||
suppress_func_warnings=true
|
||||
sys=system
|
||||
trace_addr=0
|
||||
functional=system.funcmem.port[2]
|
||||
test=system.l1_cntrl2.sequencer.slave[0]
|
||||
|
||||
[system.cpu3]
|
||||
type=MemTest
|
||||
atomic=false
|
||||
issue_dmas=false
|
||||
max_loads=100000
|
||||
memory_size=65536
|
||||
percent_dest_unaligned=50
|
||||
percent_functional=50
|
||||
percent_reads=65
|
||||
percent_source_unaligned=50
|
||||
percent_uncacheable=0
|
||||
progress_interval=10000
|
||||
suppress_func_warnings=true
|
||||
sys=system
|
||||
trace_addr=0
|
||||
functional=system.funcmem.port[3]
|
||||
test=system.l1_cntrl3.sequencer.slave[0]
|
||||
|
||||
[system.cpu4]
|
||||
type=MemTest
|
||||
atomic=false
|
||||
issue_dmas=false
|
||||
max_loads=100000
|
||||
memory_size=65536
|
||||
percent_dest_unaligned=50
|
||||
percent_functional=50
|
||||
percent_reads=65
|
||||
percent_source_unaligned=50
|
||||
percent_uncacheable=0
|
||||
progress_interval=10000
|
||||
suppress_func_warnings=true
|
||||
sys=system
|
||||
trace_addr=0
|
||||
functional=system.funcmem.port[4]
|
||||
test=system.l1_cntrl4.sequencer.slave[0]
|
||||
|
||||
[system.cpu5]
|
||||
type=MemTest
|
||||
atomic=false
|
||||
issue_dmas=false
|
||||
max_loads=100000
|
||||
memory_size=65536
|
||||
percent_dest_unaligned=50
|
||||
percent_functional=50
|
||||
percent_reads=65
|
||||
percent_source_unaligned=50
|
||||
percent_uncacheable=0
|
||||
progress_interval=10000
|
||||
suppress_func_warnings=true
|
||||
sys=system
|
||||
trace_addr=0
|
||||
functional=system.funcmem.port[5]
|
||||
test=system.l1_cntrl5.sequencer.slave[0]
|
||||
|
||||
[system.cpu6]
|
||||
type=MemTest
|
||||
atomic=false
|
||||
issue_dmas=false
|
||||
max_loads=100000
|
||||
memory_size=65536
|
||||
percent_dest_unaligned=50
|
||||
percent_functional=50
|
||||
percent_reads=65
|
||||
percent_source_unaligned=50
|
||||
percent_uncacheable=0
|
||||
progress_interval=10000
|
||||
suppress_func_warnings=true
|
||||
sys=system
|
||||
trace_addr=0
|
||||
functional=system.funcmem.port[6]
|
||||
test=system.l1_cntrl6.sequencer.slave[0]
|
||||
|
||||
[system.cpu7]
|
||||
type=MemTest
|
||||
atomic=false
|
||||
issue_dmas=false
|
||||
max_loads=100000
|
||||
memory_size=65536
|
||||
percent_dest_unaligned=50
|
||||
percent_functional=50
|
||||
percent_reads=65
|
||||
percent_source_unaligned=50
|
||||
percent_uncacheable=0
|
||||
progress_interval=10000
|
||||
suppress_func_warnings=true
|
||||
sys=system
|
||||
trace_addr=0
|
||||
functional=system.funcmem.port[7]
|
||||
test=system.l1_cntrl7.sequencer.slave[0]
|
||||
|
||||
[system.dir_cntrl0]
|
||||
type=Directory_Controller
|
||||
children=directory memBuffer
|
||||
buffer_size=0
|
||||
cntrl_id=8
|
||||
directory=system.dir_cntrl0.directory
|
||||
directory_latency=12
|
||||
memBuffer=system.dir_cntrl0.memBuffer
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
ruby_system=system.ruby
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.dir_cntrl0.directory]
|
||||
type=RubyDirectoryMemory
|
||||
map_levels=4
|
||||
numa_high_bit=6
|
||||
size=268435456
|
||||
use_map=false
|
||||
version=0
|
||||
|
||||
[system.dir_cntrl0.memBuffer]
|
||||
type=RubyMemoryControl
|
||||
bank_bit_0=8
|
||||
bank_busy_time=11
|
||||
bank_queue_size=12
|
||||
banks_per_rank=8
|
||||
basic_bus_busy_time=2
|
||||
dimm_bit_0=12
|
||||
dimms_per_channel=2
|
||||
mem_bus_cycle_multiplier=10
|
||||
mem_ctl_latency=12
|
||||
mem_fixed_delay=0
|
||||
mem_random_arbitrate=0
|
||||
rank_bit_0=11
|
||||
rank_rank_delay=1
|
||||
ranks_per_dimm=2
|
||||
read_write_delay=2
|
||||
refresh_period=1560
|
||||
tFaw=0
|
||||
version=0
|
||||
|
||||
[system.funcmem]
|
||||
type=SimpleMemory
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=false
|
||||
latency=30
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.cpu0.functional system.cpu1.functional system.cpu2.functional system.cpu3.functional system.cpu4.functional system.cpu5.functional system.cpu6.functional system.cpu7.functional
|
||||
|
||||
[system.l1_cntrl0]
|
||||
type=L1Cache_Controller
|
||||
children=cacheMemory sequencer
|
||||
buffer_size=0
|
||||
cacheMemory=system.l1_cntrl0.cacheMemory
|
||||
cache_response_latency=12
|
||||
cntrl_id=0
|
||||
issue_latency=2
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
ruby_system=system.ruby
|
||||
send_evictions=false
|
||||
sequencer=system.l1_cntrl0.sequencer
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.l1_cntrl0.cacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
is_icache=false
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl0.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=false
|
||||
dcache=system.l1_cntrl0.cacheMemory
|
||||
deadlock_threshold=1000000
|
||||
icache=system.l1_cntrl0.cacheMemory
|
||||
max_outstanding_requests=16
|
||||
ruby_system=system.ruby
|
||||
support_data_reqs=true
|
||||
support_inst_reqs=true
|
||||
system=system
|
||||
using_network_tester=false
|
||||
using_ruby_tester=false
|
||||
version=0
|
||||
slave=system.cpu0.test
|
||||
|
||||
[system.l1_cntrl1]
|
||||
type=L1Cache_Controller
|
||||
children=cacheMemory sequencer
|
||||
buffer_size=0
|
||||
cacheMemory=system.l1_cntrl1.cacheMemory
|
||||
cache_response_latency=12
|
||||
cntrl_id=1
|
||||
issue_latency=2
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
ruby_system=system.ruby
|
||||
send_evictions=false
|
||||
sequencer=system.l1_cntrl1.sequencer
|
||||
transitions_per_cycle=32
|
||||
version=1
|
||||
|
||||
[system.l1_cntrl1.cacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
is_icache=false
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl1.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=false
|
||||
dcache=system.l1_cntrl1.cacheMemory
|
||||
deadlock_threshold=1000000
|
||||
icache=system.l1_cntrl1.cacheMemory
|
||||
max_outstanding_requests=16
|
||||
ruby_system=system.ruby
|
||||
support_data_reqs=true
|
||||
support_inst_reqs=true
|
||||
system=system
|
||||
using_network_tester=false
|
||||
using_ruby_tester=false
|
||||
version=1
|
||||
slave=system.cpu1.test
|
||||
|
||||
[system.l1_cntrl2]
|
||||
type=L1Cache_Controller
|
||||
children=cacheMemory sequencer
|
||||
buffer_size=0
|
||||
cacheMemory=system.l1_cntrl2.cacheMemory
|
||||
cache_response_latency=12
|
||||
cntrl_id=2
|
||||
issue_latency=2
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
ruby_system=system.ruby
|
||||
send_evictions=false
|
||||
sequencer=system.l1_cntrl2.sequencer
|
||||
transitions_per_cycle=32
|
||||
version=2
|
||||
|
||||
[system.l1_cntrl2.cacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
is_icache=false
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl2.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=false
|
||||
dcache=system.l1_cntrl2.cacheMemory
|
||||
deadlock_threshold=1000000
|
||||
icache=system.l1_cntrl2.cacheMemory
|
||||
max_outstanding_requests=16
|
||||
ruby_system=system.ruby
|
||||
support_data_reqs=true
|
||||
support_inst_reqs=true
|
||||
system=system
|
||||
using_network_tester=false
|
||||
using_ruby_tester=false
|
||||
version=2
|
||||
slave=system.cpu2.test
|
||||
|
||||
[system.l1_cntrl3]
|
||||
type=L1Cache_Controller
|
||||
children=cacheMemory sequencer
|
||||
buffer_size=0
|
||||
cacheMemory=system.l1_cntrl3.cacheMemory
|
||||
cache_response_latency=12
|
||||
cntrl_id=3
|
||||
issue_latency=2
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
ruby_system=system.ruby
|
||||
send_evictions=false
|
||||
sequencer=system.l1_cntrl3.sequencer
|
||||
transitions_per_cycle=32
|
||||
version=3
|
||||
|
||||
[system.l1_cntrl3.cacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
is_icache=false
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl3.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=false
|
||||
dcache=system.l1_cntrl3.cacheMemory
|
||||
deadlock_threshold=1000000
|
||||
icache=system.l1_cntrl3.cacheMemory
|
||||
max_outstanding_requests=16
|
||||
ruby_system=system.ruby
|
||||
support_data_reqs=true
|
||||
support_inst_reqs=true
|
||||
system=system
|
||||
using_network_tester=false
|
||||
using_ruby_tester=false
|
||||
version=3
|
||||
slave=system.cpu3.test
|
||||
|
||||
[system.l1_cntrl4]
|
||||
type=L1Cache_Controller
|
||||
children=cacheMemory sequencer
|
||||
buffer_size=0
|
||||
cacheMemory=system.l1_cntrl4.cacheMemory
|
||||
cache_response_latency=12
|
||||
cntrl_id=4
|
||||
issue_latency=2
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
ruby_system=system.ruby
|
||||
send_evictions=false
|
||||
sequencer=system.l1_cntrl4.sequencer
|
||||
transitions_per_cycle=32
|
||||
version=4
|
||||
|
||||
[system.l1_cntrl4.cacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
is_icache=false
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl4.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=false
|
||||
dcache=system.l1_cntrl4.cacheMemory
|
||||
deadlock_threshold=1000000
|
||||
icache=system.l1_cntrl4.cacheMemory
|
||||
max_outstanding_requests=16
|
||||
ruby_system=system.ruby
|
||||
support_data_reqs=true
|
||||
support_inst_reqs=true
|
||||
system=system
|
||||
using_network_tester=false
|
||||
using_ruby_tester=false
|
||||
version=4
|
||||
slave=system.cpu4.test
|
||||
|
||||
[system.l1_cntrl5]
|
||||
type=L1Cache_Controller
|
||||
children=cacheMemory sequencer
|
||||
buffer_size=0
|
||||
cacheMemory=system.l1_cntrl5.cacheMemory
|
||||
cache_response_latency=12
|
||||
cntrl_id=5
|
||||
issue_latency=2
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
ruby_system=system.ruby
|
||||
send_evictions=false
|
||||
sequencer=system.l1_cntrl5.sequencer
|
||||
transitions_per_cycle=32
|
||||
version=5
|
||||
|
||||
[system.l1_cntrl5.cacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
is_icache=false
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl5.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=false
|
||||
dcache=system.l1_cntrl5.cacheMemory
|
||||
deadlock_threshold=1000000
|
||||
icache=system.l1_cntrl5.cacheMemory
|
||||
max_outstanding_requests=16
|
||||
ruby_system=system.ruby
|
||||
support_data_reqs=true
|
||||
support_inst_reqs=true
|
||||
system=system
|
||||
using_network_tester=false
|
||||
using_ruby_tester=false
|
||||
version=5
|
||||
slave=system.cpu5.test
|
||||
|
||||
[system.l1_cntrl6]
|
||||
type=L1Cache_Controller
|
||||
children=cacheMemory sequencer
|
||||
buffer_size=0
|
||||
cacheMemory=system.l1_cntrl6.cacheMemory
|
||||
cache_response_latency=12
|
||||
cntrl_id=6
|
||||
issue_latency=2
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
ruby_system=system.ruby
|
||||
send_evictions=false
|
||||
sequencer=system.l1_cntrl6.sequencer
|
||||
transitions_per_cycle=32
|
||||
version=6
|
||||
|
||||
[system.l1_cntrl6.cacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
is_icache=false
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl6.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=false
|
||||
dcache=system.l1_cntrl6.cacheMemory
|
||||
deadlock_threshold=1000000
|
||||
icache=system.l1_cntrl6.cacheMemory
|
||||
max_outstanding_requests=16
|
||||
ruby_system=system.ruby
|
||||
support_data_reqs=true
|
||||
support_inst_reqs=true
|
||||
system=system
|
||||
using_network_tester=false
|
||||
using_ruby_tester=false
|
||||
version=6
|
||||
slave=system.cpu6.test
|
||||
|
||||
[system.l1_cntrl7]
|
||||
type=L1Cache_Controller
|
||||
children=cacheMemory sequencer
|
||||
buffer_size=0
|
||||
cacheMemory=system.l1_cntrl7.cacheMemory
|
||||
cache_response_latency=12
|
||||
cntrl_id=7
|
||||
issue_latency=2
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
ruby_system=system.ruby
|
||||
send_evictions=false
|
||||
sequencer=system.l1_cntrl7.sequencer
|
||||
transitions_per_cycle=32
|
||||
version=7
|
||||
|
||||
[system.l1_cntrl7.cacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
is_icache=false
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl7.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=false
|
||||
dcache=system.l1_cntrl7.cacheMemory
|
||||
deadlock_threshold=1000000
|
||||
icache=system.l1_cntrl7.cacheMemory
|
||||
max_outstanding_requests=16
|
||||
ruby_system=system.ruby
|
||||
support_data_reqs=true
|
||||
support_inst_reqs=true
|
||||
system=system
|
||||
using_network_tester=false
|
||||
using_ruby_tester=false
|
||||
version=7
|
||||
slave=system.cpu7.test
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=30
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
|
||||
[system.ruby]
|
||||
type=RubySystem
|
||||
children=network profiler
|
||||
block_size_bytes=64
|
||||
clock=1
|
||||
mem_size=268435456
|
||||
no_mem_vec=false
|
||||
random_seed=1234
|
||||
randomization=false
|
||||
stats_filename=ruby.stats
|
||||
|
||||
[system.ruby.network]
|
||||
type=SimpleNetwork
|
||||
children=topology
|
||||
adaptive_routing=false
|
||||
buffer_size=0
|
||||
control_msg_size=8
|
||||
endpoint_bandwidth=1000
|
||||
number_of_virtual_networks=10
|
||||
ruby_system=system.ruby
|
||||
topology=system.ruby.network.topology
|
||||
|
||||
[system.ruby.network.topology]
|
||||
type=Topology
|
||||
children=ext_links0 ext_links1 ext_links2 ext_links3 ext_links4 ext_links5 ext_links6 ext_links7 ext_links8 int_links0 int_links1 int_links2 int_links3 int_links4 int_links5 int_links6 int_links7 int_links8 routers0 routers1 routers2 routers3 routers4 routers5 routers6 routers7 routers8 routers9
|
||||
description=Crossbar
|
||||
ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2 system.ruby.network.topology.ext_links3 system.ruby.network.topology.ext_links4 system.ruby.network.topology.ext_links5 system.ruby.network.topology.ext_links6 system.ruby.network.topology.ext_links7 system.ruby.network.topology.ext_links8
|
||||
int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2 system.ruby.network.topology.int_links3 system.ruby.network.topology.int_links4 system.ruby.network.topology.int_links5 system.ruby.network.topology.int_links6 system.ruby.network.topology.int_links7 system.ruby.network.topology.int_links8
|
||||
print_config=false
|
||||
routers=system.ruby.network.topology.routers0 system.ruby.network.topology.routers1 system.ruby.network.topology.routers2 system.ruby.network.topology.routers3 system.ruby.network.topology.routers4 system.ruby.network.topology.routers5 system.ruby.network.topology.routers6 system.ruby.network.topology.routers7 system.ruby.network.topology.routers8 system.ruby.network.topology.routers9
|
||||
|
||||
[system.ruby.network.topology.ext_links0]
|
||||
type=SimpleExtLink
|
||||
bandwidth_factor=16
|
||||
ext_node=system.l1_cntrl0
|
||||
int_node=system.ruby.network.topology.routers0
|
||||
latency=1
|
||||
link_id=0
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links1]
|
||||
type=SimpleExtLink
|
||||
bandwidth_factor=16
|
||||
ext_node=system.l1_cntrl1
|
||||
int_node=system.ruby.network.topology.routers1
|
||||
latency=1
|
||||
link_id=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links2]
|
||||
type=SimpleExtLink
|
||||
bandwidth_factor=16
|
||||
ext_node=system.l1_cntrl2
|
||||
int_node=system.ruby.network.topology.routers2
|
||||
latency=1
|
||||
link_id=2
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links3]
|
||||
type=SimpleExtLink
|
||||
bandwidth_factor=16
|
||||
ext_node=system.l1_cntrl3
|
||||
int_node=system.ruby.network.topology.routers3
|
||||
latency=1
|
||||
link_id=3
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links4]
|
||||
type=SimpleExtLink
|
||||
bandwidth_factor=16
|
||||
ext_node=system.l1_cntrl4
|
||||
int_node=system.ruby.network.topology.routers4
|
||||
latency=1
|
||||
link_id=4
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links5]
|
||||
type=SimpleExtLink
|
||||
bandwidth_factor=16
|
||||
ext_node=system.l1_cntrl5
|
||||
int_node=system.ruby.network.topology.routers5
|
||||
latency=1
|
||||
link_id=5
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links6]
|
||||
type=SimpleExtLink
|
||||
bandwidth_factor=16
|
||||
ext_node=system.l1_cntrl6
|
||||
int_node=system.ruby.network.topology.routers6
|
||||
latency=1
|
||||
link_id=6
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links7]
|
||||
type=SimpleExtLink
|
||||
bandwidth_factor=16
|
||||
ext_node=system.l1_cntrl7
|
||||
int_node=system.ruby.network.topology.routers7
|
||||
latency=1
|
||||
link_id=7
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links8]
|
||||
type=SimpleExtLink
|
||||
bandwidth_factor=16
|
||||
ext_node=system.dir_cntrl0
|
||||
int_node=system.ruby.network.topology.routers8
|
||||
latency=1
|
||||
link_id=8
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.int_links0]
|
||||
type=SimpleIntLink
|
||||
bandwidth_factor=16
|
||||
latency=1
|
||||
link_id=9
|
||||
node_a=system.ruby.network.topology.routers0
|
||||
node_b=system.ruby.network.topology.routers9
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.int_links1]
|
||||
type=SimpleIntLink
|
||||
bandwidth_factor=16
|
||||
latency=1
|
||||
link_id=10
|
||||
node_a=system.ruby.network.topology.routers1
|
||||
node_b=system.ruby.network.topology.routers9
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.int_links2]
|
||||
type=SimpleIntLink
|
||||
bandwidth_factor=16
|
||||
latency=1
|
||||
link_id=11
|
||||
node_a=system.ruby.network.topology.routers2
|
||||
node_b=system.ruby.network.topology.routers9
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.int_links3]
|
||||
type=SimpleIntLink
|
||||
bandwidth_factor=16
|
||||
latency=1
|
||||
link_id=12
|
||||
node_a=system.ruby.network.topology.routers3
|
||||
node_b=system.ruby.network.topology.routers9
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.int_links4]
|
||||
type=SimpleIntLink
|
||||
bandwidth_factor=16
|
||||
latency=1
|
||||
link_id=13
|
||||
node_a=system.ruby.network.topology.routers4
|
||||
node_b=system.ruby.network.topology.routers9
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.int_links5]
|
||||
type=SimpleIntLink
|
||||
bandwidth_factor=16
|
||||
latency=1
|
||||
link_id=14
|
||||
node_a=system.ruby.network.topology.routers5
|
||||
node_b=system.ruby.network.topology.routers9
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.int_links6]
|
||||
type=SimpleIntLink
|
||||
bandwidth_factor=16
|
||||
latency=1
|
||||
link_id=15
|
||||
node_a=system.ruby.network.topology.routers6
|
||||
node_b=system.ruby.network.topology.routers9
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.int_links7]
|
||||
type=SimpleIntLink
|
||||
bandwidth_factor=16
|
||||
latency=1
|
||||
link_id=16
|
||||
node_a=system.ruby.network.topology.routers7
|
||||
node_b=system.ruby.network.topology.routers9
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.int_links8]
|
||||
type=SimpleIntLink
|
||||
bandwidth_factor=16
|
||||
latency=1
|
||||
link_id=17
|
||||
node_a=system.ruby.network.topology.routers8
|
||||
node_b=system.ruby.network.topology.routers9
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.routers0]
|
||||
type=BasicRouter
|
||||
router_id=0
|
||||
|
||||
[system.ruby.network.topology.routers1]
|
||||
type=BasicRouter
|
||||
router_id=1
|
||||
|
||||
[system.ruby.network.topology.routers2]
|
||||
type=BasicRouter
|
||||
router_id=2
|
||||
|
||||
[system.ruby.network.topology.routers3]
|
||||
type=BasicRouter
|
||||
router_id=3
|
||||
|
||||
[system.ruby.network.topology.routers4]
|
||||
type=BasicRouter
|
||||
router_id=4
|
||||
|
||||
[system.ruby.network.topology.routers5]
|
||||
type=BasicRouter
|
||||
router_id=5
|
||||
|
||||
[system.ruby.network.topology.routers6]
|
||||
type=BasicRouter
|
||||
router_id=6
|
||||
|
||||
[system.ruby.network.topology.routers7]
|
||||
type=BasicRouter
|
||||
router_id=7
|
||||
|
||||
[system.ruby.network.topology.routers8]
|
||||
type=BasicRouter
|
||||
router_id=8
|
||||
|
||||
[system.ruby.network.topology.routers9]
|
||||
type=BasicRouter
|
||||
router_id=9
|
||||
|
||||
[system.ruby.profiler]
|
||||
type=RubyProfiler
|
||||
all_instructions=false
|
||||
hot_lines=false
|
||||
num_of_sequencers=8
|
||||
ruby_system=system.ruby
|
||||
|
||||
[system.sys_port_proxy]
|
||||
type=RubyPortProxy
|
||||
access_phys_mem=true
|
||||
ruby_system=system.ruby
|
||||
support_data_reqs=true
|
||||
support_inst_reqs=true
|
||||
system=system
|
||||
using_network_tester=false
|
||||
using_ruby_tester=false
|
||||
version=0
|
||||
slave=system.system_port
|
||||
|
||||
@ -0,0 +1,498 @@
|
||||
|
||||
================ Begin RubySystem Configuration Print ================
|
||||
|
||||
RubySystem config:
|
||||
random_seed: 1234
|
||||
randomization: 0
|
||||
cycle_period: 1
|
||||
block_size_bytes: 64
|
||||
block_size_bits: 6
|
||||
memory_size_bytes: 268435456
|
||||
memory_size_bits: 28
|
||||
|
||||
Network Configuration
|
||||
---------------------
|
||||
network: SIMPLE_NETWORK
|
||||
topology:
|
||||
|
||||
virtual_net_0: active, ordered
|
||||
virtual_net_1: active, ordered
|
||||
virtual_net_2: active, ordered
|
||||
virtual_net_3: active, ordered
|
||||
virtual_net_4: active, ordered
|
||||
virtual_net_5: inactive
|
||||
virtual_net_6: inactive
|
||||
virtual_net_7: inactive
|
||||
virtual_net_8: inactive
|
||||
virtual_net_9: inactive
|
||||
|
||||
|
||||
Profiler Configuration
|
||||
----------------------
|
||||
periodic_stats_period: 1000000
|
||||
|
||||
================ End RubySystem Configuration Print ================
|
||||
|
||||
|
||||
Real time: Jun/04/2012 14:22:53
|
||||
|
||||
Profiler Stats
|
||||
--------------
|
||||
Elapsed_time_in_seconds: 41
|
||||
Elapsed_time_in_minutes: 0.683333
|
||||
Elapsed_time_in_hours: 0.0113889
|
||||
Elapsed_time_in_days: 0.000474537
|
||||
|
||||
Virtual_time_in_seconds: 41.24
|
||||
Virtual_time_in_minutes: 0.687333
|
||||
Virtual_time_in_hours: 0.0114556
|
||||
Virtual_time_in_days: 0.000477315
|
||||
|
||||
Ruby_current_time: 28725020
|
||||
Ruby_start_time: 0
|
||||
Ruby_cycles: 28725020
|
||||
|
||||
mbytes_resident: 60.7461
|
||||
mbytes_total: 361.262
|
||||
resident_ratio: 0.16815
|
||||
|
||||
ruby_cycles_executed: [ 28725021 28725021 28725021 28725021 28725021 28725021 28725021 28725021 ]
|
||||
|
||||
Busy Controller Counts:
|
||||
L1Cache-0:0 L1Cache-1:0 L1Cache-2:0 L1Cache-3:0 L1Cache-4:0 L1Cache-5:0 L1Cache-6:0 L1Cache-7:0
|
||||
|
||||
Directory-0:0
|
||||
|
||||
|
||||
Busy Bank Count:0
|
||||
|
||||
sequencer_requests_outstanding: [binsize: 1 max: 16 count: 615998 average: 15.9984 | standard deviation: 0.126895 | 0 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 615878 ]
|
||||
|
||||
All Non-Zero Cycle Demand Cache Accesses
|
||||
----------------------------------------
|
||||
miss_latency: [binsize: 128 max: 17550 count: 615870 average: 5969.46 | standard deviation: 7116.59 | 0 4 6 6 5 4 5 1 5 4 3 6 4 5 21 31 46 90 169 235 418 648 1027 1394 1760 2694 3780 4717 5558 6535 8753 9589 11125 13750 13954 15292 17133 20395 19978 18654 22068 23938 22152 22290 22426 24096 21689 21471 22547 19077 18860 18264 18773 15923 13248 14135 13631 11388 10257 9512 9377 7381 6802 6677 5240 4722 4293 4074 3235 2564 2639 2296 1833 1614 1375 1233 1052 854 776 591 544 492 453 330 284 288 215 200 140 122 116 82 91 55 52 34 38 32 20 19 15 17 10 8 11 3 5 4 3 1 0 0 1 2 2 1 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_LD: [binsize: 128 max: 17550 count: 400035 average: 5968.22 | standard deviation: 1417.97 | 0 4 3 5 3 2 4 1 2 2 1 2 2 4 14 21 27 59 108 148 275 433 688 907 1155 1771 2429 3013 3676 4199 5764 6270 7293 8986 9054 9918 11064 13179 12948 12115 14336 15590 14383 14461 14549 15708 14037 13915 14593 12436 12325 11870 12195 10304 8534 9247 8896 7405 6689 6174 6004 4768 4401 4309 3422 3106 2791 2621 2096 1647 1749 1478 1176 1060 878 801 692 570 497 397 361 314 289 233 190 190 131 126 85 78 64 59 58 30 29 16 25 20 14 11 10 13 6 4 6 2 3 1 1 0 0 0 1 2 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_ST: [binsize: 128 max: 16420 count: 215835 average: 5971.76 | standard deviation: 1418.95 | 0 0 3 1 2 2 1 0 3 2 2 4 2 1 7 10 19 31 61 87 143 215 339 487 605 923 1351 1704 1882 2336 2989 3319 3832 4764 4900 5374 6069 7216 7030 6539 7732 8348 7769 7829 7877 8388 7652 7556 7954 6641 6535 6394 6578 5619 4714 4888 4735 3983 3568 3338 3373 2613 2401 2368 1818 1616 1502 1453 1139 917 890 818 657 554 497 432 360 284 279 194 183 178 164 97 94 98 84 74 55 44 52 23 33 25 23 18 13 12 6 8 5 4 4 4 5 1 2 3 2 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_Directory: [binsize: 128 max: 17550 count: 607509 average: 5975.88 | standard deviation: 7210.5 | 0 4 6 6 5 4 5 1 5 4 2 6 4 5 17 27 42 88 158 222 402 618 977 1328 1698 2630 3655 4589 5430 6369 8536 9419 10886 13519 13647 15042 16854 20026 19684 18343 21765 23626 21819 22017 22137 23782 21417 21230 22311 18836 18644 18063 18598 15763 13119 14010 13517 11272 10178 9410 9289 7324 6756 6627 5186 4688 4257 4046 3210 2538 2620 2281 1809 1600 1365 1221 1045 850 772 587 539 484 451 326 282 287 213 200 140 121 112 80 90 55 52 34 38 32 20 19 15 17 10 8 11 3 5 4 3 1 0 0 1 2 2 1 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_L1Cache_wCC: [binsize: 64 max: 11892 count: 8361 average: 5503.07 | standard deviation: 1405.32 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 2 2 2 2 1 3 0 2 5 6 7 6 10 6 16 14 19 31 39 27 26 36 23 41 67 58 59 69 63 65 72 94 106 111 94 76 113 126 110 121 152 155 134 116 137 142 173 196 157 137 171 140 153 150 150 162 167 166 135 138 142 147 168 146 131 141 113 128 99 137 136 105 110 106 88 113 83 92 85 75 72 57 65 60 51 63 66 50 39 40 51 51 44 44 31 26 20 26 28 22 29 25 18 16 22 14 12 16 13 12 15 11 12 7 7 8 15 9 5 9 4 6 7 5 4 3 3 1 2 2 3 1 3 2 4 4 1 1 2 2 2 0 1 0 0 2 0 0 0 0 1 0 3 1 1 1 0 1 ]
|
||||
miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
imcomplete_wCC_Times: 8361
|
||||
miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 7 average: 0 | standard deviation: 0 | 7 ]
|
||||
miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 7 average: 0 | standard deviation: 0 | 7 ]
|
||||
miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 7 average: 0 | standard deviation: 0 | 7 ]
|
||||
miss_latency_dir_first_response_to_completion: [binsize: 4 max: 539 count: 7 average: 334.714 | standard deviation: 168.608 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
imcomplete_dir_Times: 607502
|
||||
miss_latency_LD_Directory: [binsize: 128 max: 17550 count: 394629 average: 5974.59 | standard deviation: 1417.29 | 0 4 3 5 3 2 4 1 2 2 0 2 2 4 12 19 26 58 101 141 268 411 656 862 1113 1732 2355 2930 3601 4101 5626 6152 7140 8833 8863 9755 10888 12929 12755 11909 14133 15388 14160 14288 14352 15497 13858 13765 14436 12280 12181 11739 12073 10206 8456 9180 8819 7329 6645 6110 5948 4735 4371 4278 3389 3086 2766 2599 2081 1630 1735 1469 1159 1055 871 794 686 566 493 394 358 310 288 231 189 189 130 126 85 78 62 58 57 30 29 16 25 20 14 11 10 13 6 4 6 2 3 1 1 0 0 0 1 2 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_LD_L1Cache_wCC: [binsize: 64 max: 11892 count: 5406 average: 5502.87 | standard deviation: 1389.98 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1 1 1 0 1 0 1 3 4 6 1 3 4 11 11 12 20 23 22 18 24 18 21 41 33 36 47 39 36 42 56 71 67 63 55 69 84 71 82 98 93 85 78 90 86 118 132 103 90 116 90 106 97 93 109 110 113 88 85 95 102 115 96 79 100 69 81 57 100 89 67 62 82 57 74 55 67 55 43 46 32 35 32 35 42 42 34 22 22 37 27 26 30 18 15 12 18 20 11 14 19 9 11 15 10 10 12 10 5 9 8 10 4 5 4 10 7 2 3 2 5 4 3 4 2 3 1 2 2 2 1 2 1 0 4 0 1 1 1 1 0 1 0 0 1 0 0 0 0 0 0 1 1 0 1 0 1 ]
|
||||
miss_latency_ST_Directory: [binsize: 128 max: 16420 count: 212880 average: 5978.26 | standard deviation: 1417.67 | 0 0 3 1 2 2 1 0 3 2 2 4 2 1 5 8 16 30 57 81 134 207 321 466 585 898 1300 1659 1829 2268 2910 3267 3746 4686 4784 5287 5966 7097 6929 6434 7632 8238 7659 7729 7785 8285 7559 7465 7875 6556 6463 6324 6525 5557 4663 4830 4698 3943 3533 3300 3341 2589 2385 2349 1797 1602 1491 1447 1129 908 885 812 650 545 494 427 359 284 279 193 181 174 163 95 93 98 83 74 55 43 50 22 33 25 23 18 13 12 6 8 5 4 4 4 5 1 2 3 2 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_ST_L1Cache_wCC: [binsize: 64 max: 11673 count: 2955 average: 5503.42 | standard deviation: 1433.2 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 2 0 1 2 2 1 5 7 2 5 3 7 11 16 5 8 12 5 20 26 25 23 22 24 29 30 38 35 44 31 21 44 42 39 39 54 62 49 38 47 56 55 64 54 47 55 50 47 53 57 53 57 53 47 53 47 45 53 50 52 41 44 47 42 37 47 38 48 24 31 39 28 25 30 32 26 25 30 28 16 21 24 16 17 18 14 24 18 14 13 11 8 8 8 11 15 6 9 5 7 4 2 4 3 7 6 3 2 3 2 4 5 2 3 6 2 1 3 2 0 1 0 0 0 0 1 0 1 1 4 0 1 0 1 1 1 0 0 0 0 1 0 0 0 0 1 0 2 0 1 ]
|
||||
|
||||
All Non-Zero Cycle SW Prefetch Requests
|
||||
------------------------------------
|
||||
prefetch_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
prefetch_latency_L2Miss:[binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
Request vs. RubySystem State Profile
|
||||
--------------------------------
|
||||
|
||||
|
||||
filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
||||
Message Delayed Cycles
|
||||
----------------------
|
||||
Total_delay_cycles: [binsize: 1 max: 22 count: 1233888 average: 0.00745367 | standard deviation: 0.17583 | 1231378 88 178 447 1777 0 0 1 0 0 0 0 1 11 0 0 0 0 3 0 0 0 4 ]
|
||||
Total_nonPF_delay_cycles: [binsize: 1 max: 22 count: 1233888 average: 0.00745367 | standard deviation: 0.17583 | 1231378 88 178 447 1777 0 0 1 0 0 0 0 1 11 0 0 0 0 3 0 0 0 4 ]
|
||||
virtual_network_0_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_1_delay_cycles: [binsize: 1 max: 3 count: 615870 average: 0.000342605 | standard deviation: 0.0243446 | 615732 69 65 4 ]
|
||||
virtual_network_2_delay_cycles: [binsize: 1 max: 22 count: 618018 average: 0.01454 | standard deviation: 0.24705 | 615646 19 113 443 1777 0 0 1 0 0 0 0 1 11 0 0 0 0 3 0 0 0 4 ]
|
||||
virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_6_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_7_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_8_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_9_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
||||
Resource Usage
|
||||
--------------
|
||||
page_size: 4096
|
||||
user_time: 41
|
||||
system_time: 0
|
||||
page_reclaims: 15955
|
||||
page_faults: 2
|
||||
swaps: 0
|
||||
block_inputs: 128
|
||||
block_outputs: 184
|
||||
|
||||
Network Stats
|
||||
-------------
|
||||
|
||||
total_msg_count_Control: 1847643 14781144
|
||||
total_msg_count_Data: 1829024 131689728
|
||||
total_msg_count_Response_Data: 1847610 133027920
|
||||
total_msg_count_Writeback_Control: 1854054 14832432
|
||||
total_msgs: 7378331 total_bytes: 294331224
|
||||
|
||||
switch_0_inlinks: 2
|
||||
switch_0_outlinks: 2
|
||||
links_utilized_percent_switch_0: 1.34528
|
||||
links_utilized_percent_switch_0_link_0: 1.34317 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_0_link_1: 1.34738 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_0_link_0_Response_Data: 77136 5553792 [ 0 0 0 0 77136 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Writeback_Control: 77433 619464 [ 0 0 0 77433 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Control: 77138 617104 [ 0 0 77138 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Data: 76420 5502240 [ 0 0 76420 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Response_Data: 1017 73224 [ 0 0 0 0 1017 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_1_inlinks: 2
|
||||
switch_1_outlinks: 2
|
||||
links_utilized_percent_switch_1: 1.34599
|
||||
links_utilized_percent_switch_1_link_0: 1.34421 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_1_link_1: 1.34776 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_1_link_0_Response_Data: 77200 5558400 [ 0 0 0 0 77200 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Writeback_Control: 77452 619616 [ 0 0 0 77452 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Control: 77201 617608 [ 0 0 77201 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Data: 76436 5503392 [ 0 0 76436 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Response_Data: 1018 73296 [ 0 0 0 0 1018 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_2_inlinks: 2
|
||||
switch_2_outlinks: 2
|
||||
links_utilized_percent_switch_2: 1.34111
|
||||
links_utilized_percent_switch_2_link_0: 1.33905 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_2_link_1: 1.34318 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_2_link_0_Response_Data: 76899 5536728 [ 0 0 0 0 76899 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Writeback_Control: 77195 617560 [ 0 0 0 77195 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Control: 76900 615200 [ 0 0 76900 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Data: 76098 5479056 [ 0 0 76098 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Response_Data: 1097 78984 [ 0 0 0 0 1097 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_3_inlinks: 2
|
||||
switch_3_outlinks: 2
|
||||
links_utilized_percent_switch_3: 1.34039
|
||||
links_utilized_percent_switch_3_link_0: 1.33852 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_3_link_1: 1.34225 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_3_link_0_Response_Data: 76872 5534784 [ 0 0 0 0 76872 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_Writeback_Control: 77134 617072 [ 0 0 0 77134 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Control: 76875 615000 [ 0 0 76875 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Data: 76106 5479632 [ 0 0 76106 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Response_Data: 1033 74376 [ 0 0 0 0 1033 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_4_inlinks: 2
|
||||
switch_4_outlinks: 2
|
||||
links_utilized_percent_switch_4: 1.34098
|
||||
links_utilized_percent_switch_4_link_0: 1.33927 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_4_link_1: 1.34269 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_4_link_0_Response_Data: 76917 5538024 [ 0 0 0 0 76917 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_4_link_0_Writeback_Control: 77161 617288 [ 0 0 0 77161 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_4_link_1_Control: 76918 615344 [ 0 0 76918 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_4_link_1_Data: 76104 5479488 [ 0 0 76104 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_4_link_1_Response_Data: 1058 76176 [ 0 0 0 0 1058 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_5_inlinks: 2
|
||||
switch_5_outlinks: 2
|
||||
links_utilized_percent_switch_5: 1.34326
|
||||
links_utilized_percent_switch_5_link_0: 1.34149 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_5_link_1: 1.34504 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_5_link_0_Response_Data: 77043 5547096 [ 0 0 0 0 77043 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_0_Writeback_Control: 77297 618376 [ 0 0 0 77297 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_1_Control: 77044 616352 [ 0 0 77044 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_1_Data: 76280 5492160 [ 0 0 76280 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_1_Response_Data: 1018 73296 [ 0 0 0 0 1018 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_6_inlinks: 2
|
||||
switch_6_outlinks: 2
|
||||
links_utilized_percent_switch_6: 1.33528
|
||||
links_utilized_percent_switch_6_link_0: 1.33337 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_6_link_1: 1.33719 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_6_link_0_Response_Data: 76575 5513400 [ 0 0 0 0 76575 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_6_link_0_Writeback_Control: 76846 614768 [ 0 0 0 76846 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_6_link_1_Control: 76576 612608 [ 0 0 76576 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_6_link_1_Data: 75797 5457384 [ 0 0 75797 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_6_link_1_Response_Data: 1052 75744 [ 0 0 0 0 1052 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_7_inlinks: 2
|
||||
switch_7_outlinks: 2
|
||||
links_utilized_percent_switch_7: 1.34665
|
||||
links_utilized_percent_switch_7_link_0: 1.34474 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_7_link_1: 1.34856 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_7_link_0_Response_Data: 77228 5560416 [ 0 0 0 0 77228 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_7_link_0_Writeback_Control: 77500 620000 [ 0 0 0 77500 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_7_link_1_Control: 77229 617832 [ 0 0 77229 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_7_link_1_Data: 76434 5503248 [ 0 0 76434 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_7_link_1_Response_Data: 1068 76896 [ 0 0 0 0 1068 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_8_inlinks: 2
|
||||
switch_8_outlinks: 2
|
||||
links_utilized_percent_switch_8: 10.608
|
||||
links_utilized_percent_switch_8_link_0: 10.6231 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_8_link_1: 10.5929 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_8_link_0_Control: 615881 4927048 [ 0 0 615881 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_8_link_0_Data: 609674 43896528 [ 0 0 609674 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_8_link_1_Response_Data: 607509 43740648 [ 0 0 0 0 607509 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_8_link_1_Writeback_Control: 618018 4944144 [ 0 0 0 618018 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_9_inlinks: 9
|
||||
switch_9_outlinks: 9
|
||||
links_utilized_percent_switch_9: 2.37188
|
||||
links_utilized_percent_switch_9_link_0: 1.34318 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_9_link_1: 1.34421 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_9_link_2: 1.33905 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_9_link_3: 1.33852 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_9_link_4: 1.33927 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_9_link_5: 1.34149 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_9_link_6: 1.33337 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_9_link_7: 1.34474 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_9_link_8: 10.6231 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_9_link_0_Response_Data: 77136 5553792 [ 0 0 0 0 77136 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_0_Writeback_Control: 77433 619464 [ 0 0 0 77433 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_1_Response_Data: 77200 5558400 [ 0 0 0 0 77200 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_1_Writeback_Control: 77452 619616 [ 0 0 0 77452 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_2_Response_Data: 76899 5536728 [ 0 0 0 0 76899 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_2_Writeback_Control: 77195 617560 [ 0 0 0 77195 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_3_Response_Data: 76872 5534784 [ 0 0 0 0 76872 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_3_Writeback_Control: 77134 617072 [ 0 0 0 77134 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_4_Response_Data: 76917 5538024 [ 0 0 0 0 76917 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_4_Writeback_Control: 77161 617288 [ 0 0 0 77161 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_5_Response_Data: 77043 5547096 [ 0 0 0 0 77043 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_5_Writeback_Control: 77297 618376 [ 0 0 0 77297 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_6_Response_Data: 76575 5513400 [ 0 0 0 0 76575 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_6_Writeback_Control: 76846 614768 [ 0 0 0 76846 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_7_Response_Data: 77228 5560416 [ 0 0 0 0 77228 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_7_Writeback_Control: 77500 620000 [ 0 0 0 77500 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_8_Control: 615881 4927048 [ 0 0 615881 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_8_Data: 609675 43896600 [ 0 0 609675 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
Cache Stats: system.l1_cntrl0.cacheMemory
|
||||
system.l1_cntrl0.cacheMemory_total_misses: 77138
|
||||
system.l1_cntrl0.cacheMemory_total_demand_misses: 77138
|
||||
system.l1_cntrl0.cacheMemory_total_prefetches: 0
|
||||
system.l1_cntrl0.cacheMemory_total_sw_prefetches: 0
|
||||
system.l1_cntrl0.cacheMemory_total_hw_prefetches: 0
|
||||
|
||||
system.l1_cntrl0.cacheMemory_request_type_LD: 65.2065%
|
||||
system.l1_cntrl0.cacheMemory_request_type_ST: 34.7935%
|
||||
|
||||
system.l1_cntrl0.cacheMemory_access_mode_type_Supervisor: 77138 100%
|
||||
|
||||
--- L1Cache ---
|
||||
- Event Counts -
|
||||
Load [50062 49936 49885 50169 50299 50006 49692 49994 ] 400043
|
||||
Ifetch [0 0 0 0 0 0 0 0 ] 0
|
||||
Store [26856 27108 26691 27060 26839 27195 27208 26882 ] 215839
|
||||
Data [76917 77043 76575 77228 77136 77200 76899 76872 ] 615870
|
||||
Fwd_GETX [1058 1018 1052 1068 1017 1018 1097 1033 ] 8361
|
||||
Inv [0 0 0 0 0 0 0 0 ] 0
|
||||
Replacement [76914 77040 76572 77225 77134 77197 76896 76872 ] 615850
|
||||
Writeback_Ack [75855 76021 75517 76155 76113 76177 75799 75834 ] 607471
|
||||
Writeback_Nack [248 258 277 277 303 257 299 267 ] 2186
|
||||
|
||||
- Transitions -
|
||||
I Load [50062 49936 49885 50169 50299 50006 49692 49994 ] 400043
|
||||
I Ifetch [0 0 0 0 0 0 0 0 ] 0
|
||||
I Store [26856 27108 26691 27060 26839 27195 27208 26882 ] 215839
|
||||
I Inv [0 0 0 0 0 0 0 0 ] 0
|
||||
I Replacement [810 760 775 791 714 761 798 766 ] 6175
|
||||
|
||||
II Writeback_Nack [248 258 277 277 303 257 299 267 ] 2186
|
||||
|
||||
M Load [0 0 0 0 0 0 0 0 ] 0
|
||||
M Ifetch [0 0 0 0 0 0 0 0 ] 0
|
||||
M Store [0 0 0 0 0 0 0 0 ] 0
|
||||
M Fwd_GETX [810 760 775 791 714 761 798 766 ] 6175
|
||||
M Inv [0 0 0 0 0 0 0 0 ] 0
|
||||
M Replacement [76104 76280 75797 76434 76420 76436 76098 76106 ] 609675
|
||||
|
||||
MI Fwd_GETX [248 258 277 277 303 257 299 267 ] 2186
|
||||
MI Inv [0 0 0 0 0 0 0 0 ] 0
|
||||
MI Writeback_Ack [75855 76021 75517 76155 76113 76177 75799 75834 ] 607471
|
||||
MI Writeback_Nack [0 0 0 0 0 0 0 0 ] 0
|
||||
|
||||
MII Fwd_GETX [0 0 0 0 0 0 0 0 ] 0
|
||||
|
||||
IS Data [50061 49936 49885 50168 50297 50005 49691 49992 ] 400035
|
||||
|
||||
IM Data [26856 27107 26690 27060 26839 27195 27208 26880 ] 215835
|
||||
|
||||
Cache Stats: system.l1_cntrl1.cacheMemory
|
||||
system.l1_cntrl1.cacheMemory_total_misses: 77201
|
||||
system.l1_cntrl1.cacheMemory_total_demand_misses: 77201
|
||||
system.l1_cntrl1.cacheMemory_total_prefetches: 0
|
||||
system.l1_cntrl1.cacheMemory_total_sw_prefetches: 0
|
||||
system.l1_cntrl1.cacheMemory_total_hw_prefetches: 0
|
||||
|
||||
system.l1_cntrl1.cacheMemory_request_type_LD: 64.7738%
|
||||
system.l1_cntrl1.cacheMemory_request_type_ST: 35.2262%
|
||||
|
||||
system.l1_cntrl1.cacheMemory_access_mode_type_Supervisor: 77201 100%
|
||||
|
||||
Cache Stats: system.l1_cntrl2.cacheMemory
|
||||
system.l1_cntrl2.cacheMemory_total_misses: 76900
|
||||
system.l1_cntrl2.cacheMemory_total_demand_misses: 76900
|
||||
system.l1_cntrl2.cacheMemory_total_prefetches: 0
|
||||
system.l1_cntrl2.cacheMemory_total_sw_prefetches: 0
|
||||
system.l1_cntrl2.cacheMemory_total_hw_prefetches: 0
|
||||
|
||||
system.l1_cntrl2.cacheMemory_request_type_LD: 64.619%
|
||||
system.l1_cntrl2.cacheMemory_request_type_ST: 35.381%
|
||||
|
||||
system.l1_cntrl2.cacheMemory_access_mode_type_Supervisor: 76900 100%
|
||||
|
||||
Cache Stats: system.l1_cntrl3.cacheMemory
|
||||
system.l1_cntrl3.cacheMemory_total_misses: 76876
|
||||
system.l1_cntrl3.cacheMemory_total_demand_misses: 76876
|
||||
system.l1_cntrl3.cacheMemory_total_prefetches: 0
|
||||
system.l1_cntrl3.cacheMemory_total_sw_prefetches: 0
|
||||
system.l1_cntrl3.cacheMemory_total_hw_prefetches: 0
|
||||
|
||||
system.l1_cntrl3.cacheMemory_request_type_LD: 65.032%
|
||||
system.l1_cntrl3.cacheMemory_request_type_ST: 34.968%
|
||||
|
||||
system.l1_cntrl3.cacheMemory_access_mode_type_Supervisor: 76876 100%
|
||||
|
||||
Cache Stats: system.l1_cntrl4.cacheMemory
|
||||
system.l1_cntrl4.cacheMemory_total_misses: 76918
|
||||
system.l1_cntrl4.cacheMemory_total_demand_misses: 76918
|
||||
system.l1_cntrl4.cacheMemory_total_prefetches: 0
|
||||
system.l1_cntrl4.cacheMemory_total_sw_prefetches: 0
|
||||
system.l1_cntrl4.cacheMemory_total_hw_prefetches: 0
|
||||
|
||||
system.l1_cntrl4.cacheMemory_request_type_LD: 65.0849%
|
||||
system.l1_cntrl4.cacheMemory_request_type_ST: 34.9151%
|
||||
|
||||
system.l1_cntrl4.cacheMemory_access_mode_type_Supervisor: 76918 100%
|
||||
|
||||
Cache Stats: system.l1_cntrl5.cacheMemory
|
||||
system.l1_cntrl5.cacheMemory_total_misses: 77044
|
||||
system.l1_cntrl5.cacheMemory_total_demand_misses: 77044
|
||||
system.l1_cntrl5.cacheMemory_total_prefetches: 0
|
||||
system.l1_cntrl5.cacheMemory_total_sw_prefetches: 0
|
||||
system.l1_cntrl5.cacheMemory_total_hw_prefetches: 0
|
||||
|
||||
system.l1_cntrl5.cacheMemory_request_type_LD: 64.8149%
|
||||
system.l1_cntrl5.cacheMemory_request_type_ST: 35.1851%
|
||||
|
||||
system.l1_cntrl5.cacheMemory_access_mode_type_Supervisor: 77044 100%
|
||||
|
||||
Cache Stats: system.l1_cntrl6.cacheMemory
|
||||
system.l1_cntrl6.cacheMemory_total_misses: 76576
|
||||
system.l1_cntrl6.cacheMemory_total_demand_misses: 76576
|
||||
system.l1_cntrl6.cacheMemory_total_prefetches: 0
|
||||
system.l1_cntrl6.cacheMemory_total_sw_prefetches: 0
|
||||
system.l1_cntrl6.cacheMemory_total_hw_prefetches: 0
|
||||
|
||||
system.l1_cntrl6.cacheMemory_request_type_LD: 65.1444%
|
||||
system.l1_cntrl6.cacheMemory_request_type_ST: 34.8556%
|
||||
|
||||
system.l1_cntrl6.cacheMemory_access_mode_type_Supervisor: 76576 100%
|
||||
|
||||
Cache Stats: system.l1_cntrl7.cacheMemory
|
||||
system.l1_cntrl7.cacheMemory_total_misses: 77229
|
||||
system.l1_cntrl7.cacheMemory_total_demand_misses: 77229
|
||||
system.l1_cntrl7.cacheMemory_total_prefetches: 0
|
||||
system.l1_cntrl7.cacheMemory_total_sw_prefetches: 0
|
||||
system.l1_cntrl7.cacheMemory_total_hw_prefetches: 0
|
||||
|
||||
system.l1_cntrl7.cacheMemory_request_type_LD: 64.9613%
|
||||
system.l1_cntrl7.cacheMemory_request_type_ST: 35.0387%
|
||||
|
||||
system.l1_cntrl7.cacheMemory_access_mode_type_Supervisor: 77229 100%
|
||||
|
||||
Memory controller: system.dir_cntrl0.memBuffer:
|
||||
memory_total_requests: 1215007
|
||||
memory_reads: 607514
|
||||
memory_writes: 607471
|
||||
memory_refreshes: 59844
|
||||
memory_total_request_delays: 94490839
|
||||
memory_delays_per_request: 77.7698
|
||||
memory_delays_in_input_queue: 4956280
|
||||
memory_delays_behind_head_of_bank_queue: 42721539
|
||||
memory_delays_stalled_at_head_of_bank_queue: 46813020
|
||||
memory_stalls_for_bank_busy: 7203781
|
||||
memory_stalls_for_random_busy: 0
|
||||
memory_stalls_for_anti_starvation: 12030630
|
||||
memory_stalls_for_arbitration: 9262268
|
||||
memory_stalls_for_bus: 12663868
|
||||
memory_stalls_for_tfaw: 0
|
||||
memory_stalls_for_read_write_turnaround: 4593756
|
||||
memory_stalls_for_read_read_turnaround: 1058717
|
||||
accesses_per_bank: 38064 37906 37810 38185 38131 38139 38459 38015 38286 38038 38075 38326 37705 37695 37985 37984 37848 37764 37931 38109 38114 37875 38032 37917 37934 37358 38024 37068 37768 38020 38377 38065
|
||||
|
||||
--- Directory ---
|
||||
- Event Counts -
|
||||
GETX [1243024 ] 1243024
|
||||
GETS [0 ] 0
|
||||
PUTX [607488 ] 607488
|
||||
PUTX_NotOwner [2186 ] 2186
|
||||
DMA_READ [0 ] 0
|
||||
DMA_WRITE [0 ] 0
|
||||
Memory_Data [607509 ] 607509
|
||||
Memory_Ack [607471 ] 607471
|
||||
|
||||
- Transitions -
|
||||
I GETX [607519 ] 607519
|
||||
I PUTX_NotOwner [0 ] 0
|
||||
I DMA_READ [0 ] 0
|
||||
I DMA_WRITE [0 ] 0
|
||||
|
||||
M GETX [8361 ] 8361
|
||||
M PUTX [607488 ] 607488
|
||||
M PUTX_NotOwner [2186 ] 2186
|
||||
M DMA_READ [0 ] 0
|
||||
M DMA_WRITE [0 ] 0
|
||||
|
||||
M_DRD GETX [0 ] 0
|
||||
M_DRD PUTX [0 ] 0
|
||||
|
||||
M_DWR GETX [0 ] 0
|
||||
M_DWR PUTX [0 ] 0
|
||||
|
||||
M_DWRI GETX [0 ] 0
|
||||
M_DWRI Memory_Ack [0 ] 0
|
||||
|
||||
M_DRDI GETX [0 ] 0
|
||||
M_DRDI Memory_Ack [0 ] 0
|
||||
|
||||
IM GETX [250002 ] 250002
|
||||
IM GETS [0 ] 0
|
||||
IM PUTX [0 ] 0
|
||||
IM PUTX_NotOwner [0 ] 0
|
||||
IM DMA_READ [0 ] 0
|
||||
IM DMA_WRITE [0 ] 0
|
||||
IM Memory_Data [607509 ] 607509
|
||||
|
||||
MI GETX [377142 ] 377142
|
||||
MI GETS [0 ] 0
|
||||
MI PUTX [0 ] 0
|
||||
MI PUTX_NotOwner [0 ] 0
|
||||
MI DMA_READ [0 ] 0
|
||||
MI DMA_WRITE [0 ] 0
|
||||
MI Memory_Ack [607471 ] 607471
|
||||
|
||||
ID GETX [0 ] 0
|
||||
ID GETS [0 ] 0
|
||||
ID PUTX [0 ] 0
|
||||
ID PUTX_NotOwner [0 ] 0
|
||||
ID DMA_READ [0 ] 0
|
||||
ID DMA_WRITE [0 ] 0
|
||||
ID Memory_Data [0 ] 0
|
||||
|
||||
ID_W GETX [0 ] 0
|
||||
ID_W GETS [0 ] 0
|
||||
ID_W PUTX [0 ] 0
|
||||
ID_W PUTX_NotOwner [0 ] 0
|
||||
ID_W DMA_READ [0 ] 0
|
||||
ID_W DMA_WRITE [0 ] 0
|
||||
ID_W Memory_Ack [0 ] 0
|
||||
|
||||
@ -0,0 +1,74 @@
|
||||
system.cpu5: completed 10000 read, 5419 write accesses @2858002
|
||||
system.cpu7: completed 10000 read, 5473 write accesses @2858520
|
||||
system.cpu0: completed 10000 read, 5305 write accesses @2868940
|
||||
system.cpu1: completed 10000 read, 5416 write accesses @2893421
|
||||
system.cpu4: completed 10000 read, 5371 write accesses @2900102
|
||||
system.cpu2: completed 10000 read, 5337 write accesses @2905419
|
||||
system.cpu3: completed 10000 read, 5513 write accesses @2916882
|
||||
system.cpu6: completed 10000 read, 5458 write accesses @2971509
|
||||
system.cpu1: completed 20000 read, 10866 write accesses @5727829
|
||||
system.cpu0: completed 20000 read, 10592 write accesses @5734440
|
||||
system.cpu4: completed 20000 read, 10679 write accesses @5748810
|
||||
system.cpu7: completed 20000 read, 10819 write accesses @5759030
|
||||
system.cpu3: completed 20000 read, 10666 write accesses @5769940
|
||||
system.cpu5: completed 20000 read, 10771 write accesses @5778709
|
||||
system.cpu6: completed 20000 read, 10832 write accesses @5805350
|
||||
system.cpu2: completed 20000 read, 10785 write accesses @5828740
|
||||
system.cpu1: completed 30000 read, 16207 write accesses @8557570
|
||||
system.cpu0: completed 30000 read, 15949 write accesses @8566069
|
||||
system.cpu7: completed 30000 read, 16214 write accesses @8624139
|
||||
system.cpu4: completed 30000 read, 16127 write accesses @8660230
|
||||
system.cpu3: completed 30000 read, 16038 write accesses @8676099
|
||||
system.cpu5: completed 30000 read, 16217 write accesses @8736099
|
||||
system.cpu6: completed 30000 read, 16240 write accesses @8737471
|
||||
system.cpu2: completed 30000 read, 16356 write accesses @8775610
|
||||
system.cpu4: completed 40000 read, 21442 write accesses @11430710
|
||||
system.cpu1: completed 40000 read, 21431 write accesses @11446880
|
||||
system.cpu0: completed 40000 read, 21249 write accesses @11450119
|
||||
system.cpu7: completed 40000 read, 21591 write accesses @11495090
|
||||
system.cpu3: completed 40000 read, 21525 write accesses @11637130
|
||||
system.cpu6: completed 40000 read, 21625 write accesses @11655440
|
||||
system.cpu5: completed 40000 read, 21557 write accesses @11655900
|
||||
system.cpu2: completed 40000 read, 22064 write accesses @11762920
|
||||
system.cpu0: completed 50000 read, 26643 write accesses @14301920
|
||||
system.cpu7: completed 50000 read, 26956 write accesses @14350920
|
||||
system.cpu1: completed 50000 read, 26912 write accesses @14419140
|
||||
system.cpu4: completed 50000 read, 27035 write accesses @14428630
|
||||
system.cpu3: completed 50000 read, 26875 write accesses @14456189
|
||||
system.cpu6: completed 50000 read, 26968 write accesses @14552960
|
||||
system.cpu5: completed 50000 read, 27033 write accesses @14560100
|
||||
system.cpu2: completed 50000 read, 27494 write accesses @14706770
|
||||
system.cpu0: completed 60000 read, 32018 write accesses @17124880
|
||||
system.cpu7: completed 60000 read, 32300 write accesses @17213372
|
||||
system.cpu3: completed 60000 read, 32247 write accesses @17322589
|
||||
system.cpu4: completed 60000 read, 32351 write accesses @17326542
|
||||
system.cpu1: completed 60000 read, 32302 write accesses @17368660
|
||||
system.cpu6: completed 60000 read, 32274 write accesses @17446980
|
||||
system.cpu5: completed 60000 read, 32418 write accesses @17468540
|
||||
system.cpu2: completed 60000 read, 32981 write accesses @17554781
|
||||
system.cpu0: completed 70000 read, 37316 write accesses @19965899
|
||||
system.cpu7: completed 70000 read, 37727 write accesses @20108089
|
||||
system.cpu4: completed 70000 read, 37633 write accesses @20233790
|
||||
system.cpu1: completed 70000 read, 37821 write accesses @20289790
|
||||
system.cpu3: completed 70000 read, 37645 write accesses @20291829
|
||||
system.cpu6: completed 70000 read, 37499 write accesses @20304889
|
||||
system.cpu5: completed 70000 read, 37769 write accesses @20345680
|
||||
system.cpu2: completed 70000 read, 38246 write accesses @20384949
|
||||
system.cpu0: completed 80000 read, 42438 write accesses @22835499
|
||||
system.cpu7: completed 80000 read, 43085 write accesses @23031949
|
||||
system.cpu4: completed 80000 read, 42968 write accesses @23134444
|
||||
system.cpu3: completed 80000 read, 42908 write accesses @23138450
|
||||
system.cpu1: completed 80000 read, 43002 write accesses @23183439
|
||||
system.cpu6: completed 80000 read, 42955 write accesses @23224650
|
||||
system.cpu2: completed 80000 read, 43596 write accesses @23229730
|
||||
system.cpu5: completed 80000 read, 43242 write accesses @23231600
|
||||
system.cpu0: completed 90000 read, 47763 write accesses @25792220
|
||||
system.cpu7: completed 90000 read, 48675 write accesses @25948310
|
||||
system.cpu3: completed 90000 read, 48223 write accesses @26022110
|
||||
system.cpu4: completed 90000 read, 48406 write accesses @26054041
|
||||
system.cpu6: completed 90000 read, 48309 write accesses @26074843
|
||||
system.cpu2: completed 90000 read, 49141 write accesses @26106590
|
||||
system.cpu5: completed 90000 read, 48681 write accesses @26106730
|
||||
system.cpu1: completed 90000 read, 48449 write accesses @26117229
|
||||
system.cpu0: completed 100000 read, 53147 write accesses @28725020
|
||||
hack: be nice to actually delete the event here
|
||||
@ -0,0 +1,10 @@
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jun 4 2012 11:50:11
|
||||
gem5 started Jun 4 2012 14:22:12
|
||||
gem5 executing on zizzer
|
||||
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby -re tests/run.py build/ALPHA/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 28725020 because maximum number of loads reached
|
||||
@ -0,0 +1,35 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.028725 # Number of seconds simulated
|
||||
sim_ticks 28725020 # Number of ticks simulated
|
||||
final_tick 28725020 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_tick_rate 699351 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 369936 # Number of bytes of host memory used
|
||||
host_seconds 41.07 # Real time elapsed on the host
|
||||
system.cpu0.num_reads 100000 # number of read accesses completed
|
||||
system.cpu0.num_writes 53147 # number of write accesses completed
|
||||
system.cpu0.num_copies 0 # number of copy accesses completed
|
||||
system.cpu1.num_reads 99027 # number of read accesses completed
|
||||
system.cpu1.num_writes 53354 # number of write accesses completed
|
||||
system.cpu1.num_copies 0 # number of copy accesses completed
|
||||
system.cpu2.num_reads 98992 # number of read accesses completed
|
||||
system.cpu2.num_writes 53956 # number of write accesses completed
|
||||
system.cpu2.num_copies 0 # number of copy accesses completed
|
||||
system.cpu3.num_reads 99374 # number of read accesses completed
|
||||
system.cpu3.num_writes 53181 # number of write accesses completed
|
||||
system.cpu3.num_copies 0 # number of copy accesses completed
|
||||
system.cpu4.num_reads 99392 # number of read accesses completed
|
||||
system.cpu4.num_writes 53489 # number of write accesses completed
|
||||
system.cpu4.num_copies 0 # number of copy accesses completed
|
||||
system.cpu5.num_reads 99177 # number of read accesses completed
|
||||
system.cpu5.num_writes 53605 # number of write accesses completed
|
||||
system.cpu5.num_copies 0 # number of copy accesses completed
|
||||
system.cpu6.num_reads 99055 # number of read accesses completed
|
||||
system.cpu6.num_writes 53188 # number of write accesses completed
|
||||
system.cpu6.num_copies 0 # number of copy accesses completed
|
||||
system.cpu7.num_reads 99520 # number of read accesses completed
|
||||
system.cpu7.num_writes 53821 # number of write accesses completed
|
||||
system.cpu7.num_copies 0 # number of copy accesses completed
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
@ -0,0 +1,450 @@
|
||||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
full_system=false
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
||||
[system]
|
||||
type=System
|
||||
children=cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 funcmem l2c membus physmem toL2Bus
|
||||
boot_osflags=a
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
mem_mode=timing
|
||||
memories=system.physmem system.funcmem
|
||||
num_work_ids=16
|
||||
readfile=
|
||||
symbolfile=
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.membus.slave[1]
|
||||
|
||||
[system.cpu0]
|
||||
type=MemTest
|
||||
children=l1c
|
||||
atomic=false
|
||||
issue_dmas=false
|
||||
max_loads=100000
|
||||
memory_size=65536
|
||||
percent_dest_unaligned=50
|
||||
percent_functional=50
|
||||
percent_reads=65
|
||||
percent_source_unaligned=50
|
||||
percent_uncacheable=10
|
||||
progress_interval=10000
|
||||
suppress_func_warnings=false
|
||||
sys=system
|
||||
trace_addr=0
|
||||
functional=system.funcmem.port[0]
|
||||
test=system.cpu0.l1c.cpu_side
|
||||
|
||||
[system.cpu0.l1c]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=4
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=12
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=32768
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=8
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu0.test
|
||||
mem_side=system.toL2Bus.slave[0]
|
||||
|
||||
[system.cpu1]
|
||||
type=MemTest
|
||||
children=l1c
|
||||
atomic=false
|
||||
issue_dmas=false
|
||||
max_loads=100000
|
||||
memory_size=65536
|
||||
percent_dest_unaligned=50
|
||||
percent_functional=50
|
||||
percent_reads=65
|
||||
percent_source_unaligned=50
|
||||
percent_uncacheable=10
|
||||
progress_interval=10000
|
||||
suppress_func_warnings=false
|
||||
sys=system
|
||||
trace_addr=0
|
||||
functional=system.funcmem.port[1]
|
||||
test=system.cpu1.l1c.cpu_side
|
||||
|
||||
[system.cpu1.l1c]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=4
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=12
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=32768
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=8
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu1.test
|
||||
mem_side=system.toL2Bus.slave[1]
|
||||
|
||||
[system.cpu2]
|
||||
type=MemTest
|
||||
children=l1c
|
||||
atomic=false
|
||||
issue_dmas=false
|
||||
max_loads=100000
|
||||
memory_size=65536
|
||||
percent_dest_unaligned=50
|
||||
percent_functional=50
|
||||
percent_reads=65
|
||||
percent_source_unaligned=50
|
||||
percent_uncacheable=10
|
||||
progress_interval=10000
|
||||
suppress_func_warnings=false
|
||||
sys=system
|
||||
trace_addr=0
|
||||
functional=system.funcmem.port[2]
|
||||
test=system.cpu2.l1c.cpu_side
|
||||
|
||||
[system.cpu2.l1c]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=4
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=12
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=32768
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=8
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu2.test
|
||||
mem_side=system.toL2Bus.slave[2]
|
||||
|
||||
[system.cpu3]
|
||||
type=MemTest
|
||||
children=l1c
|
||||
atomic=false
|
||||
issue_dmas=false
|
||||
max_loads=100000
|
||||
memory_size=65536
|
||||
percent_dest_unaligned=50
|
||||
percent_functional=50
|
||||
percent_reads=65
|
||||
percent_source_unaligned=50
|
||||
percent_uncacheable=10
|
||||
progress_interval=10000
|
||||
suppress_func_warnings=false
|
||||
sys=system
|
||||
trace_addr=0
|
||||
functional=system.funcmem.port[3]
|
||||
test=system.cpu3.l1c.cpu_side
|
||||
|
||||
[system.cpu3.l1c]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=4
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=12
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=32768
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=8
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu3.test
|
||||
mem_side=system.toL2Bus.slave[3]
|
||||
|
||||
[system.cpu4]
|
||||
type=MemTest
|
||||
children=l1c
|
||||
atomic=false
|
||||
issue_dmas=false
|
||||
max_loads=100000
|
||||
memory_size=65536
|
||||
percent_dest_unaligned=50
|
||||
percent_functional=50
|
||||
percent_reads=65
|
||||
percent_source_unaligned=50
|
||||
percent_uncacheable=10
|
||||
progress_interval=10000
|
||||
suppress_func_warnings=false
|
||||
sys=system
|
||||
trace_addr=0
|
||||
functional=system.funcmem.port[4]
|
||||
test=system.cpu4.l1c.cpu_side
|
||||
|
||||
[system.cpu4.l1c]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=4
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=12
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=32768
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=8
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu4.test
|
||||
mem_side=system.toL2Bus.slave[4]
|
||||
|
||||
[system.cpu5]
|
||||
type=MemTest
|
||||
children=l1c
|
||||
atomic=false
|
||||
issue_dmas=false
|
||||
max_loads=100000
|
||||
memory_size=65536
|
||||
percent_dest_unaligned=50
|
||||
percent_functional=50
|
||||
percent_reads=65
|
||||
percent_source_unaligned=50
|
||||
percent_uncacheable=10
|
||||
progress_interval=10000
|
||||
suppress_func_warnings=false
|
||||
sys=system
|
||||
trace_addr=0
|
||||
functional=system.funcmem.port[5]
|
||||
test=system.cpu5.l1c.cpu_side
|
||||
|
||||
[system.cpu5.l1c]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=4
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=12
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=32768
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=8
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu5.test
|
||||
mem_side=system.toL2Bus.slave[5]
|
||||
|
||||
[system.cpu6]
|
||||
type=MemTest
|
||||
children=l1c
|
||||
atomic=false
|
||||
issue_dmas=false
|
||||
max_loads=100000
|
||||
memory_size=65536
|
||||
percent_dest_unaligned=50
|
||||
percent_functional=50
|
||||
percent_reads=65
|
||||
percent_source_unaligned=50
|
||||
percent_uncacheable=10
|
||||
progress_interval=10000
|
||||
suppress_func_warnings=false
|
||||
sys=system
|
||||
trace_addr=0
|
||||
functional=system.funcmem.port[6]
|
||||
test=system.cpu6.l1c.cpu_side
|
||||
|
||||
[system.cpu6.l1c]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=4
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=12
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=32768
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=8
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu6.test
|
||||
mem_side=system.toL2Bus.slave[6]
|
||||
|
||||
[system.cpu7]
|
||||
type=MemTest
|
||||
children=l1c
|
||||
atomic=false
|
||||
issue_dmas=false
|
||||
max_loads=100000
|
||||
memory_size=65536
|
||||
percent_dest_unaligned=50
|
||||
percent_functional=50
|
||||
percent_reads=65
|
||||
percent_source_unaligned=50
|
||||
percent_uncacheable=10
|
||||
progress_interval=10000
|
||||
suppress_func_warnings=false
|
||||
sys=system
|
||||
trace_addr=0
|
||||
functional=system.funcmem.port[7]
|
||||
test=system.cpu7.l1c.cpu_side
|
||||
|
||||
[system.cpu7.l1c]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=4
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=12
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=32768
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=8
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu7.test
|
||||
mem_side=system.toL2Bus.slave[7]
|
||||
|
||||
[system.funcmem]
|
||||
type=SimpleMemory
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=false
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.cpu0.functional system.cpu1.functional system.cpu2.functional system.cpu3.functional system.cpu4.functional system.cpu5.functional system.cpu6.functional system.cpu7.functional
|
||||
|
||||
[system.l2c]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=8
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=false
|
||||
latency=10000
|
||||
max_miss_count=0
|
||||
mshrs=92
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=65536
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=16
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.toL2Bus.master[0]
|
||||
mem_side=system.membus.slave[0]
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=2
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=16
|
||||
master=system.physmem.port[0]
|
||||
slave=system.l2c.mem_side system.system_port
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.membus.master[0]
|
||||
|
||||
[system.toL2Bus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=2
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=16
|
||||
master=system.l2c.cpu_side
|
||||
slave=system.cpu0.l1c.mem_side system.cpu1.l1c.mem_side system.cpu2.l1c.mem_side system.cpu3.l1c.mem_side system.cpu4.l1c.mem_side system.cpu5.l1c.mem_side system.cpu6.l1c.mem_side system.cpu7.l1c.mem_side
|
||||
|
||||
74
simulators/gem5/tests/quick/se/50.memtest/ref/alpha/linux/memtest/simerr
Executable file
74
simulators/gem5/tests/quick/se/50.memtest/ref/alpha/linux/memtest/simerr
Executable file
@ -0,0 +1,74 @@
|
||||
system.cpu5: completed 10000 read, 5261 write accesses @25602084
|
||||
system.cpu0: completed 10000 read, 5478 write accesses @26185688
|
||||
system.cpu4: completed 10000 read, 5410 write accesses @26212882
|
||||
system.cpu3: completed 10000 read, 5338 write accesses @26366308
|
||||
system.cpu1: completed 10000 read, 5460 write accesses @26447108
|
||||
system.cpu7: completed 10000 read, 5362 write accesses @26537664
|
||||
system.cpu2: completed 10000 read, 5282 write accesses @26676832
|
||||
system.cpu6: completed 10000 read, 5370 write accesses @26707781
|
||||
system.cpu3: completed 20000 read, 10741 write accesses @51951998
|
||||
system.cpu5: completed 20000 read, 10677 write accesses @52231737
|
||||
system.cpu0: completed 20000 read, 11006 write accesses @52523512
|
||||
system.cpu4: completed 20000 read, 10704 write accesses @52614186
|
||||
system.cpu7: completed 20000 read, 10588 write accesses @52674871
|
||||
system.cpu1: completed 20000 read, 10959 write accesses @52986792
|
||||
system.cpu2: completed 20000 read, 10676 write accesses @53365626
|
||||
system.cpu6: completed 20000 read, 10788 write accesses @53537042
|
||||
system.cpu5: completed 30000 read, 16233 write accesses @78528098
|
||||
system.cpu3: completed 30000 read, 16192 write accesses @78636475
|
||||
system.cpu7: completed 30000 read, 15958 write accesses @79069859
|
||||
system.cpu0: completed 30000 read, 16488 write accesses @79082669
|
||||
system.cpu4: completed 30000 read, 16215 write accesses @79163244
|
||||
system.cpu6: completed 30000 read, 16191 write accesses @79592442
|
||||
system.cpu2: completed 30000 read, 16073 write accesses @79845712
|
||||
system.cpu1: completed 30000 read, 16466 write accesses @80286691
|
||||
system.cpu5: completed 40000 read, 21620 write accesses @103783596
|
||||
system.cpu0: completed 40000 read, 21781 write accesses @103983848
|
||||
system.cpu7: completed 40000 read, 21333 write accesses @104306510
|
||||
system.cpu3: completed 40000 read, 21577 write accesses @104792070
|
||||
system.cpu6: completed 40000 read, 21636 write accesses @104882247
|
||||
system.cpu4: completed 40000 read, 21525 write accesses @104921736
|
||||
system.cpu1: completed 40000 read, 21768 write accesses @105789168
|
||||
system.cpu2: completed 40000 read, 21470 write accesses @106255146
|
||||
system.cpu5: completed 50000 read, 26996 write accesses @130119835
|
||||
system.cpu0: completed 50000 read, 27148 write accesses @130621851
|
||||
system.cpu4: completed 50000 read, 26714 write accesses @131102250
|
||||
system.cpu7: completed 50000 read, 26744 write accesses @131131435
|
||||
system.cpu3: completed 50000 read, 26919 write accesses @131315326
|
||||
system.cpu6: completed 50000 read, 27071 write accesses @131463045
|
||||
system.cpu2: completed 50000 read, 26691 write accesses @132748289
|
||||
system.cpu1: completed 50000 read, 27351 write accesses @133533726
|
||||
system.cpu0: completed 60000 read, 32524 write accesses @157291050
|
||||
system.cpu5: completed 60000 read, 32351 write accesses @157331674
|
||||
system.cpu3: completed 60000 read, 32133 write accesses @157609229
|
||||
system.cpu4: completed 60000 read, 32278 write accesses @158092666
|
||||
system.cpu7: completed 60000 read, 32237 write accesses @158094050
|
||||
system.cpu6: completed 60000 read, 32492 write accesses @158284016
|
||||
system.cpu2: completed 60000 read, 32099 write accesses @159310066
|
||||
system.cpu1: completed 60000 read, 32786 write accesses @160315811
|
||||
system.cpu5: completed 70000 read, 37785 write accesses @184174146
|
||||
system.cpu0: completed 70000 read, 37907 write accesses @184194427
|
||||
system.cpu3: completed 70000 read, 37695 write accesses @184756116
|
||||
system.cpu7: completed 70000 read, 37537 write accesses @185107500
|
||||
system.cpu6: completed 70000 read, 37865 write accesses @185115722
|
||||
system.cpu4: completed 70000 read, 37642 write accesses @185437602
|
||||
system.cpu2: completed 70000 read, 37459 write accesses @186101472
|
||||
system.cpu1: completed 70000 read, 38271 write accesses @187053767
|
||||
system.cpu0: completed 80000 read, 43182 write accesses @210453706
|
||||
system.cpu7: completed 80000 read, 43001 write accesses @210994557
|
||||
system.cpu5: completed 80000 read, 43199 write accesses @211075215
|
||||
system.cpu3: completed 80000 read, 43061 write accesses @211165517
|
||||
system.cpu4: completed 80000 read, 43118 write accesses @211798954
|
||||
system.cpu6: completed 80000 read, 43219 write accesses @211876903
|
||||
system.cpu2: completed 80000 read, 43025 write accesses @212410812
|
||||
system.cpu1: completed 80000 read, 43805 write accesses @214554639
|
||||
system.cpu0: completed 90000 read, 48653 write accesses @236986702
|
||||
system.cpu5: completed 90000 read, 48401 write accesses @237258796
|
||||
system.cpu7: completed 90000 read, 48251 write accesses @237456793
|
||||
system.cpu4: completed 90000 read, 48341 write accesses @237741580
|
||||
system.cpu3: completed 90000 read, 48504 write accesses @237892702
|
||||
system.cpu6: completed 90000 read, 48675 write accesses @238620248
|
||||
system.cpu2: completed 90000 read, 48457 write accesses @239205755
|
||||
system.cpu1: completed 90000 read, 49067 write accesses @239913307
|
||||
system.cpu5: completed 100000 read, 53710 write accesses @263488655
|
||||
hack: be nice to actually delete the event here
|
||||
10
simulators/gem5/tests/quick/se/50.memtest/ref/alpha/linux/memtest/simout
Executable file
10
simulators/gem5/tests/quick/se/50.memtest/ref/alpha/linux/memtest/simout
Executable file
@ -0,0 +1,10 @@
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jun 4 2012 11:50:11
|
||||
gem5 started Jun 4 2012 14:15:53
|
||||
gem5 executing on zizzer
|
||||
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/50.memtest/alpha/linux/memtest -re tests/run.py build/ALPHA/tests/opt/quick/se/50.memtest/alpha/linux/memtest
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 263488655 because maximum number of loads reached
|
||||
File diff suppressed because it is too large
Load Diff
30
simulators/gem5/tests/quick/se/50.memtest/test.py
Normal file
30
simulators/gem5/tests/quick/se/50.memtest/test.py
Normal file
@ -0,0 +1,30 @@
|
||||
# Copyright (c) 2006-2007 The Regents of The University of Michigan
|
||||
# All rights reserved.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are
|
||||
# met: redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer;
|
||||
# redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in the
|
||||
# documentation and/or other materials provided with the distribution;
|
||||
# neither the name of the copyright holders nor the names of its
|
||||
# contributors may be used to endorse or promote products derived from
|
||||
# this software without specific prior written permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
#
|
||||
# Authors: Ron Dreslinski
|
||||
|
||||
MemTest.max_loads=1e5
|
||||
MemTest.progress_interval=1e4
|
||||
Reference in New Issue
Block a user