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Adding gem5 source to svn.

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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1819 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
This commit is contained in:
friemel
2012-10-24 19:18:57 +00:00
parent f7ff71bd46
commit b41eec3f65
3222 changed files with 658579 additions and 1 deletions
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231
simulators/gem5/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/config.ini Normal file
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[root]
type=Root
children=system
full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
boot_osflags=a
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
readfile=
symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.cpu]
type=InOrderCPU
children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
BTBEntries=4096
BTBTagSize=16
RASSize=16
activity=0
cachePorts=2
checker=Null
choiceCtrBits=2
choicePredictorSize=8192
clock=500
cpu_id=0
defer_registration=false
div16Latency=1
div16RepeatRate=1
div24Latency=1
div24RepeatRate=1
div32Latency=1
div32RepeatRate=1
div8Latency=1
div8RepeatRate=1
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
fetchBuffSize=4
functionTrace=false
functionTraceStart=0
function_trace=false
function_trace_start=0
globalCtrBits=2
globalHistoryBits=13
globalPredictorSize=8192
instShiftAmt=2
interrupts=system.cpu.interrupts
itb=system.cpu.itb
localCtrBits=2
localHistoryBits=11
localHistoryTableSize=2048
localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
memBlockSize=64
multLatency=1
multRepeatRate=1
numThreads=1
phase=0
predType=tournament
profile=0
progress_interval=0
stageTracing=false
stageWidth=4
system=system
threadModel=SMT
tracer=system.cpu.tracer
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=262144
subblock_size=0
system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
[system.cpu.dtb]
type=SparcTLB
size=64
[system.cpu.icache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=131072
subblock_size=0
system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.interrupts]
type=SparcInterrupts
[system.cpu.itb]
type=SparcTLB
size=64
[system.cpu.l2cache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=false
latency=10000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=2097152
subblock_size=0
system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
[system.cpu.toL2Bus]
type=CoherentBus
block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=insttest
cwd=
egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/regression/test-progs/insttest/bin/sparc/linux/insttest
gid=100
input=cin
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=0
system=system
uid=100
[system.membus]
type=CoherentBus
block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
master=system.physmem.port[0]
slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=SimpleMemory
conf_table_reported=false
file=
in_addr_map=true
latency=30000
latency_var=0
null=false
range=0:134217727
zero=false
port=system.membus.master[0]

2
simulators/gem5/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/simerr Executable file
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warn: Sockets disabled, not accepting gdb connections
hack: be nice to actually delete the event here

21
simulators/gem5/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/simout Executable file
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gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 4 2012 12:01:47
gem5 started Jun 4 2012 14:44:53
gem5 executing on zizzer
command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/inorder-timing -re tests/run.py build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/inorder-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Begining test of difficult SPARC instructions...
LDSTUB: Passed
SWAP: Passed
CAS FAIL: Passed
CAS WORK: Passed
CASX FAIL: Passed
CASX WORK: Passed
LDTX: Passed
LDTW: Passed
STTW: Passed
Done
Exiting @ tick 25007500 because target called exit()

419
simulators/gem5/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt Normal file
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---------- Begin Simulation Statistics ----------
sim_seconds 0.000025 # Number of seconds simulated
sim_ticks 25007500 # Number of ticks simulated
final_tick 25007500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 72389 # Simulator instruction rate (inst/s)
host_op_rate 72383 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 119272701 # Simulator tick rate (ticks/s)
host_mem_usage 221376 # Number of bytes of host memory used
host_seconds 0.21 # Real time elapsed on the host
sim_insts 15175 # Number of instructions simulated
sim_ops 15175 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 19072 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 8832 # Number of bytes read from this memory
system.physmem.bytes_read::total 27904 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 19072 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 19072 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 298 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory
system.physmem.num_reads::total 436 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 762651205 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 353174048 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 1115825252 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 762651205 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 762651205 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 762651205 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 353174048 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 1115825252 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 18 # Number of system calls
system.cpu.numCycles 50016 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.branch_predictor.lookups 5015 # Number of BP lookups
system.cpu.branch_predictor.condPredicted 3353 # Number of conditional branches predicted
system.cpu.branch_predictor.condIncorrect 2379 # Number of conditional branches incorrect
system.cpu.branch_predictor.BTBLookups 3332 # Number of BTB lookups
system.cpu.branch_predictor.BTBHits 2040 # Number of BTB hits
system.cpu.branch_predictor.usedRAS 174 # Number of times the RAS was used to get a target.
system.cpu.branch_predictor.RASInCorrect 5 # Number of incorrect RAS predictions.
system.cpu.branch_predictor.BTBHitPct 61.224490 # BTB Hit Percentage
system.cpu.branch_predictor.predictedTaken 2214 # Number of Branches Predicted As Taken (True).
system.cpu.branch_predictor.predictedNotTaken 2801 # Number of Branches Predicted As Not Taken (False).
system.cpu.regfile_manager.intRegFileReads 14401 # Number of Reads from Int. Register File
system.cpu.regfile_manager.intRegFileWrites 11111 # Number of Writes to Int. Register File
system.cpu.regfile_manager.intRegFileAccesses 25512 # Total Accesses (Read+Write) to the Int. Register File
system.cpu.regfile_manager.floatRegFileReads 0 # Number of Reads from FP Register File
system.cpu.regfile_manager.floatRegFileWrites 0 # Number of Writes to FP Register File
system.cpu.regfile_manager.floatRegFileAccesses 0 # Total Accesses (Read+Write) to the FP Register File
system.cpu.regfile_manager.regForwards 4993 # Number of Registers Read Through Forwarding Logic
system.cpu.agen_unit.agens 3952 # Number of Address Generations
system.cpu.execution_unit.predictedTakenIncorrect 1316 # Number of Branches Incorrectly Predicted As Taken.
system.cpu.execution_unit.predictedNotTakenIncorrect 1000 # Number of Branches Incorrectly Predicted As Not Taken).
system.cpu.execution_unit.mispredicted 2316 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.predicted 1043 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.mispredictPct 68.949092 # Percentage of Incorrect Branches Predicts
system.cpu.execution_unit.executions 11084 # Number of Instructions Executed.
system.cpu.mult_div_unit.multiplies 0 # Number of Multipy Operations Executed
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
system.cpu.contextSwitches 1 # Number of context switches
system.cpu.threadCycles 21887 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
system.cpu.timesIdled 453 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 32683 # Number of cycles cpu's stages were not processed
system.cpu.runCycles 17333 # Number of cycles cpu stages are processed.
system.cpu.activity 34.654910 # Percentage of cycles cpu is active
system.cpu.comLoads 2226 # Number of Load instructions committed
system.cpu.comStores 1448 # Number of Store instructions committed
system.cpu.comBranches 3359 # Number of Branches instructions committed
system.cpu.comNops 726 # Number of Nop instructions committed
system.cpu.comNonSpec 222 # Number of Non-Speculative instructions committed
system.cpu.comInts 7177 # Number of Integer instructions committed
system.cpu.comFloats 0 # Number of Floating Point instructions committed
system.cpu.committedInsts 15175 # Number of Instructions committed (Per-Thread)
system.cpu.committedOps 15175 # Number of Ops committed (Per-Thread)
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
system.cpu.committedInsts_total 15175 # Number of Instructions committed (Total)
system.cpu.cpi 3.295947 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.smt_cpi nan # CPI: Total SMT-CPI
system.cpu.cpi_total 3.295947 # CPI: Total CPI of All Threads
system.cpu.ipc 0.303403 # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.smt_ipc nan # IPC: Total SMT-IPC
system.cpu.ipc_total 0.303403 # IPC: Total IPC of All Threads
system.cpu.stage0.idleCycles 36923 # Number of cycles 0 instructions are processed.
system.cpu.stage0.runCycles 13093 # Number of cycles 1+ instructions are processed.
system.cpu.stage0.utilization 26.177623 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage1.idleCycles 40814 # Number of cycles 0 instructions are processed.
system.cpu.stage1.runCycles 9202 # Number of cycles 1+ instructions are processed.
system.cpu.stage1.utilization 18.398113 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage2.idleCycles 41191 # Number of cycles 0 instructions are processed.
system.cpu.stage2.runCycles 8825 # Number of cycles 1+ instructions are processed.
system.cpu.stage2.utilization 17.644354 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage3.idleCycles 47132 # Number of cycles 0 instructions are processed.
system.cpu.stage3.runCycles 2884 # Number of cycles 1+ instructions are processed.
system.cpu.stage3.utilization 5.766155 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage4.idleCycles 40690 # Number of cycles 0 instructions are processed.
system.cpu.stage4.runCycles 9326 # Number of cycles 1+ instructions are processed.
system.cpu.stage4.utilization 18.646033 # Percentage of cycles stage was utilized (processing insts).
system.cpu.icache.replacements 0 # number of replacements
system.cpu.icache.tagsinuse 165.557258 # Cycle average of tags in use
system.cpu.icache.total_refs 2602 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 299 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 8.702341 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 165.557258 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.080839 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.080839 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 2602 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 2602 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 2602 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 2602 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 2602 # number of overall hits
system.cpu.icache.overall_hits::total 2602 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 368 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 368 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 368 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 368 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 368 # number of overall misses
system.cpu.icache.overall_misses::total 368 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 20203500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 20203500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 20203500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 20203500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 20203500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 20203500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 2970 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 2970 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 2970 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 2970 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 2970 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 2970 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.123906 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.123906 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.123906 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.123906 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.123906 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.123906 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54900.815217 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 54900.815217 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 54900.815217 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 54900.815217 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 54900.815217 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 54900.815217 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 65500 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 2 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets 32750 # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 67 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 67 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 67 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 67 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 67 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 67 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 301 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 301 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 301 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 301 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 301 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 301 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15872000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 15872000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15872000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 15872000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15872000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 15872000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.101347 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.101347 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.101347 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.101347 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.101347 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.101347 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52730.897010 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52730.897010 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52730.897010 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 52730.897010 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52730.897010 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 52730.897010 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.tagsinuse 97.041769 # Cycle average of tags in use
system.cpu.dcache.total_refs 3316 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 24.028986 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 97.041769 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.023692 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.023692 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 2168 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 2168 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 1142 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 1142 # number of WriteReq hits
system.cpu.dcache.SwapReq_hits::cpu.data 6 # number of SwapReq hits
system.cpu.dcache.SwapReq_hits::total 6 # number of SwapReq hits
system.cpu.dcache.demand_hits::cpu.data 3310 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 3310 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 3310 # number of overall hits
system.cpu.dcache.overall_hits::total 3310 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 58 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 58 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 300 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 300 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 358 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 358 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 358 # number of overall misses
system.cpu.dcache.overall_misses::total 358 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 3281500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 3281500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 16397000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 16397000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 19678500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 19678500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 19678500 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 19678500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 2226 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 2226 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 1442 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SwapReq_accesses::cpu.data 6 # number of SwapReq accesses(hits+misses)
system.cpu.dcache.SwapReq_accesses::total 6 # number of SwapReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 3668 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 3668 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 3668 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 3668 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.026056 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.026056 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.208044 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.208044 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.097601 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.097601 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.097601 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.097601 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56577.586207 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 56577.586207 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54656.666667 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 54656.666667 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 54967.877095 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 54967.877095 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 54967.877095 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 54967.877095 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 2208000 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 44 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 50181.818182 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 5 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 5 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 215 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 215 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 220 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 220 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 220 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 220 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 53 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 53 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 85 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 85 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2837000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2837000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4545000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 4545000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7382000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 7382000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7382000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 7382000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.023810 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.023810 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.058946 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.058946 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.037623 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.037623 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037623 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.037623 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53528.301887 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53528.301887 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53470.588235 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53470.588235 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53492.753623 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 53492.753623 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53492.753623 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 53492.753623 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 196.205624 # Cycle average of tags in use
system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 350 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.005714 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::cpu.inst 164.948941 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 31.256684 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::cpu.inst 0.005034 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.000954 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.005988 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits
system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits
system.cpu.l2cache.overall_hits::total 2 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 299 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 53 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 352 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 85 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 85 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 299 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 138 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 437 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 299 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 138 # number of overall misses
system.cpu.l2cache.overall_misses::total 437 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15533000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2776500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 18309500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4442500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 4442500 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 15533000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 7219000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 22752000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 15533000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 7219000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 22752000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 301 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 53 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 354 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 85 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 85 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 301 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 138 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 439 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 301 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 138 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 439 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.993355 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.994350 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993355 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.995444 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993355 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.995444 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 51949.832776 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52386.792453 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52015.625000 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52264.705882 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52264.705882 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 51949.832776 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52311.594203 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 52064.073227 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 51949.832776 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52311.594203 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 52064.073227 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 299 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 53 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 352 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 85 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 85 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 299 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 437 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 299 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 437 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11916000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2132500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14048500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3416000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3416000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11916000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5548500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 17464500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11916000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5548500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 17464500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993355 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.994350 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993355 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.995444 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993355 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.995444 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39852.842809 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40235.849057 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39910.511364 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40188.235294 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40188.235294 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39852.842809 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40206.521739 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39964.530892 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39852.842809 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40206.521739 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39964.530892 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

529
simulators/gem5/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini Normal file
View File

@ -0,0 +1,529 @@
[root]
type=Root
children=system
full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
boot_osflags=a
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
readfile=
symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.cpu]
type=DerivO3CPU
children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
LSQDepCheckShift=4
RASSize=16
SQEntries=32
SSITSize=1024
activity=0
backComSize=5
cachePorts=200
checker=Null
choiceCtrBits=2
choicePredictorSize=8192
clock=500
commitToDecodeDelay=1
commitToFetchDelay=1
commitToIEWDelay=1
commitToRenameDelay=1
commitWidth=8
cpu_id=0
decodeToFetchDelay=1
decodeToRenameDelay=1
decodeWidth=8
defer_registration=false
dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
fetchToDecodeDelay=1
fetchTrapLatency=1
fetchWidth=8
forwardComSize=5
fuPool=system.cpu.fuPool
function_trace=false
function_trace_start=0
globalCtrBits=2
globalHistoryBits=13
globalPredictorSize=8192
iewToCommitDelay=1
iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
instShiftAmt=2
interrupts=system.cpu.interrupts
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
localCtrBits=2
localHistoryBits=11
localHistoryTableSize=2048
localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
needsTSO=false
numIQEntries=64
numPhysFloatRegs=256
numPhysIntRegs=256
numROBEntries=192
numRobs=1
numThreads=1
phase=0
predType=tournament
profile=0
progress_interval=0
renameToDecodeDelay=1
renameToFetchDelay=1
renameToIEWDelay=2
renameToROBDelay=1
renameWidth=8
smtCommitPolicy=RoundRobin
smtFetchPolicy=SingleThread
smtIQPolicy=Partitioned
smtIQThreshold=100
smtLSQPolicy=Partitioned
smtLSQThreshold=100
smtNumFetchingThreads=1
smtROBPolicy=Partitioned
smtROBThreshold=100
squashWidth=8
store_set_clear_period=250000
system=system
tracer=system.cpu.tracer
trapLatency=13
wbDepth=1
wbWidth=8
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=262144
subblock_size=0
system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
[system.cpu.dtb]
type=SparcTLB
size=64
[system.cpu.fuPool]
type=FUPool
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
[system.cpu.fuPool.FUList0]
type=FUDesc
children=opList
count=6
opList=system.cpu.fuPool.FUList0.opList
[system.cpu.fuPool.FUList0.opList]
type=OpDesc
issueLat=1
opClass=IntAlu
opLat=1
[system.cpu.fuPool.FUList1]
type=FUDesc
children=opList0 opList1
count=2
opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
[system.cpu.fuPool.FUList1.opList0]
type=OpDesc
issueLat=1
opClass=IntMult
opLat=3
[system.cpu.fuPool.FUList1.opList1]
type=OpDesc
issueLat=19
opClass=IntDiv
opLat=20
[system.cpu.fuPool.FUList2]
type=FUDesc
children=opList0 opList1 opList2
count=4
opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
[system.cpu.fuPool.FUList2.opList0]
type=OpDesc
issueLat=1
opClass=FloatAdd
opLat=2
[system.cpu.fuPool.FUList2.opList1]
type=OpDesc
issueLat=1
opClass=FloatCmp
opLat=2
[system.cpu.fuPool.FUList2.opList2]
type=OpDesc
issueLat=1
opClass=FloatCvt
opLat=2
[system.cpu.fuPool.FUList3]
type=FUDesc
children=opList0 opList1 opList2
count=2
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
[system.cpu.fuPool.FUList3.opList0]
type=OpDesc
issueLat=1
opClass=FloatMult
opLat=4
[system.cpu.fuPool.FUList3.opList1]
type=OpDesc
issueLat=12
opClass=FloatDiv
opLat=12
[system.cpu.fuPool.FUList3.opList2]
type=OpDesc
issueLat=24
opClass=FloatSqrt
opLat=24
[system.cpu.fuPool.FUList4]
type=FUDesc
children=opList
count=0
opList=system.cpu.fuPool.FUList4.opList
[system.cpu.fuPool.FUList4.opList]
type=OpDesc
issueLat=1
opClass=MemRead
opLat=1
[system.cpu.fuPool.FUList5]
type=FUDesc
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
count=4
opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
[system.cpu.fuPool.FUList5.opList00]
type=OpDesc
issueLat=1
opClass=SimdAdd
opLat=1
[system.cpu.fuPool.FUList5.opList01]
type=OpDesc
issueLat=1
opClass=SimdAddAcc
opLat=1
[system.cpu.fuPool.FUList5.opList02]
type=OpDesc
issueLat=1
opClass=SimdAlu
opLat=1
[system.cpu.fuPool.FUList5.opList03]
type=OpDesc
issueLat=1
opClass=SimdCmp
opLat=1
[system.cpu.fuPool.FUList5.opList04]
type=OpDesc
issueLat=1
opClass=SimdCvt
opLat=1
[system.cpu.fuPool.FUList5.opList05]
type=OpDesc
issueLat=1
opClass=SimdMisc
opLat=1
[system.cpu.fuPool.FUList5.opList06]
type=OpDesc
issueLat=1
opClass=SimdMult
opLat=1
[system.cpu.fuPool.FUList5.opList07]
type=OpDesc
issueLat=1
opClass=SimdMultAcc
opLat=1
[system.cpu.fuPool.FUList5.opList08]
type=OpDesc
issueLat=1
opClass=SimdShift
opLat=1
[system.cpu.fuPool.FUList5.opList09]
type=OpDesc
issueLat=1
opClass=SimdShiftAcc
opLat=1
[system.cpu.fuPool.FUList5.opList10]
type=OpDesc
issueLat=1
opClass=SimdSqrt
opLat=1
[system.cpu.fuPool.FUList5.opList11]
type=OpDesc
issueLat=1
opClass=SimdFloatAdd
opLat=1
[system.cpu.fuPool.FUList5.opList12]
type=OpDesc
issueLat=1
opClass=SimdFloatAlu
opLat=1
[system.cpu.fuPool.FUList5.opList13]
type=OpDesc
issueLat=1
opClass=SimdFloatCmp
opLat=1
[system.cpu.fuPool.FUList5.opList14]
type=OpDesc
issueLat=1
opClass=SimdFloatCvt
opLat=1
[system.cpu.fuPool.FUList5.opList15]
type=OpDesc
issueLat=1
opClass=SimdFloatDiv
opLat=1
[system.cpu.fuPool.FUList5.opList16]
type=OpDesc
issueLat=1
opClass=SimdFloatMisc
opLat=1
[system.cpu.fuPool.FUList5.opList17]
type=OpDesc
issueLat=1
opClass=SimdFloatMult
opLat=1
[system.cpu.fuPool.FUList5.opList18]
type=OpDesc
issueLat=1
opClass=SimdFloatMultAcc
opLat=1
[system.cpu.fuPool.FUList5.opList19]
type=OpDesc
issueLat=1
opClass=SimdFloatSqrt
opLat=1
[system.cpu.fuPool.FUList6]
type=FUDesc
children=opList
count=0
opList=system.cpu.fuPool.FUList6.opList
[system.cpu.fuPool.FUList6.opList]
type=OpDesc
issueLat=1
opClass=MemWrite
opLat=1
[system.cpu.fuPool.FUList7]
type=FUDesc
children=opList0 opList1
count=4
opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
[system.cpu.fuPool.FUList7.opList0]
type=OpDesc
issueLat=1
opClass=MemRead
opLat=1
[system.cpu.fuPool.FUList7.opList1]
type=OpDesc
issueLat=1
opClass=MemWrite
opLat=1
[system.cpu.fuPool.FUList8]
type=FUDesc
children=opList
count=1
opList=system.cpu.fuPool.FUList8.opList
[system.cpu.fuPool.FUList8.opList]
type=OpDesc
issueLat=3
opClass=IprAccess
opLat=3
[system.cpu.icache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=131072
subblock_size=0
system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.interrupts]
type=SparcInterrupts
[system.cpu.itb]
type=SparcTLB
size=64
[system.cpu.l2cache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=false
latency=1000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=2097152
subblock_size=0
system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
[system.cpu.toL2Bus]
type=CoherentBus
block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=insttest
cwd=
egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/regression/test-progs/insttest/bin/sparc/linux/insttest
gid=100
input=cin
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=0
system=system
uid=100
[system.membus]
type=CoherentBus
block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
master=system.physmem.port[0]
slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=SimpleMemory
conf_table_reported=false
file=
in_addr_map=true
latency=30000
latency_var=0
null=false
range=0:134217727
zero=false
port=system.membus.master[0]

2
simulators/gem5/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simerr Executable file
View File

@ -0,0 +1,2 @@
warn: Sockets disabled, not accepting gdb connections
hack: be nice to actually delete the event here

21
simulators/gem5/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout Executable file
View File

@ -0,0 +1,21 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 4 2012 12:01:47
gem5 started Jun 4 2012 14:45:02
gem5 executing on zizzer
command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing -re tests/run.py build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Begining test of difficult SPARC instructions...
LDSTUB: Passed
SWAP: Passed
CAS FAIL: Passed
CAS WORK: Passed
CASX FAIL: Passed
CASX WORK: Passed
LDTX: Passed
LDTW: Passed
STTW: Passed
Done
Exiting @ tick 19744500 because target called exit()

614
simulators/gem5/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt Normal file
View File

@ -0,0 +1,614 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000020 # Number of seconds simulated
sim_ticks 19744500 # Number of ticks simulated
final_tick 19744500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 74885 # Simulator instruction rate (inst/s)
host_op_rate 74878 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 102311932 # Simulator tick rate (ticks/s)
host_mem_usage 222004 # Number of bytes of host memory used
host_seconds 0.19 # Real time elapsed on the host
sim_insts 14449 # Number of instructions simulated
sim_ops 14449 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 21632 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 9344 # Number of bytes read from this memory
system.physmem.bytes_read::total 30976 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 21632 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 21632 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 338 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 146 # Number of read requests responded to by this memory
system.physmem.num_reads::total 484 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 1095596242 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 473245714 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 1568841956 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 1095596242 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 1095596242 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 1095596242 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 473245714 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 1568841956 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 18 # Number of system calls
system.cpu.numCycles 39490 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.BPredUnit.lookups 6899 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 4560 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 1119 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 5346 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 2573 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 464 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 172 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 11886 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 32156 # Number of instructions fetch has processed
system.cpu.fetch.Branches 6899 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 3037 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 9512 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 3178 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 6896 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 726 # Number of stall cycles due to pending traps
system.cpu.fetch.CacheLines 5506 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 480 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 30987 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 1.037725 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.210162 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 21475 69.30% 69.30% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 4729 15.26% 84.56% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 477 1.54% 86.10% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 446 1.44% 87.54% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 688 2.22% 89.76% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 747 2.41% 92.17% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 238 0.77% 92.94% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 276 0.89% 93.83% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 1911 6.17% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 30987 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.174702 # Number of branch fetches per cycle
system.cpu.fetch.rate 0.814282 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 12512 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 7643 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 8680 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 189 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 1963 # Number of cycles decode is squashing
system.cpu.decode.DecodedInsts 29984 # Number of instructions handled by decode
system.cpu.rename.SquashCycles 1963 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 13183 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 245 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 6907 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 8245 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 444 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 27285 # Number of instructions processed by rename
system.cpu.rename.IQFullEvents 2 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 121 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenamedOperands 24368 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 50732 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 50732 # Number of integer rename lookups
system.cpu.rename.CommittedMaps 13832 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 10536 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 705 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 708 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 2853 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 3628 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 2437 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 4 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 23083 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 663 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 21701 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 105 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 8350 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 5831 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 188 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 30987 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 0.700326 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.316293 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 21563 69.59% 69.59% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 3594 11.60% 81.19% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 2382 7.69% 88.87% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 1729 5.58% 94.45% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 896 2.89% 97.34% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 479 1.55% 98.89% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 250 0.81% 99.70% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 75 0.24% 99.94% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 19 0.06% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 30987 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 54 30.17% 30.17% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 30.17% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 30.17% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 30.17% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 30.17% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 30.17% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 30.17% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 30.17% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 30.17% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 30.17% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 30.17% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 30.17% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 30.17% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 30.17% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 30.17% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 30.17% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 30.17% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 30.17% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 30.17% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 30.17% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 30.17% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 30.17% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 30.17% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 30.17% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 30.17% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 30.17% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 30.17% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 30.17% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 30.17% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 26 14.53% 44.69% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 99 55.31% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 16032 73.88% 73.88% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 0 0.00% 73.88% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 73.88% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 73.88% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 73.88% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 73.88% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 73.88% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 73.88% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 73.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 73.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 73.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 73.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 73.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 73.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 73.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 73.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 73.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 73.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 73.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 73.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 73.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 73.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 73.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 73.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 73.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 73.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 73.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 73.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 73.88% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 3432 15.81% 89.69% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 2237 10.31% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 21701 # Type of FU issued
system.cpu.iq.rate 0.549532 # Inst issue rate
system.cpu.iq.fu_busy_cnt 179 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.008248 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 74673 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 32122 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 19916 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 21880 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 26 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 1402 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 27 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 989 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 1963 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 144 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 10 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 24909 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 369 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 3628 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 2437 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 663 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 27 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 296 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 956 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 1252 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 20511 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 3278 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 1190 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 1163 # number of nop insts executed
system.cpu.iew.exec_refs 5392 # number of memory reference insts executed
system.cpu.iew.exec_branches 4300 # Number of branches executed
system.cpu.iew.exec_stores 2114 # Number of stores executed
system.cpu.iew.exec_rate 0.519397 # Inst execution rate
system.cpu.iew.wb_sent 20186 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 19916 # cumulative count of insts written-back
system.cpu.iew.wb_producers 9270 # num instructions producing a value
system.cpu.iew.wb_consumers 11399 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 0.504330 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.813229 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitCommittedInsts 15175 # The number of committed instructions
system.cpu.commit.commitCommittedOps 15175 # The number of committed instructions
system.cpu.commit.commitSquashedInsts 9652 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 475 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 1119 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 29041 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 0.522537 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.206609 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 21661 74.59% 74.59% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 4067 14.00% 88.59% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 1430 4.92% 93.52% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 794 2.73% 96.25% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 339 1.17% 97.42% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 260 0.90% 98.31% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 321 1.11% 99.42% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 68 0.23% 99.65% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 101 0.35% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 29041 # Number of insts commited each cycle
system.cpu.commit.committedInsts 15175 # Number of instructions committed
system.cpu.commit.committedOps 15175 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 3674 # Number of memory references committed
system.cpu.commit.loads 2226 # Number of loads committed
system.cpu.commit.membars 0 # Number of memory barriers committed
system.cpu.commit.branches 3359 # Number of branches committed
system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
system.cpu.commit.int_insts 12186 # Number of committed integer instructions.
system.cpu.commit.function_calls 187 # Number of function calls committed.
system.cpu.commit.bw_lim_events 101 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 52944 # The number of ROB reads
system.cpu.rob.rob_writes 51625 # The number of ROB writes
system.cpu.timesIdled 185 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 8503 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 14449 # Number of Instructions Simulated
system.cpu.committedOps 14449 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 14449 # Number of Instructions Simulated
system.cpu.cpi 2.733061 # CPI: Cycles Per Instruction
system.cpu.cpi_total 2.733061 # CPI: Total CPI of All Threads
system.cpu.ipc 0.365890 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.365890 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 32680 # number of integer regfile reads
system.cpu.int_regfile_writes 18187 # number of integer regfile writes
system.cpu.misc_regfile_reads 7045 # number of misc regfile reads
system.cpu.misc_regfile_writes 569 # number of misc regfile writes
system.cpu.icache.replacements 0 # number of replacements
system.cpu.icache.tagsinuse 200.774248 # Cycle average of tags in use
system.cpu.icache.total_refs 5020 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 340 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 14.764706 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 200.774248 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.098034 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.098034 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 5020 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 5020 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 5020 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 5020 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 5020 # number of overall hits
system.cpu.icache.overall_hits::total 5020 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 486 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 486 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 486 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 486 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 486 # number of overall misses
system.cpu.icache.overall_misses::total 486 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 16725500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 16725500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 16725500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 16725500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 16725500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 16725500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 5506 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 5506 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 5506 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 5506 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 5506 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 5506 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.088267 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.088267 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.088267 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.088267 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.088267 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.088267 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34414.609053 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 34414.609053 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 34414.609053 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 34414.609053 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 34414.609053 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 34414.609053 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 146 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 146 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 146 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 146 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 146 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 146 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 340 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 340 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 340 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 340 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 340 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 340 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11937500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 11937500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11937500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 11937500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11937500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 11937500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.061751 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.061751 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.061751 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.061751 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.061751 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.061751 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35110.294118 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35110.294118 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35110.294118 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 35110.294118 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35110.294118 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 35110.294118 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.tagsinuse 103.476464 # Cycle average of tags in use
system.cpu.dcache.total_refs 4083 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 146 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 27.965753 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 103.476464 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.025263 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.025263 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 3043 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 3043 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 1034 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 1034 # number of WriteReq hits
system.cpu.dcache.SwapReq_hits::cpu.data 6 # number of SwapReq hits
system.cpu.dcache.SwapReq_hits::total 6 # number of SwapReq hits
system.cpu.dcache.demand_hits::cpu.data 4077 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 4077 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 4077 # number of overall hits
system.cpu.dcache.overall_hits::total 4077 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 118 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 118 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 408 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 408 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 526 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 526 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 526 # number of overall misses
system.cpu.dcache.overall_misses::total 526 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 4092500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 4092500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 14593500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 14593500 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 18686000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 18686000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 18686000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 18686000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 3161 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 3161 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 1442 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SwapReq_accesses::cpu.data 6 # number of SwapReq accesses(hits+misses)
system.cpu.dcache.SwapReq_accesses::total 6 # number of SwapReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 4603 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 4603 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 4603 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 4603 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.037330 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.037330 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.282940 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.282940 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.114273 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.114273 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.114273 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.114273 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34682.203390 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 34682.203390 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35768.382353 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 35768.382353 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 35524.714829 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 35524.714829 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 35524.714829 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 35524.714829 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 55 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 55 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 325 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 325 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 380 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 380 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 380 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 380 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 63 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 63 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 83 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 83 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 146 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 146 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 146 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 146 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2243500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2243500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2979500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 2979500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5223000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 5223000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5223000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 5223000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.019930 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.019930 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.057559 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.057559 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.031718 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.031718 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.031718 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.031718 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35611.111111 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 35611.111111 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35897.590361 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35897.590361 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35773.972603 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 35773.972603 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 35773.972603 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 35773.972603 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 236.259194 # Cycle average of tags in use
system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 401 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.004988 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::cpu.inst 200.029408 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 36.229787 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::cpu.inst 0.006104 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.001106 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.007210 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits
system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits
system.cpu.l2cache.overall_hits::total 2 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 338 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 63 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 401 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 83 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 83 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 338 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 146 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 484 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 338 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 146 # number of overall misses
system.cpu.l2cache.overall_misses::total 484 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 11582500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2169000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 13751500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2869000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 2869000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 11582500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 5038000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 16620500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 11582500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 5038000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 16620500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 340 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 63 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 403 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 83 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 83 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 340 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 146 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 486 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 340 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 146 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 486 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.994118 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.995037 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.994118 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.995885 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.994118 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.995885 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34267.751479 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34428.571429 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 34293.017456 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34566.265060 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34566.265060 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34267.751479 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34506.849315 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 34339.876033 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34267.751479 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34506.849315 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 34339.876033 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 338 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 63 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 401 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 83 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 83 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 338 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 146 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 484 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 338 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 146 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 484 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10497000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1968500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12465500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2607500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2607500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10497000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4576000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 15073000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10497000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4576000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 15073000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.994118 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.995037 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.994118 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.995885 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.994118 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.995885 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31056.213018 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31246.031746 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31086.034913 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31415.662651 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31415.662651 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31056.213018 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31342.465753 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31142.561983 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31056.213018 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31342.465753 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31142.561983 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

117
simulators/gem5/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/config.ini Normal file
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[root]
type=Root
children=system
full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
boot_osflags=a
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
readfile=
symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.cpu]
type=AtomicSimpleCPU
children=dtb interrupts itb tracer workload
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
fastmem=false
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
phase=0
profile=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
system=system
tracer=system.cpu.tracer
width=1
workload=system.cpu.workload
dcache_port=system.membus.slave[2]
icache_port=system.membus.slave[1]
[system.cpu.dtb]
type=SparcTLB
size=64
[system.cpu.interrupts]
type=SparcInterrupts
[system.cpu.itb]
type=SparcTLB
size=64
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=insttest
cwd=
egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/regression/test-progs/insttest/bin/sparc/linux/insttest
gid=100
input=cin
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=0
system=system
uid=100
[system.membus]
type=CoherentBus
block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
master=system.physmem.port[0]
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
[system.physmem]
type=SimpleMemory
conf_table_reported=false
file=
in_addr_map=true
latency=30000
latency_var=0
null=false
range=0:134217727
zero=false
port=system.membus.master[0]

3
simulators/gem5/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simerr Executable file
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@ -0,0 +1,3 @@
warn: CoherentBus system.membus has no snooping ports attached!
warn: Sockets disabled, not accepting gdb connections
hack: be nice to actually delete the event here

21
simulators/gem5/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simout Executable file
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@ -0,0 +1,21 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 4 2012 12:01:47
gem5 started Jun 4 2012 14:45:04
gem5 executing on zizzer
command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Begining test of difficult SPARC instructions...
LDSTUB: Passed
SWAP: Passed
CAS FAIL: Passed
CAS WORK: Passed
CASX FAIL: Passed
CASX WORK: Passed
LDTX: Passed
LDTW: Passed
STTW: Passed
Done
Exiting @ tick 7618500 because target called exit()

62
simulators/gem5/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt Normal file
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@ -0,0 +1,62 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000008 # Number of seconds simulated
sim_ticks 7618500 # Number of ticks simulated
final_tick 7618500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 949089 # Simulator instruction rate (inst/s)
host_op_rate 948034 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 475431989 # Simulator tick rate (ticks/s)
host_mem_usage 212076 # Number of bytes of host memory used
host_seconds 0.02 # Real time elapsed on the host
sim_insts 15175 # Number of instructions simulated
sim_ops 15175 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 60880 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 11343 # Number of bytes read from this memory
system.physmem.bytes_read::total 72223 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 60880 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 60880 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 9042 # Number of bytes written to this memory
system.physmem.bytes_written::total 9042 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 15220 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 2226 # Number of read requests responded to by this memory
system.physmem.num_reads::total 17446 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 1442 # Number of write requests responded to by this memory
system.physmem.num_writes::total 1442 # Number of write requests responded to by this memory
system.physmem.num_other::cpu.data 6 # Number of other requests responded to by this memory
system.physmem.num_other::total 6 # Number of other requests responded to by this memory
system.physmem.bw_read::cpu.inst 7991074358 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 1488875763 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 9479950121 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 7991074358 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 7991074358 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 1186847805 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 1186847805 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 7991074358 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2675723568 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 10666797926 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 18 # Number of system calls
system.cpu.numCycles 15238 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 15175 # Number of instructions committed
system.cpu.committedOps 15175 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 12231 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu.num_func_calls 385 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 2435 # number of instructions that are conditional controls
system.cpu.num_int_insts 12231 # number of integer instructions
system.cpu.num_fp_insts 0 # number of float instructions
system.cpu.num_int_register_reads 29059 # number of times the integer registers were read
system.cpu.num_int_register_writes 13832 # number of times the integer registers were written
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_mem_refs 3684 # number of memory refs
system.cpu.num_load_insts 2232 # Number of load instructions
system.cpu.num_store_insts 1452 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 15238 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
---------- End Simulation Statistics ----------

198
simulators/gem5/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini Normal file
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@ -0,0 +1,198 @@
[root]
type=Root
children=system
full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
boot_osflags=a
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
readfile=
symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.cpu]
type=TimingSimpleCPU
children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
phase=0
profile=0
progress_interval=0
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=262144
subblock_size=0
system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
[system.cpu.dtb]
type=SparcTLB
size=64
[system.cpu.icache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=131072
subblock_size=0
system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.interrupts]
type=SparcInterrupts
[system.cpu.itb]
type=SparcTLB
size=64
[system.cpu.l2cache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=false
latency=10000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=2097152
subblock_size=0
system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
[system.cpu.toL2Bus]
type=CoherentBus
block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=insttest
cwd=
egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/regression/test-progs/insttest/bin/sparc/linux/insttest
gid=100
input=cin
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=0
system=system
uid=100
[system.membus]
type=CoherentBus
block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
master=system.physmem.port[0]
slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=SimpleMemory
conf_table_reported=false
file=
in_addr_map=true
latency=30000
latency_var=0
null=false
range=0:134217727
zero=false
port=system.membus.master[0]

2
simulators/gem5/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simerr Executable file
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@ -0,0 +1,2 @@
warn: Sockets disabled, not accepting gdb connections
hack: be nice to actually delete the event here

21
simulators/gem5/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simout Executable file
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@ -0,0 +1,21 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 4 2012 12:01:47
gem5 started Jun 4 2012 14:45:13
gem5 executing on zizzer
command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Begining test of difficult SPARC instructions...
LDSTUB: Passed
SWAP: Passed
CAS FAIL: Passed
CAS WORK: Passed
CASX FAIL: Passed
CASX WORK: Passed
LDTX: Passed
LDTW: Passed
STTW: Passed
Done
Exiting @ tick 41800000 because target called exit()

359
simulators/gem5/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt Normal file
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@ -0,0 +1,359 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000042 # Number of seconds simulated
sim_ticks 41800000 # Number of ticks simulated
final_tick 41800000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 488993 # Simulator instruction rate (inst/s)
host_op_rate 488707 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1345414902 # Simulator tick rate (ticks/s)
host_mem_usage 221064 # Number of bytes of host memory used
host_seconds 0.03 # Real time elapsed on the host
sim_insts 15175 # Number of instructions simulated
sim_ops 15175 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 8832 # Number of bytes read from this memory
system.physmem.bytes_read::total 26624 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 17792 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 17792 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 278 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory
system.physmem.num_reads::total 416 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 425645933 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 211291866 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 636937799 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 425645933 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 425645933 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 425645933 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 211291866 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 636937799 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 18 # Number of system calls
system.cpu.numCycles 83600 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 15175 # Number of instructions committed
system.cpu.committedOps 15175 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 12231 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu.num_func_calls 385 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 2435 # number of instructions that are conditional controls
system.cpu.num_int_insts 12231 # number of integer instructions
system.cpu.num_fp_insts 0 # number of float instructions
system.cpu.num_int_register_reads 29059 # number of times the integer registers were read
system.cpu.num_int_register_writes 13831 # number of times the integer registers were written
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_mem_refs 3684 # number of memory refs
system.cpu.num_load_insts 2232 # Number of load instructions
system.cpu.num_store_insts 1452 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 83600 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.icache.replacements 0 # number of replacements
system.cpu.icache.tagsinuse 153.436702 # Cycle average of tags in use
system.cpu.icache.total_refs 14941 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 280 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 53.360714 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 153.436702 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.074920 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.074920 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 14941 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 14941 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 14941 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 14941 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 14941 # number of overall hits
system.cpu.icache.overall_hits::total 14941 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 280 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 280 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 280 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 280 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 280 # number of overall misses
system.cpu.icache.overall_misses::total 280 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 15596000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 15596000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 15596000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 15596000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 15596000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 15596000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 15221 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 15221 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 15221 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 15221 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 15221 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 15221 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.018396 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.018396 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.018396 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.018396 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.018396 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.018396 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55700 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 55700 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 55700 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 55700 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 55700 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 55700 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 280 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 280 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 280 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 280 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 280 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 280 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14756000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 14756000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14756000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 14756000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14756000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 14756000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.018396 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.018396 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.018396 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.018396 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.018396 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.018396 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52700 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52700 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52700 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 52700 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52700 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 52700 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.tagsinuse 97.842991 # Cycle average of tags in use
system.cpu.dcache.total_refs 3536 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 25.623188 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 97.842991 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.023887 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.023887 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 2173 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 2173 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 1357 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 1357 # number of WriteReq hits
system.cpu.dcache.SwapReq_hits::cpu.data 6 # number of SwapReq hits
system.cpu.dcache.SwapReq_hits::total 6 # number of SwapReq hits
system.cpu.dcache.demand_hits::cpu.data 3530 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 3530 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 3530 # number of overall hits
system.cpu.dcache.overall_hits::total 3530 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 53 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 53 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 85 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 85 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 138 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 138 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 138 # number of overall misses
system.cpu.dcache.overall_misses::total 138 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 2968000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 2968000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 4760000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 4760000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 7728000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 7728000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 7728000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 7728000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 2226 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 2226 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 1442 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SwapReq_accesses::cpu.data 6 # number of SwapReq accesses(hits+misses)
system.cpu.dcache.SwapReq_accesses::total 6 # number of SwapReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 3668 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 3668 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 3668 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 3668 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.023810 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.023810 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.058946 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.058946 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.037623 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.037623 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.037623 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.037623 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56000 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 56000 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56000 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 56000 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 56000 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 56000 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 56000 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 56000 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 53 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 53 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 85 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 85 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2809000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2809000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4505000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 4505000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7314000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 7314000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7314000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 7314000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.023810 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.023810 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.058946 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.058946 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.037623 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.037623 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037623 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.037623 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 184.236128 # Cycle average of tags in use
system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 331 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.006042 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::cpu.inst 152.765242 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 31.470886 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::cpu.inst 0.004662 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.000960 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.005622 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits
system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits
system.cpu.l2cache.overall_hits::total 2 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 278 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 53 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 331 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 85 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 85 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 278 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 138 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 416 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 278 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 138 # number of overall misses
system.cpu.l2cache.overall_misses::total 416 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14456000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2756000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 17212000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4420000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 4420000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 14456000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 7176000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 21632000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 14456000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 7176000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 21632000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 280 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 53 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 333 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 85 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 85 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 280 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 138 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 418 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 280 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 138 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 418 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.992857 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.993994 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.992857 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.995215 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.992857 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.995215 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 278 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 53 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 331 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 85 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 85 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 278 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 416 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 278 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 416 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11120000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2120000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13240000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3400000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3400000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11120000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5520000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 16640000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11120000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5520000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 16640000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.992857 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.993994 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.992857 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.995215 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.992857 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.995215 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

30
simulators/gem5/tests/quick/se/02.insttest/test.py Normal file
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@ -0,0 +1,30 @@
# Copyright (c) 2007 The Regents of The University of Michigan
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Ali Saidi
root.system.cpu.workload = LiveProcess(cmd = 'insttest',
executable = binpath('insttest'))