christoph/fail
1
Fork 0
Code Actions Packages Releases Activity

Adding gem5 source to svn.

Browse Source 
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1819 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
This commit is contained in:
friemel
2012-10-24 19:18:57 +00:00
parent f7ff71bd46
commit b41eec3f65
3222 changed files with 658579 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

44
simulators/gem5/tests/quick/se/00.hello.mp/test.py Normal file
View File

@ -0,0 +1,44 @@
# Copyright (c) 2006 The Regents of The University of Michigan
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Ron Dreslinski
# workload
benchmarks = [
"tests/test-progs/hello/bin/alpha/linux/hello", "'hello'",
"tests/test-progs/hello/bin/alpha/linux/hello", "'hello'",
"tests/test-progs/hello/bin/alpha/linux/hello", "'hello'",
"tests/test-progs/hello/bin/alpha/linux/hello", "'hello'",
]
for i, cpu in zip(range(len(cpus)), root.system.cpu):
p = LiveProcess()
p.executable = benchmarks[i*2]
p.cmd = benchmarks[(i*2)+1]
root.system.cpu[i].workload = p
root.system.cpu[i].max_insts_all_threads = 10000000
#root.system.cpu.workload = LiveProcess(cmd = 'hello',
# executable = binpath('hello'))

231
simulators/gem5/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/config.ini Normal file
View File

@ -0,0 +1,231 @@
[root]
type=Root
children=system
full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
boot_osflags=a
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
readfile=
symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.cpu]
type=InOrderCPU
children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
BTBEntries=4096
BTBTagSize=16
RASSize=16
activity=0
cachePorts=2
checker=Null
choiceCtrBits=2
choicePredictorSize=8192
clock=500
cpu_id=0
defer_registration=false
div16Latency=1
div16RepeatRate=1
div24Latency=1
div24RepeatRate=1
div32Latency=1
div32RepeatRate=1
div8Latency=1
div8RepeatRate=1
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
fetchBuffSize=4
functionTrace=false
functionTraceStart=0
function_trace=false
function_trace_start=0
globalCtrBits=2
globalHistoryBits=13
globalPredictorSize=8192
instShiftAmt=2
interrupts=system.cpu.interrupts
itb=system.cpu.itb
localCtrBits=2
localHistoryBits=11
localHistoryTableSize=2048
localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
memBlockSize=64
multLatency=1
multRepeatRate=1
numThreads=1
phase=0
predType=tournament
profile=0
progress_interval=0
stageTracing=false
stageWidth=4
system=system
threadModel=SMT
tracer=system.cpu.tracer
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=262144
subblock_size=0
system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
[system.cpu.dtb]
type=AlphaTLB
size=64
[system.cpu.icache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=131072
subblock_size=0
system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.interrupts]
type=AlphaInterrupts
[system.cpu.itb]
type=AlphaTLB
size=48
[system.cpu.l2cache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=false
latency=10000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=2097152
subblock_size=0
system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
[system.cpu.toL2Bus]
type=CoherentBus
block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=hello
cwd=
egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
gid=100
input=cin
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=0
system=system
uid=100
[system.membus]
type=CoherentBus
block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
master=system.physmem.port[0]
slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=SimpleMemory
conf_table_reported=false
file=
in_addr_map=true
latency=30000
latency_var=0
null=false
range=0:134217727
zero=false
port=system.membus.master[0]

2
simulators/gem5/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simerr Executable file
View File

@ -0,0 +1,2 @@
warn: Sockets disabled, not accepting gdb connections
hack: be nice to actually delete the event here

12
simulators/gem5/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simout Executable file
View File

@ -0,0 +1,12 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 4 2012 11:50:11
gem5 started Jun 4 2012 14:15:31
gem5 executing on zizzer
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/inorder-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/inorder-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello world!
Exiting @ tick 21234500 because target called exit()

447
simulators/gem5/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt Normal file
View File

@ -0,0 +1,447 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000021 # Number of seconds simulated
sim_ticks 21234500 # Number of ticks simulated
final_tick 21234500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 73768 # Simulator instruction rate (inst/s)
host_op_rate 73752 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 244499363 # Simulator tick rate (ticks/s)
host_mem_usage 214444 # Number of bytes of host memory used
host_seconds 0.09 # Real time elapsed on the host
sim_insts 6404 # Number of instructions simulated
sim_ops 6404 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 19264 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 10752 # Number of bytes read from this memory
system.physmem.bytes_read::total 30016 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 19264 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 19264 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 301 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 168 # Number of read requests responded to by this memory
system.physmem.num_reads::total 469 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 907202901 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 506345805 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 1413548706 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 907202901 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 907202901 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 907202901 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 506345805 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 1413548706 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 1186 # DTB read hits
system.cpu.dtb.read_misses 7 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 1193 # DTB read accesses
system.cpu.dtb.write_hits 898 # DTB write hits
system.cpu.dtb.write_misses 3 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 901 # DTB write accesses
system.cpu.dtb.data_hits 2084 # DTB hits
system.cpu.dtb.data_misses 10 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 2094 # DTB accesses
system.cpu.itb.fetch_hits 908 # ITB hits
system.cpu.itb.fetch_misses 17 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 925 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 17 # Number of system calls
system.cpu.numCycles 42470 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.branch_predictor.lookups 1608 # Number of BP lookups
system.cpu.branch_predictor.condPredicted 1127 # Number of conditional branches predicted
system.cpu.branch_predictor.condIncorrect 712 # Number of conditional branches incorrect
system.cpu.branch_predictor.BTBLookups 1187 # Number of BTB lookups
system.cpu.branch_predictor.BTBHits 314 # Number of BTB hits
system.cpu.branch_predictor.usedRAS 126 # Number of times the RAS was used to get a target.
system.cpu.branch_predictor.RASInCorrect 0 # Number of incorrect RAS predictions.
system.cpu.branch_predictor.BTBHitPct 26.453243 # BTB Hit Percentage
system.cpu.branch_predictor.predictedTaken 464 # Number of Branches Predicted As Taken (True).
system.cpu.branch_predictor.predictedNotTaken 1144 # Number of Branches Predicted As Not Taken (False).
system.cpu.regfile_manager.intRegFileReads 5213 # Number of Reads from Int. Register File
system.cpu.regfile_manager.intRegFileWrites 4580 # Number of Writes to Int. Register File
system.cpu.regfile_manager.intRegFileAccesses 9793 # Total Accesses (Read+Write) to the Int. Register File
system.cpu.regfile_manager.floatRegFileReads 8 # Number of Reads from FP Register File
system.cpu.regfile_manager.floatRegFileWrites 2 # Number of Writes to FP Register File
system.cpu.regfile_manager.floatRegFileAccesses 10 # Total Accesses (Read+Write) to the FP Register File
system.cpu.regfile_manager.regForwards 2970 # Number of Registers Read Through Forwarding Logic
system.cpu.agen_unit.agens 2183 # Number of Address Generations
system.cpu.execution_unit.predictedTakenIncorrect 284 # Number of Branches Incorrectly Predicted As Taken.
system.cpu.execution_unit.predictedNotTakenIncorrect 367 # Number of Branches Incorrectly Predicted As Not Taken).
system.cpu.execution_unit.mispredicted 651 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.predicted 401 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.mispredictPct 61.882129 # Percentage of Incorrect Branches Predicts
system.cpu.execution_unit.executions 4474 # Number of Instructions Executed.
system.cpu.mult_div_unit.multiplies 1 # Number of Multipy Operations Executed
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
system.cpu.contextSwitches 1 # Number of context switches
system.cpu.threadCycles 11434 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
system.cpu.timesIdled 443 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 35079 # Number of cycles cpu's stages were not processed
system.cpu.runCycles 7391 # Number of cycles cpu stages are processed.
system.cpu.activity 17.402873 # Percentage of cycles cpu is active
system.cpu.comLoads 1185 # Number of Load instructions committed
system.cpu.comStores 865 # Number of Store instructions committed
system.cpu.comBranches 1051 # Number of Branches instructions committed
system.cpu.comNops 17 # Number of Nop instructions committed
system.cpu.comNonSpec 17 # Number of Non-Speculative instructions committed
system.cpu.comInts 3265 # Number of Integer instructions committed
system.cpu.comFloats 2 # Number of Floating Point instructions committed
system.cpu.committedInsts 6404 # Number of Instructions committed (Per-Thread)
system.cpu.committedOps 6404 # Number of Ops committed (Per-Thread)
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
system.cpu.committedInsts_total 6404 # Number of Instructions committed (Total)
system.cpu.cpi 6.631793 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.smt_cpi nan # CPI: Total SMT-CPI
system.cpu.cpi_total 6.631793 # CPI: Total CPI of All Threads
system.cpu.ipc 0.150789 # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.smt_ipc nan # IPC: Total SMT-IPC
system.cpu.ipc_total 0.150789 # IPC: Total IPC of All Threads
system.cpu.stage0.idleCycles 37550 # Number of cycles 0 instructions are processed.
system.cpu.stage0.runCycles 4920 # Number of cycles 1+ instructions are processed.
system.cpu.stage0.utilization 11.584648 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage1.idleCycles 38585 # Number of cycles 0 instructions are processed.
system.cpu.stage1.runCycles 3885 # Number of cycles 1+ instructions are processed.
system.cpu.stage1.utilization 9.147634 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage2.idleCycles 38290 # Number of cycles 0 instructions are processed.
system.cpu.stage2.runCycles 4180 # Number of cycles 1+ instructions are processed.
system.cpu.stage2.utilization 9.842242 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage3.idleCycles 41130 # Number of cycles 0 instructions are processed.
system.cpu.stage3.runCycles 1340 # Number of cycles 1+ instructions are processed.
system.cpu.stage3.utilization 3.155168 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage4.idleCycles 38002 # Number of cycles 0 instructions are processed.
system.cpu.stage4.runCycles 4468 # Number of cycles 1+ instructions are processed.
system.cpu.stage4.utilization 10.520367 # Percentage of cycles stage was utilized (processing insts).
system.cpu.icache.replacements 0 # number of replacements
system.cpu.icache.tagsinuse 138.955928 # Cycle average of tags in use
system.cpu.icache.total_refs 558 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 301 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 1.853821 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 138.955928 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.067850 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.067850 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 558 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 558 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 558 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 558 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 558 # number of overall hits
system.cpu.icache.overall_hits::total 558 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 350 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 350 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 350 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 350 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 350 # number of overall misses
system.cpu.icache.overall_misses::total 350 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 19343500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 19343500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 19343500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 19343500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 19343500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 19343500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 908 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 908 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 908 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 908 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 908 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 908 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.385463 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.385463 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.385463 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.385463 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.385463 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.385463 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55267.142857 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 55267.142857 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 55267.142857 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 55267.142857 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 55267.142857 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 55267.142857 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 48 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 48 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 48 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 48 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 48 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 48 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 302 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 302 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 302 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 302 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 302 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 302 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16051500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 16051500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16051500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 16051500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16051500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 16051500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.332599 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.332599 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.332599 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.332599 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.332599 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.332599 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53150.662252 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53150.662252 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53150.662252 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 53150.662252 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53150.662252 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 53150.662252 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.tagsinuse 102.711534 # Cycle average of tags in use
system.cpu.dcache.total_refs 1703 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 168 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 10.136905 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 102.711534 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.025076 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.025076 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 1088 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 1088 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 615 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 615 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 1703 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 1703 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 1703 # number of overall hits
system.cpu.dcache.overall_hits::total 1703 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 97 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 97 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 250 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 250 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 347 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 347 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 347 # number of overall misses
system.cpu.dcache.overall_misses::total 347 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 5507500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 5507500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 13555000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 13555000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 19062500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 19062500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 19062500 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 19062500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 1185 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 1185 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 2050 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 2050 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 2050 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 2050 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.081857 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.081857 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289017 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.289017 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.169268 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.169268 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.169268 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.169268 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56778.350515 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 56778.350515 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54220 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 54220 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 54935.158501 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 54935.158501 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 54935.158501 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 54935.158501 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 1656000 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 36 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 46000 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 2 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 177 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 177 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 179 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 179 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 179 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 179 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 95 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 95 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 168 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 168 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 168 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5113000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 5113000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3909500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3909500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9022500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 9022500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9022500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 9022500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.080169 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.080169 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.081951 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.081951 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.081951 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.081951 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53821.052632 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53821.052632 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53554.794521 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53554.794521 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53705.357143 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 53705.357143 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53705.357143 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 53705.357143 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 195.300582 # Cycle average of tags in use
system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 395 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.002532 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::cpu.inst 139.031748 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 56.268833 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::cpu.inst 0.004243 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.001717 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.005960 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits
system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits
system.cpu.l2cache.overall_hits::total 1 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 301 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 95 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 396 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 73 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 73 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 301 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 168 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 469 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 301 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 168 # number of overall misses
system.cpu.l2cache.overall_misses::total 469 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15708000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4994000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 20702000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3821500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 3821500 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 15708000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 8815500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 24523500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 15708000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 8815500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 24523500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 302 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 95 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 397 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 73 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 302 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 168 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 470 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 302 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 168 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 470 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996689 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.997481 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996689 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.997872 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996689 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.997872 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52186.046512 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52568.421053 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52277.777778 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52349.315068 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52349.315068 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52186.046512 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52473.214286 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 52288.912580 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52186.046512 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52473.214286 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 52288.912580 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 301 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 95 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 396 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 73 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 73 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 301 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 168 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 469 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 301 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 469 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12038500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3838000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15876500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2942500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2942500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12038500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6780500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 18819000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12038500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6780500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 18819000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997481 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.997872 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.997872 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39995.016611 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40400 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40092.171717 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40308.219178 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40308.219178 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39995.016611 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40360.119048 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40125.799574 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39995.016611 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40360.119048 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40125.799574 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

529
simulators/gem5/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini Normal file
View File

@ -0,0 +1,529 @@
[root]
type=Root
children=system
full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
boot_osflags=a
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
readfile=
symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.cpu]
type=DerivO3CPU
children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
LSQDepCheckShift=4
RASSize=16
SQEntries=32
SSITSize=1024
activity=0
backComSize=5
cachePorts=200
checker=Null
choiceCtrBits=2
choicePredictorSize=8192
clock=500
commitToDecodeDelay=1
commitToFetchDelay=1
commitToIEWDelay=1
commitToRenameDelay=1
commitWidth=8
cpu_id=0
decodeToFetchDelay=1
decodeToRenameDelay=1
decodeWidth=8
defer_registration=false
dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
fetchToDecodeDelay=1
fetchTrapLatency=1
fetchWidth=8
forwardComSize=5
fuPool=system.cpu.fuPool
function_trace=false
function_trace_start=0
globalCtrBits=2
globalHistoryBits=13
globalPredictorSize=8192
iewToCommitDelay=1
iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
instShiftAmt=2
interrupts=system.cpu.interrupts
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
localCtrBits=2
localHistoryBits=11
localHistoryTableSize=2048
localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
needsTSO=false
numIQEntries=64
numPhysFloatRegs=256
numPhysIntRegs=256
numROBEntries=192
numRobs=1
numThreads=1
phase=0
predType=tournament
profile=0
progress_interval=0
renameToDecodeDelay=1
renameToFetchDelay=1
renameToIEWDelay=2
renameToROBDelay=1
renameWidth=8
smtCommitPolicy=RoundRobin
smtFetchPolicy=SingleThread
smtIQPolicy=Partitioned
smtIQThreshold=100
smtLSQPolicy=Partitioned
smtLSQThreshold=100
smtNumFetchingThreads=1
smtROBPolicy=Partitioned
smtROBThreshold=100
squashWidth=8
store_set_clear_period=250000
system=system
tracer=system.cpu.tracer
trapLatency=13
wbDepth=1
wbWidth=8
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=262144
subblock_size=0
system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
[system.cpu.dtb]
type=AlphaTLB
size=64
[system.cpu.fuPool]
type=FUPool
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
[system.cpu.fuPool.FUList0]
type=FUDesc
children=opList
count=6
opList=system.cpu.fuPool.FUList0.opList
[system.cpu.fuPool.FUList0.opList]
type=OpDesc
issueLat=1
opClass=IntAlu
opLat=1
[system.cpu.fuPool.FUList1]
type=FUDesc
children=opList0 opList1
count=2
opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
[system.cpu.fuPool.FUList1.opList0]
type=OpDesc
issueLat=1
opClass=IntMult
opLat=3
[system.cpu.fuPool.FUList1.opList1]
type=OpDesc
issueLat=19
opClass=IntDiv
opLat=20
[system.cpu.fuPool.FUList2]
type=FUDesc
children=opList0 opList1 opList2
count=4
opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
[system.cpu.fuPool.FUList2.opList0]
type=OpDesc
issueLat=1
opClass=FloatAdd
opLat=2
[system.cpu.fuPool.FUList2.opList1]
type=OpDesc
issueLat=1
opClass=FloatCmp
opLat=2
[system.cpu.fuPool.FUList2.opList2]
type=OpDesc
issueLat=1
opClass=FloatCvt
opLat=2
[system.cpu.fuPool.FUList3]
type=FUDesc
children=opList0 opList1 opList2
count=2
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
[system.cpu.fuPool.FUList3.opList0]
type=OpDesc
issueLat=1
opClass=FloatMult
opLat=4
[system.cpu.fuPool.FUList3.opList1]
type=OpDesc
issueLat=12
opClass=FloatDiv
opLat=12
[system.cpu.fuPool.FUList3.opList2]
type=OpDesc
issueLat=24
opClass=FloatSqrt
opLat=24
[system.cpu.fuPool.FUList4]
type=FUDesc
children=opList
count=0
opList=system.cpu.fuPool.FUList4.opList
[system.cpu.fuPool.FUList4.opList]
type=OpDesc
issueLat=1
opClass=MemRead
opLat=1
[system.cpu.fuPool.FUList5]
type=FUDesc
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
count=4
opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
[system.cpu.fuPool.FUList5.opList00]
type=OpDesc
issueLat=1
opClass=SimdAdd
opLat=1
[system.cpu.fuPool.FUList5.opList01]
type=OpDesc
issueLat=1
opClass=SimdAddAcc
opLat=1
[system.cpu.fuPool.FUList5.opList02]
type=OpDesc
issueLat=1
opClass=SimdAlu
opLat=1
[system.cpu.fuPool.FUList5.opList03]
type=OpDesc
issueLat=1
opClass=SimdCmp
opLat=1
[system.cpu.fuPool.FUList5.opList04]
type=OpDesc
issueLat=1
opClass=SimdCvt
opLat=1
[system.cpu.fuPool.FUList5.opList05]
type=OpDesc
issueLat=1
opClass=SimdMisc
opLat=1
[system.cpu.fuPool.FUList5.opList06]
type=OpDesc
issueLat=1
opClass=SimdMult
opLat=1
[system.cpu.fuPool.FUList5.opList07]
type=OpDesc
issueLat=1
opClass=SimdMultAcc
opLat=1
[system.cpu.fuPool.FUList5.opList08]
type=OpDesc
issueLat=1
opClass=SimdShift
opLat=1
[system.cpu.fuPool.FUList5.opList09]
type=OpDesc
issueLat=1
opClass=SimdShiftAcc
opLat=1
[system.cpu.fuPool.FUList5.opList10]
type=OpDesc
issueLat=1
opClass=SimdSqrt
opLat=1
[system.cpu.fuPool.FUList5.opList11]
type=OpDesc
issueLat=1
opClass=SimdFloatAdd
opLat=1
[system.cpu.fuPool.FUList5.opList12]
type=OpDesc
issueLat=1
opClass=SimdFloatAlu
opLat=1
[system.cpu.fuPool.FUList5.opList13]
type=OpDesc
issueLat=1
opClass=SimdFloatCmp
opLat=1
[system.cpu.fuPool.FUList5.opList14]
type=OpDesc
issueLat=1
opClass=SimdFloatCvt
opLat=1
[system.cpu.fuPool.FUList5.opList15]
type=OpDesc
issueLat=1
opClass=SimdFloatDiv
opLat=1
[system.cpu.fuPool.FUList5.opList16]
type=OpDesc
issueLat=1
opClass=SimdFloatMisc
opLat=1
[system.cpu.fuPool.FUList5.opList17]
type=OpDesc
issueLat=1
opClass=SimdFloatMult
opLat=1
[system.cpu.fuPool.FUList5.opList18]
type=OpDesc
issueLat=1
opClass=SimdFloatMultAcc
opLat=1
[system.cpu.fuPool.FUList5.opList19]
type=OpDesc
issueLat=1
opClass=SimdFloatSqrt
opLat=1
[system.cpu.fuPool.FUList6]
type=FUDesc
children=opList
count=0
opList=system.cpu.fuPool.FUList6.opList
[system.cpu.fuPool.FUList6.opList]
type=OpDesc
issueLat=1
opClass=MemWrite
opLat=1
[system.cpu.fuPool.FUList7]
type=FUDesc
children=opList0 opList1
count=4
opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
[system.cpu.fuPool.FUList7.opList0]
type=OpDesc
issueLat=1
opClass=MemRead
opLat=1
[system.cpu.fuPool.FUList7.opList1]
type=OpDesc
issueLat=1
opClass=MemWrite
opLat=1
[system.cpu.fuPool.FUList8]
type=FUDesc
children=opList
count=1
opList=system.cpu.fuPool.FUList8.opList
[system.cpu.fuPool.FUList8.opList]
type=OpDesc
issueLat=3
opClass=IprAccess
opLat=3
[system.cpu.icache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=131072
subblock_size=0
system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.interrupts]
type=AlphaInterrupts
[system.cpu.itb]
type=AlphaTLB
size=48
[system.cpu.l2cache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=false
latency=1000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=2097152
subblock_size=0
system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
[system.cpu.toL2Bus]
type=CoherentBus
block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=hello
cwd=
egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
gid=100
input=cin
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=0
system=system
uid=100
[system.membus]
type=CoherentBus
block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
master=system.physmem.port[0]
slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=SimpleMemory
conf_table_reported=false
file=
in_addr_map=true
latency=30000
latency_var=0
null=false
range=0:134217727
zero=false
port=system.membus.master[0]

2
simulators/gem5/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simerr Executable file
View File

@ -0,0 +1,2 @@
warn: Sockets disabled, not accepting gdb connections
hack: be nice to actually delete the event here

12
simulators/gem5/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout Executable file
View File

@ -0,0 +1,12 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 4 2012 11:50:11
gem5 started Jun 4 2012 14:03:27
gem5 executing on zizzer
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello world!
Exiting @ tick 12450500 because target called exit()

648
simulators/gem5/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt Normal file
View File

@ -0,0 +1,648 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000012 # Number of seconds simulated
sim_ticks 12450500 # Number of ticks simulated
final_tick 12450500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 73568 # Simulator instruction rate (inst/s)
host_op_rate 73552 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 143373020 # Simulator tick rate (ticks/s)
host_mem_usage 215332 # Number of bytes of host memory used
host_seconds 0.09 # Real time elapsed on the host
sim_insts 6386 # Number of instructions simulated
sim_ops 6386 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 20096 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 11264 # Number of bytes read from this memory
system.physmem.bytes_read::total 31360 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 20096 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 20096 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 314 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 176 # Number of read requests responded to by this memory
system.physmem.num_reads::total 490 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 1614071724 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 904702622 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 2518774346 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 1614071724 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 1614071724 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 1614071724 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 904702622 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 2518774346 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 1943 # DTB read hits
system.cpu.dtb.read_misses 53 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 1996 # DTB read accesses
system.cpu.dtb.write_hits 1071 # DTB write hits
system.cpu.dtb.write_misses 32 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 1103 # DTB write accesses
system.cpu.dtb.data_hits 3014 # DTB hits
system.cpu.dtb.data_misses 85 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 3099 # DTB accesses
system.cpu.itb.fetch_hits 2367 # ITB hits
system.cpu.itb.fetch_misses 26 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 2393 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 17 # Number of system calls
system.cpu.numCycles 24902 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.BPredUnit.lookups 2873 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 1642 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 561 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 2186 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 748 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 430 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 100 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 7799 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 16643 # Number of instructions fetch has processed
system.cpu.fetch.Branches 2873 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 1178 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 2979 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 1864 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 854 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 22 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 590 # Number of stall cycles due to pending traps
system.cpu.fetch.CacheLines 2367 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 368 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 13505 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 1.232358 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.611762 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 10526 77.94% 77.94% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 289 2.14% 80.08% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 251 1.86% 81.94% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 257 1.90% 83.84% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 272 2.01% 85.86% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 206 1.53% 87.38% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 248 1.84% 89.22% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 173 1.28% 90.50% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 1283 9.50% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 13505 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.115372 # Number of branch fetches per cycle
system.cpu.fetch.rate 0.668340 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 8546 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 938 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 2784 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 62 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 1175 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 292 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 96 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 15310 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 265 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 1175 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 8782 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 334 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 357 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 2587 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 270 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 14488 # Number of instructions processed by rename
system.cpu.rename.IQFullEvents 7 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 212 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenamedOperands 10864 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 18125 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 18108 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 17 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 4583 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 6281 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 28 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 22 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 777 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 2616 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 1352 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 7 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 12765 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 26 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 10522 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 44 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 6026 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 3602 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 9 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 13505 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 0.779119 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.404443 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 9165 67.86% 67.86% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 1484 10.99% 78.85% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 1164 8.62% 87.47% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 762 5.64% 93.11% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 469 3.47% 96.59% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 274 2.03% 98.62% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 142 1.05% 99.67% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 34 0.25% 99.92% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 11 0.08% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 13505 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 10 8.93% 8.93% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 8.93% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 8.93% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.93% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.93% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.93% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 8.93% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.93% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.93% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.93% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.93% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.93% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.93% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.93% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.93% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 8.93% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.93% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 8.93% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.93% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.93% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.93% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.93% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.93% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.93% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.93% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.93% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.93% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.93% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.93% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 65 58.04% 66.96% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 37 33.04% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 7148 67.93% 67.95% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.96% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.96% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.98% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.98% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.98% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.98% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.98% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.98% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.98% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.98% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.98% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.98% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.98% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.98% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.98% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.98% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.98% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.98% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.98% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.98% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.98% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.98% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.98% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.98% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.98% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.98% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.98% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.98% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 2225 21.15% 89.13% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 1144 10.87% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 10522 # Type of FU issued
system.cpu.iq.rate 0.422536 # Inst issue rate
system.cpu.iq.fu_busy_cnt 112 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.010644 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 34684 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 18825 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 9477 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 10 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 10621 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 11 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 63 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 1431 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 487 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 1175 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 41 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 1 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 12870 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 183 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 2616 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 1352 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 26 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 19 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 166 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 401 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 567 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 9878 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 2009 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 644 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 79 # number of nop insts executed
system.cpu.iew.exec_refs 3117 # number of memory reference insts executed
system.cpu.iew.exec_branches 1605 # Number of branches executed
system.cpu.iew.exec_stores 1108 # Number of stores executed
system.cpu.iew.exec_rate 0.396675 # Inst execution rate
system.cpu.iew.wb_sent 9634 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 9487 # cumulative count of insts written-back
system.cpu.iew.wb_producers 4957 # num instructions producing a value
system.cpu.iew.wb_consumers 6732 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 0.380973 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.736334 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitCommittedInsts 6403 # The number of committed instructions
system.cpu.commit.commitCommittedOps 6403 # The number of committed instructions
system.cpu.commit.commitSquashedInsts 6436 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 475 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 12330 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 0.519303 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.354208 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 9591 77.79% 77.79% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 1448 11.74% 89.53% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 489 3.97% 93.50% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 259 2.10% 95.60% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 152 1.23% 96.83% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 96 0.78% 97.61% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 104 0.84% 98.45% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 40 0.32% 98.78% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 151 1.22% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 12330 # Number of insts commited each cycle
system.cpu.commit.committedInsts 6403 # Number of instructions committed
system.cpu.commit.committedOps 6403 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 2050 # Number of memory references committed
system.cpu.commit.loads 1185 # Number of loads committed
system.cpu.commit.membars 0 # Number of memory barriers committed
system.cpu.commit.branches 1051 # Number of branches committed
system.cpu.commit.fp_insts 10 # Number of committed floating point instructions.
system.cpu.commit.int_insts 6321 # Number of committed integer instructions.
system.cpu.commit.function_calls 127 # Number of function calls committed.
system.cpu.commit.bw_lim_events 151 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 24667 # The number of ROB reads
system.cpu.rob.rob_writes 26868 # The number of ROB writes
system.cpu.timesIdled 232 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 11397 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 6386 # Number of Instructions Simulated
system.cpu.committedOps 6386 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 6386 # Number of Instructions Simulated
system.cpu.cpi 3.899468 # CPI: Cycles Per Instruction
system.cpu.cpi_total 3.899468 # CPI: Total CPI of All Threads
system.cpu.ipc 0.256445 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.256445 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 12526 # number of integer regfile reads
system.cpu.int_regfile_writes 7116 # number of integer regfile writes
system.cpu.fp_regfile_reads 8 # number of floating regfile reads
system.cpu.fp_regfile_writes 2 # number of floating regfile writes
system.cpu.misc_regfile_reads 1 # number of misc regfile reads
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
system.cpu.icache.replacements 0 # number of replacements
system.cpu.icache.tagsinuse 162.256588 # Cycle average of tags in use
system.cpu.icache.total_refs 1909 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 315 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 6.060317 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 162.256588 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.079227 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.079227 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 1909 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 1909 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 1909 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 1909 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 1909 # number of overall hits
system.cpu.icache.overall_hits::total 1909 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 458 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 458 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 458 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 458 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 458 # number of overall misses
system.cpu.icache.overall_misses::total 458 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 16026500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 16026500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 16026500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 16026500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 16026500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 16026500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 2367 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 2367 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 2367 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 2367 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 2367 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 2367 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.193494 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.193494 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.193494 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.193494 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.193494 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.193494 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34992.358079 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 34992.358079 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 34992.358079 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 34992.358079 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 34992.358079 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 34992.358079 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 143 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 143 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 143 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 143 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 143 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 143 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 315 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 315 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 315 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 315 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 315 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 315 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11133500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 11133500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11133500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 11133500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11133500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 11133500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.133080 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.133080 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.133080 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.133080 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.133080 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.133080 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35344.444444 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35344.444444 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35344.444444 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 35344.444444 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35344.444444 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 35344.444444 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.tagsinuse 109.847039 # Cycle average of tags in use
system.cpu.dcache.total_refs 2244 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 175 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 12.822857 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 109.847039 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.026818 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.026818 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 1735 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 1735 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 509 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 509 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 2244 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 2244 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 2244 # number of overall hits
system.cpu.dcache.overall_hits::total 2244 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 144 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 144 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 356 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 356 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 500 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 500 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 500 # number of overall misses
system.cpu.dcache.overall_misses::total 500 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 5240000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 5240000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 12485500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 12485500 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 17725500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 17725500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 17725500 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 17725500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 1879 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 1879 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 2744 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 2744 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 2744 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 2744 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.076637 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.076637 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.411561 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.411561 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.182216 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.182216 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.182216 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.182216 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36388.888889 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 36388.888889 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35071.629213 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 35071.629213 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 35451 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 35451 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 35451 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 35451 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 40 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 40 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 284 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 284 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 324 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 324 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 324 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 324 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 104 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 104 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 72 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 72 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 176 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 176 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 176 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 176 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3722000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 3722000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2575500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 2575500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6297500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 6297500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6297500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 6297500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.055349 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.055349 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083237 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.083237 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.064140 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.064140 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.064140 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.064140 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35788.461538 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 35788.461538 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35770.833333 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35770.833333 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35781.250000 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 35781.250000 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 35781.250000 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 35781.250000 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 224.787735 # Cycle average of tags in use
system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 418 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.002392 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::cpu.inst 162.229240 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 62.558495 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::cpu.inst 0.004951 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.001909 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.006860 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits
system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits
system.cpu.l2cache.overall_hits::total 1 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 314 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 104 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 418 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 72 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 72 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 314 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 176 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 490 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 314 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 176 # number of overall misses
system.cpu.l2cache.overall_misses::total 490 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 10779500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3600000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 14379500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2488500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 2488500 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 10779500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 6088500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 16868000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 10779500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 6088500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 16868000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 315 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 104 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 419 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 72 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 72 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 315 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 176 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 491 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 315 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 176 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 491 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996825 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.997613 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996825 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.997963 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996825 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.997963 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34329.617834 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34615.384615 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 34400.717703 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34562.500000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34562.500000 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34329.617834 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34593.750000 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 34424.489796 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34329.617834 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34593.750000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 34424.489796 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 314 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 104 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 418 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 72 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 72 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 314 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 176 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 490 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 314 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 176 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 490 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9770500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3273500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13044000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2264000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2264000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9770500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5537500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 15308000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9770500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5537500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 15308000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996825 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997613 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996825 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.997963 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996825 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.997963 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31116.242038 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31475.961538 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31205.741627 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31444.444444 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31444.444444 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31116.242038 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31463.068182 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31240.816327 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31116.242038 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31463.068182 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31240.816327 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

117
simulators/gem5/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/config.ini Normal file
View File

@ -0,0 +1,117 @@
[root]
type=Root
children=system
full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
boot_osflags=a
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
readfile=
symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.cpu]
type=AtomicSimpleCPU
children=dtb interrupts itb tracer workload
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
fastmem=false
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
phase=0
profile=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
system=system
tracer=system.cpu.tracer
width=1
workload=system.cpu.workload
dcache_port=system.membus.slave[2]
icache_port=system.membus.slave[1]
[system.cpu.dtb]
type=AlphaTLB
size=64
[system.cpu.interrupts]
type=AlphaInterrupts
[system.cpu.itb]
type=AlphaTLB
size=48
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=hello
cwd=
egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
gid=100
input=cin
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=0
system=system
uid=100
[system.membus]
type=CoherentBus
block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
master=system.physmem.port[0]
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
[system.physmem]
type=SimpleMemory
conf_table_reported=false
file=
in_addr_map=true
latency=30000
latency_var=0
null=false
range=0:134217727
zero=false
port=system.membus.master[0]

3
simulators/gem5/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simerr Executable file
View File

@ -0,0 +1,3 @@
warn: CoherentBus system.membus has no snooping ports attached!
warn: Sockets disabled, not accepting gdb connections
hack: be nice to actually delete the event here

12
simulators/gem5/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simout Executable file
View File

@ -0,0 +1,12 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 4 2012 11:50:11
gem5 started Jun 4 2012 13:46:44
gem5 executing on zizzer
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-atomic -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello world!
Exiting @ tick 3215000 because target called exit()

92
simulators/gem5/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt Normal file
View File

@ -0,0 +1,92 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000003 # Number of seconds simulated
sim_ticks 3215000 # Number of ticks simulated
final_tick 3215000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1264163 # Simulator instruction rate (inst/s)
host_op_rate 1259559 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 630191855 # Simulator tick rate (ticks/s)
host_mem_usage 205200 # Number of bytes of host memory used
host_seconds 0.01 # Real time elapsed on the host
sim_insts 6404 # Number of instructions simulated
sim_ops 6404 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 25656 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 8804 # Number of bytes read from this memory
system.physmem.bytes_read::total 34460 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 25656 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 25656 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 6696 # Number of bytes written to this memory
system.physmem.bytes_written::total 6696 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 6414 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 1185 # Number of read requests responded to by this memory
system.physmem.num_reads::total 7599 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 865 # Number of write requests responded to by this memory
system.physmem.num_writes::total 865 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 7980093313 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 2738413686 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 10718506998 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 7980093313 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 7980093313 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 2082737170 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 2082737170 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 7980093313 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 4821150855 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 12801244168 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 1185 # DTB read hits
system.cpu.dtb.read_misses 7 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 1192 # DTB read accesses
system.cpu.dtb.write_hits 865 # DTB write hits
system.cpu.dtb.write_misses 3 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 868 # DTB write accesses
system.cpu.dtb.data_hits 2050 # DTB hits
system.cpu.dtb.data_misses 10 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 2060 # DTB accesses
system.cpu.itb.fetch_hits 6414 # ITB hits
system.cpu.itb.fetch_misses 17 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 6431 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 17 # Number of system calls
system.cpu.numCycles 6431 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 6404 # Number of instructions committed
system.cpu.committedOps 6404 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 6331 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses
system.cpu.num_func_calls 251 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 750 # number of instructions that are conditional controls
system.cpu.num_int_insts 6331 # number of integer instructions
system.cpu.num_fp_insts 10 # number of float instructions
system.cpu.num_int_register_reads 8304 # number of times the integer registers were read
system.cpu.num_int_register_writes 4581 # number of times the integer registers were written
system.cpu.num_fp_register_reads 8 # number of times the floating registers were read
system.cpu.num_fp_register_writes 2 # number of times the floating registers were written
system.cpu.num_mem_refs 2060 # number of memory refs
system.cpu.num_load_insts 1192 # Number of load instructions
system.cpu.num_store_insts 868 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 6431 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
---------- End Simulation Statistics ----------

343
simulators/gem5/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/config.ini Normal file
View File

@ -0,0 +1,343 @@
[root]
type=Root
children=system
full_system=false
time_sync_enable=false
time_sync_period=100000000
time_sync_spin_threshold=100000
[system]
type=System
children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby sys_port_proxy
boot_osflags=a
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=timing
memories=system.physmem
num_work_ids=16
readfile=
symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.sys_port_proxy.slave[0]
[system.cpu]
type=TimingSimpleCPU
children=dtb interrupts itb tracer workload
checker=Null
clock=1
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
phase=0
profile=0
progress_interval=0
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
dcache_port=system.l1_cntrl0.sequencer.slave[1]
icache_port=system.l1_cntrl0.sequencer.slave[0]
[system.cpu.dtb]
type=AlphaTLB
size=64
[system.cpu.interrupts]
type=AlphaInterrupts
[system.cpu.itb]
type=AlphaTLB
size=48
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=hello
cwd=
egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
gid=100
input=cin
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=0
system=system
uid=100
[system.dir_cntrl0]
type=Directory_Controller
children=directory memBuffer
buffer_size=0
cntrl_id=2
directory=system.dir_cntrl0.directory
directory_latency=6
memBuffer=system.dir_cntrl0.memBuffer
number_of_TBEs=256
recycle_latency=10
ruby_system=system.ruby
to_mem_ctrl_latency=1
transitions_per_cycle=32
version=0
[system.dir_cntrl0.directory]
type=RubyDirectoryMemory
map_levels=4
numa_high_bit=6
size=134217728
use_map=false
version=0
[system.dir_cntrl0.memBuffer]
type=RubyMemoryControl
bank_bit_0=8
bank_busy_time=11
bank_queue_size=12
banks_per_rank=8
basic_bus_busy_time=2
dimm_bit_0=12
dimms_per_channel=2
mem_bus_cycle_multiplier=10
mem_ctl_latency=12
mem_fixed_delay=0
mem_random_arbitrate=0
rank_bit_0=11
rank_rank_delay=1
ranks_per_dimm=2
read_write_delay=2
refresh_period=1560
tFaw=0
version=0
[system.l1_cntrl0]
type=L1Cache_Controller
children=L1DcacheMemory L1IcacheMemory sequencer
L1DcacheMemory=system.l1_cntrl0.L1DcacheMemory
L1IcacheMemory=system.l1_cntrl0.L1IcacheMemory
buffer_size=0
cntrl_id=0
l1_request_latency=2
l1_response_latency=2
l2_select_num_bits=0
number_of_TBEs=256
recycle_latency=10
ruby_system=system.ruby
send_evictions=false
sequencer=system.l1_cntrl0.sequencer
to_l2_latency=1
transitions_per_cycle=32
version=0
[system.l1_cntrl0.L1DcacheMemory]
type=RubyCache
assoc=2
is_icache=false
latency=3
replacement_policy=PSEUDO_LRU
size=256
start_index_bit=6
[system.l1_cntrl0.L1IcacheMemory]
type=RubyCache
assoc=2
is_icache=false
latency=3
replacement_policy=PSEUDO_LRU
size=256
start_index_bit=6
[system.l1_cntrl0.sequencer]
type=RubySequencer
access_phys_mem=true
dcache=system.l1_cntrl0.L1DcacheMemory
deadlock_threshold=500000
icache=system.l1_cntrl0.L1IcacheMemory
max_outstanding_requests=16
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
system=system
using_network_tester=false
using_ruby_tester=false
version=0
slave=system.cpu.icache_port system.cpu.dcache_port
[system.l2_cntrl0]
type=L2Cache_Controller
children=L2cacheMemory
L2cacheMemory=system.l2_cntrl0.L2cacheMemory
buffer_size=0
cntrl_id=1
l2_request_latency=2
l2_response_latency=2
number_of_TBEs=256
recycle_latency=10
ruby_system=system.ruby
to_l1_latency=1
transitions_per_cycle=32
version=0
[system.l2_cntrl0.L2cacheMemory]
type=RubyCache
assoc=2
is_icache=false
latency=15
replacement_policy=PSEUDO_LRU
size=512
start_index_bit=6
[system.physmem]
type=SimpleMemory
conf_table_reported=false
file=
in_addr_map=true
latency=30
latency_var=0
null=false
range=0:134217727
zero=false
[system.ruby]
type=RubySystem
children=network profiler
block_size_bytes=64
clock=1
mem_size=134217728
no_mem_vec=false
random_seed=1234
randomization=false
stats_filename=ruby.stats
[system.ruby.network]
type=SimpleNetwork
children=topology
adaptive_routing=false
buffer_size=0
control_msg_size=8
endpoint_bandwidth=1000
number_of_virtual_networks=10
ruby_system=system.ruby
topology=system.ruby.network.topology
[system.ruby.network.topology]
type=Topology
children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2 routers0 routers1 routers2 routers3
description=Crossbar
ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2
int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2
print_config=false
routers=system.ruby.network.topology.routers0 system.ruby.network.topology.routers1 system.ruby.network.topology.routers2 system.ruby.network.topology.routers3
[system.ruby.network.topology.ext_links0]
type=SimpleExtLink
bandwidth_factor=16
ext_node=system.l1_cntrl0
int_node=system.ruby.network.topology.routers0
latency=1
link_id=0
weight=1
[system.ruby.network.topology.ext_links1]
type=SimpleExtLink
bandwidth_factor=16
ext_node=system.l2_cntrl0
int_node=system.ruby.network.topology.routers1
latency=1
link_id=1
weight=1
[system.ruby.network.topology.ext_links2]
type=SimpleExtLink
bandwidth_factor=16
ext_node=system.dir_cntrl0
int_node=system.ruby.network.topology.routers2
latency=1
link_id=2
weight=1
[system.ruby.network.topology.int_links0]
type=SimpleIntLink
bandwidth_factor=16
latency=1
link_id=3
node_a=system.ruby.network.topology.routers0
node_b=system.ruby.network.topology.routers3
weight=1
[system.ruby.network.topology.int_links1]
type=SimpleIntLink
bandwidth_factor=16
latency=1
link_id=4
node_a=system.ruby.network.topology.routers1
node_b=system.ruby.network.topology.routers3
weight=1
[system.ruby.network.topology.int_links2]
type=SimpleIntLink
bandwidth_factor=16
latency=1
link_id=5
node_a=system.ruby.network.topology.routers2
node_b=system.ruby.network.topology.routers3
weight=1
[system.ruby.network.topology.routers0]
type=BasicRouter
router_id=0
[system.ruby.network.topology.routers1]
type=BasicRouter
router_id=1
[system.ruby.network.topology.routers2]
type=BasicRouter
router_id=2
[system.ruby.network.topology.routers3]
type=BasicRouter
router_id=3
[system.ruby.profiler]
type=RubyProfiler
all_instructions=false
hot_lines=false
num_of_sequencers=1
ruby_system=system.ruby
[system.sys_port_proxy]
type=RubyPortProxy
access_phys_mem=true
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
system=system
using_network_tester=false
using_ruby_tester=false
version=0
slave=system.system_port

636
simulators/gem5/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats Normal file
View File

@ -0,0 +1,636 @@
================ Begin RubySystem Configuration Print ================
RubySystem config:
random_seed: 1234
randomization: 0
cycle_period: 1
block_size_bytes: 64
block_size_bits: 6
memory_size_bytes: 134217728
memory_size_bits: 27
Network Configuration
---------------------
network: SIMPLE_NETWORK
topology:
virtual_net_0: active, unordered
virtual_net_1: active, unordered
virtual_net_2: active, unordered
virtual_net_3: inactive
virtual_net_4: inactive
virtual_net_5: inactive
virtual_net_6: inactive
virtual_net_7: inactive
virtual_net_8: inactive
virtual_net_9: inactive
Profiler Configuration
----------------------
periodic_stats_period: 1000000
================ End RubySystem Configuration Print ================
Real time: Jun/04/2012 13:42:36
Profiler Stats
--------------
Elapsed_time_in_seconds: 1
Elapsed_time_in_minutes: 0.0166667
Elapsed_time_in_hours: 0.000277778
Elapsed_time_in_days: 1.15741e-05
Virtual_time_in_seconds: 0.43
Virtual_time_in_minutes: 0.00716667
Virtual_time_in_hours: 0.000119444
Virtual_time_in_days: 4.97685e-06
Ruby_current_time: 279353
Ruby_start_time: 0
Ruby_cycles: 279353
mbytes_resident: 49.4727
mbytes_total: 221.031
resident_ratio: 0.223827
ruby_cycles_executed: [ 279354 ]
Busy Controller Counts:
L1Cache-0:0
L2Cache-0:0
Directory-0:0
Busy Bank Count:0
sequencer_requests_outstanding: [binsize: 1 max: 1 count: 8465 average: 1 | standard deviation: 0 | 0 8465 ]
All Non-Zero Cycle Demand Cache Accesses
----------------------------------------
miss_latency: [binsize: 2 max: 297 count: 8464 average: 32.0048 | standard deviation: 63.6079 | 0 6974 0 0 0 0 0 0 0 29 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 118 380 227 310 190 17 40 4 7 11 8 23 23 28 22 21 12 0 0 0 2 2 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 3 3 0 0 1 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
miss_latency_LD: [binsize: 2 max: 287 count: 1185 average: 83.8878 | standard deviation: 84.2176 | 0 602 0 0 0 0 0 0 0 12 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 54 155 70 110 81 8 29 3 2 5 2 9 4 12 7 5 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 3 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
miss_latency_ST: [binsize: 2 max: 297 count: 865 average: 43.8439 | standard deviation: 73.6087 | 0 649 0 0 0 0 0 0 0 12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 35 63 19 18 8 4 0 0 1 1 3 15 1 3 16 4 0 0 0 2 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
miss_latency_IFETCH: [binsize: 2 max: 295 count: 6414 average: 20.8227 | standard deviation: 51.5606 | 0 5723 0 0 0 0 0 0 0 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 58 190 94 181 91 1 7 1 5 5 5 11 4 15 12 0 0 0 0 0 0 2 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
miss_latency_NULL: [binsize: 2 max: 297 count: 8464 average: 32.0048 | standard deviation: 63.6079 | 0 6974 0 0 0 0 0 0 0 29 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 118 380 227 310 190 17 40 4 7 11 8 23 23 28 22 21 12 0 0 0 2 2 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 3 3 0 0 1 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
imcomplete_wCC_Times: 0
miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
imcomplete_dir_Times: 0
miss_latency_LD_NULL: [binsize: 2 max: 287 count: 1185 average: 83.8878 | standard deviation: 84.2176 | 0 602 0 0 0 0 0 0 0 12 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 54 155 70 110 81 8 29 3 2 5 2 9 4 12 7 5 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 3 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
miss_latency_ST_NULL: [binsize: 2 max: 297 count: 865 average: 43.8439 | standard deviation: 73.6087 | 0 649 0 0 0 0 0 0 0 12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 35 63 19 18 8 4 0 0 1 1 3 15 1 3 16 4 0 0 0 2 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
miss_latency_IFETCH_NULL: [binsize: 2 max: 295 count: 6414 average: 20.8227 | standard deviation: 51.5606 | 0 5723 0 0 0 0 0 0 0 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 58 190 94 181 91 1 7 1 5 5 5 11 4 15 12 0 0 0 0 0 0 2 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
All Non-Zero Cycle SW Prefetch Requests
------------------------------------
prefetch_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
prefetch_latency_L2Miss:[binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
Request vs. RubySystem State Profile
--------------------------------
filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
Message Delayed Cycles
----------------------
Total_delay_cycles: [binsize: 1 max: 18 count: 9645 average: 0.0636599 | standard deviation: 0.52686 | 9495 0 1 0 147 0 1 0 0 0 0 0 0 0 0 0 0 0 1 ]
Total_nonPF_delay_cycles: [binsize: 1 max: 2 count: 6920 average: 0.000289017 | standard deviation: 0.0240441 | 6919 0 1 ]
virtual_network_0_delay_cycles: [binsize: 1 max: 18 count: 2725 average: 0.224587 | standard deviation: 0.972266 | 2576 0 0 0 147 0 1 0 0 0 0 0 0 0 0 0 0 0 1 ]
virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 1041 average: 0 | standard deviation: 0 | 1041 ]
virtual_network_3_delay_cycles: [binsize: 1 max: 2 count: 5879 average: 0.000340194 | standard deviation: 0.0260865 | 5878 0 1 ]
virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
virtual_network_6_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
virtual_network_7_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
virtual_network_8_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
virtual_network_9_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
Resource Usage
--------------
page_size: 4096
user_time: 0
system_time: 0
page_reclaims: 13079
page_faults: 9
swaps: 0
block_inputs: 1264
block_outputs: 96
Network Stats
-------------
total_msg_count_Control: 8850 70800
total_msg_count_Request_Control: 3123 24984
total_msg_count_Response_Data: 9681 697032
total_msg_count_Response_Control: 14286 114288
total_msg_count_Writeback_Data: 864 62208
total_msg_count_Writeback_Control: 867 6936
total_msgs: 37671 total_bytes: 976248
switch_0_inlinks: 2
switch_0_outlinks: 2
links_utilized_percent_switch_0: 1.87549
links_utilized_percent_switch_0_link_0: 2.66455 bw: 16000 base_latency: 1
links_utilized_percent_switch_0_link_1: 1.08644 bw: 16000 base_latency: 1
outgoing_messages_switch_0_link_0_Request_Control: 1041 8328 [ 1041 0 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_0_link_0_Response_Data: 1490 107280 [ 0 1490 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_0_link_0_Response_Control: 436 3488 [ 0 436 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_0_link_1_Control: 1490 11920 [ 1490 0 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_0_link_1_Response_Control: 1699 13592 [ 0 900 799 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_0_link_1_Writeback_Data: 288 20736 [ 147 141 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_0_link_1_Writeback_Control: 289 2312 [ 289 0 0 0 0 0 0 0 0 0 ] base_latency: 1
switch_1_inlinks: 2
switch_1_outlinks: 2
links_utilized_percent_switch_1: 3.64029
links_utilized_percent_switch_1_link_0: 3.69819 bw: 16000 base_latency: 1
links_utilized_percent_switch_1_link_1: 3.58239 bw: 16000 base_latency: 1
outgoing_messages_switch_1_link_0_Control: 1490 11920 [ 1490 0 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_1_link_0_Response_Data: 1460 105120 [ 0 1460 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_1_link_0_Response_Control: 3151 25208 [ 0 2352 799 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_1_link_0_Writeback_Data: 288 20736 [ 147 141 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_1_link_0_Writeback_Control: 289 2312 [ 289 0 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_1_link_1_Control: 1460 11680 [ 1460 0 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_1_link_1_Request_Control: 1041 8328 [ 1041 0 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_1_link_1_Response_Data: 1767 127224 [ 0 1767 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_1_link_1_Response_Control: 1611 12888 [ 0 1611 0 0 0 0 0 0 0 0 ] base_latency: 1
switch_2_inlinks: 2
switch_2_outlinks: 2
links_utilized_percent_switch_2: 1.76479
links_utilized_percent_switch_2_link_0: 0.917835 bw: 16000 base_latency: 1
links_utilized_percent_switch_2_link_1: 2.61175 bw: 16000 base_latency: 1
outgoing_messages_switch_2_link_0_Control: 1460 11680 [ 1460 0 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_2_link_0_Response_Data: 277 19944 [ 0 277 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_2_link_0_Response_Control: 1175 9400 [ 0 1175 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_2_link_1_Response_Data: 1460 105120 [ 0 1460 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_2_link_1_Response_Control: 1452 11616 [ 0 1452 0 0 0 0 0 0 0 0 ] base_latency: 1
switch_3_inlinks: 3
switch_3_outlinks: 3
links_utilized_percent_switch_3: 2.42686
links_utilized_percent_switch_3_link_0: 2.66455 bw: 16000 base_latency: 1
links_utilized_percent_switch_3_link_1: 3.69819 bw: 16000 base_latency: 1
links_utilized_percent_switch_3_link_2: 0.917835 bw: 16000 base_latency: 1
outgoing_messages_switch_3_link_0_Request_Control: 1041 8328 [ 1041 0 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_3_link_0_Response_Data: 1490 107280 [ 0 1490 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_3_link_0_Response_Control: 436 3488 [ 0 436 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_3_link_1_Control: 1490 11920 [ 1490 0 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_3_link_1_Response_Data: 1460 105120 [ 0 1460 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_3_link_1_Response_Control: 3151 25208 [ 0 2352 799 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_3_link_1_Writeback_Data: 288 20736 [ 147 141 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_3_link_1_Writeback_Control: 289 2312 [ 289 0 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_3_link_2_Control: 1460 11680 [ 1460 0 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_3_link_2_Response_Data: 277 19944 [ 0 277 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_3_link_2_Response_Control: 1175 9400 [ 0 1175 0 0 0 0 0 0 0 0 ] base_latency: 1
Cache Stats: system.l1_cntrl0.L1IcacheMemory
system.l1_cntrl0.L1IcacheMemory_total_misses: 691
system.l1_cntrl0.L1IcacheMemory_total_demand_misses: 691
system.l1_cntrl0.L1IcacheMemory_total_prefetches: 0
system.l1_cntrl0.L1IcacheMemory_total_sw_prefetches: 0
system.l1_cntrl0.L1IcacheMemory_total_hw_prefetches: 0
system.l1_cntrl0.L1IcacheMemory_request_type_IFETCH: 100%
system.l1_cntrl0.L1IcacheMemory_access_mode_type_Supervisor: 691 100%
Cache Stats: system.l1_cntrl0.L1DcacheMemory
system.l1_cntrl0.L1DcacheMemory_total_misses: 799
system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 799
system.l1_cntrl0.L1DcacheMemory_total_prefetches: 0
system.l1_cntrl0.L1DcacheMemory_total_sw_prefetches: 0
system.l1_cntrl0.L1DcacheMemory_total_hw_prefetches: 0
system.l1_cntrl0.L1DcacheMemory_request_type_LD: 72.9662%
system.l1_cntrl0.L1DcacheMemory_request_type_ST: 27.0338%
system.l1_cntrl0.L1DcacheMemory_access_mode_type_Supervisor: 799 100%
--- L1Cache ---
- Event Counts -
Load [1185 ] 1185
Ifetch [6414 ] 6414
Store [865 ] 865
Inv [1041 ] 1041
L1_Replacement [1354 ] 1354
Fwd_GETX [0 ] 0
Fwd_GETS [0 ] 0
Fwd_GET_INSTR [0 ] 0
Data [0 ] 0
Data_Exclusive [583 ] 583
DataS_fromL1 [0 ] 0
Data_all_Acks [907 ] 907
Ack [0 ] 0
Ack_all [0 ] 0
WB_Ack [436 ] 436
- Transitions -
NP Load [525 ] 525
NP Ifetch [646 ] 646
NP Store [191 ] 191
NP Inv [356 ] 356
NP L1_Replacement [0 ] 0
I Load [58 ] 58
I Ifetch [45 ] 45
I Store [25 ] 25
I Inv [0 ] 0
I L1_Replacement [556 ] 556
S Load [0 ] 0
S Ifetch [5723 ] 5723
S Store [0 ] 0
S Inv [325 ] 325
S L1_Replacement [362 ] 362
E Load [454 ] 454
E Ifetch [0 ] 0
E Store [71 ] 71
E Inv [219 ] 219
E L1_Replacement [291 ] 291
E Fwd_GETX [0 ] 0
E Fwd_GETS [0 ] 0
E Fwd_GET_INSTR [0 ] 0
M Load [148 ] 148
M Ifetch [0 ] 0
M Store [578 ] 578
M Inv [141 ] 141
M L1_Replacement [145 ] 145
M Fwd_GETX [0 ] 0
M Fwd_GETS [0 ] 0
M Fwd_GET_INSTR [0 ] 0
IS Load [0 ] 0
IS Ifetch [0 ] 0
IS Store [0 ] 0
IS Inv [0 ] 0
IS L1_Replacement [0 ] 0
IS Data_Exclusive [583 ] 583
IS DataS_fromL1 [0 ] 0
IS Data_all_Acks [691 ] 691
IM Load [0 ] 0
IM Ifetch [0 ] 0
IM Store [0 ] 0
IM Inv [0 ] 0
IM L1_Replacement [0 ] 0
IM Data [0 ] 0
IM Data_all_Acks [216 ] 216
IM Ack [0 ] 0
SM Load [0 ] 0
SM Ifetch [0 ] 0
SM Store [0 ] 0
SM Inv [0 ] 0
SM L1_Replacement [0 ] 0
SM Ack [0 ] 0
SM Ack_all [0 ] 0
IS_I Load [0 ] 0
IS_I Ifetch [0 ] 0
IS_I Store [0 ] 0
IS_I Inv [0 ] 0
IS_I L1_Replacement [0 ] 0
IS_I Data_Exclusive [0 ] 0
IS_I DataS_fromL1 [0 ] 0
IS_I Data_all_Acks [0 ] 0
M_I Load [0 ] 0
M_I Ifetch [0 ] 0
M_I Store [0 ] 0
M_I Inv [0 ] 0
M_I L1_Replacement [0 ] 0
M_I Fwd_GETX [0 ] 0
M_I Fwd_GETS [0 ] 0
M_I Fwd_GET_INSTR [0 ] 0
M_I WB_Ack [436 ] 436
SINK_WB_ACK Load [0 ] 0
SINK_WB_ACK Ifetch [0 ] 0
SINK_WB_ACK Store [0 ] 0
SINK_WB_ACK Inv [0 ] 0
SINK_WB_ACK L1_Replacement [0 ] 0
SINK_WB_ACK WB_Ack [0 ] 0
Cache Stats: system.l2_cntrl0.L2cacheMemory
system.l2_cntrl0.L2cacheMemory_total_misses: 1460
system.l2_cntrl0.L2cacheMemory_total_demand_misses: 1460
system.l2_cntrl0.L2cacheMemory_total_prefetches: 0
system.l2_cntrl0.L2cacheMemory_total_sw_prefetches: 0
system.l2_cntrl0.L2cacheMemory_total_hw_prefetches: 0
system.l2_cntrl0.L2cacheMemory_request_type_GETS: 39.0411%
system.l2_cntrl0.L2cacheMemory_request_type_GET_INSTR: 46.9863%
system.l2_cntrl0.L2cacheMemory_request_type_GETX: 13.9726%
system.l2_cntrl0.L2cacheMemory_access_mode_type_Supervisor: 1460 100%
--- L2Cache ---
- Event Counts -
L1_GET_INSTR [691 ] 691
L1_GETS [585 ] 585
L1_GETX [216 ] 216
L1_UPGRADE [0 ] 0
L1_PUTX [436 ] 436
L1_PUTX_old [0 ] 0
Fwd_L1_GETX [0 ] 0
Fwd_L1_GETS [0 ] 0
Fwd_L1_GET_INSTR [0 ] 0
L2_Replacement [142 ] 142
L2_Replacement_clean [1310 ] 1310
Mem_Data [1460 ] 1460
Mem_Ack [1452 ] 1452
WB_Data [141 ] 141
WB_Data_clean [0 ] 0
Ack [0 ] 0
Ack_all [900 ] 900
Unblock [0 ] 0
Unblock_Cancel [0 ] 0
Exclusive_Unblock [799 ] 799
MEM_Inv [0 ] 0
- Transitions -
NP L1_GET_INSTR [686 ] 686
NP L1_GETS [570 ] 570
NP L1_GETX [204 ] 204
NP L1_PUTX [0 ] 0
NP L1_PUTX_old [0 ] 0
SS L1_GET_INSTR [5 ] 5
SS L1_GETS [0 ] 0
SS L1_GETX [0 ] 0
SS L1_UPGRADE [0 ] 0
SS L1_PUTX [0 ] 0
SS L1_PUTX_old [0 ] 0
SS L2_Replacement [0 ] 0
SS L2_Replacement_clean [681 ] 681
SS MEM_Inv [0 ] 0
M L1_GET_INSTR [0 ] 0
M L1_GETS [13 ] 13
M L1_GETX [12 ] 12
M L1_PUTX [0 ] 0
M L1_PUTX_old [0 ] 0
M L2_Replacement [134 ] 134
M L2_Replacement_clean [277 ] 277
M MEM_Inv [0 ] 0
MT L1_GET_INSTR [0 ] 0
MT L1_GETS [0 ] 0
MT L1_GETX [0 ] 0
MT L1_PUTX [436 ] 436
MT L1_PUTX_old [0 ] 0
MT L2_Replacement [8 ] 8
MT L2_Replacement_clean [352 ] 352
MT MEM_Inv [0 ] 0
M_I L1_GET_INSTR [0 ] 0
M_I L1_GETS [2 ] 2
M_I L1_GETX [0 ] 0
M_I L1_UPGRADE [0 ] 0
M_I L1_PUTX [0 ] 0
M_I L1_PUTX_old [0 ] 0
M_I Mem_Ack [1452 ] 1452
M_I MEM_Inv [0 ] 0
MT_I L1_GET_INSTR [0 ] 0
MT_I L1_GETS [0 ] 0
MT_I L1_GETX [0 ] 0
MT_I L1_UPGRADE [0 ] 0
MT_I L1_PUTX [0 ] 0
MT_I L1_PUTX_old [0 ] 0
MT_I WB_Data [6 ] 6
MT_I WB_Data_clean [0 ] 0
MT_I Ack_all [2 ] 2
MT_I MEM_Inv [0 ] 0
MCT_I L1_GET_INSTR [0 ] 0
MCT_I L1_GETS [0 ] 0
MCT_I L1_GETX [0 ] 0
MCT_I L1_UPGRADE [0 ] 0
MCT_I L1_PUTX [0 ] 0
MCT_I L1_PUTX_old [0 ] 0
MCT_I WB_Data [135 ] 135
MCT_I WB_Data_clean [0 ] 0
MCT_I Ack_all [217 ] 217
I_I L1_GET_INSTR [0 ] 0
I_I L1_GETS [0 ] 0
I_I L1_GETX [0 ] 0
I_I L1_UPGRADE [0 ] 0
I_I L1_PUTX [0 ] 0
I_I L1_PUTX_old [0 ] 0
I_I Ack [0 ] 0
I_I Ack_all [681 ] 681
S_I L1_GET_INSTR [0 ] 0
S_I L1_GETS [0 ] 0
S_I L1_GETX [0 ] 0
S_I L1_UPGRADE [0 ] 0
S_I L1_PUTX [0 ] 0
S_I L1_PUTX_old [0 ] 0
S_I Ack [0 ] 0
S_I Ack_all [0 ] 0
S_I MEM_Inv [0 ] 0
ISS L1_GET_INSTR [0 ] 0
ISS L1_GETS [0 ] 0
ISS L1_GETX [0 ] 0
ISS L1_PUTX [0 ] 0
ISS L1_PUTX_old [0 ] 0
ISS L2_Replacement [0 ] 0
ISS L2_Replacement_clean [0 ] 0
ISS Mem_Data [570 ] 570
ISS MEM_Inv [0 ] 0
IS L1_GET_INSTR [0 ] 0
IS L1_GETS [0 ] 0
IS L1_GETX [0 ] 0
IS L1_PUTX [0 ] 0
IS L1_PUTX_old [0 ] 0
IS L2_Replacement [0 ] 0
IS L2_Replacement_clean [0 ] 0
IS Mem_Data [686 ] 686
IS MEM_Inv [0 ] 0
IM L1_GET_INSTR [0 ] 0
IM L1_GETS [0 ] 0
IM L1_GETX [0 ] 0
IM L1_PUTX [0 ] 0
IM L1_PUTX_old [0 ] 0
IM L2_Replacement [0 ] 0
IM L2_Replacement_clean [0 ] 0
IM Mem_Data [204 ] 204
IM MEM_Inv [0 ] 0
SS_MB L1_GET_INSTR [0 ] 0
SS_MB L1_GETS [0 ] 0
SS_MB L1_GETX [0 ] 0
SS_MB L1_UPGRADE [0 ] 0
SS_MB L1_PUTX [0 ] 0
SS_MB L1_PUTX_old [0 ] 0
SS_MB L2_Replacement [0 ] 0
SS_MB L2_Replacement_clean [0 ] 0
SS_MB Unblock_Cancel [0 ] 0
SS_MB Exclusive_Unblock [0 ] 0
SS_MB MEM_Inv [0 ] 0
MT_MB L1_GET_INSTR [0 ] 0
MT_MB L1_GETS [0 ] 0
MT_MB L1_GETX [0 ] 0
MT_MB L1_UPGRADE [0 ] 0
MT_MB L1_PUTX [0 ] 0
MT_MB L1_PUTX_old [0 ] 0
MT_MB L2_Replacement [0 ] 0
MT_MB L2_Replacement_clean [0 ] 0
MT_MB Unblock_Cancel [0 ] 0
MT_MB Exclusive_Unblock [799 ] 799
MT_MB MEM_Inv [0 ] 0
M_MB L1_GET_INSTR [0 ] 0
M_MB L1_GETS [0 ] 0
M_MB L1_GETX [0 ] 0
M_MB L1_UPGRADE [0 ] 0
M_MB L1_PUTX [0 ] 0
M_MB L1_PUTX_old [0 ] 0
M_MB L2_Replacement [0 ] 0
M_MB L2_Replacement_clean [0 ] 0
M_MB Exclusive_Unblock [0 ] 0
M_MB MEM_Inv [0 ] 0
MT_IIB L1_GET_INSTR [0 ] 0
MT_IIB L1_GETS [0 ] 0
MT_IIB L1_GETX [0 ] 0
MT_IIB L1_UPGRADE [0 ] 0
MT_IIB L1_PUTX [0 ] 0
MT_IIB L1_PUTX_old [0 ] 0
MT_IIB L2_Replacement [0 ] 0
MT_IIB L2_Replacement_clean [0 ] 0
MT_IIB WB_Data [0 ] 0
MT_IIB WB_Data_clean [0 ] 0
MT_IIB Unblock [0 ] 0
MT_IIB MEM_Inv [0 ] 0
MT_IB L1_GET_INSTR [0 ] 0
MT_IB L1_GETS [0 ] 0
MT_IB L1_GETX [0 ] 0
MT_IB L1_UPGRADE [0 ] 0
MT_IB L1_PUTX [0 ] 0
MT_IB L1_PUTX_old [0 ] 0
MT_IB L2_Replacement [0 ] 0
MT_IB L2_Replacement_clean [0 ] 0
MT_IB WB_Data [0 ] 0
MT_IB WB_Data_clean [0 ] 0
MT_IB Unblock_Cancel [0 ] 0
MT_IB MEM_Inv [0 ] 0
MT_SB L1_GET_INSTR [0 ] 0
MT_SB L1_GETS [0 ] 0
MT_SB L1_GETX [0 ] 0
MT_SB L1_UPGRADE [0 ] 0
MT_SB L1_PUTX [0 ] 0
MT_SB L1_PUTX_old [0 ] 0
MT_SB L2_Replacement [0 ] 0
MT_SB L2_Replacement_clean [0 ] 0
MT_SB Unblock [0 ] 0
MT_SB MEM_Inv [0 ] 0
Memory controller: system.dir_cntrl0.memBuffer:
memory_total_requests: 1737
memory_reads: 1460
memory_writes: 277
memory_refreshes: 582
memory_total_request_delays: 821
memory_delays_per_request: 0.472654
memory_delays_in_input_queue: 84
memory_delays_behind_head_of_bank_queue: 0
memory_delays_stalled_at_head_of_bank_queue: 737
memory_stalls_for_bank_busy: 197
memory_stalls_for_random_busy: 0
memory_stalls_for_anti_starvation: 0
memory_stalls_for_arbitration: 40
memory_stalls_for_bus: 242
memory_stalls_for_tfaw: 0
memory_stalls_for_read_write_turnaround: 258
memory_stalls_for_read_read_turnaround: 0
accesses_per_bank: 92 21 45 54 57 174 48 18 19 22 35 37 56 59 44 36 41 24 22 28 32 48 122 36 32 25 35 96 114 185 19 61
--- Directory ---
- Event Counts -
Fetch [1460 ] 1460
Data [277 ] 277
Memory_Data [1460 ] 1460
Memory_Ack [277 ] 277
DMA_READ [0 ] 0
DMA_WRITE [0 ] 0
CleanReplacement [1175 ] 1175
- Transitions -
I Fetch [1460 ] 1460
I DMA_READ [0 ] 0
I DMA_WRITE [0 ] 0
ID Fetch [0 ] 0
ID Data [0 ] 0
ID Memory_Data [0 ] 0
ID DMA_READ [0 ] 0
ID DMA_WRITE [0 ] 0
ID_W Fetch [0 ] 0
ID_W Data [0 ] 0
ID_W Memory_Ack [0 ] 0
ID_W DMA_READ [0 ] 0
ID_W DMA_WRITE [0 ] 0
M Data [277 ] 277
M DMA_READ [0 ] 0
M DMA_WRITE [0 ] 0
M CleanReplacement [1175 ] 1175
IM Fetch [0 ] 0
IM Data [0 ] 0
IM Memory_Data [1460 ] 1460
IM DMA_READ [0 ] 0
IM DMA_WRITE [0 ] 0
MI Fetch [0 ] 0
MI Data [0 ] 0
MI Memory_Ack [277 ] 277
MI DMA_READ [0 ] 0
MI DMA_WRITE [0 ] 0
M_DRD Data [0 ] 0
M_DRD DMA_READ [0 ] 0
M_DRD DMA_WRITE [0 ] 0
M_DRDI Fetch [0 ] 0
M_DRDI Data [0 ] 0
M_DRDI Memory_Ack [0 ] 0
M_DRDI DMA_READ [0 ] 0
M_DRDI DMA_WRITE [0 ] 0
M_DWR Data [0 ] 0
M_DWR DMA_READ [0 ] 0
M_DWR DMA_WRITE [0 ] 0
M_DWRI Fetch [0 ] 0
M_DWRI Data [0 ] 0
M_DWRI Memory_Ack [0 ] 0
M_DWRI DMA_READ [0 ] 0
M_DWRI DMA_WRITE [0 ] 0

2
simulators/gem5/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simerr Executable file
View File

@ -0,0 +1,2 @@
warn: Sockets disabled, not accepting gdb connections
hack: be nice to actually delete the event here

12
simulators/gem5/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout Executable file
View File

@ -0,0 +1,12 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 4 2012 11:53:20
gem5 started Jun 4 2012 13:42:35
gem5 executing on zizzer
command line: build/ALPHA_MESI_CMP_directory/gem5.opt -d build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MESI_CMP_directory
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello world!
Exiting @ tick 279353 because target called exit()

92
simulators/gem5/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt Normal file
View File

@ -0,0 +1,92 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000279 # Number of seconds simulated
sim_ticks 279353 # Number of ticks simulated
final_tick 279353 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
host_inst_rate 12119 # Simulator instruction rate (inst/s)
host_op_rate 12118 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 528605 # Simulator tick rate (ticks/s)
host_mem_usage 226340 # Number of bytes of host memory used
host_seconds 0.53 # Real time elapsed on the host
sim_insts 6404 # Number of instructions simulated
sim_ops 6404 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 25656 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 8804 # Number of bytes read from this memory
system.physmem.bytes_read::total 34460 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 25656 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 25656 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 6696 # Number of bytes written to this memory
system.physmem.bytes_written::total 6696 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 6414 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 1185 # Number of read requests responded to by this memory
system.physmem.num_reads::total 7599 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 865 # Number of write requests responded to by this memory
system.physmem.num_writes::total 865 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 91840789 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 31515681 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 123356470 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 91840789 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 91840789 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 23969673 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 23969673 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 91840789 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 55485354 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 147326143 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 1185 # DTB read hits
system.cpu.dtb.read_misses 7 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 1192 # DTB read accesses
system.cpu.dtb.write_hits 865 # DTB write hits
system.cpu.dtb.write_misses 3 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 868 # DTB write accesses
system.cpu.dtb.data_hits 2050 # DTB hits
system.cpu.dtb.data_misses 10 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 2060 # DTB accesses
system.cpu.itb.fetch_hits 6415 # ITB hits
system.cpu.itb.fetch_misses 17 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 6432 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 17 # Number of system calls
system.cpu.numCycles 279353 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 6404 # Number of instructions committed
system.cpu.committedOps 6404 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 6331 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses
system.cpu.num_func_calls 251 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 750 # number of instructions that are conditional controls
system.cpu.num_int_insts 6331 # number of integer instructions
system.cpu.num_fp_insts 10 # number of float instructions
system.cpu.num_int_register_reads 8304 # number of times the integer registers were read
system.cpu.num_int_register_writes 4581 # number of times the integer registers were written
system.cpu.num_fp_register_reads 8 # number of times the floating registers were read
system.cpu.num_fp_register_writes 2 # number of times the floating registers were written
system.cpu.num_mem_refs 2060 # number of memory refs
system.cpu.num_load_insts 1192 # Number of load instructions
system.cpu.num_store_insts 868 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 279353 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
---------- End Simulation Statistics ----------

339
simulators/gem5/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini Normal file
View File

@ -0,0 +1,339 @@
[root]
type=Root
children=system
full_system=false
time_sync_enable=false
time_sync_period=100000000
time_sync_spin_threshold=100000
[system]
type=System
children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby sys_port_proxy
boot_osflags=a
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=timing
memories=system.physmem
num_work_ids=16
readfile=
symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.sys_port_proxy.slave[0]
[system.cpu]
type=TimingSimpleCPU
children=dtb interrupts itb tracer workload
checker=Null
clock=1
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
phase=0
profile=0
progress_interval=0
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
dcache_port=system.l1_cntrl0.sequencer.slave[1]
icache_port=system.l1_cntrl0.sequencer.slave[0]
[system.cpu.dtb]
type=AlphaTLB
size=64
[system.cpu.interrupts]
type=AlphaInterrupts
[system.cpu.itb]
type=AlphaTLB
size=48
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=hello
cwd=
egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
gid=100
input=cin
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=0
system=system
uid=100
[system.dir_cntrl0]
type=Directory_Controller
children=directory memBuffer
buffer_size=0
cntrl_id=2
directory=system.dir_cntrl0.directory
directory_latency=6
memBuffer=system.dir_cntrl0.memBuffer
number_of_TBEs=256
recycle_latency=10
ruby_system=system.ruby
transitions_per_cycle=32
version=0
[system.dir_cntrl0.directory]
type=RubyDirectoryMemory
map_levels=4
numa_high_bit=6
size=134217728
use_map=false
version=0
[system.dir_cntrl0.memBuffer]
type=RubyMemoryControl
bank_bit_0=8
bank_busy_time=11
bank_queue_size=12
banks_per_rank=8
basic_bus_busy_time=2
dimm_bit_0=12
dimms_per_channel=2
mem_bus_cycle_multiplier=10
mem_ctl_latency=12
mem_fixed_delay=0
mem_random_arbitrate=0
rank_bit_0=11
rank_rank_delay=1
ranks_per_dimm=2
read_write_delay=2
refresh_period=1560
tFaw=0
version=0
[system.l1_cntrl0]
type=L1Cache_Controller
children=L1DcacheMemory L1IcacheMemory sequencer
L1DcacheMemory=system.l1_cntrl0.L1DcacheMemory
L1IcacheMemory=system.l1_cntrl0.L1IcacheMemory
buffer_size=0
cntrl_id=0
l2_select_num_bits=0
number_of_TBEs=256
recycle_latency=10
request_latency=2
ruby_system=system.ruby
send_evictions=false
sequencer=system.l1_cntrl0.sequencer
transitions_per_cycle=32
version=0
[system.l1_cntrl0.L1DcacheMemory]
type=RubyCache
assoc=2
is_icache=false
latency=3
replacement_policy=PSEUDO_LRU
size=256
start_index_bit=6
[system.l1_cntrl0.L1IcacheMemory]
type=RubyCache
assoc=2
is_icache=false
latency=3
replacement_policy=PSEUDO_LRU
size=256
start_index_bit=6
[system.l1_cntrl0.sequencer]
type=RubySequencer
access_phys_mem=true
dcache=system.l1_cntrl0.L1DcacheMemory
deadlock_threshold=500000
icache=system.l1_cntrl0.L1IcacheMemory
max_outstanding_requests=16
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
system=system
using_network_tester=false
using_ruby_tester=false
version=0
slave=system.cpu.icache_port system.cpu.dcache_port
[system.l2_cntrl0]
type=L2Cache_Controller
children=L2cacheMemory
L2cacheMemory=system.l2_cntrl0.L2cacheMemory
buffer_size=0
cntrl_id=1
number_of_TBEs=256
recycle_latency=10
request_latency=2
response_latency=2
ruby_system=system.ruby
transitions_per_cycle=32
version=0
[system.l2_cntrl0.L2cacheMemory]
type=RubyCache
assoc=2
is_icache=false
latency=15
replacement_policy=PSEUDO_LRU
size=512
start_index_bit=6
[system.physmem]
type=SimpleMemory
conf_table_reported=false
file=
in_addr_map=true
latency=30
latency_var=0
null=false
range=0:134217727
zero=false
[system.ruby]
type=RubySystem
children=network profiler
block_size_bytes=64
clock=1
mem_size=134217728
no_mem_vec=false
random_seed=1234
randomization=false
stats_filename=ruby.stats
[system.ruby.network]
type=SimpleNetwork
children=topology
adaptive_routing=false
buffer_size=0
control_msg_size=8
endpoint_bandwidth=1000
number_of_virtual_networks=10
ruby_system=system.ruby
topology=system.ruby.network.topology
[system.ruby.network.topology]
type=Topology
children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2 routers0 routers1 routers2 routers3
description=Crossbar
ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2
int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2
print_config=false
routers=system.ruby.network.topology.routers0 system.ruby.network.topology.routers1 system.ruby.network.topology.routers2 system.ruby.network.topology.routers3
[system.ruby.network.topology.ext_links0]
type=SimpleExtLink
bandwidth_factor=16
ext_node=system.l1_cntrl0
int_node=system.ruby.network.topology.routers0
latency=1
link_id=0
weight=1
[system.ruby.network.topology.ext_links1]
type=SimpleExtLink
bandwidth_factor=16
ext_node=system.l2_cntrl0
int_node=system.ruby.network.topology.routers1
latency=1
link_id=1
weight=1
[system.ruby.network.topology.ext_links2]
type=SimpleExtLink
bandwidth_factor=16
ext_node=system.dir_cntrl0
int_node=system.ruby.network.topology.routers2
latency=1
link_id=2
weight=1
[system.ruby.network.topology.int_links0]
type=SimpleIntLink
bandwidth_factor=16
latency=1
link_id=3
node_a=system.ruby.network.topology.routers0
node_b=system.ruby.network.topology.routers3
weight=1
[system.ruby.network.topology.int_links1]
type=SimpleIntLink
bandwidth_factor=16
latency=1
link_id=4
node_a=system.ruby.network.topology.routers1
node_b=system.ruby.network.topology.routers3
weight=1
[system.ruby.network.topology.int_links2]
type=SimpleIntLink
bandwidth_factor=16
latency=1
link_id=5
node_a=system.ruby.network.topology.routers2
node_b=system.ruby.network.topology.routers3
weight=1
[system.ruby.network.topology.routers0]
type=BasicRouter
router_id=0
[system.ruby.network.topology.routers1]
type=BasicRouter
router_id=1
[system.ruby.network.topology.routers2]
type=BasicRouter
router_id=2
[system.ruby.network.topology.routers3]
type=BasicRouter
router_id=3
[system.ruby.profiler]
type=RubyProfiler
all_instructions=false
hot_lines=false
num_of_sequencers=1
ruby_system=system.ruby
[system.sys_port_proxy]
type=RubyPortProxy
access_phys_mem=true
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
system=system
using_network_tester=false
using_ruby_tester=false
version=0
slave=system.system_port

1470
simulators/gem5/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/ruby.stats Normal file
View File

File diff suppressed because it is too large Load Diff

2
simulators/gem5/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simerr Executable file
View File

@ -0,0 +1,2 @@
warn: Sockets disabled, not accepting gdb connections
hack: be nice to actually delete the event here

12
simulators/gem5/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout Executable file
View File

@ -0,0 +1,12 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 4 2012 11:54:55
gem5 started Jun 4 2012 14:41:04
gem5 executing on zizzer
command line: build/ALPHA_MOESI_CMP_directory/gem5.opt -d build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello world!
Exiting @ tick 223694 because target called exit()

92
simulators/gem5/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt Normal file
View File

@ -0,0 +1,92 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000224 # Number of seconds simulated
sim_ticks 223694 # Number of ticks simulated
final_tick 223694 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
host_inst_rate 30014 # Simulator instruction rate (inst/s)
host_op_rate 30012 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1048235 # Simulator tick rate (ticks/s)
host_mem_usage 226460 # Number of bytes of host memory used
host_seconds 0.21 # Real time elapsed on the host
sim_insts 6404 # Number of instructions simulated
sim_ops 6404 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 25656 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 8804 # Number of bytes read from this memory
system.physmem.bytes_read::total 34460 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 25656 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 25656 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 6696 # Number of bytes written to this memory
system.physmem.bytes_written::total 6696 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 6414 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 1185 # Number of read requests responded to by this memory
system.physmem.num_reads::total 7599 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 865 # Number of write requests responded to by this memory
system.physmem.num_writes::total 865 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 114692392 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 39357336 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 154049729 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 114692392 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 114692392 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 29933749 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 29933749 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 114692392 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 69291085 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 183983477 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 1185 # DTB read hits
system.cpu.dtb.read_misses 7 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 1192 # DTB read accesses
system.cpu.dtb.write_hits 865 # DTB write hits
system.cpu.dtb.write_misses 3 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 868 # DTB write accesses
system.cpu.dtb.data_hits 2050 # DTB hits
system.cpu.dtb.data_misses 10 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 2060 # DTB accesses
system.cpu.itb.fetch_hits 6415 # ITB hits
system.cpu.itb.fetch_misses 17 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 6432 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 17 # Number of system calls
system.cpu.numCycles 223694 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 6404 # Number of instructions committed
system.cpu.committedOps 6404 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 6331 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses
system.cpu.num_func_calls 251 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 750 # number of instructions that are conditional controls
system.cpu.num_int_insts 6331 # number of integer instructions
system.cpu.num_fp_insts 10 # number of float instructions
system.cpu.num_int_register_reads 8304 # number of times the integer registers were read
system.cpu.num_int_register_writes 4581 # number of times the integer registers were written
system.cpu.num_fp_register_reads 8 # number of times the floating registers were read
system.cpu.num_fp_register_writes 2 # number of times the floating registers were written
system.cpu.num_mem_refs 2060 # number of memory refs
system.cpu.num_load_insts 1192 # Number of load instructions
system.cpu.num_store_insts 868 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 223694 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
---------- End Simulation Statistics ----------

350
simulators/gem5/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini Normal file
View File

@ -0,0 +1,350 @@
[root]
type=Root
children=system
full_system=false
time_sync_enable=false
time_sync_period=100000000
time_sync_spin_threshold=100000
[system]
type=System
children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby sys_port_proxy
boot_osflags=a
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=timing
memories=system.physmem
num_work_ids=16
readfile=
symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.sys_port_proxy.slave[0]
[system.cpu]
type=TimingSimpleCPU
children=dtb interrupts itb tracer workload
checker=Null
clock=1
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
phase=0
profile=0
progress_interval=0
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
dcache_port=system.l1_cntrl0.sequencer.slave[1]
icache_port=system.l1_cntrl0.sequencer.slave[0]
[system.cpu.dtb]
type=AlphaTLB
size=64
[system.cpu.interrupts]
type=AlphaInterrupts
[system.cpu.itb]
type=AlphaTLB
size=48
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=hello
cwd=
egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
gid=100
input=cin
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=0
system=system
uid=100
[system.dir_cntrl0]
type=Directory_Controller
children=directory memBuffer
buffer_size=0
cntrl_id=2
directory=system.dir_cntrl0.directory
directory_latency=5
distributed_persistent=true
fixed_timeout_latency=100
l2_select_num_bits=0
memBuffer=system.dir_cntrl0.memBuffer
number_of_TBEs=256
recycle_latency=10
ruby_system=system.ruby
transitions_per_cycle=32
version=0
[system.dir_cntrl0.directory]
type=RubyDirectoryMemory
map_levels=4
numa_high_bit=6
size=134217728
use_map=false
version=0
[system.dir_cntrl0.memBuffer]
type=RubyMemoryControl
bank_bit_0=8
bank_busy_time=11
bank_queue_size=12
banks_per_rank=8
basic_bus_busy_time=2
dimm_bit_0=12
dimms_per_channel=2
mem_bus_cycle_multiplier=10
mem_ctl_latency=12
mem_fixed_delay=0
mem_random_arbitrate=0
rank_bit_0=11
rank_rank_delay=1
ranks_per_dimm=2
read_write_delay=2
refresh_period=1560
tFaw=0
version=0
[system.l1_cntrl0]
type=L1Cache_Controller
children=L1DcacheMemory L1IcacheMemory sequencer
L1DcacheMemory=system.l1_cntrl0.L1DcacheMemory
L1IcacheMemory=system.l1_cntrl0.L1IcacheMemory
N_tokens=2
buffer_size=0
cntrl_id=0
dynamic_timeout_enabled=true
fixed_timeout_latency=300
l1_request_latency=2
l1_response_latency=2
l2_select_num_bits=0
no_mig_atomic=true
number_of_TBEs=256
recycle_latency=10
retry_threshold=1
ruby_system=system.ruby
send_evictions=false
sequencer=system.l1_cntrl0.sequencer
transitions_per_cycle=32
version=0
[system.l1_cntrl0.L1DcacheMemory]
type=RubyCache
assoc=2
is_icache=false
latency=2
replacement_policy=PSEUDO_LRU
size=256
start_index_bit=6
[system.l1_cntrl0.L1IcacheMemory]
type=RubyCache
assoc=2
is_icache=false
latency=2
replacement_policy=PSEUDO_LRU
size=256
start_index_bit=6
[system.l1_cntrl0.sequencer]
type=RubySequencer
access_phys_mem=true
dcache=system.l1_cntrl0.L1DcacheMemory
deadlock_threshold=500000
icache=system.l1_cntrl0.L1IcacheMemory
max_outstanding_requests=16
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
system=system
using_network_tester=false
using_ruby_tester=false
version=0
slave=system.cpu.icache_port system.cpu.dcache_port
[system.l2_cntrl0]
type=L2Cache_Controller
children=L2cacheMemory
L2cacheMemory=system.l2_cntrl0.L2cacheMemory
N_tokens=2
buffer_size=0
cntrl_id=1
filtering_enabled=true
l2_request_latency=5
l2_response_latency=5
number_of_TBEs=256
recycle_latency=10
ruby_system=system.ruby
transitions_per_cycle=32
version=0
[system.l2_cntrl0.L2cacheMemory]
type=RubyCache
assoc=2
is_icache=false
latency=10
replacement_policy=PSEUDO_LRU
size=512
start_index_bit=6
[system.physmem]
type=SimpleMemory
conf_table_reported=false
file=
in_addr_map=true
latency=30
latency_var=0
null=false
range=0:134217727
zero=false
[system.ruby]
type=RubySystem
children=network profiler
block_size_bytes=64
clock=1
mem_size=134217728
no_mem_vec=false
random_seed=1234
randomization=false
stats_filename=ruby.stats
[system.ruby.network]
type=SimpleNetwork
children=topology
adaptive_routing=false
buffer_size=0
control_msg_size=8
endpoint_bandwidth=1000
number_of_virtual_networks=10
ruby_system=system.ruby
topology=system.ruby.network.topology
[system.ruby.network.topology]
type=Topology
children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2 routers0 routers1 routers2 routers3
description=Crossbar
ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2
int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2
print_config=false
routers=system.ruby.network.topology.routers0 system.ruby.network.topology.routers1 system.ruby.network.topology.routers2 system.ruby.network.topology.routers3
[system.ruby.network.topology.ext_links0]
type=SimpleExtLink
bandwidth_factor=16
ext_node=system.l1_cntrl0
int_node=system.ruby.network.topology.routers0
latency=1
link_id=0
weight=1
[system.ruby.network.topology.ext_links1]
type=SimpleExtLink
bandwidth_factor=16
ext_node=system.l2_cntrl0
int_node=system.ruby.network.topology.routers1
latency=1
link_id=1
weight=1
[system.ruby.network.topology.ext_links2]
type=SimpleExtLink
bandwidth_factor=16
ext_node=system.dir_cntrl0
int_node=system.ruby.network.topology.routers2
latency=1
link_id=2
weight=1
[system.ruby.network.topology.int_links0]
type=SimpleIntLink
bandwidth_factor=16
latency=1
link_id=3
node_a=system.ruby.network.topology.routers0
node_b=system.ruby.network.topology.routers3
weight=1
[system.ruby.network.topology.int_links1]
type=SimpleIntLink
bandwidth_factor=16
latency=1
link_id=4
node_a=system.ruby.network.topology.routers1
node_b=system.ruby.network.topology.routers3
weight=1
[system.ruby.network.topology.int_links2]
type=SimpleIntLink
bandwidth_factor=16
latency=1
link_id=5
node_a=system.ruby.network.topology.routers2
node_b=system.ruby.network.topology.routers3
weight=1
[system.ruby.network.topology.routers0]
type=BasicRouter
router_id=0
[system.ruby.network.topology.routers1]
type=BasicRouter
router_id=1
[system.ruby.network.topology.routers2]
type=BasicRouter
router_id=2
[system.ruby.network.topology.routers3]
type=BasicRouter
router_id=3
[system.ruby.profiler]
type=RubyProfiler
all_instructions=false
hot_lines=false
num_of_sequencers=1
ruby_system=system.ruby
[system.sys_port_proxy]
type=RubyPortProxy
access_phys_mem=true
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
system=system
using_network_tester=false
using_ruby_tester=false
version=0
slave=system.system_port

1043
simulators/gem5/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/ruby.stats Normal file
View File

File diff suppressed because it is too large Load Diff

2
simulators/gem5/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simerr Executable file
View File

@ -0,0 +1,2 @@
warn: Sockets disabled, not accepting gdb connections
hack: be nice to actually delete the event here

12
simulators/gem5/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout Executable file
View File

@ -0,0 +1,12 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 4 2012 11:56:32
gem5 started Jun 4 2012 14:42:12
gem5 executing on zizzer
command line: build/ALPHA_MOESI_CMP_token/gem5.opt -d build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello world!
Exiting @ tick 231701 because target called exit()

92
simulators/gem5/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt Normal file
View File

@ -0,0 +1,92 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000232 # Number of seconds simulated
sim_ticks 231701 # Number of ticks simulated
final_tick 231701 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
host_inst_rate 50012 # Simulator instruction rate (inst/s)
host_op_rate 50005 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1808952 # Simulator tick rate (ticks/s)
host_mem_usage 224692 # Number of bytes of host memory used
host_seconds 0.13 # Real time elapsed on the host
sim_insts 6404 # Number of instructions simulated
sim_ops 6404 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 25656 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 8804 # Number of bytes read from this memory
system.physmem.bytes_read::total 34460 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 25656 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 25656 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 6696 # Number of bytes written to this memory
system.physmem.bytes_written::total 6696 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 6414 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 1185 # Number of read requests responded to by this memory
system.physmem.num_reads::total 7599 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 865 # Number of write requests responded to by this memory
system.physmem.num_writes::total 865 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 110728914 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 37997246 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 148726160 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 110728914 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 110728914 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 28899314 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 28899314 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 110728914 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 66896561 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 177625474 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 1185 # DTB read hits
system.cpu.dtb.read_misses 7 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 1192 # DTB read accesses
system.cpu.dtb.write_hits 865 # DTB write hits
system.cpu.dtb.write_misses 3 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 868 # DTB write accesses
system.cpu.dtb.data_hits 2050 # DTB hits
system.cpu.dtb.data_misses 10 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 2060 # DTB accesses
system.cpu.itb.fetch_hits 6415 # ITB hits
system.cpu.itb.fetch_misses 17 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 6432 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 17 # Number of system calls
system.cpu.numCycles 231701 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 6404 # Number of instructions committed
system.cpu.committedOps 6404 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 6331 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses
system.cpu.num_func_calls 251 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 750 # number of instructions that are conditional controls
system.cpu.num_int_insts 6331 # number of integer instructions
system.cpu.num_fp_insts 10 # number of float instructions
system.cpu.num_int_register_reads 8304 # number of times the integer registers were read
system.cpu.num_int_register_writes 4581 # number of times the integer registers were written
system.cpu.num_fp_register_reads 8 # number of times the floating registers were read
system.cpu.num_fp_register_writes 2 # number of times the floating registers were written
system.cpu.num_mem_refs 2060 # number of memory refs
system.cpu.num_load_insts 1192 # Number of load instructions
system.cpu.num_store_insts 868 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 231701 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
---------- End Simulation Statistics ----------

318
simulators/gem5/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini Normal file
View File

@ -0,0 +1,318 @@
[root]
type=Root
children=system
full_system=false
time_sync_enable=false
time_sync_period=100000000
time_sync_spin_threshold=100000
[system]
type=System
children=cpu dir_cntrl0 l1_cntrl0 physmem ruby sys_port_proxy
boot_osflags=a
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=timing
memories=system.physmem
num_work_ids=16
readfile=
symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.sys_port_proxy.slave[0]
[system.cpu]
type=TimingSimpleCPU
children=dtb interrupts itb tracer workload
checker=Null
clock=1
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
phase=0
profile=0
progress_interval=0
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
dcache_port=system.l1_cntrl0.sequencer.slave[1]
icache_port=system.l1_cntrl0.sequencer.slave[0]
[system.cpu.dtb]
type=AlphaTLB
size=64
[system.cpu.interrupts]
type=AlphaInterrupts
[system.cpu.itb]
type=AlphaTLB
size=48
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=hello
cwd=
egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
gid=100
input=cin
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=0
system=system
uid=100
[system.dir_cntrl0]
type=Directory_Controller
children=directory memBuffer probeFilter
buffer_size=0
cntrl_id=1
directory=system.dir_cntrl0.directory
full_bit_dir_enabled=false
memBuffer=system.dir_cntrl0.memBuffer
memory_controller_latency=2
number_of_TBEs=256
probeFilter=system.dir_cntrl0.probeFilter
probe_filter_enabled=false
recycle_latency=10
ruby_system=system.ruby
transitions_per_cycle=32
version=0
[system.dir_cntrl0.directory]
type=RubyDirectoryMemory
map_levels=4
numa_high_bit=6
size=134217728
use_map=false
version=0
[system.dir_cntrl0.memBuffer]
type=RubyMemoryControl
bank_bit_0=8
bank_busy_time=11
bank_queue_size=12
banks_per_rank=8
basic_bus_busy_time=2
dimm_bit_0=12
dimms_per_channel=2
mem_bus_cycle_multiplier=10
mem_ctl_latency=12
mem_fixed_delay=0
mem_random_arbitrate=0
rank_bit_0=11
rank_rank_delay=1
ranks_per_dimm=2
read_write_delay=2
refresh_period=1560
tFaw=0
version=0
[system.dir_cntrl0.probeFilter]
type=RubyCache
assoc=4
is_icache=false
latency=1
replacement_policy=PSEUDO_LRU
size=1024
start_index_bit=6
[system.l1_cntrl0]
type=L1Cache_Controller
children=L1DcacheMemory L1IcacheMemory L2cacheMemory sequencer
L1DcacheMemory=system.l1_cntrl0.L1DcacheMemory
L1IcacheMemory=system.l1_cntrl0.L1IcacheMemory
L2cacheMemory=system.l1_cntrl0.L2cacheMemory
buffer_size=0
cache_response_latency=10
cntrl_id=0
issue_latency=2
l2_cache_hit_latency=10
no_mig_atomic=true
number_of_TBEs=256
recycle_latency=10
ruby_system=system.ruby
send_evictions=false
sequencer=system.l1_cntrl0.sequencer
transitions_per_cycle=32
version=0
[system.l1_cntrl0.L1DcacheMemory]
type=RubyCache
assoc=2
is_icache=false
latency=2
replacement_policy=PSEUDO_LRU
size=256
start_index_bit=6
[system.l1_cntrl0.L1IcacheMemory]
type=RubyCache
assoc=2
is_icache=true
latency=2
replacement_policy=PSEUDO_LRU
size=256
start_index_bit=6
[system.l1_cntrl0.L2cacheMemory]
type=RubyCache
assoc=2
is_icache=false
latency=10
replacement_policy=PSEUDO_LRU
size=512
start_index_bit=6
[system.l1_cntrl0.sequencer]
type=RubySequencer
access_phys_mem=true
dcache=system.l1_cntrl0.L1DcacheMemory
deadlock_threshold=500000
icache=system.l1_cntrl0.L1IcacheMemory
max_outstanding_requests=16
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
system=system
using_network_tester=false
using_ruby_tester=false
version=0
slave=system.cpu.icache_port system.cpu.dcache_port
[system.physmem]
type=SimpleMemory
conf_table_reported=false
file=
in_addr_map=true
latency=30
latency_var=0
null=false
range=0:134217727
zero=false
[system.ruby]
type=RubySystem
children=network profiler
block_size_bytes=64
clock=1
mem_size=134217728
no_mem_vec=false
random_seed=1234
randomization=false
stats_filename=ruby.stats
[system.ruby.network]
type=SimpleNetwork
children=topology
adaptive_routing=false
buffer_size=0
control_msg_size=8
endpoint_bandwidth=1000
number_of_virtual_networks=10
ruby_system=system.ruby
topology=system.ruby.network.topology
[system.ruby.network.topology]
type=Topology
children=ext_links0 ext_links1 int_links0 int_links1 routers0 routers1 routers2
description=Crossbar
ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1
int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1
print_config=false
routers=system.ruby.network.topology.routers0 system.ruby.network.topology.routers1 system.ruby.network.topology.routers2
[system.ruby.network.topology.ext_links0]
type=SimpleExtLink
bandwidth_factor=16
ext_node=system.l1_cntrl0
int_node=system.ruby.network.topology.routers0
latency=1
link_id=0
weight=1
[system.ruby.network.topology.ext_links1]
type=SimpleExtLink
bandwidth_factor=16
ext_node=system.dir_cntrl0
int_node=system.ruby.network.topology.routers1
latency=1
link_id=1
weight=1
[system.ruby.network.topology.int_links0]
type=SimpleIntLink
bandwidth_factor=16
latency=1
link_id=2
node_a=system.ruby.network.topology.routers0
node_b=system.ruby.network.topology.routers2
weight=1
[system.ruby.network.topology.int_links1]
type=SimpleIntLink
bandwidth_factor=16
latency=1
link_id=3
node_a=system.ruby.network.topology.routers1
node_b=system.ruby.network.topology.routers2
weight=1
[system.ruby.network.topology.routers0]
type=BasicRouter
router_id=0
[system.ruby.network.topology.routers1]
type=BasicRouter
router_id=1
[system.ruby.network.topology.routers2]
type=BasicRouter
router_id=2
[system.ruby.profiler]
type=RubyProfiler
all_instructions=false
hot_lines=false
num_of_sequencers=1
ruby_system=system.ruby
[system.sys_port_proxy]
type=RubyPortProxy
access_phys_mem=true
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
system=system
using_network_tester=false
using_ruby_tester=false
version=0
slave=system.system_port

973
simulators/gem5/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/ruby.stats Normal file
View File

@ -0,0 +1,973 @@
================ Begin RubySystem Configuration Print ================
RubySystem config:
random_seed: 1234
randomization: 0
cycle_period: 1
block_size_bytes: 64
block_size_bits: 6
memory_size_bytes: 134217728
memory_size_bits: 27
Network Configuration
---------------------
network: SIMPLE_NETWORK
topology:
virtual_net_0: active, ordered
virtual_net_1: active, ordered
virtual_net_2: active, unordered
virtual_net_3: active, unordered
virtual_net_4: active, unordered
virtual_net_5: active, unordered
virtual_net_6: inactive
virtual_net_7: inactive
virtual_net_8: inactive
virtual_net_9: inactive
Profiler Configuration
----------------------
periodic_stats_period: 1000000
================ End RubySystem Configuration Print ================
Real time: Jun/04/2012 13:41:27
Profiler Stats
--------------
Elapsed_time_in_seconds: 0
Elapsed_time_in_minutes: 0
Elapsed_time_in_hours: 0
Elapsed_time_in_days: 0
Virtual_time_in_seconds: 0.34
Virtual_time_in_minutes: 0.00566667
Virtual_time_in_hours: 9.44444e-05
Virtual_time_in_days: 3.93519e-06
Ruby_current_time: 208400
Ruby_start_time: 0
Ruby_cycles: 208400
mbytes_resident: 47.2969
mbytes_total: 218.926
resident_ratio: 0.216041
ruby_cycles_executed: [ 208401 ]
Busy Controller Counts:
L1Cache-0:0
Directory-0:0
Busy Bank Count:0
sequencer_requests_outstanding: [binsize: 1 max: 1 count: 8465 average: 1 | standard deviation: 0 | 0 8465 ]
All Non-Zero Cycle Demand Cache Accesses
----------------------------------------
miss_latency: [binsize: 2 max: 340 count: 8464 average: 23.6219 | standard deviation: 54.4451 | 0 7102 0 0 0 0 203 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 81 188 166 188 149 272 6 5 3 5 20 2 4 9 1 15 3 1 0 0 1 1 0 3 2 1 0 1 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 2 3 18 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 ]
miss_latency_LD: [binsize: 2 max: 327 count: 1185 average: 57.3924 | standard deviation: 73.6654 | 0 660 0 0 0 0 105 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 37 78 73 59 44 91 2 3 1 3 5 2 2 3 0 6 1 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
miss_latency_ST: [binsize: 2 max: 340 count: 865 average: 34.9399 | standard deviation: 73.2706 | 0 674 0 0 0 0 33 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 8 37 38 7 31 0 0 0 0 1 0 2 1 0 2 0 1 0 0 0 1 0 2 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 3 17 0 0 0 0 0 0 0 0 0 1 ]
miss_latency_IFETCH: [binsize: 2 max: 206 count: 6414 average: 15.8564 | standard deviation: 43.57 | 0 5768 0 0 0 0 65 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 43 102 56 91 98 150 4 2 2 2 14 0 0 5 1 7 2 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
miss_latency_L1Cache: [binsize: 1 max: 2 count: 7102 average: 2 | standard deviation: 0 | 0 0 7102 ]
miss_latency_L2Cache: [binsize: 1 max: 13 count: 203 average: 13 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 203 ]
miss_latency_Directory: [binsize: 2 max: 340 count: 1159 average: 157.975 | standard deviation: 26.6537 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 81 188 166 188 149 272 6 5 3 5 20 2 4 9 1 15 3 1 0 0 1 1 0 3 2 1 0 1 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 2 3 18 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 ]
miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
imcomplete_wCC_Times: 0
miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ]
miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ]
miss_latency_dir_forward_to_first_response: [binsize: 1 max: 158 count: 1 average: 158 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ]
imcomplete_dir_Times: 1158
miss_latency_LD_L1Cache: [binsize: 1 max: 2 count: 660 average: 2 | standard deviation: 0 | 0 0 660 ]
miss_latency_LD_L2Cache: [binsize: 1 max: 13 count: 105 average: 13 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 105 ]
miss_latency_LD_Directory: [binsize: 2 max: 327 count: 420 average: 155.536 | standard deviation: 18.768 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 37 78 73 59 44 91 2 3 1 3 5 2 2 3 0 6 1 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
miss_latency_ST_L1Cache: [binsize: 1 max: 2 count: 674 average: 2 | standard deviation: 0 | 0 0 674 ]
miss_latency_ST_L2Cache: [binsize: 1 max: 13 count: 33 average: 13 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 33 ]
miss_latency_ST_Directory: [binsize: 2 max: 340 count: 158 average: 180.038 | standard deviation: 59.9794 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 8 37 38 7 31 0 0 0 0 1 0 2 1 0 2 0 1 0 0 0 1 0 2 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 3 17 0 0 0 0 0 0 0 0 0 1 ]
miss_latency_IFETCH_L1Cache: [binsize: 1 max: 2 count: 5768 average: 2 | standard deviation: 0 | 0 0 5768 ]
miss_latency_IFETCH_L2Cache: [binsize: 1 max: 13 count: 65 average: 13 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 65 ]
miss_latency_IFETCH_Directory: [binsize: 2 max: 206 count: 581 average: 153.738 | standard deviation: 5.93543 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 43 102 56 91 98 150 4 2 2 2 14 0 0 5 1 7 2 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
All Non-Zero Cycle SW Prefetch Requests
------------------------------------
prefetch_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
prefetch_latency_L2Miss:[binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
Request vs. RubySystem State Profile
--------------------------------
filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
Message Delayed Cycles
----------------------
Total_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
virtual_network_0_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
virtual_network_6_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
virtual_network_7_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
virtual_network_8_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
virtual_network_9_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
Resource Usage
--------------
page_size: 4096
user_time: 0
system_time: 0
page_reclaims: 12505
page_faults: 5
swaps: 0
block_inputs: 1000
block_outputs: 96
Network Stats
-------------
total_msg_count_Request_Control: 3477 27816
total_msg_count_Response_Data: 3477 250344
total_msg_count_Writeback_Data: 660 47520
total_msg_count_Writeback_Control: 9627 77016
total_msg_count_Unblock_Control: 3477 27816
total_msgs: 20718 total_bytes: 430512
switch_0_inlinks: 2
switch_0_outlinks: 2
links_utilized_percent_switch_0: 2.15187
links_utilized_percent_switch_0_link_0: 2.77687 bw: 16000 base_latency: 1
links_utilized_percent_switch_0_link_1: 1.52687 bw: 16000 base_latency: 1
outgoing_messages_switch_0_link_0_Response_Data: 1159 83448 [ 0 0 0 0 1159 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_0_link_0_Writeback_Control: 1143 9144 [ 0 0 0 1143 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_0_link_1_Request_Control: 1159 9272 [ 0 0 1159 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_0_link_1_Writeback_Data: 220 15840 [ 0 0 0 0 0 220 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_0_link_1_Writeback_Control: 2066 16528 [ 0 0 1143 0 0 923 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_0_link_1_Unblock_Control: 1159 9272 [ 0 0 0 0 0 1159 0 0 0 0 ] base_latency: 1
switch_1_inlinks: 2
switch_1_outlinks: 2
links_utilized_percent_switch_1: 2.15187
links_utilized_percent_switch_1_link_0: 1.52687 bw: 16000 base_latency: 1
links_utilized_percent_switch_1_link_1: 2.77687 bw: 16000 base_latency: 1
outgoing_messages_switch_1_link_0_Request_Control: 1159 9272 [ 0 0 1159 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_1_link_0_Writeback_Data: 220 15840 [ 0 0 0 0 0 220 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_1_link_0_Writeback_Control: 2066 16528 [ 0 0 1143 0 0 923 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_1_link_0_Unblock_Control: 1159 9272 [ 0 0 0 0 0 1159 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_1_link_1_Response_Data: 1159 83448 [ 0 0 0 0 1159 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_1_link_1_Writeback_Control: 1143 9144 [ 0 0 0 1143 0 0 0 0 0 0 ] base_latency: 1
switch_2_inlinks: 2
switch_2_outlinks: 2
links_utilized_percent_switch_2: 2.15187
links_utilized_percent_switch_2_link_0: 2.77687 bw: 16000 base_latency: 1
links_utilized_percent_switch_2_link_1: 1.52687 bw: 16000 base_latency: 1
outgoing_messages_switch_2_link_0_Response_Data: 1159 83448 [ 0 0 0 0 1159 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_2_link_0_Writeback_Control: 1143 9144 [ 0 0 0 1143 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_2_link_1_Request_Control: 1159 9272 [ 0 0 1159 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_2_link_1_Writeback_Data: 220 15840 [ 0 0 0 0 0 220 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_2_link_1_Writeback_Control: 2066 16528 [ 0 0 1143 0 0 923 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_2_link_1_Unblock_Control: 1159 9272 [ 0 0 0 0 0 1159 0 0 0 0 ] base_latency: 1
Cache Stats: system.l1_cntrl0.L1IcacheMemory
system.l1_cntrl0.L1IcacheMemory_total_misses: 646
system.l1_cntrl0.L1IcacheMemory_total_demand_misses: 646
system.l1_cntrl0.L1IcacheMemory_total_prefetches: 0
system.l1_cntrl0.L1IcacheMemory_total_sw_prefetches: 0
system.l1_cntrl0.L1IcacheMemory_total_hw_prefetches: 0
system.l1_cntrl0.L1IcacheMemory_request_type_IFETCH: 100%
system.l1_cntrl0.L1IcacheMemory_access_mode_type_Supervisor: 646 100%
Cache Stats: system.l1_cntrl0.L1DcacheMemory
system.l1_cntrl0.L1DcacheMemory_total_misses: 716
system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 716
system.l1_cntrl0.L1DcacheMemory_total_prefetches: 0
system.l1_cntrl0.L1DcacheMemory_total_sw_prefetches: 0
system.l1_cntrl0.L1DcacheMemory_total_hw_prefetches: 0
system.l1_cntrl0.L1DcacheMemory_request_type_LD: 73.324%
system.l1_cntrl0.L1DcacheMemory_request_type_ST: 26.676%
system.l1_cntrl0.L1DcacheMemory_access_mode_type_Supervisor: 716 100%
Cache Stats: system.l1_cntrl0.L2cacheMemory
system.l1_cntrl0.L2cacheMemory_total_misses: 1362
system.l1_cntrl0.L2cacheMemory_total_demand_misses: 1362
system.l1_cntrl0.L2cacheMemory_total_prefetches: 0
system.l1_cntrl0.L2cacheMemory_total_sw_prefetches: 0
system.l1_cntrl0.L2cacheMemory_total_hw_prefetches: 0
system.l1_cntrl0.L2cacheMemory_request_type_LD: 38.5463%
system.l1_cntrl0.L2cacheMemory_request_type_ST: 14.0235%
system.l1_cntrl0.L2cacheMemory_request_type_IFETCH: 47.4302%
system.l1_cntrl0.L2cacheMemory_access_mode_type_Supervisor: 1362 100%
--- L1Cache ---
- Event Counts -
Load [1193 ] 1193
Ifetch [6425 ] 6425
Store [892 ] 892
L2_Replacement [1143 ] 1143
L1_to_L2 [1354 ] 1354
Trigger_L2_to_L1D [138 ] 138
Trigger_L2_to_L1I [65 ] 65
Complete_L2_to_L1 [203 ] 203
Other_GETX [0 ] 0
Other_GETS [0 ] 0
Merged_GETS [0 ] 0
Other_GETS_No_Mig [0 ] 0
NC_DMA_GETS [0 ] 0
Invalidate [0 ] 0
Ack [0 ] 0
Shared_Ack [0 ] 0
Data [0 ] 0
Shared_Data [0 ] 0
Exclusive_Data [1159 ] 1159
Writeback_Ack [1143 ] 1143
Writeback_Nack [0 ] 0
All_acks [0 ] 0
All_acks_no_sharers [1159 ] 1159
Flush_line [0 ] 0
Block_Ack [0 ] 0
- Transitions -
I Load [420 ] 420
I Ifetch [581 ] 581
I Store [158 ] 158
I L2_Replacement [0 ] 0
I L1_to_L2 [0 ] 0
I Trigger_L2_to_L1D [0 ] 0
I Trigger_L2_to_L1I [0 ] 0
I Other_GETX [0 ] 0
I Other_GETS [0 ] 0
I Other_GETS_No_Mig [0 ] 0
I NC_DMA_GETS [0 ] 0
I Invalidate [0 ] 0
I Flush_line [0 ] 0
S Load [0 ] 0
S Ifetch [0 ] 0
S Store [0 ] 0
S L2_Replacement [0 ] 0
S L1_to_L2 [0 ] 0
S Trigger_L2_to_L1D [0 ] 0
S Trigger_L2_to_L1I [0 ] 0
S Other_GETX [0 ] 0
S Other_GETS [0 ] 0
S Other_GETS_No_Mig [0 ] 0
S NC_DMA_GETS [0 ] 0
S Invalidate [0 ] 0
S Flush_line [0 ] 0
O Load [0 ] 0
O Ifetch [0 ] 0
O Store [0 ] 0
O L2_Replacement [0 ] 0
O L1_to_L2 [0 ] 0
O Trigger_L2_to_L1D [0 ] 0
O Trigger_L2_to_L1I [0 ] 0
O Other_GETX [0 ] 0
O Other_GETS [0 ] 0
O Merged_GETS [0 ] 0
O Other_GETS_No_Mig [0 ] 0
O NC_DMA_GETS [0 ] 0
O Invalidate [0 ] 0
O Flush_line [0 ] 0
M Load [306 ] 306
M Ifetch [5768 ] 5768
M Store [60 ] 60
M L2_Replacement [923 ] 923
M L1_to_L2 [1061 ] 1061
M Trigger_L2_to_L1D [68 ] 68
M Trigger_L2_to_L1I [65 ] 65
M Other_GETX [0 ] 0
M Other_GETS [0 ] 0
M Merged_GETS [0 ] 0
M Other_GETS_No_Mig [0 ] 0
M NC_DMA_GETS [0 ] 0
M Invalidate [0 ] 0
M Flush_line [0 ] 0
MM Load [354 ] 354
MM Ifetch [0 ] 0
MM Store [614 ] 614
MM L2_Replacement [220 ] 220
MM L1_to_L2 [293 ] 293
MM Trigger_L2_to_L1D [70 ] 70
MM Trigger_L2_to_L1I [0 ] 0
MM Other_GETX [0 ] 0
MM Other_GETS [0 ] 0
MM Merged_GETS [0 ] 0
MM Other_GETS_No_Mig [0 ] 0
MM NC_DMA_GETS [0 ] 0
MM Invalidate [0 ] 0
MM Flush_line [0 ] 0
IR Load [0 ] 0
IR Ifetch [0 ] 0
IR Store [0 ] 0
IR L1_to_L2 [0 ] 0
IR Flush_line [0 ] 0
SR Load [0 ] 0
SR Ifetch [0 ] 0
SR Store [0 ] 0
SR L1_to_L2 [0 ] 0
SR Flush_line [0 ] 0
OR Load [0 ] 0
OR Ifetch [0 ] 0
OR Store [0 ] 0
OR L1_to_L2 [0 ] 0
OR Flush_line [0 ] 0
MR Load [62 ] 62
MR Ifetch [65 ] 65
MR Store [6 ] 6
MR L1_to_L2 [0 ] 0
MR Flush_line [0 ] 0
MMR Load [43 ] 43
MMR Ifetch [0 ] 0
MMR Store [27 ] 27
MMR L1_to_L2 [0 ] 0
MMR Flush_line [0 ] 0
IM Load [0 ] 0
IM Ifetch [0 ] 0
IM Store [0 ] 0
IM L2_Replacement [0 ] 0
IM L1_to_L2 [0 ] 0
IM Other_GETX [0 ] 0
IM Other_GETS [0 ] 0
IM Other_GETS_No_Mig [0 ] 0
IM NC_DMA_GETS [0 ] 0
IM Invalidate [0 ] 0
IM Ack [0 ] 0
IM Data [0 ] 0
IM Exclusive_Data [158 ] 158
IM Flush_line [0 ] 0
SM Load [0 ] 0
SM Ifetch [0 ] 0
SM Store [0 ] 0
SM L2_Replacement [0 ] 0
SM L1_to_L2 [0 ] 0
SM Other_GETX [0 ] 0
SM Other_GETS [0 ] 0
SM Other_GETS_No_Mig [0 ] 0
SM NC_DMA_GETS [0 ] 0
SM Invalidate [0 ] 0
SM Ack [0 ] 0
SM Data [0 ] 0
SM Exclusive_Data [0 ] 0
SM Flush_line [0 ] 0
OM Load [0 ] 0
OM Ifetch [0 ] 0
OM Store [0 ] 0
OM L2_Replacement [0 ] 0
OM L1_to_L2 [0 ] 0
OM Other_GETX [0 ] 0
OM Other_GETS [0 ] 0
OM Merged_GETS [0 ] 0
OM Other_GETS_No_Mig [0 ] 0
OM NC_DMA_GETS [0 ] 0
OM Invalidate [0 ] 0
OM Ack [0 ] 0
OM All_acks [0 ] 0
OM All_acks_no_sharers [0 ] 0
OM Flush_line [0 ] 0
ISM Load [0 ] 0
ISM Ifetch [0 ] 0
ISM Store [0 ] 0
ISM L2_Replacement [0 ] 0
ISM L1_to_L2 [0 ] 0
ISM Ack [0 ] 0
ISM All_acks_no_sharers [0 ] 0
ISM Flush_line [0 ] 0
M_W Load [0 ] 0
M_W Ifetch [0 ] 0
M_W Store [0 ] 0
M_W L2_Replacement [0 ] 0
M_W L1_to_L2 [0 ] 0
M_W Ack [0 ] 0
M_W All_acks_no_sharers [1001 ] 1001
M_W Flush_line [0 ] 0
MM_W Load [0 ] 0
MM_W Ifetch [0 ] 0
MM_W Store [0 ] 0
MM_W L2_Replacement [0 ] 0
MM_W L1_to_L2 [0 ] 0
MM_W Ack [0 ] 0
MM_W All_acks_no_sharers [158 ] 158
MM_W Flush_line [0 ] 0
IS Load [0 ] 0
IS Ifetch [0 ] 0
IS Store [0 ] 0
IS L2_Replacement [0 ] 0
IS L1_to_L2 [0 ] 0
IS Other_GETX [0 ] 0
IS Other_GETS [0 ] 0
IS Other_GETS_No_Mig [0 ] 0
IS NC_DMA_GETS [0 ] 0
IS Invalidate [0 ] 0
IS Ack [0 ] 0
IS Shared_Ack [0 ] 0
IS Data [0 ] 0
IS Shared_Data [0 ] 0
IS Exclusive_Data [1001 ] 1001
IS Flush_line [0 ] 0
SS Load [0 ] 0
SS Ifetch [0 ] 0
SS Store [0 ] 0
SS L2_Replacement [0 ] 0
SS L1_to_L2 [0 ] 0
SS Ack [0 ] 0
SS Shared_Ack [0 ] 0
SS All_acks [0 ] 0
SS All_acks_no_sharers [0 ] 0
SS Flush_line [0 ] 0
OI Load [0 ] 0
OI Ifetch [0 ] 0
OI Store [0 ] 0
OI L2_Replacement [0 ] 0
OI L1_to_L2 [0 ] 0
OI Other_GETX [0 ] 0
OI Other_GETS [0 ] 0
OI Merged_GETS [0 ] 0
OI Other_GETS_No_Mig [0 ] 0
OI NC_DMA_GETS [0 ] 0
OI Invalidate [0 ] 0
OI Writeback_Ack [0 ] 0
OI Flush_line [0 ] 0
MI Load [8 ] 8
MI Ifetch [11 ] 11
MI Store [27 ] 27
MI L2_Replacement [0 ] 0
MI L1_to_L2 [0 ] 0
MI Other_GETX [0 ] 0
MI Other_GETS [0 ] 0
MI Merged_GETS [0 ] 0
MI Other_GETS_No_Mig [0 ] 0
MI NC_DMA_GETS [0 ] 0
MI Invalidate [0 ] 0
MI Writeback_Ack [1143 ] 1143
MI Flush_line [0 ] 0
II Load [0 ] 0
II Ifetch [0 ] 0
II Store [0 ] 0
II L2_Replacement [0 ] 0
II L1_to_L2 [0 ] 0
II Other_GETX [0 ] 0
II Other_GETS [0 ] 0
II Other_GETS_No_Mig [0 ] 0
II NC_DMA_GETS [0 ] 0
II Invalidate [0 ] 0
II Writeback_Ack [0 ] 0
II Writeback_Nack [0 ] 0
II Flush_line [0 ] 0
IT Load [0 ] 0
IT Ifetch [0 ] 0
IT Store [0 ] 0
IT L2_Replacement [0 ] 0
IT L1_to_L2 [0 ] 0
IT Complete_L2_to_L1 [0 ] 0
ST Load [0 ] 0
ST Ifetch [0 ] 0
ST Store [0 ] 0
ST L2_Replacement [0 ] 0
ST L1_to_L2 [0 ] 0
ST Complete_L2_to_L1 [0 ] 0
OT Load [0 ] 0
OT Ifetch [0 ] 0
OT Store [0 ] 0
OT L2_Replacement [0 ] 0
OT L1_to_L2 [0 ] 0
OT Complete_L2_to_L1 [0 ] 0
MT Load [0 ] 0
MT Ifetch [0 ] 0
MT Store [0 ] 0
MT L2_Replacement [0 ] 0
MT L1_to_L2 [0 ] 0
MT Complete_L2_to_L1 [133 ] 133
MMT Load [0 ] 0
MMT Ifetch [0 ] 0
MMT Store [0 ] 0
MMT L2_Replacement [0 ] 0
MMT L1_to_L2 [0 ] 0
MMT Complete_L2_to_L1 [70 ] 70
MI_F Load [0 ] 0
MI_F Ifetch [0 ] 0
MI_F Store [0 ] 0
MI_F L1_to_L2 [0 ] 0
MI_F Writeback_Ack [0 ] 0
MI_F Flush_line [0 ] 0
MM_F Load [0 ] 0
MM_F Ifetch [0 ] 0
MM_F Store [0 ] 0
MM_F L1_to_L2 [0 ] 0
MM_F Other_GETX [0 ] 0
MM_F Other_GETS [0 ] 0
MM_F Merged_GETS [0 ] 0
MM_F Other_GETS_No_Mig [0 ] 0
MM_F NC_DMA_GETS [0 ] 0
MM_F Invalidate [0 ] 0
MM_F Ack [0 ] 0
MM_F All_acks [0 ] 0
MM_F All_acks_no_sharers [0 ] 0
MM_F Flush_line [0 ] 0
MM_F Block_Ack [0 ] 0
IM_F Load [0 ] 0
IM_F Ifetch [0 ] 0
IM_F Store [0 ] 0
IM_F L2_Replacement [0 ] 0
IM_F L1_to_L2 [0 ] 0
IM_F Other_GETX [0 ] 0
IM_F Other_GETS [0 ] 0
IM_F Other_GETS_No_Mig [0 ] 0
IM_F NC_DMA_GETS [0 ] 0
IM_F Invalidate [0 ] 0
IM_F Ack [0 ] 0
IM_F Data [0 ] 0
IM_F Exclusive_Data [0 ] 0
IM_F Flush_line [0 ] 0
ISM_F Load [0 ] 0
ISM_F Ifetch [0 ] 0
ISM_F Store [0 ] 0
ISM_F L2_Replacement [0 ] 0
ISM_F L1_to_L2 [0 ] 0
ISM_F Ack [0 ] 0
ISM_F All_acks_no_sharers [0 ] 0
ISM_F Flush_line [0 ] 0
SM_F Load [0 ] 0
SM_F Ifetch [0 ] 0
SM_F Store [0 ] 0
SM_F L2_Replacement [0 ] 0
SM_F L1_to_L2 [0 ] 0
SM_F Other_GETX [0 ] 0
SM_F Other_GETS [0 ] 0
SM_F Other_GETS_No_Mig [0 ] 0
SM_F NC_DMA_GETS [0 ] 0
SM_F Invalidate [0 ] 0
SM_F Ack [0 ] 0
SM_F Data [0 ] 0
SM_F Exclusive_Data [0 ] 0
SM_F Flush_line [0 ] 0
OM_F Load [0 ] 0
OM_F Ifetch [0 ] 0
OM_F Store [0 ] 0
OM_F L2_Replacement [0 ] 0
OM_F L1_to_L2 [0 ] 0
OM_F Other_GETX [0 ] 0
OM_F Other_GETS [0 ] 0
OM_F Merged_GETS [0 ] 0
OM_F Other_GETS_No_Mig [0 ] 0
OM_F NC_DMA_GETS [0 ] 0
OM_F Invalidate [0 ] 0
OM_F Ack [0 ] 0
OM_F All_acks [0 ] 0
OM_F All_acks_no_sharers [0 ] 0
OM_F Flush_line [0 ] 0
MM_WF Load [0 ] 0
MM_WF Ifetch [0 ] 0
MM_WF Store [0 ] 0
MM_WF L2_Replacement [0 ] 0
MM_WF L1_to_L2 [0 ] 0
MM_WF Ack [0 ] 0
MM_WF All_acks_no_sharers [0 ] 0
MM_WF Flush_line [0 ] 0
Cache Stats: system.dir_cntrl0.probeFilter
system.dir_cntrl0.probeFilter_total_misses: 0
system.dir_cntrl0.probeFilter_total_demand_misses: 0
system.dir_cntrl0.probeFilter_total_prefetches: 0
system.dir_cntrl0.probeFilter_total_sw_prefetches: 0
system.dir_cntrl0.probeFilter_total_hw_prefetches: 0
Memory controller: system.dir_cntrl0.memBuffer:
memory_total_requests: 1379
memory_reads: 1159
memory_writes: 220
memory_refreshes: 435
memory_total_request_delays: 495
memory_delays_per_request: 0.358956
memory_delays_in_input_queue: 3
memory_delays_behind_head_of_bank_queue: 0
memory_delays_stalled_at_head_of_bank_queue: 492
memory_stalls_for_bank_busy: 124
memory_stalls_for_random_busy: 0
memory_stalls_for_anti_starvation: 0
memory_stalls_for_arbitration: 23
memory_stalls_for_bus: 78
memory_stalls_for_tfaw: 0
memory_stalls_for_read_write_turnaround: 267
memory_stalls_for_read_read_turnaround: 0
accesses_per_bank: 75 17 45 40 54 101 33 16 20 22 32 34 53 50 39 31 39 22 21 27 28 38 81 22 31 23 32 72 89 126 14 52
--- Directory ---
- Event Counts -
GETX [189 ] 189
GETS [1027 ] 1027
PUT [1143 ] 1143
Unblock [0 ] 0
UnblockS [0 ] 0
UnblockM [1159 ] 1159
Writeback_Clean [0 ] 0
Writeback_Dirty [0 ] 0
Writeback_Exclusive_Clean [923 ] 923
Writeback_Exclusive_Dirty [220 ] 220
Pf_Replacement [0 ] 0
DMA_READ [0 ] 0
DMA_WRITE [0 ] 0
Memory_Data [1159 ] 1159
Memory_Ack [220 ] 220
Ack [0 ] 0
Shared_Ack [0 ] 0
Shared_Data [0 ] 0
Data [0 ] 0
Exclusive_Data [0 ] 0
All_acks_and_shared_data [0 ] 0
All_acks_and_owner_data [0 ] 0
All_acks_and_data_no_sharers [0 ] 0
All_Unblocks [0 ] 0
GETF [0 ] 0
PUTF [0 ] 0
- Transitions -
NX GETX [0 ] 0
NX GETS [0 ] 0
NX PUT [0 ] 0
NX Pf_Replacement [0 ] 0
NX DMA_READ [0 ] 0
NX DMA_WRITE [0 ] 0
NX GETF [0 ] 0
NO GETX [0 ] 0
NO GETS [0 ] 0
NO PUT [1143 ] 1143
NO Pf_Replacement [0 ] 0
NO DMA_READ [0 ] 0
NO DMA_WRITE [0 ] 0
NO GETF [0 ] 0
S GETX [0 ] 0
S GETS [0 ] 0
S PUT [0 ] 0
S Pf_Replacement [0 ] 0
S DMA_READ [0 ] 0
S DMA_WRITE [0 ] 0
S GETF [0 ] 0
O GETX [0 ] 0
O GETS [0 ] 0
O PUT [0 ] 0
O Pf_Replacement [0 ] 0
O DMA_READ [0 ] 0
O DMA_WRITE [0 ] 0
O GETF [0 ] 0
E GETX [158 ] 158
E GETS [1001 ] 1001
E PUT [0 ] 0
E DMA_READ [0 ] 0
E DMA_WRITE [0 ] 0
E GETF [0 ] 0
O_R GETX [0 ] 0
O_R GETS [0 ] 0
O_R PUT [0 ] 0
O_R Pf_Replacement [0 ] 0
O_R DMA_READ [0 ] 0
O_R DMA_WRITE [0 ] 0
O_R Ack [0 ] 0
O_R All_acks_and_data_no_sharers [0 ] 0
O_R GETF [0 ] 0
S_R GETX [0 ] 0
S_R GETS [0 ] 0
S_R PUT [0 ] 0
S_R Pf_Replacement [0 ] 0
S_R DMA_READ [0 ] 0
S_R DMA_WRITE [0 ] 0
S_R Ack [0 ] 0
S_R Data [0 ] 0
S_R All_acks_and_data_no_sharers [0 ] 0
S_R GETF [0 ] 0
NO_R GETX [0 ] 0
NO_R GETS [0 ] 0
NO_R PUT [0 ] 0
NO_R Pf_Replacement [0 ] 0
NO_R DMA_READ [0 ] 0
NO_R DMA_WRITE [0 ] 0
NO_R Ack [0 ] 0
NO_R Data [0 ] 0
NO_R Exclusive_Data [0 ] 0
NO_R All_acks_and_data_no_sharers [0 ] 0
NO_R GETF [0 ] 0
NO_B GETX [0 ] 0
NO_B GETS [0 ] 0
NO_B PUT [0 ] 0
NO_B UnblockS [0 ] 0
NO_B UnblockM [1159 ] 1159
NO_B Pf_Replacement [0 ] 0
NO_B DMA_READ [0 ] 0
NO_B DMA_WRITE [0 ] 0
NO_B GETF [0 ] 0
NO_B_X GETX [0 ] 0
NO_B_X GETS [0 ] 0
NO_B_X PUT [0 ] 0
NO_B_X UnblockS [0 ] 0
NO_B_X UnblockM [0 ] 0
NO_B_X Pf_Replacement [0 ] 0
NO_B_X DMA_READ [0 ] 0
NO_B_X DMA_WRITE [0 ] 0
NO_B_X GETF [0 ] 0
NO_B_S GETX [0 ] 0
NO_B_S GETS [0 ] 0
NO_B_S PUT [0 ] 0
NO_B_S UnblockS [0 ] 0
NO_B_S UnblockM [0 ] 0
NO_B_S Pf_Replacement [0 ] 0
NO_B_S DMA_READ [0 ] 0
NO_B_S DMA_WRITE [0 ] 0
NO_B_S GETF [0 ] 0
NO_B_S_W GETX [0 ] 0
NO_B_S_W GETS [0 ] 0
NO_B_S_W PUT [0 ] 0
NO_B_S_W UnblockS [0 ] 0
NO_B_S_W Pf_Replacement [0 ] 0
NO_B_S_W DMA_READ [0 ] 0
NO_B_S_W DMA_WRITE [0 ] 0
NO_B_S_W All_Unblocks [0 ] 0
NO_B_S_W GETF [0 ] 0
O_B GETX [0 ] 0
O_B GETS [0 ] 0
O_B PUT [0 ] 0
O_B UnblockS [0 ] 0
O_B UnblockM [0 ] 0
O_B Pf_Replacement [0 ] 0
O_B DMA_READ [0 ] 0
O_B DMA_WRITE [0 ] 0
O_B GETF [0 ] 0
NO_B_W GETX [0 ] 0
NO_B_W GETS [0 ] 0
NO_B_W PUT [0 ] 0
NO_B_W UnblockS [0 ] 0
NO_B_W UnblockM [0 ] 0
NO_B_W Pf_Replacement [0 ] 0
NO_B_W DMA_READ [0 ] 0
NO_B_W DMA_WRITE [0 ] 0
NO_B_W Memory_Data [1159 ] 1159
NO_B_W GETF [0 ] 0
O_B_W GETX [0 ] 0
O_B_W GETS [0 ] 0
O_B_W PUT [0 ] 0
O_B_W UnblockS [0 ] 0
O_B_W Pf_Replacement [0 ] 0
O_B_W DMA_READ [0 ] 0
O_B_W DMA_WRITE [0 ] 0
O_B_W Memory_Data [0 ] 0
O_B_W GETF [0 ] 0
NO_W GETX [0 ] 0
NO_W GETS [0 ] 0
NO_W PUT [0 ] 0
NO_W Pf_Replacement [0 ] 0
NO_W DMA_READ [0 ] 0
NO_W DMA_WRITE [0 ] 0
NO_W Memory_Data [0 ] 0
NO_W GETF [0 ] 0
O_W GETX [0 ] 0
O_W GETS [0 ] 0
O_W PUT [0 ] 0
O_W Pf_Replacement [0 ] 0
O_W DMA_READ [0 ] 0
O_W DMA_WRITE [0 ] 0
O_W Memory_Data [0 ] 0
O_W GETF [0 ] 0
NO_DW_B_W GETX [0 ] 0
NO_DW_B_W GETS [0 ] 0
NO_DW_B_W PUT [0 ] 0
NO_DW_B_W Pf_Replacement [0 ] 0
NO_DW_B_W DMA_READ [0 ] 0
NO_DW_B_W DMA_WRITE [0 ] 0
NO_DW_B_W Ack [0 ] 0
NO_DW_B_W Data [0 ] 0
NO_DW_B_W Exclusive_Data [0 ] 0
NO_DW_B_W All_acks_and_data_no_sharers [0 ] 0
NO_DW_B_W GETF [0 ] 0
NO_DR_B_W GETX [0 ] 0
NO_DR_B_W GETS [0 ] 0
NO_DR_B_W PUT [0 ] 0
NO_DR_B_W Pf_Replacement [0 ] 0
NO_DR_B_W DMA_READ [0 ] 0
NO_DR_B_W DMA_WRITE [0 ] 0
NO_DR_B_W Memory_Data [0 ] 0
NO_DR_B_W Ack [0 ] 0
NO_DR_B_W Shared_Ack [0 ] 0
NO_DR_B_W Shared_Data [0 ] 0
NO_DR_B_W Data [0 ] 0
NO_DR_B_W Exclusive_Data [0 ] 0
NO_DR_B_W GETF [0 ] 0
NO_DR_B_D GETX [0 ] 0
NO_DR_B_D GETS [0 ] 0
NO_DR_B_D PUT [0 ] 0
NO_DR_B_D Pf_Replacement [0 ] 0
NO_DR_B_D DMA_READ [0 ] 0
NO_DR_B_D DMA_WRITE [0 ] 0
NO_DR_B_D Ack [0 ] 0
NO_DR_B_D Shared_Ack [0 ] 0
NO_DR_B_D Shared_Data [0 ] 0
NO_DR_B_D Data [0 ] 0
NO_DR_B_D Exclusive_Data [0 ] 0
NO_DR_B_D All_acks_and_shared_data [0 ] 0
NO_DR_B_D All_acks_and_owner_data [0 ] 0
NO_DR_B_D All_acks_and_data_no_sharers [0 ] 0
NO_DR_B_D GETF [0 ] 0
NO_DR_B GETX [0 ] 0
NO_DR_B GETS [0 ] 0
NO_DR_B PUT [0 ] 0
NO_DR_B Pf_Replacement [0 ] 0
NO_DR_B DMA_READ [0 ] 0
NO_DR_B DMA_WRITE [0 ] 0
NO_DR_B Ack [0 ] 0
NO_DR_B Shared_Ack [0 ] 0
NO_DR_B Shared_Data [0 ] 0
NO_DR_B Data [0 ] 0
NO_DR_B Exclusive_Data [0 ] 0
NO_DR_B All_acks_and_shared_data [0 ] 0
NO_DR_B All_acks_and_owner_data [0 ] 0
NO_DR_B All_acks_and_data_no_sharers [0 ] 0
NO_DR_B GETF [0 ] 0
NO_DW_W GETX [0 ] 0
NO_DW_W GETS [0 ] 0
NO_DW_W PUT [0 ] 0
NO_DW_W Pf_Replacement [0 ] 0
NO_DW_W DMA_READ [0 ] 0
NO_DW_W DMA_WRITE [0 ] 0
NO_DW_W Memory_Ack [0 ] 0
NO_DW_W GETF [0 ] 0
O_DR_B_W GETX [0 ] 0
O_DR_B_W GETS [0 ] 0
O_DR_B_W PUT [0 ] 0
O_DR_B_W Pf_Replacement [0 ] 0
O_DR_B_W DMA_READ [0 ] 0
O_DR_B_W DMA_WRITE [0 ] 0
O_DR_B_W Memory_Data [0 ] 0
O_DR_B_W Ack [0 ] 0
O_DR_B_W Shared_Ack [0 ] 0
O_DR_B_W GETF [0 ] 0
O_DR_B GETX [0 ] 0
O_DR_B GETS [0 ] 0
O_DR_B PUT [0 ] 0
O_DR_B Pf_Replacement [0 ] 0
O_DR_B DMA_READ [0 ] 0
O_DR_B DMA_WRITE [0 ] 0
O_DR_B Ack [0 ] 0
O_DR_B Shared_Ack [0 ] 0
O_DR_B All_acks_and_owner_data [0 ] 0
O_DR_B All_acks_and_data_no_sharers [0 ] 0
O_DR_B GETF [0 ] 0
WB GETX [27 ] 27
WB GETS [19 ] 19
WB PUT [0 ] 0
WB Unblock [0 ] 0
WB Writeback_Clean [0 ] 0
WB Writeback_Dirty [0 ] 0
WB Writeback_Exclusive_Clean [923 ] 923
WB Writeback_Exclusive_Dirty [220 ] 220
WB Pf_Replacement [0 ] 0
WB DMA_READ [0 ] 0
WB DMA_WRITE [0 ] 0
WB GETF [0 ] 0
WB_O_W GETX [0 ] 0
WB_O_W GETS [0 ] 0
WB_O_W PUT [0 ] 0
WB_O_W Pf_Replacement [0 ] 0
WB_O_W DMA_READ [0 ] 0
WB_O_W DMA_WRITE [0 ] 0
WB_O_W Memory_Ack [0 ] 0
WB_O_W GETF [0 ] 0
WB_E_W GETX [4 ] 4
WB_E_W GETS [7 ] 7
WB_E_W PUT [0 ] 0
WB_E_W Pf_Replacement [0 ] 0
WB_E_W DMA_READ [0 ] 0
WB_E_W DMA_WRITE [0 ] 0
WB_E_W Memory_Ack [220 ] 220
WB_E_W GETF [0 ] 0
NO_F GETX [0 ] 0
NO_F GETS [0 ] 0
NO_F PUT [0 ] 0
NO_F UnblockM [0 ] 0
NO_F Pf_Replacement [0 ] 0
NO_F GETF [0 ] 0
NO_F PUTF [0 ] 0
NO_F_W GETX [0 ] 0
NO_F_W GETS [0 ] 0
NO_F_W PUT [0 ] 0
NO_F_W Pf_Replacement [0 ] 0
NO_F_W DMA_READ [0 ] 0
NO_F_W DMA_WRITE [0 ] 0
NO_F_W Memory_Data [0 ] 0
NO_F_W GETF [0 ] 0

2
simulators/gem5/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simerr Executable file
View File

@ -0,0 +1,2 @@
warn: Sockets disabled, not accepting gdb connections
hack: be nice to actually delete the event here

12
simulators/gem5/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout Executable file
View File

@ -0,0 +1,12 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 4 2012 11:51:44
gem5 started Jun 4 2012 13:41:27
gem5 executing on zizzer
command line: build/ALPHA_MOESI_hammer/gem5.opt -d build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer -re tests/run.py build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello world!
Exiting @ tick 208400 because target called exit()

92
simulators/gem5/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt Normal file
View File

@ -0,0 +1,92 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000208 # Number of seconds simulated
sim_ticks 208400 # Number of ticks simulated
final_tick 208400 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
host_inst_rate 52133 # Simulator instruction rate (inst/s)
host_op_rate 52125 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1696034 # Simulator tick rate (ticks/s)
host_mem_usage 224184 # Number of bytes of host memory used
host_seconds 0.12 # Real time elapsed on the host
sim_insts 6404 # Number of instructions simulated
sim_ops 6404 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 25656 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 8804 # Number of bytes read from this memory
system.physmem.bytes_read::total 34460 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 25656 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 25656 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 6696 # Number of bytes written to this memory
system.physmem.bytes_written::total 6696 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 6414 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 1185 # Number of read requests responded to by this memory
system.physmem.num_reads::total 7599 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 865 # Number of write requests responded to by this memory
system.physmem.num_writes::total 865 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 123109405 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 42245681 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 165355086 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 123109405 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 123109405 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 32130518 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 32130518 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 123109405 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 74376200 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 197485605 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 1185 # DTB read hits
system.cpu.dtb.read_misses 7 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 1192 # DTB read accesses
system.cpu.dtb.write_hits 865 # DTB write hits
system.cpu.dtb.write_misses 3 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 868 # DTB write accesses
system.cpu.dtb.data_hits 2050 # DTB hits
system.cpu.dtb.data_misses 10 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 2060 # DTB accesses
system.cpu.itb.fetch_hits 6415 # ITB hits
system.cpu.itb.fetch_misses 17 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 6432 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 17 # Number of system calls
system.cpu.numCycles 208400 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 6404 # Number of instructions committed
system.cpu.committedOps 6404 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 6331 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses
system.cpu.num_func_calls 251 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 750 # number of instructions that are conditional controls
system.cpu.num_int_insts 6331 # number of integer instructions
system.cpu.num_fp_insts 10 # number of float instructions
system.cpu.num_int_register_reads 8304 # number of times the integer registers were read
system.cpu.num_int_register_writes 4581 # number of times the integer registers were written
system.cpu.num_fp_register_reads 8 # number of times the floating registers were read
system.cpu.num_fp_register_writes 2 # number of times the floating registers were written
system.cpu.num_mem_refs 2060 # number of memory refs
system.cpu.num_load_insts 1192 # Number of load instructions
system.cpu.num_store_insts 868 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 208400 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
---------- End Simulation Statistics ----------

284
simulators/gem5/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini Normal file
View File

@ -0,0 +1,284 @@
[root]
type=Root
children=system
full_system=false
time_sync_enable=false
time_sync_period=100000000
time_sync_spin_threshold=100000
[system]
type=System
children=cpu dir_cntrl0 l1_cntrl0 physmem ruby sys_port_proxy
boot_osflags=a
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=timing
memories=system.physmem
num_work_ids=16
readfile=
symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.sys_port_proxy.slave[0]
[system.cpu]
type=TimingSimpleCPU
children=dtb interrupts itb tracer workload
checker=Null
clock=1
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
phase=0
profile=0
progress_interval=0
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
dcache_port=system.l1_cntrl0.sequencer.slave[1]
icache_port=system.l1_cntrl0.sequencer.slave[0]
[system.cpu.dtb]
type=AlphaTLB
size=64
[system.cpu.interrupts]
type=AlphaInterrupts
[system.cpu.itb]
type=AlphaTLB
size=48
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=hello
cwd=
egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
gid=100
input=cin
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=0
system=system
uid=100
[system.dir_cntrl0]
type=Directory_Controller
children=directory memBuffer
buffer_size=0
cntrl_id=1
directory=system.dir_cntrl0.directory
directory_latency=12
memBuffer=system.dir_cntrl0.memBuffer
number_of_TBEs=256
recycle_latency=10
ruby_system=system.ruby
transitions_per_cycle=32
version=0
[system.dir_cntrl0.directory]
type=RubyDirectoryMemory
map_levels=4
numa_high_bit=6
size=134217728
use_map=false
version=0
[system.dir_cntrl0.memBuffer]
type=RubyMemoryControl
bank_bit_0=8
bank_busy_time=11
bank_queue_size=12
banks_per_rank=8
basic_bus_busy_time=2
dimm_bit_0=12
dimms_per_channel=2
mem_bus_cycle_multiplier=10
mem_ctl_latency=12
mem_fixed_delay=0
mem_random_arbitrate=0
rank_bit_0=11
rank_rank_delay=1
ranks_per_dimm=2
read_write_delay=2
refresh_period=1560
tFaw=0
version=0
[system.l1_cntrl0]
type=L1Cache_Controller
children=cacheMemory sequencer
buffer_size=0
cacheMemory=system.l1_cntrl0.cacheMemory
cache_response_latency=12
cntrl_id=0
issue_latency=2
number_of_TBEs=256
recycle_latency=10
ruby_system=system.ruby
send_evictions=false
sequencer=system.l1_cntrl0.sequencer
transitions_per_cycle=32
version=0
[system.l1_cntrl0.cacheMemory]
type=RubyCache
assoc=2
is_icache=false
latency=3
replacement_policy=PSEUDO_LRU
size=256
start_index_bit=6
[system.l1_cntrl0.sequencer]
type=RubySequencer
access_phys_mem=true
dcache=system.l1_cntrl0.cacheMemory
deadlock_threshold=500000
icache=system.l1_cntrl0.cacheMemory
max_outstanding_requests=16
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
system=system
using_network_tester=false
using_ruby_tester=false
version=0
slave=system.cpu.icache_port system.cpu.dcache_port
[system.physmem]
type=SimpleMemory
conf_table_reported=false
file=
in_addr_map=true
latency=30
latency_var=0
null=false
range=0:134217727
zero=false
[system.ruby]
type=RubySystem
children=network profiler
block_size_bytes=64
clock=1
mem_size=134217728
no_mem_vec=false
random_seed=1234
randomization=false
stats_filename=ruby.stats
[system.ruby.network]
type=SimpleNetwork
children=topology
adaptive_routing=false
buffer_size=0
control_msg_size=8
endpoint_bandwidth=1000
number_of_virtual_networks=10
ruby_system=system.ruby
topology=system.ruby.network.topology
[system.ruby.network.topology]
type=Topology
children=ext_links0 ext_links1 int_links0 int_links1 routers0 routers1 routers2
description=Crossbar
ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1
int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1
print_config=false
routers=system.ruby.network.topology.routers0 system.ruby.network.topology.routers1 system.ruby.network.topology.routers2
[system.ruby.network.topology.ext_links0]
type=SimpleExtLink
bandwidth_factor=16
ext_node=system.l1_cntrl0
int_node=system.ruby.network.topology.routers0
latency=1
link_id=0
weight=1
[system.ruby.network.topology.ext_links1]
type=SimpleExtLink
bandwidth_factor=16
ext_node=system.dir_cntrl0
int_node=system.ruby.network.topology.routers1
latency=1
link_id=1
weight=1
[system.ruby.network.topology.int_links0]
type=SimpleIntLink
bandwidth_factor=16
latency=1
link_id=2
node_a=system.ruby.network.topology.routers0
node_b=system.ruby.network.topology.routers2
weight=1
[system.ruby.network.topology.int_links1]
type=SimpleIntLink
bandwidth_factor=16
latency=1
link_id=3
node_a=system.ruby.network.topology.routers1
node_b=system.ruby.network.topology.routers2
weight=1
[system.ruby.network.topology.routers0]
type=BasicRouter
router_id=0
[system.ruby.network.topology.routers1]
type=BasicRouter
router_id=1
[system.ruby.network.topology.routers2]
type=BasicRouter
router_id=2
[system.ruby.profiler]
type=RubyProfiler
all_instructions=false
hot_lines=false
num_of_sequencers=1
ruby_system=system.ruby
[system.sys_port_proxy]
type=RubyPortProxy
access_phys_mem=true
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
system=system
using_network_tester=false
using_ruby_tester=false
version=0
slave=system.system_port

311
simulators/gem5/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/ruby.stats Normal file
View File

@ -0,0 +1,311 @@
================ Begin RubySystem Configuration Print ================
RubySystem config:
random_seed: 1234
randomization: 0
cycle_period: 1
block_size_bytes: 64
block_size_bits: 6
memory_size_bytes: 134217728
memory_size_bits: 27
Network Configuration
---------------------
network: SIMPLE_NETWORK
topology:
virtual_net_0: active, ordered
virtual_net_1: active, ordered
virtual_net_2: active, ordered
virtual_net_3: active, ordered
virtual_net_4: active, ordered
virtual_net_5: inactive
virtual_net_6: inactive
virtual_net_7: inactive
virtual_net_8: inactive
virtual_net_9: inactive
Profiler Configuration
----------------------
periodic_stats_period: 1000000
================ End RubySystem Configuration Print ================
Real time: Jun/04/2012 13:42:47
Profiler Stats
--------------
Elapsed_time_in_seconds: 0
Elapsed_time_in_minutes: 0
Elapsed_time_in_hours: 0
Elapsed_time_in_days: 0
Virtual_time_in_seconds: 0.35
Virtual_time_in_minutes: 0.00583333
Virtual_time_in_hours: 9.72222e-05
Virtual_time_in_days: 4.05093e-06
Ruby_current_time: 342698
Ruby_start_time: 0
Ruby_cycles: 342698
mbytes_resident: 48.4648
mbytes_total: 219.84
resident_ratio: 0.220455
ruby_cycles_executed: [ 342699 ]
Busy Controller Counts:
L1Cache-0:0
Directory-0:0
Busy Bank Count:0
sequencer_requests_outstanding: [binsize: 1 max: 1 count: 8465 average: 1 | standard deviation: 0 | 0 8465 ]
All Non-Zero Cycle Demand Cache Accesses
----------------------------------------
miss_latency: [binsize: 2 max: 377 count: 8464 average: 39.4889 | standard deviation: 72.9776 | 0 6734 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 6 1 3 6 0 334 211 182 529 243 4 4 0 5 2 15 9 4 14 10 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 30 18 15 24 37 2 3 0 0 2 2 1 1 3 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 ]
miss_latency_LD: [binsize: 2 max: 375 count: 1185 average: 110.608 | standard deviation: 87.0282 | 0 458 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 3 0 1 2 0 147 90 74 255 81 2 1 0 3 0 12 3 1 9 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 4 2 11 4 0 2 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 ]
miss_latency_ST: [binsize: 2 max: 377 count: 865 average: 62.2439 | standard deviation: 89.6671 | 0 592 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 32 30 31 54 70 0 0 0 1 0 1 0 2 2 4 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 5 8 3 21 0 0 0 0 0 0 0 1 2 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 ]
miss_latency_IFETCH: [binsize: 2 max: 285 count: 6414 average: 23.2806 | standard deviation: 57.2661 | 0 5684 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 3 1 2 4 0 155 91 77 220 92 2 3 0 1 2 2 6 1 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 20 9 5 10 12 2 1 0 0 1 2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
miss_latency_L1Cache: [binsize: 1 max: 3 count: 6734 average: 3 | standard deviation: 0 | 0 0 0 6734 ]
miss_latency_Directory: [binsize: 2 max: 377 count: 1730 average: 181.521 | standard deviation: 26.4115 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 6 1 3 6 0 334 211 182 529 243 4 4 0 5 2 15 9 4 14 10 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 30 18 15 24 37 2 3 0 0 2 2 1 1 3 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 ]
miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
imcomplete_wCC_Times: 0
miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ]
miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ]
miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ]
miss_latency_dir_first_response_to_completion: [binsize: 1 max: 159 count: 1 average: 159 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
imcomplete_dir_Times: 1729
miss_latency_LD_L1Cache: [binsize: 1 max: 3 count: 458 average: 3 | standard deviation: 0 | 0 0 0 458 ]
miss_latency_LD_Directory: [binsize: 2 max: 375 count: 727 average: 178.4 | standard deviation: 21.0913 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 3 0 1 2 0 147 90 74 255 81 2 1 0 3 0 12 3 1 9 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 4 2 11 4 0 2 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 ]
miss_latency_ST_L1Cache: [binsize: 1 max: 3 count: 592 average: 3 | standard deviation: 0 | 0 0 0 592 ]
miss_latency_ST_Directory: [binsize: 2 max: 377 count: 273 average: 190.714 | standard deviation: 36.5384 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 32 30 31 54 70 0 0 0 1 0 1 0 2 2 4 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 5 8 3 21 0 0 0 0 0 0 0 1 2 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 ]
miss_latency_IFETCH_L1Cache: [binsize: 1 max: 3 count: 5684 average: 3 | standard deviation: 0 | 0 0 0 5684 ]
miss_latency_IFETCH_Directory: [binsize: 2 max: 285 count: 730 average: 181.192 | standard deviation: 25.9199 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 3 1 2 4 0 155 91 77 220 92 2 3 0 1 2 2 6 1 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 20 9 5 10 12 2 1 0 0 1 2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
All Non-Zero Cycle SW Prefetch Requests
------------------------------------
prefetch_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
prefetch_latency_L2Miss:[binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
Request vs. RubySystem State Profile
--------------------------------
filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
Message Delayed Cycles
----------------------
Total_delay_cycles: [binsize: 1 max: 0 count: 3456 average: 0 | standard deviation: 0 | 3456 ]
Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 3456 average: 0 | standard deviation: 0 | 3456 ]
virtual_network_0_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 1730 average: 0 | standard deviation: 0 | 1730 ]
virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 1726 average: 0 | standard deviation: 0 | 1726 ]
virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
virtual_network_6_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
virtual_network_7_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
virtual_network_8_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
virtual_network_9_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
Resource Usage
--------------
page_size: 4096
user_time: 0
system_time: 0
page_reclaims: 12835
page_faults: 0
swaps: 0
block_inputs: 0
block_outputs: 88
Network Stats
-------------
total_msg_count_Control: 5190 41520
total_msg_count_Data: 5178 372816
total_msg_count_Response_Data: 5190 373680
total_msg_count_Writeback_Control: 5178 41424
total_msgs: 20736 total_bytes: 829440
switch_0_inlinks: 2
switch_0_outlinks: 2
links_utilized_percent_switch_0: 2.52117
links_utilized_percent_switch_0_link_0: 2.5235 bw: 16000 base_latency: 1
links_utilized_percent_switch_0_link_1: 2.51884 bw: 16000 base_latency: 1
outgoing_messages_switch_0_link_0_Response_Data: 1730 124560 [ 0 0 0 0 1730 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_0_link_0_Writeback_Control: 1726 13808 [ 0 0 0 1726 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_0_link_1_Control: 1730 13840 [ 0 0 1730 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_0_link_1_Data: 1726 124272 [ 0 0 1726 0 0 0 0 0 0 0 ] base_latency: 1
switch_1_inlinks: 2
switch_1_outlinks: 2
links_utilized_percent_switch_1: 2.52117
links_utilized_percent_switch_1_link_0: 2.51884 bw: 16000 base_latency: 1
links_utilized_percent_switch_1_link_1: 2.5235 bw: 16000 base_latency: 1
outgoing_messages_switch_1_link_0_Control: 1730 13840 [ 0 0 1730 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_1_link_0_Data: 1726 124272 [ 0 0 1726 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_1_link_1_Response_Data: 1730 124560 [ 0 0 0 0 1730 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_1_link_1_Writeback_Control: 1726 13808 [ 0 0 0 1726 0 0 0 0 0 0 ] base_latency: 1
switch_2_inlinks: 2
switch_2_outlinks: 2
links_utilized_percent_switch_2: 2.52117
links_utilized_percent_switch_2_link_0: 2.5235 bw: 16000 base_latency: 1
links_utilized_percent_switch_2_link_1: 2.51884 bw: 16000 base_latency: 1
outgoing_messages_switch_2_link_0_Response_Data: 1730 124560 [ 0 0 0 0 1730 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_2_link_0_Writeback_Control: 1726 13808 [ 0 0 0 1726 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_2_link_1_Control: 1730 13840 [ 0 0 1730 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_2_link_1_Data: 1726 124272 [ 0 0 1726 0 0 0 0 0 0 0 ] base_latency: 1
Cache Stats: system.l1_cntrl0.cacheMemory
system.l1_cntrl0.cacheMemory_total_misses: 1730
system.l1_cntrl0.cacheMemory_total_demand_misses: 1730
system.l1_cntrl0.cacheMemory_total_prefetches: 0
system.l1_cntrl0.cacheMemory_total_sw_prefetches: 0
system.l1_cntrl0.cacheMemory_total_hw_prefetches: 0
system.l1_cntrl0.cacheMemory_request_type_LD: 42.0231%
system.l1_cntrl0.cacheMemory_request_type_ST: 15.7803%
system.l1_cntrl0.cacheMemory_request_type_IFETCH: 42.1965%
system.l1_cntrl0.cacheMemory_access_mode_type_Supervisor: 1730 100%
--- L1Cache ---
- Event Counts -
Load [1185 ] 1185
Ifetch [6414 ] 6414
Store [865 ] 865
Data [1730 ] 1730
Fwd_GETX [0 ] 0
Inv [0 ] 0
Replacement [1726 ] 1726
Writeback_Ack [1726 ] 1726
Writeback_Nack [0 ] 0
- Transitions -
I Load [727 ] 727
I Ifetch [730 ] 730
I Store [273 ] 273
I Inv [0 ] 0
I Replacement [0 ] 0
II Writeback_Nack [0 ] 0
M Load [458 ] 458
M Ifetch [5684 ] 5684
M Store [592 ] 592
M Fwd_GETX [0 ] 0
M Inv [0 ] 0
M Replacement [1726 ] 1726
MI Fwd_GETX [0 ] 0
MI Inv [0 ] 0
MI Writeback_Ack [1726 ] 1726
MI Writeback_Nack [0 ] 0
MII Fwd_GETX [0 ] 0
IS Data [1457 ] 1457
IM Data [273 ] 273
Memory controller: system.dir_cntrl0.memBuffer:
memory_total_requests: 3456
memory_reads: 1730
memory_writes: 1726
memory_refreshes: 714
memory_total_request_delays: 4411
memory_delays_per_request: 1.27633
memory_delays_in_input_queue: 1083
memory_delays_behind_head_of_bank_queue: 8
memory_delays_stalled_at_head_of_bank_queue: 3320
memory_stalls_for_bank_busy: 1509
memory_stalls_for_random_busy: 0
memory_stalls_for_anti_starvation: 0
memory_stalls_for_arbitration: 99
memory_stalls_for_bus: 1677
memory_stalls_for_tfaw: 0
memory_stalls_for_read_write_turnaround: 35
memory_stalls_for_read_read_turnaround: 0
accesses_per_bank: 162 36 92 110 106 362 98 36 32 34 83 92 110 104 84 86 83 53 50 58 64 124 212 72 66 50 122 190 220 325 42 98
--- Directory ---
- Event Counts -
GETX [1730 ] 1730
GETS [0 ] 0
PUTX [1726 ] 1726
PUTX_NotOwner [0 ] 0
DMA_READ [0 ] 0
DMA_WRITE [0 ] 0
Memory_Data [1730 ] 1730
Memory_Ack [1726 ] 1726
- Transitions -
I GETX [1730 ] 1730
I PUTX_NotOwner [0 ] 0
I DMA_READ [0 ] 0
I DMA_WRITE [0 ] 0
M GETX [0 ] 0
M PUTX [1726 ] 1726
M PUTX_NotOwner [0 ] 0
M DMA_READ [0 ] 0
M DMA_WRITE [0 ] 0
M_DRD GETX [0 ] 0
M_DRD PUTX [0 ] 0
M_DWR GETX [0 ] 0
M_DWR PUTX [0 ] 0
M_DWRI GETX [0 ] 0
M_DWRI Memory_Ack [0 ] 0
M_DRDI GETX [0 ] 0
M_DRDI Memory_Ack [0 ] 0
IM GETX [0 ] 0
IM GETS [0 ] 0
IM PUTX [0 ] 0
IM PUTX_NotOwner [0 ] 0
IM DMA_READ [0 ] 0
IM DMA_WRITE [0 ] 0
IM Memory_Data [1730 ] 1730
MI GETX [0 ] 0
MI GETS [0 ] 0
MI PUTX [0 ] 0
MI PUTX_NotOwner [0 ] 0
MI DMA_READ [0 ] 0
MI DMA_WRITE [0 ] 0
MI Memory_Ack [1726 ] 1726
ID GETX [0 ] 0
ID GETS [0 ] 0
ID PUTX [0 ] 0
ID PUTX_NotOwner [0 ] 0
ID DMA_READ [0 ] 0
ID DMA_WRITE [0 ] 0
ID Memory_Data [0 ] 0
ID_W GETX [0 ] 0
ID_W GETS [0 ] 0
ID_W PUTX [0 ] 0
ID_W PUTX_NotOwner [0 ] 0
ID_W DMA_READ [0 ] 0
ID_W DMA_WRITE [0 ] 0
ID_W Memory_Ack [0 ] 0

2
simulators/gem5/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simerr Executable file
View File

@ -0,0 +1,2 @@
warn: Sockets disabled, not accepting gdb connections
hack: be nice to actually delete the event here

12
simulators/gem5/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simout Executable file
View File

@ -0,0 +1,12 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 4 2012 11:50:11
gem5 started Jun 4 2012 13:42:46
gem5 executing on zizzer
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello world!
Exiting @ tick 342698 because target called exit()

92
simulators/gem5/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt Normal file
View File

@ -0,0 +1,92 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000343 # Number of seconds simulated
sim_ticks 342698 # Number of ticks simulated
final_tick 342698 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
host_inst_rate 17946 # Simulator instruction rate (inst/s)
host_op_rate 17945 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 960252 # Simulator tick rate (ticks/s)
host_mem_usage 225120 # Number of bytes of host memory used
host_seconds 0.36 # Real time elapsed on the host
sim_insts 6404 # Number of instructions simulated
sim_ops 6404 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 25656 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 8804 # Number of bytes read from this memory
system.physmem.bytes_read::total 34460 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 25656 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 25656 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 6696 # Number of bytes written to this memory
system.physmem.bytes_written::total 6696 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 6414 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 1185 # Number of read requests responded to by this memory
system.physmem.num_reads::total 7599 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 865 # Number of write requests responded to by this memory
system.physmem.num_writes::total 865 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 74864750 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 25690258 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 100555008 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 74864750 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 74864750 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 19539069 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 19539069 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 74864750 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 45229327 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 120094077 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 1185 # DTB read hits
system.cpu.dtb.read_misses 7 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 1192 # DTB read accesses
system.cpu.dtb.write_hits 865 # DTB write hits
system.cpu.dtb.write_misses 3 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 868 # DTB write accesses
system.cpu.dtb.data_hits 2050 # DTB hits
system.cpu.dtb.data_misses 10 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 2060 # DTB accesses
system.cpu.itb.fetch_hits 6415 # ITB hits
system.cpu.itb.fetch_misses 17 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 6432 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 17 # Number of system calls
system.cpu.numCycles 342698 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 6404 # Number of instructions committed
system.cpu.committedOps 6404 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 6331 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses
system.cpu.num_func_calls 251 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 750 # number of instructions that are conditional controls
system.cpu.num_int_insts 6331 # number of integer instructions
system.cpu.num_fp_insts 10 # number of float instructions
system.cpu.num_int_register_reads 8304 # number of times the integer registers were read
system.cpu.num_int_register_writes 4581 # number of times the integer registers were written
system.cpu.num_fp_register_reads 8 # number of times the floating registers were read
system.cpu.num_fp_register_writes 2 # number of times the floating registers were written
system.cpu.num_mem_refs 2060 # number of memory refs
system.cpu.num_load_insts 1192 # Number of load instructions
system.cpu.num_store_insts 868 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 342698 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
---------- End Simulation Statistics ----------

198
simulators/gem5/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini Normal file
View File

@ -0,0 +1,198 @@
[root]
type=Root
children=system
full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
boot_osflags=a
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
readfile=
symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.cpu]
type=TimingSimpleCPU
children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
phase=0
profile=0
progress_interval=0
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=262144
subblock_size=0
system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
[system.cpu.dtb]
type=AlphaTLB
size=64
[system.cpu.icache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=131072
subblock_size=0
system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.interrupts]
type=AlphaInterrupts
[system.cpu.itb]
type=AlphaTLB
size=48
[system.cpu.l2cache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=false
latency=10000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=2097152
subblock_size=0
system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
[system.cpu.toL2Bus]
type=CoherentBus
block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=hello
cwd=
egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
gid=100
input=cin
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=0
system=system
uid=100
[system.membus]
type=CoherentBus
block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
master=system.physmem.port[0]
slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=SimpleMemory
conf_table_reported=false
file=
in_addr_map=true
latency=30000
latency_var=0
null=false
range=0:134217727
zero=false
port=system.membus.master[0]

2
simulators/gem5/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/simerr Executable file
View File

@ -0,0 +1,2 @@
warn: Sockets disabled, not accepting gdb connections
hack: be nice to actually delete the event here

12
simulators/gem5/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/simout Executable file
View File

@ -0,0 +1,12 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 4 2012 11:50:11
gem5 started Jun 4 2012 13:52:31
gem5 executing on zizzer
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello world!
Exiting @ tick 33007000 because target called exit()

387
simulators/gem5/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt Normal file
View File

@ -0,0 +1,387 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000033 # Number of seconds simulated
sim_ticks 33007000 # Number of ticks simulated
final_tick 33007000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 524144 # Simulator instruction rate (inst/s)
host_op_rate 523337 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 2693393609 # Simulator tick rate (ticks/s)
host_mem_usage 214140 # Number of bytes of host memory used
host_seconds 0.01 # Real time elapsed on the host
sim_insts 6404 # Number of instructions simulated
sim_ops 6404 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 10752 # Number of bytes read from this memory
system.physmem.bytes_read::total 28544 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 17792 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 17792 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 278 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 168 # Number of read requests responded to by this memory
system.physmem.num_reads::total 446 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 539037174 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 325749084 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 864786257 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 539037174 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 539037174 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 539037174 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 325749084 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 864786257 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 1185 # DTB read hits
system.cpu.dtb.read_misses 7 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 1192 # DTB read accesses
system.cpu.dtb.write_hits 865 # DTB write hits
system.cpu.dtb.write_misses 3 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 868 # DTB write accesses
system.cpu.dtb.data_hits 2050 # DTB hits
system.cpu.dtb.data_misses 10 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 2060 # DTB accesses
system.cpu.itb.fetch_hits 6415 # ITB hits
system.cpu.itb.fetch_misses 17 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 6432 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 17 # Number of system calls
system.cpu.numCycles 66014 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 6404 # Number of instructions committed
system.cpu.committedOps 6404 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 6331 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses
system.cpu.num_func_calls 251 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 750 # number of instructions that are conditional controls
system.cpu.num_int_insts 6331 # number of integer instructions
system.cpu.num_fp_insts 10 # number of float instructions
system.cpu.num_int_register_reads 8304 # number of times the integer registers were read
system.cpu.num_int_register_writes 4581 # number of times the integer registers were written
system.cpu.num_fp_register_reads 8 # number of times the floating registers were read
system.cpu.num_fp_register_writes 2 # number of times the floating registers were written
system.cpu.num_mem_refs 2060 # number of memory refs
system.cpu.num_load_insts 1192 # Number of load instructions
system.cpu.num_store_insts 868 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 66014 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.icache.replacements 0 # number of replacements
system.cpu.icache.tagsinuse 127.883393 # Cycle average of tags in use
system.cpu.icache.total_refs 6136 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 279 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 21.992832 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 127.883393 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.062443 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.062443 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 6136 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 6136 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 6136 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 6136 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 6136 # number of overall hits
system.cpu.icache.overall_hits::total 6136 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 279 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 279 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 279 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 279 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 279 # number of overall misses
system.cpu.icache.overall_misses::total 279 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 15582000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 15582000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 15582000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 15582000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 15582000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 15582000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 6415 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 6415 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 6415 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 6415 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 6415 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 6415 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.043492 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.043492 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.043492 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.043492 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.043492 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.043492 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55849.462366 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 55849.462366 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 55849.462366 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 55849.462366 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 55849.462366 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 55849.462366 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 279 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 279 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 279 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 279 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 279 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 279 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14745000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 14745000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14745000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 14745000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14745000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 14745000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.043492 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.043492 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.043492 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.043492 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.043492 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.043492 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52849.462366 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52849.462366 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52849.462366 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 52849.462366 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52849.462366 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 52849.462366 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.tagsinuse 103.680615 # Cycle average of tags in use
system.cpu.dcache.total_refs 1882 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 168 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 11.202381 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 103.680615 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.025313 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.025313 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 1090 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 1090 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 792 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 792 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 1882 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 1882 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 1882 # number of overall hits
system.cpu.dcache.overall_hits::total 1882 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 95 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 95 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 73 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 73 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 168 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 168 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 168 # number of overall misses
system.cpu.dcache.overall_misses::total 168 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 5320000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 5320000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 4088000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 4088000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 9408000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 9408000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 9408000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 9408000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 1185 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 1185 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 2050 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 2050 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 2050 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 2050 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.080169 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.080169 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.084393 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.084393 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.081951 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.081951 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.081951 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.081951 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56000 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 56000 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56000 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 56000 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 56000 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 56000 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 56000 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 56000 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 95 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 95 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 168 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 168 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 168 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5035000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 5035000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3869000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3869000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8904000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 8904000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8904000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 8904000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.080169 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.080169 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.081951 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.081951 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.081951 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.081951 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 184.342479 # Cycle average of tags in use
system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 373 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.002681 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::cpu.inst 127.900723 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 56.441756 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::cpu.inst 0.003903 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.001722 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.005626 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits
system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits
system.cpu.l2cache.overall_hits::total 1 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 278 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 95 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 373 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 73 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 73 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 278 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 168 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 446 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 278 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 168 # number of overall misses
system.cpu.l2cache.overall_misses::total 446 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14456000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4940000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 19396000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3796000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 3796000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 14456000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 8736000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 23192000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 14456000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 8736000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 23192000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 279 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 95 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 374 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 73 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 279 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 168 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 447 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 279 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 168 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 447 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996416 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.997326 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996416 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.997763 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996416 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.997763 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 278 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 95 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 373 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 73 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 73 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 278 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 168 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 446 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 278 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 446 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11120000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3800000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14920000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2920000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2920000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11120000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6720000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 17840000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11120000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6720000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 17840000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996416 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997326 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996416 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.997763 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996416 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.997763 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

529
simulators/gem5/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini Normal file
View File

@ -0,0 +1,529 @@
[root]
type=Root
children=system
full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
boot_osflags=a
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
readfile=
symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.cpu]
type=DerivO3CPU
children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
LSQDepCheckShift=4
RASSize=16
SQEntries=32
SSITSize=1024
activity=0
backComSize=5
cachePorts=200
checker=Null
choiceCtrBits=2
choicePredictorSize=8192
clock=500
commitToDecodeDelay=1
commitToFetchDelay=1
commitToIEWDelay=1
commitToRenameDelay=1
commitWidth=8
cpu_id=0
decodeToFetchDelay=1
decodeToRenameDelay=1
decodeWidth=8
defer_registration=false
dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
fetchToDecodeDelay=1
fetchTrapLatency=1
fetchWidth=8
forwardComSize=5
fuPool=system.cpu.fuPool
function_trace=false
function_trace_start=0
globalCtrBits=2
globalHistoryBits=13
globalPredictorSize=8192
iewToCommitDelay=1
iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
instShiftAmt=2
interrupts=system.cpu.interrupts
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
localCtrBits=2
localHistoryBits=11
localHistoryTableSize=2048
localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
needsTSO=false
numIQEntries=64
numPhysFloatRegs=256
numPhysIntRegs=256
numROBEntries=192
numRobs=1
numThreads=1
phase=0
predType=tournament
profile=0
progress_interval=0
renameToDecodeDelay=1
renameToFetchDelay=1
renameToIEWDelay=2
renameToROBDelay=1
renameWidth=8
smtCommitPolicy=RoundRobin
smtFetchPolicy=SingleThread
smtIQPolicy=Partitioned
smtIQThreshold=100
smtLSQPolicy=Partitioned
smtLSQThreshold=100
smtNumFetchingThreads=1
smtROBPolicy=Partitioned
smtROBThreshold=100
squashWidth=8
store_set_clear_period=250000
system=system
tracer=system.cpu.tracer
trapLatency=13
wbDepth=1
wbWidth=8
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=262144
subblock_size=0
system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
[system.cpu.dtb]
type=AlphaTLB
size=64
[system.cpu.fuPool]
type=FUPool
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
[system.cpu.fuPool.FUList0]
type=FUDesc
children=opList
count=6
opList=system.cpu.fuPool.FUList0.opList
[system.cpu.fuPool.FUList0.opList]
type=OpDesc
issueLat=1
opClass=IntAlu
opLat=1
[system.cpu.fuPool.FUList1]
type=FUDesc
children=opList0 opList1
count=2
opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
[system.cpu.fuPool.FUList1.opList0]
type=OpDesc
issueLat=1
opClass=IntMult
opLat=3
[system.cpu.fuPool.FUList1.opList1]
type=OpDesc
issueLat=19
opClass=IntDiv
opLat=20
[system.cpu.fuPool.FUList2]
type=FUDesc
children=opList0 opList1 opList2
count=4
opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
[system.cpu.fuPool.FUList2.opList0]
type=OpDesc
issueLat=1
opClass=FloatAdd
opLat=2
[system.cpu.fuPool.FUList2.opList1]
type=OpDesc
issueLat=1
opClass=FloatCmp
opLat=2
[system.cpu.fuPool.FUList2.opList2]
type=OpDesc
issueLat=1
opClass=FloatCvt
opLat=2
[system.cpu.fuPool.FUList3]
type=FUDesc
children=opList0 opList1 opList2
count=2
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
[system.cpu.fuPool.FUList3.opList0]
type=OpDesc
issueLat=1
opClass=FloatMult
opLat=4
[system.cpu.fuPool.FUList3.opList1]
type=OpDesc
issueLat=12
opClass=FloatDiv
opLat=12
[system.cpu.fuPool.FUList3.opList2]
type=OpDesc
issueLat=24
opClass=FloatSqrt
opLat=24
[system.cpu.fuPool.FUList4]
type=FUDesc
children=opList
count=0
opList=system.cpu.fuPool.FUList4.opList
[system.cpu.fuPool.FUList4.opList]
type=OpDesc
issueLat=1
opClass=MemRead
opLat=1
[system.cpu.fuPool.FUList5]
type=FUDesc
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
count=4
opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
[system.cpu.fuPool.FUList5.opList00]
type=OpDesc
issueLat=1
opClass=SimdAdd
opLat=1
[system.cpu.fuPool.FUList5.opList01]
type=OpDesc
issueLat=1
opClass=SimdAddAcc
opLat=1
[system.cpu.fuPool.FUList5.opList02]
type=OpDesc
issueLat=1
opClass=SimdAlu
opLat=1
[system.cpu.fuPool.FUList5.opList03]
type=OpDesc
issueLat=1
opClass=SimdCmp
opLat=1
[system.cpu.fuPool.FUList5.opList04]
type=OpDesc
issueLat=1
opClass=SimdCvt
opLat=1
[system.cpu.fuPool.FUList5.opList05]
type=OpDesc
issueLat=1
opClass=SimdMisc
opLat=1
[system.cpu.fuPool.FUList5.opList06]
type=OpDesc
issueLat=1
opClass=SimdMult
opLat=1
[system.cpu.fuPool.FUList5.opList07]
type=OpDesc
issueLat=1
opClass=SimdMultAcc
opLat=1
[system.cpu.fuPool.FUList5.opList08]
type=OpDesc
issueLat=1
opClass=SimdShift
opLat=1
[system.cpu.fuPool.FUList5.opList09]
type=OpDesc
issueLat=1
opClass=SimdShiftAcc
opLat=1
[system.cpu.fuPool.FUList5.opList10]
type=OpDesc
issueLat=1
opClass=SimdSqrt
opLat=1
[system.cpu.fuPool.FUList5.opList11]
type=OpDesc
issueLat=1
opClass=SimdFloatAdd
opLat=1
[system.cpu.fuPool.FUList5.opList12]
type=OpDesc
issueLat=1
opClass=SimdFloatAlu
opLat=1
[system.cpu.fuPool.FUList5.opList13]
type=OpDesc
issueLat=1
opClass=SimdFloatCmp
opLat=1
[system.cpu.fuPool.FUList5.opList14]
type=OpDesc
issueLat=1
opClass=SimdFloatCvt
opLat=1
[system.cpu.fuPool.FUList5.opList15]
type=OpDesc
issueLat=1
opClass=SimdFloatDiv
opLat=1
[system.cpu.fuPool.FUList5.opList16]
type=OpDesc
issueLat=1
opClass=SimdFloatMisc
opLat=1
[system.cpu.fuPool.FUList5.opList17]
type=OpDesc
issueLat=1
opClass=SimdFloatMult
opLat=1
[system.cpu.fuPool.FUList5.opList18]
type=OpDesc
issueLat=1
opClass=SimdFloatMultAcc
opLat=1
[system.cpu.fuPool.FUList5.opList19]
type=OpDesc
issueLat=1
opClass=SimdFloatSqrt
opLat=1
[system.cpu.fuPool.FUList6]
type=FUDesc
children=opList
count=0
opList=system.cpu.fuPool.FUList6.opList
[system.cpu.fuPool.FUList6.opList]
type=OpDesc
issueLat=1
opClass=MemWrite
opLat=1
[system.cpu.fuPool.FUList7]
type=FUDesc
children=opList0 opList1
count=4
opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
[system.cpu.fuPool.FUList7.opList0]
type=OpDesc
issueLat=1
opClass=MemRead
opLat=1
[system.cpu.fuPool.FUList7.opList1]
type=OpDesc
issueLat=1
opClass=MemWrite
opLat=1
[system.cpu.fuPool.FUList8]
type=FUDesc
children=opList
count=1
opList=system.cpu.fuPool.FUList8.opList
[system.cpu.fuPool.FUList8.opList]
type=OpDesc
issueLat=3
opClass=IprAccess
opLat=3
[system.cpu.icache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=131072
subblock_size=0
system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.interrupts]
type=AlphaInterrupts
[system.cpu.itb]
type=AlphaTLB
size=48
[system.cpu.l2cache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=false
latency=1000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=2097152
subblock_size=0
system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
[system.cpu.toL2Bus]
type=CoherentBus
block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=hello
cwd=
egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello
gid=100
input=cin
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=0
system=system
uid=100
[system.membus]
type=CoherentBus
block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
master=system.physmem.port[0]
slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=SimpleMemory
conf_table_reported=false
file=
in_addr_map=true
latency=30000
latency_var=0
null=false
range=0:134217727
zero=false
port=system.membus.master[0]

4
simulators/gem5/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simerr Executable file
View File

@ -0,0 +1,4 @@
warn: Sockets disabled, not accepting gdb connections
warn: Prefetch instructions in Alpha do not do anything
warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
hack: be nice to actually delete the event here

12
simulators/gem5/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout Executable file
View File

@ -0,0 +1,12 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 4 2012 11:50:11
gem5 started Jun 4 2012 13:45:03
gem5 executing on zizzer
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello world!
Exiting @ tick 7015000 because target called exit()

641
simulators/gem5/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt Normal file
View File

@ -0,0 +1,641 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000007 # Number of seconds simulated
sim_ticks 7015000 # Number of ticks simulated
final_tick 7015000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 16156 # Simulator instruction rate (inst/s)
host_op_rate 16154 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 47467285 # Simulator tick rate (ticks/s)
host_mem_usage 214556 # Number of bytes of host memory used
host_seconds 0.15 # Real time elapsed on the host
sim_insts 2387 # Number of instructions simulated
sim_ops 2387 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 12096 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 5504 # Number of bytes read from this memory
system.physmem.bytes_read::total 17600 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 12096 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 12096 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 189 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 86 # Number of read requests responded to by this memory
system.physmem.num_reads::total 275 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 1724305061 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 784604419 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 2508909480 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 1724305061 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 1724305061 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 1724305061 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 784604419 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 2508909480 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 711 # DTB read hits
system.cpu.dtb.read_misses 43 # DTB read misses
system.cpu.dtb.read_acv 1 # DTB read access violations
system.cpu.dtb.read_accesses 754 # DTB read accesses
system.cpu.dtb.write_hits 380 # DTB write hits
system.cpu.dtb.write_misses 23 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 403 # DTB write accesses
system.cpu.dtb.data_hits 1091 # DTB hits
system.cpu.dtb.data_misses 66 # DTB misses
system.cpu.dtb.data_acv 1 # DTB access violations
system.cpu.dtb.data_accesses 1157 # DTB accesses
system.cpu.itb.fetch_hits 1067 # ITB hits
system.cpu.itb.fetch_misses 33 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 1100 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 4 # Number of system calls
system.cpu.numCycles 14031 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.BPredUnit.lookups 1201 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 569 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 276 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 824 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 230 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 243 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 55 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 3890 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 7412 # Number of instructions fetch has processed
system.cpu.fetch.Branches 1201 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 473 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 1260 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 922 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 250 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 17 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 780 # Number of stall cycles due to pending traps
system.cpu.fetch.CacheLines 1067 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 174 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 6820 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 1.086804 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.510240 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 5560 81.52% 81.52% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 47 0.69% 82.21% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 133 1.95% 84.16% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 103 1.51% 85.67% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 148 2.17% 87.84% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 78 1.14% 88.99% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 68 1.00% 89.99% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 64 0.94% 90.92% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 619 9.08% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 6820 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.085596 # Number of branch fetches per cycle
system.cpu.fetch.rate 0.528259 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 4790 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 271 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 1197 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 17 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 545 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 185 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 83 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 6535 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 298 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 545 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 4889 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 77 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 147 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 1115 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 47 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 6259 # Number of instructions processed by rename
system.cpu.rename.IQFullEvents 17 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 24 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenamedOperands 4535 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 7053 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 7041 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 12 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 1768 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 2767 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 8 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 6 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 162 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 996 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 505 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 0 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 5232 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 7 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 4206 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 51 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 2612 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 1532 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 3 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 6820 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 0.616716 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.331431 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 5134 75.28% 75.28% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 613 8.99% 84.27% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 383 5.62% 89.88% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 269 3.94% 93.83% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 207 3.04% 96.86% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 134 1.96% 98.83% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 52 0.76% 99.59% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 14 0.21% 99.79% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 14 0.21% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 6820 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 5 11.63% 11.63% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 11.63% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 11.63% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.63% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.63% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.63% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 11.63% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.63% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 11.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 11.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.63% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 15 34.88% 46.51% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 23 53.49% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 2987 71.02% 71.02% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 1 0.02% 71.04% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 71.04% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 71.04% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 71.04% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 71.04% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 71.04% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 71.04% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 71.04% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 71.04% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 71.04% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 71.04% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 71.04% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 71.04% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 71.04% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 71.04% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 71.04% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 71.04% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 71.04% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 71.04% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 71.04% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 71.04% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 71.04% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 71.04% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 71.04% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 71.04% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 71.04% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 71.04% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 71.04% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 805 19.14% 90.18% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 413 9.82% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 4206 # Type of FU issued
system.cpu.iq.rate 0.299765 # Inst issue rate
system.cpu.iq.fu_busy_cnt 43 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.010223 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 15313 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 7848 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 3807 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 13 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 6 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 6 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 4242 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 7 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 33 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 581 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 5 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 211 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 545 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 53 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 17 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 5607 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 106 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 996 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 505 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 7 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 17 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 5 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 80 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 161 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 241 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 4005 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 757 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 201 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 368 # number of nop insts executed
system.cpu.iew.exec_refs 1160 # number of memory reference insts executed
system.cpu.iew.exec_branches 681 # Number of branches executed
system.cpu.iew.exec_stores 403 # Number of stores executed
system.cpu.iew.exec_rate 0.285439 # Inst execution rate
system.cpu.iew.wb_sent 3920 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 3813 # cumulative count of insts written-back
system.cpu.iew.wb_producers 1793 # num instructions producing a value
system.cpu.iew.wb_consumers 2339 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 0.271755 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.766567 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitCommittedInsts 2576 # The number of committed instructions
system.cpu.commit.commitCommittedOps 2576 # The number of committed instructions
system.cpu.commit.commitSquashedInsts 3022 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 198 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 6275 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 0.410518 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.252508 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 5374 85.64% 85.64% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 226 3.60% 89.24% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 318 5.07% 94.31% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 120 1.91% 96.22% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 75 1.20% 97.42% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 53 0.84% 98.26% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 33 0.53% 98.79% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 17 0.27% 99.06% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 59 0.94% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 6275 # Number of insts commited each cycle
system.cpu.commit.committedInsts 2576 # Number of instructions committed
system.cpu.commit.committedOps 2576 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 709 # Number of memory references committed
system.cpu.commit.loads 415 # Number of loads committed
system.cpu.commit.membars 0 # Number of memory barriers committed
system.cpu.commit.branches 396 # Number of branches committed
system.cpu.commit.fp_insts 6 # Number of committed floating point instructions.
system.cpu.commit.int_insts 2367 # Number of committed integer instructions.
system.cpu.commit.function_calls 71 # Number of function calls committed.
system.cpu.commit.bw_lim_events 59 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 11567 # The number of ROB reads
system.cpu.rob.rob_writes 11753 # The number of ROB writes
system.cpu.timesIdled 138 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 7211 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 2387 # Number of Instructions Simulated
system.cpu.committedOps 2387 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 2387 # Number of Instructions Simulated
system.cpu.cpi 5.878090 # CPI: Cycles Per Instruction
system.cpu.cpi_total 5.878090 # CPI: Total CPI of All Threads
system.cpu.ipc 0.170123 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.170123 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 4832 # number of integer regfile reads
system.cpu.int_regfile_writes 2958 # number of integer regfile writes
system.cpu.fp_regfile_reads 6 # number of floating regfile reads
system.cpu.misc_regfile_reads 1 # number of misc regfile reads
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
system.cpu.icache.replacements 0 # number of replacements
system.cpu.icache.tagsinuse 93.540284 # Cycle average of tags in use
system.cpu.icache.total_refs 817 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 189 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 4.322751 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 93.540284 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.045674 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.045674 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 817 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 817 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 817 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 817 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 817 # number of overall hits
system.cpu.icache.overall_hits::total 817 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 250 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 250 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 250 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 250 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 250 # number of overall misses
system.cpu.icache.overall_misses::total 250 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 8957500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 8957500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 8957500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 8957500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 8957500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 8957500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 1067 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 1067 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 1067 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 1067 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 1067 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 1067 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.234302 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.234302 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.234302 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.234302 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.234302 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.234302 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35830 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 35830 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 35830 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 35830 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 35830 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 35830 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 61 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 61 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 61 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 61 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 61 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 61 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 189 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 189 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 189 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 189 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 189 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 189 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 6695500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 6695500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 6695500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 6695500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 6695500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 6695500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.177132 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.177132 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.177132 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.177132 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.177132 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.177132 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35425.925926 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35425.925926 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35425.925926 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 35425.925926 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35425.925926 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 35425.925926 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.tagsinuse 46.152964 # Cycle average of tags in use
system.cpu.dcache.total_refs 793 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 86 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 9.220930 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 46.152964 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.011268 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.011268 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 571 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 571 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 222 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 222 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 793 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 793 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 793 # number of overall hits
system.cpu.dcache.overall_hits::total 793 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 107 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 107 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 72 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 72 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 179 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 179 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 179 # number of overall misses
system.cpu.dcache.overall_misses::total 179 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 3676500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 3676500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 2816000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 2816000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 6492500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 6492500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 6492500 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 6492500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 678 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 678 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 294 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 972 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 972 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 972 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 972 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.157817 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.157817 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.244898 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.244898 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.184156 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.184156 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.184156 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.184156 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34359.813084 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 34359.813084 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39111.111111 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 39111.111111 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 36270.949721 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 36270.949721 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 36270.949721 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 36270.949721 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 45 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 45 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 48 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 48 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 93 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 93 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 93 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 93 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 62 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 24 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 24 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 86 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 86 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 86 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 86 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2205000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2205000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 873500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 873500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 3078500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 3078500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 3078500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 3078500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.091445 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.091445 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081633 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.081633 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.088477 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.088477 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.088477 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.088477 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35564.516129 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 35564.516129 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36395.833333 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36395.833333 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35796.511628 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 35796.511628 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 35796.511628 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 35796.511628 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 122.732805 # Cycle average of tags in use
system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 251 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::cpu.inst 93.626172 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 29.106633 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::cpu.inst 0.002857 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.000888 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.003746 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_misses::cpu.inst 189 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 62 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 251 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 24 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 24 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 189 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 86 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 275 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 189 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 86 # number of overall misses
system.cpu.l2cache.overall_misses::total 275 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 6484000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2135500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 8619500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 832000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 832000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 6484000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 2967500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 9451500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 6484000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 2967500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 9451500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 189 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 62 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 251 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 24 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 24 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 189 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 86 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 275 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 189 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 86 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 275 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 1 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34306.878307 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34443.548387 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 34340.637450 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34666.666667 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34666.666667 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34306.878307 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34505.813953 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 34369.090909 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34306.878307 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34505.813953 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 34369.090909 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 189 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 62 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 251 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 24 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 24 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 189 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 86 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 275 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 189 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 86 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 275 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 5881500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1936500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 7818000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 757500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 757500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 5881500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 2694000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 8575500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 5881500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2694000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 8575500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31119.047619 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31233.870968 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31147.410359 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31562.500000 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31562.500000 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31119.047619 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31325.581395 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31183.636364 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31119.047619 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31325.581395 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31183.636364 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

117
simulators/gem5/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/config.ini Normal file
View File

@ -0,0 +1,117 @@
[root]
type=Root
children=system
full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
boot_osflags=a
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
readfile=
symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.cpu]
type=AtomicSimpleCPU
children=dtb interrupts itb tracer workload
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
fastmem=false
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
phase=0
profile=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
system=system
tracer=system.cpu.tracer
width=1
workload=system.cpu.workload
dcache_port=system.membus.slave[2]
icache_port=system.membus.slave[1]
[system.cpu.dtb]
type=AlphaTLB
size=64
[system.cpu.interrupts]
type=AlphaInterrupts
[system.cpu.itb]
type=AlphaTLB
size=48
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=hello
cwd=
egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello
gid=100
input=cin
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=0
system=system
uid=100
[system.membus]
type=CoherentBus
block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
master=system.physmem.port[0]
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
[system.physmem]
type=SimpleMemory
conf_table_reported=false
file=
in_addr_map=true
latency=30000
latency_var=0
null=false
range=0:134217727
zero=false
port=system.membus.master[0]

4
simulators/gem5/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/simerr Executable file
View File

@ -0,0 +1,4 @@
warn: CoherentBus system.membus has no snooping ports attached!
warn: Sockets disabled, not accepting gdb connections
warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
hack: be nice to actually delete the event here

12
simulators/gem5/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/simout Executable file
View File

@ -0,0 +1,12 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 4 2012 11:50:11
gem5 started Jun 4 2012 14:15:42
gem5 executing on zizzer
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello world!
Exiting @ tick 1297500 because target called exit()

92
simulators/gem5/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/stats.txt Normal file
View File

@ -0,0 +1,92 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000001 # Number of seconds simulated
sim_ticks 1297500 # Number of ticks simulated
final_tick 1297500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 760610 # Simulator instruction rate (inst/s)
host_op_rate 756680 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 379104629 # Simulator tick rate (ticks/s)
host_mem_usage 204432 # Number of bytes of host memory used
host_seconds 0.00 # Real time elapsed on the host
sim_insts 2577 # Number of instructions simulated
sim_ops 2577 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 10340 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 3016 # Number of bytes read from this memory
system.physmem.bytes_read::total 13356 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 10340 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 10340 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 2058 # Number of bytes written to this memory
system.physmem.bytes_written::total 2058 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 2585 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 415 # Number of read requests responded to by this memory
system.physmem.num_reads::total 3000 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 294 # Number of write requests responded to by this memory
system.physmem.num_writes::total 294 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 7969171484 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 2324470135 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 10293641618 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 7969171484 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 7969171484 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 1586127168 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 1586127168 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 7969171484 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 3910597303 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 11879768786 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 415 # DTB read hits
system.cpu.dtb.read_misses 4 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 419 # DTB read accesses
system.cpu.dtb.write_hits 294 # DTB write hits
system.cpu.dtb.write_misses 4 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 298 # DTB write accesses
system.cpu.dtb.data_hits 709 # DTB hits
system.cpu.dtb.data_misses 8 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 717 # DTB accesses
system.cpu.itb.fetch_hits 2585 # ITB hits
system.cpu.itb.fetch_misses 11 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 2596 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 4 # Number of system calls
system.cpu.numCycles 2596 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 2577 # Number of instructions committed
system.cpu.committedOps 2577 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses
system.cpu.num_func_calls 140 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 238 # number of instructions that are conditional controls
system.cpu.num_int_insts 2375 # number of integer instructions
system.cpu.num_fp_insts 6 # number of float instructions
system.cpu.num_int_register_reads 2998 # number of times the integer registers were read
system.cpu.num_int_register_writes 1768 # number of times the integer registers were written
system.cpu.num_fp_register_reads 6 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_mem_refs 717 # number of memory refs
system.cpu.num_load_insts 419 # Number of load instructions
system.cpu.num_store_insts 298 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 2596 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
---------- End Simulation Statistics ----------

343
simulators/gem5/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini Normal file
View File

@ -0,0 +1,343 @@
[root]
type=Root
children=system
full_system=false
time_sync_enable=false
time_sync_period=100000000
time_sync_spin_threshold=100000
[system]
type=System
children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby sys_port_proxy
boot_osflags=a
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=timing
memories=system.physmem
num_work_ids=16
readfile=
symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.sys_port_proxy.slave[0]
[system.cpu]
type=TimingSimpleCPU
children=dtb interrupts itb tracer workload
checker=Null
clock=1
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
phase=0
profile=0
progress_interval=0
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
dcache_port=system.l1_cntrl0.sequencer.slave[1]
icache_port=system.l1_cntrl0.sequencer.slave[0]
[system.cpu.dtb]
type=AlphaTLB
size=64
[system.cpu.interrupts]
type=AlphaInterrupts
[system.cpu.itb]
type=AlphaTLB
size=48
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=hello
cwd=
egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello
gid=100
input=cin
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=0
system=system
uid=100
[system.dir_cntrl0]
type=Directory_Controller
children=directory memBuffer
buffer_size=0
cntrl_id=2
directory=system.dir_cntrl0.directory
directory_latency=6
memBuffer=system.dir_cntrl0.memBuffer
number_of_TBEs=256
recycle_latency=10
ruby_system=system.ruby
to_mem_ctrl_latency=1
transitions_per_cycle=32
version=0
[system.dir_cntrl0.directory]
type=RubyDirectoryMemory
map_levels=4
numa_high_bit=6
size=134217728
use_map=false
version=0
[system.dir_cntrl0.memBuffer]
type=RubyMemoryControl
bank_bit_0=8
bank_busy_time=11
bank_queue_size=12
banks_per_rank=8
basic_bus_busy_time=2
dimm_bit_0=12
dimms_per_channel=2
mem_bus_cycle_multiplier=10
mem_ctl_latency=12
mem_fixed_delay=0
mem_random_arbitrate=0
rank_bit_0=11
rank_rank_delay=1
ranks_per_dimm=2
read_write_delay=2
refresh_period=1560
tFaw=0
version=0
[system.l1_cntrl0]
type=L1Cache_Controller
children=L1DcacheMemory L1IcacheMemory sequencer
L1DcacheMemory=system.l1_cntrl0.L1DcacheMemory
L1IcacheMemory=system.l1_cntrl0.L1IcacheMemory
buffer_size=0
cntrl_id=0
l1_request_latency=2
l1_response_latency=2
l2_select_num_bits=0
number_of_TBEs=256
recycle_latency=10
ruby_system=system.ruby
send_evictions=false
sequencer=system.l1_cntrl0.sequencer
to_l2_latency=1
transitions_per_cycle=32
version=0
[system.l1_cntrl0.L1DcacheMemory]
type=RubyCache
assoc=2
is_icache=false
latency=3
replacement_policy=PSEUDO_LRU
size=256
start_index_bit=6
[system.l1_cntrl0.L1IcacheMemory]
type=RubyCache
assoc=2
is_icache=false
latency=3
replacement_policy=PSEUDO_LRU
size=256
start_index_bit=6
[system.l1_cntrl0.sequencer]
type=RubySequencer
access_phys_mem=true
dcache=system.l1_cntrl0.L1DcacheMemory
deadlock_threshold=500000
icache=system.l1_cntrl0.L1IcacheMemory
max_outstanding_requests=16
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
system=system
using_network_tester=false
using_ruby_tester=false
version=0
slave=system.cpu.icache_port system.cpu.dcache_port
[system.l2_cntrl0]
type=L2Cache_Controller
children=L2cacheMemory
L2cacheMemory=system.l2_cntrl0.L2cacheMemory
buffer_size=0
cntrl_id=1
l2_request_latency=2
l2_response_latency=2
number_of_TBEs=256
recycle_latency=10
ruby_system=system.ruby
to_l1_latency=1
transitions_per_cycle=32
version=0
[system.l2_cntrl0.L2cacheMemory]
type=RubyCache
assoc=2
is_icache=false
latency=15
replacement_policy=PSEUDO_LRU
size=512
start_index_bit=6
[system.physmem]
type=SimpleMemory
conf_table_reported=false
file=
in_addr_map=true
latency=30
latency_var=0
null=false
range=0:134217727
zero=false
[system.ruby]
type=RubySystem
children=network profiler
block_size_bytes=64
clock=1
mem_size=134217728
no_mem_vec=false
random_seed=1234
randomization=false
stats_filename=ruby.stats
[system.ruby.network]
type=SimpleNetwork
children=topology
adaptive_routing=false
buffer_size=0
control_msg_size=8
endpoint_bandwidth=1000
number_of_virtual_networks=10
ruby_system=system.ruby
topology=system.ruby.network.topology
[system.ruby.network.topology]
type=Topology
children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2 routers0 routers1 routers2 routers3
description=Crossbar
ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2
int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2
print_config=false
routers=system.ruby.network.topology.routers0 system.ruby.network.topology.routers1 system.ruby.network.topology.routers2 system.ruby.network.topology.routers3
[system.ruby.network.topology.ext_links0]
type=SimpleExtLink
bandwidth_factor=16
ext_node=system.l1_cntrl0
int_node=system.ruby.network.topology.routers0
latency=1
link_id=0
weight=1
[system.ruby.network.topology.ext_links1]
type=SimpleExtLink
bandwidth_factor=16
ext_node=system.l2_cntrl0
int_node=system.ruby.network.topology.routers1
latency=1
link_id=1
weight=1
[system.ruby.network.topology.ext_links2]
type=SimpleExtLink
bandwidth_factor=16
ext_node=system.dir_cntrl0
int_node=system.ruby.network.topology.routers2
latency=1
link_id=2
weight=1
[system.ruby.network.topology.int_links0]
type=SimpleIntLink
bandwidth_factor=16
latency=1
link_id=3
node_a=system.ruby.network.topology.routers0
node_b=system.ruby.network.topology.routers3
weight=1
[system.ruby.network.topology.int_links1]
type=SimpleIntLink
bandwidth_factor=16
latency=1
link_id=4
node_a=system.ruby.network.topology.routers1
node_b=system.ruby.network.topology.routers3
weight=1
[system.ruby.network.topology.int_links2]
type=SimpleIntLink
bandwidth_factor=16
latency=1
link_id=5
node_a=system.ruby.network.topology.routers2
node_b=system.ruby.network.topology.routers3
weight=1
[system.ruby.network.topology.routers0]
type=BasicRouter
router_id=0
[system.ruby.network.topology.routers1]
type=BasicRouter
router_id=1
[system.ruby.network.topology.routers2]
type=BasicRouter
router_id=2
[system.ruby.network.topology.routers3]
type=BasicRouter
router_id=3
[system.ruby.profiler]
type=RubyProfiler
all_instructions=false
hot_lines=false
num_of_sequencers=1
ruby_system=system.ruby
[system.sys_port_proxy]
type=RubyPortProxy
access_phys_mem=true
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
system=system
using_network_tester=false
using_ruby_tester=false
version=0
slave=system.system_port

636
simulators/gem5/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats Normal file
View File

@ -0,0 +1,636 @@
================ Begin RubySystem Configuration Print ================
RubySystem config:
random_seed: 1234
randomization: 0
cycle_period: 1
block_size_bytes: 64
block_size_bits: 6
memory_size_bytes: 134217728
memory_size_bits: 27
Network Configuration
---------------------
network: SIMPLE_NETWORK
topology:
virtual_net_0: active, unordered
virtual_net_1: active, unordered
virtual_net_2: active, unordered
virtual_net_3: inactive
virtual_net_4: inactive
virtual_net_5: inactive
virtual_net_6: inactive
virtual_net_7: inactive
virtual_net_8: inactive
virtual_net_9: inactive
Profiler Configuration
----------------------
periodic_stats_period: 1000000
================ End RubySystem Configuration Print ================
Real time: Jun/04/2012 13:42:36
Profiler Stats
--------------
Elapsed_time_in_seconds: 1
Elapsed_time_in_minutes: 0.0166667
Elapsed_time_in_hours: 0.000277778
Elapsed_time_in_days: 1.15741e-05
Virtual_time_in_seconds: 0.31
Virtual_time_in_minutes: 0.00516667
Virtual_time_in_hours: 8.61111e-05
Virtual_time_in_days: 3.58796e-06
Ruby_current_time: 104867
Ruby_start_time: 0
Ruby_cycles: 104867
mbytes_resident: 46.8984
mbytes_total: 218.785
resident_ratio: 0.214358
ruby_cycles_executed: [ 104868 ]
Busy Controller Counts:
L1Cache-0:0
L2Cache-0:0
Directory-0:0
Busy Bank Count:0
sequencer_requests_outstanding: [binsize: 1 max: 1 count: 3295 average: 1 | standard deviation: 0 | 0 3295 ]
All Non-Zero Cycle Demand Cache Accesses
----------------------------------------
miss_latency: [binsize: 2 max: 275 count: 3294 average: 30.8358 | standard deviation: 62.2139 | 0 2722 0 0 0 0 0 0 0 23 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 62 131 87 117 74 6 17 4 2 2 1 11 10 5 4 3 5 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
miss_latency_LD: [binsize: 2 max: 235 count: 415 average: 80.7349 | standard deviation: 83.1868 | 0 211 0 0 0 0 0 0 0 11 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 24 46 24 49 14 4 7 4 1 1 0 5 0 4 0 3 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
miss_latency_ST: [binsize: 2 max: 275 count: 294 average: 39.8435 | standard deviation: 69.7713 | 0 226 0 0 0 0 0 0 0 3 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 19 3 12 8 0 8 0 0 0 0 1 1 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
miss_latency_IFETCH: [binsize: 2 max: 267 count: 2585 average: 21.8004 | standard deviation: 52.7361 | 0 2285 0 0 0 0 0 0 0 9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 30 66 60 56 52 2 2 0 1 1 1 5 9 1 1 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
miss_latency_NULL: [binsize: 2 max: 275 count: 3294 average: 30.8358 | standard deviation: 62.2139 | 0 2722 0 0 0 0 0 0 0 23 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 62 131 87 117 74 6 17 4 2 2 1 11 10 5 4 3 5 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
imcomplete_wCC_Times: 0
miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
imcomplete_dir_Times: 0
miss_latency_LD_NULL: [binsize: 2 max: 235 count: 415 average: 80.7349 | standard deviation: 83.1868 | 0 211 0 0 0 0 0 0 0 11 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 24 46 24 49 14 4 7 4 1 1 0 5 0 4 0 3 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
miss_latency_ST_NULL: [binsize: 2 max: 275 count: 294 average: 39.8435 | standard deviation: 69.7713 | 0 226 0 0 0 0 0 0 0 3 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 19 3 12 8 0 8 0 0 0 0 1 1 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
miss_latency_IFETCH_NULL: [binsize: 2 max: 267 count: 2585 average: 21.8004 | standard deviation: 52.7361 | 0 2285 0 0 0 0 0 0 0 9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 30 66 60 56 52 2 2 0 1 1 1 5 9 1 1 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
All Non-Zero Cycle SW Prefetch Requests
------------------------------------
prefetch_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
prefetch_latency_L2Miss:[binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
Request vs. RubySystem State Profile
--------------------------------
filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
Message Delayed Cycles
----------------------
Total_delay_cycles: [binsize: 1 max: 18 count: 3612 average: 0.0625692 | standard deviation: 0.620431 | 3562 0 1 0 47 0 0 0 0 0 0 0 0 0 0 0 0 0 2 ]
Total_nonPF_delay_cycles: [binsize: 1 max: 2 count: 2644 average: 0.00075643 | standard deviation: 0.0389028 | 2643 0 1 ]
virtual_network_0_delay_cycles: [binsize: 1 max: 18 count: 968 average: 0.231405 | standard deviation: 1.18112 | 919 0 0 0 47 0 0 0 0 0 0 0 0 0 0 0 0 0 2 ]
virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 431 average: 0 | standard deviation: 0 | 431 ]
virtual_network_3_delay_cycles: [binsize: 1 max: 2 count: 2213 average: 0.000903751 | standard deviation: 0.0425243 | 2212 0 1 ]
virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
virtual_network_6_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
virtual_network_7_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
virtual_network_8_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
virtual_network_9_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
Resource Usage
--------------
page_size: 4096
user_time: 0
system_time: 0
page_reclaims: 12410
page_faults: 4
swaps: 0
block_inputs: 480
block_outputs: 96
Network Stats
-------------
total_msg_count_Control: 3357 26856
total_msg_count_Request_Control: 1293 10344
total_msg_count_Response_Data: 3666 263952
total_msg_count_Response_Control: 5220 41760
total_msg_count_Writeback_Data: 327 23544
total_msg_count_Writeback_Control: 231 1848
total_msgs: 14094 total_bytes: 368304
switch_0_inlinks: 2
switch_0_outlinks: 2
links_utilized_percent_switch_0: 1.90098
links_utilized_percent_switch_0_link_0: 2.71916 bw: 16000 base_latency: 1
links_utilized_percent_switch_0_link_1: 1.0828 bw: 16000 base_latency: 1
outgoing_messages_switch_0_link_0_Request_Control: 431 3448 [ 431 0 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_0_link_0_Response_Data: 572 41184 [ 0 572 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_0_link_0_Response_Control: 124 992 [ 0 124 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_0_link_1_Control: 572 4576 [ 572 0 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_0_link_1_Response_Control: 641 5128 [ 0 369 272 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_0_link_1_Writeback_Data: 109 7848 [ 47 62 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_0_link_1_Writeback_Control: 77 616 [ 77 0 0 0 0 0 0 0 0 0 ] base_latency: 1
switch_1_inlinks: 2
switch_1_outlinks: 2
links_utilized_percent_switch_1: 3.65844
links_utilized_percent_switch_1_link_0: 3.68705 bw: 16000 base_latency: 1
links_utilized_percent_switch_1_link_1: 3.62984 bw: 16000 base_latency: 1
outgoing_messages_switch_1_link_0_Control: 572 4576 [ 572 0 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_1_link_0_Response_Data: 547 39384 [ 0 547 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_1_link_0_Response_Control: 1180 9440 [ 0 908 272 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_1_link_0_Writeback_Data: 109 7848 [ 47 62 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_1_link_0_Writeback_Control: 77 616 [ 77 0 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_1_link_1_Control: 547 4376 [ 547 0 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_1_link_1_Request_Control: 431 3448 [ 431 0 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_1_link_1_Response_Data: 675 48600 [ 0 675 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_1_link_1_Response_Control: 560 4480 [ 0 560 0 0 0 0 0 0 0 0 ] base_latency: 1
switch_2_inlinks: 2
switch_2_outlinks: 2
links_utilized_percent_switch_2: 1.75746
links_utilized_percent_switch_2_link_0: 0.910677 bw: 16000 base_latency: 1
links_utilized_percent_switch_2_link_1: 2.60425 bw: 16000 base_latency: 1
outgoing_messages_switch_2_link_0_Control: 547 4376 [ 547 0 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_2_link_0_Response_Data: 103 7416 [ 0 103 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_2_link_0_Response_Control: 436 3488 [ 0 436 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_2_link_1_Response_Data: 547 39384 [ 0 547 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_2_link_1_Response_Control: 539 4312 [ 0 539 0 0 0 0 0 0 0 0 ] base_latency: 1
switch_3_inlinks: 3
switch_3_outlinks: 3
links_utilized_percent_switch_3: 2.43896
links_utilized_percent_switch_3_link_0: 2.71916 bw: 16000 base_latency: 1
links_utilized_percent_switch_3_link_1: 3.68705 bw: 16000 base_latency: 1
links_utilized_percent_switch_3_link_2: 0.910677 bw: 16000 base_latency: 1
outgoing_messages_switch_3_link_0_Request_Control: 431 3448 [ 431 0 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_3_link_0_Response_Data: 572 41184 [ 0 572 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_3_link_0_Response_Control: 124 992 [ 0 124 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_3_link_1_Control: 572 4576 [ 572 0 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_3_link_1_Response_Data: 547 39384 [ 0 547 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_3_link_1_Response_Control: 1180 9440 [ 0 908 272 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_3_link_1_Writeback_Data: 109 7848 [ 47 62 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_3_link_1_Writeback_Control: 77 616 [ 77 0 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_3_link_2_Control: 547 4376 [ 547 0 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_3_link_2_Response_Data: 103 7416 [ 0 103 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_3_link_2_Response_Control: 436 3488 [ 0 436 0 0 0 0 0 0 0 0 ] base_latency: 1
Cache Stats: system.l1_cntrl0.L1IcacheMemory
system.l1_cntrl0.L1IcacheMemory_total_misses: 300
system.l1_cntrl0.L1IcacheMemory_total_demand_misses: 300
system.l1_cntrl0.L1IcacheMemory_total_prefetches: 0
system.l1_cntrl0.L1IcacheMemory_total_sw_prefetches: 0
system.l1_cntrl0.L1IcacheMemory_total_hw_prefetches: 0
system.l1_cntrl0.L1IcacheMemory_request_type_IFETCH: 100%
system.l1_cntrl0.L1IcacheMemory_access_mode_type_Supervisor: 300 100%
Cache Stats: system.l1_cntrl0.L1DcacheMemory
system.l1_cntrl0.L1DcacheMemory_total_misses: 272
system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 272
system.l1_cntrl0.L1DcacheMemory_total_prefetches: 0
system.l1_cntrl0.L1DcacheMemory_total_sw_prefetches: 0
system.l1_cntrl0.L1DcacheMemory_total_hw_prefetches: 0
system.l1_cntrl0.L1DcacheMemory_request_type_LD: 75%
system.l1_cntrl0.L1DcacheMemory_request_type_ST: 25%
system.l1_cntrl0.L1DcacheMemory_access_mode_type_Supervisor: 272 100%
--- L1Cache ---
- Event Counts -
Load [415 ] 415
Ifetch [2585 ] 2585
Store [294 ] 294
Inv [431 ] 431
L1_Replacement [502 ] 502
Fwd_GETX [0 ] 0
Fwd_GETS [0 ] 0
Fwd_GET_INSTR [0 ] 0
Data [0 ] 0
Data_Exclusive [204 ] 204
DataS_fromL1 [0 ] 0
Data_all_Acks [368 ] 368
Ack [0 ] 0
Ack_all [0 ] 0
WB_Ack [124 ] 124
- Transitions -
NP Load [182 ] 182
NP Ifetch [270 ] 270
NP Store [58 ] 58
NP Inv [162 ] 162
NP L1_Replacement [0 ] 0
I Load [22 ] 22
I Ifetch [30 ] 30
I Store [10 ] 10
I Inv [0 ] 0
I L1_Replacement [206 ] 206
S Load [0 ] 0
S Ifetch [2285 ] 2285
S Store [0 ] 0
S Inv [124 ] 124
S L1_Replacement [172 ] 172
E Load [140 ] 140
E Ifetch [0 ] 0
E Store [41 ] 41
E Inv [83 ] 83
E L1_Replacement [79 ] 79
E Fwd_GETX [0 ] 0
E Fwd_GETS [0 ] 0
E Fwd_GET_INSTR [0 ] 0
M Load [71 ] 71
M Ifetch [0 ] 0
M Store [185 ] 185
M Inv [62 ] 62
M L1_Replacement [45 ] 45
M Fwd_GETX [0 ] 0
M Fwd_GETS [0 ] 0
M Fwd_GET_INSTR [0 ] 0
IS Load [0 ] 0
IS Ifetch [0 ] 0
IS Store [0 ] 0
IS Inv [0 ] 0
IS L1_Replacement [0 ] 0
IS Data_Exclusive [204 ] 204
IS DataS_fromL1 [0 ] 0
IS Data_all_Acks [300 ] 300
IM Load [0 ] 0
IM Ifetch [0 ] 0
IM Store [0 ] 0
IM Inv [0 ] 0
IM L1_Replacement [0 ] 0
IM Data [0 ] 0
IM Data_all_Acks [68 ] 68
IM Ack [0 ] 0
SM Load [0 ] 0
SM Ifetch [0 ] 0
SM Store [0 ] 0
SM Inv [0 ] 0
SM L1_Replacement [0 ] 0
SM Ack [0 ] 0
SM Ack_all [0 ] 0
IS_I Load [0 ] 0
IS_I Ifetch [0 ] 0
IS_I Store [0 ] 0
IS_I Inv [0 ] 0
IS_I L1_Replacement [0 ] 0
IS_I Data_Exclusive [0 ] 0
IS_I DataS_fromL1 [0 ] 0
IS_I Data_all_Acks [0 ] 0
M_I Load [0 ] 0
M_I Ifetch [0 ] 0
M_I Store [0 ] 0
M_I Inv [0 ] 0
M_I L1_Replacement [0 ] 0
M_I Fwd_GETX [0 ] 0
M_I Fwd_GETS [0 ] 0
M_I Fwd_GET_INSTR [0 ] 0
M_I WB_Ack [124 ] 124
SINK_WB_ACK Load [0 ] 0
SINK_WB_ACK Ifetch [0 ] 0
SINK_WB_ACK Store [0 ] 0
SINK_WB_ACK Inv [0 ] 0
SINK_WB_ACK L1_Replacement [0 ] 0
SINK_WB_ACK WB_Ack [0 ] 0
Cache Stats: system.l2_cntrl0.L2cacheMemory
system.l2_cntrl0.L2cacheMemory_total_misses: 547
system.l2_cntrl0.L2cacheMemory_total_demand_misses: 547
system.l2_cntrl0.L2cacheMemory_total_prefetches: 0
system.l2_cntrl0.L2cacheMemory_total_sw_prefetches: 0
system.l2_cntrl0.L2cacheMemory_total_hw_prefetches: 0
system.l2_cntrl0.L2cacheMemory_request_type_GETS: 35.1005%
system.l2_cntrl0.L2cacheMemory_request_type_GET_INSTR: 53.1993%
system.l2_cntrl0.L2cacheMemory_request_type_GETX: 11.7002%
system.l2_cntrl0.L2cacheMemory_access_mode_type_Supervisor: 547 100%
--- L2Cache ---
- Event Counts -
L1_GET_INSTR [300 ] 300
L1_GETS [205 ] 205
L1_GETX [69 ] 69
L1_UPGRADE [0 ] 0
L1_PUTX [124 ] 124
L1_PUTX_old [0 ] 0
Fwd_L1_GETX [0 ] 0
Fwd_L1_GETS [0 ] 0
Fwd_L1_GET_INSTR [0 ] 0
L2_Replacement [43 ] 43
L2_Replacement_clean [496 ] 496
Mem_Data [547 ] 547
Mem_Ack [539 ] 539
WB_Data [62 ] 62
WB_Data_clean [0 ] 0
Ack [0 ] 0
Ack_all [369 ] 369
Unblock [0 ] 0
Unblock_Cancel [0 ] 0
Exclusive_Unblock [272 ] 272
MEM_Inv [0 ] 0
- Transitions -
NP L1_GET_INSTR [291 ] 291
NP L1_GETS [192 ] 192
NP L1_GETX [64 ] 64
NP L1_PUTX [0 ] 0
NP L1_PUTX_old [0 ] 0
SS L1_GET_INSTR [9 ] 9
SS L1_GETS [0 ] 0
SS L1_GETX [0 ] 0
SS L1_UPGRADE [0 ] 0
SS L1_PUTX [0 ] 0
SS L1_PUTX_old [0 ] 0
SS L2_Replacement [0 ] 0
SS L2_Replacement_clean [286 ] 286
SS MEM_Inv [0 ] 0
M L1_GET_INSTR [0 ] 0
M L1_GETS [12 ] 12
M L1_GETX [4 ] 4
M L1_PUTX [0 ] 0
M L1_PUTX_old [0 ] 0
M L2_Replacement [39 ] 39
M L2_Replacement_clean [69 ] 69
M MEM_Inv [0 ] 0
MT L1_GET_INSTR [0 ] 0
MT L1_GETS [0 ] 0
MT L1_GETX [0 ] 0
MT L1_PUTX [124 ] 124
MT L1_PUTX_old [0 ] 0
MT L2_Replacement [4 ] 4
MT L2_Replacement_clean [141 ] 141
MT MEM_Inv [0 ] 0
M_I L1_GET_INSTR [0 ] 0
M_I L1_GETS [1 ] 1
M_I L1_GETX [1 ] 1
M_I L1_UPGRADE [0 ] 0
M_I L1_PUTX [0 ] 0
M_I L1_PUTX_old [0 ] 0
M_I Mem_Ack [539 ] 539
M_I MEM_Inv [0 ] 0
MT_I L1_GET_INSTR [0 ] 0
MT_I L1_GETS [0 ] 0
MT_I L1_GETX [0 ] 0
MT_I L1_UPGRADE [0 ] 0
MT_I L1_PUTX [0 ] 0
MT_I L1_PUTX_old [0 ] 0
MT_I WB_Data [2 ] 2
MT_I WB_Data_clean [0 ] 0
MT_I Ack_all [2 ] 2
MT_I MEM_Inv [0 ] 0
MCT_I L1_GET_INSTR [0 ] 0
MCT_I L1_GETS [0 ] 0
MCT_I L1_GETX [0 ] 0
MCT_I L1_UPGRADE [0 ] 0
MCT_I L1_PUTX [0 ] 0
MCT_I L1_PUTX_old [0 ] 0
MCT_I WB_Data [60 ] 60
MCT_I WB_Data_clean [0 ] 0
MCT_I Ack_all [81 ] 81
I_I L1_GET_INSTR [0 ] 0
I_I L1_GETS [0 ] 0
I_I L1_GETX [0 ] 0
I_I L1_UPGRADE [0 ] 0
I_I L1_PUTX [0 ] 0
I_I L1_PUTX_old [0 ] 0
I_I Ack [0 ] 0
I_I Ack_all [286 ] 286
S_I L1_GET_INSTR [0 ] 0
S_I L1_GETS [0 ] 0
S_I L1_GETX [0 ] 0
S_I L1_UPGRADE [0 ] 0
S_I L1_PUTX [0 ] 0
S_I L1_PUTX_old [0 ] 0
S_I Ack [0 ] 0
S_I Ack_all [0 ] 0
S_I MEM_Inv [0 ] 0
ISS L1_GET_INSTR [0 ] 0
ISS L1_GETS [0 ] 0
ISS L1_GETX [0 ] 0
ISS L1_PUTX [0 ] 0
ISS L1_PUTX_old [0 ] 0
ISS L2_Replacement [0 ] 0
ISS L2_Replacement_clean [0 ] 0
ISS Mem_Data [192 ] 192
ISS MEM_Inv [0 ] 0
IS L1_GET_INSTR [0 ] 0
IS L1_GETS [0 ] 0
IS L1_GETX [0 ] 0
IS L1_PUTX [0 ] 0
IS L1_PUTX_old [0 ] 0
IS L2_Replacement [0 ] 0
IS L2_Replacement_clean [0 ] 0
IS Mem_Data [291 ] 291
IS MEM_Inv [0 ] 0
IM L1_GET_INSTR [0 ] 0
IM L1_GETS [0 ] 0
IM L1_GETX [0 ] 0
IM L1_PUTX [0 ] 0
IM L1_PUTX_old [0 ] 0
IM L2_Replacement [0 ] 0
IM L2_Replacement_clean [0 ] 0
IM Mem_Data [64 ] 64
IM MEM_Inv [0 ] 0
SS_MB L1_GET_INSTR [0 ] 0
SS_MB L1_GETS [0 ] 0
SS_MB L1_GETX [0 ] 0
SS_MB L1_UPGRADE [0 ] 0
SS_MB L1_PUTX [0 ] 0
SS_MB L1_PUTX_old [0 ] 0
SS_MB L2_Replacement [0 ] 0
SS_MB L2_Replacement_clean [0 ] 0
SS_MB Unblock_Cancel [0 ] 0
SS_MB Exclusive_Unblock [0 ] 0
SS_MB MEM_Inv [0 ] 0
MT_MB L1_GET_INSTR [0 ] 0
MT_MB L1_GETS [0 ] 0
MT_MB L1_GETX [0 ] 0
MT_MB L1_UPGRADE [0 ] 0
MT_MB L1_PUTX [0 ] 0
MT_MB L1_PUTX_old [0 ] 0
MT_MB L2_Replacement [0 ] 0
MT_MB L2_Replacement_clean [0 ] 0
MT_MB Unblock_Cancel [0 ] 0
MT_MB Exclusive_Unblock [272 ] 272
MT_MB MEM_Inv [0 ] 0
M_MB L1_GET_INSTR [0 ] 0
M_MB L1_GETS [0 ] 0
M_MB L1_GETX [0 ] 0
M_MB L1_UPGRADE [0 ] 0
M_MB L1_PUTX [0 ] 0
M_MB L1_PUTX_old [0 ] 0
M_MB L2_Replacement [0 ] 0
M_MB L2_Replacement_clean [0 ] 0
M_MB Exclusive_Unblock [0 ] 0
M_MB MEM_Inv [0 ] 0
MT_IIB L1_GET_INSTR [0 ] 0
MT_IIB L1_GETS [0 ] 0
MT_IIB L1_GETX [0 ] 0
MT_IIB L1_UPGRADE [0 ] 0
MT_IIB L1_PUTX [0 ] 0
MT_IIB L1_PUTX_old [0 ] 0
MT_IIB L2_Replacement [0 ] 0
MT_IIB L2_Replacement_clean [0 ] 0
MT_IIB WB_Data [0 ] 0
MT_IIB WB_Data_clean [0 ] 0
MT_IIB Unblock [0 ] 0
MT_IIB MEM_Inv [0 ] 0
MT_IB L1_GET_INSTR [0 ] 0
MT_IB L1_GETS [0 ] 0
MT_IB L1_GETX [0 ] 0
MT_IB L1_UPGRADE [0 ] 0
MT_IB L1_PUTX [0 ] 0
MT_IB L1_PUTX_old [0 ] 0
MT_IB L2_Replacement [0 ] 0
MT_IB L2_Replacement_clean [0 ] 0
MT_IB WB_Data [0 ] 0
MT_IB WB_Data_clean [0 ] 0
MT_IB Unblock_Cancel [0 ] 0
MT_IB MEM_Inv [0 ] 0
MT_SB L1_GET_INSTR [0 ] 0
MT_SB L1_GETS [0 ] 0
MT_SB L1_GETX [0 ] 0
MT_SB L1_UPGRADE [0 ] 0
MT_SB L1_PUTX [0 ] 0
MT_SB L1_PUTX_old [0 ] 0
MT_SB L2_Replacement [0 ] 0
MT_SB L2_Replacement_clean [0 ] 0
MT_SB Unblock [0 ] 0
MT_SB MEM_Inv [0 ] 0
Memory controller: system.dir_cntrl0.memBuffer:
memory_total_requests: 650
memory_reads: 547
memory_writes: 103
memory_refreshes: 219
memory_total_request_delays: 306
memory_delays_per_request: 0.470769
memory_delays_in_input_queue: 27
memory_delays_behind_head_of_bank_queue: 0
memory_delays_stalled_at_head_of_bank_queue: 279
memory_stalls_for_bank_busy: 56
memory_stalls_for_random_busy: 0
memory_stalls_for_anti_starvation: 0
memory_stalls_for_arbitration: 9
memory_stalls_for_bus: 94
memory_stalls_for_tfaw: 0
memory_stalls_for_read_write_turnaround: 120
memory_stalls_for_read_read_turnaround: 0
accesses_per_bank: 26 14 0 49 21 21 42 25 6 4 7 4 24 42 26 3 5 7 7 18 10 29 15 50 19 5 6 16 14 24 19 92
--- Directory ---
- Event Counts -
Fetch [547 ] 547
Data [103 ] 103
Memory_Data [547 ] 547
Memory_Ack [103 ] 103
DMA_READ [0 ] 0
DMA_WRITE [0 ] 0
CleanReplacement [436 ] 436
- Transitions -
I Fetch [547 ] 547
I DMA_READ [0 ] 0
I DMA_WRITE [0 ] 0
ID Fetch [0 ] 0
ID Data [0 ] 0
ID Memory_Data [0 ] 0
ID DMA_READ [0 ] 0
ID DMA_WRITE [0 ] 0
ID_W Fetch [0 ] 0
ID_W Data [0 ] 0
ID_W Memory_Ack [0 ] 0
ID_W DMA_READ [0 ] 0
ID_W DMA_WRITE [0 ] 0
M Data [103 ] 103
M DMA_READ [0 ] 0
M DMA_WRITE [0 ] 0
M CleanReplacement [436 ] 436
IM Fetch [0 ] 0
IM Data [0 ] 0
IM Memory_Data [547 ] 547
IM DMA_READ [0 ] 0
IM DMA_WRITE [0 ] 0
MI Fetch [0 ] 0
MI Data [0 ] 0
MI Memory_Ack [103 ] 103
MI DMA_READ [0 ] 0
MI DMA_WRITE [0 ] 0
M_DRD Data [0 ] 0
M_DRD DMA_READ [0 ] 0
M_DRD DMA_WRITE [0 ] 0
M_DRDI Fetch [0 ] 0
M_DRDI Data [0 ] 0
M_DRDI Memory_Ack [0 ] 0
M_DRDI DMA_READ [0 ] 0
M_DRDI DMA_WRITE [0 ] 0
M_DWR Data [0 ] 0
M_DWR DMA_READ [0 ] 0
M_DWR DMA_WRITE [0 ] 0
M_DWRI Fetch [0 ] 0
M_DWRI Data [0 ] 0
M_DWRI Memory_Ack [0 ] 0
M_DWRI DMA_READ [0 ] 0
M_DWRI DMA_WRITE [0 ] 0

3
simulators/gem5/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simerr Executable file
View File

@ -0,0 +1,3 @@
warn: Sockets disabled, not accepting gdb connections
warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
hack: be nice to actually delete the event here

12
simulators/gem5/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout Executable file
View File

@ -0,0 +1,12 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 4 2012 11:53:20
gem5 started Jun 4 2012 13:42:35
gem5 executing on zizzer
command line: build/ALPHA_MESI_CMP_directory/gem5.opt -d build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MESI_CMP_directory
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello world!
Exiting @ tick 104867 because target called exit()

92
simulators/gem5/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt Normal file
View File

@ -0,0 +1,92 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000105 # Number of seconds simulated
sim_ticks 104867 # Number of ticks simulated
final_tick 104867 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
host_inst_rate 4864 # Simulator instruction rate (inst/s)
host_op_rate 4864 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 197908 # Simulator tick rate (ticks/s)
host_mem_usage 224040 # Number of bytes of host memory used
host_seconds 0.53 # Real time elapsed on the host
sim_insts 2577 # Number of instructions simulated
sim_ops 2577 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 10340 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 3016 # Number of bytes read from this memory
system.physmem.bytes_read::total 13356 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 10340 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 10340 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 2058 # Number of bytes written to this memory
system.physmem.bytes_written::total 2058 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 2585 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 415 # Number of read requests responded to by this memory
system.physmem.num_reads::total 3000 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 294 # Number of write requests responded to by this memory
system.physmem.num_writes::total 294 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 98601085 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 28760239 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 127361324 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 98601085 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 98601085 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 19624858 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 19624858 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 98601085 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 48385097 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 146986182 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 415 # DTB read hits
system.cpu.dtb.read_misses 4 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 419 # DTB read accesses
system.cpu.dtb.write_hits 294 # DTB write hits
system.cpu.dtb.write_misses 4 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 298 # DTB write accesses
system.cpu.dtb.data_hits 709 # DTB hits
system.cpu.dtb.data_misses 8 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 717 # DTB accesses
system.cpu.itb.fetch_hits 2586 # ITB hits
system.cpu.itb.fetch_misses 11 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 2597 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 4 # Number of system calls
system.cpu.numCycles 104867 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 2577 # Number of instructions committed
system.cpu.committedOps 2577 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses
system.cpu.num_func_calls 140 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 238 # number of instructions that are conditional controls
system.cpu.num_int_insts 2375 # number of integer instructions
system.cpu.num_fp_insts 6 # number of float instructions
system.cpu.num_int_register_reads 2998 # number of times the integer registers were read
system.cpu.num_int_register_writes 1768 # number of times the integer registers were written
system.cpu.num_fp_register_reads 6 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_mem_refs 717 # number of memory refs
system.cpu.num_load_insts 419 # Number of load instructions
system.cpu.num_store_insts 298 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 104867 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
---------- End Simulation Statistics ----------

339
simulators/gem5/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini Normal file
View File

@ -0,0 +1,339 @@
[root]
type=Root
children=system
full_system=false
time_sync_enable=false
time_sync_period=100000000
time_sync_spin_threshold=100000
[system]
type=System
children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby sys_port_proxy
boot_osflags=a
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=timing
memories=system.physmem
num_work_ids=16
readfile=
symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.sys_port_proxy.slave[0]
[system.cpu]
type=TimingSimpleCPU
children=dtb interrupts itb tracer workload
checker=Null
clock=1
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
phase=0
profile=0
progress_interval=0
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
dcache_port=system.l1_cntrl0.sequencer.slave[1]
icache_port=system.l1_cntrl0.sequencer.slave[0]
[system.cpu.dtb]
type=AlphaTLB
size=64
[system.cpu.interrupts]
type=AlphaInterrupts
[system.cpu.itb]
type=AlphaTLB
size=48
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=hello
cwd=
egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello
gid=100
input=cin
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=0
system=system
uid=100
[system.dir_cntrl0]
type=Directory_Controller
children=directory memBuffer
buffer_size=0
cntrl_id=2
directory=system.dir_cntrl0.directory
directory_latency=6
memBuffer=system.dir_cntrl0.memBuffer
number_of_TBEs=256
recycle_latency=10
ruby_system=system.ruby
transitions_per_cycle=32
version=0
[system.dir_cntrl0.directory]
type=RubyDirectoryMemory
map_levels=4
numa_high_bit=6
size=134217728
use_map=false
version=0
[system.dir_cntrl0.memBuffer]
type=RubyMemoryControl
bank_bit_0=8
bank_busy_time=11
bank_queue_size=12
banks_per_rank=8
basic_bus_busy_time=2
dimm_bit_0=12
dimms_per_channel=2
mem_bus_cycle_multiplier=10
mem_ctl_latency=12
mem_fixed_delay=0
mem_random_arbitrate=0
rank_bit_0=11
rank_rank_delay=1
ranks_per_dimm=2
read_write_delay=2
refresh_period=1560
tFaw=0
version=0
[system.l1_cntrl0]
type=L1Cache_Controller
children=L1DcacheMemory L1IcacheMemory sequencer
L1DcacheMemory=system.l1_cntrl0.L1DcacheMemory
L1IcacheMemory=system.l1_cntrl0.L1IcacheMemory
buffer_size=0
cntrl_id=0
l2_select_num_bits=0
number_of_TBEs=256
recycle_latency=10
request_latency=2
ruby_system=system.ruby
send_evictions=false
sequencer=system.l1_cntrl0.sequencer
transitions_per_cycle=32
version=0
[system.l1_cntrl0.L1DcacheMemory]
type=RubyCache
assoc=2
is_icache=false
latency=3
replacement_policy=PSEUDO_LRU
size=256
start_index_bit=6
[system.l1_cntrl0.L1IcacheMemory]
type=RubyCache
assoc=2
is_icache=false
latency=3
replacement_policy=PSEUDO_LRU
size=256
start_index_bit=6
[system.l1_cntrl0.sequencer]
type=RubySequencer
access_phys_mem=true
dcache=system.l1_cntrl0.L1DcacheMemory
deadlock_threshold=500000
icache=system.l1_cntrl0.L1IcacheMemory
max_outstanding_requests=16
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
system=system
using_network_tester=false
using_ruby_tester=false
version=0
slave=system.cpu.icache_port system.cpu.dcache_port
[system.l2_cntrl0]
type=L2Cache_Controller
children=L2cacheMemory
L2cacheMemory=system.l2_cntrl0.L2cacheMemory
buffer_size=0
cntrl_id=1
number_of_TBEs=256
recycle_latency=10
request_latency=2
response_latency=2
ruby_system=system.ruby
transitions_per_cycle=32
version=0
[system.l2_cntrl0.L2cacheMemory]
type=RubyCache
assoc=2
is_icache=false
latency=15
replacement_policy=PSEUDO_LRU
size=512
start_index_bit=6
[system.physmem]
type=SimpleMemory
conf_table_reported=false
file=
in_addr_map=true
latency=30
latency_var=0
null=false
range=0:134217727
zero=false
[system.ruby]
type=RubySystem
children=network profiler
block_size_bytes=64
clock=1
mem_size=134217728
no_mem_vec=false
random_seed=1234
randomization=false
stats_filename=ruby.stats
[system.ruby.network]
type=SimpleNetwork
children=topology
adaptive_routing=false
buffer_size=0
control_msg_size=8
endpoint_bandwidth=1000
number_of_virtual_networks=10
ruby_system=system.ruby
topology=system.ruby.network.topology
[system.ruby.network.topology]
type=Topology
children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2 routers0 routers1 routers2 routers3
description=Crossbar
ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2
int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2
print_config=false
routers=system.ruby.network.topology.routers0 system.ruby.network.topology.routers1 system.ruby.network.topology.routers2 system.ruby.network.topology.routers3
[system.ruby.network.topology.ext_links0]
type=SimpleExtLink
bandwidth_factor=16
ext_node=system.l1_cntrl0
int_node=system.ruby.network.topology.routers0
latency=1
link_id=0
weight=1
[system.ruby.network.topology.ext_links1]
type=SimpleExtLink
bandwidth_factor=16
ext_node=system.l2_cntrl0
int_node=system.ruby.network.topology.routers1
latency=1
link_id=1
weight=1
[system.ruby.network.topology.ext_links2]
type=SimpleExtLink
bandwidth_factor=16
ext_node=system.dir_cntrl0
int_node=system.ruby.network.topology.routers2
latency=1
link_id=2
weight=1
[system.ruby.network.topology.int_links0]
type=SimpleIntLink
bandwidth_factor=16
latency=1
link_id=3
node_a=system.ruby.network.topology.routers0
node_b=system.ruby.network.topology.routers3
weight=1
[system.ruby.network.topology.int_links1]
type=SimpleIntLink
bandwidth_factor=16
latency=1
link_id=4
node_a=system.ruby.network.topology.routers1
node_b=system.ruby.network.topology.routers3
weight=1
[system.ruby.network.topology.int_links2]
type=SimpleIntLink
bandwidth_factor=16
latency=1
link_id=5
node_a=system.ruby.network.topology.routers2
node_b=system.ruby.network.topology.routers3
weight=1
[system.ruby.network.topology.routers0]
type=BasicRouter
router_id=0
[system.ruby.network.topology.routers1]
type=BasicRouter
router_id=1
[system.ruby.network.topology.routers2]
type=BasicRouter
router_id=2
[system.ruby.network.topology.routers3]
type=BasicRouter
router_id=3
[system.ruby.profiler]
type=RubyProfiler
all_instructions=false
hot_lines=false
num_of_sequencers=1
ruby_system=system.ruby
[system.sys_port_proxy]
type=RubyPortProxy
access_phys_mem=true
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
system=system
using_network_tester=false
using_ruby_tester=false
version=0
slave=system.system_port

1470
simulators/gem5/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/ruby.stats Normal file
View File

File diff suppressed because it is too large Load Diff

3
simulators/gem5/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simerr Executable file
View File

@ -0,0 +1,3 @@
warn: Sockets disabled, not accepting gdb connections
warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
hack: be nice to actually delete the event here

12
simulators/gem5/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout Executable file
View File

@ -0,0 +1,12 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 4 2012 11:54:55
gem5 started Jun 4 2012 14:41:15
gem5 executing on zizzer
command line: build/ALPHA_MOESI_CMP_directory/gem5.opt -d build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello world!
Exiting @ tick 85418 because target called exit()

92
simulators/gem5/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt Normal file
View File

@ -0,0 +1,92 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000085 # Number of seconds simulated
sim_ticks 85418 # Number of ticks simulated
final_tick 85418 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
host_inst_rate 30509 # Simulator instruction rate (inst/s)
host_op_rate 30502 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1010829 # Simulator tick rate (ticks/s)
host_mem_usage 224228 # Number of bytes of host memory used
host_seconds 0.08 # Real time elapsed on the host
sim_insts 2577 # Number of instructions simulated
sim_ops 2577 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 10340 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 3016 # Number of bytes read from this memory
system.physmem.bytes_read::total 13356 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 10340 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 10340 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 2058 # Number of bytes written to this memory
system.physmem.bytes_written::total 2058 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 2585 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 415 # Number of read requests responded to by this memory
system.physmem.num_reads::total 3000 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 294 # Number of write requests responded to by this memory
system.physmem.num_writes::total 294 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 121051769 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 35308717 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 156360486 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 121051769 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 121051769 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 24093282 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 24093282 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 121051769 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 59402000 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 180453769 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 415 # DTB read hits
system.cpu.dtb.read_misses 4 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 419 # DTB read accesses
system.cpu.dtb.write_hits 294 # DTB write hits
system.cpu.dtb.write_misses 4 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 298 # DTB write accesses
system.cpu.dtb.data_hits 709 # DTB hits
system.cpu.dtb.data_misses 8 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 717 # DTB accesses
system.cpu.itb.fetch_hits 2586 # ITB hits
system.cpu.itb.fetch_misses 11 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 2597 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 4 # Number of system calls
system.cpu.numCycles 85418 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 2577 # Number of instructions committed
system.cpu.committedOps 2577 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses
system.cpu.num_func_calls 140 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 238 # number of instructions that are conditional controls
system.cpu.num_int_insts 2375 # number of integer instructions
system.cpu.num_fp_insts 6 # number of float instructions
system.cpu.num_int_register_reads 2998 # number of times the integer registers were read
system.cpu.num_int_register_writes 1768 # number of times the integer registers were written
system.cpu.num_fp_register_reads 6 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_mem_refs 717 # number of memory refs
system.cpu.num_load_insts 419 # Number of load instructions
system.cpu.num_store_insts 298 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 85418 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
---------- End Simulation Statistics ----------

350
simulators/gem5/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini Normal file
View File

@ -0,0 +1,350 @@
[root]
type=Root
children=system
full_system=false
time_sync_enable=false
time_sync_period=100000000
time_sync_spin_threshold=100000
[system]
type=System
children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby sys_port_proxy
boot_osflags=a
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=timing
memories=system.physmem
num_work_ids=16
readfile=
symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.sys_port_proxy.slave[0]
[system.cpu]
type=TimingSimpleCPU
children=dtb interrupts itb tracer workload
checker=Null
clock=1
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
phase=0
profile=0
progress_interval=0
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
dcache_port=system.l1_cntrl0.sequencer.slave[1]
icache_port=system.l1_cntrl0.sequencer.slave[0]
[system.cpu.dtb]
type=AlphaTLB
size=64
[system.cpu.interrupts]
type=AlphaInterrupts
[system.cpu.itb]
type=AlphaTLB
size=48
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=hello
cwd=
egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello
gid=100
input=cin
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=0
system=system
uid=100
[system.dir_cntrl0]
type=Directory_Controller
children=directory memBuffer
buffer_size=0
cntrl_id=2
directory=system.dir_cntrl0.directory
directory_latency=5
distributed_persistent=true
fixed_timeout_latency=100
l2_select_num_bits=0
memBuffer=system.dir_cntrl0.memBuffer
number_of_TBEs=256
recycle_latency=10
ruby_system=system.ruby
transitions_per_cycle=32
version=0
[system.dir_cntrl0.directory]
type=RubyDirectoryMemory
map_levels=4
numa_high_bit=6
size=134217728
use_map=false
version=0
[system.dir_cntrl0.memBuffer]
type=RubyMemoryControl
bank_bit_0=8
bank_busy_time=11
bank_queue_size=12
banks_per_rank=8
basic_bus_busy_time=2
dimm_bit_0=12
dimms_per_channel=2
mem_bus_cycle_multiplier=10
mem_ctl_latency=12
mem_fixed_delay=0
mem_random_arbitrate=0
rank_bit_0=11
rank_rank_delay=1
ranks_per_dimm=2
read_write_delay=2
refresh_period=1560
tFaw=0
version=0
[system.l1_cntrl0]
type=L1Cache_Controller
children=L1DcacheMemory L1IcacheMemory sequencer
L1DcacheMemory=system.l1_cntrl0.L1DcacheMemory
L1IcacheMemory=system.l1_cntrl0.L1IcacheMemory
N_tokens=2
buffer_size=0
cntrl_id=0
dynamic_timeout_enabled=true
fixed_timeout_latency=300
l1_request_latency=2
l1_response_latency=2
l2_select_num_bits=0
no_mig_atomic=true
number_of_TBEs=256
recycle_latency=10
retry_threshold=1
ruby_system=system.ruby
send_evictions=false
sequencer=system.l1_cntrl0.sequencer
transitions_per_cycle=32
version=0
[system.l1_cntrl0.L1DcacheMemory]
type=RubyCache
assoc=2
is_icache=false
latency=2
replacement_policy=PSEUDO_LRU
size=256
start_index_bit=6
[system.l1_cntrl0.L1IcacheMemory]
type=RubyCache
assoc=2
is_icache=false
latency=2
replacement_policy=PSEUDO_LRU
size=256
start_index_bit=6
[system.l1_cntrl0.sequencer]
type=RubySequencer
access_phys_mem=true
dcache=system.l1_cntrl0.L1DcacheMemory
deadlock_threshold=500000
icache=system.l1_cntrl0.L1IcacheMemory
max_outstanding_requests=16
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
system=system
using_network_tester=false
using_ruby_tester=false
version=0
slave=system.cpu.icache_port system.cpu.dcache_port
[system.l2_cntrl0]
type=L2Cache_Controller
children=L2cacheMemory
L2cacheMemory=system.l2_cntrl0.L2cacheMemory
N_tokens=2
buffer_size=0
cntrl_id=1
filtering_enabled=true
l2_request_latency=5
l2_response_latency=5
number_of_TBEs=256
recycle_latency=10
ruby_system=system.ruby
transitions_per_cycle=32
version=0
[system.l2_cntrl0.L2cacheMemory]
type=RubyCache
assoc=2
is_icache=false
latency=10
replacement_policy=PSEUDO_LRU
size=512
start_index_bit=6
[system.physmem]
type=SimpleMemory
conf_table_reported=false
file=
in_addr_map=true
latency=30
latency_var=0
null=false
range=0:134217727
zero=false
[system.ruby]
type=RubySystem
children=network profiler
block_size_bytes=64
clock=1
mem_size=134217728
no_mem_vec=false
random_seed=1234
randomization=false
stats_filename=ruby.stats
[system.ruby.network]
type=SimpleNetwork
children=topology
adaptive_routing=false
buffer_size=0
control_msg_size=8
endpoint_bandwidth=1000
number_of_virtual_networks=10
ruby_system=system.ruby
topology=system.ruby.network.topology
[system.ruby.network.topology]
type=Topology
children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2 routers0 routers1 routers2 routers3
description=Crossbar
ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2
int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2
print_config=false
routers=system.ruby.network.topology.routers0 system.ruby.network.topology.routers1 system.ruby.network.topology.routers2 system.ruby.network.topology.routers3
[system.ruby.network.topology.ext_links0]
type=SimpleExtLink
bandwidth_factor=16
ext_node=system.l1_cntrl0
int_node=system.ruby.network.topology.routers0
latency=1
link_id=0
weight=1
[system.ruby.network.topology.ext_links1]
type=SimpleExtLink
bandwidth_factor=16
ext_node=system.l2_cntrl0
int_node=system.ruby.network.topology.routers1
latency=1
link_id=1
weight=1
[system.ruby.network.topology.ext_links2]
type=SimpleExtLink
bandwidth_factor=16
ext_node=system.dir_cntrl0
int_node=system.ruby.network.topology.routers2
latency=1
link_id=2
weight=1
[system.ruby.network.topology.int_links0]
type=SimpleIntLink
bandwidth_factor=16
latency=1
link_id=3
node_a=system.ruby.network.topology.routers0
node_b=system.ruby.network.topology.routers3
weight=1
[system.ruby.network.topology.int_links1]
type=SimpleIntLink
bandwidth_factor=16
latency=1
link_id=4
node_a=system.ruby.network.topology.routers1
node_b=system.ruby.network.topology.routers3
weight=1
[system.ruby.network.topology.int_links2]
type=SimpleIntLink
bandwidth_factor=16
latency=1
link_id=5
node_a=system.ruby.network.topology.routers2
node_b=system.ruby.network.topology.routers3
weight=1
[system.ruby.network.topology.routers0]
type=BasicRouter
router_id=0
[system.ruby.network.topology.routers1]
type=BasicRouter
router_id=1
[system.ruby.network.topology.routers2]
type=BasicRouter
router_id=2
[system.ruby.network.topology.routers3]
type=BasicRouter
router_id=3
[system.ruby.profiler]
type=RubyProfiler
all_instructions=false
hot_lines=false
num_of_sequencers=1
ruby_system=system.ruby
[system.sys_port_proxy]
type=RubyPortProxy
access_phys_mem=true
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
system=system
using_network_tester=false
using_ruby_tester=false
version=0
slave=system.system_port

1036
simulators/gem5/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/ruby.stats Normal file
View File

File diff suppressed because it is too large Load Diff

3
simulators/gem5/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simerr Executable file
View File

@ -0,0 +1,3 @@
warn: Sockets disabled, not accepting gdb connections
warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
hack: be nice to actually delete the event here

12
simulators/gem5/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout Executable file
View File

@ -0,0 +1,12 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 4 2012 11:56:32
gem5 started Jun 4 2012 14:42:22
gem5 executing on zizzer
command line: build/ALPHA_MOESI_CMP_token/gem5.opt -d build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello world!
Exiting @ tick 87899 because target called exit()

92
simulators/gem5/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt Normal file
View File

@ -0,0 +1,92 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000088 # Number of seconds simulated
sim_ticks 87899 # Number of ticks simulated
final_tick 87899 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
host_inst_rate 49141 # Simulator instruction rate (inst/s)
host_op_rate 49125 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1675041 # Simulator tick rate (ticks/s)
host_mem_usage 223232 # Number of bytes of host memory used
host_seconds 0.05 # Real time elapsed on the host
sim_insts 2577 # Number of instructions simulated
sim_ops 2577 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 10340 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 3016 # Number of bytes read from this memory
system.physmem.bytes_read::total 13356 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 10340 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 10340 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 2058 # Number of bytes written to this memory
system.physmem.bytes_written::total 2058 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 2585 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 415 # Number of read requests responded to by this memory
system.physmem.num_reads::total 3000 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 294 # Number of write requests responded to by this memory
system.physmem.num_writes::total 294 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 117635013 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 34312108 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 151947121 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 117635013 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 117635013 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 23413236 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 23413236 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 117635013 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 57725344 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 175360357 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 415 # DTB read hits
system.cpu.dtb.read_misses 4 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 419 # DTB read accesses
system.cpu.dtb.write_hits 294 # DTB write hits
system.cpu.dtb.write_misses 4 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 298 # DTB write accesses
system.cpu.dtb.data_hits 709 # DTB hits
system.cpu.dtb.data_misses 8 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 717 # DTB accesses
system.cpu.itb.fetch_hits 2586 # ITB hits
system.cpu.itb.fetch_misses 11 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 2597 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 4 # Number of system calls
system.cpu.numCycles 87899 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 2577 # Number of instructions committed
system.cpu.committedOps 2577 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses
system.cpu.num_func_calls 140 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 238 # number of instructions that are conditional controls
system.cpu.num_int_insts 2375 # number of integer instructions
system.cpu.num_fp_insts 6 # number of float instructions
system.cpu.num_int_register_reads 2998 # number of times the integer registers were read
system.cpu.num_int_register_writes 1768 # number of times the integer registers were written
system.cpu.num_fp_register_reads 6 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_mem_refs 717 # number of memory refs
system.cpu.num_load_insts 419 # Number of load instructions
system.cpu.num_store_insts 298 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 87899 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
---------- End Simulation Statistics ----------

318
simulators/gem5/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini Normal file
View File

@ -0,0 +1,318 @@
[root]
type=Root
children=system
full_system=false
time_sync_enable=false
time_sync_period=100000000
time_sync_spin_threshold=100000
[system]
type=System
children=cpu dir_cntrl0 l1_cntrl0 physmem ruby sys_port_proxy
boot_osflags=a
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=timing
memories=system.physmem
num_work_ids=16
readfile=
symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.sys_port_proxy.slave[0]
[system.cpu]
type=TimingSimpleCPU
children=dtb interrupts itb tracer workload
checker=Null
clock=1
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
phase=0
profile=0
progress_interval=0
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
dcache_port=system.l1_cntrl0.sequencer.slave[1]
icache_port=system.l1_cntrl0.sequencer.slave[0]
[system.cpu.dtb]
type=AlphaTLB
size=64
[system.cpu.interrupts]
type=AlphaInterrupts
[system.cpu.itb]
type=AlphaTLB
size=48
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=hello
cwd=
egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello
gid=100
input=cin
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=0
system=system
uid=100
[system.dir_cntrl0]
type=Directory_Controller
children=directory memBuffer probeFilter
buffer_size=0
cntrl_id=1
directory=system.dir_cntrl0.directory
full_bit_dir_enabled=false
memBuffer=system.dir_cntrl0.memBuffer
memory_controller_latency=2
number_of_TBEs=256
probeFilter=system.dir_cntrl0.probeFilter
probe_filter_enabled=false
recycle_latency=10
ruby_system=system.ruby
transitions_per_cycle=32
version=0
[system.dir_cntrl0.directory]
type=RubyDirectoryMemory
map_levels=4
numa_high_bit=6
size=134217728
use_map=false
version=0
[system.dir_cntrl0.memBuffer]
type=RubyMemoryControl
bank_bit_0=8
bank_busy_time=11
bank_queue_size=12
banks_per_rank=8
basic_bus_busy_time=2
dimm_bit_0=12
dimms_per_channel=2
mem_bus_cycle_multiplier=10
mem_ctl_latency=12
mem_fixed_delay=0
mem_random_arbitrate=0
rank_bit_0=11
rank_rank_delay=1
ranks_per_dimm=2
read_write_delay=2
refresh_period=1560
tFaw=0
version=0
[system.dir_cntrl0.probeFilter]
type=RubyCache
assoc=4
is_icache=false
latency=1
replacement_policy=PSEUDO_LRU
size=1024
start_index_bit=6
[system.l1_cntrl0]
type=L1Cache_Controller
children=L1DcacheMemory L1IcacheMemory L2cacheMemory sequencer
L1DcacheMemory=system.l1_cntrl0.L1DcacheMemory
L1IcacheMemory=system.l1_cntrl0.L1IcacheMemory
L2cacheMemory=system.l1_cntrl0.L2cacheMemory
buffer_size=0
cache_response_latency=10
cntrl_id=0
issue_latency=2
l2_cache_hit_latency=10
no_mig_atomic=true
number_of_TBEs=256
recycle_latency=10
ruby_system=system.ruby
send_evictions=false
sequencer=system.l1_cntrl0.sequencer
transitions_per_cycle=32
version=0
[system.l1_cntrl0.L1DcacheMemory]
type=RubyCache
assoc=2
is_icache=false
latency=2
replacement_policy=PSEUDO_LRU
size=256
start_index_bit=6
[system.l1_cntrl0.L1IcacheMemory]
type=RubyCache
assoc=2
is_icache=true
latency=2
replacement_policy=PSEUDO_LRU
size=256
start_index_bit=6
[system.l1_cntrl0.L2cacheMemory]
type=RubyCache
assoc=2
is_icache=false
latency=10
replacement_policy=PSEUDO_LRU
size=512
start_index_bit=6
[system.l1_cntrl0.sequencer]
type=RubySequencer
access_phys_mem=true
dcache=system.l1_cntrl0.L1DcacheMemory
deadlock_threshold=500000
icache=system.l1_cntrl0.L1IcacheMemory
max_outstanding_requests=16
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
system=system
using_network_tester=false
using_ruby_tester=false
version=0
slave=system.cpu.icache_port system.cpu.dcache_port
[system.physmem]
type=SimpleMemory
conf_table_reported=false
file=
in_addr_map=true
latency=30
latency_var=0
null=false
range=0:134217727
zero=false
[system.ruby]
type=RubySystem
children=network profiler
block_size_bytes=64
clock=1
mem_size=134217728
no_mem_vec=false
random_seed=1234
randomization=false
stats_filename=ruby.stats
[system.ruby.network]
type=SimpleNetwork
children=topology
adaptive_routing=false
buffer_size=0
control_msg_size=8
endpoint_bandwidth=1000
number_of_virtual_networks=10
ruby_system=system.ruby
topology=system.ruby.network.topology
[system.ruby.network.topology]
type=Topology
children=ext_links0 ext_links1 int_links0 int_links1 routers0 routers1 routers2
description=Crossbar
ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1
int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1
print_config=false
routers=system.ruby.network.topology.routers0 system.ruby.network.topology.routers1 system.ruby.network.topology.routers2
[system.ruby.network.topology.ext_links0]
type=SimpleExtLink
bandwidth_factor=16
ext_node=system.l1_cntrl0
int_node=system.ruby.network.topology.routers0
latency=1
link_id=0
weight=1
[system.ruby.network.topology.ext_links1]
type=SimpleExtLink
bandwidth_factor=16
ext_node=system.dir_cntrl0
int_node=system.ruby.network.topology.routers1
latency=1
link_id=1
weight=1
[system.ruby.network.topology.int_links0]
type=SimpleIntLink
bandwidth_factor=16
latency=1
link_id=2
node_a=system.ruby.network.topology.routers0
node_b=system.ruby.network.topology.routers2
weight=1
[system.ruby.network.topology.int_links1]
type=SimpleIntLink
bandwidth_factor=16
latency=1
link_id=3
node_a=system.ruby.network.topology.routers1
node_b=system.ruby.network.topology.routers2
weight=1
[system.ruby.network.topology.routers0]
type=BasicRouter
router_id=0
[system.ruby.network.topology.routers1]
type=BasicRouter
router_id=1
[system.ruby.network.topology.routers2]
type=BasicRouter
router_id=2
[system.ruby.profiler]
type=RubyProfiler
all_instructions=false
hot_lines=false
num_of_sequencers=1
ruby_system=system.ruby
[system.sys_port_proxy]
type=RubyPortProxy
access_phys_mem=true
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
system=system
using_network_tester=false
using_ruby_tester=false
version=0
slave=system.system_port

973
simulators/gem5/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/ruby.stats Normal file
View File

@ -0,0 +1,973 @@
================ Begin RubySystem Configuration Print ================
RubySystem config:
random_seed: 1234
randomization: 0
cycle_period: 1
block_size_bytes: 64
block_size_bits: 6
memory_size_bytes: 134217728
memory_size_bits: 27
Network Configuration
---------------------
network: SIMPLE_NETWORK
topology:
virtual_net_0: active, ordered
virtual_net_1: active, ordered
virtual_net_2: active, unordered
virtual_net_3: active, unordered
virtual_net_4: active, unordered
virtual_net_5: active, unordered
virtual_net_6: inactive
virtual_net_7: inactive
virtual_net_8: inactive
virtual_net_9: inactive
Profiler Configuration
----------------------
periodic_stats_period: 1000000
================ End RubySystem Configuration Print ================
Real time: Jun/04/2012 13:42:34
Profiler Stats
--------------
Elapsed_time_in_seconds: 0
Elapsed_time_in_minutes: 0
Elapsed_time_in_hours: 0
Elapsed_time_in_days: 0
Virtual_time_in_seconds: 0.34
Virtual_time_in_minutes: 0.00566667
Virtual_time_in_hours: 9.44444e-05
Virtual_time_in_days: 3.93519e-06
Ruby_current_time: 78448
Ruby_start_time: 0
Ruby_cycles: 78448
mbytes_resident: 45.7539
mbytes_total: 217.664
resident_ratio: 0.210204
ruby_cycles_executed: [ 78449 ]
Busy Controller Counts:
L1Cache-0:0
Directory-0:0
Busy Bank Count:0
sequencer_requests_outstanding: [binsize: 1 max: 1 count: 3295 average: 1 | standard deviation: 0 | 0 3295 ]
All Non-Zero Cycle Demand Cache Accesses
----------------------------------------
miss_latency: [binsize: 2 max: 320 count: 3294 average: 22.8154 | standard deviation: 52.8821 | 0 2784 0 0 0 0 69 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 35 77 95 66 57 76 2 2 1 4 2 0 1 2 2 5 1 4 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 3 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
miss_latency_LD: [binsize: 2 max: 319 count: 415 average: 57.3952 | standard deviation: 74.7751 | 0 233 0 0 0 0 36 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 35 24 16 16 26 0 1 1 0 1 0 0 1 2 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
miss_latency_ST: [binsize: 2 max: 320 count: 294 average: 28.9728 | standard deviation: 63.5282 | 0 236 0 0 0 0 11 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 7 6 7 5 10 0 0 0 1 1 0 1 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 2 0 1 0 0 0 0 0 0 0 0 0 0 ]
miss_latency_IFETCH: [binsize: 1 max: 181 count: 2585 average: 16.5636 | standard deviation: 44.4401 | 0 0 2315 0 0 0 0 0 0 0 0 0 0 22 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 47 18 11 32 22 14 39 1 1 1 1 0 0 0 2 1 0 0 0 0 0 0 0 1 0 0 0 2 1 0 2 1 ]
miss_latency_L1Cache: [binsize: 1 max: 2 count: 2784 average: 2 | standard deviation: 0 | 0 0 2784 ]
miss_latency_L2Cache: [binsize: 1 max: 13 count: 69 average: 13 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 69 ]
miss_latency_Directory: [binsize: 2 max: 320 count: 441 average: 155.757 | standard deviation: 21.4255 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 35 77 95 66 57 76 2 2 1 4 2 0 1 2 2 5 1 4 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 3 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
imcomplete_wCC_Times: 0
miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ]
miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ]
miss_latency_dir_forward_to_first_response: [binsize: 1 max: 158 count: 1 average: 158 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ]
imcomplete_dir_Times: 440
miss_latency_LD_L1Cache: [binsize: 1 max: 2 count: 233 average: 2 | standard deviation: 0 | 0 0 233 ]
miss_latency_LD_L2Cache: [binsize: 1 max: 13 count: 36 average: 13 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 36 ]
miss_latency_LD_Directory: [binsize: 2 max: 319 count: 146 average: 156.747 | standard deviation: 24.5989 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 35 24 16 16 26 0 1 1 0 1 0 0 1 2 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
miss_latency_ST_L1Cache: [binsize: 1 max: 2 count: 236 average: 2 | standard deviation: 0 | 0 0 236 ]
miss_latency_ST_L2Cache: [binsize: 1 max: 13 count: 11 average: 13 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 11 ]
miss_latency_ST_Directory: [binsize: 2 max: 320 count: 47 average: 168.149 | standard deviation: 46.0633 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 7 6 7 5 10 0 0 0 1 1 0 1 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 2 0 1 0 0 0 0 0 0 0 0 0 0 ]
miss_latency_IFETCH_L1Cache: [binsize: 1 max: 2 count: 2315 average: 2 | standard deviation: 0 | 0 0 2315 ]
miss_latency_IFETCH_L2Cache: [binsize: 1 max: 13 count: 22 average: 13 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 22 ]
miss_latency_IFETCH_Directory: [binsize: 1 max: 181 count: 248 average: 152.827 | standard deviation: 5.37952 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 47 18 11 32 22 14 39 1 1 1 1 0 0 0 2 1 0 0 0 0 0 0 0 1 0 0 0 2 1 0 2 1 ]
All Non-Zero Cycle SW Prefetch Requests
------------------------------------
prefetch_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
prefetch_latency_L2Miss:[binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
Request vs. RubySystem State Profile
--------------------------------
filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
Message Delayed Cycles
----------------------
Total_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
virtual_network_0_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
virtual_network_6_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
virtual_network_7_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
virtual_network_8_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
virtual_network_9_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
Resource Usage
--------------
page_size: 4096
user_time: 0
system_time: 0
page_reclaims: 12072
page_faults: 20
swaps: 0
block_inputs: 2944
block_outputs: 96
Network Stats
-------------
total_msg_count_Request_Control: 1323 10584
total_msg_count_Response_Data: 1323 95256
total_msg_count_Writeback_Data: 243 17496
total_msg_count_Writeback_Control: 3582 28656
total_msg_count_Unblock_Control: 1320 10560
total_msgs: 7791 total_bytes: 162552
switch_0_inlinks: 2
switch_0_outlinks: 2
links_utilized_percent_switch_0: 2.15844
links_utilized_percent_switch_0_link_0: 2.80058 bw: 16000 base_latency: 1
links_utilized_percent_switch_0_link_1: 1.51629 bw: 16000 base_latency: 1
outgoing_messages_switch_0_link_0_Response_Data: 441 31752 [ 0 0 0 0 441 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_0_link_0_Writeback_Control: 425 3400 [ 0 0 0 425 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_0_link_1_Request_Control: 441 3528 [ 0 0 441 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_0_link_1_Writeback_Data: 81 5832 [ 0 0 0 0 0 81 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_0_link_1_Writeback_Control: 769 6152 [ 0 0 425 0 0 344 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_0_link_1_Unblock_Control: 440 3520 [ 0 0 0 0 0 440 0 0 0 0 ] base_latency: 1
switch_1_inlinks: 2
switch_1_outlinks: 2
links_utilized_percent_switch_1: 2.15844
links_utilized_percent_switch_1_link_0: 1.51629 bw: 16000 base_latency: 1
links_utilized_percent_switch_1_link_1: 2.80058 bw: 16000 base_latency: 1
outgoing_messages_switch_1_link_0_Request_Control: 441 3528 [ 0 0 441 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_1_link_0_Writeback_Data: 81 5832 [ 0 0 0 0 0 81 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_1_link_0_Writeback_Control: 769 6152 [ 0 0 425 0 0 344 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_1_link_0_Unblock_Control: 440 3520 [ 0 0 0 0 0 440 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_1_link_1_Response_Data: 441 31752 [ 0 0 0 0 441 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_1_link_1_Writeback_Control: 425 3400 [ 0 0 0 425 0 0 0 0 0 0 ] base_latency: 1
switch_2_inlinks: 2
switch_2_outlinks: 2
links_utilized_percent_switch_2: 2.15844
links_utilized_percent_switch_2_link_0: 2.80058 bw: 16000 base_latency: 1
links_utilized_percent_switch_2_link_1: 1.51629 bw: 16000 base_latency: 1
outgoing_messages_switch_2_link_0_Response_Data: 441 31752 [ 0 0 0 0 441 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_2_link_0_Writeback_Control: 425 3400 [ 0 0 0 425 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_2_link_1_Request_Control: 441 3528 [ 0 0 441 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_2_link_1_Writeback_Data: 81 5832 [ 0 0 0 0 0 81 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_2_link_1_Writeback_Control: 769 6152 [ 0 0 425 0 0 344 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_2_link_1_Unblock_Control: 440 3520 [ 0 0 0 0 0 440 0 0 0 0 ] base_latency: 1
Cache Stats: system.l1_cntrl0.L1IcacheMemory
system.l1_cntrl0.L1IcacheMemory_total_misses: 270
system.l1_cntrl0.L1IcacheMemory_total_demand_misses: 270
system.l1_cntrl0.L1IcacheMemory_total_prefetches: 0
system.l1_cntrl0.L1IcacheMemory_total_sw_prefetches: 0
system.l1_cntrl0.L1IcacheMemory_total_hw_prefetches: 0
system.l1_cntrl0.L1IcacheMemory_request_type_IFETCH: 100%
system.l1_cntrl0.L1IcacheMemory_access_mode_type_Supervisor: 270 100%
Cache Stats: system.l1_cntrl0.L1DcacheMemory
system.l1_cntrl0.L1DcacheMemory_total_misses: 240
system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 240
system.l1_cntrl0.L1DcacheMemory_total_prefetches: 0
system.l1_cntrl0.L1DcacheMemory_total_sw_prefetches: 0
system.l1_cntrl0.L1DcacheMemory_total_hw_prefetches: 0
system.l1_cntrl0.L1DcacheMemory_request_type_LD: 75.8333%
system.l1_cntrl0.L1DcacheMemory_request_type_ST: 24.1667%
system.l1_cntrl0.L1DcacheMemory_access_mode_type_Supervisor: 240 100%
Cache Stats: system.l1_cntrl0.L2cacheMemory
system.l1_cntrl0.L2cacheMemory_total_misses: 510
system.l1_cntrl0.L2cacheMemory_total_demand_misses: 510
system.l1_cntrl0.L2cacheMemory_total_prefetches: 0
system.l1_cntrl0.L2cacheMemory_total_sw_prefetches: 0
system.l1_cntrl0.L2cacheMemory_total_hw_prefetches: 0
system.l1_cntrl0.L2cacheMemory_request_type_LD: 35.6863%
system.l1_cntrl0.L2cacheMemory_request_type_ST: 11.3725%
system.l1_cntrl0.L2cacheMemory_request_type_IFETCH: 52.9412%
system.l1_cntrl0.L2cacheMemory_access_mode_type_Supervisor: 510 100%
--- L1Cache ---
- Event Counts -
Load [422 ] 422
Ifetch [2591 ] 2591
Store [298 ] 298
L2_Replacement [425 ] 425
L1_to_L2 [502 ] 502
Trigger_L2_to_L1D [47 ] 47
Trigger_L2_to_L1I [22 ] 22
Complete_L2_to_L1 [69 ] 69
Other_GETX [0 ] 0
Other_GETS [0 ] 0
Merged_GETS [0 ] 0
Other_GETS_No_Mig [0 ] 0
NC_DMA_GETS [0 ] 0
Invalidate [0 ] 0
Ack [0 ] 0
Shared_Ack [0 ] 0
Data [0 ] 0
Shared_Data [0 ] 0
Exclusive_Data [441 ] 441
Writeback_Ack [425 ] 425
Writeback_Nack [0 ] 0
All_acks [0 ] 0
All_acks_no_sharers [441 ] 441
Flush_line [0 ] 0
Block_Ack [0 ] 0
- Transitions -
I Load [146 ] 146
I Ifetch [248 ] 248
I Store [47 ] 47
I L2_Replacement [0 ] 0
I L1_to_L2 [0 ] 0
I Trigger_L2_to_L1D [0 ] 0
I Trigger_L2_to_L1I [0 ] 0
I Other_GETX [0 ] 0
I Other_GETS [0 ] 0
I Other_GETS_No_Mig [0 ] 0
I NC_DMA_GETS [0 ] 0
I Invalidate [0 ] 0
I Flush_line [0 ] 0
S Load [0 ] 0
S Ifetch [0 ] 0
S Store [0 ] 0
S L2_Replacement [0 ] 0
S L1_to_L2 [0 ] 0
S Trigger_L2_to_L1D [0 ] 0
S Trigger_L2_to_L1I [0 ] 0
S Other_GETX [0 ] 0
S Other_GETS [0 ] 0
S Other_GETS_No_Mig [0 ] 0
S NC_DMA_GETS [0 ] 0
S Invalidate [0 ] 0
S Flush_line [0 ] 0
O Load [0 ] 0
O Ifetch [0 ] 0
O Store [0 ] 0
O L2_Replacement [0 ] 0
O L1_to_L2 [0 ] 0
O Trigger_L2_to_L1D [0 ] 0
O Trigger_L2_to_L1I [0 ] 0
O Other_GETX [0 ] 0
O Other_GETS [0 ] 0
O Merged_GETS [0 ] 0
O Other_GETS_No_Mig [0 ] 0
O NC_DMA_GETS [0 ] 0
O Invalidate [0 ] 0
O Flush_line [0 ] 0
M Load [109 ] 109
M Ifetch [2315 ] 2315
M Store [35 ] 35
M L2_Replacement [344 ] 344
M L1_to_L2 [397 ] 397
M Trigger_L2_to_L1D [23 ] 23
M Trigger_L2_to_L1I [22 ] 22
M Other_GETX [0 ] 0
M Other_GETS [0 ] 0
M Merged_GETS [0 ] 0
M Other_GETS_No_Mig [0 ] 0
M NC_DMA_GETS [0 ] 0
M Invalidate [0 ] 0
M Flush_line [0 ] 0
MM Load [124 ] 124
MM Ifetch [0 ] 0
MM Store [201 ] 201
MM L2_Replacement [81 ] 81
MM L1_to_L2 [105 ] 105
MM Trigger_L2_to_L1D [24 ] 24
MM Trigger_L2_to_L1I [0 ] 0
MM Other_GETX [0 ] 0
MM Other_GETS [0 ] 0
MM Merged_GETS [0 ] 0
MM Other_GETS_No_Mig [0 ] 0
MM NC_DMA_GETS [0 ] 0
MM Invalidate [0 ] 0
MM Flush_line [0 ] 0
IR Load [0 ] 0
IR Ifetch [0 ] 0
IR Store [0 ] 0
IR L1_to_L2 [0 ] 0
IR Flush_line [0 ] 0
SR Load [0 ] 0
SR Ifetch [0 ] 0
SR Store [0 ] 0
SR L1_to_L2 [0 ] 0
SR Flush_line [0 ] 0
OR Load [0 ] 0
OR Ifetch [0 ] 0
OR Store [0 ] 0
OR L1_to_L2 [0 ] 0
OR Flush_line [0 ] 0
MR Load [22 ] 22
MR Ifetch [22 ] 22
MR Store [1 ] 1
MR L1_to_L2 [0 ] 0
MR Flush_line [0 ] 0
MMR Load [14 ] 14
MMR Ifetch [0 ] 0
MMR Store [10 ] 10
MMR L1_to_L2 [0 ] 0
MMR Flush_line [0 ] 0
IM Load [0 ] 0
IM Ifetch [0 ] 0
IM Store [0 ] 0
IM L2_Replacement [0 ] 0
IM L1_to_L2 [0 ] 0
IM Other_GETX [0 ] 0
IM Other_GETS [0 ] 0
IM Other_GETS_No_Mig [0 ] 0
IM NC_DMA_GETS [0 ] 0
IM Invalidate [0 ] 0
IM Ack [0 ] 0
IM Data [0 ] 0
IM Exclusive_Data [47 ] 47
IM Flush_line [0 ] 0
SM Load [0 ] 0
SM Ifetch [0 ] 0
SM Store [0 ] 0
SM L2_Replacement [0 ] 0
SM L1_to_L2 [0 ] 0
SM Other_GETX [0 ] 0
SM Other_GETS [0 ] 0
SM Other_GETS_No_Mig [0 ] 0
SM NC_DMA_GETS [0 ] 0
SM Invalidate [0 ] 0
SM Ack [0 ] 0
SM Data [0 ] 0
SM Exclusive_Data [0 ] 0
SM Flush_line [0 ] 0
OM Load [0 ] 0
OM Ifetch [0 ] 0
OM Store [0 ] 0
OM L2_Replacement [0 ] 0
OM L1_to_L2 [0 ] 0
OM Other_GETX [0 ] 0
OM Other_GETS [0 ] 0
OM Merged_GETS [0 ] 0
OM Other_GETS_No_Mig [0 ] 0
OM NC_DMA_GETS [0 ] 0
OM Invalidate [0 ] 0
OM Ack [0 ] 0
OM All_acks [0 ] 0
OM All_acks_no_sharers [0 ] 0
OM Flush_line [0 ] 0
ISM Load [0 ] 0
ISM Ifetch [0 ] 0
ISM Store [0 ] 0
ISM L2_Replacement [0 ] 0
ISM L1_to_L2 [0 ] 0
ISM Ack [0 ] 0
ISM All_acks_no_sharers [0 ] 0
ISM Flush_line [0 ] 0
M_W Load [0 ] 0
M_W Ifetch [0 ] 0
M_W Store [0 ] 0
M_W L2_Replacement [0 ] 0
M_W L1_to_L2 [0 ] 0
M_W Ack [0 ] 0
M_W All_acks_no_sharers [394 ] 394
M_W Flush_line [0 ] 0
MM_W Load [0 ] 0
MM_W Ifetch [0 ] 0
MM_W Store [0 ] 0
MM_W L2_Replacement [0 ] 0
MM_W L1_to_L2 [0 ] 0
MM_W Ack [0 ] 0
MM_W All_acks_no_sharers [47 ] 47
MM_W Flush_line [0 ] 0
IS Load [0 ] 0
IS Ifetch [0 ] 0
IS Store [0 ] 0
IS L2_Replacement [0 ] 0
IS L1_to_L2 [0 ] 0
IS Other_GETX [0 ] 0
IS Other_GETS [0 ] 0
IS Other_GETS_No_Mig [0 ] 0
IS NC_DMA_GETS [0 ] 0
IS Invalidate [0 ] 0
IS Ack [0 ] 0
IS Shared_Ack [0 ] 0
IS Data [0 ] 0
IS Shared_Data [0 ] 0
IS Exclusive_Data [394 ] 394
IS Flush_line [0 ] 0
SS Load [0 ] 0
SS Ifetch [0 ] 0
SS Store [0 ] 0
SS L2_Replacement [0 ] 0
SS L1_to_L2 [0 ] 0
SS Ack [0 ] 0
SS Shared_Ack [0 ] 0
SS All_acks [0 ] 0
SS All_acks_no_sharers [0 ] 0
SS Flush_line [0 ] 0
OI Load [0 ] 0
OI Ifetch [0 ] 0
OI Store [0 ] 0
OI L2_Replacement [0 ] 0
OI L1_to_L2 [0 ] 0
OI Other_GETX [0 ] 0
OI Other_GETS [0 ] 0
OI Merged_GETS [0 ] 0
OI Other_GETS_No_Mig [0 ] 0
OI NC_DMA_GETS [0 ] 0
OI Invalidate [0 ] 0
OI Writeback_Ack [0 ] 0
OI Flush_line [0 ] 0
MI Load [7 ] 7
MI Ifetch [6 ] 6
MI Store [4 ] 4
MI L2_Replacement [0 ] 0
MI L1_to_L2 [0 ] 0
MI Other_GETX [0 ] 0
MI Other_GETS [0 ] 0
MI Merged_GETS [0 ] 0
MI Other_GETS_No_Mig [0 ] 0
MI NC_DMA_GETS [0 ] 0
MI Invalidate [0 ] 0
MI Writeback_Ack [425 ] 425
MI Flush_line [0 ] 0
II Load [0 ] 0
II Ifetch [0 ] 0
II Store [0 ] 0
II L2_Replacement [0 ] 0
II L1_to_L2 [0 ] 0
II Other_GETX [0 ] 0
II Other_GETS [0 ] 0
II Other_GETS_No_Mig [0 ] 0
II NC_DMA_GETS [0 ] 0
II Invalidate [0 ] 0
II Writeback_Ack [0 ] 0
II Writeback_Nack [0 ] 0
II Flush_line [0 ] 0
IT Load [0 ] 0
IT Ifetch [0 ] 0
IT Store [0 ] 0
IT L2_Replacement [0 ] 0
IT L1_to_L2 [0 ] 0
IT Complete_L2_to_L1 [0 ] 0
ST Load [0 ] 0
ST Ifetch [0 ] 0
ST Store [0 ] 0
ST L2_Replacement [0 ] 0
ST L1_to_L2 [0 ] 0
ST Complete_L2_to_L1 [0 ] 0
OT Load [0 ] 0
OT Ifetch [0 ] 0
OT Store [0 ] 0
OT L2_Replacement [0 ] 0
OT L1_to_L2 [0 ] 0
OT Complete_L2_to_L1 [0 ] 0
MT Load [0 ] 0
MT Ifetch [0 ] 0
MT Store [0 ] 0
MT L2_Replacement [0 ] 0
MT L1_to_L2 [0 ] 0
MT Complete_L2_to_L1 [45 ] 45
MMT Load [0 ] 0
MMT Ifetch [0 ] 0
MMT Store [0 ] 0
MMT L2_Replacement [0 ] 0
MMT L1_to_L2 [0 ] 0
MMT Complete_L2_to_L1 [24 ] 24
MI_F Load [0 ] 0
MI_F Ifetch [0 ] 0
MI_F Store [0 ] 0
MI_F L1_to_L2 [0 ] 0
MI_F Writeback_Ack [0 ] 0
MI_F Flush_line [0 ] 0
MM_F Load [0 ] 0
MM_F Ifetch [0 ] 0
MM_F Store [0 ] 0
MM_F L1_to_L2 [0 ] 0
MM_F Other_GETX [0 ] 0
MM_F Other_GETS [0 ] 0
MM_F Merged_GETS [0 ] 0
MM_F Other_GETS_No_Mig [0 ] 0
MM_F NC_DMA_GETS [0 ] 0
MM_F Invalidate [0 ] 0
MM_F Ack [0 ] 0
MM_F All_acks [0 ] 0
MM_F All_acks_no_sharers [0 ] 0
MM_F Flush_line [0 ] 0
MM_F Block_Ack [0 ] 0
IM_F Load [0 ] 0
IM_F Ifetch [0 ] 0
IM_F Store [0 ] 0
IM_F L2_Replacement [0 ] 0
IM_F L1_to_L2 [0 ] 0
IM_F Other_GETX [0 ] 0
IM_F Other_GETS [0 ] 0
IM_F Other_GETS_No_Mig [0 ] 0
IM_F NC_DMA_GETS [0 ] 0
IM_F Invalidate [0 ] 0
IM_F Ack [0 ] 0
IM_F Data [0 ] 0
IM_F Exclusive_Data [0 ] 0
IM_F Flush_line [0 ] 0
ISM_F Load [0 ] 0
ISM_F Ifetch [0 ] 0
ISM_F Store [0 ] 0
ISM_F L2_Replacement [0 ] 0
ISM_F L1_to_L2 [0 ] 0
ISM_F Ack [0 ] 0
ISM_F All_acks_no_sharers [0 ] 0
ISM_F Flush_line [0 ] 0
SM_F Load [0 ] 0
SM_F Ifetch [0 ] 0
SM_F Store [0 ] 0
SM_F L2_Replacement [0 ] 0
SM_F L1_to_L2 [0 ] 0
SM_F Other_GETX [0 ] 0
SM_F Other_GETS [0 ] 0
SM_F Other_GETS_No_Mig [0 ] 0
SM_F NC_DMA_GETS [0 ] 0
SM_F Invalidate [0 ] 0
SM_F Ack [0 ] 0
SM_F Data [0 ] 0
SM_F Exclusive_Data [0 ] 0
SM_F Flush_line [0 ] 0
OM_F Load [0 ] 0
OM_F Ifetch [0 ] 0
OM_F Store [0 ] 0
OM_F L2_Replacement [0 ] 0
OM_F L1_to_L2 [0 ] 0
OM_F Other_GETX [0 ] 0
OM_F Other_GETS [0 ] 0
OM_F Merged_GETS [0 ] 0
OM_F Other_GETS_No_Mig [0 ] 0
OM_F NC_DMA_GETS [0 ] 0
OM_F Invalidate [0 ] 0
OM_F Ack [0 ] 0
OM_F All_acks [0 ] 0
OM_F All_acks_no_sharers [0 ] 0
OM_F Flush_line [0 ] 0
MM_WF Load [0 ] 0
MM_WF Ifetch [0 ] 0
MM_WF Store [0 ] 0
MM_WF L2_Replacement [0 ] 0
MM_WF L1_to_L2 [0 ] 0
MM_WF Ack [0 ] 0
MM_WF All_acks_no_sharers [0 ] 0
MM_WF Flush_line [0 ] 0
Cache Stats: system.dir_cntrl0.probeFilter
system.dir_cntrl0.probeFilter_total_misses: 0
system.dir_cntrl0.probeFilter_total_demand_misses: 0
system.dir_cntrl0.probeFilter_total_prefetches: 0
system.dir_cntrl0.probeFilter_total_sw_prefetches: 0
system.dir_cntrl0.probeFilter_total_hw_prefetches: 0
Memory controller: system.dir_cntrl0.memBuffer:
memory_total_requests: 522
memory_reads: 441
memory_writes: 81
memory_refreshes: 164
memory_total_request_delays: 151
memory_delays_per_request: 0.289272
memory_delays_in_input_queue: 2
memory_delays_behind_head_of_bank_queue: 0
memory_delays_stalled_at_head_of_bank_queue: 149
memory_stalls_for_bank_busy: 22
memory_stalls_for_random_busy: 0
memory_stalls_for_anti_starvation: 0
memory_stalls_for_arbitration: 7
memory_stalls_for_bus: 26
memory_stalls_for_tfaw: 0
memory_stalls_for_read_write_turnaround: 94
memory_stalls_for_read_read_turnaround: 0
accesses_per_bank: 18 10 0 36 20 19 31 22 5 4 7 4 22 41 22 3 4 6 7 13 10 18 14 41 16 5 5 12 13 18 14 62
--- Directory ---
- Event Counts -
GETX [53 ] 53
GETS [410 ] 410
PUT [425 ] 425
Unblock [0 ] 0
UnblockS [0 ] 0
UnblockM [440 ] 440
Writeback_Clean [0 ] 0
Writeback_Dirty [0 ] 0
Writeback_Exclusive_Clean [344 ] 344
Writeback_Exclusive_Dirty [81 ] 81
Pf_Replacement [0 ] 0
DMA_READ [0 ] 0
DMA_WRITE [0 ] 0
Memory_Data [441 ] 441
Memory_Ack [81 ] 81
Ack [0 ] 0
Shared_Ack [0 ] 0
Shared_Data [0 ] 0
Data [0 ] 0
Exclusive_Data [0 ] 0
All_acks_and_shared_data [0 ] 0
All_acks_and_owner_data [0 ] 0
All_acks_and_data_no_sharers [0 ] 0
All_Unblocks [0 ] 0
GETF [0 ] 0
PUTF [0 ] 0
- Transitions -
NX GETX [0 ] 0
NX GETS [0 ] 0
NX PUT [0 ] 0
NX Pf_Replacement [0 ] 0
NX DMA_READ [0 ] 0
NX DMA_WRITE [0 ] 0
NX GETF [0 ] 0
NO GETX [0 ] 0
NO GETS [0 ] 0
NO PUT [425 ] 425
NO Pf_Replacement [0 ] 0
NO DMA_READ [0 ] 0
NO DMA_WRITE [0 ] 0
NO GETF [0 ] 0
S GETX [0 ] 0
S GETS [0 ] 0
S PUT [0 ] 0
S Pf_Replacement [0 ] 0
S DMA_READ [0 ] 0
S DMA_WRITE [0 ] 0
S GETF [0 ] 0
O GETX [0 ] 0
O GETS [0 ] 0
O PUT [0 ] 0
O Pf_Replacement [0 ] 0
O DMA_READ [0 ] 0
O DMA_WRITE [0 ] 0
O GETF [0 ] 0
E GETX [47 ] 47
E GETS [394 ] 394
E PUT [0 ] 0
E DMA_READ [0 ] 0
E DMA_WRITE [0 ] 0
E GETF [0 ] 0
O_R GETX [0 ] 0
O_R GETS [0 ] 0
O_R PUT [0 ] 0
O_R Pf_Replacement [0 ] 0
O_R DMA_READ [0 ] 0
O_R DMA_WRITE [0 ] 0
O_R Ack [0 ] 0
O_R All_acks_and_data_no_sharers [0 ] 0
O_R GETF [0 ] 0
S_R GETX [0 ] 0
S_R GETS [0 ] 0
S_R PUT [0 ] 0
S_R Pf_Replacement [0 ] 0
S_R DMA_READ [0 ] 0
S_R DMA_WRITE [0 ] 0
S_R Ack [0 ] 0
S_R Data [0 ] 0
S_R All_acks_and_data_no_sharers [0 ] 0
S_R GETF [0 ] 0
NO_R GETX [0 ] 0
NO_R GETS [0 ] 0
NO_R PUT [0 ] 0
NO_R Pf_Replacement [0 ] 0
NO_R DMA_READ [0 ] 0
NO_R DMA_WRITE [0 ] 0
NO_R Ack [0 ] 0
NO_R Data [0 ] 0
NO_R Exclusive_Data [0 ] 0
NO_R All_acks_and_data_no_sharers [0 ] 0
NO_R GETF [0 ] 0
NO_B GETX [0 ] 0
NO_B GETS [0 ] 0
NO_B PUT [0 ] 0
NO_B UnblockS [0 ] 0
NO_B UnblockM [440 ] 440
NO_B Pf_Replacement [0 ] 0
NO_B DMA_READ [0 ] 0
NO_B DMA_WRITE [0 ] 0
NO_B GETF [0 ] 0
NO_B_X GETX [0 ] 0
NO_B_X GETS [0 ] 0
NO_B_X PUT [0 ] 0
NO_B_X UnblockS [0 ] 0
NO_B_X UnblockM [0 ] 0
NO_B_X Pf_Replacement [0 ] 0
NO_B_X DMA_READ [0 ] 0
NO_B_X DMA_WRITE [0 ] 0
NO_B_X GETF [0 ] 0
NO_B_S GETX [0 ] 0
NO_B_S GETS [0 ] 0
NO_B_S PUT [0 ] 0
NO_B_S UnblockS [0 ] 0
NO_B_S UnblockM [0 ] 0
NO_B_S Pf_Replacement [0 ] 0
NO_B_S DMA_READ [0 ] 0
NO_B_S DMA_WRITE [0 ] 0
NO_B_S GETF [0 ] 0
NO_B_S_W GETX [0 ] 0
NO_B_S_W GETS [0 ] 0
NO_B_S_W PUT [0 ] 0
NO_B_S_W UnblockS [0 ] 0
NO_B_S_W Pf_Replacement [0 ] 0
NO_B_S_W DMA_READ [0 ] 0
NO_B_S_W DMA_WRITE [0 ] 0
NO_B_S_W All_Unblocks [0 ] 0
NO_B_S_W GETF [0 ] 0
O_B GETX [0 ] 0
O_B GETS [0 ] 0
O_B PUT [0 ] 0
O_B UnblockS [0 ] 0
O_B UnblockM [0 ] 0
O_B Pf_Replacement [0 ] 0
O_B DMA_READ [0 ] 0
O_B DMA_WRITE [0 ] 0
O_B GETF [0 ] 0
NO_B_W GETX [0 ] 0
NO_B_W GETS [0 ] 0
NO_B_W PUT [0 ] 0
NO_B_W UnblockS [0 ] 0
NO_B_W UnblockM [0 ] 0
NO_B_W Pf_Replacement [0 ] 0
NO_B_W DMA_READ [0 ] 0
NO_B_W DMA_WRITE [0 ] 0
NO_B_W Memory_Data [441 ] 441
NO_B_W GETF [0 ] 0
O_B_W GETX [0 ] 0
O_B_W GETS [0 ] 0
O_B_W PUT [0 ] 0
O_B_W UnblockS [0 ] 0
O_B_W Pf_Replacement [0 ] 0
O_B_W DMA_READ [0 ] 0
O_B_W DMA_WRITE [0 ] 0
O_B_W Memory_Data [0 ] 0
O_B_W GETF [0 ] 0
NO_W GETX [0 ] 0
NO_W GETS [0 ] 0
NO_W PUT [0 ] 0
NO_W Pf_Replacement [0 ] 0
NO_W DMA_READ [0 ] 0
NO_W DMA_WRITE [0 ] 0
NO_W Memory_Data [0 ] 0
NO_W GETF [0 ] 0
O_W GETX [0 ] 0
O_W GETS [0 ] 0
O_W PUT [0 ] 0
O_W Pf_Replacement [0 ] 0
O_W DMA_READ [0 ] 0
O_W DMA_WRITE [0 ] 0
O_W Memory_Data [0 ] 0
O_W GETF [0 ] 0
NO_DW_B_W GETX [0 ] 0
NO_DW_B_W GETS [0 ] 0
NO_DW_B_W PUT [0 ] 0
NO_DW_B_W Pf_Replacement [0 ] 0
NO_DW_B_W DMA_READ [0 ] 0
NO_DW_B_W DMA_WRITE [0 ] 0
NO_DW_B_W Ack [0 ] 0
NO_DW_B_W Data [0 ] 0
NO_DW_B_W Exclusive_Data [0 ] 0
NO_DW_B_W All_acks_and_data_no_sharers [0 ] 0
NO_DW_B_W GETF [0 ] 0
NO_DR_B_W GETX [0 ] 0
NO_DR_B_W GETS [0 ] 0
NO_DR_B_W PUT [0 ] 0
NO_DR_B_W Pf_Replacement [0 ] 0
NO_DR_B_W DMA_READ [0 ] 0
NO_DR_B_W DMA_WRITE [0 ] 0
NO_DR_B_W Memory_Data [0 ] 0
NO_DR_B_W Ack [0 ] 0
NO_DR_B_W Shared_Ack [0 ] 0
NO_DR_B_W Shared_Data [0 ] 0
NO_DR_B_W Data [0 ] 0
NO_DR_B_W Exclusive_Data [0 ] 0
NO_DR_B_W GETF [0 ] 0
NO_DR_B_D GETX [0 ] 0
NO_DR_B_D GETS [0 ] 0
NO_DR_B_D PUT [0 ] 0
NO_DR_B_D Pf_Replacement [0 ] 0
NO_DR_B_D DMA_READ [0 ] 0
NO_DR_B_D DMA_WRITE [0 ] 0
NO_DR_B_D Ack [0 ] 0
NO_DR_B_D Shared_Ack [0 ] 0
NO_DR_B_D Shared_Data [0 ] 0
NO_DR_B_D Data [0 ] 0
NO_DR_B_D Exclusive_Data [0 ] 0
NO_DR_B_D All_acks_and_shared_data [0 ] 0
NO_DR_B_D All_acks_and_owner_data [0 ] 0
NO_DR_B_D All_acks_and_data_no_sharers [0 ] 0
NO_DR_B_D GETF [0 ] 0
NO_DR_B GETX [0 ] 0
NO_DR_B GETS [0 ] 0
NO_DR_B PUT [0 ] 0
NO_DR_B Pf_Replacement [0 ] 0
NO_DR_B DMA_READ [0 ] 0
NO_DR_B DMA_WRITE [0 ] 0
NO_DR_B Ack [0 ] 0
NO_DR_B Shared_Ack [0 ] 0
NO_DR_B Shared_Data [0 ] 0
NO_DR_B Data [0 ] 0
NO_DR_B Exclusive_Data [0 ] 0
NO_DR_B All_acks_and_shared_data [0 ] 0
NO_DR_B All_acks_and_owner_data [0 ] 0
NO_DR_B All_acks_and_data_no_sharers [0 ] 0
NO_DR_B GETF [0 ] 0
NO_DW_W GETX [0 ] 0
NO_DW_W GETS [0 ] 0
NO_DW_W PUT [0 ] 0
NO_DW_W Pf_Replacement [0 ] 0
NO_DW_W DMA_READ [0 ] 0
NO_DW_W DMA_WRITE [0 ] 0
NO_DW_W Memory_Ack [0 ] 0
NO_DW_W GETF [0 ] 0
O_DR_B_W GETX [0 ] 0
O_DR_B_W GETS [0 ] 0
O_DR_B_W PUT [0 ] 0
O_DR_B_W Pf_Replacement [0 ] 0
O_DR_B_W DMA_READ [0 ] 0
O_DR_B_W DMA_WRITE [0 ] 0
O_DR_B_W Memory_Data [0 ] 0
O_DR_B_W Ack [0 ] 0
O_DR_B_W Shared_Ack [0 ] 0
O_DR_B_W GETF [0 ] 0
O_DR_B GETX [0 ] 0
O_DR_B GETS [0 ] 0
O_DR_B PUT [0 ] 0
O_DR_B Pf_Replacement [0 ] 0
O_DR_B DMA_READ [0 ] 0
O_DR_B DMA_WRITE [0 ] 0
O_DR_B Ack [0 ] 0
O_DR_B Shared_Ack [0 ] 0
O_DR_B All_acks_and_owner_data [0 ] 0
O_DR_B All_acks_and_data_no_sharers [0 ] 0
O_DR_B GETF [0 ] 0
WB GETX [4 ] 4
WB GETS [14 ] 14
WB PUT [0 ] 0
WB Unblock [0 ] 0
WB Writeback_Clean [0 ] 0
WB Writeback_Dirty [0 ] 0
WB Writeback_Exclusive_Clean [344 ] 344
WB Writeback_Exclusive_Dirty [81 ] 81
WB Pf_Replacement [0 ] 0
WB DMA_READ [0 ] 0
WB DMA_WRITE [0 ] 0
WB GETF [0 ] 0
WB_O_W GETX [0 ] 0
WB_O_W GETS [0 ] 0
WB_O_W PUT [0 ] 0
WB_O_W Pf_Replacement [0 ] 0
WB_O_W DMA_READ [0 ] 0
WB_O_W DMA_WRITE [0 ] 0
WB_O_W Memory_Ack [0 ] 0
WB_O_W GETF [0 ] 0
WB_E_W GETX [2 ] 2
WB_E_W GETS [2 ] 2
WB_E_W PUT [0 ] 0
WB_E_W Pf_Replacement [0 ] 0
WB_E_W DMA_READ [0 ] 0
WB_E_W DMA_WRITE [0 ] 0
WB_E_W Memory_Ack [81 ] 81
WB_E_W GETF [0 ] 0
NO_F GETX [0 ] 0
NO_F GETS [0 ] 0
NO_F PUT [0 ] 0
NO_F UnblockM [0 ] 0
NO_F Pf_Replacement [0 ] 0
NO_F GETF [0 ] 0
NO_F PUTF [0 ] 0
NO_F_W GETX [0 ] 0
NO_F_W GETS [0 ] 0
NO_F_W PUT [0 ] 0
NO_F_W Pf_Replacement [0 ] 0
NO_F_W DMA_READ [0 ] 0
NO_F_W DMA_WRITE [0 ] 0
NO_F_W Memory_Data [0 ] 0
NO_F_W GETF [0 ] 0

3
simulators/gem5/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simerr Executable file
View File

@ -0,0 +1,3 @@
warn: Sockets disabled, not accepting gdb connections
warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
hack: be nice to actually delete the event here

12
simulators/gem5/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout Executable file
View File

@ -0,0 +1,12 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 4 2012 11:51:44
gem5 started Jun 4 2012 13:42:34
gem5 executing on zizzer
command line: build/ALPHA_MOESI_hammer/gem5.opt -d build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer -re tests/run.py build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello world!
Exiting @ tick 78448 because target called exit()

92
simulators/gem5/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt Normal file
View File

@ -0,0 +1,92 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000078 # Number of seconds simulated
sim_ticks 78448 # Number of ticks simulated
final_tick 78448 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
host_inst_rate 9618 # Simulator instruction rate (inst/s)
host_op_rate 9618 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 292754 # Simulator tick rate (ticks/s)
host_mem_usage 222892 # Number of bytes of host memory used
host_seconds 0.27 # Real time elapsed on the host
sim_insts 2577 # Number of instructions simulated
sim_ops 2577 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 10340 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 3016 # Number of bytes read from this memory
system.physmem.bytes_read::total 13356 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 10340 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 10340 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 2058 # Number of bytes written to this memory
system.physmem.bytes_written::total 2058 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 2585 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 415 # Number of read requests responded to by this memory
system.physmem.num_reads::total 3000 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 294 # Number of write requests responded to by this memory
system.physmem.num_writes::total 294 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 131807057 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 38445849 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 170252906 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 131807057 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 131807057 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 26233938 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 26233938 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 131807057 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 64679788 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 196486845 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 415 # DTB read hits
system.cpu.dtb.read_misses 4 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 419 # DTB read accesses
system.cpu.dtb.write_hits 294 # DTB write hits
system.cpu.dtb.write_misses 4 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 298 # DTB write accesses
system.cpu.dtb.data_hits 709 # DTB hits
system.cpu.dtb.data_misses 8 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 717 # DTB accesses
system.cpu.itb.fetch_hits 2586 # ITB hits
system.cpu.itb.fetch_misses 11 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 2597 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 4 # Number of system calls
system.cpu.numCycles 78448 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 2577 # Number of instructions committed
system.cpu.committedOps 2577 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses
system.cpu.num_func_calls 140 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 238 # number of instructions that are conditional controls
system.cpu.num_int_insts 2375 # number of integer instructions
system.cpu.num_fp_insts 6 # number of float instructions
system.cpu.num_int_register_reads 2998 # number of times the integer registers were read
system.cpu.num_int_register_writes 1768 # number of times the integer registers were written
system.cpu.num_fp_register_reads 6 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_mem_refs 717 # number of memory refs
system.cpu.num_load_insts 419 # Number of load instructions
system.cpu.num_store_insts 298 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 78448 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
---------- End Simulation Statistics ----------

284
simulators/gem5/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini Normal file
View File

@ -0,0 +1,284 @@
[root]
type=Root
children=system
full_system=false
time_sync_enable=false
time_sync_period=100000000
time_sync_spin_threshold=100000
[system]
type=System
children=cpu dir_cntrl0 l1_cntrl0 physmem ruby sys_port_proxy
boot_osflags=a
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=timing
memories=system.physmem
num_work_ids=16
readfile=
symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.sys_port_proxy.slave[0]
[system.cpu]
type=TimingSimpleCPU
children=dtb interrupts itb tracer workload
checker=Null
clock=1
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
phase=0
profile=0
progress_interval=0
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
dcache_port=system.l1_cntrl0.sequencer.slave[1]
icache_port=system.l1_cntrl0.sequencer.slave[0]
[system.cpu.dtb]
type=AlphaTLB
size=64
[system.cpu.interrupts]
type=AlphaInterrupts
[system.cpu.itb]
type=AlphaTLB
size=48
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=hello
cwd=
egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello
gid=100
input=cin
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=0
system=system
uid=100
[system.dir_cntrl0]
type=Directory_Controller
children=directory memBuffer
buffer_size=0
cntrl_id=1
directory=system.dir_cntrl0.directory
directory_latency=12
memBuffer=system.dir_cntrl0.memBuffer
number_of_TBEs=256
recycle_latency=10
ruby_system=system.ruby
transitions_per_cycle=32
version=0
[system.dir_cntrl0.directory]
type=RubyDirectoryMemory
map_levels=4
numa_high_bit=6
size=134217728
use_map=false
version=0
[system.dir_cntrl0.memBuffer]
type=RubyMemoryControl
bank_bit_0=8
bank_busy_time=11
bank_queue_size=12
banks_per_rank=8
basic_bus_busy_time=2
dimm_bit_0=12
dimms_per_channel=2
mem_bus_cycle_multiplier=10
mem_ctl_latency=12
mem_fixed_delay=0
mem_random_arbitrate=0
rank_bit_0=11
rank_rank_delay=1
ranks_per_dimm=2
read_write_delay=2
refresh_period=1560
tFaw=0
version=0
[system.l1_cntrl0]
type=L1Cache_Controller
children=cacheMemory sequencer
buffer_size=0
cacheMemory=system.l1_cntrl0.cacheMemory
cache_response_latency=12
cntrl_id=0
issue_latency=2
number_of_TBEs=256
recycle_latency=10
ruby_system=system.ruby
send_evictions=false
sequencer=system.l1_cntrl0.sequencer
transitions_per_cycle=32
version=0
[system.l1_cntrl0.cacheMemory]
type=RubyCache
assoc=2
is_icache=false
latency=3
replacement_policy=PSEUDO_LRU
size=256
start_index_bit=6
[system.l1_cntrl0.sequencer]
type=RubySequencer
access_phys_mem=true
dcache=system.l1_cntrl0.cacheMemory
deadlock_threshold=500000
icache=system.l1_cntrl0.cacheMemory
max_outstanding_requests=16
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
system=system
using_network_tester=false
using_ruby_tester=false
version=0
slave=system.cpu.icache_port system.cpu.dcache_port
[system.physmem]
type=SimpleMemory
conf_table_reported=false
file=
in_addr_map=true
latency=30
latency_var=0
null=false
range=0:134217727
zero=false
[system.ruby]
type=RubySystem
children=network profiler
block_size_bytes=64
clock=1
mem_size=134217728
no_mem_vec=false
random_seed=1234
randomization=false
stats_filename=ruby.stats
[system.ruby.network]
type=SimpleNetwork
children=topology
adaptive_routing=false
buffer_size=0
control_msg_size=8
endpoint_bandwidth=1000
number_of_virtual_networks=10
ruby_system=system.ruby
topology=system.ruby.network.topology
[system.ruby.network.topology]
type=Topology
children=ext_links0 ext_links1 int_links0 int_links1 routers0 routers1 routers2
description=Crossbar
ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1
int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1
print_config=false
routers=system.ruby.network.topology.routers0 system.ruby.network.topology.routers1 system.ruby.network.topology.routers2
[system.ruby.network.topology.ext_links0]
type=SimpleExtLink
bandwidth_factor=16
ext_node=system.l1_cntrl0
int_node=system.ruby.network.topology.routers0
latency=1
link_id=0
weight=1
[system.ruby.network.topology.ext_links1]
type=SimpleExtLink
bandwidth_factor=16
ext_node=system.dir_cntrl0
int_node=system.ruby.network.topology.routers1
latency=1
link_id=1
weight=1
[system.ruby.network.topology.int_links0]
type=SimpleIntLink
bandwidth_factor=16
latency=1
link_id=2
node_a=system.ruby.network.topology.routers0
node_b=system.ruby.network.topology.routers2
weight=1
[system.ruby.network.topology.int_links1]
type=SimpleIntLink
bandwidth_factor=16
latency=1
link_id=3
node_a=system.ruby.network.topology.routers1
node_b=system.ruby.network.topology.routers2
weight=1
[system.ruby.network.topology.routers0]
type=BasicRouter
router_id=0
[system.ruby.network.topology.routers1]
type=BasicRouter
router_id=1
[system.ruby.network.topology.routers2]
type=BasicRouter
router_id=2
[system.ruby.profiler]
type=RubyProfiler
all_instructions=false
hot_lines=false
num_of_sequencers=1
ruby_system=system.ruby
[system.sys_port_proxy]
type=RubyPortProxy
access_phys_mem=true
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
system=system
using_network_tester=false
using_ruby_tester=false
version=0
slave=system.system_port

311
simulators/gem5/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/ruby.stats Normal file
View File

@ -0,0 +1,311 @@
================ Begin RubySystem Configuration Print ================
RubySystem config:
random_seed: 1234
randomization: 0
cycle_period: 1
block_size_bytes: 64
block_size_bits: 6
memory_size_bytes: 134217728
memory_size_bits: 27
Network Configuration
---------------------
network: SIMPLE_NETWORK
topology:
virtual_net_0: active, ordered
virtual_net_1: active, ordered
virtual_net_2: active, ordered
virtual_net_3: active, ordered
virtual_net_4: active, ordered
virtual_net_5: inactive
virtual_net_6: inactive
virtual_net_7: inactive
virtual_net_8: inactive
virtual_net_9: inactive
Profiler Configuration
----------------------
periodic_stats_period: 1000000
================ End RubySystem Configuration Print ================
Real time: Jun/04/2012 14:06:25
Profiler Stats
--------------
Elapsed_time_in_seconds: 1
Elapsed_time_in_minutes: 0.0166667
Elapsed_time_in_hours: 0.000277778
Elapsed_time_in_days: 1.15741e-05
Virtual_time_in_seconds: 0.26
Virtual_time_in_minutes: 0.00433333
Virtual_time_in_hours: 7.22222e-05
Virtual_time_in_days: 3.00926e-06
Ruby_current_time: 123378
Ruby_start_time: 0
Ruby_cycles: 123378
mbytes_resident: 46.1406
mbytes_total: 217.871
resident_ratio: 0.211779
ruby_cycles_executed: [ 123379 ]
Busy Controller Counts:
L1Cache-0:0
Directory-0:0
Busy Bank Count:0
sequencer_requests_outstanding: [binsize: 1 max: 1 count: 3295 average: 1 | standard deviation: 0 | 0 3295 ]
All Non-Zero Cycle Demand Cache Accesses
----------------------------------------
miss_latency: [binsize: 2 max: 375 count: 3294 average: 36.4554 | standard deviation: 69.7725 | 0 2668 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 0 0 0 3 1 1 4 2 101 88 63 177 126 0 1 1 8 0 2 1 1 4 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 4 5 13 2 0 0 0 1 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 ]
miss_latency_LD: [binsize: 2 max: 281 count: 415 average: 107.304 | standard deviation: 88.8453 | 0 170 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 0 2 0 56 24 27 75 32 0 0 1 3 0 1 0 0 2 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 0 4 7 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
miss_latency_ST: [binsize: 2 max: 265 count: 294 average: 53.2585 | standard deviation: 80.456 | 0 210 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 14 11 7 31 12 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
miss_latency_IFETCH: [binsize: 2 max: 375 count: 2585 average: 23.1702 | standard deviation: 56.4841 | 0 2288 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 2 0 0 2 2 31 53 29 71 82 0 1 0 5 0 1 1 1 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 2 1 3 2 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
miss_latency_L1Cache: [binsize: 1 max: 3 count: 2668 average: 3 | standard deviation: 0 | 0 0 0 2668 ]
miss_latency_Directory: [binsize: 2 max: 375 count: 626 average: 179.042 | standard deviation: 22.5462 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 0 0 0 3 1 1 4 2 101 88 63 177 126 0 1 1 8 0 2 1 1 4 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 4 5 13 2 0 0 0 1 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 ]
miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
imcomplete_wCC_Times: 0
miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ]
miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ]
miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ]
miss_latency_dir_first_response_to_completion: [binsize: 1 max: 159 count: 1 average: 159 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
imcomplete_dir_Times: 625
miss_latency_LD_L1Cache: [binsize: 1 max: 3 count: 170 average: 3 | standard deviation: 0 | 0 0 0 170 ]
miss_latency_LD_Directory: [binsize: 2 max: 281 count: 245 average: 179.678 | standard deviation: 23.5327 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 0 2 0 56 24 27 75 32 0 0 1 3 0 1 0 0 2 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 0 4 7 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
miss_latency_ST_L1Cache: [binsize: 1 max: 3 count: 210 average: 3 | standard deviation: 0 | 0 0 0 210 ]
miss_latency_ST_Directory: [binsize: 2 max: 265 count: 84 average: 178.905 | standard deviation: 21.977 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 14 11 7 31 12 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
miss_latency_IFETCH_L1Cache: [binsize: 1 max: 3 count: 2288 average: 3 | standard deviation: 0 | 0 0 0 2288 ]
miss_latency_IFETCH_Directory: [binsize: 2 max: 375 count: 297 average: 178.556 | standard deviation: 21.9279 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 2 0 0 2 2 31 53 29 71 82 0 1 0 5 0 1 1 1 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 2 1 3 2 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
All Non-Zero Cycle SW Prefetch Requests
------------------------------------
prefetch_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
prefetch_latency_L2Miss:[binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
Request vs. RubySystem State Profile
--------------------------------
filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
Message Delayed Cycles
----------------------
Total_delay_cycles: [binsize: 1 max: 0 count: 1248 average: 0 | standard deviation: 0 | 1248 ]
Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 1248 average: 0 | standard deviation: 0 | 1248 ]
virtual_network_0_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 626 average: 0 | standard deviation: 0 | 626 ]
virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 622 average: 0 | standard deviation: 0 | 622 ]
virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
virtual_network_6_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
virtual_network_7_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
virtual_network_8_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
virtual_network_9_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
Resource Usage
--------------
page_size: 4096
user_time: 0
system_time: 0
page_reclaims: 12216
page_faults: 0
swaps: 0
block_inputs: 0
block_outputs: 88
Network Stats
-------------
total_msg_count_Control: 1878 15024
total_msg_count_Data: 1866 134352
total_msg_count_Response_Data: 1878 135216
total_msg_count_Writeback_Control: 1866 14928
total_msgs: 7488 total_bytes: 299520
switch_0_inlinks: 2
switch_0_outlinks: 2
links_utilized_percent_switch_0: 2.52881
links_utilized_percent_switch_0_link_0: 2.5353 bw: 16000 base_latency: 1
links_utilized_percent_switch_0_link_1: 2.52233 bw: 16000 base_latency: 1
outgoing_messages_switch_0_link_0_Response_Data: 626 45072 [ 0 0 0 0 626 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_0_link_0_Writeback_Control: 622 4976 [ 0 0 0 622 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_0_link_1_Control: 626 5008 [ 0 0 626 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_0_link_1_Data: 622 44784 [ 0 0 622 0 0 0 0 0 0 0 ] base_latency: 1
switch_1_inlinks: 2
switch_1_outlinks: 2
links_utilized_percent_switch_1: 2.52881
links_utilized_percent_switch_1_link_0: 2.52233 bw: 16000 base_latency: 1
links_utilized_percent_switch_1_link_1: 2.5353 bw: 16000 base_latency: 1
outgoing_messages_switch_1_link_0_Control: 626 5008 [ 0 0 626 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_1_link_0_Data: 622 44784 [ 0 0 622 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_1_link_1_Response_Data: 626 45072 [ 0 0 0 0 626 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_1_link_1_Writeback_Control: 622 4976 [ 0 0 0 622 0 0 0 0 0 0 ] base_latency: 1
switch_2_inlinks: 2
switch_2_outlinks: 2
links_utilized_percent_switch_2: 2.52881
links_utilized_percent_switch_2_link_0: 2.5353 bw: 16000 base_latency: 1
links_utilized_percent_switch_2_link_1: 2.52233 bw: 16000 base_latency: 1
outgoing_messages_switch_2_link_0_Response_Data: 626 45072 [ 0 0 0 0 626 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_2_link_0_Writeback_Control: 622 4976 [ 0 0 0 622 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_2_link_1_Control: 626 5008 [ 0 0 626 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_2_link_1_Data: 622 44784 [ 0 0 622 0 0 0 0 0 0 0 ] base_latency: 1
Cache Stats: system.l1_cntrl0.cacheMemory
system.l1_cntrl0.cacheMemory_total_misses: 626
system.l1_cntrl0.cacheMemory_total_demand_misses: 626
system.l1_cntrl0.cacheMemory_total_prefetches: 0
system.l1_cntrl0.cacheMemory_total_sw_prefetches: 0
system.l1_cntrl0.cacheMemory_total_hw_prefetches: 0
system.l1_cntrl0.cacheMemory_request_type_LD: 39.1374%
system.l1_cntrl0.cacheMemory_request_type_ST: 13.4185%
system.l1_cntrl0.cacheMemory_request_type_IFETCH: 47.4441%
system.l1_cntrl0.cacheMemory_access_mode_type_Supervisor: 626 100%
--- L1Cache ---
- Event Counts -
Load [415 ] 415
Ifetch [2585 ] 2585
Store [294 ] 294
Data [626 ] 626
Fwd_GETX [0 ] 0
Inv [0 ] 0
Replacement [622 ] 622
Writeback_Ack [622 ] 622
Writeback_Nack [0 ] 0
- Transitions -
I Load [245 ] 245
I Ifetch [297 ] 297
I Store [84 ] 84
I Inv [0 ] 0
I Replacement [0 ] 0
II Writeback_Nack [0 ] 0
M Load [170 ] 170
M Ifetch [2288 ] 2288
M Store [210 ] 210
M Fwd_GETX [0 ] 0
M Inv [0 ] 0
M Replacement [622 ] 622
MI Fwd_GETX [0 ] 0
MI Inv [0 ] 0
MI Writeback_Ack [622 ] 622
MI Writeback_Nack [0 ] 0
MII Fwd_GETX [0 ] 0
IS Data [542 ] 542
IM Data [84 ] 84
Memory controller: system.dir_cntrl0.memBuffer:
memory_total_requests: 1248
memory_reads: 626
memory_writes: 622
memory_refreshes: 258
memory_total_request_delays: 1502
memory_delays_per_request: 1.20353
memory_delays_in_input_queue: 414
memory_delays_behind_head_of_bank_queue: 3
memory_delays_stalled_at_head_of_bank_queue: 1085
memory_stalls_for_bank_busy: 404
memory_stalls_for_random_busy: 0
memory_stalls_for_anti_starvation: 0
memory_stalls_for_arbitration: 39
memory_stalls_for_bus: 620
memory_stalls_for_tfaw: 0
memory_stalls_for_read_write_turnaround: 22
memory_stalls_for_read_read_turnaround: 0
accesses_per_bank: 55 40 0 100 42 42 88 45 14 10 14 10 46 82 38 6 22 14 14 48 20 52 26 92 34 10 12 24 28 44 38 138
--- Directory ---
- Event Counts -
GETX [626 ] 626
GETS [0 ] 0
PUTX [622 ] 622
PUTX_NotOwner [0 ] 0
DMA_READ [0 ] 0
DMA_WRITE [0 ] 0
Memory_Data [626 ] 626
Memory_Ack [622 ] 622
- Transitions -
I GETX [626 ] 626
I PUTX_NotOwner [0 ] 0
I DMA_READ [0 ] 0
I DMA_WRITE [0 ] 0
M GETX [0 ] 0
M PUTX [622 ] 622
M PUTX_NotOwner [0 ] 0
M DMA_READ [0 ] 0
M DMA_WRITE [0 ] 0
M_DRD GETX [0 ] 0
M_DRD PUTX [0 ] 0
M_DWR GETX [0 ] 0
M_DWR PUTX [0 ] 0
M_DWRI GETX [0 ] 0
M_DWRI Memory_Ack [0 ] 0
M_DRDI GETX [0 ] 0
M_DRDI Memory_Ack [0 ] 0
IM GETX [0 ] 0
IM GETS [0 ] 0
IM PUTX [0 ] 0
IM PUTX_NotOwner [0 ] 0
IM DMA_READ [0 ] 0
IM DMA_WRITE [0 ] 0
IM Memory_Data [626 ] 626
MI GETX [0 ] 0
MI GETS [0 ] 0
MI PUTX [0 ] 0
MI PUTX_NotOwner [0 ] 0
MI DMA_READ [0 ] 0
MI DMA_WRITE [0 ] 0
MI Memory_Ack [622 ] 622
ID GETX [0 ] 0
ID GETS [0 ] 0
ID PUTX [0 ] 0
ID PUTX_NotOwner [0 ] 0
ID DMA_READ [0 ] 0
ID DMA_WRITE [0 ] 0
ID Memory_Data [0 ] 0
ID_W GETX [0 ] 0
ID_W GETS [0 ] 0
ID_W PUTX [0 ] 0
ID_W PUTX_NotOwner [0 ] 0
ID_W DMA_READ [0 ] 0
ID_W DMA_WRITE [0 ] 0
ID_W Memory_Ack [0 ] 0

3
simulators/gem5/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simerr Executable file
View File

@ -0,0 +1,3 @@
warn: Sockets disabled, not accepting gdb connections
warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
hack: be nice to actually delete the event here

12
simulators/gem5/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simout Executable file
View File

@ -0,0 +1,12 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 4 2012 11:50:11
gem5 started Jun 4 2012 14:06:24
gem5 executing on zizzer
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello world!
Exiting @ tick 123378 because target called exit()

92
simulators/gem5/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt Normal file
View File

@ -0,0 +1,92 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000123 # Number of seconds simulated
sim_ticks 123378 # Number of ticks simulated
final_tick 123378 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
host_inst_rate 56001 # Simulator instruction rate (inst/s)
host_op_rate 55979 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 2679090 # Simulator tick rate (ticks/s)
host_mem_usage 223104 # Number of bytes of host memory used
host_seconds 0.05 # Real time elapsed on the host
sim_insts 2577 # Number of instructions simulated
sim_ops 2577 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 10340 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 3016 # Number of bytes read from this memory
system.physmem.bytes_read::total 13356 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 10340 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 10340 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 2058 # Number of bytes written to this memory
system.physmem.bytes_written::total 2058 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 2585 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 415 # Number of read requests responded to by this memory
system.physmem.num_reads::total 3000 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 294 # Number of write requests responded to by this memory
system.physmem.num_writes::total 294 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 83807486 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 24445201 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 108252687 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 83807486 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 83807486 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 16680445 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 16680445 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 83807486 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 41125646 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 124933132 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 415 # DTB read hits
system.cpu.dtb.read_misses 4 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 419 # DTB read accesses
system.cpu.dtb.write_hits 294 # DTB write hits
system.cpu.dtb.write_misses 4 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 298 # DTB write accesses
system.cpu.dtb.data_hits 709 # DTB hits
system.cpu.dtb.data_misses 8 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 717 # DTB accesses
system.cpu.itb.fetch_hits 2586 # ITB hits
system.cpu.itb.fetch_misses 11 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 2597 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 4 # Number of system calls
system.cpu.numCycles 123378 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 2577 # Number of instructions committed
system.cpu.committedOps 2577 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses
system.cpu.num_func_calls 140 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 238 # number of instructions that are conditional controls
system.cpu.num_int_insts 2375 # number of integer instructions
system.cpu.num_fp_insts 6 # number of float instructions
system.cpu.num_int_register_reads 2998 # number of times the integer registers were read
system.cpu.num_int_register_writes 1768 # number of times the integer registers were written
system.cpu.num_fp_register_reads 6 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_mem_refs 717 # number of memory refs
system.cpu.num_load_insts 419 # Number of load instructions
system.cpu.num_store_insts 298 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 123378 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
---------- End Simulation Statistics ----------

198
simulators/gem5/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini Normal file
View File

@ -0,0 +1,198 @@
[root]
type=Root
children=system
full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
boot_osflags=a
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
readfile=
symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.cpu]
type=TimingSimpleCPU
children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
phase=0
profile=0
progress_interval=0
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=262144
subblock_size=0
system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
[system.cpu.dtb]
type=AlphaTLB
size=64
[system.cpu.icache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=131072
subblock_size=0
system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.interrupts]
type=AlphaInterrupts
[system.cpu.itb]
type=AlphaTLB
size=48
[system.cpu.l2cache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=false
latency=10000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=2097152
subblock_size=0
system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
[system.cpu.toL2Bus]
type=CoherentBus
block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=hello
cwd=
egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello
gid=100
input=cin
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=0
system=system
uid=100
[system.membus]
type=CoherentBus
block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
master=system.physmem.port[0]
slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=SimpleMemory
conf_table_reported=false
file=
in_addr_map=true
latency=30000
latency_var=0
null=false
range=0:134217727
zero=false
port=system.membus.master[0]

3
simulators/gem5/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simerr Executable file
View File

@ -0,0 +1,3 @@
warn: Sockets disabled, not accepting gdb connections
warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
hack: be nice to actually delete the event here

12
simulators/gem5/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simout Executable file
View File

@ -0,0 +1,12 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 4 2012 11:50:11
gem5 started Jun 4 2012 14:39:41
gem5 executing on zizzer
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello world!
Exiting @ tick 16769000 because target called exit()

381
simulators/gem5/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt Normal file
View File

@ -0,0 +1,381 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000017 # Number of seconds simulated
sim_ticks 16769000 # Number of ticks simulated
final_tick 16769000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 308591 # Simulator instruction rate (inst/s)
host_op_rate 307918 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1999557615 # Simulator tick rate (ticks/s)
host_mem_usage 213304 # Number of bytes of host memory used
host_seconds 0.01 # Real time elapsed on the host
sim_insts 2577 # Number of instructions simulated
sim_ops 2577 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 10432 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 5248 # Number of bytes read from this memory
system.physmem.bytes_read::total 15680 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 10432 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 10432 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 163 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 82 # Number of read requests responded to by this memory
system.physmem.num_reads::total 245 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 622100304 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 312958435 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 935058739 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 622100304 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 622100304 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 622100304 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 312958435 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 935058739 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 415 # DTB read hits
system.cpu.dtb.read_misses 4 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 419 # DTB read accesses
system.cpu.dtb.write_hits 294 # DTB write hits
system.cpu.dtb.write_misses 4 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 298 # DTB write accesses
system.cpu.dtb.data_hits 709 # DTB hits
system.cpu.dtb.data_misses 8 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 717 # DTB accesses
system.cpu.itb.fetch_hits 2586 # ITB hits
system.cpu.itb.fetch_misses 11 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 2597 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 4 # Number of system calls
system.cpu.numCycles 33538 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 2577 # Number of instructions committed
system.cpu.committedOps 2577 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses
system.cpu.num_func_calls 140 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 238 # number of instructions that are conditional controls
system.cpu.num_int_insts 2375 # number of integer instructions
system.cpu.num_fp_insts 6 # number of float instructions
system.cpu.num_int_register_reads 2998 # number of times the integer registers were read
system.cpu.num_int_register_writes 1768 # number of times the integer registers were written
system.cpu.num_fp_register_reads 6 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_mem_refs 717 # number of memory refs
system.cpu.num_load_insts 419 # Number of load instructions
system.cpu.num_store_insts 298 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 33538 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.icache.replacements 0 # number of replacements
system.cpu.icache.tagsinuse 80.003762 # Cycle average of tags in use
system.cpu.icache.total_refs 2423 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 163 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 14.865031 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 80.003762 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.039064 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.039064 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 2423 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 2423 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 2423 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 2423 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 2423 # number of overall hits
system.cpu.icache.overall_hits::total 2423 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 163 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 163 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 163 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 163 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 163 # number of overall misses
system.cpu.icache.overall_misses::total 163 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 9128000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 9128000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 9128000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 9128000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 9128000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 9128000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 2586 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 2586 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 2586 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 2586 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 2586 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 2586 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.063032 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.063032 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.063032 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.063032 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.063032 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.063032 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56000 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 56000 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 56000 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 56000 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 56000 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 56000 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 163 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 163 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 163 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 163 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 163 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 163 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 8639000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 8639000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 8639000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 8639000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 8639000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 8639000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.063032 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.063032 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.063032 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.063032 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.063032 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.063032 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53000 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.tagsinuse 47.418751 # Cycle average of tags in use
system.cpu.dcache.total_refs 627 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 82 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 7.646341 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 47.418751 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.011577 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.011577 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 360 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 360 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 267 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 267 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 627 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 627 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 627 # number of overall hits
system.cpu.dcache.overall_hits::total 627 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 55 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 55 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 27 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 27 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 82 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 82 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 82 # number of overall misses
system.cpu.dcache.overall_misses::total 82 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 3080000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 3080000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 1512000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 1512000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 4592000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 4592000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 4592000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 4592000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 415 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 415 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 294 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 709 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 709 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 709 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 709 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.132530 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.132530 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.091837 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.091837 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.115656 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.115656 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.115656 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.115656 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56000 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 56000 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56000 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 56000 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 56000 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 56000 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 56000 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 56000 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 55 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 27 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 27 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 82 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 82 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 82 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 82 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2915000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2915000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1431000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 1431000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4346000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 4346000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4346000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 4346000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.132530 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.132530 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.091837 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.091837 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.115656 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.115656 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.115656 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.115656 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 107.101205 # Cycle average of tags in use
system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 218 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::cpu.inst 80.120406 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 26.980800 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::cpu.inst 0.002445 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.000823 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.003268 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_misses::cpu.inst 163 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 55 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 218 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 27 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 27 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 163 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 82 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 245 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 163 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 82 # number of overall misses
system.cpu.l2cache.overall_misses::total 245 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 8476000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2860000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 11336000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1404000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 1404000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 8476000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 4264000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 12740000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 8476000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 4264000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 12740000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 163 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 55 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 218 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 27 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 27 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 163 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 82 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 245 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 163 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 82 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 245 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 1 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 163 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 218 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 27 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 27 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 163 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 82 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 245 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 163 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 82 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 245 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 6520000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2200000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 8720000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1080000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1080000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 6520000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3280000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 9800000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 6520000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3280000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 9800000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

606
simulators/gem5/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini Normal file
View File

@ -0,0 +1,606 @@
[root]
type=Root
children=system
full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
boot_osflags=a
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
readfile=
symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.cpu]
type=DerivO3CPU
children=checker dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
LSQDepCheckShift=4
RASSize=16
SQEntries=32
SSITSize=1024
activity=0
backComSize=5
cachePorts=200
checker=system.cpu.checker
choiceCtrBits=2
choicePredictorSize=8192
clock=500
commitToDecodeDelay=1
commitToFetchDelay=1
commitToIEWDelay=1
commitToRenameDelay=1
commitWidth=8
cpu_id=0
decodeToFetchDelay=1
decodeToRenameDelay=1
decodeWidth=8
defer_registration=false
dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
fetchToDecodeDelay=1
fetchTrapLatency=1
fetchWidth=8
forwardComSize=5
fuPool=system.cpu.fuPool
function_trace=false
function_trace_start=0
globalCtrBits=2
globalHistoryBits=13
globalPredictorSize=8192
iewToCommitDelay=1
iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
instShiftAmt=2
interrupts=system.cpu.interrupts
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
localCtrBits=2
localHistoryBits=11
localHistoryTableSize=2048
localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
needsTSO=false
numIQEntries=64
numPhysFloatRegs=256
numPhysIntRegs=256
numROBEntries=192
numRobs=1
numThreads=1
phase=0
predType=tournament
profile=0
progress_interval=0
renameToDecodeDelay=1
renameToFetchDelay=1
renameToIEWDelay=2
renameToROBDelay=1
renameWidth=8
smtCommitPolicy=RoundRobin
smtFetchPolicy=SingleThread
smtIQPolicy=Partitioned
smtIQThreshold=100
smtLSQPolicy=Partitioned
smtLSQThreshold=100
smtNumFetchingThreads=1
smtROBPolicy=Partitioned
smtROBThreshold=100
squashWidth=8
store_set_clear_period=250000
system=system
tracer=system.cpu.tracer
trapLatency=13
wbDepth=1
wbWidth=8
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.checker]
type=O3Checker
children=dtb itb tracer
checker=Null
clock=1
cpu_id=-1
defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.checker.dtb
exitOnError=false
function_trace=false
function_trace_start=0
interrupts=Null
itb=system.cpu.checker.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
phase=0
profile=0
progress_interval=0
system=system
tracer=system.cpu.checker.tracer
updateOnError=true
warnOnlyOnLoadError=true
workload=system.cpu.workload
[system.cpu.checker.dtb]
type=ArmTLB
children=walker
size=64
walker=system.cpu.checker.dtb.walker
[system.cpu.checker.dtb.walker]
type=ArmTableWalker
max_backoff=100000
min_backoff=0
sys=system
port=system.cpu.toL2Bus.slave[5]
[system.cpu.checker.itb]
type=ArmTLB
children=walker
size=64
walker=system.cpu.checker.itb.walker
[system.cpu.checker.itb.walker]
type=ArmTableWalker
max_backoff=100000
min_backoff=0
sys=system
port=system.cpu.toL2Bus.slave[4]
[system.cpu.checker.tracer]
type=ExeTracer
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=262144
subblock_size=0
system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
[system.cpu.dtb]
type=ArmTLB
children=walker
size=64
walker=system.cpu.dtb.walker
[system.cpu.dtb.walker]
type=ArmTableWalker
max_backoff=100000
min_backoff=0
sys=system
port=system.cpu.toL2Bus.slave[3]
[system.cpu.fuPool]
type=FUPool
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
[system.cpu.fuPool.FUList0]
type=FUDesc
children=opList
count=6
opList=system.cpu.fuPool.FUList0.opList
[system.cpu.fuPool.FUList0.opList]
type=OpDesc
issueLat=1
opClass=IntAlu
opLat=1
[system.cpu.fuPool.FUList1]
type=FUDesc
children=opList0 opList1
count=2
opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
[system.cpu.fuPool.FUList1.opList0]
type=OpDesc
issueLat=1
opClass=IntMult
opLat=3
[system.cpu.fuPool.FUList1.opList1]
type=OpDesc
issueLat=19
opClass=IntDiv
opLat=20
[system.cpu.fuPool.FUList2]
type=FUDesc
children=opList0 opList1 opList2
count=4
opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
[system.cpu.fuPool.FUList2.opList0]
type=OpDesc
issueLat=1
opClass=FloatAdd
opLat=2
[system.cpu.fuPool.FUList2.opList1]
type=OpDesc
issueLat=1
opClass=FloatCmp
opLat=2
[system.cpu.fuPool.FUList2.opList2]
type=OpDesc
issueLat=1
opClass=FloatCvt
opLat=2
[system.cpu.fuPool.FUList3]
type=FUDesc
children=opList0 opList1 opList2
count=2
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
[system.cpu.fuPool.FUList3.opList0]
type=OpDesc
issueLat=1
opClass=FloatMult
opLat=4
[system.cpu.fuPool.FUList3.opList1]
type=OpDesc
issueLat=12
opClass=FloatDiv
opLat=12
[system.cpu.fuPool.FUList3.opList2]
type=OpDesc
issueLat=24
opClass=FloatSqrt
opLat=24
[system.cpu.fuPool.FUList4]
type=FUDesc
children=opList
count=0
opList=system.cpu.fuPool.FUList4.opList
[system.cpu.fuPool.FUList4.opList]
type=OpDesc
issueLat=1
opClass=MemRead
opLat=1
[system.cpu.fuPool.FUList5]
type=FUDesc
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
count=4
opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
[system.cpu.fuPool.FUList5.opList00]
type=OpDesc
issueLat=1
opClass=SimdAdd
opLat=1
[system.cpu.fuPool.FUList5.opList01]
type=OpDesc
issueLat=1
opClass=SimdAddAcc
opLat=1
[system.cpu.fuPool.FUList5.opList02]
type=OpDesc
issueLat=1
opClass=SimdAlu
opLat=1
[system.cpu.fuPool.FUList5.opList03]
type=OpDesc
issueLat=1
opClass=SimdCmp
opLat=1
[system.cpu.fuPool.FUList5.opList04]
type=OpDesc
issueLat=1
opClass=SimdCvt
opLat=1
[system.cpu.fuPool.FUList5.opList05]
type=OpDesc
issueLat=1
opClass=SimdMisc
opLat=1
[system.cpu.fuPool.FUList5.opList06]
type=OpDesc
issueLat=1
opClass=SimdMult
opLat=1
[system.cpu.fuPool.FUList5.opList07]
type=OpDesc
issueLat=1
opClass=SimdMultAcc
opLat=1
[system.cpu.fuPool.FUList5.opList08]
type=OpDesc
issueLat=1
opClass=SimdShift
opLat=1
[system.cpu.fuPool.FUList5.opList09]
type=OpDesc
issueLat=1
opClass=SimdShiftAcc
opLat=1
[system.cpu.fuPool.FUList5.opList10]
type=OpDesc
issueLat=1
opClass=SimdSqrt
opLat=1
[system.cpu.fuPool.FUList5.opList11]
type=OpDesc
issueLat=1
opClass=SimdFloatAdd
opLat=1
[system.cpu.fuPool.FUList5.opList12]
type=OpDesc
issueLat=1
opClass=SimdFloatAlu
opLat=1
[system.cpu.fuPool.FUList5.opList13]
type=OpDesc
issueLat=1
opClass=SimdFloatCmp
opLat=1
[system.cpu.fuPool.FUList5.opList14]
type=OpDesc
issueLat=1
opClass=SimdFloatCvt
opLat=1
[system.cpu.fuPool.FUList5.opList15]
type=OpDesc
issueLat=1
opClass=SimdFloatDiv
opLat=1
[system.cpu.fuPool.FUList5.opList16]
type=OpDesc
issueLat=1
opClass=SimdFloatMisc
opLat=1
[system.cpu.fuPool.FUList5.opList17]
type=OpDesc
issueLat=1
opClass=SimdFloatMult
opLat=1
[system.cpu.fuPool.FUList5.opList18]
type=OpDesc
issueLat=1
opClass=SimdFloatMultAcc
opLat=1
[system.cpu.fuPool.FUList5.opList19]
type=OpDesc
issueLat=1
opClass=SimdFloatSqrt
opLat=1
[system.cpu.fuPool.FUList6]
type=FUDesc
children=opList
count=0
opList=system.cpu.fuPool.FUList6.opList
[system.cpu.fuPool.FUList6.opList]
type=OpDesc
issueLat=1
opClass=MemWrite
opLat=1
[system.cpu.fuPool.FUList7]
type=FUDesc
children=opList0 opList1
count=4
opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
[system.cpu.fuPool.FUList7.opList0]
type=OpDesc
issueLat=1
opClass=MemRead
opLat=1
[system.cpu.fuPool.FUList7.opList1]
type=OpDesc
issueLat=1
opClass=MemWrite
opLat=1
[system.cpu.fuPool.FUList8]
type=FUDesc
children=opList
count=1
opList=system.cpu.fuPool.FUList8.opList
[system.cpu.fuPool.FUList8.opList]
type=OpDesc
issueLat=3
opClass=IprAccess
opLat=3
[system.cpu.icache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=131072
subblock_size=0
system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.interrupts]
type=ArmInterrupts
[system.cpu.itb]
type=ArmTLB
children=walker
size=64
walker=system.cpu.itb.walker
[system.cpu.itb.walker]
type=ArmTableWalker
max_backoff=100000
min_backoff=0
sys=system
port=system.cpu.toL2Bus.slave[2]
[system.cpu.l2cache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=false
latency=1000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=2097152
subblock_size=0
system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
[system.cpu.toL2Bus]
type=CoherentBus
block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.checker.itb.walker.port system.cpu.checker.dtb.walker.port
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=hello
cwd=
egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/regression/test-progs/hello/bin/arm/linux/hello
gid=100
input=cin
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=0
system=system
uid=100
[system.membus]
type=CoherentBus
block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
master=system.physmem.port[0]
slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=SimpleMemory
conf_table_reported=false
file=
in_addr_map=true
latency=30000
latency_var=0
null=false
range=0:134217727
zero=false
port=system.membus.master[0]

2
simulators/gem5/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simerr Executable file
View File

@ -0,0 +1,2 @@
warn: Sockets disabled, not accepting gdb connections
hack: be nice to actually delete the event here

11
simulators/gem5/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout Executable file
View File

@ -0,0 +1,11 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 4 2012 12:14:06
gem5 started Jun 4 2012 17:23:41
gem5 executing on zizzer
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Hello world!
Exiting @ tick 10303500 because target called exit()

729
simulators/gem5/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt Normal file
View File

@ -0,0 +1,729 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000010 # Number of seconds simulated
sim_ticks 10303500 # Number of ticks simulated
final_tick 10303500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 43907 # Simulator instruction rate (inst/s)
host_op_rate 54769 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 98312554 # Simulator tick rate (ticks/s)
host_mem_usage 230064 # Number of bytes of host memory used
host_seconds 0.10 # Real time elapsed on the host
sim_insts 4600 # Number of instructions simulated
sim_ops 5739 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 17664 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 8000 # Number of bytes read from this memory
system.physmem.bytes_read::total 25664 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 17664 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 17664 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 276 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 125 # Number of read requests responded to by this memory
system.physmem.num_reads::total 401 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 1714368904 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 776435192 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 2490804096 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 1714368904 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 1714368904 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 1714368904 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 776435192 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 2490804096 # Total bandwidth to/from this memory (bytes/s)
system.cpu.checker.dtb.inst_hits 0 # ITB inst hits
system.cpu.checker.dtb.inst_misses 0 # ITB inst misses
system.cpu.checker.dtb.read_hits 0 # DTB read hits
system.cpu.checker.dtb.read_misses 0 # DTB read misses
system.cpu.checker.dtb.write_hits 0 # DTB write hits
system.cpu.checker.dtb.write_misses 0 # DTB write misses
system.cpu.checker.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.checker.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.checker.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.checker.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.checker.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.checker.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.checker.dtb.read_accesses 0 # DTB read accesses
system.cpu.checker.dtb.write_accesses 0 # DTB write accesses
system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.checker.dtb.hits 0 # DTB hits
system.cpu.checker.dtb.misses 0 # DTB misses
system.cpu.checker.dtb.accesses 0 # DTB accesses
system.cpu.checker.itb.inst_hits 0 # ITB inst hits
system.cpu.checker.itb.inst_misses 0 # ITB inst misses
system.cpu.checker.itb.read_hits 0 # DTB read hits
system.cpu.checker.itb.read_misses 0 # DTB read misses
system.cpu.checker.itb.write_hits 0 # DTB write hits
system.cpu.checker.itb.write_misses 0 # DTB write misses
system.cpu.checker.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.checker.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.checker.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.checker.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.checker.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.checker.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.checker.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.checker.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.checker.itb.read_accesses 0 # DTB read accesses
system.cpu.checker.itb.write_accesses 0 # DTB write accesses
system.cpu.checker.itb.inst_accesses 0 # ITB inst accesses
system.cpu.checker.itb.hits 0 # DTB hits
system.cpu.checker.itb.misses 0 # DTB misses
system.cpu.checker.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 13 # Number of system calls
system.cpu.checker.numCycles 5752 # number of cpu cycles simulated
system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.numCycles 20608 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.BPredUnit.lookups 2552 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 1875 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 474 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 2008 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 693 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 237 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 53 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 6263 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 13044 # Number of instructions fetch has processed
system.cpu.fetch.Branches 2552 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 930 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 2846 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 1780 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 1715 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 2 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 37 # Number of stall cycles due to pending traps
system.cpu.fetch.CacheLines 2031 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 304 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 12075 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 1.376812 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.767860 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 9229 76.43% 76.43% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 246 2.04% 78.47% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 197 1.63% 80.10% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 227 1.88% 81.98% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 225 1.86% 83.84% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 278 2.30% 86.14% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 120 0.99% 87.14% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 130 1.08% 88.22% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 1423 11.78% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 12075 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.123835 # Number of branch fetches per cycle
system.cpu.fetch.rate 0.632958 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 6461 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 1883 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 2624 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 61 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 1046 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 445 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 174 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 14512 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 583 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 1046 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 6744 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 274 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 1422 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 2398 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 191 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 13646 # Number of instructions processed by rename
system.cpu.rename.IQFullEvents 14 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 155 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenamedOperands 13298 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 62745 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 61353 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 1392 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 5684 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 7614 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 44 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 42 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 614 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 2865 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 1803 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 22 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 17 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 11802 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 52 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 9165 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 112 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 5733 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 16704 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 15 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 12075 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 0.759006 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.446143 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 8430 69.81% 69.81% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 1334 11.05% 80.86% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 801 6.63% 87.49% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 552 4.57% 92.07% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 480 3.98% 96.04% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 289 2.39% 98.43% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 130 1.08% 99.51% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 44 0.36% 99.88% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 15 0.12% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 12075 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 2 0.93% 0.93% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 0.93% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 0.93% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.93% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.93% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.93% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 0.93% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.93% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.93% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.93% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.93% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.93% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.93% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.93% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.93% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 0.93% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.93% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 0.93% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.93% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.93% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.93% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.93% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.93% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.93% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.93% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.93% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.93% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.93% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.93% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 150 69.77% 70.70% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 63 29.30% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 5502 60.03% 60.03% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 7 0.08% 60.11% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.11% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.11% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.11% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.11% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.11% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.11% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.11% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.11% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.11% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.11% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.11% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.11% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.11% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.11% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.11% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.11% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.11% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.11% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.11% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.11% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.11% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.11% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.11% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.14% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.14% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.14% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.14% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 2395 26.13% 86.27% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 1258 13.73% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 9165 # Type of FU issued
system.cpu.iq.rate 0.444730 # Inst issue rate
system.cpu.iq.fu_busy_cnt 215 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.023459 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 30696 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 17588 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 8151 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 9360 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 60 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 1664 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 865 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 1046 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 169 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 21 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 11855 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 180 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 2865 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 1803 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 40 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 13 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 19 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 104 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 321 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 425 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 8667 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 2152 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 498 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 1 # number of nop insts executed
system.cpu.iew.exec_refs 3351 # number of memory reference insts executed
system.cpu.iew.exec_branches 1406 # Number of branches executed
system.cpu.iew.exec_stores 1199 # Number of stores executed
system.cpu.iew.exec_rate 0.420565 # Inst execution rate
system.cpu.iew.wb_sent 8349 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 8167 # cumulative count of insts written-back
system.cpu.iew.wb_producers 3874 # num instructions producing a value
system.cpu.iew.wb_consumers 7832 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 0.396302 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.494637 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitCommittedInsts 4600 # The number of committed instructions
system.cpu.commit.commitCommittedOps 5739 # The number of committed instructions
system.cpu.commit.commitSquashedInsts 6115 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 378 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 11030 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 0.520308 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.336045 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 8688 78.77% 78.77% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 1103 10.00% 88.77% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 433 3.93% 92.69% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 253 2.29% 94.99% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 182 1.65% 96.64% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 178 1.61% 98.25% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 56 0.51% 98.76% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 39 0.35% 99.11% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 98 0.89% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 11030 # Number of insts commited each cycle
system.cpu.commit.committedInsts 4600 # Number of instructions committed
system.cpu.commit.committedOps 5739 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 2139 # Number of memory references committed
system.cpu.commit.loads 1201 # Number of loads committed
system.cpu.commit.membars 12 # Number of memory barriers committed
system.cpu.commit.branches 945 # Number of branches committed
system.cpu.commit.fp_insts 16 # Number of committed floating point instructions.
system.cpu.commit.int_insts 4985 # Number of committed integer instructions.
system.cpu.commit.function_calls 82 # Number of function calls committed.
system.cpu.commit.bw_lim_events 98 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 22629 # The number of ROB reads
system.cpu.rob.rob_writes 24771 # The number of ROB writes
system.cpu.timesIdled 177 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 8533 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 4600 # Number of Instructions Simulated
system.cpu.committedOps 5739 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 4600 # Number of Instructions Simulated
system.cpu.cpi 4.480000 # CPI: Cycles Per Instruction
system.cpu.cpi_total 4.480000 # CPI: Total CPI of All Threads
system.cpu.ipc 0.223214 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.223214 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 39716 # number of integer regfile reads
system.cpu.int_regfile_writes 8038 # number of integer regfile writes
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
system.cpu.misc_regfile_reads 16043 # number of misc regfile reads
system.cpu.misc_regfile_writes 24 # number of misc regfile writes
system.cpu.icache.replacements 2 # number of replacements
system.cpu.icache.tagsinuse 151.737773 # Cycle average of tags in use
system.cpu.icache.total_refs 1665 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 296 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 5.625000 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 151.737773 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.074091 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.074091 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 1665 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 1665 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 1665 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 1665 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 1665 # number of overall hits
system.cpu.icache.overall_hits::total 1665 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 366 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 366 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 366 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 366 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 366 # number of overall misses
system.cpu.icache.overall_misses::total 366 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 12617500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 12617500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 12617500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 12617500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 12617500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 12617500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 2031 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 2031 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 2031 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 2031 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 2031 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 2031 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.180207 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.180207 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.180207 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.180207 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.180207 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.180207 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34474.043716 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 34474.043716 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 34474.043716 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 34474.043716 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 34474.043716 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 34474.043716 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 70 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 70 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 70 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 70 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 70 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 70 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 296 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 296 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 296 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 296 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 296 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 296 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9833500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 9833500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9833500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 9833500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9833500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 9833500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.145741 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.145741 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.145741 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.145741 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.145741 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.145741 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 33221.283784 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 33221.283784 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 33221.283784 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 33221.283784 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 33221.283784 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 33221.283784 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.tagsinuse 87.257006 # Cycle average of tags in use
system.cpu.dcache.total_refs 2425 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 149 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 16.275168 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 87.257006 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.021303 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.021303 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 1796 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 1796 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 609 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 609 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 9 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 9 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 2405 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 2405 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 2405 # number of overall hits
system.cpu.dcache.overall_hits::total 2405 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 170 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 170 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 304 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 304 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data 474 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 474 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 474 # number of overall misses
system.cpu.dcache.overall_misses::total 474 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 5541500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 5541500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 10844000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 10844000 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 76500 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 76500 # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 16385500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 16385500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 16385500 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 16385500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 1966 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 1966 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 2879 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 2879 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 2879 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 2879 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.086470 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.086470 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.332968 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.332968 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.181818 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.181818 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.164641 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.164641 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.164641 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.164641 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32597.058824 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 32597.058824 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35671.052632 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 35671.052632 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 38250 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 38250 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 34568.565401 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 34568.565401 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 34568.565401 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 34568.565401 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 63 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 63 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 262 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 262 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 325 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 325 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 325 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 325 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 107 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 107 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 42 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 42 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 149 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 149 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 149 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 149 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3192000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 3192000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1501500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 1501500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4693500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 4693500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4693500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 4693500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054425 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054425 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046002 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046002 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051754 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.051754 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051754 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.051754 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29831.775701 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29831.775701 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35750 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35750 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 31500 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 31500 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 31500 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 31500 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 188.789311 # Cycle average of tags in use
system.cpu.l2cache.total_refs 40 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 359 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.111421 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::cpu.inst 142.150350 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 46.638961 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::cpu.inst 0.004338 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.001423 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.005761 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 20 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 20 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 40 # number of ReadReq hits
system.cpu.l2cache.demand_hits::cpu.inst 20 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 20 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 40 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 20 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 20 # number of overall hits
system.cpu.l2cache.overall_hits::total 40 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 276 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 87 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 363 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 42 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 42 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 276 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 129 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 405 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 276 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 129 # number of overall misses
system.cpu.l2cache.overall_misses::total 405 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 9475500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2999000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 12474500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1446500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 1446500 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 9475500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 4445500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 13921000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 9475500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 4445500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 13921000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 296 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 107 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 403 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 42 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 42 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 296 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 149 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 445 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 296 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 149 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 445 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.932432 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.813084 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.900744 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.932432 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.865772 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.910112 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.932432 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.865772 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.910112 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34331.521739 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34471.264368 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 34365.013774 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34440.476190 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34440.476190 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34331.521739 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34461.240310 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 34372.839506 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34331.521739 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34461.240310 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 34372.839506 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 4 # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total 4 # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data 4 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total 4 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data 4 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total 4 # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 276 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 83 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 359 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 42 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 42 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 276 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 125 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 401 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 276 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 125 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 401 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 8590500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2612000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11202500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1315000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1315000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 8590500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3927000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 12517500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 8590500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3927000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 12517500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.932432 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.775701 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.890819 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.932432 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.838926 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.901124 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.932432 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.838926 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.901124 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31125 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31469.879518 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31204.735376 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31309.523810 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31309.523810 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31125 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31416 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31215.710723 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31125 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31416 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31215.710723 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

547
simulators/gem5/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini Normal file
View File

@ -0,0 +1,547 @@
[root]
type=Root
children=system
full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
boot_osflags=a
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
readfile=
symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.cpu]
type=DerivO3CPU
children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
LSQDepCheckShift=4
RASSize=16
SQEntries=32
SSITSize=1024
activity=0
backComSize=5
cachePorts=200
checker=Null
choiceCtrBits=2
choicePredictorSize=8192
clock=500
commitToDecodeDelay=1
commitToFetchDelay=1
commitToIEWDelay=1
commitToRenameDelay=1
commitWidth=8
cpu_id=0
decodeToFetchDelay=1
decodeToRenameDelay=1
decodeWidth=8
defer_registration=false
dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
fetchToDecodeDelay=1
fetchTrapLatency=1
fetchWidth=8
forwardComSize=5
fuPool=system.cpu.fuPool
function_trace=false
function_trace_start=0
globalCtrBits=2
globalHistoryBits=13
globalPredictorSize=8192
iewToCommitDelay=1
iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
instShiftAmt=2
interrupts=system.cpu.interrupts
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
localCtrBits=2
localHistoryBits=11
localHistoryTableSize=2048
localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
needsTSO=false
numIQEntries=64
numPhysFloatRegs=256
numPhysIntRegs=256
numROBEntries=192
numRobs=1
numThreads=1
phase=0
predType=tournament
profile=0
progress_interval=0
renameToDecodeDelay=1
renameToFetchDelay=1
renameToIEWDelay=2
renameToROBDelay=1
renameWidth=8
smtCommitPolicy=RoundRobin
smtFetchPolicy=SingleThread
smtIQPolicy=Partitioned
smtIQThreshold=100
smtLSQPolicy=Partitioned
smtLSQThreshold=100
smtNumFetchingThreads=1
smtROBPolicy=Partitioned
smtROBThreshold=100
squashWidth=8
store_set_clear_period=250000
system=system
tracer=system.cpu.tracer
trapLatency=13
wbDepth=1
wbWidth=8
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=262144
subblock_size=0
system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
[system.cpu.dtb]
type=ArmTLB
children=walker
size=64
walker=system.cpu.dtb.walker
[system.cpu.dtb.walker]
type=ArmTableWalker
max_backoff=100000
min_backoff=0
sys=system
port=system.cpu.toL2Bus.slave[3]
[system.cpu.fuPool]
type=FUPool
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
[system.cpu.fuPool.FUList0]
type=FUDesc
children=opList
count=6
opList=system.cpu.fuPool.FUList0.opList
[system.cpu.fuPool.FUList0.opList]
type=OpDesc
issueLat=1
opClass=IntAlu
opLat=1
[system.cpu.fuPool.FUList1]
type=FUDesc
children=opList0 opList1
count=2
opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
[system.cpu.fuPool.FUList1.opList0]
type=OpDesc
issueLat=1
opClass=IntMult
opLat=3
[system.cpu.fuPool.FUList1.opList1]
type=OpDesc
issueLat=19
opClass=IntDiv
opLat=20
[system.cpu.fuPool.FUList2]
type=FUDesc
children=opList0 opList1 opList2
count=4
opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
[system.cpu.fuPool.FUList2.opList0]
type=OpDesc
issueLat=1
opClass=FloatAdd
opLat=2
[system.cpu.fuPool.FUList2.opList1]
type=OpDesc
issueLat=1
opClass=FloatCmp
opLat=2
[system.cpu.fuPool.FUList2.opList2]
type=OpDesc
issueLat=1
opClass=FloatCvt
opLat=2
[system.cpu.fuPool.FUList3]
type=FUDesc
children=opList0 opList1 opList2
count=2
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
[system.cpu.fuPool.FUList3.opList0]
type=OpDesc
issueLat=1
opClass=FloatMult
opLat=4
[system.cpu.fuPool.FUList3.opList1]
type=OpDesc
issueLat=12
opClass=FloatDiv
opLat=12
[system.cpu.fuPool.FUList3.opList2]
type=OpDesc
issueLat=24
opClass=FloatSqrt
opLat=24
[system.cpu.fuPool.FUList4]
type=FUDesc
children=opList
count=0
opList=system.cpu.fuPool.FUList4.opList
[system.cpu.fuPool.FUList4.opList]
type=OpDesc
issueLat=1
opClass=MemRead
opLat=1
[system.cpu.fuPool.FUList5]
type=FUDesc
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
count=4
opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
[system.cpu.fuPool.FUList5.opList00]
type=OpDesc
issueLat=1
opClass=SimdAdd
opLat=1
[system.cpu.fuPool.FUList5.opList01]
type=OpDesc
issueLat=1
opClass=SimdAddAcc
opLat=1
[system.cpu.fuPool.FUList5.opList02]
type=OpDesc
issueLat=1
opClass=SimdAlu
opLat=1
[system.cpu.fuPool.FUList5.opList03]
type=OpDesc
issueLat=1
opClass=SimdCmp
opLat=1
[system.cpu.fuPool.FUList5.opList04]
type=OpDesc
issueLat=1
opClass=SimdCvt
opLat=1
[system.cpu.fuPool.FUList5.opList05]
type=OpDesc
issueLat=1
opClass=SimdMisc
opLat=1
[system.cpu.fuPool.FUList5.opList06]
type=OpDesc
issueLat=1
opClass=SimdMult
opLat=1
[system.cpu.fuPool.FUList5.opList07]
type=OpDesc
issueLat=1
opClass=SimdMultAcc
opLat=1
[system.cpu.fuPool.FUList5.opList08]
type=OpDesc
issueLat=1
opClass=SimdShift
opLat=1
[system.cpu.fuPool.FUList5.opList09]
type=OpDesc
issueLat=1
opClass=SimdShiftAcc
opLat=1
[system.cpu.fuPool.FUList5.opList10]
type=OpDesc
issueLat=1
opClass=SimdSqrt
opLat=1
[system.cpu.fuPool.FUList5.opList11]
type=OpDesc
issueLat=1
opClass=SimdFloatAdd
opLat=1
[system.cpu.fuPool.FUList5.opList12]
type=OpDesc
issueLat=1
opClass=SimdFloatAlu
opLat=1
[system.cpu.fuPool.FUList5.opList13]
type=OpDesc
issueLat=1
opClass=SimdFloatCmp
opLat=1
[system.cpu.fuPool.FUList5.opList14]
type=OpDesc
issueLat=1
opClass=SimdFloatCvt
opLat=1
[system.cpu.fuPool.FUList5.opList15]
type=OpDesc
issueLat=1
opClass=SimdFloatDiv
opLat=1
[system.cpu.fuPool.FUList5.opList16]
type=OpDesc
issueLat=1
opClass=SimdFloatMisc
opLat=1
[system.cpu.fuPool.FUList5.opList17]
type=OpDesc
issueLat=1
opClass=SimdFloatMult
opLat=1
[system.cpu.fuPool.FUList5.opList18]
type=OpDesc
issueLat=1
opClass=SimdFloatMultAcc
opLat=1
[system.cpu.fuPool.FUList5.opList19]
type=OpDesc
issueLat=1
opClass=SimdFloatSqrt
opLat=1
[system.cpu.fuPool.FUList6]
type=FUDesc
children=opList
count=0
opList=system.cpu.fuPool.FUList6.opList
[system.cpu.fuPool.FUList6.opList]
type=OpDesc
issueLat=1
opClass=MemWrite
opLat=1
[system.cpu.fuPool.FUList7]
type=FUDesc
children=opList0 opList1
count=4
opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
[system.cpu.fuPool.FUList7.opList0]
type=OpDesc
issueLat=1
opClass=MemRead
opLat=1
[system.cpu.fuPool.FUList7.opList1]
type=OpDesc
issueLat=1
opClass=MemWrite
opLat=1
[system.cpu.fuPool.FUList8]
type=FUDesc
children=opList
count=1
opList=system.cpu.fuPool.FUList8.opList
[system.cpu.fuPool.FUList8.opList]
type=OpDesc
issueLat=3
opClass=IprAccess
opLat=3
[system.cpu.icache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=131072
subblock_size=0
system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.interrupts]
type=ArmInterrupts
[system.cpu.itb]
type=ArmTLB
children=walker
size=64
walker=system.cpu.itb.walker
[system.cpu.itb.walker]
type=ArmTableWalker
max_backoff=100000
min_backoff=0
sys=system
port=system.cpu.toL2Bus.slave[2]
[system.cpu.l2cache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=false
latency=1000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=2097152
subblock_size=0
system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
[system.cpu.toL2Bus]
type=CoherentBus
block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=hello
cwd=
egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/regression/test-progs/hello/bin/arm/linux/hello
gid=100
input=cin
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=0
system=system
uid=100
[system.membus]
type=CoherentBus
block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
master=system.physmem.port[0]
slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=SimpleMemory
conf_table_reported=false
file=
in_addr_map=true
latency=30000
latency_var=0
null=false
range=0:134217727
zero=false
port=system.membus.master[0]

2
simulators/gem5/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simerr Executable file
View File

@ -0,0 +1,2 @@
warn: Sockets disabled, not accepting gdb connections
hack: be nice to actually delete the event here

11
simulators/gem5/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout Executable file
View File

@ -0,0 +1,11 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 4 2012 12:14:06
gem5 started Jun 4 2012 17:23:30
gem5 executing on zizzer
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Hello world!
Exiting @ tick 10303500 because target called exit()

684
simulators/gem5/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt Normal file
View File

@ -0,0 +1,684 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000010 # Number of seconds simulated
sim_ticks 10303500 # Number of ticks simulated
final_tick 10303500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 49511 # Simulator instruction rate (inst/s)
host_op_rate 61757 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 110854808 # Simulator tick rate (ticks/s)
host_mem_usage 229756 # Number of bytes of host memory used
host_seconds 0.09 # Real time elapsed on the host
sim_insts 4600 # Number of instructions simulated
sim_ops 5739 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 17664 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 8000 # Number of bytes read from this memory
system.physmem.bytes_read::total 25664 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 17664 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 17664 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 276 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 125 # Number of read requests responded to by this memory
system.physmem.num_reads::total 401 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 1714368904 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 776435192 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 2490804096 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 1714368904 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 1714368904 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 1714368904 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 776435192 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 2490804096 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 13 # Number of system calls
system.cpu.numCycles 20608 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.BPredUnit.lookups 2552 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 1875 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 474 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 2008 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 693 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 237 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 53 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 6263 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 13044 # Number of instructions fetch has processed
system.cpu.fetch.Branches 2552 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 930 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 2846 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 1780 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 1715 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 2 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 37 # Number of stall cycles due to pending traps
system.cpu.fetch.CacheLines 2031 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 304 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 12075 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 1.376812 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.767860 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 9229 76.43% 76.43% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 246 2.04% 78.47% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 197 1.63% 80.10% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 227 1.88% 81.98% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 225 1.86% 83.84% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 278 2.30% 86.14% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 120 0.99% 87.14% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 130 1.08% 88.22% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 1423 11.78% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 12075 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.123835 # Number of branch fetches per cycle
system.cpu.fetch.rate 0.632958 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 6461 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 1883 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 2624 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 61 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 1046 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 445 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 174 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 14512 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 583 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 1046 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 6744 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 274 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 1422 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 2398 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 191 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 13646 # Number of instructions processed by rename
system.cpu.rename.IQFullEvents 14 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 155 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenamedOperands 13298 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 62745 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 61353 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 1392 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 5684 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 7614 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 44 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 42 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 614 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 2865 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 1803 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 22 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 17 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 11802 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 52 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 9165 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 112 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 5733 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 16704 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 15 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 12075 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 0.759006 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.446143 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 8430 69.81% 69.81% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 1334 11.05% 80.86% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 801 6.63% 87.49% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 552 4.57% 92.07% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 480 3.98% 96.04% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 289 2.39% 98.43% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 130 1.08% 99.51% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 44 0.36% 99.88% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 15 0.12% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 12075 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 2 0.93% 0.93% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 0.93% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 0.93% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.93% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.93% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.93% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 0.93% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.93% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.93% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.93% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.93% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.93% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.93% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.93% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.93% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 0.93% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.93% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 0.93% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.93% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.93% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.93% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.93% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.93% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.93% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.93% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.93% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.93% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.93% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.93% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 150 69.77% 70.70% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 63 29.30% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 5502 60.03% 60.03% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 7 0.08% 60.11% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.11% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.11% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.11% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.11% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.11% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.11% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.11% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.11% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.11% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.11% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.11% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.11% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.11% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.11% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.11% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.11% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.11% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.11% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.11% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.11% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.11% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.11% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.11% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.14% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.14% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.14% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.14% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 2395 26.13% 86.27% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 1258 13.73% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 9165 # Type of FU issued
system.cpu.iq.rate 0.444730 # Inst issue rate
system.cpu.iq.fu_busy_cnt 215 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.023459 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 30696 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 17588 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 8151 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 9360 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 60 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 1664 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 865 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 1046 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 169 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 21 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 11855 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 180 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 2865 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 1803 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 40 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 13 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 19 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 104 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 321 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 425 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 8667 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 2152 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 498 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 1 # number of nop insts executed
system.cpu.iew.exec_refs 3351 # number of memory reference insts executed
system.cpu.iew.exec_branches 1406 # Number of branches executed
system.cpu.iew.exec_stores 1199 # Number of stores executed
system.cpu.iew.exec_rate 0.420565 # Inst execution rate
system.cpu.iew.wb_sent 8349 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 8167 # cumulative count of insts written-back
system.cpu.iew.wb_producers 3874 # num instructions producing a value
system.cpu.iew.wb_consumers 7832 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 0.396302 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.494637 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitCommittedInsts 4600 # The number of committed instructions
system.cpu.commit.commitCommittedOps 5739 # The number of committed instructions
system.cpu.commit.commitSquashedInsts 6115 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 378 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 11030 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 0.520308 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.336045 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 8688 78.77% 78.77% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 1103 10.00% 88.77% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 433 3.93% 92.69% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 253 2.29% 94.99% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 182 1.65% 96.64% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 178 1.61% 98.25% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 56 0.51% 98.76% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 39 0.35% 99.11% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 98 0.89% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 11030 # Number of insts commited each cycle
system.cpu.commit.committedInsts 4600 # Number of instructions committed
system.cpu.commit.committedOps 5739 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 2139 # Number of memory references committed
system.cpu.commit.loads 1201 # Number of loads committed
system.cpu.commit.membars 12 # Number of memory barriers committed
system.cpu.commit.branches 945 # Number of branches committed
system.cpu.commit.fp_insts 16 # Number of committed floating point instructions.
system.cpu.commit.int_insts 4985 # Number of committed integer instructions.
system.cpu.commit.function_calls 82 # Number of function calls committed.
system.cpu.commit.bw_lim_events 98 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 22629 # The number of ROB reads
system.cpu.rob.rob_writes 24771 # The number of ROB writes
system.cpu.timesIdled 177 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 8533 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 4600 # Number of Instructions Simulated
system.cpu.committedOps 5739 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 4600 # Number of Instructions Simulated
system.cpu.cpi 4.480000 # CPI: Cycles Per Instruction
system.cpu.cpi_total 4.480000 # CPI: Total CPI of All Threads
system.cpu.ipc 0.223214 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.223214 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 39716 # number of integer regfile reads
system.cpu.int_regfile_writes 8038 # number of integer regfile writes
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
system.cpu.misc_regfile_reads 16043 # number of misc regfile reads
system.cpu.misc_regfile_writes 24 # number of misc regfile writes
system.cpu.icache.replacements 2 # number of replacements
system.cpu.icache.tagsinuse 151.737773 # Cycle average of tags in use
system.cpu.icache.total_refs 1665 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 296 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 5.625000 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 151.737773 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.074091 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.074091 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 1665 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 1665 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 1665 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 1665 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 1665 # number of overall hits
system.cpu.icache.overall_hits::total 1665 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 366 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 366 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 366 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 366 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 366 # number of overall misses
system.cpu.icache.overall_misses::total 366 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 12617500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 12617500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 12617500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 12617500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 12617500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 12617500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 2031 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 2031 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 2031 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 2031 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 2031 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 2031 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.180207 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.180207 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.180207 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.180207 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.180207 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.180207 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34474.043716 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 34474.043716 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 34474.043716 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 34474.043716 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 34474.043716 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 34474.043716 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 70 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 70 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 70 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 70 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 70 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 70 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 296 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 296 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 296 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 296 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 296 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 296 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9833500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 9833500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9833500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 9833500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9833500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 9833500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.145741 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.145741 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.145741 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.145741 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.145741 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.145741 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 33221.283784 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 33221.283784 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 33221.283784 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 33221.283784 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 33221.283784 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 33221.283784 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.tagsinuse 87.257006 # Cycle average of tags in use
system.cpu.dcache.total_refs 2425 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 149 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 16.275168 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 87.257006 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.021303 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.021303 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 1796 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 1796 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 609 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 609 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 9 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 9 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 2405 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 2405 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 2405 # number of overall hits
system.cpu.dcache.overall_hits::total 2405 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 170 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 170 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 304 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 304 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data 474 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 474 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 474 # number of overall misses
system.cpu.dcache.overall_misses::total 474 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 5541500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 5541500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 10844000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 10844000 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 76500 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 76500 # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 16385500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 16385500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 16385500 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 16385500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 1966 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 1966 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 2879 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 2879 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 2879 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 2879 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.086470 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.086470 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.332968 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.332968 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.181818 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.181818 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.164641 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.164641 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.164641 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.164641 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32597.058824 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 32597.058824 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35671.052632 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 35671.052632 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 38250 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 38250 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 34568.565401 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 34568.565401 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 34568.565401 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 34568.565401 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 63 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 63 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 262 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 262 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 325 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 325 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 325 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 325 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 107 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 107 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 42 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 42 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 149 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 149 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 149 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 149 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3192000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 3192000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1501500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 1501500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4693500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 4693500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4693500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 4693500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054425 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054425 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046002 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046002 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051754 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.051754 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051754 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.051754 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29831.775701 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29831.775701 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35750 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35750 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 31500 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 31500 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 31500 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 31500 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 188.789311 # Cycle average of tags in use
system.cpu.l2cache.total_refs 40 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 359 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.111421 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::cpu.inst 142.150350 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 46.638961 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::cpu.inst 0.004338 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.001423 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.005761 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 20 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 20 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 40 # number of ReadReq hits
system.cpu.l2cache.demand_hits::cpu.inst 20 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 20 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 40 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 20 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 20 # number of overall hits
system.cpu.l2cache.overall_hits::total 40 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 276 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 87 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 363 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 42 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 42 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 276 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 129 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 405 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 276 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 129 # number of overall misses
system.cpu.l2cache.overall_misses::total 405 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 9475500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2999000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 12474500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1446500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 1446500 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 9475500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 4445500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 13921000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 9475500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 4445500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 13921000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 296 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 107 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 403 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 42 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 42 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 296 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 149 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 445 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 296 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 149 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 445 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.932432 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.813084 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.900744 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.932432 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.865772 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.910112 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.932432 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.865772 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.910112 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34331.521739 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34471.264368 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 34365.013774 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34440.476190 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34440.476190 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34331.521739 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34461.240310 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 34372.839506 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34331.521739 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34461.240310 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 34372.839506 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 4 # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total 4 # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data 4 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total 4 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data 4 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total 4 # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 276 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 83 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 359 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 42 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 42 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 276 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 125 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 401 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 276 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 125 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 401 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 8590500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2612000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11202500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1315000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1315000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 8590500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3927000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 12517500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 8590500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3927000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 12517500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.932432 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.775701 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.890819 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.932432 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.838926 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.901124 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.932432 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.838926 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.901124 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31125 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31469.879518 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31204.735376 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31309.523810 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31309.523810 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31125 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31416 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31215.710723 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31125 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31416 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31215.710723 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

189
simulators/gem5/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini Normal file
View File

@ -0,0 +1,189 @@
[root]
type=Root
children=system
full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
boot_osflags=a
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
readfile=
symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.cpu]
type=AtomicSimpleCPU
children=checker dtb interrupts itb tracer workload
checker=system.cpu.checker
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
fastmem=false
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
phase=0
profile=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
system=system
tracer=system.cpu.tracer
width=1
workload=system.cpu.workload
dcache_port=system.membus.slave[2]
icache_port=system.membus.slave[1]
[system.cpu.checker]
type=DummyChecker
children=dtb itb tracer
checker=Null
clock=1
cpu_id=-1
defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.checker.dtb
function_trace=false
function_trace_start=0
interrupts=Null
itb=system.cpu.checker.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
phase=0
profile=0
progress_interval=0
system=system
tracer=system.cpu.checker.tracer
workload=system.cpu.workload
[system.cpu.checker.dtb]
type=ArmTLB
children=walker
size=64
walker=system.cpu.checker.dtb.walker
[system.cpu.checker.dtb.walker]
type=ArmTableWalker
max_backoff=100000
min_backoff=0
sys=system
[system.cpu.checker.itb]
type=ArmTLB
children=walker
size=64
walker=system.cpu.checker.itb.walker
[system.cpu.checker.itb.walker]
type=ArmTableWalker
max_backoff=100000
min_backoff=0
sys=system
[system.cpu.checker.tracer]
type=ExeTracer
[system.cpu.dtb]
type=ArmTLB
children=walker
size=64
walker=system.cpu.dtb.walker
[system.cpu.dtb.walker]
type=ArmTableWalker
max_backoff=100000
min_backoff=0
sys=system
port=system.membus.slave[4]
[system.cpu.interrupts]
type=ArmInterrupts
[system.cpu.itb]
type=ArmTLB
children=walker
size=64
walker=system.cpu.itb.walker
[system.cpu.itb.walker]
type=ArmTableWalker
max_backoff=100000
min_backoff=0
sys=system
port=system.membus.slave[3]
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=hello
cwd=
egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/regression/test-progs/hello/bin/arm/linux/hello
gid=100
input=cin
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=0
system=system
uid=100
[system.membus]
type=CoherentBus
block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
master=system.physmem.port[0]
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port
[system.physmem]
type=SimpleMemory
conf_table_reported=false
file=
in_addr_map=true
latency=30000
latency_var=0
null=false
range=0:134217727
zero=false
port=system.membus.master[0]

2
simulators/gem5/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simerr Executable file
View File

@ -0,0 +1,2 @@
warn: Sockets disabled, not accepting gdb connections
hack: be nice to actually delete the event here

11
simulators/gem5/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simout Executable file
View File

@ -0,0 +1,11 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 4 2012 12:14:06
gem5 started Jun 4 2012 17:24:03
gem5 executing on zizzer
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic-dummychecker -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic-dummychecker
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Hello world!
Exiting @ tick 2875500 because target called exit()

147
simulators/gem5/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt Normal file
View File

@ -0,0 +1,147 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000003 # Number of seconds simulated
sim_ticks 2875500 # Number of ticks simulated
final_tick 2875500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 760705 # Simulator instruction rate (inst/s)
host_op_rate 946184 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 472746039 # Simulator tick rate (ticks/s)
host_mem_usage 219832 # Number of bytes of host memory used
host_seconds 0.01 # Real time elapsed on the host
sim_insts 4600 # Number of instructions simulated
sim_ops 5739 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 18452 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 4492 # Number of bytes read from this memory
system.physmem.bytes_read::total 22944 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 18452 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 18452 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 3648 # Number of bytes written to this memory
system.physmem.bytes_written::total 3648 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 4613 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 1158 # Number of read requests responded to by this memory
system.physmem.num_reads::total 5771 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 924 # Number of write requests responded to by this memory
system.physmem.num_writes::total 924 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 6416970962 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 1562163102 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 7979134064 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 6416970962 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 6416970962 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 1268648931 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 1268648931 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 6416970962 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2830812033 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 9247782994 # Total bandwidth to/from this memory (bytes/s)
system.cpu.checker.dtb.inst_hits 0 # ITB inst hits
system.cpu.checker.dtb.inst_misses 0 # ITB inst misses
system.cpu.checker.dtb.read_hits 0 # DTB read hits
system.cpu.checker.dtb.read_misses 0 # DTB read misses
system.cpu.checker.dtb.write_hits 0 # DTB write hits
system.cpu.checker.dtb.write_misses 0 # DTB write misses
system.cpu.checker.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.checker.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.checker.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.checker.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.checker.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.checker.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.checker.dtb.read_accesses 0 # DTB read accesses
system.cpu.checker.dtb.write_accesses 0 # DTB write accesses
system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.checker.dtb.hits 0 # DTB hits
system.cpu.checker.dtb.misses 0 # DTB misses
system.cpu.checker.dtb.accesses 0 # DTB accesses
system.cpu.checker.itb.inst_hits 0 # ITB inst hits
system.cpu.checker.itb.inst_misses 0 # ITB inst misses
system.cpu.checker.itb.read_hits 0 # DTB read hits
system.cpu.checker.itb.read_misses 0 # DTB read misses
system.cpu.checker.itb.write_hits 0 # DTB write hits
system.cpu.checker.itb.write_misses 0 # DTB write misses
system.cpu.checker.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.checker.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.checker.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.checker.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.checker.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.checker.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.checker.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.checker.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.checker.itb.read_accesses 0 # DTB read accesses
system.cpu.checker.itb.write_accesses 0 # DTB write accesses
system.cpu.checker.itb.inst_accesses 0 # ITB inst accesses
system.cpu.checker.itb.hits 0 # DTB hits
system.cpu.checker.itb.misses 0 # DTB misses
system.cpu.checker.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 13 # Number of system calls
system.cpu.checker.numCycles 0 # number of cpu cycles simulated
system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.numCycles 5752 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 4600 # Number of instructions committed
system.cpu.committedOps 5739 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 4985 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses
system.cpu.num_func_calls 185 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 775 # number of instructions that are conditional controls
system.cpu.num_int_insts 4985 # number of integer instructions
system.cpu.num_fp_insts 16 # number of float instructions
system.cpu.num_int_register_reads 25237 # number of times the integer registers were read
system.cpu.num_int_register_writes 5345 # number of times the integer registers were written
system.cpu.num_fp_register_reads 16 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_mem_refs 2139 # number of memory refs
system.cpu.num_load_insts 1201 # Number of load instructions
system.cpu.num_store_insts 938 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 5752 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
---------- End Simulation Statistics ----------

135
simulators/gem5/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/config.ini Normal file
View File

@ -0,0 +1,135 @@
[root]
type=Root
children=system
full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
boot_osflags=a
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
readfile=
symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.cpu]
type=AtomicSimpleCPU
children=dtb interrupts itb tracer workload
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
fastmem=false
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
phase=0
profile=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
system=system
tracer=system.cpu.tracer
width=1
workload=system.cpu.workload
dcache_port=system.membus.slave[2]
icache_port=system.membus.slave[1]
[system.cpu.dtb]
type=ArmTLB
children=walker
size=64
walker=system.cpu.dtb.walker
[system.cpu.dtb.walker]
type=ArmTableWalker
max_backoff=100000
min_backoff=0
sys=system
port=system.membus.slave[4]
[system.cpu.interrupts]
type=ArmInterrupts
[system.cpu.itb]
type=ArmTLB
children=walker
size=64
walker=system.cpu.itb.walker
[system.cpu.itb.walker]
type=ArmTableWalker
max_backoff=100000
min_backoff=0
sys=system
port=system.membus.slave[3]
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=hello
cwd=
egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/regression/test-progs/hello/bin/arm/linux/hello
gid=100
input=cin
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=0
system=system
uid=100
[system.membus]
type=CoherentBus
block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
master=system.physmem.port[0]
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port
[system.physmem]
type=SimpleMemory
conf_table_reported=false
file=
in_addr_map=true
latency=30000
latency_var=0
null=false
range=0:134217727
zero=false
port=system.membus.master[0]

2
simulators/gem5/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simerr Executable file
View File

@ -0,0 +1,2 @@
warn: Sockets disabled, not accepting gdb connections
hack: be nice to actually delete the event here

11
simulators/gem5/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simout Executable file
View File

@ -0,0 +1,11 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 4 2012 12:14:06
gem5 started Jun 4 2012 17:23:52
gem5 executing on zizzer
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Hello world!
Exiting @ tick 2875500 because target called exit()

102
simulators/gem5/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt Normal file
View File

@ -0,0 +1,102 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000003 # Number of seconds simulated
sim_ticks 2875500 # Number of ticks simulated
final_tick 2875500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 577592 # Simulator instruction rate (inst/s)
host_op_rate 718947 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 359450620 # Simulator tick rate (ticks/s)
host_mem_usage 219740 # Number of bytes of host memory used
host_seconds 0.01 # Real time elapsed on the host
sim_insts 4600 # Number of instructions simulated
sim_ops 5739 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 18452 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 4492 # Number of bytes read from this memory
system.physmem.bytes_read::total 22944 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 18452 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 18452 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 3648 # Number of bytes written to this memory
system.physmem.bytes_written::total 3648 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 4613 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 1158 # Number of read requests responded to by this memory
system.physmem.num_reads::total 5771 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 924 # Number of write requests responded to by this memory
system.physmem.num_writes::total 924 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 6416970962 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 1562163102 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 7979134064 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 6416970962 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 6416970962 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 1268648931 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 1268648931 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 6416970962 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2830812033 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 9247782994 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 13 # Number of system calls
system.cpu.numCycles 5752 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 4600 # Number of instructions committed
system.cpu.committedOps 5739 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 4985 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses
system.cpu.num_func_calls 185 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 775 # number of instructions that are conditional controls
system.cpu.num_int_insts 4985 # number of integer instructions
system.cpu.num_fp_insts 16 # number of float instructions
system.cpu.num_int_register_reads 25237 # number of times the integer registers were read
system.cpu.num_int_register_writes 5345 # number of times the integer registers were written
system.cpu.num_fp_register_reads 16 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_mem_refs 2139 # number of memory refs
system.cpu.num_load_insts 1201 # Number of load instructions
system.cpu.num_store_insts 938 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 5752 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
---------- End Simulation Statistics ----------

216
simulators/gem5/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini Normal file
View File

@ -0,0 +1,216 @@
[root]
type=Root
children=system
full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
boot_osflags=a
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
readfile=
symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.cpu]
type=TimingSimpleCPU
children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
phase=0
profile=0
progress_interval=0
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=262144
subblock_size=0
system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
[system.cpu.dtb]
type=ArmTLB
children=walker
size=64
walker=system.cpu.dtb.walker
[system.cpu.dtb.walker]
type=ArmTableWalker
max_backoff=100000
min_backoff=0
sys=system
port=system.cpu.toL2Bus.slave[3]
[system.cpu.icache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=131072
subblock_size=0
system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.interrupts]
type=ArmInterrupts
[system.cpu.itb]
type=ArmTLB
children=walker
size=64
walker=system.cpu.itb.walker
[system.cpu.itb.walker]
type=ArmTableWalker
max_backoff=100000
min_backoff=0
sys=system
port=system.cpu.toL2Bus.slave[2]
[system.cpu.l2cache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=false
latency=10000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=2097152
subblock_size=0
system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
[system.cpu.toL2Bus]
type=CoherentBus
block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=hello
cwd=
egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/regression/test-progs/hello/bin/arm/linux/hello
gid=100
input=cin
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=0
system=system
uid=100
[system.membus]
type=CoherentBus
block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
master=system.physmem.port[0]
slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=SimpleMemory
conf_table_reported=false
file=
in_addr_map=true
latency=30000
latency_var=0
null=false
range=0:134217727
zero=false
port=system.membus.master[0]

2
simulators/gem5/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simerr Executable file
View File

@ -0,0 +1,2 @@
warn: Sockets disabled, not accepting gdb connections
hack: be nice to actually delete the event here

11
simulators/gem5/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout Executable file
View File

@ -0,0 +1,11 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 4 2012 12:14:06
gem5 started Jun 4 2012 17:24:13
gem5 executing on zizzer
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Hello world!
Exiting @ tick 26361000 because target called exit()

408
simulators/gem5/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt Normal file
View File

@ -0,0 +1,408 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000026 # Number of seconds simulated
sim_ticks 26361000 # Number of ticks simulated
final_tick 26361000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 366471 # Simulator instruction rate (inst/s)
host_op_rate 454532 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 2105652624 # Simulator tick rate (ticks/s)
host_mem_usage 228652 # Number of bytes of host memory used
host_seconds 0.01 # Real time elapsed on the host
sim_insts 4574 # Number of instructions simulated
sim_ops 5682 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 14400 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 8000 # Number of bytes read from this memory
system.physmem.bytes_read::total 22400 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 14400 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 14400 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 225 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 125 # Number of read requests responded to by this memory
system.physmem.num_reads::total 350 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 546261523 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 303478624 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 849740146 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 546261523 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 546261523 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 546261523 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 303478624 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 849740146 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 13 # Number of system calls
system.cpu.numCycles 52722 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 4574 # Number of instructions committed
system.cpu.committedOps 5682 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 4985 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses
system.cpu.num_func_calls 185 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 775 # number of instructions that are conditional controls
system.cpu.num_int_insts 4985 # number of integer instructions
system.cpu.num_fp_insts 16 # number of float instructions
system.cpu.num_int_register_reads 28701 # number of times the integer registers were read
system.cpu.num_int_register_writes 5345 # number of times the integer registers were written
system.cpu.num_fp_register_reads 16 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_mem_refs 2139 # number of memory refs
system.cpu.num_load_insts 1201 # Number of load instructions
system.cpu.num_store_insts 938 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 52722 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.icache.replacements 1 # number of replacements
system.cpu.icache.tagsinuse 114.525744 # Cycle average of tags in use
system.cpu.icache.total_refs 4373 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 241 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 18.145228 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 114.525744 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.055921 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.055921 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 4373 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 4373 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 4373 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 4373 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 4373 # number of overall hits
system.cpu.icache.overall_hits::total 4373 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 241 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 241 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 241 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 241 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 241 # number of overall misses
system.cpu.icache.overall_misses::total 241 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 12824000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 12824000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 12824000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 12824000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 12824000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 12824000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 4614 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 4614 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 4614 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 4614 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 4614 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 4614 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.052232 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.052232 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.052232 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.052232 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.052232 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.052232 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53211.618257 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 53211.618257 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 53211.618257 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 53211.618257 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 53211.618257 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 53211.618257 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 241 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 241 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 241 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 241 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 241 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 241 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12101000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 12101000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12101000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 12101000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12101000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 12101000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.052232 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.052232 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.052232 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.052232 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.052232 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.052232 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50211.618257 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50211.618257 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50211.618257 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 50211.618257 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50211.618257 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 50211.618257 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.tagsinuse 82.937979 # Cycle average of tags in use
system.cpu.dcache.total_refs 1941 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 141 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 13.765957 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 82.937979 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.020249 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.020249 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 1049 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 1049 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 870 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 870 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 1919 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 1919 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 1919 # number of overall hits
system.cpu.dcache.overall_hits::total 1919 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 98 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 98 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 43 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 43 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 141 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 141 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 141 # number of overall misses
system.cpu.dcache.overall_misses::total 141 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 4816000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 4816000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 2408000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 2408000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 7224000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 7224000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 7224000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 7224000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 1147 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 1147 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 2060 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 2060 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 2060 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 2060 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.085440 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.085440 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.047097 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.047097 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.068447 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.068447 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.068447 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.068447 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 49142.857143 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 49142.857143 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56000 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 56000 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 51234.042553 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 51234.042553 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 51234.042553 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 51234.042553 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 98 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 98 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 43 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 141 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 141 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 141 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4522000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 4522000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2279000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 2279000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6801000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 6801000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6801000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 6801000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.085440 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.085440 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047097 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047097 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.068447 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.068447 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.068447 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.068447 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46142.857143 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46142.857143 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 48234.042553 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 48234.042553 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 48234.042553 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 48234.042553 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 153.954484 # Cycle average of tags in use
system.cpu.l2cache.total_refs 32 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 307 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.104235 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::cpu.inst 105.806385 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 48.148099 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::cpu.inst 0.003229 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.001469 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.004698 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 16 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 16 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 32 # number of ReadReq hits
system.cpu.l2cache.demand_hits::cpu.inst 16 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 16 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 32 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 16 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 16 # number of overall hits
system.cpu.l2cache.overall_hits::total 32 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 225 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 82 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 307 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 43 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 43 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 225 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 125 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 350 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 225 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 125 # number of overall misses
system.cpu.l2cache.overall_misses::total 350 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 11700000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4264000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 15964000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2236000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 2236000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 11700000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 6500000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 18200000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 11700000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 6500000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 18200000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 241 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 98 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 339 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 43 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 43 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 241 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 141 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 382 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 241 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 141 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 382 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.933610 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.836735 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.905605 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.933610 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.886525 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.916230 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.933610 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.886525 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.916230 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 225 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 82 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 307 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 43 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 43 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 225 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 125 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 350 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 225 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 125 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 350 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9000000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3280000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12280000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1720000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1720000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9000000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5000000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 14000000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9000000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5000000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 14000000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.933610 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.836735 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.905605 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.933610 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.886525 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.916230 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.933610 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.886525 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.916230 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

231
simulators/gem5/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/config.ini Normal file
View File

@ -0,0 +1,231 @@
[root]
type=Root
children=system
full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
boot_osflags=a
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
readfile=
symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.cpu]
type=InOrderCPU
children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
BTBEntries=4096
BTBTagSize=16
RASSize=16
activity=0
cachePorts=2
checker=Null
choiceCtrBits=2
choicePredictorSize=8192
clock=500
cpu_id=0
defer_registration=false
div16Latency=1
div16RepeatRate=1
div24Latency=1
div24RepeatRate=1
div32Latency=1
div32RepeatRate=1
div8Latency=1
div8RepeatRate=1
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
fetchBuffSize=4
functionTrace=false
functionTraceStart=0
function_trace=false
function_trace_start=0
globalCtrBits=2
globalHistoryBits=13
globalPredictorSize=8192
instShiftAmt=2
interrupts=system.cpu.interrupts
itb=system.cpu.itb
localCtrBits=2
localHistoryBits=11
localHistoryTableSize=2048
localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
memBlockSize=64
multLatency=1
multRepeatRate=1
numThreads=1
phase=0
predType=tournament
profile=0
progress_interval=0
stageTracing=false
stageWidth=4
system=system
threadModel=SMT
tracer=system.cpu.tracer
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=262144
subblock_size=0
system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
[system.cpu.dtb]
type=MipsTLB
size=64
[system.cpu.icache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=131072
subblock_size=0
system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.interrupts]
type=MipsInterrupts
[system.cpu.itb]
type=MipsTLB
size=64
[system.cpu.l2cache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=false
latency=10000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=2097152
subblock_size=0
system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
[system.cpu.toL2Bus]
type=CoherentBus
block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=hello
cwd=
egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/regression/test-progs/hello/bin/mips/linux/hello
gid=100
input=cin
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=0
system=system
uid=100
[system.membus]
type=CoherentBus
block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
master=system.physmem.port[0]
slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=SimpleMemory
conf_table_reported=false
file=
in_addr_map=true
latency=30000
latency_var=0
null=false
range=0:134217727
zero=false
port=system.membus.master[0]

Some files were not shown because too many files have changed in this diff Show More