Adding gem5 source to svn.
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1819 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
This commit is contained in:
friemel
@ -0,0 +1,913 @@
|
||||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
full_system=true
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
||||
[system]
|
||||
type=LinuxAlphaSystem
|
||||
children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami
|
||||
boot_cpu_frequency=500
|
||||
boot_osflags=root=/dev/hda1 console=ttyS0
|
||||
console=/dist/m5/system/binaries/console
|
||||
init_param=0
|
||||
kernel=/dist/m5/system/binaries/vmlinux
|
||||
load_addr_mask=1099511627775
|
||||
mem_mode=atomic
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
pal=/dist/m5/system/binaries/ts_osfpal
|
||||
readfile=tests/halt.sh
|
||||
symbolfile=
|
||||
system_rev=1024
|
||||
system_type=34
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.membus.slave[0]
|
||||
|
||||
[system.bridge]
|
||||
type=Bridge
|
||||
delay=50000
|
||||
nack_delay=4000
|
||||
ranges=8796093022208:18446744073709551615
|
||||
req_size=16
|
||||
resp_size=16
|
||||
write_ack=false
|
||||
master=system.iobus.slave[0]
|
||||
slave=system.membus.master[0]
|
||||
|
||||
[system.cpu0]
|
||||
type=AtomicSimpleCPU
|
||||
children=dcache dtb icache interrupts itb tracer
|
||||
checker=Null
|
||||
clock=500
|
||||
cpu_id=0
|
||||
defer_registration=false
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu0.dtb
|
||||
fastmem=false
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
interrupts=system.cpu0.interrupts
|
||||
itb=system.cpu0.itb
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
phase=0
|
||||
profile=0
|
||||
progress_interval=0
|
||||
simulate_data_stalls=false
|
||||
simulate_inst_stalls=false
|
||||
system=system
|
||||
tracer=system.cpu0.tracer
|
||||
width=1
|
||||
workload=
|
||||
dcache_port=system.cpu0.dcache.cpu_side
|
||||
icache_port=system.cpu0.icache.cpu_side
|
||||
|
||||
[system.cpu0.dcache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=4
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=32768
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=8
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu0.dcache_port
|
||||
mem_side=system.toL2Bus.slave[1]
|
||||
|
||||
[system.cpu0.dtb]
|
||||
type=AlphaTLB
|
||||
size=64
|
||||
|
||||
[system.cpu0.icache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=1
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=32768
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=8
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu0.icache_port
|
||||
mem_side=system.toL2Bus.slave[0]
|
||||
|
||||
[system.cpu0.interrupts]
|
||||
type=AlphaInterrupts
|
||||
|
||||
[system.cpu0.itb]
|
||||
type=AlphaTLB
|
||||
size=48
|
||||
|
||||
[system.cpu0.tracer]
|
||||
type=ExeTracer
|
||||
|
||||
[system.cpu1]
|
||||
type=AtomicSimpleCPU
|
||||
children=dcache dtb icache interrupts itb tracer
|
||||
checker=Null
|
||||
clock=500
|
||||
cpu_id=1
|
||||
defer_registration=false
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu1.dtb
|
||||
fastmem=false
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
interrupts=system.cpu1.interrupts
|
||||
itb=system.cpu1.itb
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
phase=0
|
||||
profile=0
|
||||
progress_interval=0
|
||||
simulate_data_stalls=false
|
||||
simulate_inst_stalls=false
|
||||
system=system
|
||||
tracer=system.cpu1.tracer
|
||||
width=1
|
||||
workload=
|
||||
dcache_port=system.cpu1.dcache.cpu_side
|
||||
icache_port=system.cpu1.icache.cpu_side
|
||||
|
||||
[system.cpu1.dcache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=4
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=32768
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=8
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu1.dcache_port
|
||||
mem_side=system.toL2Bus.slave[3]
|
||||
|
||||
[system.cpu1.dtb]
|
||||
type=AlphaTLB
|
||||
size=64
|
||||
|
||||
[system.cpu1.icache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=1
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=32768
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=8
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu1.icache_port
|
||||
mem_side=system.toL2Bus.slave[2]
|
||||
|
||||
[system.cpu1.interrupts]
|
||||
type=AlphaInterrupts
|
||||
|
||||
[system.cpu1.itb]
|
||||
type=AlphaTLB
|
||||
size=48
|
||||
|
||||
[system.cpu1.tracer]
|
||||
type=ExeTracer
|
||||
|
||||
[system.disk0]
|
||||
type=IdeDisk
|
||||
children=image
|
||||
delay=1000000
|
||||
driveID=master
|
||||
image=system.disk0.image
|
||||
|
||||
[system.disk0.image]
|
||||
type=CowDiskImage
|
||||
children=child
|
||||
child=system.disk0.image.child
|
||||
image_file=
|
||||
read_only=false
|
||||
table_size=65536
|
||||
|
||||
[system.disk0.image.child]
|
||||
type=RawDiskImage
|
||||
image_file=/dist/m5/system/disks/linux-latest.img
|
||||
read_only=true
|
||||
|
||||
[system.disk2]
|
||||
type=IdeDisk
|
||||
children=image
|
||||
delay=1000000
|
||||
driveID=master
|
||||
image=system.disk2.image
|
||||
|
||||
[system.disk2.image]
|
||||
type=CowDiskImage
|
||||
children=child
|
||||
child=system.disk2.image.child
|
||||
image_file=
|
||||
read_only=false
|
||||
table_size=65536
|
||||
|
||||
[system.disk2.image.child]
|
||||
type=RawDiskImage
|
||||
image_file=/dist/m5/system/disks/linux-bigswap2.img
|
||||
read_only=true
|
||||
|
||||
[system.intrctrl]
|
||||
type=IntrControl
|
||||
sys=system
|
||||
|
||||
[system.iobus]
|
||||
type=NoncoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
use_default_range=true
|
||||
width=64
|
||||
default=system.tsunami.pciconfig.pio
|
||||
master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ethernet.pio system.tsunami.ethernet.config system.iocache.cpu_side
|
||||
slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma
|
||||
|
||||
[system.iocache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:8589934591
|
||||
assoc=8
|
||||
block_size=64
|
||||
forward_snoops=false
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=50000
|
||||
max_miss_count=0
|
||||
mshrs=20
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=1024
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=12
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.iobus.master[29]
|
||||
mem_side=system.membus.slave[1]
|
||||
|
||||
[system.l2c]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=8
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=false
|
||||
latency=10000
|
||||
max_miss_count=0
|
||||
mshrs=92
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=4194304
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=16
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.toL2Bus.master[0]
|
||||
mem_side=system.membus.slave[2]
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
children=badaddr_responder
|
||||
block_size=64
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
default=system.membus.badaddr_responder.pio
|
||||
master=system.bridge.slave system.physmem.port[0]
|
||||
slave=system.system_port system.iocache.mem_side system.l2c.mem_side
|
||||
|
||||
[system.membus.badaddr_responder]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=0
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=true
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.membus.default
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.membus.master[1]
|
||||
|
||||
[system.simple_disk]
|
||||
type=SimpleDisk
|
||||
children=disk
|
||||
disk=system.simple_disk.disk
|
||||
system=system
|
||||
|
||||
[system.simple_disk.disk]
|
||||
type=RawDiskImage
|
||||
image_file=/dist/m5/system/disks/linux-latest.img
|
||||
read_only=true
|
||||
|
||||
[system.terminal]
|
||||
type=Terminal
|
||||
intr_control=system.intrctrl
|
||||
number=0
|
||||
output=true
|
||||
port=3456
|
||||
|
||||
[system.toL2Bus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
master=system.l2c.cpu_side
|
||||
slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side
|
||||
|
||||
[system.tsunami]
|
||||
type=Tsunami
|
||||
children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart
|
||||
intrctrl=system.intrctrl
|
||||
system=system
|
||||
|
||||
[system.tsunami.backdoor]
|
||||
type=AlphaBackdoor
|
||||
cpu=system.cpu0
|
||||
disk=system.simple_disk
|
||||
pio_addr=8804682956800
|
||||
pio_latency=1000
|
||||
platform=system.tsunami
|
||||
system=system
|
||||
terminal=system.terminal
|
||||
pio=system.iobus.master[24]
|
||||
|
||||
[system.tsunami.cchip]
|
||||
type=TsunamiCChip
|
||||
pio_addr=8803072344064
|
||||
pio_latency=1000
|
||||
system=system
|
||||
tsunami=system.tsunami
|
||||
pio=system.iobus.master[0]
|
||||
|
||||
[system.tsunami.ethernet]
|
||||
type=NSGigE
|
||||
BAR0=1
|
||||
BAR0LegacyIO=false
|
||||
BAR0Size=256
|
||||
BAR1=0
|
||||
BAR1LegacyIO=false
|
||||
BAR1Size=4096
|
||||
BAR2=0
|
||||
BAR2LegacyIO=false
|
||||
BAR2Size=0
|
||||
BAR3=0
|
||||
BAR3LegacyIO=false
|
||||
BAR3Size=0
|
||||
BAR4=0
|
||||
BAR4LegacyIO=false
|
||||
BAR4Size=0
|
||||
BAR5=0
|
||||
BAR5LegacyIO=false
|
||||
BAR5Size=0
|
||||
BIST=0
|
||||
CacheLineSize=0
|
||||
CardbusCIS=0
|
||||
ClassCode=2
|
||||
Command=0
|
||||
DeviceID=34
|
||||
ExpansionROM=0
|
||||
HeaderType=0
|
||||
InterruptLine=30
|
||||
InterruptPin=1
|
||||
LatencyTimer=0
|
||||
MaximumLatency=52
|
||||
MinimumGrant=176
|
||||
ProgIF=0
|
||||
Revision=0
|
||||
Status=656
|
||||
SubClassCode=0
|
||||
SubsystemID=0
|
||||
SubsystemVendorID=0
|
||||
VendorID=4107
|
||||
clock=0
|
||||
config_latency=20000
|
||||
dma_data_free=false
|
||||
dma_desc_free=false
|
||||
dma_no_allocate=true
|
||||
dma_read_delay=0
|
||||
dma_read_factor=0
|
||||
dma_write_delay=0
|
||||
dma_write_factor=0
|
||||
hardware_address=00:90:00:00:00:01
|
||||
intr_delay=10000000
|
||||
max_backoff_delay=10000000
|
||||
min_backoff_delay=4000
|
||||
pci_bus=0
|
||||
pci_dev=1
|
||||
pci_func=0
|
||||
pio_latency=1000
|
||||
platform=system.tsunami
|
||||
rss=false
|
||||
rx_delay=1000000
|
||||
rx_fifo_size=524288
|
||||
rx_filter=true
|
||||
rx_thread=false
|
||||
system=system
|
||||
tx_delay=1000000
|
||||
tx_fifo_size=524288
|
||||
tx_thread=false
|
||||
config=system.iobus.master[28]
|
||||
dma=system.iobus.slave[2]
|
||||
pio=system.iobus.master[27]
|
||||
|
||||
[system.tsunami.fake_OROM]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8796093677568
|
||||
pio_latency=1000
|
||||
pio_size=393216
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[8]
|
||||
|
||||
[system.tsunami.fake_ata0]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615848432
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[19]
|
||||
|
||||
[system.tsunami.fake_ata1]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615848304
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[20]
|
||||
|
||||
[system.tsunami.fake_pnp_addr]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615848569
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[9]
|
||||
|
||||
[system.tsunami.fake_pnp_read0]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615848451
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[11]
|
||||
|
||||
[system.tsunami.fake_pnp_read1]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615848515
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[12]
|
||||
|
||||
[system.tsunami.fake_pnp_read2]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615848579
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[13]
|
||||
|
||||
[system.tsunami.fake_pnp_read3]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615848643
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[14]
|
||||
|
||||
[system.tsunami.fake_pnp_read4]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615848707
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[15]
|
||||
|
||||
[system.tsunami.fake_pnp_read5]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615848771
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[16]
|
||||
|
||||
[system.tsunami.fake_pnp_read6]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615848835
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[17]
|
||||
|
||||
[system.tsunami.fake_pnp_read7]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615848899
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[18]
|
||||
|
||||
[system.tsunami.fake_pnp_write]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615850617
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[10]
|
||||
|
||||
[system.tsunami.fake_ppc]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615848891
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[7]
|
||||
|
||||
[system.tsunami.fake_sm_chip]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615848816
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[2]
|
||||
|
||||
[system.tsunami.fake_uart1]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615848696
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[3]
|
||||
|
||||
[system.tsunami.fake_uart2]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615848936
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[4]
|
||||
|
||||
[system.tsunami.fake_uart3]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615848680
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[5]
|
||||
|
||||
[system.tsunami.fake_uart4]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615848944
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[6]
|
||||
|
||||
[system.tsunami.fb]
|
||||
type=BadDevice
|
||||
devicename=FrameBuffer
|
||||
pio_addr=8804615848912
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.iobus.master[21]
|
||||
|
||||
[system.tsunami.ide]
|
||||
type=IdeController
|
||||
BAR0=1
|
||||
BAR0LegacyIO=false
|
||||
BAR0Size=8
|
||||
BAR1=1
|
||||
BAR1LegacyIO=false
|
||||
BAR1Size=4
|
||||
BAR2=1
|
||||
BAR2LegacyIO=false
|
||||
BAR2Size=8
|
||||
BAR3=1
|
||||
BAR3LegacyIO=false
|
||||
BAR3Size=4
|
||||
BAR4=1
|
||||
BAR4LegacyIO=false
|
||||
BAR4Size=16
|
||||
BAR5=1
|
||||
BAR5LegacyIO=false
|
||||
BAR5Size=0
|
||||
BIST=0
|
||||
CacheLineSize=0
|
||||
CardbusCIS=0
|
||||
ClassCode=1
|
||||
Command=0
|
||||
DeviceID=28945
|
||||
ExpansionROM=0
|
||||
HeaderType=0
|
||||
InterruptLine=31
|
||||
InterruptPin=1
|
||||
LatencyTimer=0
|
||||
MaximumLatency=0
|
||||
MinimumGrant=0
|
||||
ProgIF=133
|
||||
Revision=0
|
||||
Status=640
|
||||
SubClassCode=1
|
||||
SubsystemID=0
|
||||
SubsystemVendorID=0
|
||||
VendorID=32902
|
||||
config_latency=20000
|
||||
ctrl_offset=0
|
||||
disks=system.disk0 system.disk2
|
||||
io_shift=0
|
||||
max_backoff_delay=10000000
|
||||
min_backoff_delay=4000
|
||||
pci_bus=0
|
||||
pci_dev=0
|
||||
pci_func=0
|
||||
pio_latency=1000
|
||||
platform=system.tsunami
|
||||
system=system
|
||||
config=system.iobus.master[26]
|
||||
dma=system.iobus.slave[1]
|
||||
pio=system.iobus.master[25]
|
||||
|
||||
[system.tsunami.io]
|
||||
type=TsunamiIO
|
||||
frequency=976562500
|
||||
pio_addr=8804615847936
|
||||
pio_latency=1000
|
||||
system=system
|
||||
time=Thu Jan 1 00:00:00 2009
|
||||
tsunami=system.tsunami
|
||||
year_is_bcd=false
|
||||
pio=system.iobus.master[22]
|
||||
|
||||
[system.tsunami.pchip]
|
||||
type=TsunamiPChip
|
||||
pio_addr=8802535473152
|
||||
pio_latency=1000
|
||||
system=system
|
||||
tsunami=system.tsunami
|
||||
pio=system.iobus.master[1]
|
||||
|
||||
[system.tsunami.pciconfig]
|
||||
type=PciConfigAll
|
||||
bus=0
|
||||
pio_latency=1
|
||||
platform=system.tsunami
|
||||
size=16777216
|
||||
system=system
|
||||
pio=system.iobus.default
|
||||
|
||||
[system.tsunami.uart]
|
||||
type=Uart8250
|
||||
pio_addr=8804615848952
|
||||
pio_latency=1000
|
||||
platform=system.tsunami
|
||||
system=system
|
||||
terminal=system.terminal
|
||||
pio=system.iobus.master[23]
|
||||
|
||||
@ -0,0 +1,5 @@
|
||||
warn: Sockets disabled, not accepting terminal connections
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: Prefetch instructions in Alpha do not do anything
|
||||
warn: Prefetch instructions in Alpha do not do anything
|
||||
hack: be nice to actually delete the event here
|
||||
@ -0,0 +1,13 @@
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jun 4 2012 11:50:11
|
||||
gem5 started Jun 4 2012 14:39:49
|
||||
gem5 executing on zizzer
|
||||
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual -re tests/run.py build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: kernel located at: /dist/m5/system/binaries/vmlinux
|
||||
0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Launching CPU 1 @ 97861500
|
||||
Exiting @ tick 1870335522500 because m5_exit instruction encountered
|
||||
@ -0,0 +1,762 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 1.870336 # Number of seconds simulated
|
||||
sim_ticks 1870335522500 # Number of ticks simulated
|
||||
final_tick 1870335522500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 2870976 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2870973 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 85025108641 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 298608 # Number of bytes of host memory used
|
||||
host_seconds 22.00 # Real time elapsed on the host
|
||||
sim_insts 63154034 # Number of instructions simulated
|
||||
sim_ops 63154034 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu0.inst 855168 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu0.data 67882688 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::tsunami.ide 2649600 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu1.inst 139840 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu1.data 770176 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 72297472 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu0.inst 855168 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu1.inst 139840 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 995008 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 10452352 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 10452352 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu0.inst 13362 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu0.data 1060667 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::tsunami.ide 41400 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu1.inst 2185 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu1.data 12034 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 1129648 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 163318 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 163318 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu0.inst 457227 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu0.data 36294391 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::tsunami.ide 1416644 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu1.inst 74767 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu1.data 411785 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 38654814 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu0.inst 457227 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu1.inst 74767 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 531994 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 5588490 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 5588490 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 5588490 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu0.inst 457227 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu0.data 36294391 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::tsunami.ide 1416644 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu1.inst 74767 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu1.data 411785 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 44243304 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.l2c.replacements 1051788 # number of replacements
|
||||
system.l2c.tagsinuse 34117.721410 # Cycle average of tags in use
|
||||
system.l2c.total_refs 2341203 # Total number of references to valid blocks.
|
||||
system.l2c.sampled_refs 1087985 # Sample count of references to valid blocks.
|
||||
system.l2c.avg_refs 2.151871 # Average number of references to valid blocks.
|
||||
system.l2c.warmup_cycle 990121000 # Cycle when the warmup percentage was hit.
|
||||
system.l2c.occ_blocks::writebacks 23831.931773 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu0.inst 3683.485712 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu0.data 6336.188239 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu1.inst 152.381317 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu1.data 113.734368 # Average occupied blocks per requestor
|
||||
system.l2c.occ_percent::writebacks 0.363646 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu0.inst 0.056206 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu0.data 0.096683 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu1.inst 0.002325 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu1.data 0.001735 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::total 0.520595 # Average percentage of cache occupancy
|
||||
system.l2c.ReadReq_hits::cpu0.inst 871618 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu0.data 748887 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu1.inst 101445 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu1.data 35685 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::total 1757635 # number of ReadReq hits
|
||||
system.l2c.Writeback_hits::writebacks 811846 # number of Writeback hits
|
||||
system.l2c.Writeback_hits::total 811846 # number of Writeback hits
|
||||
system.l2c.UpgradeReq_hits::cpu0.data 134 # number of UpgradeReq hits
|
||||
system.l2c.UpgradeReq_hits::cpu1.data 39 # number of UpgradeReq hits
|
||||
system.l2c.UpgradeReq_hits::total 173 # number of UpgradeReq hits
|
||||
system.l2c.SCUpgradeReq_hits::cpu0.data 15 # number of SCUpgradeReq hits
|
||||
system.l2c.SCUpgradeReq_hits::cpu1.data 9 # number of SCUpgradeReq hits
|
||||
system.l2c.SCUpgradeReq_hits::total 24 # number of SCUpgradeReq hits
|
||||
system.l2c.ReadExReq_hits::cpu0.data 164417 # number of ReadExReq hits
|
||||
system.l2c.ReadExReq_hits::cpu1.data 14126 # number of ReadExReq hits
|
||||
system.l2c.ReadExReq_hits::total 178543 # number of ReadExReq hits
|
||||
system.l2c.demand_hits::cpu0.inst 871618 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu0.data 913304 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu1.inst 101445 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu1.data 49811 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::total 1936178 # number of demand (read+write) hits
|
||||
system.l2c.overall_hits::cpu0.inst 871618 # number of overall hits
|
||||
system.l2c.overall_hits::cpu0.data 913304 # number of overall hits
|
||||
system.l2c.overall_hits::cpu1.inst 101445 # number of overall hits
|
||||
system.l2c.overall_hits::cpu1.data 49811 # number of overall hits
|
||||
system.l2c.overall_hits::total 1936178 # number of overall hits
|
||||
system.l2c.ReadReq_misses::cpu0.inst 13362 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu0.data 943555 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu1.inst 2185 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu1.data 2326 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::total 961428 # number of ReadReq misses
|
||||
system.l2c.UpgradeReq_misses::cpu0.data 2441 # number of UpgradeReq misses
|
||||
system.l2c.UpgradeReq_misses::cpu1.data 567 # number of UpgradeReq misses
|
||||
system.l2c.UpgradeReq_misses::total 3008 # number of UpgradeReq misses
|
||||
system.l2c.SCUpgradeReq_misses::cpu0.data 65 # number of SCUpgradeReq misses
|
||||
system.l2c.SCUpgradeReq_misses::cpu1.data 101 # number of SCUpgradeReq misses
|
||||
system.l2c.SCUpgradeReq_misses::total 166 # number of SCUpgradeReq misses
|
||||
system.l2c.ReadExReq_misses::cpu0.data 117481 # number of ReadExReq misses
|
||||
system.l2c.ReadExReq_misses::cpu1.data 9826 # number of ReadExReq misses
|
||||
system.l2c.ReadExReq_misses::total 127307 # number of ReadExReq misses
|
||||
system.l2c.demand_misses::cpu0.inst 13362 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu0.data 1061036 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu1.inst 2185 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu1.data 12152 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::total 1088735 # number of demand (read+write) misses
|
||||
system.l2c.overall_misses::cpu0.inst 13362 # number of overall misses
|
||||
system.l2c.overall_misses::cpu0.data 1061036 # number of overall misses
|
||||
system.l2c.overall_misses::cpu1.inst 2185 # number of overall misses
|
||||
system.l2c.overall_misses::cpu1.data 12152 # number of overall misses
|
||||
system.l2c.overall_misses::total 1088735 # number of overall misses
|
||||
system.l2c.ReadReq_accesses::cpu0.inst 884980 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::cpu0.data 1692442 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::cpu1.inst 103630 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::cpu1.data 38011 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::total 2719063 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.Writeback_accesses::writebacks 811846 # number of Writeback accesses(hits+misses)
|
||||
system.l2c.Writeback_accesses::total 811846 # number of Writeback accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_accesses::cpu0.data 2575 # number of UpgradeReq accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_accesses::cpu1.data 606 # number of UpgradeReq accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_accesses::total 3181 # number of UpgradeReq accesses(hits+misses)
|
||||
system.l2c.SCUpgradeReq_accesses::cpu0.data 80 # number of SCUpgradeReq accesses(hits+misses)
|
||||
system.l2c.SCUpgradeReq_accesses::cpu1.data 110 # number of SCUpgradeReq accesses(hits+misses)
|
||||
system.l2c.SCUpgradeReq_accesses::total 190 # number of SCUpgradeReq accesses(hits+misses)
|
||||
system.l2c.ReadExReq_accesses::cpu0.data 281898 # number of ReadExReq accesses(hits+misses)
|
||||
system.l2c.ReadExReq_accesses::cpu1.data 23952 # number of ReadExReq accesses(hits+misses)
|
||||
system.l2c.ReadExReq_accesses::total 305850 # number of ReadExReq accesses(hits+misses)
|
||||
system.l2c.demand_accesses::cpu0.inst 884980 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu0.data 1974340 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu1.inst 103630 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu1.data 61963 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::total 3024913 # number of demand (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu0.inst 884980 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu0.data 1974340 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu1.inst 103630 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu1.data 61963 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::total 3024913 # number of overall (read+write) accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu0.inst 0.015099 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu0.data 0.557511 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu1.inst 0.021085 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu1.data 0.061193 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::total 0.353588 # miss rate for ReadReq accesses
|
||||
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.947961 # miss rate for UpgradeReq accesses
|
||||
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.935644 # miss rate for UpgradeReq accesses
|
||||
system.l2c.UpgradeReq_miss_rate::total 0.945615 # miss rate for UpgradeReq accesses
|
||||
system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.812500 # miss rate for SCUpgradeReq accesses
|
||||
system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.918182 # miss rate for SCUpgradeReq accesses
|
||||
system.l2c.SCUpgradeReq_miss_rate::total 0.873684 # miss rate for SCUpgradeReq accesses
|
||||
system.l2c.ReadExReq_miss_rate::cpu0.data 0.416750 # miss rate for ReadExReq accesses
|
||||
system.l2c.ReadExReq_miss_rate::cpu1.data 0.410237 # miss rate for ReadExReq accesses
|
||||
system.l2c.ReadExReq_miss_rate::total 0.416240 # miss rate for ReadExReq accesses
|
||||
system.l2c.demand_miss_rate::cpu0.inst 0.015099 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu0.data 0.537413 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu1.inst 0.021085 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu1.data 0.196117 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::total 0.359923 # miss rate for demand accesses
|
||||
system.l2c.overall_miss_rate::cpu0.inst 0.015099 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu0.data 0.537413 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu1.inst 0.021085 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu1.data 0.196117 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::total 0.359923 # miss rate for overall accesses
|
||||
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.l2c.fast_writes 0 # number of fast writes performed
|
||||
system.l2c.cache_copies 0 # number of cache copies performed
|
||||
system.l2c.writebacks::writebacks 121798 # number of writebacks
|
||||
system.l2c.writebacks::total 121798 # number of writebacks
|
||||
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.iocache.replacements 41695 # number of replacements
|
||||
system.iocache.tagsinuse 0.435437 # Cycle average of tags in use
|
||||
system.iocache.total_refs 0 # Total number of references to valid blocks.
|
||||
system.iocache.sampled_refs 41711 # Sample count of references to valid blocks.
|
||||
system.iocache.avg_refs 0 # Average number of references to valid blocks.
|
||||
system.iocache.warmup_cycle 1685787165017 # Cycle when the warmup percentage was hit.
|
||||
system.iocache.occ_blocks::tsunami.ide 0.435437 # Average occupied blocks per requestor
|
||||
system.iocache.occ_percent::tsunami.ide 0.027215 # Average percentage of cache occupancy
|
||||
system.iocache.occ_percent::total 0.027215 # Average percentage of cache occupancy
|
||||
system.iocache.ReadReq_misses::tsunami.ide 175 # number of ReadReq misses
|
||||
system.iocache.ReadReq_misses::total 175 # number of ReadReq misses
|
||||
system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses
|
||||
system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses
|
||||
system.iocache.demand_misses::tsunami.ide 41727 # number of demand (read+write) misses
|
||||
system.iocache.demand_misses::total 41727 # number of demand (read+write) misses
|
||||
system.iocache.overall_misses::tsunami.ide 41727 # number of overall misses
|
||||
system.iocache.overall_misses::total 41727 # number of overall misses
|
||||
system.iocache.ReadReq_accesses::tsunami.ide 175 # number of ReadReq accesses(hits+misses)
|
||||
system.iocache.ReadReq_accesses::total 175 # number of ReadReq accesses(hits+misses)
|
||||
system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses)
|
||||
system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses)
|
||||
system.iocache.demand_accesses::tsunami.ide 41727 # number of demand (read+write) accesses
|
||||
system.iocache.demand_accesses::total 41727 # number of demand (read+write) accesses
|
||||
system.iocache.overall_accesses::tsunami.ide 41727 # number of overall (read+write) accesses
|
||||
system.iocache.overall_accesses::total 41727 # number of overall (read+write) accesses
|
||||
system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
|
||||
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
|
||||
system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses
|
||||
system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
|
||||
system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses
|
||||
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
|
||||
system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
|
||||
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
|
||||
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.iocache.fast_writes 0 # number of fast writes performed
|
||||
system.iocache.cache_copies 0 # number of cache copies performed
|
||||
system.iocache.writebacks::writebacks 41520 # number of writebacks
|
||||
system.iocache.writebacks::total 41520 # number of writebacks
|
||||
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
||||
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
|
||||
system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
|
||||
system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
|
||||
system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
|
||||
system.disk0.dma_write_txs 395 # Number of DMA write transactions.
|
||||
system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
||||
system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
|
||||
system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
|
||||
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
|
||||
system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
|
||||
system.disk2.dma_write_txs 1 # Number of DMA write transactions.
|
||||
system.cpu0.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu0.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu0.dtb.fetch_acv 0 # ITB acv
|
||||
system.cpu0.dtb.fetch_accesses 0 # ITB accesses
|
||||
system.cpu0.dtb.read_hits 9154530 # DTB read hits
|
||||
system.cpu0.dtb.read_misses 7079 # DTB read misses
|
||||
system.cpu0.dtb.read_acv 152 # DTB read access violations
|
||||
system.cpu0.dtb.read_accesses 508987 # DTB read accesses
|
||||
system.cpu0.dtb.write_hits 5936899 # DTB write hits
|
||||
system.cpu0.dtb.write_misses 726 # DTB write misses
|
||||
system.cpu0.dtb.write_acv 99 # DTB write access violations
|
||||
system.cpu0.dtb.write_accesses 189050 # DTB write accesses
|
||||
system.cpu0.dtb.data_hits 15091429 # DTB hits
|
||||
system.cpu0.dtb.data_misses 7805 # DTB misses
|
||||
system.cpu0.dtb.data_acv 251 # DTB access violations
|
||||
system.cpu0.dtb.data_accesses 698037 # DTB accesses
|
||||
system.cpu0.itb.fetch_hits 3855556 # ITB hits
|
||||
system.cpu0.itb.fetch_misses 3485 # ITB misses
|
||||
system.cpu0.itb.fetch_acv 127 # ITB acv
|
||||
system.cpu0.itb.fetch_accesses 3859041 # ITB accesses
|
||||
system.cpu0.itb.read_hits 0 # DTB read hits
|
||||
system.cpu0.itb.read_misses 0 # DTB read misses
|
||||
system.cpu0.itb.read_acv 0 # DTB read access violations
|
||||
system.cpu0.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu0.itb.write_hits 0 # DTB write hits
|
||||
system.cpu0.itb.write_misses 0 # DTB write misses
|
||||
system.cpu0.itb.write_acv 0 # DTB write access violations
|
||||
system.cpu0.itb.write_accesses 0 # DTB write accesses
|
||||
system.cpu0.itb.data_hits 0 # DTB hits
|
||||
system.cpu0.itb.data_misses 0 # DTB misses
|
||||
system.cpu0.itb.data_acv 0 # DTB access violations
|
||||
system.cpu0.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu0.numCycles 3740670933 # number of cpu cycles simulated
|
||||
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu0.committedInsts 57222076 # Number of instructions committed
|
||||
system.cpu0.committedOps 57222076 # Number of ops (including micro ops) committed
|
||||
system.cpu0.num_int_alu_accesses 53249924 # Number of integer alu accesses
|
||||
system.cpu0.num_fp_alu_accesses 299810 # Number of float alu accesses
|
||||
system.cpu0.num_func_calls 1399585 # number of times a function call or return occured
|
||||
system.cpu0.num_conditional_control_insts 6808233 # number of instructions that are conditional controls
|
||||
system.cpu0.num_int_insts 53249924 # number of integer instructions
|
||||
system.cpu0.num_fp_insts 299810 # number of float instructions
|
||||
system.cpu0.num_int_register_reads 73318596 # number of times the integer registers were read
|
||||
system.cpu0.num_int_register_writes 39827534 # number of times the integer registers were written
|
||||
system.cpu0.num_fp_register_reads 147724 # number of times the floating registers were read
|
||||
system.cpu0.num_fp_register_writes 150835 # number of times the floating registers were written
|
||||
system.cpu0.num_mem_refs 15135515 # number of memory refs
|
||||
system.cpu0.num_load_insts 9184477 # Number of load instructions
|
||||
system.cpu0.num_store_insts 5951038 # Number of store instructions
|
||||
system.cpu0.num_idle_cycles 3683437089.313678 # Number of idle cycles
|
||||
system.cpu0.num_busy_cycles 57233843.686322 # Number of busy cycles
|
||||
system.cpu0.not_idle_fraction 0.015300 # Percentage of non-idle cycles
|
||||
system.cpu0.idle_fraction 0.984700 # Percentage of idle cycles
|
||||
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
|
||||
system.cpu0.kern.inst.quiesce 6283 # number of quiesce instructions executed
|
||||
system.cpu0.kern.inst.hwrei 197120 # number of hwrei instructions executed
|
||||
system.cpu0.kern.ipl_count::0 71004 40.60% 40.60% # number of times we switched to this ipl
|
||||
system.cpu0.kern.ipl_count::21 243 0.14% 40.74% # number of times we switched to this ipl
|
||||
system.cpu0.kern.ipl_count::22 1908 1.09% 41.83% # number of times we switched to this ipl
|
||||
system.cpu0.kern.ipl_count::30 8 0.00% 41.84% # number of times we switched to this ipl
|
||||
system.cpu0.kern.ipl_count::31 101705 58.16% 100.00% # number of times we switched to this ipl
|
||||
system.cpu0.kern.ipl_count::total 174868 # number of times we switched to this ipl
|
||||
system.cpu0.kern.ipl_good::0 69637 49.24% 49.24% # number of times we switched to this ipl from a different ipl
|
||||
system.cpu0.kern.ipl_good::21 243 0.17% 49.41% # number of times we switched to this ipl from a different ipl
|
||||
system.cpu0.kern.ipl_good::22 1908 1.35% 50.76% # number of times we switched to this ipl from a different ipl
|
||||
system.cpu0.kern.ipl_good::30 8 0.01% 50.77% # number of times we switched to this ipl from a different ipl
|
||||
system.cpu0.kern.ipl_good::31 69629 49.23% 100.00% # number of times we switched to this ipl from a different ipl
|
||||
system.cpu0.kern.ipl_good::total 141425 # number of times we switched to this ipl from a different ipl
|
||||
system.cpu0.kern.ipl_ticks::0 1852989766500 99.07% 99.07% # number of cycles we spent at this ipl
|
||||
system.cpu0.kern.ipl_ticks::21 20110000 0.00% 99.07% # number of cycles we spent at this ipl
|
||||
system.cpu0.kern.ipl_ticks::22 82044000 0.00% 99.08% # number of cycles we spent at this ipl
|
||||
system.cpu0.kern.ipl_ticks::30 949500 0.00% 99.08% # number of cycles we spent at this ipl
|
||||
system.cpu0.kern.ipl_ticks::31 17242445000 0.92% 100.00% # number of cycles we spent at this ipl
|
||||
system.cpu0.kern.ipl_ticks::total 1870335315000 # number of cycles we spent at this ipl
|
||||
system.cpu0.kern.ipl_used::0 0.980748 # fraction of swpipl calls that actually changed the ipl
|
||||
system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
|
||||
system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
|
||||
system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
|
||||
system.cpu0.kern.ipl_used::31 0.684617 # fraction of swpipl calls that actually changed the ipl
|
||||
system.cpu0.kern.ipl_used::total 0.808753 # fraction of swpipl calls that actually changed the ipl
|
||||
system.cpu0.kern.syscall::2 6 2.65% 2.65% # number of syscalls executed
|
||||
system.cpu0.kern.syscall::3 19 8.41% 11.06% # number of syscalls executed
|
||||
system.cpu0.kern.syscall::4 2 0.88% 11.95% # number of syscalls executed
|
||||
system.cpu0.kern.syscall::6 32 14.16% 26.11% # number of syscalls executed
|
||||
system.cpu0.kern.syscall::12 1 0.44% 26.55% # number of syscalls executed
|
||||
system.cpu0.kern.syscall::15 1 0.44% 26.99% # number of syscalls executed
|
||||
system.cpu0.kern.syscall::17 9 3.98% 30.97% # number of syscalls executed
|
||||
system.cpu0.kern.syscall::19 8 3.54% 34.51% # number of syscalls executed
|
||||
system.cpu0.kern.syscall::20 6 2.65% 37.17% # number of syscalls executed
|
||||
system.cpu0.kern.syscall::23 2 0.88% 38.05% # number of syscalls executed
|
||||
system.cpu0.kern.syscall::24 4 1.77% 39.82% # number of syscalls executed
|
||||
system.cpu0.kern.syscall::33 7 3.10% 42.92% # number of syscalls executed
|
||||
system.cpu0.kern.syscall::41 2 0.88% 43.81% # number of syscalls executed
|
||||
system.cpu0.kern.syscall::45 37 16.37% 60.18% # number of syscalls executed
|
||||
system.cpu0.kern.syscall::47 4 1.77% 61.95% # number of syscalls executed
|
||||
system.cpu0.kern.syscall::48 8 3.54% 65.49% # number of syscalls executed
|
||||
system.cpu0.kern.syscall::54 10 4.42% 69.91% # number of syscalls executed
|
||||
system.cpu0.kern.syscall::58 1 0.44% 70.35% # number of syscalls executed
|
||||
system.cpu0.kern.syscall::59 4 1.77% 72.12% # number of syscalls executed
|
||||
system.cpu0.kern.syscall::71 30 13.27% 85.40% # number of syscalls executed
|
||||
system.cpu0.kern.syscall::73 3 1.33% 86.73% # number of syscalls executed
|
||||
system.cpu0.kern.syscall::74 8 3.54% 90.27% # number of syscalls executed
|
||||
system.cpu0.kern.syscall::87 1 0.44% 90.71% # number of syscalls executed
|
||||
system.cpu0.kern.syscall::90 2 0.88% 91.59% # number of syscalls executed
|
||||
system.cpu0.kern.syscall::92 9 3.98% 95.58% # number of syscalls executed
|
||||
system.cpu0.kern.syscall::97 2 0.88% 96.46% # number of syscalls executed
|
||||
system.cpu0.kern.syscall::98 2 0.88% 97.35% # number of syscalls executed
|
||||
system.cpu0.kern.syscall::132 2 0.88% 98.23% # number of syscalls executed
|
||||
system.cpu0.kern.syscall::144 2 0.88% 99.12% # number of syscalls executed
|
||||
system.cpu0.kern.syscall::147 2 0.88% 100.00% # number of syscalls executed
|
||||
system.cpu0.kern.syscall::total 226 # number of syscalls executed
|
||||
system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
|
||||
system.cpu0.kern.callpal::wripir 110 0.06% 0.06% # number of callpals executed
|
||||
system.cpu0.kern.callpal::wrmces 1 0.00% 0.06% # number of callpals executed
|
||||
system.cpu0.kern.callpal::wrfen 1 0.00% 0.06% # number of callpals executed
|
||||
system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.06% # number of callpals executed
|
||||
system.cpu0.kern.callpal::swpctx 3762 2.05% 2.11% # number of callpals executed
|
||||
system.cpu0.kern.callpal::tbi 38 0.02% 2.14% # number of callpals executed
|
||||
system.cpu0.kern.callpal::wrent 7 0.00% 2.14% # number of callpals executed
|
||||
system.cpu0.kern.callpal::swpipl 168035 91.68% 93.82% # number of callpals executed
|
||||
system.cpu0.kern.callpal::rdps 6150 3.36% 97.17% # number of callpals executed
|
||||
system.cpu0.kern.callpal::wrkgp 1 0.00% 97.17% # number of callpals executed
|
||||
system.cpu0.kern.callpal::wrusp 3 0.00% 97.17% # number of callpals executed
|
||||
system.cpu0.kern.callpal::rdusp 7 0.00% 97.18% # number of callpals executed
|
||||
system.cpu0.kern.callpal::whami 2 0.00% 97.18% # number of callpals executed
|
||||
system.cpu0.kern.callpal::rti 4673 2.55% 99.73% # number of callpals executed
|
||||
system.cpu0.kern.callpal::callsys 357 0.19% 99.92% # number of callpals executed
|
||||
system.cpu0.kern.callpal::imb 142 0.08% 100.00% # number of callpals executed
|
||||
system.cpu0.kern.callpal::total 183291 # number of callpals executed
|
||||
system.cpu0.kern.mode_switch::kernel 7091 # number of protection mode switches
|
||||
system.cpu0.kern.mode_switch::user 1158 # number of protection mode switches
|
||||
system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches
|
||||
system.cpu0.kern.mode_good::kernel 1157
|
||||
system.cpu0.kern.mode_good::user 1158
|
||||
system.cpu0.kern.mode_good::idle 0
|
||||
system.cpu0.kern.mode_switch_good::kernel 0.163165 # fraction of useful protection mode switches
|
||||
system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
|
||||
system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches
|
||||
system.cpu0.kern.mode_switch_good::total 0.280640 # fraction of useful protection mode switches
|
||||
system.cpu0.kern.mode_ticks::kernel 1869378305000 99.95% 99.95% # number of ticks spent at the given mode
|
||||
system.cpu0.kern.mode_ticks::user 957009000 0.05% 100.00% # number of ticks spent at the given mode
|
||||
system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode
|
||||
system.cpu0.kern.swap_context 3763 # number of times the context was actually changed
|
||||
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
|
||||
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
|
||||
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
|
||||
system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
|
||||
system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
|
||||
system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
|
||||
system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
|
||||
system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
|
||||
system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
|
||||
system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
|
||||
system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
|
||||
system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
|
||||
system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
|
||||
system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
|
||||
system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
|
||||
system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
|
||||
system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
|
||||
system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
|
||||
system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
|
||||
system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
|
||||
system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
|
||||
system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
|
||||
system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
|
||||
system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
|
||||
system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
|
||||
system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
|
||||
system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
|
||||
system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
|
||||
system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
|
||||
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
|
||||
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
|
||||
system.cpu0.icache.replacements 884404 # number of replacements
|
||||
system.cpu0.icache.tagsinuse 511.244754 # Cycle average of tags in use
|
||||
system.cpu0.icache.total_refs 56345132 # Total number of references to valid blocks.
|
||||
system.cpu0.icache.sampled_refs 884916 # Sample count of references to valid blocks.
|
||||
system.cpu0.icache.avg_refs 63.672859 # Average number of references to valid blocks.
|
||||
system.cpu0.icache.warmup_cycle 9786576500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu0.icache.occ_blocks::cpu0.inst 511.244754 # Average occupied blocks per requestor
|
||||
system.cpu0.icache.occ_percent::cpu0.inst 0.998525 # Average percentage of cache occupancy
|
||||
system.cpu0.icache.occ_percent::total 0.998525 # Average percentage of cache occupancy
|
||||
system.cpu0.icache.ReadReq_hits::cpu0.inst 56345132 # number of ReadReq hits
|
||||
system.cpu0.icache.ReadReq_hits::total 56345132 # number of ReadReq hits
|
||||
system.cpu0.icache.demand_hits::cpu0.inst 56345132 # number of demand (read+write) hits
|
||||
system.cpu0.icache.demand_hits::total 56345132 # number of demand (read+write) hits
|
||||
system.cpu0.icache.overall_hits::cpu0.inst 56345132 # number of overall hits
|
||||
system.cpu0.icache.overall_hits::total 56345132 # number of overall hits
|
||||
system.cpu0.icache.ReadReq_misses::cpu0.inst 885000 # number of ReadReq misses
|
||||
system.cpu0.icache.ReadReq_misses::total 885000 # number of ReadReq misses
|
||||
system.cpu0.icache.demand_misses::cpu0.inst 885000 # number of demand (read+write) misses
|
||||
system.cpu0.icache.demand_misses::total 885000 # number of demand (read+write) misses
|
||||
system.cpu0.icache.overall_misses::cpu0.inst 885000 # number of overall misses
|
||||
system.cpu0.icache.overall_misses::total 885000 # number of overall misses
|
||||
system.cpu0.icache.ReadReq_accesses::cpu0.inst 57230132 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu0.icache.ReadReq_accesses::total 57230132 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu0.icache.demand_accesses::cpu0.inst 57230132 # number of demand (read+write) accesses
|
||||
system.cpu0.icache.demand_accesses::total 57230132 # number of demand (read+write) accesses
|
||||
system.cpu0.icache.overall_accesses::cpu0.inst 57230132 # number of overall (read+write) accesses
|
||||
system.cpu0.icache.overall_accesses::total 57230132 # number of overall (read+write) accesses
|
||||
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.015464 # miss rate for ReadReq accesses
|
||||
system.cpu0.icache.ReadReq_miss_rate::total 0.015464 # miss rate for ReadReq accesses
|
||||
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.015464 # miss rate for demand accesses
|
||||
system.cpu0.icache.demand_miss_rate::total 0.015464 # miss rate for demand accesses
|
||||
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.015464 # miss rate for overall accesses
|
||||
system.cpu0.icache.overall_miss_rate::total 0.015464 # miss rate for overall accesses
|
||||
system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu0.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu0.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu0.icache.writebacks::writebacks 95 # number of writebacks
|
||||
system.cpu0.icache.writebacks::total 95 # number of writebacks
|
||||
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu0.dcache.replacements 1978962 # number of replacements
|
||||
system.cpu0.dcache.tagsinuse 504.827058 # Cycle average of tags in use
|
||||
system.cpu0.dcache.total_refs 13123502 # Total number of references to valid blocks.
|
||||
system.cpu0.dcache.sampled_refs 1979474 # Sample count of references to valid blocks.
|
||||
system.cpu0.dcache.avg_refs 6.629793 # Average number of references to valid blocks.
|
||||
system.cpu0.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu0.dcache.occ_blocks::cpu0.data 504.827058 # Average occupied blocks per requestor
|
||||
system.cpu0.dcache.occ_percent::cpu0.data 0.985990 # Average percentage of cache occupancy
|
||||
system.cpu0.dcache.occ_percent::total 0.985990 # Average percentage of cache occupancy
|
||||
system.cpu0.dcache.ReadReq_hits::cpu0.data 7298106 # number of ReadReq hits
|
||||
system.cpu0.dcache.ReadReq_hits::total 7298106 # number of ReadReq hits
|
||||
system.cpu0.dcache.WriteReq_hits::cpu0.data 5462265 # number of WriteReq hits
|
||||
system.cpu0.dcache.WriteReq_hits::total 5462265 # number of WriteReq hits
|
||||
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 172138 # number of LoadLockedReq hits
|
||||
system.cpu0.dcache.LoadLockedReq_hits::total 172138 # number of LoadLockedReq hits
|
||||
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 186635 # number of StoreCondReq hits
|
||||
system.cpu0.dcache.StoreCondReq_hits::total 186635 # number of StoreCondReq hits
|
||||
system.cpu0.dcache.demand_hits::cpu0.data 12760371 # number of demand (read+write) hits
|
||||
system.cpu0.dcache.demand_hits::total 12760371 # number of demand (read+write) hits
|
||||
system.cpu0.dcache.overall_hits::cpu0.data 12760371 # number of overall hits
|
||||
system.cpu0.dcache.overall_hits::total 12760371 # number of overall hits
|
||||
system.cpu0.dcache.ReadReq_misses::cpu0.data 1683563 # number of ReadReq misses
|
||||
system.cpu0.dcache.ReadReq_misses::total 1683563 # number of ReadReq misses
|
||||
system.cpu0.dcache.WriteReq_misses::cpu0.data 285996 # number of WriteReq misses
|
||||
system.cpu0.dcache.WriteReq_misses::total 285996 # number of WriteReq misses
|
||||
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 16159 # number of LoadLockedReq misses
|
||||
system.cpu0.dcache.LoadLockedReq_misses::total 16159 # number of LoadLockedReq misses
|
||||
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 703 # number of StoreCondReq misses
|
||||
system.cpu0.dcache.StoreCondReq_misses::total 703 # number of StoreCondReq misses
|
||||
system.cpu0.dcache.demand_misses::cpu0.data 1969559 # number of demand (read+write) misses
|
||||
system.cpu0.dcache.demand_misses::total 1969559 # number of demand (read+write) misses
|
||||
system.cpu0.dcache.overall_misses::cpu0.data 1969559 # number of overall misses
|
||||
system.cpu0.dcache.overall_misses::total 1969559 # number of overall misses
|
||||
system.cpu0.dcache.ReadReq_accesses::cpu0.data 8981669 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu0.dcache.ReadReq_accesses::total 8981669 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu0.dcache.WriteReq_accesses::cpu0.data 5748261 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu0.dcache.WriteReq_accesses::total 5748261 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 188297 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu0.dcache.LoadLockedReq_accesses::total 188297 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 187338 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu0.dcache.StoreCondReq_accesses::total 187338 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu0.dcache.demand_accesses::cpu0.data 14729930 # number of demand (read+write) accesses
|
||||
system.cpu0.dcache.demand_accesses::total 14729930 # number of demand (read+write) accesses
|
||||
system.cpu0.dcache.overall_accesses::cpu0.data 14729930 # number of overall (read+write) accesses
|
||||
system.cpu0.dcache.overall_accesses::total 14729930 # number of overall (read+write) accesses
|
||||
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.187444 # miss rate for ReadReq accesses
|
||||
system.cpu0.dcache.ReadReq_miss_rate::total 0.187444 # miss rate for ReadReq accesses
|
||||
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049753 # miss rate for WriteReq accesses
|
||||
system.cpu0.dcache.WriteReq_miss_rate::total 0.049753 # miss rate for WriteReq accesses
|
||||
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.085817 # miss rate for LoadLockedReq accesses
|
||||
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.085817 # miss rate for LoadLockedReq accesses
|
||||
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.003753 # miss rate for StoreCondReq accesses
|
||||
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.003753 # miss rate for StoreCondReq accesses
|
||||
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.133711 # miss rate for demand accesses
|
||||
system.cpu0.dcache.demand_miss_rate::total 0.133711 # miss rate for demand accesses
|
||||
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.133711 # miss rate for overall accesses
|
||||
system.cpu0.dcache.overall_miss_rate::total 0.133711 # miss rate for overall accesses
|
||||
system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu0.dcache.writebacks::writebacks 771740 # number of writebacks
|
||||
system.cpu0.dcache.writebacks::total 771740 # number of writebacks
|
||||
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu1.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu1.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu1.dtb.fetch_acv 0 # ITB acv
|
||||
system.cpu1.dtb.fetch_accesses 0 # ITB accesses
|
||||
system.cpu1.dtb.read_hits 1163439 # DTB read hits
|
||||
system.cpu1.dtb.read_misses 3277 # DTB read misses
|
||||
system.cpu1.dtb.read_acv 58 # DTB read access violations
|
||||
system.cpu1.dtb.read_accesses 220342 # DTB read accesses
|
||||
system.cpu1.dtb.write_hits 751446 # DTB write hits
|
||||
system.cpu1.dtb.write_misses 415 # DTB write misses
|
||||
system.cpu1.dtb.write_acv 58 # DTB write access violations
|
||||
system.cpu1.dtb.write_accesses 103280 # DTB write accesses
|
||||
system.cpu1.dtb.data_hits 1914885 # DTB hits
|
||||
system.cpu1.dtb.data_misses 3692 # DTB misses
|
||||
system.cpu1.dtb.data_acv 116 # DTB access violations
|
||||
system.cpu1.dtb.data_accesses 323622 # DTB accesses
|
||||
system.cpu1.itb.fetch_hits 1468399 # ITB hits
|
||||
system.cpu1.itb.fetch_misses 1539 # ITB misses
|
||||
system.cpu1.itb.fetch_acv 57 # ITB acv
|
||||
system.cpu1.itb.fetch_accesses 1469938 # ITB accesses
|
||||
system.cpu1.itb.read_hits 0 # DTB read hits
|
||||
system.cpu1.itb.read_misses 0 # DTB read misses
|
||||
system.cpu1.itb.read_acv 0 # DTB read access violations
|
||||
system.cpu1.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu1.itb.write_hits 0 # DTB write hits
|
||||
system.cpu1.itb.write_misses 0 # DTB write misses
|
||||
system.cpu1.itb.write_acv 0 # DTB write access violations
|
||||
system.cpu1.itb.write_accesses 0 # DTB write accesses
|
||||
system.cpu1.itb.data_hits 0 # DTB hits
|
||||
system.cpu1.itb.data_misses 0 # DTB misses
|
||||
system.cpu1.itb.data_acv 0 # DTB access violations
|
||||
system.cpu1.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu1.numCycles 3740248881 # number of cpu cycles simulated
|
||||
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu1.committedInsts 5931958 # Number of instructions committed
|
||||
system.cpu1.committedOps 5931958 # Number of ops (including micro ops) committed
|
||||
system.cpu1.num_int_alu_accesses 5550578 # Number of integer alu accesses
|
||||
system.cpu1.num_fp_alu_accesses 28590 # Number of float alu accesses
|
||||
system.cpu1.num_func_calls 182742 # number of times a function call or return occured
|
||||
system.cpu1.num_conditional_control_insts 577190 # number of instructions that are conditional controls
|
||||
system.cpu1.num_int_insts 5550578 # number of integer instructions
|
||||
system.cpu1.num_fp_insts 28590 # number of float instructions
|
||||
system.cpu1.num_int_register_reads 7657288 # number of times the integer registers were read
|
||||
system.cpu1.num_int_register_writes 4163275 # number of times the integer registers were written
|
||||
system.cpu1.num_fp_register_reads 17889 # number of times the floating registers were read
|
||||
system.cpu1.num_fp_register_writes 17683 # number of times the floating registers were written
|
||||
system.cpu1.num_mem_refs 1926244 # number of memory refs
|
||||
system.cpu1.num_load_insts 1170888 # Number of load instructions
|
||||
system.cpu1.num_store_insts 755356 # Number of store instructions
|
||||
system.cpu1.num_idle_cycles 3734312190.077655 # Number of idle cycles
|
||||
system.cpu1.num_busy_cycles 5936690.922345 # Number of busy cycles
|
||||
system.cpu1.not_idle_fraction 0.001587 # Percentage of non-idle cycles
|
||||
system.cpu1.idle_fraction 0.998413 # Percentage of idle cycles
|
||||
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
|
||||
system.cpu1.kern.inst.quiesce 2204 # number of quiesce instructions executed
|
||||
system.cpu1.kern.inst.hwrei 39554 # number of hwrei instructions executed
|
||||
system.cpu1.kern.ipl_count::0 10328 33.46% 33.46% # number of times we switched to this ipl
|
||||
system.cpu1.kern.ipl_count::22 1907 6.18% 39.64% # number of times we switched to this ipl
|
||||
system.cpu1.kern.ipl_count::30 110 0.36% 40.00% # number of times we switched to this ipl
|
||||
system.cpu1.kern.ipl_count::31 18518 60.00% 100.00% # number of times we switched to this ipl
|
||||
system.cpu1.kern.ipl_count::total 30863 # number of times we switched to this ipl
|
||||
system.cpu1.kern.ipl_good::0 10318 45.77% 45.77% # number of times we switched to this ipl from a different ipl
|
||||
system.cpu1.kern.ipl_good::22 1907 8.46% 54.23% # number of times we switched to this ipl from a different ipl
|
||||
system.cpu1.kern.ipl_good::30 110 0.49% 54.72% # number of times we switched to this ipl from a different ipl
|
||||
system.cpu1.kern.ipl_good::31 10208 45.28% 100.00% # number of times we switched to this ipl from a different ipl
|
||||
system.cpu1.kern.ipl_good::total 22543 # number of times we switched to this ipl from a different ipl
|
||||
system.cpu1.kern.ipl_ticks::0 1859123008500 99.41% 99.41% # number of cycles we spent at this ipl
|
||||
system.cpu1.kern.ipl_ticks::22 82001000 0.00% 99.42% # number of cycles we spent at this ipl
|
||||
system.cpu1.kern.ipl_ticks::30 14064500 0.00% 99.42% # number of cycles we spent at this ipl
|
||||
system.cpu1.kern.ipl_ticks::31 10905353000 0.58% 100.00% # number of cycles we spent at this ipl
|
||||
system.cpu1.kern.ipl_ticks::total 1870124427000 # number of cycles we spent at this ipl
|
||||
system.cpu1.kern.ipl_used::0 0.999032 # fraction of swpipl calls that actually changed the ipl
|
||||
system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
|
||||
system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
|
||||
system.cpu1.kern.ipl_used::31 0.551247 # fraction of swpipl calls that actually changed the ipl
|
||||
system.cpu1.kern.ipl_used::total 0.730422 # fraction of swpipl calls that actually changed the ipl
|
||||
system.cpu1.kern.syscall::2 2 2.00% 2.00% # number of syscalls executed
|
||||
system.cpu1.kern.syscall::3 11 11.00% 13.00% # number of syscalls executed
|
||||
system.cpu1.kern.syscall::4 2 2.00% 15.00% # number of syscalls executed
|
||||
system.cpu1.kern.syscall::6 10 10.00% 25.00% # number of syscalls executed
|
||||
system.cpu1.kern.syscall::17 6 6.00% 31.00% # number of syscalls executed
|
||||
system.cpu1.kern.syscall::19 2 2.00% 33.00% # number of syscalls executed
|
||||
system.cpu1.kern.syscall::23 2 2.00% 35.00% # number of syscalls executed
|
||||
system.cpu1.kern.syscall::24 2 2.00% 37.00% # number of syscalls executed
|
||||
system.cpu1.kern.syscall::33 4 4.00% 41.00% # number of syscalls executed
|
||||
system.cpu1.kern.syscall::45 17 17.00% 58.00% # number of syscalls executed
|
||||
system.cpu1.kern.syscall::47 2 2.00% 60.00% # number of syscalls executed
|
||||
system.cpu1.kern.syscall::48 2 2.00% 62.00% # number of syscalls executed
|
||||
system.cpu1.kern.syscall::59 3 3.00% 65.00% # number of syscalls executed
|
||||
system.cpu1.kern.syscall::71 24 24.00% 89.00% # number of syscalls executed
|
||||
system.cpu1.kern.syscall::74 8 8.00% 97.00% # number of syscalls executed
|
||||
system.cpu1.kern.syscall::90 1 1.00% 98.00% # number of syscalls executed
|
||||
system.cpu1.kern.syscall::132 2 2.00% 100.00% # number of syscalls executed
|
||||
system.cpu1.kern.syscall::total 100 # number of syscalls executed
|
||||
system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
|
||||
system.cpu1.kern.callpal::wripir 8 0.02% 0.03% # number of callpals executed
|
||||
system.cpu1.kern.callpal::wrmces 1 0.00% 0.03% # number of callpals executed
|
||||
system.cpu1.kern.callpal::wrfen 1 0.00% 0.03% # number of callpals executed
|
||||
system.cpu1.kern.callpal::swpctx 470 1.46% 1.50% # number of callpals executed
|
||||
system.cpu1.kern.callpal::tbi 15 0.05% 1.54% # number of callpals executed
|
||||
system.cpu1.kern.callpal::wrent 7 0.02% 1.57% # number of callpals executed
|
||||
system.cpu1.kern.callpal::swpipl 26238 81.66% 83.22% # number of callpals executed
|
||||
system.cpu1.kern.callpal::rdps 2576 8.02% 91.24% # number of callpals executed
|
||||
system.cpu1.kern.callpal::wrkgp 1 0.00% 91.25% # number of callpals executed
|
||||
system.cpu1.kern.callpal::wrusp 4 0.01% 91.26% # number of callpals executed
|
||||
system.cpu1.kern.callpal::rdusp 2 0.01% 91.26% # number of callpals executed
|
||||
system.cpu1.kern.callpal::whami 3 0.01% 91.27% # number of callpals executed
|
||||
system.cpu1.kern.callpal::rti 2607 8.11% 99.39% # number of callpals executed
|
||||
system.cpu1.kern.callpal::callsys 158 0.49% 99.88% # number of callpals executed
|
||||
system.cpu1.kern.callpal::imb 38 0.12% 100.00% # number of callpals executed
|
||||
system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed
|
||||
system.cpu1.kern.callpal::total 32131 # number of callpals executed
|
||||
system.cpu1.kern.mode_switch::kernel 1033 # number of protection mode switches
|
||||
system.cpu1.kern.mode_switch::user 580 # number of protection mode switches
|
||||
system.cpu1.kern.mode_switch::idle 2046 # number of protection mode switches
|
||||
system.cpu1.kern.mode_good::kernel 612
|
||||
system.cpu1.kern.mode_good::user 580
|
||||
system.cpu1.kern.mode_good::idle 32
|
||||
system.cpu1.kern.mode_switch_good::kernel 0.592449 # fraction of useful protection mode switches
|
||||
system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
|
||||
system.cpu1.kern.mode_switch_good::idle 0.015640 # fraction of useful protection mode switches
|
||||
system.cpu1.kern.mode_switch_good::total 0.334518 # fraction of useful protection mode switches
|
||||
system.cpu1.kern.mode_ticks::kernel 1373917500 0.07% 0.07% # number of ticks spent at the given mode
|
||||
system.cpu1.kern.mode_ticks::user 508289000 0.03% 0.10% # number of ticks spent at the given mode
|
||||
system.cpu1.kern.mode_ticks::idle 1868002549000 99.90% 100.00% # number of ticks spent at the given mode
|
||||
system.cpu1.kern.swap_context 471 # number of times the context was actually changed
|
||||
system.cpu1.icache.replacements 103091 # number of replacements
|
||||
system.cpu1.icache.tagsinuse 427.126317 # Cycle average of tags in use
|
||||
system.cpu1.icache.total_refs 5832136 # Total number of references to valid blocks.
|
||||
system.cpu1.icache.sampled_refs 103603 # Sample count of references to valid blocks.
|
||||
system.cpu1.icache.avg_refs 56.293119 # Average number of references to valid blocks.
|
||||
system.cpu1.icache.warmup_cycle 1868933059000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu1.icache.occ_blocks::cpu1.inst 427.126317 # Average occupied blocks per requestor
|
||||
system.cpu1.icache.occ_percent::cpu1.inst 0.834231 # Average percentage of cache occupancy
|
||||
system.cpu1.icache.occ_percent::total 0.834231 # Average percentage of cache occupancy
|
||||
system.cpu1.icache.ReadReq_hits::cpu1.inst 5832136 # number of ReadReq hits
|
||||
system.cpu1.icache.ReadReq_hits::total 5832136 # number of ReadReq hits
|
||||
system.cpu1.icache.demand_hits::cpu1.inst 5832136 # number of demand (read+write) hits
|
||||
system.cpu1.icache.demand_hits::total 5832136 # number of demand (read+write) hits
|
||||
system.cpu1.icache.overall_hits::cpu1.inst 5832136 # number of overall hits
|
||||
system.cpu1.icache.overall_hits::total 5832136 # number of overall hits
|
||||
system.cpu1.icache.ReadReq_misses::cpu1.inst 103630 # number of ReadReq misses
|
||||
system.cpu1.icache.ReadReq_misses::total 103630 # number of ReadReq misses
|
||||
system.cpu1.icache.demand_misses::cpu1.inst 103630 # number of demand (read+write) misses
|
||||
system.cpu1.icache.demand_misses::total 103630 # number of demand (read+write) misses
|
||||
system.cpu1.icache.overall_misses::cpu1.inst 103630 # number of overall misses
|
||||
system.cpu1.icache.overall_misses::total 103630 # number of overall misses
|
||||
system.cpu1.icache.ReadReq_accesses::cpu1.inst 5935766 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu1.icache.ReadReq_accesses::total 5935766 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu1.icache.demand_accesses::cpu1.inst 5935766 # number of demand (read+write) accesses
|
||||
system.cpu1.icache.demand_accesses::total 5935766 # number of demand (read+write) accesses
|
||||
system.cpu1.icache.overall_accesses::cpu1.inst 5935766 # number of overall (read+write) accesses
|
||||
system.cpu1.icache.overall_accesses::total 5935766 # number of overall (read+write) accesses
|
||||
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.017459 # miss rate for ReadReq accesses
|
||||
system.cpu1.icache.ReadReq_miss_rate::total 0.017459 # miss rate for ReadReq accesses
|
||||
system.cpu1.icache.demand_miss_rate::cpu1.inst 0.017459 # miss rate for demand accesses
|
||||
system.cpu1.icache.demand_miss_rate::total 0.017459 # miss rate for demand accesses
|
||||
system.cpu1.icache.overall_miss_rate::cpu1.inst 0.017459 # miss rate for overall accesses
|
||||
system.cpu1.icache.overall_miss_rate::total 0.017459 # miss rate for overall accesses
|
||||
system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu1.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu1.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu1.icache.writebacks::writebacks 15 # number of writebacks
|
||||
system.cpu1.icache.writebacks::total 15 # number of writebacks
|
||||
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu1.dcache.replacements 62338 # number of replacements
|
||||
system.cpu1.dcache.tagsinuse 391.951263 # Cycle average of tags in use
|
||||
system.cpu1.dcache.total_refs 1834544 # Total number of references to valid blocks.
|
||||
system.cpu1.dcache.sampled_refs 62657 # Sample count of references to valid blocks.
|
||||
system.cpu1.dcache.avg_refs 29.279155 # Average number of references to valid blocks.
|
||||
system.cpu1.dcache.warmup_cycle 1851267520500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu1.dcache.occ_blocks::cpu1.data 391.951263 # Average occupied blocks per requestor
|
||||
system.cpu1.dcache.occ_percent::cpu1.data 0.765530 # Average percentage of cache occupancy
|
||||
system.cpu1.dcache.occ_percent::total 0.765530 # Average percentage of cache occupancy
|
||||
system.cpu1.dcache.ReadReq_hits::cpu1.data 1109315 # number of ReadReq hits
|
||||
system.cpu1.dcache.ReadReq_hits::total 1109315 # number of ReadReq hits
|
||||
system.cpu1.dcache.WriteReq_hits::cpu1.data 707444 # number of WriteReq hits
|
||||
system.cpu1.dcache.WriteReq_hits::total 707444 # number of WriteReq hits
|
||||
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 15129 # number of LoadLockedReq hits
|
||||
system.cpu1.dcache.LoadLockedReq_hits::total 15129 # number of LoadLockedReq hits
|
||||
system.cpu1.dcache.StoreCondReq_hits::cpu1.data 15613 # number of StoreCondReq hits
|
||||
system.cpu1.dcache.StoreCondReq_hits::total 15613 # number of StoreCondReq hits
|
||||
system.cpu1.dcache.demand_hits::cpu1.data 1816759 # number of demand (read+write) hits
|
||||
system.cpu1.dcache.demand_hits::total 1816759 # number of demand (read+write) hits
|
||||
system.cpu1.dcache.overall_hits::cpu1.data 1816759 # number of overall hits
|
||||
system.cpu1.dcache.overall_hits::total 1816759 # number of overall hits
|
||||
system.cpu1.dcache.ReadReq_misses::cpu1.data 41650 # number of ReadReq misses
|
||||
system.cpu1.dcache.ReadReq_misses::total 41650 # number of ReadReq misses
|
||||
system.cpu1.dcache.WriteReq_misses::cpu1.data 25861 # number of WriteReq misses
|
||||
system.cpu1.dcache.WriteReq_misses::total 25861 # number of WriteReq misses
|
||||
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 1289 # number of LoadLockedReq misses
|
||||
system.cpu1.dcache.LoadLockedReq_misses::total 1289 # number of LoadLockedReq misses
|
||||
system.cpu1.dcache.StoreCondReq_misses::cpu1.data 732 # number of StoreCondReq misses
|
||||
system.cpu1.dcache.StoreCondReq_misses::total 732 # number of StoreCondReq misses
|
||||
system.cpu1.dcache.demand_misses::cpu1.data 67511 # number of demand (read+write) misses
|
||||
system.cpu1.dcache.demand_misses::total 67511 # number of demand (read+write) misses
|
||||
system.cpu1.dcache.overall_misses::cpu1.data 67511 # number of overall misses
|
||||
system.cpu1.dcache.overall_misses::total 67511 # number of overall misses
|
||||
system.cpu1.dcache.ReadReq_accesses::cpu1.data 1150965 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu1.dcache.ReadReq_accesses::total 1150965 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu1.dcache.WriteReq_accesses::cpu1.data 733305 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu1.dcache.WriteReq_accesses::total 733305 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 16418 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu1.dcache.LoadLockedReq_accesses::total 16418 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 16345 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu1.dcache.StoreCondReq_accesses::total 16345 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu1.dcache.demand_accesses::cpu1.data 1884270 # number of demand (read+write) accesses
|
||||
system.cpu1.dcache.demand_accesses::total 1884270 # number of demand (read+write) accesses
|
||||
system.cpu1.dcache.overall_accesses::cpu1.data 1884270 # number of overall (read+write) accesses
|
||||
system.cpu1.dcache.overall_accesses::total 1884270 # number of overall (read+write) accesses
|
||||
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.036187 # miss rate for ReadReq accesses
|
||||
system.cpu1.dcache.ReadReq_miss_rate::total 0.036187 # miss rate for ReadReq accesses
|
||||
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.035266 # miss rate for WriteReq accesses
|
||||
system.cpu1.dcache.WriteReq_miss_rate::total 0.035266 # miss rate for WriteReq accesses
|
||||
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.078511 # miss rate for LoadLockedReq accesses
|
||||
system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.078511 # miss rate for LoadLockedReq accesses
|
||||
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.044784 # miss rate for StoreCondReq accesses
|
||||
system.cpu1.dcache.StoreCondReq_miss_rate::total 0.044784 # miss rate for StoreCondReq accesses
|
||||
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.035829 # miss rate for demand accesses
|
||||
system.cpu1.dcache.demand_miss_rate::total 0.035829 # miss rate for demand accesses
|
||||
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.035829 # miss rate for overall accesses
|
||||
system.cpu1.dcache.overall_miss_rate::total 0.035829 # miss rate for overall accesses
|
||||
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu1.dcache.writebacks::writebacks 39996 # number of writebacks
|
||||
system.cpu1.dcache.writebacks::total 39996 # number of writebacks
|
||||
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
@ -0,0 +1,112 @@
|
||||
M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
|
||||
|
||||
Got Configuration 623
|
||||
|
||||
memsize 8000000 pages 4000
|
||||
|
||||
First free page after ROM 0xFFFFFC0000018000
|
||||
|
||||
HWRPB 0xFFFFFC0000018000 l1pt 0xFFFFFC0000040000 l2pt 0xFFFFFC0000042000 l3pt_rpb 0xFFFFFC0000044000 l3pt_kernel 0xFFFFFC0000048000 l2reserv 0xFFFFFC0000046000
|
||||
|
||||
kstart = 0xFFFFFC0000310000, kend = 0xFFFFFC0000855898, kentry = 0xFFFFFC0000310000, numCPUs = 0x2
|
||||
|
||||
CPU Clock at 2000 MHz IntrClockFrequency=1024
|
||||
|
||||
Booting with 2 processor(s)
|
||||
|
||||
KSP: 0x20043FE8 PTBR 0x20
|
||||
|
||||
KSP: 0x20043FE8 PTBR 0x20
|
||||
|
||||
Console Callback at 0x0, fixup at 0x0, crb offset: 0x790
|
||||
|
||||
Memory cluster 0 [0 - 392]
|
||||
|
||||
Memory cluster 1 [392 - 15992]
|
||||
|
||||
Initalizing mdt_bitmap addr 0xFFFFFC0000038000 mem_pages 4000
|
||||
|
||||
ConsoleDispatch at virt 100008D8 phys 188D8 val FFFFFC00000100A8
|
||||
|
||||
Bootstraping CPU 1 with sp=0xFFFFFC0000076000
|
||||
|
||||
unix_boot_mem ends at FFFFFC0000078000
|
||||
|
||||
k_argc = 0
|
||||
|
||||
jumping to kernel at 0xFFFFFC0000310000, (PCBB 0xFFFFFC0000018180 pfn 1067)
|
||||
|
||||
CallbackFixup 0 18000, t7=FFFFFC000070C000
|
||||
|
||||
Entering slaveloop for cpu 1 my_rpb=FFFFFC0000018400
|
||||
|
||||
Linux version 2.6.13 (hsul@zed.eecs.umich.edu) (gcc version 3.4.3) #1 SMP Sun Oct 8 19:52:07 EDT 2006
|
||||
|
||||
Booting GENERIC on Tsunami variation DP264 using machine vector DP264 from SRM
|
||||
|
||||
Major Options: SMP LEGACY_START VERBOSE_MCHECK
|
||||
|
||||
Command line: root=/dev/hda1 console=ttyS0
|
||||
|
||||
memcluster 0, usage 1, start 0, end 392
|
||||
|
||||
memcluster 1, usage 0, start 392, end 16384
|
||||
|
||||
freeing pages 1069:16384
|
||||
|
||||
reserving pages 1069:1070
|
||||
|
||||
SMP: 2 CPUs probed -- cpu_present_mask = 3
|
||||
|
||||
Built 1 zonelists
|
||||
|
||||
Kernel command line: root=/dev/hda1 console=ttyS0
|
||||
|
||||
PID hash table entries: 1024 (order: 10, 32768 bytes)
|
||||
|
||||
Using epoch = 1900
|
||||
|
||||
Console: colour dummy device 80x25
|
||||
|
||||
Dentry cache hash table entries: 32768 (order: 5, 262144 bytes)
|
||||
|
||||
Inode-cache hash table entries: 16384 (order: 4, 131072 bytes)
|
||||
|
||||
Memory: 118784k/131072k available (3314k kernel code, 8952k reserved, 983k data, 224k init)
|
||||
|
||||
Mount-cache hash table entries: 512
|
||||
|
||||
SMP starting up secondaries.
|
||||
|
||||
Slave CPU 1 console command START
|
||||
SlaveCmd: restart FFFFFC0000310020 FFFFFC0000310020 vptb FFFFFFFE00000000 my_rpb FFFFFC0000018400 my_rpb_phys 18400
|
||||
|
||||
Brought up 2 CPUs
|
||||
|
||||
SMP: Total of 2 processors activated (8000.15 BogoMIPS).
|
||||
|
||||
NET: Registered protocol family 16
|
||||
|
||||
EISA bus registered
|
||||
|
||||
pci: enabling save/restore of SRM state
|
||||
|
||||
SCSI subsystem initialized
|
||||
|
||||
srm_env: version 0.0.5 loaded successfully
|
||||
|
||||
Installing knfsd (copyright (C) 1996 okir@monad.swb.de).
|
||||
|
||||
Initializing Cryptographic API
|
||||
|
||||
rtc: Standard PC (1900) epoch (1900) detected
|
||||
|
||||
Real Time Clock Driver v1.12
|
||||
|
||||
Serial: 8250/16550 driver $Revision: 1.90 $ 1 ports, IRQ sharing disabled
|
||||
|
||||
ttyS0 at I/O 0x3f8 (irq = 4) is a 8250
|
||||
|
||||
io scheduler noop registered
|
||||
|
||||
io scheduler anticipatory registered
|
||||
@ -0,0 +1,816 @@
|
||||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
full_system=true
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
||||
[system]
|
||||
type=LinuxAlphaSystem
|
||||
children=bridge cpu disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami
|
||||
boot_cpu_frequency=500
|
||||
boot_osflags=root=/dev/hda1 console=ttyS0
|
||||
console=/dist/m5/system/binaries/console
|
||||
init_param=0
|
||||
kernel=/dist/m5/system/binaries/vmlinux
|
||||
load_addr_mask=1099511627775
|
||||
mem_mode=atomic
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
pal=/dist/m5/system/binaries/ts_osfpal
|
||||
readfile=tests/halt.sh
|
||||
symbolfile=
|
||||
system_rev=1024
|
||||
system_type=34
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.membus.slave[0]
|
||||
|
||||
[system.bridge]
|
||||
type=Bridge
|
||||
delay=50000
|
||||
nack_delay=4000
|
||||
ranges=8796093022208:18446744073709551615
|
||||
req_size=16
|
||||
resp_size=16
|
||||
write_ack=false
|
||||
master=system.iobus.slave[0]
|
||||
slave=system.membus.master[0]
|
||||
|
||||
[system.cpu]
|
||||
type=AtomicSimpleCPU
|
||||
children=dcache dtb icache interrupts itb tracer
|
||||
checker=Null
|
||||
clock=500
|
||||
cpu_id=0
|
||||
defer_registration=false
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
fastmem=false
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
interrupts=system.cpu.interrupts
|
||||
itb=system.cpu.itb
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
phase=0
|
||||
profile=0
|
||||
progress_interval=0
|
||||
simulate_data_stalls=false
|
||||
simulate_inst_stalls=false
|
||||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
width=1
|
||||
workload=
|
||||
dcache_port=system.cpu.dcache.cpu_side
|
||||
icache_port=system.cpu.icache.cpu_side
|
||||
|
||||
[system.cpu.dcache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=4
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=32768
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=8
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.dcache_port
|
||||
mem_side=system.toL2Bus.slave[1]
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=AlphaTLB
|
||||
size=64
|
||||
|
||||
[system.cpu.icache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=1
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=32768
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=8
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.icache_port
|
||||
mem_side=system.toL2Bus.slave[0]
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=AlphaInterrupts
|
||||
|
||||
[system.cpu.itb]
|
||||
type=AlphaTLB
|
||||
size=48
|
||||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
|
||||
[system.disk0]
|
||||
type=IdeDisk
|
||||
children=image
|
||||
delay=1000000
|
||||
driveID=master
|
||||
image=system.disk0.image
|
||||
|
||||
[system.disk0.image]
|
||||
type=CowDiskImage
|
||||
children=child
|
||||
child=system.disk0.image.child
|
||||
image_file=
|
||||
read_only=false
|
||||
table_size=65536
|
||||
|
||||
[system.disk0.image.child]
|
||||
type=RawDiskImage
|
||||
image_file=/dist/m5/system/disks/linux-latest.img
|
||||
read_only=true
|
||||
|
||||
[system.disk2]
|
||||
type=IdeDisk
|
||||
children=image
|
||||
delay=1000000
|
||||
driveID=master
|
||||
image=system.disk2.image
|
||||
|
||||
[system.disk2.image]
|
||||
type=CowDiskImage
|
||||
children=child
|
||||
child=system.disk2.image.child
|
||||
image_file=
|
||||
read_only=false
|
||||
table_size=65536
|
||||
|
||||
[system.disk2.image.child]
|
||||
type=RawDiskImage
|
||||
image_file=/dist/m5/system/disks/linux-bigswap2.img
|
||||
read_only=true
|
||||
|
||||
[system.intrctrl]
|
||||
type=IntrControl
|
||||
sys=system
|
||||
|
||||
[system.iobus]
|
||||
type=NoncoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
use_default_range=true
|
||||
width=64
|
||||
default=system.tsunami.pciconfig.pio
|
||||
master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ethernet.pio system.tsunami.ethernet.config system.iocache.cpu_side
|
||||
slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma
|
||||
|
||||
[system.iocache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:8589934591
|
||||
assoc=8
|
||||
block_size=64
|
||||
forward_snoops=false
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=50000
|
||||
max_miss_count=0
|
||||
mshrs=20
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=1024
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=12
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.iobus.master[29]
|
||||
mem_side=system.membus.slave[1]
|
||||
|
||||
[system.l2c]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=8
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=false
|
||||
latency=10000
|
||||
max_miss_count=0
|
||||
mshrs=92
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=4194304
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=16
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.toL2Bus.master[0]
|
||||
mem_side=system.membus.slave[2]
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
children=badaddr_responder
|
||||
block_size=64
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
default=system.membus.badaddr_responder.pio
|
||||
master=system.bridge.slave system.physmem.port[0]
|
||||
slave=system.system_port system.iocache.mem_side system.l2c.mem_side
|
||||
|
||||
[system.membus.badaddr_responder]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=0
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=true
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.membus.default
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.membus.master[1]
|
||||
|
||||
[system.simple_disk]
|
||||
type=SimpleDisk
|
||||
children=disk
|
||||
disk=system.simple_disk.disk
|
||||
system=system
|
||||
|
||||
[system.simple_disk.disk]
|
||||
type=RawDiskImage
|
||||
image_file=/dist/m5/system/disks/linux-latest.img
|
||||
read_only=true
|
||||
|
||||
[system.terminal]
|
||||
type=Terminal
|
||||
intr_control=system.intrctrl
|
||||
number=0
|
||||
output=true
|
||||
port=3456
|
||||
|
||||
[system.toL2Bus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
master=system.l2c.cpu_side
|
||||
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
|
||||
|
||||
[system.tsunami]
|
||||
type=Tsunami
|
||||
children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart
|
||||
intrctrl=system.intrctrl
|
||||
system=system
|
||||
|
||||
[system.tsunami.backdoor]
|
||||
type=AlphaBackdoor
|
||||
cpu=system.cpu
|
||||
disk=system.simple_disk
|
||||
pio_addr=8804682956800
|
||||
pio_latency=1000
|
||||
platform=system.tsunami
|
||||
system=system
|
||||
terminal=system.terminal
|
||||
pio=system.iobus.master[24]
|
||||
|
||||
[system.tsunami.cchip]
|
||||
type=TsunamiCChip
|
||||
pio_addr=8803072344064
|
||||
pio_latency=1000
|
||||
system=system
|
||||
tsunami=system.tsunami
|
||||
pio=system.iobus.master[0]
|
||||
|
||||
[system.tsunami.ethernet]
|
||||
type=NSGigE
|
||||
BAR0=1
|
||||
BAR0LegacyIO=false
|
||||
BAR0Size=256
|
||||
BAR1=0
|
||||
BAR1LegacyIO=false
|
||||
BAR1Size=4096
|
||||
BAR2=0
|
||||
BAR2LegacyIO=false
|
||||
BAR2Size=0
|
||||
BAR3=0
|
||||
BAR3LegacyIO=false
|
||||
BAR3Size=0
|
||||
BAR4=0
|
||||
BAR4LegacyIO=false
|
||||
BAR4Size=0
|
||||
BAR5=0
|
||||
BAR5LegacyIO=false
|
||||
BAR5Size=0
|
||||
BIST=0
|
||||
CacheLineSize=0
|
||||
CardbusCIS=0
|
||||
ClassCode=2
|
||||
Command=0
|
||||
DeviceID=34
|
||||
ExpansionROM=0
|
||||
HeaderType=0
|
||||
InterruptLine=30
|
||||
InterruptPin=1
|
||||
LatencyTimer=0
|
||||
MaximumLatency=52
|
||||
MinimumGrant=176
|
||||
ProgIF=0
|
||||
Revision=0
|
||||
Status=656
|
||||
SubClassCode=0
|
||||
SubsystemID=0
|
||||
SubsystemVendorID=0
|
||||
VendorID=4107
|
||||
clock=0
|
||||
config_latency=20000
|
||||
dma_data_free=false
|
||||
dma_desc_free=false
|
||||
dma_no_allocate=true
|
||||
dma_read_delay=0
|
||||
dma_read_factor=0
|
||||
dma_write_delay=0
|
||||
dma_write_factor=0
|
||||
hardware_address=00:90:00:00:00:01
|
||||
intr_delay=10000000
|
||||
max_backoff_delay=10000000
|
||||
min_backoff_delay=4000
|
||||
pci_bus=0
|
||||
pci_dev=1
|
||||
pci_func=0
|
||||
pio_latency=1000
|
||||
platform=system.tsunami
|
||||
rss=false
|
||||
rx_delay=1000000
|
||||
rx_fifo_size=524288
|
||||
rx_filter=true
|
||||
rx_thread=false
|
||||
system=system
|
||||
tx_delay=1000000
|
||||
tx_fifo_size=524288
|
||||
tx_thread=false
|
||||
config=system.iobus.master[28]
|
||||
dma=system.iobus.slave[2]
|
||||
pio=system.iobus.master[27]
|
||||
|
||||
[system.tsunami.fake_OROM]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8796093677568
|
||||
pio_latency=1000
|
||||
pio_size=393216
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[8]
|
||||
|
||||
[system.tsunami.fake_ata0]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615848432
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[19]
|
||||
|
||||
[system.tsunami.fake_ata1]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615848304
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[20]
|
||||
|
||||
[system.tsunami.fake_pnp_addr]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615848569
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[9]
|
||||
|
||||
[system.tsunami.fake_pnp_read0]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615848451
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[11]
|
||||
|
||||
[system.tsunami.fake_pnp_read1]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615848515
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[12]
|
||||
|
||||
[system.tsunami.fake_pnp_read2]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615848579
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[13]
|
||||
|
||||
[system.tsunami.fake_pnp_read3]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615848643
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[14]
|
||||
|
||||
[system.tsunami.fake_pnp_read4]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615848707
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[15]
|
||||
|
||||
[system.tsunami.fake_pnp_read5]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615848771
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[16]
|
||||
|
||||
[system.tsunami.fake_pnp_read6]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615848835
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[17]
|
||||
|
||||
[system.tsunami.fake_pnp_read7]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615848899
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[18]
|
||||
|
||||
[system.tsunami.fake_pnp_write]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615850617
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[10]
|
||||
|
||||
[system.tsunami.fake_ppc]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615848891
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[7]
|
||||
|
||||
[system.tsunami.fake_sm_chip]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615848816
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[2]
|
||||
|
||||
[system.tsunami.fake_uart1]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615848696
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[3]
|
||||
|
||||
[system.tsunami.fake_uart2]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615848936
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[4]
|
||||
|
||||
[system.tsunami.fake_uart3]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615848680
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[5]
|
||||
|
||||
[system.tsunami.fake_uart4]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615848944
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[6]
|
||||
|
||||
[system.tsunami.fb]
|
||||
type=BadDevice
|
||||
devicename=FrameBuffer
|
||||
pio_addr=8804615848912
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.iobus.master[21]
|
||||
|
||||
[system.tsunami.ide]
|
||||
type=IdeController
|
||||
BAR0=1
|
||||
BAR0LegacyIO=false
|
||||
BAR0Size=8
|
||||
BAR1=1
|
||||
BAR1LegacyIO=false
|
||||
BAR1Size=4
|
||||
BAR2=1
|
||||
BAR2LegacyIO=false
|
||||
BAR2Size=8
|
||||
BAR3=1
|
||||
BAR3LegacyIO=false
|
||||
BAR3Size=4
|
||||
BAR4=1
|
||||
BAR4LegacyIO=false
|
||||
BAR4Size=16
|
||||
BAR5=1
|
||||
BAR5LegacyIO=false
|
||||
BAR5Size=0
|
||||
BIST=0
|
||||
CacheLineSize=0
|
||||
CardbusCIS=0
|
||||
ClassCode=1
|
||||
Command=0
|
||||
DeviceID=28945
|
||||
ExpansionROM=0
|
||||
HeaderType=0
|
||||
InterruptLine=31
|
||||
InterruptPin=1
|
||||
LatencyTimer=0
|
||||
MaximumLatency=0
|
||||
MinimumGrant=0
|
||||
ProgIF=133
|
||||
Revision=0
|
||||
Status=640
|
||||
SubClassCode=1
|
||||
SubsystemID=0
|
||||
SubsystemVendorID=0
|
||||
VendorID=32902
|
||||
config_latency=20000
|
||||
ctrl_offset=0
|
||||
disks=system.disk0 system.disk2
|
||||
io_shift=0
|
||||
max_backoff_delay=10000000
|
||||
min_backoff_delay=4000
|
||||
pci_bus=0
|
||||
pci_dev=0
|
||||
pci_func=0
|
||||
pio_latency=1000
|
||||
platform=system.tsunami
|
||||
system=system
|
||||
config=system.iobus.master[26]
|
||||
dma=system.iobus.slave[1]
|
||||
pio=system.iobus.master[25]
|
||||
|
||||
[system.tsunami.io]
|
||||
type=TsunamiIO
|
||||
frequency=976562500
|
||||
pio_addr=8804615847936
|
||||
pio_latency=1000
|
||||
system=system
|
||||
time=Thu Jan 1 00:00:00 2009
|
||||
tsunami=system.tsunami
|
||||
year_is_bcd=false
|
||||
pio=system.iobus.master[22]
|
||||
|
||||
[system.tsunami.pchip]
|
||||
type=TsunamiPChip
|
||||
pio_addr=8802535473152
|
||||
pio_latency=1000
|
||||
system=system
|
||||
tsunami=system.tsunami
|
||||
pio=system.iobus.master[1]
|
||||
|
||||
[system.tsunami.pciconfig]
|
||||
type=PciConfigAll
|
||||
bus=0
|
||||
pio_latency=1
|
||||
platform=system.tsunami
|
||||
size=16777216
|
||||
system=system
|
||||
pio=system.iobus.default
|
||||
|
||||
[system.tsunami.uart]
|
||||
type=Uart8250
|
||||
pio_addr=8804615848952
|
||||
pio_latency=1000
|
||||
platform=system.tsunami
|
||||
system=system
|
||||
terminal=system.terminal
|
||||
pio=system.iobus.master[23]
|
||||
|
||||
@ -0,0 +1,5 @@
|
||||
warn: Sockets disabled, not accepting terminal connections
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: Prefetch instructions in Alpha do not do anything
|
||||
warn: Prefetch instructions in Alpha do not do anything
|
||||
hack: be nice to actually delete the event here
|
||||
@ -0,0 +1,12 @@
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jun 4 2012 11:50:11
|
||||
gem5 started Jun 4 2012 14:07:23
|
||||
gem5 executing on zizzer
|
||||
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic -re tests/run.py build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: kernel located at: /dist/m5/system/binaries/vmlinux
|
||||
0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 1829332258000 because m5_exit instruction encountered
|
||||
@ -0,0 +1,456 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 1.829332 # Number of seconds simulated
|
||||
sim_ticks 1829332258000 # Number of ticks simulated
|
||||
final_tick 1829332258000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 2878195 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2878193 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 87696777763 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 296144 # Number of bytes of host memory used
|
||||
host_seconds 20.86 # Real time elapsed on the host
|
||||
sim_insts 60038305 # Number of instructions simulated
|
||||
sim_ops 60038305 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 955904 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 68042304 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::tsunami.ide 2652608 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 71650816 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 955904 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 955904 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 10156864 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 10156864 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 14936 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 1063161 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::tsunami.ide 41447 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 1119544 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 158701 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 158701 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 522543 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 37195159 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::tsunami.ide 1450042 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 39167743 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 522543 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 522543 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 5552225 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 5552225 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 5552225 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 522543 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 37195159 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::tsunami.ide 1450042 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 44719968 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.l2c.replacements 1045877 # number of replacements
|
||||
system.l2c.tagsinuse 33807.015903 # Cycle average of tags in use
|
||||
system.l2c.total_refs 2291835 # Total number of references to valid blocks.
|
||||
system.l2c.sampled_refs 1077848 # Sample count of references to valid blocks.
|
||||
system.l2c.avg_refs 2.126306 # Average number of references to valid blocks.
|
||||
system.l2c.warmup_cycle 765422500 # Cycle when the warmup percentage was hit.
|
||||
system.l2c.occ_blocks::writebacks 23613.410409 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu.inst 3680.391656 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu.data 6513.213838 # Average occupied blocks per requestor
|
||||
system.l2c.occ_percent::writebacks 0.360312 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu.inst 0.056158 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu.data 0.099384 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::total 0.515854 # Average percentage of cache occupancy
|
||||
system.l2c.ReadReq_hits::cpu.inst 905267 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu.data 794128 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::total 1699395 # number of ReadReq hits
|
||||
system.l2c.Writeback_hits::writebacks 825291 # number of Writeback hits
|
||||
system.l2c.Writeback_hits::total 825291 # number of Writeback hits
|
||||
system.l2c.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits
|
||||
system.l2c.UpgradeReq_hits::total 1 # number of UpgradeReq hits
|
||||
system.l2c.ReadExReq_hits::cpu.data 185383 # number of ReadExReq hits
|
||||
system.l2c.ReadExReq_hits::total 185383 # number of ReadExReq hits
|
||||
system.l2c.demand_hits::cpu.inst 905267 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu.data 979511 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::total 1884778 # number of demand (read+write) hits
|
||||
system.l2c.overall_hits::cpu.inst 905267 # number of overall hits
|
||||
system.l2c.overall_hits::cpu.data 979511 # number of overall hits
|
||||
system.l2c.overall_hits::total 1884778 # number of overall hits
|
||||
system.l2c.ReadReq_misses::cpu.inst 14936 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu.data 944693 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::total 959629 # number of ReadReq misses
|
||||
system.l2c.UpgradeReq_misses::cpu.data 12 # number of UpgradeReq misses
|
||||
system.l2c.UpgradeReq_misses::total 12 # number of UpgradeReq misses
|
||||
system.l2c.ReadExReq_misses::cpu.data 118859 # number of ReadExReq misses
|
||||
system.l2c.ReadExReq_misses::total 118859 # number of ReadExReq misses
|
||||
system.l2c.demand_misses::cpu.inst 14936 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu.data 1063552 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::total 1078488 # number of demand (read+write) misses
|
||||
system.l2c.overall_misses::cpu.inst 14936 # number of overall misses
|
||||
system.l2c.overall_misses::cpu.data 1063552 # number of overall misses
|
||||
system.l2c.overall_misses::total 1078488 # number of overall misses
|
||||
system.l2c.ReadReq_accesses::cpu.inst 920203 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::cpu.data 1738821 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::total 2659024 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.Writeback_accesses::writebacks 825291 # number of Writeback accesses(hits+misses)
|
||||
system.l2c.Writeback_accesses::total 825291 # number of Writeback accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_accesses::cpu.data 13 # number of UpgradeReq accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_accesses::total 13 # number of UpgradeReq accesses(hits+misses)
|
||||
system.l2c.ReadExReq_accesses::cpu.data 304242 # number of ReadExReq accesses(hits+misses)
|
||||
system.l2c.ReadExReq_accesses::total 304242 # number of ReadExReq accesses(hits+misses)
|
||||
system.l2c.demand_accesses::cpu.inst 920203 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu.data 2043063 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::total 2963266 # number of demand (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu.inst 920203 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu.data 2043063 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::total 2963266 # number of overall (read+write) accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu.inst 0.016231 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu.data 0.543295 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::total 0.360895 # miss rate for ReadReq accesses
|
||||
system.l2c.UpgradeReq_miss_rate::cpu.data 0.923077 # miss rate for UpgradeReq accesses
|
||||
system.l2c.UpgradeReq_miss_rate::total 0.923077 # miss rate for UpgradeReq accesses
|
||||
system.l2c.ReadExReq_miss_rate::cpu.data 0.390673 # miss rate for ReadExReq accesses
|
||||
system.l2c.ReadExReq_miss_rate::total 0.390673 # miss rate for ReadExReq accesses
|
||||
system.l2c.demand_miss_rate::cpu.inst 0.016231 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu.data 0.520567 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::total 0.363952 # miss rate for demand accesses
|
||||
system.l2c.overall_miss_rate::cpu.inst 0.016231 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu.data 0.520567 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::total 0.363952 # miss rate for overall accesses
|
||||
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.l2c.fast_writes 0 # number of fast writes performed
|
||||
system.l2c.cache_copies 0 # number of cache copies performed
|
||||
system.l2c.writebacks::writebacks 117189 # number of writebacks
|
||||
system.l2c.writebacks::total 117189 # number of writebacks
|
||||
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.iocache.replacements 41686 # number of replacements
|
||||
system.iocache.tagsinuse 1.225570 # Cycle average of tags in use
|
||||
system.iocache.total_refs 0 # Total number of references to valid blocks.
|
||||
system.iocache.sampled_refs 41702 # Sample count of references to valid blocks.
|
||||
system.iocache.avg_refs 0 # Average number of references to valid blocks.
|
||||
system.iocache.warmup_cycle 1685780659017 # Cycle when the warmup percentage was hit.
|
||||
system.iocache.occ_blocks::tsunami.ide 1.225570 # Average occupied blocks per requestor
|
||||
system.iocache.occ_percent::tsunami.ide 0.076598 # Average percentage of cache occupancy
|
||||
system.iocache.occ_percent::total 0.076598 # Average percentage of cache occupancy
|
||||
system.iocache.ReadReq_misses::tsunami.ide 174 # number of ReadReq misses
|
||||
system.iocache.ReadReq_misses::total 174 # number of ReadReq misses
|
||||
system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses
|
||||
system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses
|
||||
system.iocache.demand_misses::tsunami.ide 41726 # number of demand (read+write) misses
|
||||
system.iocache.demand_misses::total 41726 # number of demand (read+write) misses
|
||||
system.iocache.overall_misses::tsunami.ide 41726 # number of overall misses
|
||||
system.iocache.overall_misses::total 41726 # number of overall misses
|
||||
system.iocache.ReadReq_accesses::tsunami.ide 174 # number of ReadReq accesses(hits+misses)
|
||||
system.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses)
|
||||
system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses)
|
||||
system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses)
|
||||
system.iocache.demand_accesses::tsunami.ide 41726 # number of demand (read+write) accesses
|
||||
system.iocache.demand_accesses::total 41726 # number of demand (read+write) accesses
|
||||
system.iocache.overall_accesses::tsunami.ide 41726 # number of overall (read+write) accesses
|
||||
system.iocache.overall_accesses::total 41726 # number of overall (read+write) accesses
|
||||
system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
|
||||
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
|
||||
system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses
|
||||
system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
|
||||
system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses
|
||||
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
|
||||
system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
|
||||
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
|
||||
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.iocache.fast_writes 0 # number of fast writes performed
|
||||
system.iocache.cache_copies 0 # number of cache copies performed
|
||||
system.iocache.writebacks::writebacks 41512 # number of writebacks
|
||||
system.iocache.writebacks::total 41512 # number of writebacks
|
||||
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
||||
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
|
||||
system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
|
||||
system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
|
||||
system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
|
||||
system.disk0.dma_write_txs 395 # Number of DMA write transactions.
|
||||
system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
||||
system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
|
||||
system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
|
||||
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
|
||||
system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
|
||||
system.disk2.dma_write_txs 1 # Number of DMA write transactions.
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
||||
system.cpu.dtb.read_hits 9710427 # DTB read hits
|
||||
system.cpu.dtb.read_misses 10329 # DTB read misses
|
||||
system.cpu.dtb.read_acv 210 # DTB read access violations
|
||||
system.cpu.dtb.read_accesses 728856 # DTB read accesses
|
||||
system.cpu.dtb.write_hits 6352498 # DTB write hits
|
||||
system.cpu.dtb.write_misses 1142 # DTB write misses
|
||||
system.cpu.dtb.write_acv 157 # DTB write access violations
|
||||
system.cpu.dtb.write_accesses 291931 # DTB write accesses
|
||||
system.cpu.dtb.data_hits 16062925 # DTB hits
|
||||
system.cpu.dtb.data_misses 11471 # DTB misses
|
||||
system.cpu.dtb.data_acv 367 # DTB access violations
|
||||
system.cpu.dtb.data_accesses 1020787 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 4974648 # ITB hits
|
||||
system.cpu.itb.fetch_misses 5006 # ITB misses
|
||||
system.cpu.itb.fetch_acv 184 # ITB acv
|
||||
system.cpu.itb.fetch_accesses 4979654 # ITB accesses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.itb.write_hits 0 # DTB write hits
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.itb.write_acv 0 # DTB write access violations
|
||||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.itb.data_hits 0 # DTB hits
|
||||
system.cpu.itb.data_misses 0 # DTB misses
|
||||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.numCycles 3658664408 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 60038305 # Number of instructions committed
|
||||
system.cpu.committedOps 60038305 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 55913521 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 324460 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 1484182 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 7110746 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 55913521 # number of integer instructions
|
||||
system.cpu.num_fp_insts 324460 # number of float instructions
|
||||
system.cpu.num_int_register_reads 76953934 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 41740225 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 163642 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 166520 # number of times the floating registers were written
|
||||
system.cpu.num_mem_refs 16115709 # number of memory refs
|
||||
system.cpu.num_load_insts 9747513 # Number of load instructions
|
||||
system.cpu.num_store_insts 6368196 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 3598608979.180807 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 60055428.819193 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 0.016415 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0.983585 # Percentage of idle cycles
|
||||
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
||||
system.cpu.kern.inst.quiesce 6357 # number of quiesce instructions executed
|
||||
system.cpu.kern.inst.hwrei 211319 # number of hwrei instructions executed
|
||||
system.cpu.kern.ipl_count::0 74830 40.99% 40.99% # number of times we switched to this ipl
|
||||
system.cpu.kern.ipl_count::21 243 0.13% 41.12% # number of times we switched to this ipl
|
||||
system.cpu.kern.ipl_count::22 1866 1.02% 42.14% # number of times we switched to this ipl
|
||||
system.cpu.kern.ipl_count::31 105623 57.86% 100.00% # number of times we switched to this ipl
|
||||
system.cpu.kern.ipl_count::total 182562 # number of times we switched to this ipl
|
||||
system.cpu.kern.ipl_good::0 73463 49.29% 49.29% # number of times we switched to this ipl from a different ipl
|
||||
system.cpu.kern.ipl_good::21 243 0.16% 49.46% # number of times we switched to this ipl from a different ipl
|
||||
system.cpu.kern.ipl_good::22 1866 1.25% 50.71% # number of times we switched to this ipl from a different ipl
|
||||
system.cpu.kern.ipl_good::31 73463 49.29% 100.00% # number of times we switched to this ipl from a different ipl
|
||||
system.cpu.kern.ipl_good::total 149035 # number of times we switched to this ipl from a different ipl
|
||||
system.cpu.kern.ipl_ticks::0 1811927407500 99.05% 99.05% # number of cycles we spent at this ipl
|
||||
system.cpu.kern.ipl_ticks::21 20110000 0.00% 99.05% # number of cycles we spent at this ipl
|
||||
system.cpu.kern.ipl_ticks::22 80238000 0.00% 99.05% # number of cycles we spent at this ipl
|
||||
system.cpu.kern.ipl_ticks::31 17304295000 0.95% 100.00% # number of cycles we spent at this ipl
|
||||
system.cpu.kern.ipl_ticks::total 1829332050500 # number of cycles we spent at this ipl
|
||||
system.cpu.kern.ipl_used::0 0.981732 # fraction of swpipl calls that actually changed the ipl
|
||||
system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
|
||||
system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
|
||||
system.cpu.kern.ipl_used::31 0.695521 # fraction of swpipl calls that actually changed the ipl
|
||||
system.cpu.kern.ipl_used::total 0.816353 # fraction of swpipl calls that actually changed the ipl
|
||||
system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed
|
||||
system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed
|
||||
system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed
|
||||
system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed
|
||||
system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed
|
||||
system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed
|
||||
system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed
|
||||
system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed
|
||||
system.cpu.kern.syscall::20 6 1.84% 35.89% # number of syscalls executed
|
||||
system.cpu.kern.syscall::23 4 1.23% 37.12% # number of syscalls executed
|
||||
system.cpu.kern.syscall::24 6 1.84% 38.96% # number of syscalls executed
|
||||
system.cpu.kern.syscall::33 11 3.37% 42.33% # number of syscalls executed
|
||||
system.cpu.kern.syscall::41 2 0.61% 42.94% # number of syscalls executed
|
||||
system.cpu.kern.syscall::45 54 16.56% 59.51% # number of syscalls executed
|
||||
system.cpu.kern.syscall::47 6 1.84% 61.35% # number of syscalls executed
|
||||
system.cpu.kern.syscall::48 10 3.07% 64.42% # number of syscalls executed
|
||||
system.cpu.kern.syscall::54 10 3.07% 67.48% # number of syscalls executed
|
||||
system.cpu.kern.syscall::58 1 0.31% 67.79% # number of syscalls executed
|
||||
system.cpu.kern.syscall::59 7 2.15% 69.94% # number of syscalls executed
|
||||
system.cpu.kern.syscall::71 54 16.56% 86.50% # number of syscalls executed
|
||||
system.cpu.kern.syscall::73 3 0.92% 87.42% # number of syscalls executed
|
||||
system.cpu.kern.syscall::74 16 4.91% 92.33% # number of syscalls executed
|
||||
system.cpu.kern.syscall::87 1 0.31% 92.64% # number of syscalls executed
|
||||
system.cpu.kern.syscall::90 3 0.92% 93.56% # number of syscalls executed
|
||||
system.cpu.kern.syscall::92 9 2.76% 96.32% # number of syscalls executed
|
||||
system.cpu.kern.syscall::97 2 0.61% 96.93% # number of syscalls executed
|
||||
system.cpu.kern.syscall::98 2 0.61% 97.55% # number of syscalls executed
|
||||
system.cpu.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed
|
||||
system.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed
|
||||
system.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed
|
||||
system.cpu.kern.syscall::total 326 # number of syscalls executed
|
||||
system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
|
||||
system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed
|
||||
system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed
|
||||
system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed
|
||||
system.cpu.kern.callpal::swpctx 4177 2.17% 2.18% # number of callpals executed
|
||||
system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed
|
||||
system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed
|
||||
system.cpu.kern.callpal::swpipl 175249 91.19% 93.40% # number of callpals executed
|
||||
system.cpu.kern.callpal::rdps 6771 3.52% 96.92% # number of callpals executed
|
||||
system.cpu.kern.callpal::wrkgp 1 0.00% 96.92% # number of callpals executed
|
||||
system.cpu.kern.callpal::wrusp 7 0.00% 96.92% # number of callpals executed
|
||||
system.cpu.kern.callpal::rdusp 9 0.00% 96.93% # number of callpals executed
|
||||
system.cpu.kern.callpal::whami 2 0.00% 96.93% # number of callpals executed
|
||||
system.cpu.kern.callpal::rti 5203 2.71% 99.64% # number of callpals executed
|
||||
system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed
|
||||
system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed
|
||||
system.cpu.kern.callpal::total 192180 # number of callpals executed
|
||||
system.cpu.kern.mode_switch::kernel 5949 # number of protection mode switches
|
||||
system.cpu.kern.mode_switch::user 1738 # number of protection mode switches
|
||||
system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches
|
||||
system.cpu.kern.mode_good::kernel 1909
|
||||
system.cpu.kern.mode_good::user 1738
|
||||
system.cpu.kern.mode_good::idle 171
|
||||
system.cpu.kern.mode_switch_good::kernel 0.320894 # fraction of useful protection mode switches
|
||||
system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
|
||||
system.cpu.kern.mode_switch_good::idle 0.081545 # fraction of useful protection mode switches
|
||||
system.cpu.kern.mode_switch_good::total 0.390229 # fraction of useful protection mode switches
|
||||
system.cpu.kern.mode_ticks::kernel 26834202500 1.47% 1.47% # number of ticks spent at the given mode
|
||||
system.cpu.kern.mode_ticks::user 1465074000 0.08% 1.55% # number of ticks spent at the given mode
|
||||
system.cpu.kern.mode_ticks::idle 1801032773000 98.45% 100.00% # number of ticks spent at the given mode
|
||||
system.cpu.kern.swap_context 4178 # number of times the context was actually changed
|
||||
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
|
||||
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
|
||||
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
|
||||
system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
|
||||
system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
|
||||
system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
|
||||
system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
|
||||
system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
|
||||
system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
|
||||
system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
|
||||
system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
|
||||
system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
|
||||
system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
|
||||
system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
|
||||
system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
|
||||
system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
|
||||
system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
|
||||
system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
|
||||
system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
|
||||
system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
|
||||
system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
|
||||
system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
|
||||
system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
|
||||
system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
|
||||
system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
|
||||
system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
|
||||
system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
|
||||
system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
|
||||
system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
|
||||
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
|
||||
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
|
||||
system.cpu.icache.replacements 919594 # number of replacements
|
||||
system.cpu.icache.tagsinuse 511.215243 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 59129922 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 920106 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 64.264250 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 9686972500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 511.215243 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.998467 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.998467 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 59129922 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 59129922 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 59129922 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 59129922 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 59129922 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 59129922 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 920221 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 920221 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 920221 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 920221 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 920221 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 920221 # number of overall misses
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 60050143 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 60050143 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 60050143 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 60050143 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 60050143 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 60050143 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015324 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.015324 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.015324 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.015324 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.015324 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.015324 # miss rate for overall accesses
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks::writebacks 108 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 108 # number of writebacks
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 2042700 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 511.997802 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 14038433 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 2043212 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 6.870767 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 511.997802 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.999996 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 7807782 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 7807782 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 5848212 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 5848212 # number of WriteReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::cpu.data 183141 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::total 183141 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::cpu.data 199282 # number of StoreCondReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::total 199282 # number of StoreCondReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 13655994 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 13655994 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 13655994 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 13655994 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 1721705 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 1721705 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 304362 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 304362 # number of WriteReq misses
|
||||
system.cpu.dcache.LoadLockedReq_misses::cpu.data 17162 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.LoadLockedReq_misses::total 17162 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 2026067 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 2026067 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 2026067 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 2026067 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 9529487 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 9529487 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 6152574 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 6152574 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200303 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::total 200303 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::cpu.data 199282 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::total 199282 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 15682061 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 15682061 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 15682061 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 15682061 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.180671 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.180671 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049469 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.049469 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085680 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.085680 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.129196 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.129196 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.129196 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.129196 # miss rate for overall accesses
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 825183 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 825183 # number of writebacks
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
@ -0,0 +1,107 @@
|
||||
M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
|
||||
|
||||
Got Configuration 623
|
||||
|
||||
memsize 8000000 pages 4000
|
||||
|
||||
First free page after ROM 0xFFFFFC0000018000
|
||||
|
||||
HWRPB 0xFFFFFC0000018000 l1pt 0xFFFFFC0000040000 l2pt 0xFFFFFC0000042000 l3pt_rpb 0xFFFFFC0000044000 l3pt_kernel 0xFFFFFC0000048000 l2reserv 0xFFFFFC0000046000
|
||||
|
||||
kstart = 0xFFFFFC0000310000, kend = 0xFFFFFC0000855898, kentry = 0xFFFFFC0000310000, numCPUs = 0x1
|
||||
|
||||
CPU Clock at 2000 MHz IntrClockFrequency=1024
|
||||
|
||||
Booting with 1 processor(s)
|
||||
|
||||
KSP: 0x20043FE8 PTBR 0x20
|
||||
|
||||
Console Callback at 0x0, fixup at 0x0, crb offset: 0x510
|
||||
|
||||
Memory cluster 0 [0 - 392]
|
||||
|
||||
Memory cluster 1 [392 - 15992]
|
||||
|
||||
Initalizing mdt_bitmap addr 0xFFFFFC0000038000 mem_pages 4000
|
||||
|
||||
ConsoleDispatch at virt 10000658 phys 18658 val FFFFFC00000100A8
|
||||
|
||||
unix_boot_mem ends at FFFFFC0000076000
|
||||
|
||||
k_argc = 0
|
||||
|
||||
jumping to kernel at 0xFFFFFC0000310000, (PCBB 0xFFFFFC0000018180 pfn 1067)
|
||||
|
||||
CallbackFixup 0 18000, t7=FFFFFC000070C000
|
||||
|
||||
Linux version 2.6.13 (hsul@zed.eecs.umich.edu) (gcc version 3.4.3) #1 SMP Sun Oct 8 19:52:07 EDT 2006
|
||||
|
||||
Booting GENERIC on Tsunami variation DP264 using machine vector DP264 from SRM
|
||||
|
||||
Major Options: SMP LEGACY_START VERBOSE_MCHECK
|
||||
|
||||
Command line: root=/dev/hda1 console=ttyS0
|
||||
|
||||
memcluster 0, usage 1, start 0, end 392
|
||||
|
||||
memcluster 1, usage 0, start 392, end 16384
|
||||
|
||||
freeing pages 1069:16384
|
||||
|
||||
reserving pages 1069:1070
|
||||
|
||||
SMP: 1 CPUs probed -- cpu_present_mask = 1
|
||||
|
||||
Built 1 zonelists
|
||||
|
||||
Kernel command line: root=/dev/hda1 console=ttyS0
|
||||
|
||||
PID hash table entries: 1024 (order: 10, 32768 bytes)
|
||||
|
||||
Using epoch = 1900
|
||||
|
||||
Console: colour dummy device 80x25
|
||||
|
||||
Dentry cache hash table entries: 32768 (order: 5, 262144 bytes)
|
||||
|
||||
Inode-cache hash table entries: 16384 (order: 4, 131072 bytes)
|
||||
|
||||
Memory: 118784k/131072k available (3314k kernel code, 8952k reserved, 983k data, 224k init)
|
||||
|
||||
Mount-cache hash table entries: 512
|
||||
|
||||
SMP mode deactivated.
|
||||
|
||||
Brought up 1 CPUs
|
||||
|
||||
SMP: Total of 1 processors activated (4002.20 BogoMIPS).
|
||||
|
||||
NET: Registered protocol family 16
|
||||
|
||||
EISA bus registered
|
||||
|
||||
pci: enabling save/restore of SRM state
|
||||
|
||||
SCSI subsystem initialized
|
||||
|
||||
srm_env: version 0.0.5 loaded successfully
|
||||
|
||||
Installing knfsd (copyright (C) 1996 okir@monad.swb.de).
|
||||
|
||||
Initializing Cryptographic API
|
||||
|
||||
rtc: Standard PC (1900) epoch (1900) detected
|
||||
|
||||
Real Time Clock Driver v1.12
|
||||
|
||||
Serial: 8250/16550 driver $Revision: 1.90 $ 1 ports, IRQ sharing disabled
|
||||
|
||||
ttyS0 at I/O 0x3f8 (irq = 4) is a 8250
|
||||
|
||||
io scheduler noop registered
|
||||
|
||||
io scheduler anticipatory registered
|
||||
|
||||
io scheduler deadline registered
|
||||
|
||||
io scheduler cfq registered
|
||||
@ -0,0 +1,905 @@
|
||||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
full_system=true
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
||||
[system]
|
||||
type=LinuxAlphaSystem
|
||||
children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami
|
||||
boot_cpu_frequency=500
|
||||
boot_osflags=root=/dev/hda1 console=ttyS0
|
||||
console=/dist/m5/system/binaries/console
|
||||
init_param=0
|
||||
kernel=/dist/m5/system/binaries/vmlinux
|
||||
load_addr_mask=1099511627775
|
||||
mem_mode=timing
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
pal=/dist/m5/system/binaries/ts_osfpal
|
||||
readfile=tests/halt.sh
|
||||
symbolfile=
|
||||
system_rev=1024
|
||||
system_type=34
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.membus.slave[0]
|
||||
|
||||
[system.bridge]
|
||||
type=Bridge
|
||||
delay=50000
|
||||
nack_delay=4000
|
||||
ranges=8796093022208:18446744073709551615
|
||||
req_size=16
|
||||
resp_size=16
|
||||
write_ack=false
|
||||
master=system.iobus.slave[0]
|
||||
slave=system.membus.master[0]
|
||||
|
||||
[system.cpu0]
|
||||
type=TimingSimpleCPU
|
||||
children=dcache dtb icache interrupts itb tracer
|
||||
checker=Null
|
||||
clock=500
|
||||
cpu_id=0
|
||||
defer_registration=false
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu0.dtb
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
interrupts=system.cpu0.interrupts
|
||||
itb=system.cpu0.itb
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
phase=0
|
||||
profile=0
|
||||
progress_interval=0
|
||||
system=system
|
||||
tracer=system.cpu0.tracer
|
||||
workload=
|
||||
dcache_port=system.cpu0.dcache.cpu_side
|
||||
icache_port=system.cpu0.icache.cpu_side
|
||||
|
||||
[system.cpu0.dcache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=4
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=32768
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=8
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu0.dcache_port
|
||||
mem_side=system.toL2Bus.slave[1]
|
||||
|
||||
[system.cpu0.dtb]
|
||||
type=AlphaTLB
|
||||
size=64
|
||||
|
||||
[system.cpu0.icache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=1
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=32768
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=8
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu0.icache_port
|
||||
mem_side=system.toL2Bus.slave[0]
|
||||
|
||||
[system.cpu0.interrupts]
|
||||
type=AlphaInterrupts
|
||||
|
||||
[system.cpu0.itb]
|
||||
type=AlphaTLB
|
||||
size=48
|
||||
|
||||
[system.cpu0.tracer]
|
||||
type=ExeTracer
|
||||
|
||||
[system.cpu1]
|
||||
type=TimingSimpleCPU
|
||||
children=dcache dtb icache interrupts itb tracer
|
||||
checker=Null
|
||||
clock=500
|
||||
cpu_id=1
|
||||
defer_registration=false
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu1.dtb
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
interrupts=system.cpu1.interrupts
|
||||
itb=system.cpu1.itb
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
phase=0
|
||||
profile=0
|
||||
progress_interval=0
|
||||
system=system
|
||||
tracer=system.cpu1.tracer
|
||||
workload=
|
||||
dcache_port=system.cpu1.dcache.cpu_side
|
||||
icache_port=system.cpu1.icache.cpu_side
|
||||
|
||||
[system.cpu1.dcache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=4
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=32768
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=8
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu1.dcache_port
|
||||
mem_side=system.toL2Bus.slave[3]
|
||||
|
||||
[system.cpu1.dtb]
|
||||
type=AlphaTLB
|
||||
size=64
|
||||
|
||||
[system.cpu1.icache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=1
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=32768
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=8
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu1.icache_port
|
||||
mem_side=system.toL2Bus.slave[2]
|
||||
|
||||
[system.cpu1.interrupts]
|
||||
type=AlphaInterrupts
|
||||
|
||||
[system.cpu1.itb]
|
||||
type=AlphaTLB
|
||||
size=48
|
||||
|
||||
[system.cpu1.tracer]
|
||||
type=ExeTracer
|
||||
|
||||
[system.disk0]
|
||||
type=IdeDisk
|
||||
children=image
|
||||
delay=1000000
|
||||
driveID=master
|
||||
image=system.disk0.image
|
||||
|
||||
[system.disk0.image]
|
||||
type=CowDiskImage
|
||||
children=child
|
||||
child=system.disk0.image.child
|
||||
image_file=
|
||||
read_only=false
|
||||
table_size=65536
|
||||
|
||||
[system.disk0.image.child]
|
||||
type=RawDiskImage
|
||||
image_file=/dist/m5/system/disks/linux-latest.img
|
||||
read_only=true
|
||||
|
||||
[system.disk2]
|
||||
type=IdeDisk
|
||||
children=image
|
||||
delay=1000000
|
||||
driveID=master
|
||||
image=system.disk2.image
|
||||
|
||||
[system.disk2.image]
|
||||
type=CowDiskImage
|
||||
children=child
|
||||
child=system.disk2.image.child
|
||||
image_file=
|
||||
read_only=false
|
||||
table_size=65536
|
||||
|
||||
[system.disk2.image.child]
|
||||
type=RawDiskImage
|
||||
image_file=/dist/m5/system/disks/linux-bigswap2.img
|
||||
read_only=true
|
||||
|
||||
[system.intrctrl]
|
||||
type=IntrControl
|
||||
sys=system
|
||||
|
||||
[system.iobus]
|
||||
type=NoncoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
use_default_range=true
|
||||
width=64
|
||||
default=system.tsunami.pciconfig.pio
|
||||
master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ethernet.pio system.tsunami.ethernet.config system.iocache.cpu_side
|
||||
slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma
|
||||
|
||||
[system.iocache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:8589934591
|
||||
assoc=8
|
||||
block_size=64
|
||||
forward_snoops=false
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=50000
|
||||
max_miss_count=0
|
||||
mshrs=20
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=1024
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=12
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.iobus.master[29]
|
||||
mem_side=system.membus.slave[1]
|
||||
|
||||
[system.l2c]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=8
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=false
|
||||
latency=10000
|
||||
max_miss_count=0
|
||||
mshrs=92
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=4194304
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=16
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.toL2Bus.master[0]
|
||||
mem_side=system.membus.slave[2]
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
children=badaddr_responder
|
||||
block_size=64
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
default=system.membus.badaddr_responder.pio
|
||||
master=system.bridge.slave system.physmem.port[0]
|
||||
slave=system.system_port system.iocache.mem_side system.l2c.mem_side
|
||||
|
||||
[system.membus.badaddr_responder]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=0
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=true
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.membus.default
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.membus.master[1]
|
||||
|
||||
[system.simple_disk]
|
||||
type=SimpleDisk
|
||||
children=disk
|
||||
disk=system.simple_disk.disk
|
||||
system=system
|
||||
|
||||
[system.simple_disk.disk]
|
||||
type=RawDiskImage
|
||||
image_file=/dist/m5/system/disks/linux-latest.img
|
||||
read_only=true
|
||||
|
||||
[system.terminal]
|
||||
type=Terminal
|
||||
intr_control=system.intrctrl
|
||||
number=0
|
||||
output=true
|
||||
port=3456
|
||||
|
||||
[system.toL2Bus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
master=system.l2c.cpu_side
|
||||
slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side
|
||||
|
||||
[system.tsunami]
|
||||
type=Tsunami
|
||||
children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart
|
||||
intrctrl=system.intrctrl
|
||||
system=system
|
||||
|
||||
[system.tsunami.backdoor]
|
||||
type=AlphaBackdoor
|
||||
cpu=system.cpu0
|
||||
disk=system.simple_disk
|
||||
pio_addr=8804682956800
|
||||
pio_latency=1000
|
||||
platform=system.tsunami
|
||||
system=system
|
||||
terminal=system.terminal
|
||||
pio=system.iobus.master[24]
|
||||
|
||||
[system.tsunami.cchip]
|
||||
type=TsunamiCChip
|
||||
pio_addr=8803072344064
|
||||
pio_latency=1000
|
||||
system=system
|
||||
tsunami=system.tsunami
|
||||
pio=system.iobus.master[0]
|
||||
|
||||
[system.tsunami.ethernet]
|
||||
type=NSGigE
|
||||
BAR0=1
|
||||
BAR0LegacyIO=false
|
||||
BAR0Size=256
|
||||
BAR1=0
|
||||
BAR1LegacyIO=false
|
||||
BAR1Size=4096
|
||||
BAR2=0
|
||||
BAR2LegacyIO=false
|
||||
BAR2Size=0
|
||||
BAR3=0
|
||||
BAR3LegacyIO=false
|
||||
BAR3Size=0
|
||||
BAR4=0
|
||||
BAR4LegacyIO=false
|
||||
BAR4Size=0
|
||||
BAR5=0
|
||||
BAR5LegacyIO=false
|
||||
BAR5Size=0
|
||||
BIST=0
|
||||
CacheLineSize=0
|
||||
CardbusCIS=0
|
||||
ClassCode=2
|
||||
Command=0
|
||||
DeviceID=34
|
||||
ExpansionROM=0
|
||||
HeaderType=0
|
||||
InterruptLine=30
|
||||
InterruptPin=1
|
||||
LatencyTimer=0
|
||||
MaximumLatency=52
|
||||
MinimumGrant=176
|
||||
ProgIF=0
|
||||
Revision=0
|
||||
Status=656
|
||||
SubClassCode=0
|
||||
SubsystemID=0
|
||||
SubsystemVendorID=0
|
||||
VendorID=4107
|
||||
clock=0
|
||||
config_latency=20000
|
||||
dma_data_free=false
|
||||
dma_desc_free=false
|
||||
dma_no_allocate=true
|
||||
dma_read_delay=0
|
||||
dma_read_factor=0
|
||||
dma_write_delay=0
|
||||
dma_write_factor=0
|
||||
hardware_address=00:90:00:00:00:01
|
||||
intr_delay=10000000
|
||||
max_backoff_delay=10000000
|
||||
min_backoff_delay=4000
|
||||
pci_bus=0
|
||||
pci_dev=1
|
||||
pci_func=0
|
||||
pio_latency=1000
|
||||
platform=system.tsunami
|
||||
rss=false
|
||||
rx_delay=1000000
|
||||
rx_fifo_size=524288
|
||||
rx_filter=true
|
||||
rx_thread=false
|
||||
system=system
|
||||
tx_delay=1000000
|
||||
tx_fifo_size=524288
|
||||
tx_thread=false
|
||||
config=system.iobus.master[28]
|
||||
dma=system.iobus.slave[2]
|
||||
pio=system.iobus.master[27]
|
||||
|
||||
[system.tsunami.fake_OROM]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8796093677568
|
||||
pio_latency=1000
|
||||
pio_size=393216
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[8]
|
||||
|
||||
[system.tsunami.fake_ata0]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615848432
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[19]
|
||||
|
||||
[system.tsunami.fake_ata1]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615848304
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[20]
|
||||
|
||||
[system.tsunami.fake_pnp_addr]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615848569
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[9]
|
||||
|
||||
[system.tsunami.fake_pnp_read0]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615848451
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[11]
|
||||
|
||||
[system.tsunami.fake_pnp_read1]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615848515
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[12]
|
||||
|
||||
[system.tsunami.fake_pnp_read2]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615848579
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[13]
|
||||
|
||||
[system.tsunami.fake_pnp_read3]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615848643
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[14]
|
||||
|
||||
[system.tsunami.fake_pnp_read4]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615848707
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[15]
|
||||
|
||||
[system.tsunami.fake_pnp_read5]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615848771
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[16]
|
||||
|
||||
[system.tsunami.fake_pnp_read6]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615848835
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[17]
|
||||
|
||||
[system.tsunami.fake_pnp_read7]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615848899
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[18]
|
||||
|
||||
[system.tsunami.fake_pnp_write]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615850617
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[10]
|
||||
|
||||
[system.tsunami.fake_ppc]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615848891
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[7]
|
||||
|
||||
[system.tsunami.fake_sm_chip]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615848816
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[2]
|
||||
|
||||
[system.tsunami.fake_uart1]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615848696
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[3]
|
||||
|
||||
[system.tsunami.fake_uart2]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615848936
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[4]
|
||||
|
||||
[system.tsunami.fake_uart3]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615848680
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[5]
|
||||
|
||||
[system.tsunami.fake_uart4]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615848944
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[6]
|
||||
|
||||
[system.tsunami.fb]
|
||||
type=BadDevice
|
||||
devicename=FrameBuffer
|
||||
pio_addr=8804615848912
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.iobus.master[21]
|
||||
|
||||
[system.tsunami.ide]
|
||||
type=IdeController
|
||||
BAR0=1
|
||||
BAR0LegacyIO=false
|
||||
BAR0Size=8
|
||||
BAR1=1
|
||||
BAR1LegacyIO=false
|
||||
BAR1Size=4
|
||||
BAR2=1
|
||||
BAR2LegacyIO=false
|
||||
BAR2Size=8
|
||||
BAR3=1
|
||||
BAR3LegacyIO=false
|
||||
BAR3Size=4
|
||||
BAR4=1
|
||||
BAR4LegacyIO=false
|
||||
BAR4Size=16
|
||||
BAR5=1
|
||||
BAR5LegacyIO=false
|
||||
BAR5Size=0
|
||||
BIST=0
|
||||
CacheLineSize=0
|
||||
CardbusCIS=0
|
||||
ClassCode=1
|
||||
Command=0
|
||||
DeviceID=28945
|
||||
ExpansionROM=0
|
||||
HeaderType=0
|
||||
InterruptLine=31
|
||||
InterruptPin=1
|
||||
LatencyTimer=0
|
||||
MaximumLatency=0
|
||||
MinimumGrant=0
|
||||
ProgIF=133
|
||||
Revision=0
|
||||
Status=640
|
||||
SubClassCode=1
|
||||
SubsystemID=0
|
||||
SubsystemVendorID=0
|
||||
VendorID=32902
|
||||
config_latency=20000
|
||||
ctrl_offset=0
|
||||
disks=system.disk0 system.disk2
|
||||
io_shift=0
|
||||
max_backoff_delay=10000000
|
||||
min_backoff_delay=4000
|
||||
pci_bus=0
|
||||
pci_dev=0
|
||||
pci_func=0
|
||||
pio_latency=1000
|
||||
platform=system.tsunami
|
||||
system=system
|
||||
config=system.iobus.master[26]
|
||||
dma=system.iobus.slave[1]
|
||||
pio=system.iobus.master[25]
|
||||
|
||||
[system.tsunami.io]
|
||||
type=TsunamiIO
|
||||
frequency=976562500
|
||||
pio_addr=8804615847936
|
||||
pio_latency=1000
|
||||
system=system
|
||||
time=Thu Jan 1 00:00:00 2009
|
||||
tsunami=system.tsunami
|
||||
year_is_bcd=false
|
||||
pio=system.iobus.master[22]
|
||||
|
||||
[system.tsunami.pchip]
|
||||
type=TsunamiPChip
|
||||
pio_addr=8802535473152
|
||||
pio_latency=1000
|
||||
system=system
|
||||
tsunami=system.tsunami
|
||||
pio=system.iobus.master[1]
|
||||
|
||||
[system.tsunami.pciconfig]
|
||||
type=PciConfigAll
|
||||
bus=0
|
||||
pio_latency=1
|
||||
platform=system.tsunami
|
||||
size=16777216
|
||||
system=system
|
||||
pio=system.iobus.default
|
||||
|
||||
[system.tsunami.uart]
|
||||
type=Uart8250
|
||||
pio_addr=8804615848952
|
||||
pio_latency=1000
|
||||
platform=system.tsunami
|
||||
system=system
|
||||
terminal=system.terminal
|
||||
pio=system.iobus.master[23]
|
||||
|
||||
@ -0,0 +1,5 @@
|
||||
warn: Sockets disabled, not accepting terminal connections
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: Prefetch instructions in Alpha do not do anything
|
||||
warn: Prefetch instructions in Alpha do not do anything
|
||||
hack: be nice to actually delete the event here
|
||||
@ -0,0 +1,13 @@
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jun 4 2012 11:50:11
|
||||
gem5 started Jun 4 2012 13:42:45
|
||||
gem5 executing on zizzer
|
||||
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual -re tests/run.py build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: kernel located at: /dist/m5/system/binaries/vmlinux
|
||||
0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Launching CPU 1 @ 562628000
|
||||
Exiting @ tick 1958647095000 because m5_exit instruction encountered
|
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,113 @@
|
||||
M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
|
||||
|
||||
Got Configuration 623
|
||||
|
||||
memsize 8000000 pages 4000
|
||||
|
||||
First free page after ROM 0xFFFFFC0000018000
|
||||
|
||||
HWRPB 0xFFFFFC0000018000 l1pt 0xFFFFFC0000040000 l2pt 0xFFFFFC0000042000 l3pt_rpb 0xFFFFFC0000044000 l3pt_kernel 0xFFFFFC0000048000 l2reserv 0xFFFFFC0000046000
|
||||
|
||||
kstart = 0xFFFFFC0000310000, kend = 0xFFFFFC0000855898, kentry = 0xFFFFFC0000310000, numCPUs = 0x2
|
||||
|
||||
CPU Clock at 2000 MHz IntrClockFrequency=1024
|
||||
|
||||
Booting with 2 processor(s)
|
||||
|
||||
KSP: 0x20043FE8 PTBR 0x20
|
||||
|
||||
KSP: 0x20043FE8 PTBR 0x20
|
||||
|
||||
Console Callback at 0x0, fixup at 0x0, crb offset: 0x790
|
||||
|
||||
Memory cluster 0 [0 - 392]
|
||||
|
||||
Memory cluster 1 [392 - 15992]
|
||||
|
||||
Initalizing mdt_bitmap addr 0xFFFFFC0000038000 mem_pages 4000
|
||||
|
||||
ConsoleDispatch at virt 100008D8 phys 188D8 val FFFFFC00000100A8
|
||||
|
||||
Bootstraping CPU 1 with sp=0xFFFFFC0000076000
|
||||
|
||||
unix_boot_mem ends at FFFFFC0000078000
|
||||
|
||||
k_argc = 0
|
||||
|
||||
jumping to kernel at 0xFFFFFC0000310000, (PCBB 0xFFFFFC0000018180 pfn 1067)
|
||||
|
||||
Entering slaveloop for cpu 1 my_rpb=FFFFFC0000018400
|
||||
|
||||
CallbackFixup 0 18000, t7=FFFFFC000070C000
|
||||
|
||||
Linux version 2.6.13 (hsul@zed.eecs.umich.edu) (gcc version 3.4.3) #1 SMP Sun Oct 8 19:52:07 EDT 2006
|
||||
|
||||
Booting GENERIC on Tsunami variation DP264 using machine vector DP264 from SRM
|
||||
|
||||
Major Options: SMP LEGACY_START VERBOSE_MCHECK
|
||||
|
||||
Command line: root=/dev/hda1 console=ttyS0
|
||||
|
||||
memcluster 0, usage 1, start 0, end 392
|
||||
|
||||
memcluster 1, usage 0, start 392, end 16384
|
||||
|
||||
freeing pages 1069:16384
|
||||
|
||||
reserving pages 1069:1070
|
||||
|
||||
4096K Bcache detected; load hit latency 40 cycles, load miss latency 123 cycles
|
||||
|
||||
SMP: 2 CPUs probed -- cpu_present_mask = 3
|
||||
|
||||
Built 1 zonelists
|
||||
|
||||
Kernel command line: root=/dev/hda1 console=ttyS0
|
||||
|
||||
PID hash table entries: 1024 (order: 10, 32768 bytes)
|
||||
|
||||
Using epoch = 1900
|
||||
|
||||
Console: colour dummy device 80x25
|
||||
|
||||
Dentry cache hash table entries: 32768 (order: 5, 262144 bytes)
|
||||
|
||||
Inode-cache hash table entries: 16384 (order: 4, 131072 bytes)
|
||||
|
||||
Memory: 118784k/131072k available (3314k kernel code, 8952k reserved, 983k data, 224k init)
|
||||
|
||||
Mount-cache hash table entries: 512
|
||||
|
||||
SMP starting up secondaries.
|
||||
|
||||
Slave CPU 1 console command START
|
||||
SlaveCmd: restart FFFFFC0000310020 FFFFFC0000310020 vptb FFFFFFFE00000000 my_rpb FFFFFC0000018400 my_rpb_phys 18400
|
||||
|
||||
Brought up 2 CPUs
|
||||
|
||||
SMP: Total of 2 processors activated (8000.15 BogoMIPS).
|
||||
|
||||
NET: Registered protocol family 16
|
||||
|
||||
EISA bus registered
|
||||
|
||||
pci: enabling save/restore of SRM state
|
||||
|
||||
SCSI subsystem initialized
|
||||
|
||||
srm_env: version 0.0.5 loaded successfully
|
||||
|
||||
Installing knfsd (copyright (C) 1996 okir@monad.swb.de).
|
||||
|
||||
Initializing Cryptographic API
|
||||
|
||||
rtc: Standard PC (1900) epoch (1900) detected
|
||||
|
||||
Real Time Clock Driver v1.12
|
||||
|
||||
Serial: 8250/16550 driver $Revision: 1.90 $ 1 ports, IRQ sharing disabled
|
||||
|
||||
ttyS0 at I/O 0x3f8 (irq = 4) is a 8250
|
||||
|
||||
io scheduler noop registered
|
||||
|
||||
@ -0,0 +1,812 @@
|
||||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
full_system=true
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
||||
[system]
|
||||
type=LinuxAlphaSystem
|
||||
children=bridge cpu disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami
|
||||
boot_cpu_frequency=500
|
||||
boot_osflags=root=/dev/hda1 console=ttyS0
|
||||
console=/dist/m5/system/binaries/console
|
||||
init_param=0
|
||||
kernel=/dist/m5/system/binaries/vmlinux
|
||||
load_addr_mask=1099511627775
|
||||
mem_mode=timing
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
pal=/dist/m5/system/binaries/ts_osfpal
|
||||
readfile=tests/halt.sh
|
||||
symbolfile=
|
||||
system_rev=1024
|
||||
system_type=34
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.membus.slave[0]
|
||||
|
||||
[system.bridge]
|
||||
type=Bridge
|
||||
delay=50000
|
||||
nack_delay=4000
|
||||
ranges=8796093022208:18446744073709551615
|
||||
req_size=16
|
||||
resp_size=16
|
||||
write_ack=false
|
||||
master=system.iobus.slave[0]
|
||||
slave=system.membus.master[0]
|
||||
|
||||
[system.cpu]
|
||||
type=TimingSimpleCPU
|
||||
children=dcache dtb icache interrupts itb tracer
|
||||
checker=Null
|
||||
clock=500
|
||||
cpu_id=0
|
||||
defer_registration=false
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
interrupts=system.cpu.interrupts
|
||||
itb=system.cpu.itb
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
phase=0
|
||||
profile=0
|
||||
progress_interval=0
|
||||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
workload=
|
||||
dcache_port=system.cpu.dcache.cpu_side
|
||||
icache_port=system.cpu.icache.cpu_side
|
||||
|
||||
[system.cpu.dcache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=4
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=32768
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=8
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.dcache_port
|
||||
mem_side=system.toL2Bus.slave[1]
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=AlphaTLB
|
||||
size=64
|
||||
|
||||
[system.cpu.icache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=1
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=32768
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=8
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.icache_port
|
||||
mem_side=system.toL2Bus.slave[0]
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=AlphaInterrupts
|
||||
|
||||
[system.cpu.itb]
|
||||
type=AlphaTLB
|
||||
size=48
|
||||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
|
||||
[system.disk0]
|
||||
type=IdeDisk
|
||||
children=image
|
||||
delay=1000000
|
||||
driveID=master
|
||||
image=system.disk0.image
|
||||
|
||||
[system.disk0.image]
|
||||
type=CowDiskImage
|
||||
children=child
|
||||
child=system.disk0.image.child
|
||||
image_file=
|
||||
read_only=false
|
||||
table_size=65536
|
||||
|
||||
[system.disk0.image.child]
|
||||
type=RawDiskImage
|
||||
image_file=/dist/m5/system/disks/linux-latest.img
|
||||
read_only=true
|
||||
|
||||
[system.disk2]
|
||||
type=IdeDisk
|
||||
children=image
|
||||
delay=1000000
|
||||
driveID=master
|
||||
image=system.disk2.image
|
||||
|
||||
[system.disk2.image]
|
||||
type=CowDiskImage
|
||||
children=child
|
||||
child=system.disk2.image.child
|
||||
image_file=
|
||||
read_only=false
|
||||
table_size=65536
|
||||
|
||||
[system.disk2.image.child]
|
||||
type=RawDiskImage
|
||||
image_file=/dist/m5/system/disks/linux-bigswap2.img
|
||||
read_only=true
|
||||
|
||||
[system.intrctrl]
|
||||
type=IntrControl
|
||||
sys=system
|
||||
|
||||
[system.iobus]
|
||||
type=NoncoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
use_default_range=true
|
||||
width=64
|
||||
default=system.tsunami.pciconfig.pio
|
||||
master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ethernet.pio system.tsunami.ethernet.config system.iocache.cpu_side
|
||||
slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma
|
||||
|
||||
[system.iocache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:8589934591
|
||||
assoc=8
|
||||
block_size=64
|
||||
forward_snoops=false
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=50000
|
||||
max_miss_count=0
|
||||
mshrs=20
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=1024
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=12
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.iobus.master[29]
|
||||
mem_side=system.membus.slave[1]
|
||||
|
||||
[system.l2c]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=8
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=false
|
||||
latency=10000
|
||||
max_miss_count=0
|
||||
mshrs=92
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=4194304
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=16
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.toL2Bus.master[0]
|
||||
mem_side=system.membus.slave[2]
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
children=badaddr_responder
|
||||
block_size=64
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
default=system.membus.badaddr_responder.pio
|
||||
master=system.bridge.slave system.physmem.port[0]
|
||||
slave=system.system_port system.iocache.mem_side system.l2c.mem_side
|
||||
|
||||
[system.membus.badaddr_responder]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=0
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=true
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.membus.default
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.membus.master[1]
|
||||
|
||||
[system.simple_disk]
|
||||
type=SimpleDisk
|
||||
children=disk
|
||||
disk=system.simple_disk.disk
|
||||
system=system
|
||||
|
||||
[system.simple_disk.disk]
|
||||
type=RawDiskImage
|
||||
image_file=/dist/m5/system/disks/linux-latest.img
|
||||
read_only=true
|
||||
|
||||
[system.terminal]
|
||||
type=Terminal
|
||||
intr_control=system.intrctrl
|
||||
number=0
|
||||
output=true
|
||||
port=3456
|
||||
|
||||
[system.toL2Bus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
master=system.l2c.cpu_side
|
||||
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
|
||||
|
||||
[system.tsunami]
|
||||
type=Tsunami
|
||||
children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart
|
||||
intrctrl=system.intrctrl
|
||||
system=system
|
||||
|
||||
[system.tsunami.backdoor]
|
||||
type=AlphaBackdoor
|
||||
cpu=system.cpu
|
||||
disk=system.simple_disk
|
||||
pio_addr=8804682956800
|
||||
pio_latency=1000
|
||||
platform=system.tsunami
|
||||
system=system
|
||||
terminal=system.terminal
|
||||
pio=system.iobus.master[24]
|
||||
|
||||
[system.tsunami.cchip]
|
||||
type=TsunamiCChip
|
||||
pio_addr=8803072344064
|
||||
pio_latency=1000
|
||||
system=system
|
||||
tsunami=system.tsunami
|
||||
pio=system.iobus.master[0]
|
||||
|
||||
[system.tsunami.ethernet]
|
||||
type=NSGigE
|
||||
BAR0=1
|
||||
BAR0LegacyIO=false
|
||||
BAR0Size=256
|
||||
BAR1=0
|
||||
BAR1LegacyIO=false
|
||||
BAR1Size=4096
|
||||
BAR2=0
|
||||
BAR2LegacyIO=false
|
||||
BAR2Size=0
|
||||
BAR3=0
|
||||
BAR3LegacyIO=false
|
||||
BAR3Size=0
|
||||
BAR4=0
|
||||
BAR4LegacyIO=false
|
||||
BAR4Size=0
|
||||
BAR5=0
|
||||
BAR5LegacyIO=false
|
||||
BAR5Size=0
|
||||
BIST=0
|
||||
CacheLineSize=0
|
||||
CardbusCIS=0
|
||||
ClassCode=2
|
||||
Command=0
|
||||
DeviceID=34
|
||||
ExpansionROM=0
|
||||
HeaderType=0
|
||||
InterruptLine=30
|
||||
InterruptPin=1
|
||||
LatencyTimer=0
|
||||
MaximumLatency=52
|
||||
MinimumGrant=176
|
||||
ProgIF=0
|
||||
Revision=0
|
||||
Status=656
|
||||
SubClassCode=0
|
||||
SubsystemID=0
|
||||
SubsystemVendorID=0
|
||||
VendorID=4107
|
||||
clock=0
|
||||
config_latency=20000
|
||||
dma_data_free=false
|
||||
dma_desc_free=false
|
||||
dma_no_allocate=true
|
||||
dma_read_delay=0
|
||||
dma_read_factor=0
|
||||
dma_write_delay=0
|
||||
dma_write_factor=0
|
||||
hardware_address=00:90:00:00:00:01
|
||||
intr_delay=10000000
|
||||
max_backoff_delay=10000000
|
||||
min_backoff_delay=4000
|
||||
pci_bus=0
|
||||
pci_dev=1
|
||||
pci_func=0
|
||||
pio_latency=1000
|
||||
platform=system.tsunami
|
||||
rss=false
|
||||
rx_delay=1000000
|
||||
rx_fifo_size=524288
|
||||
rx_filter=true
|
||||
rx_thread=false
|
||||
system=system
|
||||
tx_delay=1000000
|
||||
tx_fifo_size=524288
|
||||
tx_thread=false
|
||||
config=system.iobus.master[28]
|
||||
dma=system.iobus.slave[2]
|
||||
pio=system.iobus.master[27]
|
||||
|
||||
[system.tsunami.fake_OROM]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8796093677568
|
||||
pio_latency=1000
|
||||
pio_size=393216
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[8]
|
||||
|
||||
[system.tsunami.fake_ata0]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615848432
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[19]
|
||||
|
||||
[system.tsunami.fake_ata1]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615848304
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[20]
|
||||
|
||||
[system.tsunami.fake_pnp_addr]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615848569
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[9]
|
||||
|
||||
[system.tsunami.fake_pnp_read0]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615848451
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[11]
|
||||
|
||||
[system.tsunami.fake_pnp_read1]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615848515
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[12]
|
||||
|
||||
[system.tsunami.fake_pnp_read2]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615848579
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[13]
|
||||
|
||||
[system.tsunami.fake_pnp_read3]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615848643
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[14]
|
||||
|
||||
[system.tsunami.fake_pnp_read4]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615848707
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[15]
|
||||
|
||||
[system.tsunami.fake_pnp_read5]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615848771
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[16]
|
||||
|
||||
[system.tsunami.fake_pnp_read6]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615848835
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[17]
|
||||
|
||||
[system.tsunami.fake_pnp_read7]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615848899
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[18]
|
||||
|
||||
[system.tsunami.fake_pnp_write]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615850617
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[10]
|
||||
|
||||
[system.tsunami.fake_ppc]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615848891
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[7]
|
||||
|
||||
[system.tsunami.fake_sm_chip]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615848816
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[2]
|
||||
|
||||
[system.tsunami.fake_uart1]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615848696
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[3]
|
||||
|
||||
[system.tsunami.fake_uart2]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615848936
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[4]
|
||||
|
||||
[system.tsunami.fake_uart3]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615848680
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[5]
|
||||
|
||||
[system.tsunami.fake_uart4]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615848944
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[6]
|
||||
|
||||
[system.tsunami.fb]
|
||||
type=BadDevice
|
||||
devicename=FrameBuffer
|
||||
pio_addr=8804615848912
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.iobus.master[21]
|
||||
|
||||
[system.tsunami.ide]
|
||||
type=IdeController
|
||||
BAR0=1
|
||||
BAR0LegacyIO=false
|
||||
BAR0Size=8
|
||||
BAR1=1
|
||||
BAR1LegacyIO=false
|
||||
BAR1Size=4
|
||||
BAR2=1
|
||||
BAR2LegacyIO=false
|
||||
BAR2Size=8
|
||||
BAR3=1
|
||||
BAR3LegacyIO=false
|
||||
BAR3Size=4
|
||||
BAR4=1
|
||||
BAR4LegacyIO=false
|
||||
BAR4Size=16
|
||||
BAR5=1
|
||||
BAR5LegacyIO=false
|
||||
BAR5Size=0
|
||||
BIST=0
|
||||
CacheLineSize=0
|
||||
CardbusCIS=0
|
||||
ClassCode=1
|
||||
Command=0
|
||||
DeviceID=28945
|
||||
ExpansionROM=0
|
||||
HeaderType=0
|
||||
InterruptLine=31
|
||||
InterruptPin=1
|
||||
LatencyTimer=0
|
||||
MaximumLatency=0
|
||||
MinimumGrant=0
|
||||
ProgIF=133
|
||||
Revision=0
|
||||
Status=640
|
||||
SubClassCode=1
|
||||
SubsystemID=0
|
||||
SubsystemVendorID=0
|
||||
VendorID=32902
|
||||
config_latency=20000
|
||||
ctrl_offset=0
|
||||
disks=system.disk0 system.disk2
|
||||
io_shift=0
|
||||
max_backoff_delay=10000000
|
||||
min_backoff_delay=4000
|
||||
pci_bus=0
|
||||
pci_dev=0
|
||||
pci_func=0
|
||||
pio_latency=1000
|
||||
platform=system.tsunami
|
||||
system=system
|
||||
config=system.iobus.master[26]
|
||||
dma=system.iobus.slave[1]
|
||||
pio=system.iobus.master[25]
|
||||
|
||||
[system.tsunami.io]
|
||||
type=TsunamiIO
|
||||
frequency=976562500
|
||||
pio_addr=8804615847936
|
||||
pio_latency=1000
|
||||
system=system
|
||||
time=Thu Jan 1 00:00:00 2009
|
||||
tsunami=system.tsunami
|
||||
year_is_bcd=false
|
||||
pio=system.iobus.master[22]
|
||||
|
||||
[system.tsunami.pchip]
|
||||
type=TsunamiPChip
|
||||
pio_addr=8802535473152
|
||||
pio_latency=1000
|
||||
system=system
|
||||
tsunami=system.tsunami
|
||||
pio=system.iobus.master[1]
|
||||
|
||||
[system.tsunami.pciconfig]
|
||||
type=PciConfigAll
|
||||
bus=0
|
||||
pio_latency=1
|
||||
platform=system.tsunami
|
||||
size=16777216
|
||||
system=system
|
||||
pio=system.iobus.default
|
||||
|
||||
[system.tsunami.uart]
|
||||
type=Uart8250
|
||||
pio_addr=8804615848952
|
||||
pio_latency=1000
|
||||
platform=system.tsunami
|
||||
system=system
|
||||
terminal=system.terminal
|
||||
pio=system.iobus.master[23]
|
||||
|
||||
@ -0,0 +1,5 @@
|
||||
warn: Sockets disabled, not accepting terminal connections
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: Prefetch instructions in Alpha do not do anything
|
||||
warn: Prefetch instructions in Alpha do not do anything
|
||||
hack: be nice to actually delete the event here
|
||||
@ -0,0 +1,12 @@
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jun 4 2012 11:50:11
|
||||
gem5 started Jun 4 2012 14:23:20
|
||||
gem5 executing on zizzer
|
||||
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing -re tests/run.py build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: kernel located at: /dist/m5/system/binaries/vmlinux
|
||||
0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 1915548867000 because m5_exit instruction encountered
|
||||
@ -0,0 +1,702 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 1.915549 # Number of seconds simulated
|
||||
sim_ticks 1915548867000 # Number of ticks simulated
|
||||
final_tick 1915548867000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1238015 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1238014 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 42244373047 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 292960 # Number of bytes of host memory used
|
||||
host_seconds 45.34 # Real time elapsed on the host
|
||||
sim_insts 56137087 # Number of instructions simulated
|
||||
sim_ops 56137087 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 943040 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 26067904 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::tsunami.ide 2652416 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 29663360 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 943040 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 943040 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 10122368 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 10122368 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 14735 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 407311 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::tsunami.ide 41444 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 463490 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 158162 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 158162 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 492308 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 13608582 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::tsunami.ide 1384677 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 15485567 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 492308 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 492308 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 5284317 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 5284317 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 5284317 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 492308 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 13608582 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::tsunami.ide 1384677 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 20769884 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.l2c.replacements 389289 # number of replacements
|
||||
system.l2c.tagsinuse 34352.038344 # Cycle average of tags in use
|
||||
system.l2c.total_refs 2311163 # Total number of references to valid blocks.
|
||||
system.l2c.sampled_refs 421794 # Sample count of references to valid blocks.
|
||||
system.l2c.avg_refs 5.479364 # Average number of references to valid blocks.
|
||||
system.l2c.warmup_cycle 6937912000 # Cycle when the warmup percentage was hit.
|
||||
system.l2c.occ_blocks::writebacks 23110.665097 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu.inst 3746.363547 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu.data 7495.009700 # Average occupied blocks per requestor
|
||||
system.l2c.occ_percent::writebacks 0.352641 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu.inst 0.057165 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu.data 0.114365 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::total 0.524171 # Average percentage of cache occupancy
|
||||
system.l2c.ReadReq_hits::cpu.inst 913599 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu.data 796862 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::total 1710461 # number of ReadReq hits
|
||||
system.l2c.Writeback_hits::writebacks 826671 # number of Writeback hits
|
||||
system.l2c.Writeback_hits::total 826671 # number of Writeback hits
|
||||
system.l2c.UpgradeReq_hits::cpu.data 6 # number of UpgradeReq hits
|
||||
system.l2c.UpgradeReq_hits::total 6 # number of UpgradeReq hits
|
||||
system.l2c.ReadExReq_hits::cpu.data 185878 # number of ReadExReq hits
|
||||
system.l2c.ReadExReq_hits::total 185878 # number of ReadExReq hits
|
||||
system.l2c.demand_hits::cpu.inst 913599 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu.data 982740 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::total 1896339 # number of demand (read+write) hits
|
||||
system.l2c.overall_hits::cpu.inst 913599 # number of overall hits
|
||||
system.l2c.overall_hits::cpu.data 982740 # number of overall hits
|
||||
system.l2c.overall_hits::total 1896339 # number of overall hits
|
||||
system.l2c.ReadReq_misses::cpu.inst 14735 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu.data 289403 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::total 304138 # number of ReadReq misses
|
||||
system.l2c.UpgradeReq_misses::cpu.data 7 # number of UpgradeReq misses
|
||||
system.l2c.UpgradeReq_misses::total 7 # number of UpgradeReq misses
|
||||
system.l2c.ReadExReq_misses::cpu.data 118294 # number of ReadExReq misses
|
||||
system.l2c.ReadExReq_misses::total 118294 # number of ReadExReq misses
|
||||
system.l2c.demand_misses::cpu.inst 14735 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu.data 407697 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::total 422432 # number of demand (read+write) misses
|
||||
system.l2c.overall_misses::cpu.inst 14735 # number of overall misses
|
||||
system.l2c.overall_misses::cpu.data 407697 # number of overall misses
|
||||
system.l2c.overall_misses::total 422432 # number of overall misses
|
||||
system.l2c.ReadReq_miss_latency::cpu.inst 766261500 # number of ReadReq miss cycles
|
||||
system.l2c.ReadReq_miss_latency::cpu.data 15053945000 # number of ReadReq miss cycles
|
||||
system.l2c.ReadReq_miss_latency::total 15820206500 # number of ReadReq miss cycles
|
||||
system.l2c.UpgradeReq_miss_latency::cpu.data 248000 # number of UpgradeReq miss cycles
|
||||
system.l2c.UpgradeReq_miss_latency::total 248000 # number of UpgradeReq miss cycles
|
||||
system.l2c.ReadExReq_miss_latency::cpu.data 6151753000 # number of ReadExReq miss cycles
|
||||
system.l2c.ReadExReq_miss_latency::total 6151753000 # number of ReadExReq miss cycles
|
||||
system.l2c.demand_miss_latency::cpu.inst 766261500 # number of demand (read+write) miss cycles
|
||||
system.l2c.demand_miss_latency::cpu.data 21205698000 # number of demand (read+write) miss cycles
|
||||
system.l2c.demand_miss_latency::total 21971959500 # number of demand (read+write) miss cycles
|
||||
system.l2c.overall_miss_latency::cpu.inst 766261500 # number of overall miss cycles
|
||||
system.l2c.overall_miss_latency::cpu.data 21205698000 # number of overall miss cycles
|
||||
system.l2c.overall_miss_latency::total 21971959500 # number of overall miss cycles
|
||||
system.l2c.ReadReq_accesses::cpu.inst 928334 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::cpu.data 1086265 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::total 2014599 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.Writeback_accesses::writebacks 826671 # number of Writeback accesses(hits+misses)
|
||||
system.l2c.Writeback_accesses::total 826671 # number of Writeback accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_accesses::cpu.data 13 # number of UpgradeReq accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_accesses::total 13 # number of UpgradeReq accesses(hits+misses)
|
||||
system.l2c.ReadExReq_accesses::cpu.data 304172 # number of ReadExReq accesses(hits+misses)
|
||||
system.l2c.ReadExReq_accesses::total 304172 # number of ReadExReq accesses(hits+misses)
|
||||
system.l2c.demand_accesses::cpu.inst 928334 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu.data 1390437 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::total 2318771 # number of demand (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu.inst 928334 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu.data 1390437 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::total 2318771 # number of overall (read+write) accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu.inst 0.015873 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu.data 0.266420 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::total 0.150967 # miss rate for ReadReq accesses
|
||||
system.l2c.UpgradeReq_miss_rate::cpu.data 0.538462 # miss rate for UpgradeReq accesses
|
||||
system.l2c.UpgradeReq_miss_rate::total 0.538462 # miss rate for UpgradeReq accesses
|
||||
system.l2c.ReadExReq_miss_rate::cpu.data 0.388905 # miss rate for ReadExReq accesses
|
||||
system.l2c.ReadExReq_miss_rate::total 0.388905 # miss rate for ReadExReq accesses
|
||||
system.l2c.demand_miss_rate::cpu.inst 0.015873 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu.data 0.293215 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::total 0.182179 # miss rate for demand accesses
|
||||
system.l2c.overall_miss_rate::cpu.inst 0.015873 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu.data 0.293215 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::total 0.182179 # miss rate for overall accesses
|
||||
system.l2c.ReadReq_avg_miss_latency::cpu.inst 52002.816423 # average ReadReq miss latency
|
||||
system.l2c.ReadReq_avg_miss_latency::cpu.data 52017.238937 # average ReadReq miss latency
|
||||
system.l2c.ReadReq_avg_miss_latency::total 52016.540189 # average ReadReq miss latency
|
||||
system.l2c.UpgradeReq_avg_miss_latency::cpu.data 35428.571429 # average UpgradeReq miss latency
|
||||
system.l2c.UpgradeReq_avg_miss_latency::total 35428.571429 # average UpgradeReq miss latency
|
||||
system.l2c.ReadExReq_avg_miss_latency::cpu.data 52003.930884 # average ReadExReq miss latency
|
||||
system.l2c.ReadExReq_avg_miss_latency::total 52003.930884 # average ReadExReq miss latency
|
||||
system.l2c.demand_avg_miss_latency::cpu.inst 52002.816423 # average overall miss latency
|
||||
system.l2c.demand_avg_miss_latency::cpu.data 52013.377582 # average overall miss latency
|
||||
system.l2c.demand_avg_miss_latency::total 52013.009194 # average overall miss latency
|
||||
system.l2c.overall_avg_miss_latency::cpu.inst 52002.816423 # average overall miss latency
|
||||
system.l2c.overall_avg_miss_latency::cpu.data 52013.377582 # average overall miss latency
|
||||
system.l2c.overall_avg_miss_latency::total 52013.009194 # average overall miss latency
|
||||
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.l2c.fast_writes 0 # number of fast writes performed
|
||||
system.l2c.cache_copies 0 # number of cache copies performed
|
||||
system.l2c.writebacks::writebacks 116650 # number of writebacks
|
||||
system.l2c.writebacks::total 116650 # number of writebacks
|
||||
system.l2c.ReadReq_mshr_misses::cpu.inst 14735 # number of ReadReq MSHR misses
|
||||
system.l2c.ReadReq_mshr_misses::cpu.data 289403 # number of ReadReq MSHR misses
|
||||
system.l2c.ReadReq_mshr_misses::total 304138 # number of ReadReq MSHR misses
|
||||
system.l2c.UpgradeReq_mshr_misses::cpu.data 7 # number of UpgradeReq MSHR misses
|
||||
system.l2c.UpgradeReq_mshr_misses::total 7 # number of UpgradeReq MSHR misses
|
||||
system.l2c.ReadExReq_mshr_misses::cpu.data 118294 # number of ReadExReq MSHR misses
|
||||
system.l2c.ReadExReq_mshr_misses::total 118294 # number of ReadExReq MSHR misses
|
||||
system.l2c.demand_mshr_misses::cpu.inst 14735 # number of demand (read+write) MSHR misses
|
||||
system.l2c.demand_mshr_misses::cpu.data 407697 # number of demand (read+write) MSHR misses
|
||||
system.l2c.demand_mshr_misses::total 422432 # number of demand (read+write) MSHR misses
|
||||
system.l2c.overall_mshr_misses::cpu.inst 14735 # number of overall MSHR misses
|
||||
system.l2c.overall_mshr_misses::cpu.data 407697 # number of overall MSHR misses
|
||||
system.l2c.overall_mshr_misses::total 422432 # number of overall MSHR misses
|
||||
system.l2c.ReadReq_mshr_miss_latency::cpu.inst 589436000 # number of ReadReq MSHR miss cycles
|
||||
system.l2c.ReadReq_mshr_miss_latency::cpu.data 11581109000 # number of ReadReq MSHR miss cycles
|
||||
system.l2c.ReadReq_mshr_miss_latency::total 12170545000 # number of ReadReq MSHR miss cycles
|
||||
system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 320000 # number of UpgradeReq MSHR miss cycles
|
||||
system.l2c.UpgradeReq_mshr_miss_latency::total 320000 # number of UpgradeReq MSHR miss cycles
|
||||
system.l2c.ReadExReq_mshr_miss_latency::cpu.data 4732225000 # number of ReadExReq MSHR miss cycles
|
||||
system.l2c.ReadExReq_mshr_miss_latency::total 4732225000 # number of ReadExReq MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_latency::cpu.inst 589436000 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_latency::cpu.data 16313334000 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_latency::total 16902770000 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency::cpu.inst 589436000 # number of overall MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency::cpu.data 16313334000 # number of overall MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency::total 16902770000 # number of overall MSHR miss cycles
|
||||
system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 772673000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.l2c.ReadReq_mshr_uncacheable_latency::total 772673000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 1083819500 # number of WriteReq MSHR uncacheable cycles
|
||||
system.l2c.WriteReq_mshr_uncacheable_latency::total 1083819500 # number of WriteReq MSHR uncacheable cycles
|
||||
system.l2c.overall_mshr_uncacheable_latency::cpu.data 1856492500 # number of overall MSHR uncacheable cycles
|
||||
system.l2c.overall_mshr_uncacheable_latency::total 1856492500 # number of overall MSHR uncacheable cycles
|
||||
system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.015873 # mshr miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.266420 # mshr miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_mshr_miss_rate::total 0.150967 # mshr miss rate for ReadReq accesses
|
||||
system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.538462 # mshr miss rate for UpgradeReq accesses
|
||||
system.l2c.UpgradeReq_mshr_miss_rate::total 0.538462 # mshr miss rate for UpgradeReq accesses
|
||||
system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.388905 # mshr miss rate for ReadExReq accesses
|
||||
system.l2c.ReadExReq_mshr_miss_rate::total 0.388905 # mshr miss rate for ReadExReq accesses
|
||||
system.l2c.demand_mshr_miss_rate::cpu.inst 0.015873 # mshr miss rate for demand accesses
|
||||
system.l2c.demand_mshr_miss_rate::cpu.data 0.293215 # mshr miss rate for demand accesses
|
||||
system.l2c.demand_mshr_miss_rate::total 0.182179 # mshr miss rate for demand accesses
|
||||
system.l2c.overall_mshr_miss_rate::cpu.inst 0.015873 # mshr miss rate for overall accesses
|
||||
system.l2c.overall_mshr_miss_rate::cpu.data 0.293215 # mshr miss rate for overall accesses
|
||||
system.l2c.overall_mshr_miss_rate::total 0.182179 # mshr miss rate for overall accesses
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40002.443163 # average ReadReq mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40017.238937 # average ReadReq mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::total 40016.522105 # average ReadReq mshr miss latency
|
||||
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 45714.285714 # average UpgradeReq mshr miss latency
|
||||
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 45714.285714 # average UpgradeReq mshr miss latency
|
||||
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40003.930884 # average ReadExReq mshr miss latency
|
||||
system.l2c.ReadExReq_avg_mshr_miss_latency::total 40003.930884 # average ReadExReq mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40002.443163 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu.data 40013.377582 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::total 40012.996175 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40002.443163 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu.data 40013.377582 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::total 40012.996175 # average overall mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
|
||||
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
||||
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
|
||||
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
||||
system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
|
||||
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
||||
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.iocache.replacements 41685 # number of replacements
|
||||
system.iocache.tagsinuse 1.340325 # Cycle average of tags in use
|
||||
system.iocache.total_refs 0 # Total number of references to valid blocks.
|
||||
system.iocache.sampled_refs 41701 # Sample count of references to valid blocks.
|
||||
system.iocache.avg_refs 0 # Average number of references to valid blocks.
|
||||
system.iocache.warmup_cycle 1750545944000 # Cycle when the warmup percentage was hit.
|
||||
system.iocache.occ_blocks::tsunami.ide 1.340325 # Average occupied blocks per requestor
|
||||
system.iocache.occ_percent::tsunami.ide 0.083770 # Average percentage of cache occupancy
|
||||
system.iocache.occ_percent::total 0.083770 # Average percentage of cache occupancy
|
||||
system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses
|
||||
system.iocache.ReadReq_misses::total 173 # number of ReadReq misses
|
||||
system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses
|
||||
system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses
|
||||
system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses
|
||||
system.iocache.demand_misses::total 41725 # number of demand (read+write) misses
|
||||
system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses
|
||||
system.iocache.overall_misses::total 41725 # number of overall misses
|
||||
system.iocache.ReadReq_miss_latency::tsunami.ide 19940998 # number of ReadReq miss cycles
|
||||
system.iocache.ReadReq_miss_latency::total 19940998 # number of ReadReq miss cycles
|
||||
system.iocache.WriteReq_miss_latency::tsunami.ide 5722300806 # number of WriteReq miss cycles
|
||||
system.iocache.WriteReq_miss_latency::total 5722300806 # number of WriteReq miss cycles
|
||||
system.iocache.demand_miss_latency::tsunami.ide 5742241804 # number of demand (read+write) miss cycles
|
||||
system.iocache.demand_miss_latency::total 5742241804 # number of demand (read+write) miss cycles
|
||||
system.iocache.overall_miss_latency::tsunami.ide 5742241804 # number of overall miss cycles
|
||||
system.iocache.overall_miss_latency::total 5742241804 # number of overall miss cycles
|
||||
system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses)
|
||||
system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses)
|
||||
system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses)
|
||||
system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses)
|
||||
system.iocache.demand_accesses::tsunami.ide 41725 # number of demand (read+write) accesses
|
||||
system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses
|
||||
system.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses
|
||||
system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses
|
||||
system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
|
||||
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
|
||||
system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses
|
||||
system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
|
||||
system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses
|
||||
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
|
||||
system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
|
||||
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
|
||||
system.iocache.ReadReq_avg_miss_latency::tsunami.ide 115265.884393 # average ReadReq miss latency
|
||||
system.iocache.ReadReq_avg_miss_latency::total 115265.884393 # average ReadReq miss latency
|
||||
system.iocache.WriteReq_avg_miss_latency::tsunami.ide 137714.208847 # average WriteReq miss latency
|
||||
system.iocache.WriteReq_avg_miss_latency::total 137714.208847 # average WriteReq miss latency
|
||||
system.iocache.demand_avg_miss_latency::tsunami.ide 137621.133709 # average overall miss latency
|
||||
system.iocache.demand_avg_miss_latency::total 137621.133709 # average overall miss latency
|
||||
system.iocache.overall_avg_miss_latency::tsunami.ide 137621.133709 # average overall miss latency
|
||||
system.iocache.overall_avg_miss_latency::total 137621.133709 # average overall miss latency
|
||||
system.iocache.blocked_cycles::no_mshrs 64604060 # number of cycles access was blocked
|
||||
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.iocache.blocked::no_mshrs 10476 # number of cycles access was blocked
|
||||
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.iocache.avg_blocked_cycles::no_mshrs 6166.863307 # average number of cycles each access was blocked
|
||||
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.iocache.fast_writes 0 # number of fast writes performed
|
||||
system.iocache.cache_copies 0 # number of cache copies performed
|
||||
system.iocache.writebacks::writebacks 41512 # number of writebacks
|
||||
system.iocache.writebacks::total 41512 # number of writebacks
|
||||
system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses
|
||||
system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses
|
||||
system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses
|
||||
system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses
|
||||
system.iocache.demand_mshr_misses::tsunami.ide 41725 # number of demand (read+write) MSHR misses
|
||||
system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses
|
||||
system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses
|
||||
system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses
|
||||
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 10944998 # number of ReadReq MSHR miss cycles
|
||||
system.iocache.ReadReq_mshr_miss_latency::total 10944998 # number of ReadReq MSHR miss cycles
|
||||
system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 3561447990 # number of WriteReq MSHR miss cycles
|
||||
system.iocache.WriteReq_mshr_miss_latency::total 3561447990 # number of WriteReq MSHR miss cycles
|
||||
system.iocache.demand_mshr_miss_latency::tsunami.ide 3572392988 # number of demand (read+write) MSHR miss cycles
|
||||
system.iocache.demand_mshr_miss_latency::total 3572392988 # number of demand (read+write) MSHR miss cycles
|
||||
system.iocache.overall_mshr_miss_latency::tsunami.ide 3572392988 # number of overall MSHR miss cycles
|
||||
system.iocache.overall_mshr_miss_latency::total 3572392988 # number of overall MSHR miss cycles
|
||||
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
|
||||
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
|
||||
system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses
|
||||
system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
|
||||
system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses
|
||||
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
|
||||
system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses
|
||||
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
|
||||
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 63265.884393 # average ReadReq mshr miss latency
|
||||
system.iocache.ReadReq_avg_mshr_miss_latency::total 63265.884393 # average ReadReq mshr miss latency
|
||||
system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 85710.627407 # average WriteReq mshr miss latency
|
||||
system.iocache.WriteReq_avg_mshr_miss_latency::total 85710.627407 # average WriteReq mshr miss latency
|
||||
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 85617.567118 # average overall mshr miss latency
|
||||
system.iocache.demand_avg_mshr_miss_latency::total 85617.567118 # average overall mshr miss latency
|
||||
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 85617.567118 # average overall mshr miss latency
|
||||
system.iocache.overall_avg_mshr_miss_latency::total 85617.567118 # average overall mshr miss latency
|
||||
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
||||
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
|
||||
system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
|
||||
system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
|
||||
system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
|
||||
system.disk0.dma_write_txs 395 # Number of DMA write transactions.
|
||||
system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
||||
system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
|
||||
system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
|
||||
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
|
||||
system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
|
||||
system.disk2.dma_write_txs 1 # Number of DMA write transactions.
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
||||
system.cpu.dtb.read_hits 9057511 # DTB read hits
|
||||
system.cpu.dtb.read_misses 10312 # DTB read misses
|
||||
system.cpu.dtb.read_acv 210 # DTB read access violations
|
||||
system.cpu.dtb.read_accesses 728817 # DTB read accesses
|
||||
system.cpu.dtb.write_hits 6352446 # DTB write hits
|
||||
system.cpu.dtb.write_misses 1140 # DTB write misses
|
||||
system.cpu.dtb.write_acv 157 # DTB write access violations
|
||||
system.cpu.dtb.write_accesses 291929 # DTB write accesses
|
||||
system.cpu.dtb.data_hits 15409957 # DTB hits
|
||||
system.cpu.dtb.data_misses 11452 # DTB misses
|
||||
system.cpu.dtb.data_acv 367 # DTB access violations
|
||||
system.cpu.dtb.data_accesses 1020746 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 4973520 # ITB hits
|
||||
system.cpu.itb.fetch_misses 4997 # ITB misses
|
||||
system.cpu.itb.fetch_acv 184 # ITB acv
|
||||
system.cpu.itb.fetch_accesses 4978517 # ITB accesses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.itb.write_hits 0 # DTB write hits
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.itb.write_acv 0 # DTB write access violations
|
||||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.itb.data_hits 0 # DTB hits
|
||||
system.cpu.itb.data_misses 0 # DTB misses
|
||||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.numCycles 3831097734 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 56137087 # Number of instructions committed
|
||||
system.cpu.committedOps 56137087 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 52011214 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 324192 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 1482242 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 6464616 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 52011214 # number of integer instructions
|
||||
system.cpu.num_fp_insts 324192 # number of float instructions
|
||||
system.cpu.num_int_register_reads 71259077 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 38485860 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 163510 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 166384 # number of times the floating registers were written
|
||||
system.cpu.num_mem_refs 15462519 # number of memory refs
|
||||
system.cpu.num_load_insts 9094324 # Number of load instructions
|
||||
system.cpu.num_store_insts 6368195 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 3587943187.998127 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 243154546.001873 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 0.063469 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0.936531 # Percentage of idle cycles
|
||||
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
||||
system.cpu.kern.inst.quiesce 6379 # number of quiesce instructions executed
|
||||
system.cpu.kern.inst.hwrei 211932 # number of hwrei instructions executed
|
||||
system.cpu.kern.ipl_count::0 74887 40.89% 40.89% # number of times we switched to this ipl
|
||||
system.cpu.kern.ipl_count::21 131 0.07% 40.96% # number of times we switched to this ipl
|
||||
system.cpu.kern.ipl_count::22 1931 1.05% 42.02% # number of times we switched to this ipl
|
||||
system.cpu.kern.ipl_count::31 106197 57.98% 100.00% # number of times we switched to this ipl
|
||||
system.cpu.kern.ipl_count::total 183146 # number of times we switched to this ipl
|
||||
system.cpu.kern.ipl_good::0 73520 49.31% 49.31% # number of times we switched to this ipl from a different ipl
|
||||
system.cpu.kern.ipl_good::21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl
|
||||
system.cpu.kern.ipl_good::22 1931 1.30% 50.69% # number of times we switched to this ipl from a different ipl
|
||||
system.cpu.kern.ipl_good::31 73520 49.31% 100.00% # number of times we switched to this ipl from a different ipl
|
||||
system.cpu.kern.ipl_good::total 149102 # number of times we switched to this ipl from a different ipl
|
||||
system.cpu.kern.ipl_ticks::0 1857816228500 96.99% 96.99% # number of cycles we spent at this ipl
|
||||
system.cpu.kern.ipl_ticks::21 79988500 0.00% 96.99% # number of cycles we spent at this ipl
|
||||
system.cpu.kern.ipl_ticks::22 554693000 0.03% 97.02% # number of cycles we spent at this ipl
|
||||
system.cpu.kern.ipl_ticks::31 57097199000 2.98% 100.00% # number of cycles we spent at this ipl
|
||||
system.cpu.kern.ipl_ticks::total 1915548109000 # number of cycles we spent at this ipl
|
||||
system.cpu.kern.ipl_used::0 0.981746 # fraction of swpipl calls that actually changed the ipl
|
||||
system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
|
||||
system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
|
||||
system.cpu.kern.ipl_used::31 0.692298 # fraction of swpipl calls that actually changed the ipl
|
||||
system.cpu.kern.ipl_used::total 0.814116 # fraction of swpipl calls that actually changed the ipl
|
||||
system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed
|
||||
system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed
|
||||
system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed
|
||||
system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed
|
||||
system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed
|
||||
system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed
|
||||
system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed
|
||||
system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed
|
||||
system.cpu.kern.syscall::20 6 1.84% 35.89% # number of syscalls executed
|
||||
system.cpu.kern.syscall::23 4 1.23% 37.12% # number of syscalls executed
|
||||
system.cpu.kern.syscall::24 6 1.84% 38.96% # number of syscalls executed
|
||||
system.cpu.kern.syscall::33 11 3.37% 42.33% # number of syscalls executed
|
||||
system.cpu.kern.syscall::41 2 0.61% 42.94% # number of syscalls executed
|
||||
system.cpu.kern.syscall::45 54 16.56% 59.51% # number of syscalls executed
|
||||
system.cpu.kern.syscall::47 6 1.84% 61.35% # number of syscalls executed
|
||||
system.cpu.kern.syscall::48 10 3.07% 64.42% # number of syscalls executed
|
||||
system.cpu.kern.syscall::54 10 3.07% 67.48% # number of syscalls executed
|
||||
system.cpu.kern.syscall::58 1 0.31% 67.79% # number of syscalls executed
|
||||
system.cpu.kern.syscall::59 7 2.15% 69.94% # number of syscalls executed
|
||||
system.cpu.kern.syscall::71 54 16.56% 86.50% # number of syscalls executed
|
||||
system.cpu.kern.syscall::73 3 0.92% 87.42% # number of syscalls executed
|
||||
system.cpu.kern.syscall::74 16 4.91% 92.33% # number of syscalls executed
|
||||
system.cpu.kern.syscall::87 1 0.31% 92.64% # number of syscalls executed
|
||||
system.cpu.kern.syscall::90 3 0.92% 93.56% # number of syscalls executed
|
||||
system.cpu.kern.syscall::92 9 2.76% 96.32% # number of syscalls executed
|
||||
system.cpu.kern.syscall::97 2 0.61% 96.93% # number of syscalls executed
|
||||
system.cpu.kern.syscall::98 2 0.61% 97.55% # number of syscalls executed
|
||||
system.cpu.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed
|
||||
system.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed
|
||||
system.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed
|
||||
system.cpu.kern.syscall::total 326 # number of syscalls executed
|
||||
system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
|
||||
system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed
|
||||
system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed
|
||||
system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed
|
||||
system.cpu.kern.callpal::swpctx 4173 2.16% 2.17% # number of callpals executed
|
||||
system.cpu.kern.callpal::tbi 54 0.03% 2.19% # number of callpals executed
|
||||
system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed
|
||||
system.cpu.kern.callpal::swpipl 175927 91.22% 93.41% # number of callpals executed
|
||||
system.cpu.kern.callpal::rdps 6832 3.54% 96.96% # number of callpals executed
|
||||
system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed
|
||||
system.cpu.kern.callpal::wrusp 7 0.00% 96.96% # number of callpals executed
|
||||
system.cpu.kern.callpal::rdusp 9 0.00% 96.96% # number of callpals executed
|
||||
system.cpu.kern.callpal::whami 2 0.00% 96.97% # number of callpals executed
|
||||
system.cpu.kern.callpal::rti 5156 2.67% 99.64% # number of callpals executed
|
||||
system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed
|
||||
system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed
|
||||
system.cpu.kern.callpal::total 192868 # number of callpals executed
|
||||
system.cpu.kern.mode_switch::kernel 5903 # number of protection mode switches
|
||||
system.cpu.kern.mode_switch::user 1738 # number of protection mode switches
|
||||
system.cpu.kern.mode_switch::idle 2092 # number of protection mode switches
|
||||
system.cpu.kern.mode_good::kernel 1906
|
||||
system.cpu.kern.mode_good::user 1738
|
||||
system.cpu.kern.mode_good::idle 168
|
||||
system.cpu.kern.mode_switch_good::kernel 0.322887 # fraction of useful protection mode switches
|
||||
system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
|
||||
system.cpu.kern.mode_switch_good::idle 0.080306 # fraction of useful protection mode switches
|
||||
system.cpu.kern.mode_switch_good::total 0.391657 # fraction of useful protection mode switches
|
||||
system.cpu.kern.mode_ticks::kernel 45253274000 2.36% 2.36% # number of ticks spent at the given mode
|
||||
system.cpu.kern.mode_ticks::user 5124228000 0.27% 2.63% # number of ticks spent at the given mode
|
||||
system.cpu.kern.mode_ticks::idle 1865170605000 97.37% 100.00% # number of ticks spent at the given mode
|
||||
system.cpu.kern.swap_context 4174 # number of times the context was actually changed
|
||||
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
|
||||
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
|
||||
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
|
||||
system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
|
||||
system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
|
||||
system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
|
||||
system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
|
||||
system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
|
||||
system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
|
||||
system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
|
||||
system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
|
||||
system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
|
||||
system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
|
||||
system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
|
||||
system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
|
||||
system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
|
||||
system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
|
||||
system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
|
||||
system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
|
||||
system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
|
||||
system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
|
||||
system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
|
||||
system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
|
||||
system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
|
||||
system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
|
||||
system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
|
||||
system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
|
||||
system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
|
||||
system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
|
||||
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
|
||||
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
|
||||
system.cpu.icache.replacements 927683 # number of replacements
|
||||
system.cpu.icache.tagsinuse 508.721464 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 55220553 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 928194 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 59.492469 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 36307428000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 508.721464 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.993597 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.993597 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 55220553 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 55220553 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 55220553 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 55220553 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 55220553 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 55220553 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 928354 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 928354 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 928354 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 928354 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 928354 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 928354 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 13616370500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 13616370500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 13616370500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 13616370500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 13616370500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 13616370500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 56148907 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 56148907 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 56148907 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 56148907 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 56148907 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 56148907 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016534 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.016534 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.016534 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.016534 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.016534 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.016534 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14667.218001 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 14667.218001 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 14667.218001 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 14667.218001 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 14667.218001 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 14667.218001 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks::writebacks 85 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 85 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 928354 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 928354 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 928354 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 928354 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 928354 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 928354 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10830625500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 10830625500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10830625500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 10830625500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10830625500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 10830625500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016534 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016534 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016534 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.016534 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016534 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.016534 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11666.482290 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11666.482290 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11666.482290 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 11666.482290 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11666.482290 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 11666.482290 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 1390115 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 511.984023 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 14038335 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 1390627 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 10.094968 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 84029000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 511.984023 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.999969 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.999969 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 7807536 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 7807536 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 5848554 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 5848554 # number of WriteReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::cpu.data 183025 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::total 183025 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::cpu.data 199203 # number of StoreCondReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::total 199203 # number of StoreCondReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 13656090 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 13656090 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 13656090 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 13656090 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 1069110 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 1069110 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 304335 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 304335 # number of WriteReq misses
|
||||
system.cpu.dcache.LoadLockedReq_misses::cpu.data 17201 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.LoadLockedReq_misses::total 17201 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 1373445 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 1373445 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 1373445 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 1373445 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 27121920500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 27121920500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 9228484000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 9228484000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 245980000 # number of LoadLockedReq miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_miss_latency::total 245980000 # number of LoadLockedReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 36350404500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 36350404500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 36350404500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 36350404500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 8876646 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 8876646 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 6152889 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 6152889 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200226 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::total 200226 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::cpu.data 199203 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::total 199203 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 15029535 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 15029535 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 15029535 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 15029535 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120441 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.120441 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049462 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.049462 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085908 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.085908 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.091383 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.091383 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.091383 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.091383 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 25368.690313 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 25368.690313 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30323.439631 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 30323.439631 # average WriteReq miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14300.331376 # average LoadLockedReq miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14300.331376 # average LoadLockedReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 26466.589124 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 26466.589124 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 26466.589124 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 26466.589124 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 826586 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 826586 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069110 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 1069110 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304335 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 304335 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17201 # number of LoadLockedReq MSHR misses
|
||||
system.cpu.dcache.LoadLockedReq_mshr_misses::total 17201 # number of LoadLockedReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 1373445 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 1373445 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 1373445 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 1373445 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23914545000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 23914545000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8315479000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 8315479000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 194377000 # number of LoadLockedReq MSHR miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 194377000 # number of LoadLockedReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 32230024000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 32230024000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 32230024000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 32230024000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 862763000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 862763000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1199607500 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1199607500 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 2062370500 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency::total 2062370500 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120441 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120441 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049462 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049462 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.085908 # mshr miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.085908 # mshr miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091383 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.091383 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091383 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.091383 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22368.647754 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22368.647754 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27323.439631 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27323.439631 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11300.331376 # average LoadLockedReq mshr miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11300.331376 # average LoadLockedReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23466.555996 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 23466.555996 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23466.555996 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 23466.555996 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
@ -0,0 +1,108 @@
|
||||
M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
|
||||
|
||||
Got Configuration 623
|
||||
|
||||
memsize 8000000 pages 4000
|
||||
|
||||
First free page after ROM 0xFFFFFC0000018000
|
||||
|
||||
HWRPB 0xFFFFFC0000018000 l1pt 0xFFFFFC0000040000 l2pt 0xFFFFFC0000042000 l3pt_rpb 0xFFFFFC0000044000 l3pt_kernel 0xFFFFFC0000048000 l2reserv 0xFFFFFC0000046000
|
||||
|
||||
kstart = 0xFFFFFC0000310000, kend = 0xFFFFFC0000855898, kentry = 0xFFFFFC0000310000, numCPUs = 0x1
|
||||
|
||||
CPU Clock at 2000 MHz IntrClockFrequency=1024
|
||||
|
||||
Booting with 1 processor(s)
|
||||
|
||||
KSP: 0x20043FE8 PTBR 0x20
|
||||
|
||||
Console Callback at 0x0, fixup at 0x0, crb offset: 0x510
|
||||
|
||||
Memory cluster 0 [0 - 392]
|
||||
|
||||
Memory cluster 1 [392 - 15992]
|
||||
|
||||
Initalizing mdt_bitmap addr 0xFFFFFC0000038000 mem_pages 4000
|
||||
|
||||
ConsoleDispatch at virt 10000658 phys 18658 val FFFFFC00000100A8
|
||||
|
||||
unix_boot_mem ends at FFFFFC0000076000
|
||||
|
||||
k_argc = 0
|
||||
|
||||
jumping to kernel at 0xFFFFFC0000310000, (PCBB 0xFFFFFC0000018180 pfn 1067)
|
||||
|
||||
CallbackFixup 0 18000, t7=FFFFFC000070C000
|
||||
|
||||
Linux version 2.6.13 (hsul@zed.eecs.umich.edu) (gcc version 3.4.3) #1 SMP Sun Oct 8 19:52:07 EDT 2006
|
||||
|
||||
Booting GENERIC on Tsunami variation DP264 using machine vector DP264 from SRM
|
||||
|
||||
Major Options: SMP LEGACY_START VERBOSE_MCHECK
|
||||
|
||||
Command line: root=/dev/hda1 console=ttyS0
|
||||
|
||||
memcluster 0, usage 1, start 0, end 392
|
||||
|
||||
memcluster 1, usage 0, start 392, end 16384
|
||||
|
||||
freeing pages 1069:16384
|
||||
|
||||
reserving pages 1069:1070
|
||||
|
||||
4096K Bcache detected; load hit latency 40 cycles, load miss latency 124 cycles
|
||||
|
||||
SMP: 1 CPUs probed -- cpu_present_mask = 1
|
||||
|
||||
Built 1 zonelists
|
||||
|
||||
Kernel command line: root=/dev/hda1 console=ttyS0
|
||||
|
||||
PID hash table entries: 1024 (order: 10, 32768 bytes)
|
||||
|
||||
Using epoch = 1900
|
||||
|
||||
Console: colour dummy device 80x25
|
||||
|
||||
Dentry cache hash table entries: 32768 (order: 5, 262144 bytes)
|
||||
|
||||
Inode-cache hash table entries: 16384 (order: 4, 131072 bytes)
|
||||
|
||||
Memory: 118784k/131072k available (3314k kernel code, 8952k reserved, 983k data, 224k init)
|
||||
|
||||
Mount-cache hash table entries: 512
|
||||
|
||||
SMP mode deactivated.
|
||||
|
||||
Brought up 1 CPUs
|
||||
|
||||
SMP: Total of 1 processors activated (4002.20 BogoMIPS).
|
||||
|
||||
NET: Registered protocol family 16
|
||||
|
||||
EISA bus registered
|
||||
|
||||
pci: enabling save/restore of SRM state
|
||||
|
||||
SCSI subsystem initialized
|
||||
|
||||
srm_env: version 0.0.5 loaded successfully
|
||||
|
||||
Installing knfsd (copyright (C) 1996 okir@monad.swb.de).
|
||||
|
||||
Initializing Cryptographic API
|
||||
|
||||
rtc: Standard PC (1900) epoch (1900) detected
|
||||
|
||||
Real Time Clock Driver v1.12
|
||||
|
||||
Serial: 8250/16550 driver $Revision: 1.90 $ 1 ports, IRQ sharing disabled
|
||||
|
||||
ttyS0 at I/O 0x3f8 (irq = 4) is a 8250
|
||||
|
||||
io scheduler noop registered
|
||||
|
||||
io scheduler anticipatory registered
|
||||
|
||||
io scheduler deadline registered
|
||||
|
||||
@ -0,0 +1,791 @@
|
||||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
full_system=true
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
||||
[system]
|
||||
type=LinuxArmSystem
|
||||
children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver
|
||||
atags_addr=256
|
||||
boot_loader=/dist/m5/system/binaries/boot.arm
|
||||
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
|
||||
early_kernel_symbols=false
|
||||
flags_addr=268435504
|
||||
gic_cpu_addr=520093952
|
||||
init_param=0
|
||||
kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
|
||||
load_addr_mask=268435455
|
||||
machine_type=RealView_PBX
|
||||
mem_mode=atomic
|
||||
memories=system.realview.nvmem system.physmem
|
||||
midr_regval=890224640
|
||||
num_work_ids=16
|
||||
readfile=tests/halt.sh
|
||||
symbolfile=
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.membus.slave[0]
|
||||
|
||||
[system.bridge]
|
||||
type=Bridge
|
||||
delay=50000
|
||||
nack_delay=4000
|
||||
ranges=268435456:520093695 1073741824:1610612735
|
||||
req_size=16
|
||||
resp_size=16
|
||||
write_ack=false
|
||||
master=system.iobus.slave[0]
|
||||
slave=system.membus.master[0]
|
||||
|
||||
[system.cf0]
|
||||
type=IdeDisk
|
||||
children=image
|
||||
delay=1000000
|
||||
driveID=master
|
||||
image=system.cf0.image
|
||||
|
||||
[system.cf0.image]
|
||||
type=CowDiskImage
|
||||
children=child
|
||||
child=system.cf0.image.child
|
||||
image_file=
|
||||
read_only=false
|
||||
table_size=65536
|
||||
|
||||
[system.cf0.image.child]
|
||||
type=RawDiskImage
|
||||
image_file=/dist/m5/system/disks/linux-arm-ael.img
|
||||
read_only=true
|
||||
|
||||
[system.cpu0]
|
||||
type=AtomicSimpleCPU
|
||||
children=dcache dtb icache interrupts itb tracer
|
||||
checker=Null
|
||||
clock=500
|
||||
cpu_id=0
|
||||
defer_registration=false
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu0.dtb
|
||||
fastmem=false
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
interrupts=system.cpu0.interrupts
|
||||
itb=system.cpu0.itb
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
phase=0
|
||||
profile=0
|
||||
progress_interval=0
|
||||
simulate_data_stalls=false
|
||||
simulate_inst_stalls=false
|
||||
system=system
|
||||
tracer=system.cpu0.tracer
|
||||
width=1
|
||||
workload=
|
||||
dcache_port=system.cpu0.dcache.cpu_side
|
||||
icache_port=system.cpu0.icache.cpu_side
|
||||
|
||||
[system.cpu0.dcache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=4
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=32768
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=8
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu0.dcache_port
|
||||
mem_side=system.toL2Bus.slave[1]
|
||||
|
||||
[system.cpu0.dtb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
size=64
|
||||
walker=system.cpu0.dtb.walker
|
||||
|
||||
[system.cpu0.dtb.walker]
|
||||
type=ArmTableWalker
|
||||
max_backoff=100000
|
||||
min_backoff=0
|
||||
sys=system
|
||||
port=system.toL2Bus.slave[3]
|
||||
|
||||
[system.cpu0.icache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=1
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=32768
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=8
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu0.icache_port
|
||||
mem_side=system.toL2Bus.slave[0]
|
||||
|
||||
[system.cpu0.interrupts]
|
||||
type=ArmInterrupts
|
||||
|
||||
[system.cpu0.itb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
size=64
|
||||
walker=system.cpu0.itb.walker
|
||||
|
||||
[system.cpu0.itb.walker]
|
||||
type=ArmTableWalker
|
||||
max_backoff=100000
|
||||
min_backoff=0
|
||||
sys=system
|
||||
port=system.toL2Bus.slave[2]
|
||||
|
||||
[system.cpu0.tracer]
|
||||
type=ExeTracer
|
||||
|
||||
[system.cpu1]
|
||||
type=AtomicSimpleCPU
|
||||
children=dcache dtb icache interrupts itb tracer
|
||||
checker=Null
|
||||
clock=500
|
||||
cpu_id=1
|
||||
defer_registration=false
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu1.dtb
|
||||
fastmem=false
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
interrupts=system.cpu1.interrupts
|
||||
itb=system.cpu1.itb
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
phase=0
|
||||
profile=0
|
||||
progress_interval=0
|
||||
simulate_data_stalls=false
|
||||
simulate_inst_stalls=false
|
||||
system=system
|
||||
tracer=system.cpu1.tracer
|
||||
width=1
|
||||
workload=
|
||||
dcache_port=system.cpu1.dcache.cpu_side
|
||||
icache_port=system.cpu1.icache.cpu_side
|
||||
|
||||
[system.cpu1.dcache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=4
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=32768
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=8
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu1.dcache_port
|
||||
mem_side=system.toL2Bus.slave[5]
|
||||
|
||||
[system.cpu1.dtb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
size=64
|
||||
walker=system.cpu1.dtb.walker
|
||||
|
||||
[system.cpu1.dtb.walker]
|
||||
type=ArmTableWalker
|
||||
max_backoff=100000
|
||||
min_backoff=0
|
||||
sys=system
|
||||
port=system.toL2Bus.slave[7]
|
||||
|
||||
[system.cpu1.icache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=1
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=32768
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=8
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu1.icache_port
|
||||
mem_side=system.toL2Bus.slave[4]
|
||||
|
||||
[system.cpu1.interrupts]
|
||||
type=ArmInterrupts
|
||||
|
||||
[system.cpu1.itb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
size=64
|
||||
walker=system.cpu1.itb.walker
|
||||
|
||||
[system.cpu1.itb.walker]
|
||||
type=ArmTableWalker
|
||||
max_backoff=100000
|
||||
min_backoff=0
|
||||
sys=system
|
||||
port=system.toL2Bus.slave[6]
|
||||
|
||||
[system.cpu1.tracer]
|
||||
type=ExeTracer
|
||||
|
||||
[system.intrctrl]
|
||||
type=IntrControl
|
||||
sys=system
|
||||
|
||||
[system.iobus]
|
||||
type=NoncoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side
|
||||
slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
|
||||
|
||||
[system.iocache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:268435455
|
||||
assoc=8
|
||||
block_size=64
|
||||
forward_snoops=false
|
||||
hash_delay=1
|
||||
is_top_level=false
|
||||
latency=50000
|
||||
max_miss_count=0
|
||||
mshrs=20
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=1024
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=12
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.iobus.master[25]
|
||||
mem_side=system.membus.slave[1]
|
||||
|
||||
[system.l2c]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=8
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=false
|
||||
latency=10000
|
||||
max_miss_count=0
|
||||
mshrs=92
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=4194304
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=16
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.toL2Bus.master[0]
|
||||
mem_side=system.membus.slave[2]
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
children=badaddr_responder
|
||||
block_size=64
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
default=system.membus.badaddr_responder.pio
|
||||
master=system.bridge.slave system.realview.nvmem.port[0] system.physmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio
|
||||
slave=system.system_port system.iocache.mem_side system.l2c.mem_side
|
||||
|
||||
[system.membus.badaddr_responder]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=0
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=true
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=warn
|
||||
pio=system.membus.default
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
conf_table_reported=true
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.membus.master[2]
|
||||
|
||||
[system.realview]
|
||||
type=RealView
|
||||
children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
|
||||
intrctrl=system.intrctrl
|
||||
max_mem_size=268435456
|
||||
mem_start_addr=0
|
||||
pci_cfg_base=0
|
||||
system=system
|
||||
|
||||
[system.realview.a9scu]
|
||||
type=A9SCU
|
||||
pio_addr=520093696
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.membus.master[5]
|
||||
|
||||
[system.realview.aaci_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
ignore_access=false
|
||||
pio_addr=268451840
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.iobus.master[21]
|
||||
|
||||
[system.realview.cf_ctrl]
|
||||
type=IdeController
|
||||
BAR0=402653184
|
||||
BAR0LegacyIO=true
|
||||
BAR0Size=16
|
||||
BAR1=402653440
|
||||
BAR1LegacyIO=true
|
||||
BAR1Size=1
|
||||
BAR2=1
|
||||
BAR2LegacyIO=false
|
||||
BAR2Size=8
|
||||
BAR3=1
|
||||
BAR3LegacyIO=false
|
||||
BAR3Size=4
|
||||
BAR4=1
|
||||
BAR4LegacyIO=false
|
||||
BAR4Size=16
|
||||
BAR5=1
|
||||
BAR5LegacyIO=false
|
||||
BAR5Size=0
|
||||
BIST=0
|
||||
CacheLineSize=0
|
||||
CardbusCIS=0
|
||||
ClassCode=1
|
||||
Command=1
|
||||
DeviceID=28945
|
||||
ExpansionROM=0
|
||||
HeaderType=0
|
||||
InterruptLine=31
|
||||
InterruptPin=1
|
||||
LatencyTimer=0
|
||||
MaximumLatency=0
|
||||
MinimumGrant=0
|
||||
ProgIF=133
|
||||
Revision=0
|
||||
Status=640
|
||||
SubClassCode=1
|
||||
SubsystemID=0
|
||||
SubsystemVendorID=0
|
||||
VendorID=32902
|
||||
config_latency=20000
|
||||
ctrl_offset=2
|
||||
disks=system.cf0
|
||||
io_shift=1
|
||||
max_backoff_delay=10000000
|
||||
min_backoff_delay=4000
|
||||
pci_bus=2
|
||||
pci_dev=7
|
||||
pci_func=0
|
||||
pio_latency=1000
|
||||
platform=system.realview
|
||||
system=system
|
||||
config=system.iobus.master[8]
|
||||
dma=system.iobus.slave[2]
|
||||
pio=system.iobus.master[7]
|
||||
|
||||
[system.realview.clcd]
|
||||
type=Pl111
|
||||
amba_id=1315089
|
||||
clock=41667
|
||||
gic=system.realview.gic
|
||||
int_num=55
|
||||
max_backoff_delay=10000000
|
||||
min_backoff_delay=4000
|
||||
pio_addr=268566528
|
||||
pio_latency=10000
|
||||
system=system
|
||||
vnc=system.vncserver
|
||||
dma=system.iobus.slave[1]
|
||||
pio=system.iobus.master[4]
|
||||
|
||||
[system.realview.dmac_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
ignore_access=false
|
||||
pio_addr=268632064
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.iobus.master[9]
|
||||
|
||||
[system.realview.flash_fake]
|
||||
type=IsaFake
|
||||
fake_mem=true
|
||||
pio_addr=1073741824
|
||||
pio_latency=1000
|
||||
pio_size=536870912
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[24]
|
||||
|
||||
[system.realview.gic]
|
||||
type=Gic
|
||||
cpu_addr=520093952
|
||||
cpu_pio_delay=10000
|
||||
dist_addr=520097792
|
||||
dist_pio_delay=10000
|
||||
int_latency=10000
|
||||
it_lines=128
|
||||
platform=system.realview
|
||||
system=system
|
||||
pio=system.membus.master[3]
|
||||
|
||||
[system.realview.gpio0_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
ignore_access=false
|
||||
pio_addr=268513280
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.iobus.master[16]
|
||||
|
||||
[system.realview.gpio1_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
ignore_access=false
|
||||
pio_addr=268517376
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.iobus.master[17]
|
||||
|
||||
[system.realview.gpio2_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
ignore_access=false
|
||||
pio_addr=268521472
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.iobus.master[18]
|
||||
|
||||
[system.realview.kmi0]
|
||||
type=Pl050
|
||||
amba_id=1314896
|
||||
gic=system.realview.gic
|
||||
int_delay=1000000
|
||||
int_num=52
|
||||
is_mouse=false
|
||||
pio_addr=268460032
|
||||
pio_latency=1000
|
||||
system=system
|
||||
vnc=system.vncserver
|
||||
pio=system.iobus.master[5]
|
||||
|
||||
[system.realview.kmi1]
|
||||
type=Pl050
|
||||
amba_id=1314896
|
||||
gic=system.realview.gic
|
||||
int_delay=1000000
|
||||
int_num=53
|
||||
is_mouse=true
|
||||
pio_addr=268464128
|
||||
pio_latency=1000
|
||||
system=system
|
||||
vnc=system.vncserver
|
||||
pio=system.iobus.master[6]
|
||||
|
||||
[system.realview.l2x0_fake]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=520101888
|
||||
pio_latency=1000
|
||||
pio_size=4095
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.membus.master[4]
|
||||
|
||||
[system.realview.local_cpu_timer]
|
||||
type=CpuLocalTimer
|
||||
clock=1000
|
||||
gic=system.realview.gic
|
||||
int_num_timer=29
|
||||
int_num_watchdog=30
|
||||
pio_addr=520095232
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.membus.master[6]
|
||||
|
||||
[system.realview.mmc_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
ignore_access=false
|
||||
pio_addr=268455936
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.iobus.master[22]
|
||||
|
||||
[system.realview.nvmem]
|
||||
type=SimpleMemory
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
range=2147483648:2214592511
|
||||
zero=true
|
||||
port=system.membus.master[1]
|
||||
|
||||
[system.realview.realview_io]
|
||||
type=RealViewCtrl
|
||||
idreg=0
|
||||
pio_addr=268435456
|
||||
pio_latency=1000
|
||||
proc_id0=201326592
|
||||
proc_id1=201327138
|
||||
system=system
|
||||
pio=system.iobus.master[1]
|
||||
|
||||
[system.realview.rtc]
|
||||
type=PL031
|
||||
amba_id=3412017
|
||||
gic=system.realview.gic
|
||||
int_delay=100000
|
||||
int_num=42
|
||||
pio_addr=268529664
|
||||
pio_latency=1000
|
||||
system=system
|
||||
time=Thu Jan 1 00:00:00 2009
|
||||
pio=system.iobus.master[23]
|
||||
|
||||
[system.realview.sci_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
ignore_access=false
|
||||
pio_addr=268492800
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.iobus.master[20]
|
||||
|
||||
[system.realview.smc_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
ignore_access=false
|
||||
pio_addr=269357056
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.iobus.master[13]
|
||||
|
||||
[system.realview.sp810_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
ignore_access=true
|
||||
pio_addr=268439552
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.iobus.master[14]
|
||||
|
||||
[system.realview.ssp_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
ignore_access=false
|
||||
pio_addr=268488704
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.iobus.master[19]
|
||||
|
||||
[system.realview.timer0]
|
||||
type=Sp804
|
||||
amba_id=1316868
|
||||
clock0=1000000
|
||||
clock1=1000000
|
||||
gic=system.realview.gic
|
||||
int_num0=36
|
||||
int_num1=36
|
||||
pio_addr=268505088
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.iobus.master[2]
|
||||
|
||||
[system.realview.timer1]
|
||||
type=Sp804
|
||||
amba_id=1316868
|
||||
clock0=1000000
|
||||
clock1=1000000
|
||||
gic=system.realview.gic
|
||||
int_num0=37
|
||||
int_num1=37
|
||||
pio_addr=268509184
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.iobus.master[3]
|
||||
|
||||
[system.realview.uart]
|
||||
type=Pl011
|
||||
end_on_eot=false
|
||||
gic=system.realview.gic
|
||||
int_delay=100000
|
||||
int_num=44
|
||||
pio_addr=268472320
|
||||
pio_latency=1000
|
||||
platform=system.realview
|
||||
system=system
|
||||
terminal=system.terminal
|
||||
pio=system.iobus.master[0]
|
||||
|
||||
[system.realview.uart1_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
ignore_access=false
|
||||
pio_addr=268476416
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.iobus.master[10]
|
||||
|
||||
[system.realview.uart2_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
ignore_access=false
|
||||
pio_addr=268480512
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.iobus.master[11]
|
||||
|
||||
[system.realview.uart3_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
ignore_access=false
|
||||
pio_addr=268484608
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.iobus.master[12]
|
||||
|
||||
[system.realview.watchdog_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
ignore_access=false
|
||||
pio_addr=268500992
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.iobus.master[15]
|
||||
|
||||
[system.terminal]
|
||||
type=Terminal
|
||||
intr_control=system.intrctrl
|
||||
number=0
|
||||
output=true
|
||||
port=3456
|
||||
|
||||
[system.toL2Bus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
master=system.l2c.cpu_side
|
||||
slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port
|
||||
|
||||
[system.vncserver]
|
||||
type=VncServer
|
||||
frame_capture=false
|
||||
number=0
|
||||
port=5900
|
||||
|
||||
@ -0,0 +1,18 @@
|
||||
warn: Sockets disabled, not accepting vnc client connections
|
||||
warn: Sockets disabled, not accepting terminal connections
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: The clidr register always reports 0 caches.
|
||||
warn: clidr LoUIS field of 0b001 to match current ARM implementations.
|
||||
warn: The csselr register isn't implemented.
|
||||
warn: The ccsidr register isn't implemented and always reads as 0.
|
||||
warn: instruction 'mcr bpiallis' unimplemented
|
||||
warn: instruction 'mcr icialluis' unimplemented
|
||||
warn: instruction 'mcr dccimvac' unimplemented
|
||||
warn: instruction 'mcr dccmvau' unimplemented
|
||||
warn: instruction 'mcr icimvau' unimplemented
|
||||
warn: instruction 'mcr bpiallis' unimplemented
|
||||
warn: LCD dual screen mode not supported
|
||||
warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
|
||||
warn: instruction 'mcr icialluis' unimplemented
|
||||
warn: instruction 'mcr icialluis' unimplemented
|
||||
hack: be nice to actually delete the event here
|
||||
@ -0,0 +1,12 @@
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jun 4 2012 12:14:06
|
||||
gem5 started Jun 4 2012 17:25:17
|
||||
gem5 executing on zizzer
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
|
||||
info: Using bootloader at address 0x80000000
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 911653589000 because m5_exit instruction encountered
|
||||
@ -0,0 +1,653 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.911654 # Number of seconds simulated
|
||||
sim_ticks 911653589000 # Number of ticks simulated
|
||||
final_tick 911653589000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1520101 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1964640 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 22862175544 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 382804 # Number of bytes of host memory used
|
||||
host_seconds 39.88 # Real time elapsed on the host
|
||||
sim_insts 60615585 # Number of instructions simulated
|
||||
sim_ops 78342060 # Number of ops (including micro ops) simulated
|
||||
system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
|
||||
system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory
|
||||
system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory
|
||||
system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
|
||||
system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory
|
||||
system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory
|
||||
system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory
|
||||
system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory
|
||||
system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory
|
||||
system.realview.nvmem.bw_read::cpu0.inst 22 # Total read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_read::cpu1.inst 53 # Total read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_read::total 75 # Total read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_inst_read::cpu0.inst 22 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_inst_read::cpu1.inst 53 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_inst_read::total 75 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_total::cpu0.inst 22 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_total::cpu1.inst 53 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_total::total 75 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bytes_read::realview.clcd 39321600 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu0.dtb.walker 768 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu0.itb.walker 512 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu0.inst 661924 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu0.data 6760756 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu1.dtb.walker 1024 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu1.itb.walker 1152 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu1.inst 341852 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu1.data 3873968 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 50963556 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu0.inst 661924 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu1.inst 341852 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 1003776 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 7197696 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::cpu1.data 3010088 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 10224784 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::realview.clcd 4915200 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu0.dtb.walker 12 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu0.itb.walker 8 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu0.inst 16561 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu0.data 105709 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu1.dtb.walker 16 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu1.itb.walker 18 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu1.inst 5423 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu1.data 60557 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 5103504 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 112464 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::cpu1.data 752522 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 869236 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::realview.clcd 43132173 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu0.dtb.walker 842 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu0.itb.walker 562 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu0.inst 726070 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu0.data 7415926 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu1.dtb.walker 1123 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu1.itb.walker 1264 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu1.inst 374980 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu1.data 4249386 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 55902326 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu0.inst 726070 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu1.inst 374980 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 1101050 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 7895209 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::cpu0.data 18647 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::cpu1.data 3301789 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 11215646 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 7895209 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::realview.clcd 43132173 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu0.dtb.walker 842 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu0.itb.walker 562 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu0.inst 726070 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu0.data 7434574 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu1.dtb.walker 1123 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu1.itb.walker 1264 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu1.inst 374980 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu1.data 7551175 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 67117972 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.l2c.replacements 127935 # number of replacements
|
||||
system.l2c.tagsinuse 26245.835103 # Cycle average of tags in use
|
||||
system.l2c.total_refs 1477463 # Total number of references to valid blocks.
|
||||
system.l2c.sampled_refs 156884 # Sample count of references to valid blocks.
|
||||
system.l2c.avg_refs 9.417551 # Average number of references to valid blocks.
|
||||
system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.l2c.occ_blocks::writebacks 16687.001530 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu0.dtb.walker 1.397314 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu0.itb.walker 0.122168 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu0.inst 2780.380300 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu0.data 1123.317941 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu1.dtb.walker 4.426009 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu1.itb.walker 0.092136 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu1.inst 1942.464102 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu1.data 3706.633603 # Average occupied blocks per requestor
|
||||
system.l2c.occ_percent::writebacks 0.254623 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu0.dtb.walker 0.000021 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu0.itb.walker 0.000002 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu0.inst 0.042425 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu0.data 0.017140 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu1.dtb.walker 0.000068 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu1.itb.walker 0.000001 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu1.inst 0.029640 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu1.data 0.056559 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::total 0.400480 # Average percentage of cache occupancy
|
||||
system.l2c.ReadReq_hits::cpu0.dtb.walker 5294 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu0.itb.walker 2199 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu0.inst 485527 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu0.data 213776 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu1.dtb.walker 4291 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu1.itb.walker 1552 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu1.inst 359854 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu1.data 128180 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::total 1200673 # number of ReadReq hits
|
||||
system.l2c.Writeback_hits::writebacks 578200 # number of Writeback hits
|
||||
system.l2c.Writeback_hits::total 578200 # number of Writeback hits
|
||||
system.l2c.UpgradeReq_hits::cpu0.data 835 # number of UpgradeReq hits
|
||||
system.l2c.UpgradeReq_hits::cpu1.data 757 # number of UpgradeReq hits
|
||||
system.l2c.UpgradeReq_hits::total 1592 # number of UpgradeReq hits
|
||||
system.l2c.SCUpgradeReq_hits::cpu0.data 134 # number of SCUpgradeReq hits
|
||||
system.l2c.SCUpgradeReq_hits::cpu1.data 214 # number of SCUpgradeReq hits
|
||||
system.l2c.SCUpgradeReq_hits::total 348 # number of SCUpgradeReq hits
|
||||
system.l2c.ReadExReq_hits::cpu0.data 68011 # number of ReadExReq hits
|
||||
system.l2c.ReadExReq_hits::cpu1.data 33233 # number of ReadExReq hits
|
||||
system.l2c.ReadExReq_hits::total 101244 # number of ReadExReq hits
|
||||
system.l2c.demand_hits::cpu0.dtb.walker 5294 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu0.itb.walker 2199 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu0.inst 485527 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu0.data 281787 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu1.dtb.walker 4291 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu1.itb.walker 1552 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu1.inst 359854 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu1.data 161413 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::total 1301917 # number of demand (read+write) hits
|
||||
system.l2c.overall_hits::cpu0.dtb.walker 5294 # number of overall hits
|
||||
system.l2c.overall_hits::cpu0.itb.walker 2199 # number of overall hits
|
||||
system.l2c.overall_hits::cpu0.inst 485527 # number of overall hits
|
||||
system.l2c.overall_hits::cpu0.data 281787 # number of overall hits
|
||||
system.l2c.overall_hits::cpu1.dtb.walker 4291 # number of overall hits
|
||||
system.l2c.overall_hits::cpu1.itb.walker 1552 # number of overall hits
|
||||
system.l2c.overall_hits::cpu1.inst 359854 # number of overall hits
|
||||
system.l2c.overall_hits::cpu1.data 161413 # number of overall hits
|
||||
system.l2c.overall_hits::total 1301917 # number of overall hits
|
||||
system.l2c.ReadReq_misses::cpu0.dtb.walker 12 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu0.itb.walker 8 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu0.inst 9928 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu0.data 9109 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu1.dtb.walker 16 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu1.itb.walker 18 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu1.inst 5336 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu1.data 10106 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::total 34533 # number of ReadReq misses
|
||||
system.l2c.UpgradeReq_misses::cpu0.data 6262 # number of UpgradeReq misses
|
||||
system.l2c.UpgradeReq_misses::cpu1.data 3142 # number of UpgradeReq misses
|
||||
system.l2c.UpgradeReq_misses::total 9404 # number of UpgradeReq misses
|
||||
system.l2c.SCUpgradeReq_misses::cpu0.data 731 # number of SCUpgradeReq misses
|
||||
system.l2c.SCUpgradeReq_misses::cpu1.data 408 # number of SCUpgradeReq misses
|
||||
system.l2c.SCUpgradeReq_misses::total 1139 # number of SCUpgradeReq misses
|
||||
system.l2c.ReadExReq_misses::cpu0.data 98092 # number of ReadExReq misses
|
||||
system.l2c.ReadExReq_misses::cpu1.data 50861 # number of ReadExReq misses
|
||||
system.l2c.ReadExReq_misses::total 148953 # number of ReadExReq misses
|
||||
system.l2c.demand_misses::cpu0.dtb.walker 12 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu0.itb.walker 8 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu0.inst 9928 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu0.data 107201 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu1.dtb.walker 16 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu1.itb.walker 18 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu1.inst 5336 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu1.data 60967 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::total 183486 # number of demand (read+write) misses
|
||||
system.l2c.overall_misses::cpu0.dtb.walker 12 # number of overall misses
|
||||
system.l2c.overall_misses::cpu0.itb.walker 8 # number of overall misses
|
||||
system.l2c.overall_misses::cpu0.inst 9928 # number of overall misses
|
||||
system.l2c.overall_misses::cpu0.data 107201 # number of overall misses
|
||||
system.l2c.overall_misses::cpu1.dtb.walker 16 # number of overall misses
|
||||
system.l2c.overall_misses::cpu1.itb.walker 18 # number of overall misses
|
||||
system.l2c.overall_misses::cpu1.inst 5336 # number of overall misses
|
||||
system.l2c.overall_misses::cpu1.data 60967 # number of overall misses
|
||||
system.l2c.overall_misses::total 183486 # number of overall misses
|
||||
system.l2c.ReadReq_accesses::cpu0.dtb.walker 5306 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::cpu0.itb.walker 2207 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::cpu0.inst 495455 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::cpu0.data 222885 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::cpu1.dtb.walker 4307 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::cpu1.itb.walker 1570 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::cpu1.inst 365190 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::cpu1.data 138286 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::total 1235206 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.Writeback_accesses::writebacks 578200 # number of Writeback accesses(hits+misses)
|
||||
system.l2c.Writeback_accesses::total 578200 # number of Writeback accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_accesses::cpu0.data 7097 # number of UpgradeReq accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_accesses::cpu1.data 3899 # number of UpgradeReq accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_accesses::total 10996 # number of UpgradeReq accesses(hits+misses)
|
||||
system.l2c.SCUpgradeReq_accesses::cpu0.data 865 # number of SCUpgradeReq accesses(hits+misses)
|
||||
system.l2c.SCUpgradeReq_accesses::cpu1.data 622 # number of SCUpgradeReq accesses(hits+misses)
|
||||
system.l2c.SCUpgradeReq_accesses::total 1487 # number of SCUpgradeReq accesses(hits+misses)
|
||||
system.l2c.ReadExReq_accesses::cpu0.data 166103 # number of ReadExReq accesses(hits+misses)
|
||||
system.l2c.ReadExReq_accesses::cpu1.data 84094 # number of ReadExReq accesses(hits+misses)
|
||||
system.l2c.ReadExReq_accesses::total 250197 # number of ReadExReq accesses(hits+misses)
|
||||
system.l2c.demand_accesses::cpu0.dtb.walker 5306 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu0.itb.walker 2207 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu0.inst 495455 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu0.data 388988 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu1.dtb.walker 4307 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu1.itb.walker 1570 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu1.inst 365190 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu1.data 222380 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::total 1485403 # number of demand (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu0.dtb.walker 5306 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu0.itb.walker 2207 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu0.inst 495455 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu0.data 388988 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu1.dtb.walker 4307 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu1.itb.walker 1570 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu1.inst 365190 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu1.data 222380 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::total 1485403 # number of overall (read+write) accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.002262 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.003625 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu0.inst 0.020038 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu0.data 0.040869 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.003715 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.011465 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu1.inst 0.014612 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu1.data 0.073080 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::total 0.027957 # miss rate for ReadReq accesses
|
||||
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.882345 # miss rate for UpgradeReq accesses
|
||||
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.805848 # miss rate for UpgradeReq accesses
|
||||
system.l2c.UpgradeReq_miss_rate::total 0.855220 # miss rate for UpgradeReq accesses
|
||||
system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.845087 # miss rate for SCUpgradeReq accesses
|
||||
system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.655949 # miss rate for SCUpgradeReq accesses
|
||||
system.l2c.SCUpgradeReq_miss_rate::total 0.765972 # miss rate for SCUpgradeReq accesses
|
||||
system.l2c.ReadExReq_miss_rate::cpu0.data 0.590549 # miss rate for ReadExReq accesses
|
||||
system.l2c.ReadExReq_miss_rate::cpu1.data 0.604811 # miss rate for ReadExReq accesses
|
||||
system.l2c.ReadExReq_miss_rate::total 0.595343 # miss rate for ReadExReq accesses
|
||||
system.l2c.demand_miss_rate::cpu0.dtb.walker 0.002262 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu0.itb.walker 0.003625 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu0.inst 0.020038 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu0.data 0.275589 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu1.dtb.walker 0.003715 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu1.itb.walker 0.011465 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu1.inst 0.014612 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu1.data 0.274157 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::total 0.123526 # miss rate for demand accesses
|
||||
system.l2c.overall_miss_rate::cpu0.dtb.walker 0.002262 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu0.itb.walker 0.003625 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu0.inst 0.020038 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu0.data 0.275589 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu1.dtb.walker 0.003715 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu1.itb.walker 0.011465 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu1.inst 0.014612 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu1.data 0.274157 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::total 0.123526 # miss rate for overall accesses
|
||||
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.l2c.fast_writes 0 # number of fast writes performed
|
||||
system.l2c.cache_copies 0 # number of cache copies performed
|
||||
system.l2c.writebacks::writebacks 112464 # number of writebacks
|
||||
system.l2c.writebacks::total 112464 # number of writebacks
|
||||
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
||||
system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
|
||||
system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
|
||||
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
|
||||
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
|
||||
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
|
||||
system.cpu0.dtb.inst_hits 0 # ITB inst hits
|
||||
system.cpu0.dtb.inst_misses 0 # ITB inst misses
|
||||
system.cpu0.dtb.read_hits 9312139 # DTB read hits
|
||||
system.cpu0.dtb.read_misses 5476 # DTB read misses
|
||||
system.cpu0.dtb.write_hits 6895585 # DTB write hits
|
||||
system.cpu0.dtb.write_misses 1137 # DTB write misses
|
||||
system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed
|
||||
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
|
||||
system.cpu0.dtb.flush_entries 2449 # Number of entries that have been flushed from TLB
|
||||
system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu0.dtb.prefetch_faults 187 # Number of TLB faults due to prefetch
|
||||
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu0.dtb.perms_faults 267 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu0.dtb.read_accesses 9317615 # DTB read accesses
|
||||
system.cpu0.dtb.write_accesses 6896722 # DTB write accesses
|
||||
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
|
||||
system.cpu0.dtb.hits 16207724 # DTB hits
|
||||
system.cpu0.dtb.misses 6613 # DTB misses
|
||||
system.cpu0.dtb.accesses 16214337 # DTB accesses
|
||||
system.cpu0.itb.inst_hits 34683994 # ITB inst hits
|
||||
system.cpu0.itb.inst_misses 3170 # ITB inst misses
|
||||
system.cpu0.itb.read_hits 0 # DTB read hits
|
||||
system.cpu0.itb.read_misses 0 # DTB read misses
|
||||
system.cpu0.itb.write_hits 0 # DTB write hits
|
||||
system.cpu0.itb.write_misses 0 # DTB write misses
|
||||
system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed
|
||||
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
|
||||
system.cpu0.itb.flush_entries 1558 # Number of entries that have been flushed from TLB
|
||||
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu0.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu0.itb.write_accesses 0 # DTB write accesses
|
||||
system.cpu0.itb.inst_accesses 34687164 # ITB inst accesses
|
||||
system.cpu0.itb.hits 34683994 # DTB hits
|
||||
system.cpu0.itb.misses 3170 # DTB misses
|
||||
system.cpu0.itb.accesses 34687164 # DTB accesses
|
||||
system.cpu0.numCycles 1823259919 # number of cpu cycles simulated
|
||||
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu0.committedInsts 33900598 # Number of instructions committed
|
||||
system.cpu0.committedOps 44786074 # Number of ops (including micro ops) committed
|
||||
system.cpu0.num_int_alu_accesses 39685287 # Number of integer alu accesses
|
||||
system.cpu0.num_fp_alu_accesses 5074 # Number of float alu accesses
|
||||
system.cpu0.num_func_calls 1296918 # number of times a function call or return occured
|
||||
system.cpu0.num_conditional_control_insts 4494112 # number of instructions that are conditional controls
|
||||
system.cpu0.num_int_insts 39685287 # number of integer instructions
|
||||
system.cpu0.num_fp_insts 5074 # number of float instructions
|
||||
system.cpu0.num_int_register_reads 201262894 # number of times the integer registers were read
|
||||
system.cpu0.num_int_register_writes 42034263 # number of times the integer registers were written
|
||||
system.cpu0.num_fp_register_reads 3706 # number of times the floating registers were read
|
||||
system.cpu0.num_fp_register_writes 1372 # number of times the floating registers were written
|
||||
system.cpu0.num_mem_refs 16978573 # number of memory refs
|
||||
system.cpu0.num_load_insts 9760184 # Number of load instructions
|
||||
system.cpu0.num_store_insts 7218389 # Number of store instructions
|
||||
system.cpu0.num_idle_cycles 1777623684.411826 # Number of idle cycles
|
||||
system.cpu0.num_busy_cycles 45636234.588174 # Number of busy cycles
|
||||
system.cpu0.not_idle_fraction 0.025030 # Percentage of non-idle cycles
|
||||
system.cpu0.idle_fraction 0.974970 # Percentage of idle cycles
|
||||
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
|
||||
system.cpu0.kern.inst.quiesce 58955 # number of quiesce instructions executed
|
||||
system.cpu0.icache.replacements 497177 # number of replacements
|
||||
system.cpu0.icache.tagsinuse 511.014795 # Cycle average of tags in use
|
||||
system.cpu0.icache.total_refs 34187980 # Total number of references to valid blocks.
|
||||
system.cpu0.icache.sampled_refs 497689 # Sample count of references to valid blocks.
|
||||
system.cpu0.icache.avg_refs 68.693461 # Average number of references to valid blocks.
|
||||
system.cpu0.icache.warmup_cycle 64536851000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu0.icache.occ_blocks::cpu0.inst 511.014795 # Average occupied blocks per requestor
|
||||
system.cpu0.icache.occ_percent::cpu0.inst 0.998076 # Average percentage of cache occupancy
|
||||
system.cpu0.icache.occ_percent::total 0.998076 # Average percentage of cache occupancy
|
||||
system.cpu0.icache.ReadReq_hits::cpu0.inst 34187980 # number of ReadReq hits
|
||||
system.cpu0.icache.ReadReq_hits::total 34187980 # number of ReadReq hits
|
||||
system.cpu0.icache.demand_hits::cpu0.inst 34187980 # number of demand (read+write) hits
|
||||
system.cpu0.icache.demand_hits::total 34187980 # number of demand (read+write) hits
|
||||
system.cpu0.icache.overall_hits::cpu0.inst 34187980 # number of overall hits
|
||||
system.cpu0.icache.overall_hits::total 34187980 # number of overall hits
|
||||
system.cpu0.icache.ReadReq_misses::cpu0.inst 497690 # number of ReadReq misses
|
||||
system.cpu0.icache.ReadReq_misses::total 497690 # number of ReadReq misses
|
||||
system.cpu0.icache.demand_misses::cpu0.inst 497690 # number of demand (read+write) misses
|
||||
system.cpu0.icache.demand_misses::total 497690 # number of demand (read+write) misses
|
||||
system.cpu0.icache.overall_misses::cpu0.inst 497690 # number of overall misses
|
||||
system.cpu0.icache.overall_misses::total 497690 # number of overall misses
|
||||
system.cpu0.icache.ReadReq_accesses::cpu0.inst 34685670 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu0.icache.ReadReq_accesses::total 34685670 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu0.icache.demand_accesses::cpu0.inst 34685670 # number of demand (read+write) accesses
|
||||
system.cpu0.icache.demand_accesses::total 34685670 # number of demand (read+write) accesses
|
||||
system.cpu0.icache.overall_accesses::cpu0.inst 34685670 # number of overall (read+write) accesses
|
||||
system.cpu0.icache.overall_accesses::total 34685670 # number of overall (read+write) accesses
|
||||
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014349 # miss rate for ReadReq accesses
|
||||
system.cpu0.icache.ReadReq_miss_rate::total 0.014349 # miss rate for ReadReq accesses
|
||||
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014349 # miss rate for demand accesses
|
||||
system.cpu0.icache.demand_miss_rate::total 0.014349 # miss rate for demand accesses
|
||||
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014349 # miss rate for overall accesses
|
||||
system.cpu0.icache.overall_miss_rate::total 0.014349 # miss rate for overall accesses
|
||||
system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu0.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu0.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu0.icache.writebacks::writebacks 26062 # number of writebacks
|
||||
system.cpu0.icache.writebacks::total 26062 # number of writebacks
|
||||
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu0.dcache.replacements 385595 # number of replacements
|
||||
system.cpu0.dcache.tagsinuse 475.569441 # Cycle average of tags in use
|
||||
system.cpu0.dcache.total_refs 14667576 # Total number of references to valid blocks.
|
||||
system.cpu0.dcache.sampled_refs 386107 # Sample count of references to valid blocks.
|
||||
system.cpu0.dcache.avg_refs 37.988371 # Average number of references to valid blocks.
|
||||
system.cpu0.dcache.warmup_cycle 22115000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu0.dcache.occ_blocks::cpu0.data 475.569441 # Average occupied blocks per requestor
|
||||
system.cpu0.dcache.occ_percent::cpu0.data 0.928847 # Average percentage of cache occupancy
|
||||
system.cpu0.dcache.occ_percent::total 0.928847 # Average percentage of cache occupancy
|
||||
system.cpu0.dcache.ReadReq_hits::cpu0.data 7775792 # number of ReadReq hits
|
||||
system.cpu0.dcache.ReadReq_hits::total 7775792 # number of ReadReq hits
|
||||
system.cpu0.dcache.WriteReq_hits::cpu0.data 6519223 # number of WriteReq hits
|
||||
system.cpu0.dcache.WriteReq_hits::total 6519223 # number of WriteReq hits
|
||||
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 172927 # number of LoadLockedReq hits
|
||||
system.cpu0.dcache.LoadLockedReq_hits::total 172927 # number of LoadLockedReq hits
|
||||
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 175483 # number of StoreCondReq hits
|
||||
system.cpu0.dcache.StoreCondReq_hits::total 175483 # number of StoreCondReq hits
|
||||
system.cpu0.dcache.demand_hits::cpu0.data 14295015 # number of demand (read+write) hits
|
||||
system.cpu0.dcache.demand_hits::total 14295015 # number of demand (read+write) hits
|
||||
system.cpu0.dcache.overall_hits::cpu0.data 14295015 # number of overall hits
|
||||
system.cpu0.dcache.overall_hits::total 14295015 # number of overall hits
|
||||
system.cpu0.dcache.ReadReq_misses::cpu0.data 240570 # number of ReadReq misses
|
||||
system.cpu0.dcache.ReadReq_misses::total 240570 # number of ReadReq misses
|
||||
system.cpu0.dcache.WriteReq_misses::cpu0.data 186007 # number of WriteReq misses
|
||||
system.cpu0.dcache.WriteReq_misses::total 186007 # number of WriteReq misses
|
||||
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9987 # number of LoadLockedReq misses
|
||||
system.cpu0.dcache.LoadLockedReq_misses::total 9987 # number of LoadLockedReq misses
|
||||
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7377 # number of StoreCondReq misses
|
||||
system.cpu0.dcache.StoreCondReq_misses::total 7377 # number of StoreCondReq misses
|
||||
system.cpu0.dcache.demand_misses::cpu0.data 426577 # number of demand (read+write) misses
|
||||
system.cpu0.dcache.demand_misses::total 426577 # number of demand (read+write) misses
|
||||
system.cpu0.dcache.overall_misses::cpu0.data 426577 # number of overall misses
|
||||
system.cpu0.dcache.overall_misses::total 426577 # number of overall misses
|
||||
system.cpu0.dcache.ReadReq_accesses::cpu0.data 8016362 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu0.dcache.ReadReq_accesses::total 8016362 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu0.dcache.WriteReq_accesses::cpu0.data 6705230 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu0.dcache.WriteReq_accesses::total 6705230 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 182914 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu0.dcache.LoadLockedReq_accesses::total 182914 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 182860 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu0.dcache.StoreCondReq_accesses::total 182860 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu0.dcache.demand_accesses::cpu0.data 14721592 # number of demand (read+write) accesses
|
||||
system.cpu0.dcache.demand_accesses::total 14721592 # number of demand (read+write) accesses
|
||||
system.cpu0.dcache.overall_accesses::cpu0.data 14721592 # number of overall (read+write) accesses
|
||||
system.cpu0.dcache.overall_accesses::total 14721592 # number of overall (read+write) accesses
|
||||
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.030010 # miss rate for ReadReq accesses
|
||||
system.cpu0.dcache.ReadReq_miss_rate::total 0.030010 # miss rate for ReadReq accesses
|
||||
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.027741 # miss rate for WriteReq accesses
|
||||
system.cpu0.dcache.WriteReq_miss_rate::total 0.027741 # miss rate for WriteReq accesses
|
||||
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.054599 # miss rate for LoadLockedReq accesses
|
||||
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.054599 # miss rate for LoadLockedReq accesses
|
||||
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.040342 # miss rate for StoreCondReq accesses
|
||||
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.040342 # miss rate for StoreCondReq accesses
|
||||
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.028976 # miss rate for demand accesses
|
||||
system.cpu0.dcache.demand_miss_rate::total 0.028976 # miss rate for demand accesses
|
||||
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.028976 # miss rate for overall accesses
|
||||
system.cpu0.dcache.overall_miss_rate::total 0.028976 # miss rate for overall accesses
|
||||
system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu0.dcache.writebacks::writebacks 342703 # number of writebacks
|
||||
system.cpu0.dcache.writebacks::total 342703 # number of writebacks
|
||||
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu1.dtb.inst_hits 0 # ITB inst hits
|
||||
system.cpu1.dtb.inst_misses 0 # ITB inst misses
|
||||
system.cpu1.dtb.read_hits 6036043 # DTB read hits
|
||||
system.cpu1.dtb.read_misses 1895 # DTB read misses
|
||||
system.cpu1.dtb.write_hits 4565126 # DTB write hits
|
||||
system.cpu1.dtb.write_misses 1147 # DTB write misses
|
||||
system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed
|
||||
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
|
||||
system.cpu1.dtb.flush_entries 1364 # Number of entries that have been flushed from TLB
|
||||
system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu1.dtb.prefetch_faults 95 # Number of TLB faults due to prefetch
|
||||
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu1.dtb.perms_faults 185 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu1.dtb.read_accesses 6037938 # DTB read accesses
|
||||
system.cpu1.dtb.write_accesses 4566273 # DTB write accesses
|
||||
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
|
||||
system.cpu1.dtb.hits 10601169 # DTB hits
|
||||
system.cpu1.dtb.misses 3042 # DTB misses
|
||||
system.cpu1.dtb.accesses 10604211 # DTB accesses
|
||||
system.cpu1.itb.inst_hits 26944447 # ITB inst hits
|
||||
system.cpu1.itb.inst_misses 1203 # ITB inst misses
|
||||
system.cpu1.itb.read_hits 0 # DTB read hits
|
||||
system.cpu1.itb.read_misses 0 # DTB read misses
|
||||
system.cpu1.itb.write_hits 0 # DTB write hits
|
||||
system.cpu1.itb.write_misses 0 # DTB write misses
|
||||
system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed
|
||||
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
|
||||
system.cpu1.itb.flush_entries 1228 # Number of entries that have been flushed from TLB
|
||||
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu1.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu1.itb.write_accesses 0 # DTB write accesses
|
||||
system.cpu1.itb.inst_accesses 26945650 # ITB inst accesses
|
||||
system.cpu1.itb.hits 26944447 # DTB hits
|
||||
system.cpu1.itb.misses 1203 # DTB misses
|
||||
system.cpu1.itb.accesses 26945650 # DTB accesses
|
||||
system.cpu1.numCycles 1822760078 # number of cpu cycles simulated
|
||||
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu1.committedInsts 26714987 # Number of instructions committed
|
||||
system.cpu1.committedOps 33555986 # Number of ops (including micro ops) committed
|
||||
system.cpu1.num_int_alu_accesses 30087808 # Number of integer alu accesses
|
||||
system.cpu1.num_fp_alu_accesses 5643 # Number of float alu accesses
|
||||
system.cpu1.num_func_calls 723750 # number of times a function call or return occured
|
||||
system.cpu1.num_conditional_control_insts 3301562 # number of instructions that are conditional controls
|
||||
system.cpu1.num_int_insts 30087808 # number of integer instructions
|
||||
system.cpu1.num_fp_insts 5643 # number of float instructions
|
||||
system.cpu1.num_int_register_reads 152234781 # number of times the integer registers were read
|
||||
system.cpu1.num_int_register_writes 32495677 # number of times the integer registers were written
|
||||
system.cpu1.num_fp_register_reads 3915 # number of times the floating registers were read
|
||||
system.cpu1.num_fp_register_writes 1728 # number of times the floating registers were written
|
||||
system.cpu1.num_mem_refs 11031013 # number of memory refs
|
||||
system.cpu1.num_load_insts 6247466 # Number of load instructions
|
||||
system.cpu1.num_store_insts 4783547 # Number of store instructions
|
||||
system.cpu1.num_idle_cycles 1788952556.347001 # Number of idle cycles
|
||||
system.cpu1.num_busy_cycles 33807521.652999 # Number of busy cycles
|
||||
system.cpu1.not_idle_fraction 0.018547 # Percentage of non-idle cycles
|
||||
system.cpu1.idle_fraction 0.981453 # Percentage of idle cycles
|
||||
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
|
||||
system.cpu1.kern.inst.quiesce 31471 # number of quiesce instructions executed
|
||||
system.cpu1.icache.replacements 365832 # number of replacements
|
||||
system.cpu1.icache.tagsinuse 475.430525 # Cycle average of tags in use
|
||||
system.cpu1.icache.total_refs 26579068 # Total number of references to valid blocks.
|
||||
system.cpu1.icache.sampled_refs 366344 # Sample count of references to valid blocks.
|
||||
system.cpu1.icache.avg_refs 72.552213 # Average number of references to valid blocks.
|
||||
system.cpu1.icache.warmup_cycle 69967043000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu1.icache.occ_blocks::cpu1.inst 475.430525 # Average occupied blocks per requestor
|
||||
system.cpu1.icache.occ_percent::cpu1.inst 0.928575 # Average percentage of cache occupancy
|
||||
system.cpu1.icache.occ_percent::total 0.928575 # Average percentage of cache occupancy
|
||||
system.cpu1.icache.ReadReq_hits::cpu1.inst 26579068 # number of ReadReq hits
|
||||
system.cpu1.icache.ReadReq_hits::total 26579068 # number of ReadReq hits
|
||||
system.cpu1.icache.demand_hits::cpu1.inst 26579068 # number of demand (read+write) hits
|
||||
system.cpu1.icache.demand_hits::total 26579068 # number of demand (read+write) hits
|
||||
system.cpu1.icache.overall_hits::cpu1.inst 26579068 # number of overall hits
|
||||
system.cpu1.icache.overall_hits::total 26579068 # number of overall hits
|
||||
system.cpu1.icache.ReadReq_misses::cpu1.inst 366344 # number of ReadReq misses
|
||||
system.cpu1.icache.ReadReq_misses::total 366344 # number of ReadReq misses
|
||||
system.cpu1.icache.demand_misses::cpu1.inst 366344 # number of demand (read+write) misses
|
||||
system.cpu1.icache.demand_misses::total 366344 # number of demand (read+write) misses
|
||||
system.cpu1.icache.overall_misses::cpu1.inst 366344 # number of overall misses
|
||||
system.cpu1.icache.overall_misses::total 366344 # number of overall misses
|
||||
system.cpu1.icache.ReadReq_accesses::cpu1.inst 26945412 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu1.icache.ReadReq_accesses::total 26945412 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu1.icache.demand_accesses::cpu1.inst 26945412 # number of demand (read+write) accesses
|
||||
system.cpu1.icache.demand_accesses::total 26945412 # number of demand (read+write) accesses
|
||||
system.cpu1.icache.overall_accesses::cpu1.inst 26945412 # number of overall (read+write) accesses
|
||||
system.cpu1.icache.overall_accesses::total 26945412 # number of overall (read+write) accesses
|
||||
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.013596 # miss rate for ReadReq accesses
|
||||
system.cpu1.icache.ReadReq_miss_rate::total 0.013596 # miss rate for ReadReq accesses
|
||||
system.cpu1.icache.demand_miss_rate::cpu1.inst 0.013596 # miss rate for demand accesses
|
||||
system.cpu1.icache.demand_miss_rate::total 0.013596 # miss rate for demand accesses
|
||||
system.cpu1.icache.overall_miss_rate::cpu1.inst 0.013596 # miss rate for overall accesses
|
||||
system.cpu1.icache.overall_miss_rate::total 0.013596 # miss rate for overall accesses
|
||||
system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu1.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu1.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu1.icache.writebacks::writebacks 12806 # number of writebacks
|
||||
system.cpu1.icache.writebacks::total 12806 # number of writebacks
|
||||
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu1.dcache.replacements 240038 # number of replacements
|
||||
system.cpu1.dcache.tagsinuse 389.638585 # Cycle average of tags in use
|
||||
system.cpu1.dcache.total_refs 9512122 # Total number of references to valid blocks.
|
||||
system.cpu1.dcache.sampled_refs 240396 # Sample count of references to valid blocks.
|
||||
system.cpu1.dcache.avg_refs 39.568554 # Average number of references to valid blocks.
|
||||
system.cpu1.dcache.warmup_cycle 69263687500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu1.dcache.occ_blocks::cpu1.data 389.638585 # Average occupied blocks per requestor
|
||||
system.cpu1.dcache.occ_percent::cpu1.data 0.761013 # Average percentage of cache occupancy
|
||||
system.cpu1.dcache.occ_percent::total 0.761013 # Average percentage of cache occupancy
|
||||
system.cpu1.dcache.ReadReq_hits::cpu1.data 5740038 # number of ReadReq hits
|
||||
system.cpu1.dcache.ReadReq_hits::total 5740038 # number of ReadReq hits
|
||||
system.cpu1.dcache.WriteReq_hits::cpu1.data 3634687 # number of WriteReq hits
|
||||
system.cpu1.dcache.WriteReq_hits::total 3634687 # number of WriteReq hits
|
||||
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 56514 # number of LoadLockedReq hits
|
||||
system.cpu1.dcache.LoadLockedReq_hits::total 56514 # number of LoadLockedReq hits
|
||||
system.cpu1.dcache.StoreCondReq_hits::cpu1.data 57060 # number of StoreCondReq hits
|
||||
system.cpu1.dcache.StoreCondReq_hits::total 57060 # number of StoreCondReq hits
|
||||
system.cpu1.dcache.demand_hits::cpu1.data 9374725 # number of demand (read+write) hits
|
||||
system.cpu1.dcache.demand_hits::total 9374725 # number of demand (read+write) hits
|
||||
system.cpu1.dcache.overall_hits::cpu1.data 9374725 # number of overall hits
|
||||
system.cpu1.dcache.overall_hits::total 9374725 # number of overall hits
|
||||
system.cpu1.dcache.ReadReq_misses::cpu1.data 161066 # number of ReadReq misses
|
||||
system.cpu1.dcache.ReadReq_misses::total 161066 # number of ReadReq misses
|
||||
system.cpu1.dcache.WriteReq_misses::cpu1.data 108913 # number of WriteReq misses
|
||||
system.cpu1.dcache.WriteReq_misses::total 108913 # number of WriteReq misses
|
||||
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 10616 # number of LoadLockedReq misses
|
||||
system.cpu1.dcache.LoadLockedReq_misses::total 10616 # number of LoadLockedReq misses
|
||||
system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10014 # number of StoreCondReq misses
|
||||
system.cpu1.dcache.StoreCondReq_misses::total 10014 # number of StoreCondReq misses
|
||||
system.cpu1.dcache.demand_misses::cpu1.data 269979 # number of demand (read+write) misses
|
||||
system.cpu1.dcache.demand_misses::total 269979 # number of demand (read+write) misses
|
||||
system.cpu1.dcache.overall_misses::cpu1.data 269979 # number of overall misses
|
||||
system.cpu1.dcache.overall_misses::total 269979 # number of overall misses
|
||||
system.cpu1.dcache.ReadReq_accesses::cpu1.data 5901104 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu1.dcache.ReadReq_accesses::total 5901104 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu1.dcache.WriteReq_accesses::cpu1.data 3743600 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu1.dcache.WriteReq_accesses::total 3743600 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 67130 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu1.dcache.LoadLockedReq_accesses::total 67130 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 67074 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu1.dcache.StoreCondReq_accesses::total 67074 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu1.dcache.demand_accesses::cpu1.data 9644704 # number of demand (read+write) accesses
|
||||
system.cpu1.dcache.demand_accesses::total 9644704 # number of demand (read+write) accesses
|
||||
system.cpu1.dcache.overall_accesses::cpu1.data 9644704 # number of overall (read+write) accesses
|
||||
system.cpu1.dcache.overall_accesses::total 9644704 # number of overall (read+write) accesses
|
||||
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.027294 # miss rate for ReadReq accesses
|
||||
system.cpu1.dcache.ReadReq_miss_rate::total 0.027294 # miss rate for ReadReq accesses
|
||||
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.029093 # miss rate for WriteReq accesses
|
||||
system.cpu1.dcache.WriteReq_miss_rate::total 0.029093 # miss rate for WriteReq accesses
|
||||
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.158141 # miss rate for LoadLockedReq accesses
|
||||
system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.158141 # miss rate for LoadLockedReq accesses
|
||||
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.149298 # miss rate for StoreCondReq accesses
|
||||
system.cpu1.dcache.StoreCondReq_miss_rate::total 0.149298 # miss rate for StoreCondReq accesses
|
||||
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.027992 # miss rate for demand accesses
|
||||
system.cpu1.dcache.demand_miss_rate::total 0.027992 # miss rate for demand accesses
|
||||
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.027992 # miss rate for overall accesses
|
||||
system.cpu1.dcache.overall_miss_rate::total 0.027992 # miss rate for overall accesses
|
||||
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu1.dcache.writebacks::writebacks 196629 # number of writebacks
|
||||
system.cpu1.dcache.writebacks::total 196629 # number of writebacks
|
||||
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.iocache.replacements 0 # number of replacements
|
||||
system.iocache.tagsinuse 0 # Cycle average of tags in use
|
||||
system.iocache.total_refs 0 # Total number of references to valid blocks.
|
||||
system.iocache.sampled_refs 0 # Sample count of references to valid blocks.
|
||||
system.iocache.avg_refs nan # Average number of references to valid blocks.
|
||||
system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.iocache.fast_writes 0 # number of fast writes performed
|
||||
system.iocache.cache_copies 0 # number of cache copies performed
|
||||
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
@ -0,0 +1 @@
|
||||
build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual FAILED!
|
||||
Binary file not shown.
@ -0,0 +1,676 @@
|
||||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
full_system=true
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
||||
[system]
|
||||
type=LinuxArmSystem
|
||||
children=bridge cf0 cpu intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver
|
||||
atags_addr=256
|
||||
boot_loader=/dist/m5/system/binaries/boot.arm
|
||||
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
|
||||
early_kernel_symbols=false
|
||||
flags_addr=268435504
|
||||
gic_cpu_addr=520093952
|
||||
init_param=0
|
||||
kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
|
||||
load_addr_mask=268435455
|
||||
machine_type=RealView_PBX
|
||||
mem_mode=atomic
|
||||
memories=system.physmem system.realview.nvmem
|
||||
midr_regval=890224640
|
||||
num_work_ids=16
|
||||
readfile=tests/halt.sh
|
||||
symbolfile=
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.membus.slave[0]
|
||||
|
||||
[system.bridge]
|
||||
type=Bridge
|
||||
delay=50000
|
||||
nack_delay=4000
|
||||
ranges=268435456:520093695 1073741824:1610612735
|
||||
req_size=16
|
||||
resp_size=16
|
||||
write_ack=false
|
||||
master=system.iobus.slave[0]
|
||||
slave=system.membus.master[0]
|
||||
|
||||
[system.cf0]
|
||||
type=IdeDisk
|
||||
children=image
|
||||
delay=1000000
|
||||
driveID=master
|
||||
image=system.cf0.image
|
||||
|
||||
[system.cf0.image]
|
||||
type=CowDiskImage
|
||||
children=child
|
||||
child=system.cf0.image.child
|
||||
image_file=
|
||||
read_only=false
|
||||
table_size=65536
|
||||
|
||||
[system.cf0.image.child]
|
||||
type=RawDiskImage
|
||||
image_file=/dist/m5/system/disks/linux-arm-ael.img
|
||||
read_only=true
|
||||
|
||||
[system.cpu]
|
||||
type=AtomicSimpleCPU
|
||||
children=dcache dtb icache interrupts itb tracer
|
||||
checker=Null
|
||||
clock=500
|
||||
cpu_id=0
|
||||
defer_registration=false
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
fastmem=false
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
interrupts=system.cpu.interrupts
|
||||
itb=system.cpu.itb
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
phase=0
|
||||
profile=0
|
||||
progress_interval=0
|
||||
simulate_data_stalls=false
|
||||
simulate_inst_stalls=false
|
||||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
width=1
|
||||
workload=
|
||||
dcache_port=system.cpu.dcache.cpu_side
|
||||
icache_port=system.cpu.icache.cpu_side
|
||||
|
||||
[system.cpu.dcache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=4
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=32768
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=8
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.dcache_port
|
||||
mem_side=system.toL2Bus.slave[1]
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
size=64
|
||||
walker=system.cpu.dtb.walker
|
||||
|
||||
[system.cpu.dtb.walker]
|
||||
type=ArmTableWalker
|
||||
max_backoff=100000
|
||||
min_backoff=0
|
||||
sys=system
|
||||
port=system.toL2Bus.slave[3]
|
||||
|
||||
[system.cpu.icache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=1
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=32768
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=8
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.icache_port
|
||||
mem_side=system.toL2Bus.slave[0]
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=ArmInterrupts
|
||||
|
||||
[system.cpu.itb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
size=64
|
||||
walker=system.cpu.itb.walker
|
||||
|
||||
[system.cpu.itb.walker]
|
||||
type=ArmTableWalker
|
||||
max_backoff=100000
|
||||
min_backoff=0
|
||||
sys=system
|
||||
port=system.toL2Bus.slave[2]
|
||||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
|
||||
[system.intrctrl]
|
||||
type=IntrControl
|
||||
sys=system
|
||||
|
||||
[system.iobus]
|
||||
type=NoncoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side
|
||||
slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
|
||||
|
||||
[system.iocache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:268435455
|
||||
assoc=8
|
||||
block_size=64
|
||||
forward_snoops=false
|
||||
hash_delay=1
|
||||
is_top_level=false
|
||||
latency=50000
|
||||
max_miss_count=0
|
||||
mshrs=20
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=1024
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=12
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.iobus.master[25]
|
||||
mem_side=system.membus.slave[1]
|
||||
|
||||
[system.l2c]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=8
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=false
|
||||
latency=10000
|
||||
max_miss_count=0
|
||||
mshrs=92
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=4194304
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=16
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.toL2Bus.master[0]
|
||||
mem_side=system.membus.slave[2]
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
children=badaddr_responder
|
||||
block_size=64
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
default=system.membus.badaddr_responder.pio
|
||||
master=system.bridge.slave system.realview.nvmem.port[0] system.physmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio
|
||||
slave=system.system_port system.iocache.mem_side system.l2c.mem_side
|
||||
|
||||
[system.membus.badaddr_responder]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=0
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=true
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=warn
|
||||
pio=system.membus.default
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
conf_table_reported=true
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.membus.master[2]
|
||||
|
||||
[system.realview]
|
||||
type=RealView
|
||||
children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
|
||||
intrctrl=system.intrctrl
|
||||
max_mem_size=268435456
|
||||
mem_start_addr=0
|
||||
pci_cfg_base=0
|
||||
system=system
|
||||
|
||||
[system.realview.a9scu]
|
||||
type=A9SCU
|
||||
pio_addr=520093696
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.membus.master[5]
|
||||
|
||||
[system.realview.aaci_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
ignore_access=false
|
||||
pio_addr=268451840
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.iobus.master[21]
|
||||
|
||||
[system.realview.cf_ctrl]
|
||||
type=IdeController
|
||||
BAR0=402653184
|
||||
BAR0LegacyIO=true
|
||||
BAR0Size=16
|
||||
BAR1=402653440
|
||||
BAR1LegacyIO=true
|
||||
BAR1Size=1
|
||||
BAR2=1
|
||||
BAR2LegacyIO=false
|
||||
BAR2Size=8
|
||||
BAR3=1
|
||||
BAR3LegacyIO=false
|
||||
BAR3Size=4
|
||||
BAR4=1
|
||||
BAR4LegacyIO=false
|
||||
BAR4Size=16
|
||||
BAR5=1
|
||||
BAR5LegacyIO=false
|
||||
BAR5Size=0
|
||||
BIST=0
|
||||
CacheLineSize=0
|
||||
CardbusCIS=0
|
||||
ClassCode=1
|
||||
Command=1
|
||||
DeviceID=28945
|
||||
ExpansionROM=0
|
||||
HeaderType=0
|
||||
InterruptLine=31
|
||||
InterruptPin=1
|
||||
LatencyTimer=0
|
||||
MaximumLatency=0
|
||||
MinimumGrant=0
|
||||
ProgIF=133
|
||||
Revision=0
|
||||
Status=640
|
||||
SubClassCode=1
|
||||
SubsystemID=0
|
||||
SubsystemVendorID=0
|
||||
VendorID=32902
|
||||
config_latency=20000
|
||||
ctrl_offset=2
|
||||
disks=system.cf0
|
||||
io_shift=1
|
||||
max_backoff_delay=10000000
|
||||
min_backoff_delay=4000
|
||||
pci_bus=2
|
||||
pci_dev=7
|
||||
pci_func=0
|
||||
pio_latency=1000
|
||||
platform=system.realview
|
||||
system=system
|
||||
config=system.iobus.master[8]
|
||||
dma=system.iobus.slave[2]
|
||||
pio=system.iobus.master[7]
|
||||
|
||||
[system.realview.clcd]
|
||||
type=Pl111
|
||||
amba_id=1315089
|
||||
clock=41667
|
||||
gic=system.realview.gic
|
||||
int_num=55
|
||||
max_backoff_delay=10000000
|
||||
min_backoff_delay=4000
|
||||
pio_addr=268566528
|
||||
pio_latency=10000
|
||||
system=system
|
||||
vnc=system.vncserver
|
||||
dma=system.iobus.slave[1]
|
||||
pio=system.iobus.master[4]
|
||||
|
||||
[system.realview.dmac_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
ignore_access=false
|
||||
pio_addr=268632064
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.iobus.master[9]
|
||||
|
||||
[system.realview.flash_fake]
|
||||
type=IsaFake
|
||||
fake_mem=true
|
||||
pio_addr=1073741824
|
||||
pio_latency=1000
|
||||
pio_size=536870912
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[24]
|
||||
|
||||
[system.realview.gic]
|
||||
type=Gic
|
||||
cpu_addr=520093952
|
||||
cpu_pio_delay=10000
|
||||
dist_addr=520097792
|
||||
dist_pio_delay=10000
|
||||
int_latency=10000
|
||||
it_lines=128
|
||||
platform=system.realview
|
||||
system=system
|
||||
pio=system.membus.master[3]
|
||||
|
||||
[system.realview.gpio0_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
ignore_access=false
|
||||
pio_addr=268513280
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.iobus.master[16]
|
||||
|
||||
[system.realview.gpio1_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
ignore_access=false
|
||||
pio_addr=268517376
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.iobus.master[17]
|
||||
|
||||
[system.realview.gpio2_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
ignore_access=false
|
||||
pio_addr=268521472
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.iobus.master[18]
|
||||
|
||||
[system.realview.kmi0]
|
||||
type=Pl050
|
||||
amba_id=1314896
|
||||
gic=system.realview.gic
|
||||
int_delay=1000000
|
||||
int_num=52
|
||||
is_mouse=false
|
||||
pio_addr=268460032
|
||||
pio_latency=1000
|
||||
system=system
|
||||
vnc=system.vncserver
|
||||
pio=system.iobus.master[5]
|
||||
|
||||
[system.realview.kmi1]
|
||||
type=Pl050
|
||||
amba_id=1314896
|
||||
gic=system.realview.gic
|
||||
int_delay=1000000
|
||||
int_num=53
|
||||
is_mouse=true
|
||||
pio_addr=268464128
|
||||
pio_latency=1000
|
||||
system=system
|
||||
vnc=system.vncserver
|
||||
pio=system.iobus.master[6]
|
||||
|
||||
[system.realview.l2x0_fake]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=520101888
|
||||
pio_latency=1000
|
||||
pio_size=4095
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.membus.master[4]
|
||||
|
||||
[system.realview.local_cpu_timer]
|
||||
type=CpuLocalTimer
|
||||
clock=1000
|
||||
gic=system.realview.gic
|
||||
int_num_timer=29
|
||||
int_num_watchdog=30
|
||||
pio_addr=520095232
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.membus.master[6]
|
||||
|
||||
[system.realview.mmc_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
ignore_access=false
|
||||
pio_addr=268455936
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.iobus.master[22]
|
||||
|
||||
[system.realview.nvmem]
|
||||
type=SimpleMemory
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
range=2147483648:2214592511
|
||||
zero=true
|
||||
port=system.membus.master[1]
|
||||
|
||||
[system.realview.realview_io]
|
||||
type=RealViewCtrl
|
||||
idreg=0
|
||||
pio_addr=268435456
|
||||
pio_latency=1000
|
||||
proc_id0=201326592
|
||||
proc_id1=201327138
|
||||
system=system
|
||||
pio=system.iobus.master[1]
|
||||
|
||||
[system.realview.rtc]
|
||||
type=PL031
|
||||
amba_id=3412017
|
||||
gic=system.realview.gic
|
||||
int_delay=100000
|
||||
int_num=42
|
||||
pio_addr=268529664
|
||||
pio_latency=1000
|
||||
system=system
|
||||
time=Thu Jan 1 00:00:00 2009
|
||||
pio=system.iobus.master[23]
|
||||
|
||||
[system.realview.sci_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
ignore_access=false
|
||||
pio_addr=268492800
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.iobus.master[20]
|
||||
|
||||
[system.realview.smc_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
ignore_access=false
|
||||
pio_addr=269357056
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.iobus.master[13]
|
||||
|
||||
[system.realview.sp810_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
ignore_access=true
|
||||
pio_addr=268439552
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.iobus.master[14]
|
||||
|
||||
[system.realview.ssp_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
ignore_access=false
|
||||
pio_addr=268488704
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.iobus.master[19]
|
||||
|
||||
[system.realview.timer0]
|
||||
type=Sp804
|
||||
amba_id=1316868
|
||||
clock0=1000000
|
||||
clock1=1000000
|
||||
gic=system.realview.gic
|
||||
int_num0=36
|
||||
int_num1=36
|
||||
pio_addr=268505088
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.iobus.master[2]
|
||||
|
||||
[system.realview.timer1]
|
||||
type=Sp804
|
||||
amba_id=1316868
|
||||
clock0=1000000
|
||||
clock1=1000000
|
||||
gic=system.realview.gic
|
||||
int_num0=37
|
||||
int_num1=37
|
||||
pio_addr=268509184
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.iobus.master[3]
|
||||
|
||||
[system.realview.uart]
|
||||
type=Pl011
|
||||
end_on_eot=false
|
||||
gic=system.realview.gic
|
||||
int_delay=100000
|
||||
int_num=44
|
||||
pio_addr=268472320
|
||||
pio_latency=1000
|
||||
platform=system.realview
|
||||
system=system
|
||||
terminal=system.terminal
|
||||
pio=system.iobus.master[0]
|
||||
|
||||
[system.realview.uart1_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
ignore_access=false
|
||||
pio_addr=268476416
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.iobus.master[10]
|
||||
|
||||
[system.realview.uart2_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
ignore_access=false
|
||||
pio_addr=268480512
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.iobus.master[11]
|
||||
|
||||
[system.realview.uart3_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
ignore_access=false
|
||||
pio_addr=268484608
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.iobus.master[12]
|
||||
|
||||
[system.realview.watchdog_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
ignore_access=false
|
||||
pio_addr=268500992
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.iobus.master[15]
|
||||
|
||||
[system.terminal]
|
||||
type=Terminal
|
||||
intr_control=system.intrctrl
|
||||
number=0
|
||||
output=true
|
||||
port=3456
|
||||
|
||||
[system.toL2Bus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
master=system.l2c.cpu_side
|
||||
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
|
||||
|
||||
[system.vncserver]
|
||||
type=VncServer
|
||||
frame_capture=false
|
||||
number=0
|
||||
port=5900
|
||||
|
||||
@ -0,0 +1,17 @@
|
||||
warn: Sockets disabled, not accepting vnc client connections
|
||||
warn: Sockets disabled, not accepting terminal connections
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: The clidr register always reports 0 caches.
|
||||
warn: clidr LoUIS field of 0b001 to match current ARM implementations.
|
||||
warn: The csselr register isn't implemented.
|
||||
warn: The ccsidr register isn't implemented and always reads as 0.
|
||||
warn: instruction 'mcr bpiallis' unimplemented
|
||||
warn: instruction 'mcr icialluis' unimplemented
|
||||
warn: instruction 'mcr dccimvac' unimplemented
|
||||
warn: instruction 'mcr dccmvau' unimplemented
|
||||
warn: instruction 'mcr icimvau' unimplemented
|
||||
warn: LCD dual screen mode not supported
|
||||
warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
|
||||
warn: instruction 'mcr icialluis' unimplemented
|
||||
warn: instruction 'mcr bpiallis' unimplemented
|
||||
hack: be nice to actually delete the event here
|
||||
@ -0,0 +1,12 @@
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jun 4 2012 12:14:06
|
||||
gem5 started Jun 4 2012 17:24:24
|
||||
gem5 executing on zizzer
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
|
||||
info: Using bootloader at address 0x80000000
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 2332330037000 because m5_exit instruction encountered
|
||||
@ -0,0 +1,368 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 2.332330 # Number of seconds simulated
|
||||
sim_ticks 2332330037000 # Number of ticks simulated
|
||||
final_tick 2332330037000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1412842 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1823742 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 55482154888 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 382804 # Number of bytes of host memory used
|
||||
host_seconds 42.04 # Real time elapsed on the host
|
||||
sim_insts 59392246 # Number of instructions simulated
|
||||
sim_ops 76665494 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::realview.clcd 111673344 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.dtb.walker 1536 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.itb.walker 960 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.inst 941920 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 10043536 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 122661296 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 941920 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 941920 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 6574400 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::cpu.data 3015816 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 9590216 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::realview.clcd 13959168 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.dtb.walker 24 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.itb.walker 15 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.inst 20920 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 156964 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 14137091 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 102725 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::cpu.data 753954 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 856679 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::realview.clcd 47880592 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.dtb.walker 659 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.itb.walker 412 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 403854 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 4306224 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 52591740 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 403854 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 403854 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 2818812 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::cpu.data 1293049 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 4111861 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 2818812 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::realview.clcd 47880592 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.dtb.walker 659 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.itb.walker 412 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 403854 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 5599273 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 56703601 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory
|
||||
system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
|
||||
system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory
|
||||
system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
|
||||
system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory
|
||||
system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
|
||||
system.realview.nvmem.bw_read::cpu.inst 9 # Total read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_read::total 9 # Total read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_inst_read::cpu.inst 9 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_inst_read::total 9 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_total::cpu.inst 9 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_total::total 9 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.l2c.replacements 117012 # number of replacements
|
||||
system.l2c.tagsinuse 24288.656748 # Cycle average of tags in use
|
||||
system.l2c.total_refs 1527554 # Total number of references to valid blocks.
|
||||
system.l2c.sampled_refs 146810 # Sample count of references to valid blocks.
|
||||
system.l2c.avg_refs 10.404972 # Average number of references to valid blocks.
|
||||
system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.l2c.occ_blocks::writebacks 13693.996987 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu.dtb.walker 7.872000 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu.itb.walker 1.975558 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu.inst 5248.163956 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu.data 5336.648246 # Average occupied blocks per requestor
|
||||
system.l2c.occ_percent::writebacks 0.208954 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu.dtb.walker 0.000120 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu.itb.walker 0.000030 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu.inst 0.080081 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu.data 0.081431 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::total 0.370615 # Average percentage of cache occupancy
|
||||
system.l2c.ReadReq_hits::cpu.dtb.walker 7515 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu.itb.walker 3139 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu.inst 835264 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu.data 357385 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::total 1203303 # number of ReadReq hits
|
||||
system.l2c.Writeback_hits::writebacks 605735 # number of Writeback hits
|
||||
system.l2c.Writeback_hits::total 605735 # number of Writeback hits
|
||||
system.l2c.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits
|
||||
system.l2c.UpgradeReq_hits::total 26 # number of UpgradeReq hits
|
||||
system.l2c.ReadExReq_hits::cpu.data 106156 # number of ReadExReq hits
|
||||
system.l2c.ReadExReq_hits::total 106156 # number of ReadExReq hits
|
||||
system.l2c.demand_hits::cpu.dtb.walker 7515 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu.itb.walker 3139 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu.inst 835264 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu.data 463541 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::total 1309459 # number of demand (read+write) hits
|
||||
system.l2c.overall_hits::cpu.dtb.walker 7515 # number of overall hits
|
||||
system.l2c.overall_hits::cpu.itb.walker 3139 # number of overall hits
|
||||
system.l2c.overall_hits::cpu.inst 835264 # number of overall hits
|
||||
system.l2c.overall_hits::cpu.data 463541 # number of overall hits
|
||||
system.l2c.overall_hits::total 1309459 # number of overall hits
|
||||
system.l2c.ReadReq_misses::cpu.dtb.walker 24 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu.itb.walker 15 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu.inst 14304 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu.data 17465 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::total 31808 # number of ReadReq misses
|
||||
system.l2c.UpgradeReq_misses::cpu.data 2918 # number of UpgradeReq misses
|
||||
system.l2c.UpgradeReq_misses::total 2918 # number of UpgradeReq misses
|
||||
system.l2c.ReadExReq_misses::cpu.data 141050 # number of ReadExReq misses
|
||||
system.l2c.ReadExReq_misses::total 141050 # number of ReadExReq misses
|
||||
system.l2c.demand_misses::cpu.dtb.walker 24 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu.itb.walker 15 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu.inst 14304 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu.data 158515 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::total 172858 # number of demand (read+write) misses
|
||||
system.l2c.overall_misses::cpu.dtb.walker 24 # number of overall misses
|
||||
system.l2c.overall_misses::cpu.itb.walker 15 # number of overall misses
|
||||
system.l2c.overall_misses::cpu.inst 14304 # number of overall misses
|
||||
system.l2c.overall_misses::cpu.data 158515 # number of overall misses
|
||||
system.l2c.overall_misses::total 172858 # number of overall misses
|
||||
system.l2c.ReadReq_accesses::cpu.dtb.walker 7539 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::cpu.itb.walker 3154 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::cpu.inst 849568 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::cpu.data 374850 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::total 1235111 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.Writeback_accesses::writebacks 605735 # number of Writeback accesses(hits+misses)
|
||||
system.l2c.Writeback_accesses::total 605735 # number of Writeback accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_accesses::cpu.data 2944 # number of UpgradeReq accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_accesses::total 2944 # number of UpgradeReq accesses(hits+misses)
|
||||
system.l2c.ReadExReq_accesses::cpu.data 247206 # number of ReadExReq accesses(hits+misses)
|
||||
system.l2c.ReadExReq_accesses::total 247206 # number of ReadExReq accesses(hits+misses)
|
||||
system.l2c.demand_accesses::cpu.dtb.walker 7539 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu.itb.walker 3154 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu.inst 849568 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu.data 622056 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::total 1482317 # number of demand (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu.dtb.walker 7539 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu.itb.walker 3154 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu.inst 849568 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu.data 622056 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::total 1482317 # number of overall (read+write) accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.003183 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.004756 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu.inst 0.016837 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu.data 0.046592 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::total 0.025753 # miss rate for ReadReq accesses
|
||||
system.l2c.UpgradeReq_miss_rate::cpu.data 0.991168 # miss rate for UpgradeReq accesses
|
||||
system.l2c.UpgradeReq_miss_rate::total 0.991168 # miss rate for UpgradeReq accesses
|
||||
system.l2c.ReadExReq_miss_rate::cpu.data 0.570577 # miss rate for ReadExReq accesses
|
||||
system.l2c.ReadExReq_miss_rate::total 0.570577 # miss rate for ReadExReq accesses
|
||||
system.l2c.demand_miss_rate::cpu.dtb.walker 0.003183 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu.itb.walker 0.004756 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu.inst 0.016837 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu.data 0.254824 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::total 0.116613 # miss rate for demand accesses
|
||||
system.l2c.overall_miss_rate::cpu.dtb.walker 0.003183 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu.itb.walker 0.004756 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu.inst 0.016837 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu.data 0.254824 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::total 0.116613 # miss rate for overall accesses
|
||||
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.l2c.fast_writes 0 # number of fast writes performed
|
||||
system.l2c.cache_copies 0 # number of cache copies performed
|
||||
system.l2c.writebacks::writebacks 102725 # number of writebacks
|
||||
system.l2c.writebacks::total 102725 # number of writebacks
|
||||
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
||||
system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
|
||||
system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
|
||||
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
|
||||
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
|
||||
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
|
||||
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.dtb.read_hits 14971229 # DTB read hits
|
||||
system.cpu.dtb.read_misses 7293 # DTB read misses
|
||||
system.cpu.dtb.write_hits 11217018 # DTB write hits
|
||||
system.cpu.dtb.write_misses 2181 # DTB write misses
|
||||
system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed
|
||||
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
|
||||
system.cpu.dtb.flush_entries 3492 # Number of entries that have been flushed from TLB
|
||||
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.dtb.prefetch_faults 174 # Number of TLB faults due to prefetch
|
||||
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.dtb.read_accesses 14978522 # DTB read accesses
|
||||
system.cpu.dtb.write_accesses 11219199 # DTB write accesses
|
||||
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
|
||||
system.cpu.dtb.hits 26188247 # DTB hits
|
||||
system.cpu.dtb.misses 9474 # DTB misses
|
||||
system.cpu.dtb.accesses 26197721 # DTB accesses
|
||||
system.cpu.itb.inst_hits 60403303 # ITB inst hits
|
||||
system.cpu.itb.inst_misses 4471 # ITB inst misses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.write_hits 0 # DTB write hits
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed
|
||||
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
|
||||
system.cpu.itb.flush_entries 2343 # Number of entries that have been flushed from TLB
|
||||
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.itb.inst_accesses 60407774 # ITB inst accesses
|
||||
system.cpu.itb.hits 60403303 # DTB hits
|
||||
system.cpu.itb.misses 4471 # DTB misses
|
||||
system.cpu.itb.accesses 60407774 # DTB accesses
|
||||
system.cpu.numCycles 4664583062 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 59392246 # Number of instructions committed
|
||||
system.cpu.committedOps 76665494 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 68281415 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 1972385 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 7647793 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 68281415 # number of integer instructions
|
||||
system.cpu.num_fp_insts 10269 # number of float instructions
|
||||
system.cpu.num_int_register_reads 345981857 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 73062916 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written
|
||||
system.cpu.num_mem_refs 27361692 # number of memory refs
|
||||
system.cpu.num_load_insts 15639569 # Number of load instructions
|
||||
system.cpu.num_store_insts 11722123 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 4586814358.980880 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 77768703.019120 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 0.016672 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0.983328 # Percentage of idle cycles
|
||||
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
||||
system.cpu.kern.inst.quiesce 82795 # number of quiesce instructions executed
|
||||
system.cpu.icache.replacements 850612 # number of replacements
|
||||
system.cpu.icache.tagsinuse 511.678549 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 59554939 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 851124 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 69.972106 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 5708999000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 511.678549 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.999372 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.999372 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 59554939 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 59554939 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 59554939 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 59554939 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 59554939 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 59554939 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 851124 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 851124 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 851124 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 851124 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 851124 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 851124 # number of overall misses
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 60406063 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 60406063 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 60406063 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 60406063 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 60406063 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 60406063 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014090 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.014090 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.014090 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.014090 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.014090 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.014090 # miss rate for overall accesses
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks::writebacks 44595 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 44595 # number of writebacks
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 623347 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 511.997030 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 23628362 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 623859 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 37.874523 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 21763000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 511.997030 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.999994 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 13180074 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 13180074 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 9962087 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 9962087 # number of WriteReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::cpu.data 236035 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::total 236035 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::cpu.data 247222 # number of StoreCondReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::total 247222 # number of StoreCondReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 23142161 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 23142161 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 23142161 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 23142161 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 365465 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 365465 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 250150 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 250150 # number of WriteReq misses
|
||||
system.cpu.dcache.LoadLockedReq_misses::cpu.data 11188 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.LoadLockedReq_misses::total 11188 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 615615 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 615615 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 615615 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 615615 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 13545539 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 13545539 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 10212237 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 10212237 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247223 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::total 247223 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::cpu.data 247222 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::total 247222 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 23757776 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 23757776 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 23757776 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 23757776 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.026980 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.026980 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024495 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.024495 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045255 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045255 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.025912 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.025912 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.025912 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.025912 # miss rate for overall accesses
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 561140 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 561140 # number of writebacks
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.iocache.replacements 0 # number of replacements
|
||||
system.iocache.tagsinuse 0 # Cycle average of tags in use
|
||||
system.iocache.total_refs 0 # Total number of references to valid blocks.
|
||||
system.iocache.sampled_refs 0 # Sample count of references to valid blocks.
|
||||
system.iocache.avg_refs nan # Average number of references to valid blocks.
|
||||
system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.iocache.fast_writes 0 # number of fast writes performed
|
||||
system.iocache.cache_copies 0 # number of cache copies performed
|
||||
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
@ -0,0 +1 @@
|
||||
build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic FAILED!
|
||||
Binary file not shown.
@ -0,0 +1,783 @@
|
||||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
full_system=true
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
||||
[system]
|
||||
type=LinuxArmSystem
|
||||
children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver
|
||||
atags_addr=256
|
||||
boot_loader=/dist/m5/system/binaries/boot.arm
|
||||
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
|
||||
early_kernel_symbols=false
|
||||
flags_addr=268435504
|
||||
gic_cpu_addr=520093952
|
||||
init_param=0
|
||||
kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
|
||||
load_addr_mask=268435455
|
||||
machine_type=RealView_PBX
|
||||
mem_mode=timing
|
||||
memories=system.realview.nvmem system.physmem
|
||||
midr_regval=890224640
|
||||
num_work_ids=16
|
||||
readfile=tests/halt.sh
|
||||
symbolfile=
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.membus.slave[0]
|
||||
|
||||
[system.bridge]
|
||||
type=Bridge
|
||||
delay=50000
|
||||
nack_delay=4000
|
||||
ranges=268435456:520093695 1073741824:1610612735
|
||||
req_size=16
|
||||
resp_size=16
|
||||
write_ack=false
|
||||
master=system.iobus.slave[0]
|
||||
slave=system.membus.master[0]
|
||||
|
||||
[system.cf0]
|
||||
type=IdeDisk
|
||||
children=image
|
||||
delay=1000000
|
||||
driveID=master
|
||||
image=system.cf0.image
|
||||
|
||||
[system.cf0.image]
|
||||
type=CowDiskImage
|
||||
children=child
|
||||
child=system.cf0.image.child
|
||||
image_file=
|
||||
read_only=false
|
||||
table_size=65536
|
||||
|
||||
[system.cf0.image.child]
|
||||
type=RawDiskImage
|
||||
image_file=/dist/m5/system/disks/linux-arm-ael.img
|
||||
read_only=true
|
||||
|
||||
[system.cpu0]
|
||||
type=TimingSimpleCPU
|
||||
children=dcache dtb icache interrupts itb tracer
|
||||
checker=Null
|
||||
clock=500
|
||||
cpu_id=0
|
||||
defer_registration=false
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu0.dtb
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
interrupts=system.cpu0.interrupts
|
||||
itb=system.cpu0.itb
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
phase=0
|
||||
profile=0
|
||||
progress_interval=0
|
||||
system=system
|
||||
tracer=system.cpu0.tracer
|
||||
workload=
|
||||
dcache_port=system.cpu0.dcache.cpu_side
|
||||
icache_port=system.cpu0.icache.cpu_side
|
||||
|
||||
[system.cpu0.dcache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=4
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=32768
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=8
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu0.dcache_port
|
||||
mem_side=system.toL2Bus.slave[1]
|
||||
|
||||
[system.cpu0.dtb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
size=64
|
||||
walker=system.cpu0.dtb.walker
|
||||
|
||||
[system.cpu0.dtb.walker]
|
||||
type=ArmTableWalker
|
||||
max_backoff=100000
|
||||
min_backoff=0
|
||||
sys=system
|
||||
port=system.toL2Bus.slave[3]
|
||||
|
||||
[system.cpu0.icache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=1
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=32768
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=8
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu0.icache_port
|
||||
mem_side=system.toL2Bus.slave[0]
|
||||
|
||||
[system.cpu0.interrupts]
|
||||
type=ArmInterrupts
|
||||
|
||||
[system.cpu0.itb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
size=64
|
||||
walker=system.cpu0.itb.walker
|
||||
|
||||
[system.cpu0.itb.walker]
|
||||
type=ArmTableWalker
|
||||
max_backoff=100000
|
||||
min_backoff=0
|
||||
sys=system
|
||||
port=system.toL2Bus.slave[2]
|
||||
|
||||
[system.cpu0.tracer]
|
||||
type=ExeTracer
|
||||
|
||||
[system.cpu1]
|
||||
type=TimingSimpleCPU
|
||||
children=dcache dtb icache interrupts itb tracer
|
||||
checker=Null
|
||||
clock=500
|
||||
cpu_id=1
|
||||
defer_registration=false
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu1.dtb
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
interrupts=system.cpu1.interrupts
|
||||
itb=system.cpu1.itb
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
phase=0
|
||||
profile=0
|
||||
progress_interval=0
|
||||
system=system
|
||||
tracer=system.cpu1.tracer
|
||||
workload=
|
||||
dcache_port=system.cpu1.dcache.cpu_side
|
||||
icache_port=system.cpu1.icache.cpu_side
|
||||
|
||||
[system.cpu1.dcache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=4
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=32768
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=8
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu1.dcache_port
|
||||
mem_side=system.toL2Bus.slave[5]
|
||||
|
||||
[system.cpu1.dtb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
size=64
|
||||
walker=system.cpu1.dtb.walker
|
||||
|
||||
[system.cpu1.dtb.walker]
|
||||
type=ArmTableWalker
|
||||
max_backoff=100000
|
||||
min_backoff=0
|
||||
sys=system
|
||||
port=system.toL2Bus.slave[7]
|
||||
|
||||
[system.cpu1.icache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=1
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=32768
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=8
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu1.icache_port
|
||||
mem_side=system.toL2Bus.slave[4]
|
||||
|
||||
[system.cpu1.interrupts]
|
||||
type=ArmInterrupts
|
||||
|
||||
[system.cpu1.itb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
size=64
|
||||
walker=system.cpu1.itb.walker
|
||||
|
||||
[system.cpu1.itb.walker]
|
||||
type=ArmTableWalker
|
||||
max_backoff=100000
|
||||
min_backoff=0
|
||||
sys=system
|
||||
port=system.toL2Bus.slave[6]
|
||||
|
||||
[system.cpu1.tracer]
|
||||
type=ExeTracer
|
||||
|
||||
[system.intrctrl]
|
||||
type=IntrControl
|
||||
sys=system
|
||||
|
||||
[system.iobus]
|
||||
type=NoncoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side
|
||||
slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
|
||||
|
||||
[system.iocache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:268435455
|
||||
assoc=8
|
||||
block_size=64
|
||||
forward_snoops=false
|
||||
hash_delay=1
|
||||
is_top_level=false
|
||||
latency=50000
|
||||
max_miss_count=0
|
||||
mshrs=20
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=1024
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=12
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.iobus.master[25]
|
||||
mem_side=system.membus.slave[1]
|
||||
|
||||
[system.l2c]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=8
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=false
|
||||
latency=10000
|
||||
max_miss_count=0
|
||||
mshrs=92
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=4194304
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=16
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.toL2Bus.master[0]
|
||||
mem_side=system.membus.slave[2]
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
children=badaddr_responder
|
||||
block_size=64
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
default=system.membus.badaddr_responder.pio
|
||||
master=system.bridge.slave system.realview.nvmem.port[0] system.physmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio
|
||||
slave=system.system_port system.iocache.mem_side system.l2c.mem_side
|
||||
|
||||
[system.membus.badaddr_responder]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=0
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=true
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=warn
|
||||
pio=system.membus.default
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
conf_table_reported=true
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.membus.master[2]
|
||||
|
||||
[system.realview]
|
||||
type=RealView
|
||||
children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
|
||||
intrctrl=system.intrctrl
|
||||
max_mem_size=268435456
|
||||
mem_start_addr=0
|
||||
pci_cfg_base=0
|
||||
system=system
|
||||
|
||||
[system.realview.a9scu]
|
||||
type=A9SCU
|
||||
pio_addr=520093696
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.membus.master[5]
|
||||
|
||||
[system.realview.aaci_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
ignore_access=false
|
||||
pio_addr=268451840
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.iobus.master[21]
|
||||
|
||||
[system.realview.cf_ctrl]
|
||||
type=IdeController
|
||||
BAR0=402653184
|
||||
BAR0LegacyIO=true
|
||||
BAR0Size=16
|
||||
BAR1=402653440
|
||||
BAR1LegacyIO=true
|
||||
BAR1Size=1
|
||||
BAR2=1
|
||||
BAR2LegacyIO=false
|
||||
BAR2Size=8
|
||||
BAR3=1
|
||||
BAR3LegacyIO=false
|
||||
BAR3Size=4
|
||||
BAR4=1
|
||||
BAR4LegacyIO=false
|
||||
BAR4Size=16
|
||||
BAR5=1
|
||||
BAR5LegacyIO=false
|
||||
BAR5Size=0
|
||||
BIST=0
|
||||
CacheLineSize=0
|
||||
CardbusCIS=0
|
||||
ClassCode=1
|
||||
Command=1
|
||||
DeviceID=28945
|
||||
ExpansionROM=0
|
||||
HeaderType=0
|
||||
InterruptLine=31
|
||||
InterruptPin=1
|
||||
LatencyTimer=0
|
||||
MaximumLatency=0
|
||||
MinimumGrant=0
|
||||
ProgIF=133
|
||||
Revision=0
|
||||
Status=640
|
||||
SubClassCode=1
|
||||
SubsystemID=0
|
||||
SubsystemVendorID=0
|
||||
VendorID=32902
|
||||
config_latency=20000
|
||||
ctrl_offset=2
|
||||
disks=system.cf0
|
||||
io_shift=1
|
||||
max_backoff_delay=10000000
|
||||
min_backoff_delay=4000
|
||||
pci_bus=2
|
||||
pci_dev=7
|
||||
pci_func=0
|
||||
pio_latency=1000
|
||||
platform=system.realview
|
||||
system=system
|
||||
config=system.iobus.master[8]
|
||||
dma=system.iobus.slave[2]
|
||||
pio=system.iobus.master[7]
|
||||
|
||||
[system.realview.clcd]
|
||||
type=Pl111
|
||||
amba_id=1315089
|
||||
clock=41667
|
||||
gic=system.realview.gic
|
||||
int_num=55
|
||||
max_backoff_delay=10000000
|
||||
min_backoff_delay=4000
|
||||
pio_addr=268566528
|
||||
pio_latency=10000
|
||||
system=system
|
||||
vnc=system.vncserver
|
||||
dma=system.iobus.slave[1]
|
||||
pio=system.iobus.master[4]
|
||||
|
||||
[system.realview.dmac_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
ignore_access=false
|
||||
pio_addr=268632064
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.iobus.master[9]
|
||||
|
||||
[system.realview.flash_fake]
|
||||
type=IsaFake
|
||||
fake_mem=true
|
||||
pio_addr=1073741824
|
||||
pio_latency=1000
|
||||
pio_size=536870912
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[24]
|
||||
|
||||
[system.realview.gic]
|
||||
type=Gic
|
||||
cpu_addr=520093952
|
||||
cpu_pio_delay=10000
|
||||
dist_addr=520097792
|
||||
dist_pio_delay=10000
|
||||
int_latency=10000
|
||||
it_lines=128
|
||||
platform=system.realview
|
||||
system=system
|
||||
pio=system.membus.master[3]
|
||||
|
||||
[system.realview.gpio0_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
ignore_access=false
|
||||
pio_addr=268513280
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.iobus.master[16]
|
||||
|
||||
[system.realview.gpio1_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
ignore_access=false
|
||||
pio_addr=268517376
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.iobus.master[17]
|
||||
|
||||
[system.realview.gpio2_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
ignore_access=false
|
||||
pio_addr=268521472
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.iobus.master[18]
|
||||
|
||||
[system.realview.kmi0]
|
||||
type=Pl050
|
||||
amba_id=1314896
|
||||
gic=system.realview.gic
|
||||
int_delay=1000000
|
||||
int_num=52
|
||||
is_mouse=false
|
||||
pio_addr=268460032
|
||||
pio_latency=1000
|
||||
system=system
|
||||
vnc=system.vncserver
|
||||
pio=system.iobus.master[5]
|
||||
|
||||
[system.realview.kmi1]
|
||||
type=Pl050
|
||||
amba_id=1314896
|
||||
gic=system.realview.gic
|
||||
int_delay=1000000
|
||||
int_num=53
|
||||
is_mouse=true
|
||||
pio_addr=268464128
|
||||
pio_latency=1000
|
||||
system=system
|
||||
vnc=system.vncserver
|
||||
pio=system.iobus.master[6]
|
||||
|
||||
[system.realview.l2x0_fake]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=520101888
|
||||
pio_latency=1000
|
||||
pio_size=4095
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.membus.master[4]
|
||||
|
||||
[system.realview.local_cpu_timer]
|
||||
type=CpuLocalTimer
|
||||
clock=1000
|
||||
gic=system.realview.gic
|
||||
int_num_timer=29
|
||||
int_num_watchdog=30
|
||||
pio_addr=520095232
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.membus.master[6]
|
||||
|
||||
[system.realview.mmc_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
ignore_access=false
|
||||
pio_addr=268455936
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.iobus.master[22]
|
||||
|
||||
[system.realview.nvmem]
|
||||
type=SimpleMemory
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
range=2147483648:2214592511
|
||||
zero=true
|
||||
port=system.membus.master[1]
|
||||
|
||||
[system.realview.realview_io]
|
||||
type=RealViewCtrl
|
||||
idreg=0
|
||||
pio_addr=268435456
|
||||
pio_latency=1000
|
||||
proc_id0=201326592
|
||||
proc_id1=201327138
|
||||
system=system
|
||||
pio=system.iobus.master[1]
|
||||
|
||||
[system.realview.rtc]
|
||||
type=PL031
|
||||
amba_id=3412017
|
||||
gic=system.realview.gic
|
||||
int_delay=100000
|
||||
int_num=42
|
||||
pio_addr=268529664
|
||||
pio_latency=1000
|
||||
system=system
|
||||
time=Thu Jan 1 00:00:00 2009
|
||||
pio=system.iobus.master[23]
|
||||
|
||||
[system.realview.sci_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
ignore_access=false
|
||||
pio_addr=268492800
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.iobus.master[20]
|
||||
|
||||
[system.realview.smc_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
ignore_access=false
|
||||
pio_addr=269357056
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.iobus.master[13]
|
||||
|
||||
[system.realview.sp810_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
ignore_access=true
|
||||
pio_addr=268439552
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.iobus.master[14]
|
||||
|
||||
[system.realview.ssp_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
ignore_access=false
|
||||
pio_addr=268488704
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.iobus.master[19]
|
||||
|
||||
[system.realview.timer0]
|
||||
type=Sp804
|
||||
amba_id=1316868
|
||||
clock0=1000000
|
||||
clock1=1000000
|
||||
gic=system.realview.gic
|
||||
int_num0=36
|
||||
int_num1=36
|
||||
pio_addr=268505088
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.iobus.master[2]
|
||||
|
||||
[system.realview.timer1]
|
||||
type=Sp804
|
||||
amba_id=1316868
|
||||
clock0=1000000
|
||||
clock1=1000000
|
||||
gic=system.realview.gic
|
||||
int_num0=37
|
||||
int_num1=37
|
||||
pio_addr=268509184
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.iobus.master[3]
|
||||
|
||||
[system.realview.uart]
|
||||
type=Pl011
|
||||
end_on_eot=false
|
||||
gic=system.realview.gic
|
||||
int_delay=100000
|
||||
int_num=44
|
||||
pio_addr=268472320
|
||||
pio_latency=1000
|
||||
platform=system.realview
|
||||
system=system
|
||||
terminal=system.terminal
|
||||
pio=system.iobus.master[0]
|
||||
|
||||
[system.realview.uart1_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
ignore_access=false
|
||||
pio_addr=268476416
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.iobus.master[10]
|
||||
|
||||
[system.realview.uart2_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
ignore_access=false
|
||||
pio_addr=268480512
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.iobus.master[11]
|
||||
|
||||
[system.realview.uart3_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
ignore_access=false
|
||||
pio_addr=268484608
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.iobus.master[12]
|
||||
|
||||
[system.realview.watchdog_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
ignore_access=false
|
||||
pio_addr=268500992
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.iobus.master[15]
|
||||
|
||||
[system.terminal]
|
||||
type=Terminal
|
||||
intr_control=system.intrctrl
|
||||
number=0
|
||||
output=true
|
||||
port=3456
|
||||
|
||||
[system.toL2Bus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
master=system.l2c.cpu_side
|
||||
slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port
|
||||
|
||||
[system.vncserver]
|
||||
type=VncServer
|
||||
frame_capture=false
|
||||
number=0
|
||||
port=5900
|
||||
|
||||
@ -0,0 +1,18 @@
|
||||
warn: Sockets disabled, not accepting vnc client connections
|
||||
warn: Sockets disabled, not accepting terminal connections
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: The clidr register always reports 0 caches.
|
||||
warn: clidr LoUIS field of 0b001 to match current ARM implementations.
|
||||
warn: The csselr register isn't implemented.
|
||||
warn: The ccsidr register isn't implemented and always reads as 0.
|
||||
warn: instruction 'mcr bpiallis' unimplemented
|
||||
warn: instruction 'mcr icialluis' unimplemented
|
||||
warn: instruction 'mcr dccimvac' unimplemented
|
||||
warn: instruction 'mcr dccmvau' unimplemented
|
||||
warn: instruction 'mcr icimvau' unimplemented
|
||||
warn: instruction 'mcr bpiallis' unimplemented
|
||||
warn: LCD dual screen mode not supported
|
||||
warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
|
||||
warn: instruction 'mcr icialluis' unimplemented
|
||||
warn: instruction 'mcr icialluis' unimplemented
|
||||
hack: be nice to actually delete the event here
|
||||
@ -0,0 +1,12 @@
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jun 4 2012 12:14:06
|
||||
gem5 started Jun 4 2012 17:26:08
|
||||
gem5 executing on zizzer
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
|
||||
info: Using bootloader at address 0x80000000
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 1169707043000 because m5_exit instruction encountered
|
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1 @@
|
||||
build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual FAILED!
|
||||
Binary file not shown.
@ -0,0 +1,672 @@
|
||||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
full_system=true
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
||||
[system]
|
||||
type=LinuxArmSystem
|
||||
children=bridge cf0 cpu intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver
|
||||
atags_addr=256
|
||||
boot_loader=/dist/m5/system/binaries/boot.arm
|
||||
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
|
||||
early_kernel_symbols=false
|
||||
flags_addr=268435504
|
||||
gic_cpu_addr=520093952
|
||||
init_param=0
|
||||
kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
|
||||
load_addr_mask=268435455
|
||||
machine_type=RealView_PBX
|
||||
mem_mode=timing
|
||||
memories=system.physmem system.realview.nvmem
|
||||
midr_regval=890224640
|
||||
num_work_ids=16
|
||||
readfile=tests/halt.sh
|
||||
symbolfile=
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.membus.slave[0]
|
||||
|
||||
[system.bridge]
|
||||
type=Bridge
|
||||
delay=50000
|
||||
nack_delay=4000
|
||||
ranges=268435456:520093695 1073741824:1610612735
|
||||
req_size=16
|
||||
resp_size=16
|
||||
write_ack=false
|
||||
master=system.iobus.slave[0]
|
||||
slave=system.membus.master[0]
|
||||
|
||||
[system.cf0]
|
||||
type=IdeDisk
|
||||
children=image
|
||||
delay=1000000
|
||||
driveID=master
|
||||
image=system.cf0.image
|
||||
|
||||
[system.cf0.image]
|
||||
type=CowDiskImage
|
||||
children=child
|
||||
child=system.cf0.image.child
|
||||
image_file=
|
||||
read_only=false
|
||||
table_size=65536
|
||||
|
||||
[system.cf0.image.child]
|
||||
type=RawDiskImage
|
||||
image_file=/dist/m5/system/disks/linux-arm-ael.img
|
||||
read_only=true
|
||||
|
||||
[system.cpu]
|
||||
type=TimingSimpleCPU
|
||||
children=dcache dtb icache interrupts itb tracer
|
||||
checker=Null
|
||||
clock=500
|
||||
cpu_id=0
|
||||
defer_registration=false
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
interrupts=system.cpu.interrupts
|
||||
itb=system.cpu.itb
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
phase=0
|
||||
profile=0
|
||||
progress_interval=0
|
||||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
workload=
|
||||
dcache_port=system.cpu.dcache.cpu_side
|
||||
icache_port=system.cpu.icache.cpu_side
|
||||
|
||||
[system.cpu.dcache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=4
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=32768
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=8
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.dcache_port
|
||||
mem_side=system.toL2Bus.slave[1]
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
size=64
|
||||
walker=system.cpu.dtb.walker
|
||||
|
||||
[system.cpu.dtb.walker]
|
||||
type=ArmTableWalker
|
||||
max_backoff=100000
|
||||
min_backoff=0
|
||||
sys=system
|
||||
port=system.toL2Bus.slave[3]
|
||||
|
||||
[system.cpu.icache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=1
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=32768
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=8
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.icache_port
|
||||
mem_side=system.toL2Bus.slave[0]
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=ArmInterrupts
|
||||
|
||||
[system.cpu.itb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
size=64
|
||||
walker=system.cpu.itb.walker
|
||||
|
||||
[system.cpu.itb.walker]
|
||||
type=ArmTableWalker
|
||||
max_backoff=100000
|
||||
min_backoff=0
|
||||
sys=system
|
||||
port=system.toL2Bus.slave[2]
|
||||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
|
||||
[system.intrctrl]
|
||||
type=IntrControl
|
||||
sys=system
|
||||
|
||||
[system.iobus]
|
||||
type=NoncoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side
|
||||
slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
|
||||
|
||||
[system.iocache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:268435455
|
||||
assoc=8
|
||||
block_size=64
|
||||
forward_snoops=false
|
||||
hash_delay=1
|
||||
is_top_level=false
|
||||
latency=50000
|
||||
max_miss_count=0
|
||||
mshrs=20
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=1024
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=12
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.iobus.master[25]
|
||||
mem_side=system.membus.slave[1]
|
||||
|
||||
[system.l2c]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=8
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=false
|
||||
latency=10000
|
||||
max_miss_count=0
|
||||
mshrs=92
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=4194304
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=16
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.toL2Bus.master[0]
|
||||
mem_side=system.membus.slave[2]
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
children=badaddr_responder
|
||||
block_size=64
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
default=system.membus.badaddr_responder.pio
|
||||
master=system.bridge.slave system.realview.nvmem.port[0] system.physmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio
|
||||
slave=system.system_port system.iocache.mem_side system.l2c.mem_side
|
||||
|
||||
[system.membus.badaddr_responder]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=0
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=true
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=warn
|
||||
pio=system.membus.default
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
conf_table_reported=true
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.membus.master[2]
|
||||
|
||||
[system.realview]
|
||||
type=RealView
|
||||
children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
|
||||
intrctrl=system.intrctrl
|
||||
max_mem_size=268435456
|
||||
mem_start_addr=0
|
||||
pci_cfg_base=0
|
||||
system=system
|
||||
|
||||
[system.realview.a9scu]
|
||||
type=A9SCU
|
||||
pio_addr=520093696
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.membus.master[5]
|
||||
|
||||
[system.realview.aaci_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
ignore_access=false
|
||||
pio_addr=268451840
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.iobus.master[21]
|
||||
|
||||
[system.realview.cf_ctrl]
|
||||
type=IdeController
|
||||
BAR0=402653184
|
||||
BAR0LegacyIO=true
|
||||
BAR0Size=16
|
||||
BAR1=402653440
|
||||
BAR1LegacyIO=true
|
||||
BAR1Size=1
|
||||
BAR2=1
|
||||
BAR2LegacyIO=false
|
||||
BAR2Size=8
|
||||
BAR3=1
|
||||
BAR3LegacyIO=false
|
||||
BAR3Size=4
|
||||
BAR4=1
|
||||
BAR4LegacyIO=false
|
||||
BAR4Size=16
|
||||
BAR5=1
|
||||
BAR5LegacyIO=false
|
||||
BAR5Size=0
|
||||
BIST=0
|
||||
CacheLineSize=0
|
||||
CardbusCIS=0
|
||||
ClassCode=1
|
||||
Command=1
|
||||
DeviceID=28945
|
||||
ExpansionROM=0
|
||||
HeaderType=0
|
||||
InterruptLine=31
|
||||
InterruptPin=1
|
||||
LatencyTimer=0
|
||||
MaximumLatency=0
|
||||
MinimumGrant=0
|
||||
ProgIF=133
|
||||
Revision=0
|
||||
Status=640
|
||||
SubClassCode=1
|
||||
SubsystemID=0
|
||||
SubsystemVendorID=0
|
||||
VendorID=32902
|
||||
config_latency=20000
|
||||
ctrl_offset=2
|
||||
disks=system.cf0
|
||||
io_shift=1
|
||||
max_backoff_delay=10000000
|
||||
min_backoff_delay=4000
|
||||
pci_bus=2
|
||||
pci_dev=7
|
||||
pci_func=0
|
||||
pio_latency=1000
|
||||
platform=system.realview
|
||||
system=system
|
||||
config=system.iobus.master[8]
|
||||
dma=system.iobus.slave[2]
|
||||
pio=system.iobus.master[7]
|
||||
|
||||
[system.realview.clcd]
|
||||
type=Pl111
|
||||
amba_id=1315089
|
||||
clock=41667
|
||||
gic=system.realview.gic
|
||||
int_num=55
|
||||
max_backoff_delay=10000000
|
||||
min_backoff_delay=4000
|
||||
pio_addr=268566528
|
||||
pio_latency=10000
|
||||
system=system
|
||||
vnc=system.vncserver
|
||||
dma=system.iobus.slave[1]
|
||||
pio=system.iobus.master[4]
|
||||
|
||||
[system.realview.dmac_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
ignore_access=false
|
||||
pio_addr=268632064
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.iobus.master[9]
|
||||
|
||||
[system.realview.flash_fake]
|
||||
type=IsaFake
|
||||
fake_mem=true
|
||||
pio_addr=1073741824
|
||||
pio_latency=1000
|
||||
pio_size=536870912
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[24]
|
||||
|
||||
[system.realview.gic]
|
||||
type=Gic
|
||||
cpu_addr=520093952
|
||||
cpu_pio_delay=10000
|
||||
dist_addr=520097792
|
||||
dist_pio_delay=10000
|
||||
int_latency=10000
|
||||
it_lines=128
|
||||
platform=system.realview
|
||||
system=system
|
||||
pio=system.membus.master[3]
|
||||
|
||||
[system.realview.gpio0_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
ignore_access=false
|
||||
pio_addr=268513280
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.iobus.master[16]
|
||||
|
||||
[system.realview.gpio1_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
ignore_access=false
|
||||
pio_addr=268517376
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.iobus.master[17]
|
||||
|
||||
[system.realview.gpio2_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
ignore_access=false
|
||||
pio_addr=268521472
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.iobus.master[18]
|
||||
|
||||
[system.realview.kmi0]
|
||||
type=Pl050
|
||||
amba_id=1314896
|
||||
gic=system.realview.gic
|
||||
int_delay=1000000
|
||||
int_num=52
|
||||
is_mouse=false
|
||||
pio_addr=268460032
|
||||
pio_latency=1000
|
||||
system=system
|
||||
vnc=system.vncserver
|
||||
pio=system.iobus.master[5]
|
||||
|
||||
[system.realview.kmi1]
|
||||
type=Pl050
|
||||
amba_id=1314896
|
||||
gic=system.realview.gic
|
||||
int_delay=1000000
|
||||
int_num=53
|
||||
is_mouse=true
|
||||
pio_addr=268464128
|
||||
pio_latency=1000
|
||||
system=system
|
||||
vnc=system.vncserver
|
||||
pio=system.iobus.master[6]
|
||||
|
||||
[system.realview.l2x0_fake]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=520101888
|
||||
pio_latency=1000
|
||||
pio_size=4095
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.membus.master[4]
|
||||
|
||||
[system.realview.local_cpu_timer]
|
||||
type=CpuLocalTimer
|
||||
clock=1000
|
||||
gic=system.realview.gic
|
||||
int_num_timer=29
|
||||
int_num_watchdog=30
|
||||
pio_addr=520095232
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.membus.master[6]
|
||||
|
||||
[system.realview.mmc_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
ignore_access=false
|
||||
pio_addr=268455936
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.iobus.master[22]
|
||||
|
||||
[system.realview.nvmem]
|
||||
type=SimpleMemory
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
range=2147483648:2214592511
|
||||
zero=true
|
||||
port=system.membus.master[1]
|
||||
|
||||
[system.realview.realview_io]
|
||||
type=RealViewCtrl
|
||||
idreg=0
|
||||
pio_addr=268435456
|
||||
pio_latency=1000
|
||||
proc_id0=201326592
|
||||
proc_id1=201327138
|
||||
system=system
|
||||
pio=system.iobus.master[1]
|
||||
|
||||
[system.realview.rtc]
|
||||
type=PL031
|
||||
amba_id=3412017
|
||||
gic=system.realview.gic
|
||||
int_delay=100000
|
||||
int_num=42
|
||||
pio_addr=268529664
|
||||
pio_latency=1000
|
||||
system=system
|
||||
time=Thu Jan 1 00:00:00 2009
|
||||
pio=system.iobus.master[23]
|
||||
|
||||
[system.realview.sci_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
ignore_access=false
|
||||
pio_addr=268492800
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.iobus.master[20]
|
||||
|
||||
[system.realview.smc_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
ignore_access=false
|
||||
pio_addr=269357056
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.iobus.master[13]
|
||||
|
||||
[system.realview.sp810_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
ignore_access=true
|
||||
pio_addr=268439552
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.iobus.master[14]
|
||||
|
||||
[system.realview.ssp_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
ignore_access=false
|
||||
pio_addr=268488704
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.iobus.master[19]
|
||||
|
||||
[system.realview.timer0]
|
||||
type=Sp804
|
||||
amba_id=1316868
|
||||
clock0=1000000
|
||||
clock1=1000000
|
||||
gic=system.realview.gic
|
||||
int_num0=36
|
||||
int_num1=36
|
||||
pio_addr=268505088
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.iobus.master[2]
|
||||
|
||||
[system.realview.timer1]
|
||||
type=Sp804
|
||||
amba_id=1316868
|
||||
clock0=1000000
|
||||
clock1=1000000
|
||||
gic=system.realview.gic
|
||||
int_num0=37
|
||||
int_num1=37
|
||||
pio_addr=268509184
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.iobus.master[3]
|
||||
|
||||
[system.realview.uart]
|
||||
type=Pl011
|
||||
end_on_eot=false
|
||||
gic=system.realview.gic
|
||||
int_delay=100000
|
||||
int_num=44
|
||||
pio_addr=268472320
|
||||
pio_latency=1000
|
||||
platform=system.realview
|
||||
system=system
|
||||
terminal=system.terminal
|
||||
pio=system.iobus.master[0]
|
||||
|
||||
[system.realview.uart1_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
ignore_access=false
|
||||
pio_addr=268476416
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.iobus.master[10]
|
||||
|
||||
[system.realview.uart2_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
ignore_access=false
|
||||
pio_addr=268480512
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.iobus.master[11]
|
||||
|
||||
[system.realview.uart3_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
ignore_access=false
|
||||
pio_addr=268484608
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.iobus.master[12]
|
||||
|
||||
[system.realview.watchdog_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
ignore_access=false
|
||||
pio_addr=268500992
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.iobus.master[15]
|
||||
|
||||
[system.terminal]
|
||||
type=Terminal
|
||||
intr_control=system.intrctrl
|
||||
number=0
|
||||
output=true
|
||||
port=3456
|
||||
|
||||
[system.toL2Bus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
master=system.l2c.cpu_side
|
||||
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
|
||||
|
||||
[system.vncserver]
|
||||
type=VncServer
|
||||
frame_capture=false
|
||||
number=0
|
||||
port=5900
|
||||
|
||||
@ -0,0 +1,17 @@
|
||||
warn: Sockets disabled, not accepting vnc client connections
|
||||
warn: Sockets disabled, not accepting terminal connections
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: The clidr register always reports 0 caches.
|
||||
warn: clidr LoUIS field of 0b001 to match current ARM implementations.
|
||||
warn: The csselr register isn't implemented.
|
||||
warn: The ccsidr register isn't implemented and always reads as 0.
|
||||
warn: instruction 'mcr bpiallis' unimplemented
|
||||
warn: instruction 'mcr icialluis' unimplemented
|
||||
warn: instruction 'mcr dccimvac' unimplemented
|
||||
warn: instruction 'mcr dccmvau' unimplemented
|
||||
warn: instruction 'mcr icimvau' unimplemented
|
||||
warn: LCD dual screen mode not supported
|
||||
warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
|
||||
warn: instruction 'mcr icialluis' unimplemented
|
||||
warn: instruction 'mcr bpiallis' unimplemented
|
||||
hack: be nice to actually delete the event here
|
||||
@ -0,0 +1,12 @@
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jun 4 2012 12:14:06
|
||||
gem5 started Jun 4 2012 17:25:42
|
||||
gem5 executing on zizzer
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
|
||||
info: Using bootloader at address 0x80000000
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 2591419000000 because m5_exit instruction encountered
|
||||
@ -0,0 +1,622 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 2.591419 # Number of seconds simulated
|
||||
sim_ticks 2591419000000 # Number of ticks simulated
|
||||
final_tick 2591419000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 555808 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 709857 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 24337050134 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 383104 # Number of bytes of host memory used
|
||||
host_seconds 106.48 # Real time elapsed on the host
|
||||
sim_insts 59182652 # Number of instructions simulated
|
||||
sim_ops 75585847 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::realview.clcd 122683392 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.dtb.walker 1408 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.itb.walker 768 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.inst 955744 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 9990864 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 133632176 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 955744 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 955744 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 6584000 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 9600072 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::realview.clcd 15335424 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.dtb.walker 22 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.itb.walker 12 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.inst 21136 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 156141 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 15512735 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 102875 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 856893 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::realview.clcd 47342167 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.dtb.walker 543 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.itb.walker 296 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 368811 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 3855364 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 51567182 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 368811 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 368811 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 2540693 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::cpu.data 1163869 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 3704562 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 2540693 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::realview.clcd 47342167 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.dtb.walker 543 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.itb.walker 296 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 368811 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 5019233 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 55271744 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory
|
||||
system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
|
||||
system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory
|
||||
system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
|
||||
system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory
|
||||
system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
|
||||
system.realview.nvmem.bw_read::cpu.inst 8 # Total read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_inst_read::cpu.inst 8 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.l2c.replacements 117210 # number of replacements
|
||||
system.l2c.tagsinuse 24850.634634 # Cycle average of tags in use
|
||||
system.l2c.total_refs 1536782 # Total number of references to valid blocks.
|
||||
system.l2c.sampled_refs 146347 # Sample count of references to valid blocks.
|
||||
system.l2c.avg_refs 10.500946 # Average number of references to valid blocks.
|
||||
system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.l2c.occ_blocks::writebacks 14582.980264 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu.dtb.walker 6.964045 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu.itb.walker 0.968003 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu.inst 5130.485110 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu.data 5129.237211 # Average occupied blocks per requestor
|
||||
system.l2c.occ_percent::writebacks 0.222519 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu.dtb.walker 0.000106 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu.itb.walker 0.000015 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu.inst 0.078285 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu.data 0.078266 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::total 0.379191 # Average percentage of cache occupancy
|
||||
system.l2c.ReadReq_hits::cpu.dtb.walker 8714 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu.itb.walker 3541 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu.inst 839785 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu.data 361146 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::total 1213186 # number of ReadReq hits
|
||||
system.l2c.Writeback_hits::writebacks 611793 # number of Writeback hits
|
||||
system.l2c.Writeback_hits::total 611793 # number of Writeback hits
|
||||
system.l2c.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits
|
||||
system.l2c.UpgradeReq_hits::total 26 # number of UpgradeReq hits
|
||||
system.l2c.ReadExReq_hits::cpu.data 106840 # number of ReadExReq hits
|
||||
system.l2c.ReadExReq_hits::total 106840 # number of ReadExReq hits
|
||||
system.l2c.demand_hits::cpu.dtb.walker 8714 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu.itb.walker 3541 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu.inst 839785 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu.data 467986 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::total 1320026 # number of demand (read+write) hits
|
||||
system.l2c.overall_hits::cpu.dtb.walker 8714 # number of overall hits
|
||||
system.l2c.overall_hits::cpu.itb.walker 3541 # number of overall hits
|
||||
system.l2c.overall_hits::cpu.inst 839785 # number of overall hits
|
||||
system.l2c.overall_hits::cpu.data 467986 # number of overall hits
|
||||
system.l2c.overall_hits::total 1320026 # number of overall hits
|
||||
system.l2c.ReadReq_misses::cpu.dtb.walker 22 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu.itb.walker 12 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu.inst 14520 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu.data 16989 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::total 31543 # number of ReadReq misses
|
||||
system.l2c.UpgradeReq_misses::cpu.data 2871 # number of UpgradeReq misses
|
||||
system.l2c.UpgradeReq_misses::total 2871 # number of UpgradeReq misses
|
||||
system.l2c.ReadExReq_misses::cpu.data 140746 # number of ReadExReq misses
|
||||
system.l2c.ReadExReq_misses::total 140746 # number of ReadExReq misses
|
||||
system.l2c.demand_misses::cpu.dtb.walker 22 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu.itb.walker 12 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu.inst 14520 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu.data 157735 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::total 172289 # number of demand (read+write) misses
|
||||
system.l2c.overall_misses::cpu.dtb.walker 22 # number of overall misses
|
||||
system.l2c.overall_misses::cpu.itb.walker 12 # number of overall misses
|
||||
system.l2c.overall_misses::cpu.inst 14520 # number of overall misses
|
||||
system.l2c.overall_misses::cpu.data 157735 # number of overall misses
|
||||
system.l2c.overall_misses::total 172289 # number of overall misses
|
||||
system.l2c.ReadReq_miss_latency::cpu.dtb.walker 1144000 # number of ReadReq miss cycles
|
||||
system.l2c.ReadReq_miss_latency::cpu.itb.walker 624000 # number of ReadReq miss cycles
|
||||
system.l2c.ReadReq_miss_latency::cpu.inst 758001000 # number of ReadReq miss cycles
|
||||
system.l2c.ReadReq_miss_latency::cpu.data 885358500 # number of ReadReq miss cycles
|
||||
system.l2c.ReadReq_miss_latency::total 1645127500 # number of ReadReq miss cycles
|
||||
system.l2c.UpgradeReq_miss_latency::cpu.data 1040000 # number of UpgradeReq miss cycles
|
||||
system.l2c.UpgradeReq_miss_latency::total 1040000 # number of UpgradeReq miss cycles
|
||||
system.l2c.ReadExReq_miss_latency::cpu.data 7328827500 # number of ReadExReq miss cycles
|
||||
system.l2c.ReadExReq_miss_latency::total 7328827500 # number of ReadExReq miss cycles
|
||||
system.l2c.demand_miss_latency::cpu.dtb.walker 1144000 # number of demand (read+write) miss cycles
|
||||
system.l2c.demand_miss_latency::cpu.itb.walker 624000 # number of demand (read+write) miss cycles
|
||||
system.l2c.demand_miss_latency::cpu.inst 758001000 # number of demand (read+write) miss cycles
|
||||
system.l2c.demand_miss_latency::cpu.data 8214186000 # number of demand (read+write) miss cycles
|
||||
system.l2c.demand_miss_latency::total 8973955000 # number of demand (read+write) miss cycles
|
||||
system.l2c.overall_miss_latency::cpu.dtb.walker 1144000 # number of overall miss cycles
|
||||
system.l2c.overall_miss_latency::cpu.itb.walker 624000 # number of overall miss cycles
|
||||
system.l2c.overall_miss_latency::cpu.inst 758001000 # number of overall miss cycles
|
||||
system.l2c.overall_miss_latency::cpu.data 8214186000 # number of overall miss cycles
|
||||
system.l2c.overall_miss_latency::total 8973955000 # number of overall miss cycles
|
||||
system.l2c.ReadReq_accesses::cpu.dtb.walker 8736 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::cpu.itb.walker 3553 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::cpu.inst 854305 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::cpu.data 378135 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::total 1244729 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.Writeback_accesses::writebacks 611793 # number of Writeback accesses(hits+misses)
|
||||
system.l2c.Writeback_accesses::total 611793 # number of Writeback accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_accesses::cpu.data 2897 # number of UpgradeReq accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_accesses::total 2897 # number of UpgradeReq accesses(hits+misses)
|
||||
system.l2c.ReadExReq_accesses::cpu.data 247586 # number of ReadExReq accesses(hits+misses)
|
||||
system.l2c.ReadExReq_accesses::total 247586 # number of ReadExReq accesses(hits+misses)
|
||||
system.l2c.demand_accesses::cpu.dtb.walker 8736 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu.itb.walker 3553 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu.inst 854305 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu.data 625721 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::total 1492315 # number of demand (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu.dtb.walker 8736 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu.itb.walker 3553 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu.inst 854305 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu.data 625721 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::total 1492315 # number of overall (read+write) accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.002518 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.003377 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu.inst 0.016996 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu.data 0.044928 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::total 0.025341 # miss rate for ReadReq accesses
|
||||
system.l2c.UpgradeReq_miss_rate::cpu.data 0.991025 # miss rate for UpgradeReq accesses
|
||||
system.l2c.UpgradeReq_miss_rate::total 0.991025 # miss rate for UpgradeReq accesses
|
||||
system.l2c.ReadExReq_miss_rate::cpu.data 0.568473 # miss rate for ReadExReq accesses
|
||||
system.l2c.ReadExReq_miss_rate::total 0.568473 # miss rate for ReadExReq accesses
|
||||
system.l2c.demand_miss_rate::cpu.dtb.walker 0.002518 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu.itb.walker 0.003377 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu.inst 0.016996 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu.data 0.252085 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::total 0.115451 # miss rate for demand accesses
|
||||
system.l2c.overall_miss_rate::cpu.dtb.walker 0.002518 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu.itb.walker 0.003377 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu.inst 0.016996 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu.data 0.252085 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::total 0.115451 # miss rate for overall accesses
|
||||
system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52000 # average ReadReq miss latency
|
||||
system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 52000 # average ReadReq miss latency
|
||||
system.l2c.ReadReq_avg_miss_latency::cpu.inst 52203.925620 # average ReadReq miss latency
|
||||
system.l2c.ReadReq_avg_miss_latency::cpu.data 52113.632350 # average ReadReq miss latency
|
||||
system.l2c.ReadReq_avg_miss_latency::total 52155.074026 # average ReadReq miss latency
|
||||
system.l2c.UpgradeReq_avg_miss_latency::cpu.data 362.243121 # average UpgradeReq miss latency
|
||||
system.l2c.UpgradeReq_avg_miss_latency::total 362.243121 # average UpgradeReq miss latency
|
||||
system.l2c.ReadExReq_avg_miss_latency::cpu.data 52071.302204 # average ReadExReq miss latency
|
||||
system.l2c.ReadExReq_avg_miss_latency::total 52071.302204 # average ReadExReq miss latency
|
||||
system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52000 # average overall miss latency
|
||||
system.l2c.demand_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency
|
||||
system.l2c.demand_avg_miss_latency::cpu.inst 52203.925620 # average overall miss latency
|
||||
system.l2c.demand_avg_miss_latency::cpu.data 52075.861413 # average overall miss latency
|
||||
system.l2c.demand_avg_miss_latency::total 52086.639310 # average overall miss latency
|
||||
system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52000 # average overall miss latency
|
||||
system.l2c.overall_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency
|
||||
system.l2c.overall_avg_miss_latency::cpu.inst 52203.925620 # average overall miss latency
|
||||
system.l2c.overall_avg_miss_latency::cpu.data 52075.861413 # average overall miss latency
|
||||
system.l2c.overall_avg_miss_latency::total 52086.639310 # average overall miss latency
|
||||
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.l2c.fast_writes 0 # number of fast writes performed
|
||||
system.l2c.cache_copies 0 # number of cache copies performed
|
||||
system.l2c.writebacks::writebacks 102875 # number of writebacks
|
||||
system.l2c.writebacks::total 102875 # number of writebacks
|
||||
system.l2c.ReadReq_mshr_misses::cpu.dtb.walker 22 # number of ReadReq MSHR misses
|
||||
system.l2c.ReadReq_mshr_misses::cpu.itb.walker 12 # number of ReadReq MSHR misses
|
||||
system.l2c.ReadReq_mshr_misses::cpu.inst 14520 # number of ReadReq MSHR misses
|
||||
system.l2c.ReadReq_mshr_misses::cpu.data 16989 # number of ReadReq MSHR misses
|
||||
system.l2c.ReadReq_mshr_misses::total 31543 # number of ReadReq MSHR misses
|
||||
system.l2c.UpgradeReq_mshr_misses::cpu.data 2871 # number of UpgradeReq MSHR misses
|
||||
system.l2c.UpgradeReq_mshr_misses::total 2871 # number of UpgradeReq MSHR misses
|
||||
system.l2c.ReadExReq_mshr_misses::cpu.data 140746 # number of ReadExReq MSHR misses
|
||||
system.l2c.ReadExReq_mshr_misses::total 140746 # number of ReadExReq MSHR misses
|
||||
system.l2c.demand_mshr_misses::cpu.dtb.walker 22 # number of demand (read+write) MSHR misses
|
||||
system.l2c.demand_mshr_misses::cpu.itb.walker 12 # number of demand (read+write) MSHR misses
|
||||
system.l2c.demand_mshr_misses::cpu.inst 14520 # number of demand (read+write) MSHR misses
|
||||
system.l2c.demand_mshr_misses::cpu.data 157735 # number of demand (read+write) MSHR misses
|
||||
system.l2c.demand_mshr_misses::total 172289 # number of demand (read+write) MSHR misses
|
||||
system.l2c.overall_mshr_misses::cpu.dtb.walker 22 # number of overall MSHR misses
|
||||
system.l2c.overall_mshr_misses::cpu.itb.walker 12 # number of overall MSHR misses
|
||||
system.l2c.overall_mshr_misses::cpu.inst 14520 # number of overall MSHR misses
|
||||
system.l2c.overall_mshr_misses::cpu.data 157735 # number of overall MSHR misses
|
||||
system.l2c.overall_mshr_misses::total 172289 # number of overall MSHR misses
|
||||
system.l2c.ReadReq_mshr_miss_latency::cpu.dtb.walker 880000 # number of ReadReq MSHR miss cycles
|
||||
system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker 480000 # number of ReadReq MSHR miss cycles
|
||||
system.l2c.ReadReq_mshr_miss_latency::cpu.inst 583755000 # number of ReadReq MSHR miss cycles
|
||||
system.l2c.ReadReq_mshr_miss_latency::cpu.data 681490000 # number of ReadReq MSHR miss cycles
|
||||
system.l2c.ReadReq_mshr_miss_latency::total 1266605000 # number of ReadReq MSHR miss cycles
|
||||
system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 114997000 # number of UpgradeReq MSHR miss cycles
|
||||
system.l2c.UpgradeReq_mshr_miss_latency::total 114997000 # number of UpgradeReq MSHR miss cycles
|
||||
system.l2c.ReadExReq_mshr_miss_latency::cpu.data 5639875000 # number of ReadExReq MSHR miss cycles
|
||||
system.l2c.ReadExReq_mshr_miss_latency::total 5639875000 # number of ReadExReq MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_latency::cpu.dtb.walker 880000 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_latency::cpu.itb.walker 480000 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_latency::cpu.inst 583755000 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_latency::cpu.data 6321365000 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_latency::total 6906480000 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency::cpu.dtb.walker 880000 # number of overall MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency::cpu.itb.walker 480000 # number of overall MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency::cpu.inst 583755000 # number of overall MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency::cpu.data 6321365000 # number of overall MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency::total 6906480000 # number of overall MSHR miss cycles
|
||||
system.l2c.ReadReq_mshr_uncacheable_latency::cpu.inst 264840000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 131544749000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.l2c.ReadReq_mshr_uncacheable_latency::total 131809589000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 31207839500 # number of WriteReq MSHR uncacheable cycles
|
||||
system.l2c.WriteReq_mshr_uncacheable_latency::total 31207839500 # number of WriteReq MSHR uncacheable cycles
|
||||
system.l2c.overall_mshr_uncacheable_latency::cpu.inst 264840000 # number of overall MSHR uncacheable cycles
|
||||
system.l2c.overall_mshr_uncacheable_latency::cpu.data 162752588500 # number of overall MSHR uncacheable cycles
|
||||
system.l2c.overall_mshr_uncacheable_latency::total 163017428500 # number of overall MSHR uncacheable cycles
|
||||
system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.002518 # mshr miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.003377 # mshr miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.016996 # mshr miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.044928 # mshr miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_mshr_miss_rate::total 0.025341 # mshr miss rate for ReadReq accesses
|
||||
system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.991025 # mshr miss rate for UpgradeReq accesses
|
||||
system.l2c.UpgradeReq_mshr_miss_rate::total 0.991025 # mshr miss rate for UpgradeReq accesses
|
||||
system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.568473 # mshr miss rate for ReadExReq accesses
|
||||
system.l2c.ReadExReq_mshr_miss_rate::total 0.568473 # mshr miss rate for ReadExReq accesses
|
||||
system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.002518 # mshr miss rate for demand accesses
|
||||
system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.003377 # mshr miss rate for demand accesses
|
||||
system.l2c.demand_mshr_miss_rate::cpu.inst 0.016996 # mshr miss rate for demand accesses
|
||||
system.l2c.demand_mshr_miss_rate::cpu.data 0.252085 # mshr miss rate for demand accesses
|
||||
system.l2c.demand_mshr_miss_rate::total 0.115451 # mshr miss rate for demand accesses
|
||||
system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.002518 # mshr miss rate for overall accesses
|
||||
system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.003377 # mshr miss rate for overall accesses
|
||||
system.l2c.overall_mshr_miss_rate::cpu.inst 0.016996 # mshr miss rate for overall accesses
|
||||
system.l2c.overall_mshr_miss_rate::cpu.data 0.252085 # mshr miss rate for overall accesses
|
||||
system.l2c.overall_mshr_miss_rate::total 0.115451 # mshr miss rate for overall accesses
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average ReadReq mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40000 # average ReadReq mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40203.512397 # average ReadReq mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40113.602920 # average ReadReq mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::total 40154.867958 # average ReadReq mshr miss latency
|
||||
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40054.684779 # average UpgradeReq mshr miss latency
|
||||
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40054.684779 # average UpgradeReq mshr miss latency
|
||||
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40071.298651 # average ReadExReq mshr miss latency
|
||||
system.l2c.ReadExReq_avg_mshr_miss_latency::total 40071.298651 # average ReadExReq mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40203.512397 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu.data 40075.855073 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::total 40086.598680 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40203.512397 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu.data 40075.855073 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::total 40086.598680 # average overall mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
|
||||
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
|
||||
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
||||
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
|
||||
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
||||
system.l2c.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
|
||||
system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
|
||||
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
||||
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
||||
system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
|
||||
system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
|
||||
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
|
||||
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
|
||||
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
|
||||
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.dtb.read_hits 14995950 # DTB read hits
|
||||
system.cpu.dtb.read_misses 7342 # DTB read misses
|
||||
system.cpu.dtb.write_hits 11230967 # DTB write hits
|
||||
system.cpu.dtb.write_misses 2209 # DTB write misses
|
||||
system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed
|
||||
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
|
||||
system.cpu.dtb.flush_entries 3488 # Number of entries that have been flushed from TLB
|
||||
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.dtb.prefetch_faults 184 # Number of TLB faults due to prefetch
|
||||
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.dtb.read_accesses 15003292 # DTB read accesses
|
||||
system.cpu.dtb.write_accesses 11233176 # DTB write accesses
|
||||
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
|
||||
system.cpu.dtb.hits 26226917 # DTB hits
|
||||
system.cpu.dtb.misses 9551 # DTB misses
|
||||
system.cpu.dtb.accesses 26236468 # DTB accesses
|
||||
system.cpu.itb.inst_hits 60464458 # ITB inst hits
|
||||
system.cpu.itb.inst_misses 4471 # ITB inst misses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.write_hits 0 # DTB write hits
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed
|
||||
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
|
||||
system.cpu.itb.flush_entries 2343 # Number of entries that have been flushed from TLB
|
||||
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.itb.inst_accesses 60468929 # ITB inst accesses
|
||||
system.cpu.itb.hits 60464458 # DTB hits
|
||||
system.cpu.itb.misses 4471 # DTB misses
|
||||
system.cpu.itb.accesses 60468929 # DTB accesses
|
||||
system.cpu.numCycles 5182838000 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 59182652 # Number of instructions committed
|
||||
system.cpu.committedOps 75585847 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 68355333 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 1976025 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 7653656 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 68355333 # number of integer instructions
|
||||
system.cpu.num_fp_insts 10269 # number of float instructions
|
||||
system.cpu.num_int_register_reads 391421263 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 73137347 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written
|
||||
system.cpu.num_mem_refs 27394170 # number of memory refs
|
||||
system.cpu.num_load_insts 15659823 # Number of load instructions
|
||||
system.cpu.num_store_insts 11734347 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 4573988502.570235 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 608849497.429765 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 0.117474 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0.882526 # Percentage of idle cycles
|
||||
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
||||
system.cpu.kern.inst.quiesce 82997 # number of quiesce instructions executed
|
||||
system.cpu.icache.replacements 855402 # number of replacements
|
||||
system.cpu.icache.tagsinuse 510.943261 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 59608544 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 855914 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 69.643146 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 18524424000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 510.943261 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.997936 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.997936 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 59608544 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 59608544 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 59608544 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 59608544 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 59608544 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 59608544 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 855914 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 855914 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 855914 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 855914 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 855914 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 855914 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 12584924000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 12584924000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 12584924000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 12584924000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 12584924000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 12584924000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 60464458 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 60464458 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 60464458 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 60464458 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 60464458 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 60464458 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014156 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.014156 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.014156 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.014156 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.014156 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.014156 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14703.491239 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 14703.491239 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 14703.491239 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 14703.491239 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 14703.491239 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 14703.491239 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks::writebacks 45705 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 45705 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 855914 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 855914 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 855914 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 855914 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 855914 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 855914 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10014791000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 10014791000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10014791000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 10014791000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10014791000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 10014791000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 350913000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 350913000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 350913000 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency::total 350913000 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014156 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014156 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014156 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.014156 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014156 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.014156 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11700.697734 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11700.697734 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11700.697734 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 11700.697734 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11700.697734 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 11700.697734 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 627094 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 511.875591 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 23655637 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 627606 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 37.691859 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 660309000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 511.875591 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.999757 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.999757 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 13195546 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 13195546 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 9973168 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 9973168 # number of WriteReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::cpu.data 236327 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::total 236327 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::cpu.data 247699 # number of StoreCondReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::total 247699 # number of StoreCondReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 23168714 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 23168714 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 23168714 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 23168714 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 368647 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 368647 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 250483 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 250483 # number of WriteReq misses
|
||||
system.cpu.dcache.LoadLockedReq_misses::cpu.data 11373 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.LoadLockedReq_misses::total 11373 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 619130 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 619130 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 619130 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 619130 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 5836151500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 5836151500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 9546175500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 9546175500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 185299500 # number of LoadLockedReq miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_miss_latency::total 185299500 # number of LoadLockedReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 15382327000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 15382327000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 15382327000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 15382327000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 13564193 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 13564193 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 10223651 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 10223651 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247700 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::total 247700 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::cpu.data 247699 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::total 247699 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 23787844 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 23787844 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 23787844 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 23787844 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.027178 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.027178 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024500 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.024500 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045914 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045914 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.026027 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.026027 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.026027 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.026027 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15831.273549 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 15831.273549 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38111.071410 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 38111.071410 # average WriteReq miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16292.930625 # average LoadLockedReq miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16292.930625 # average LoadLockedReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 24845.068079 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 24845.068079 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 24845.068079 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 24845.068079 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 566088 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 566088 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 368647 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 368647 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250483 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 250483 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11373 # number of LoadLockedReq MSHR misses
|
||||
system.cpu.dcache.LoadLockedReq_mshr_misses::total 11373 # number of LoadLockedReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 619130 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 619130 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 619130 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 619130 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4730079000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 4730079000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8794683000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 8794683000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 151180500 # number of LoadLockedReq MSHR miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 151180500 # number of LoadLockedReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13524762000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 13524762000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13524762000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 13524762000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 146938040000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 146938040000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 40368528500 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 40368528500 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 187306568500 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency::total 187306568500 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027178 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027178 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024500 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024500 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.045914 # mshr miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.045914 # mshr miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026027 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.026027 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026027 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.026027 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12830.916839 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12830.916839 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35110.897746 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35110.897746 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13292.930625 # average LoadLockedReq mshr miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13292.930625 # average LoadLockedReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21844.785425 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 21844.785425 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21844.785425 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 21844.785425 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.iocache.replacements 0 # number of replacements
|
||||
system.iocache.tagsinuse 0 # Cycle average of tags in use
|
||||
system.iocache.total_refs 0 # Total number of references to valid blocks.
|
||||
system.iocache.sampled_refs 0 # Sample count of references to valid blocks.
|
||||
system.iocache.avg_refs nan # Average number of references to valid blocks.
|
||||
system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.iocache.fast_writes 0 # number of fast writes performed
|
||||
system.iocache.cache_copies 0 # number of cache copies performed
|
||||
system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1342278175263 # number of ReadReq MSHR uncacheable cycles
|
||||
system.iocache.ReadReq_mshr_uncacheable_latency::total 1342278175263 # number of ReadReq MSHR uncacheable cycles
|
||||
system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1342278175263 # number of overall MSHR uncacheable cycles
|
||||
system.iocache.overall_mshr_uncacheable_latency::total 1342278175263 # number of overall MSHR uncacheable cycles
|
||||
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
|
||||
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
||||
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
|
||||
system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
||||
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
@ -0,0 +1 @@
|
||||
build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing FAILED!
|
||||
Binary file not shown.
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,9 @@
|
||||
warn: Sockets disabled, not accepting terminal connections
|
||||
warn: Reading current count from inactive timer.
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: Don't know what interrupt to clear for console.
|
||||
warn: instruction 'fxsave' unimplemented
|
||||
warn: Tried to clear PCI interrupt 14
|
||||
warn: Unknown mouse command 0xe1.
|
||||
warn: instruction 'wbinvd' unimplemented
|
||||
hack: be nice to actually delete the event here
|
||||
@ -0,0 +1,13 @@
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jun 4 2012 13:44:28
|
||||
gem5 started Jun 4 2012 15:04:41
|
||||
gem5 executing on zizzer
|
||||
command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-atomic -re tests/run.py build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-atomic
|
||||
warning: add_child('terminal'): child 'terminal' already has parent
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
|
||||
0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 5112043255000 because m5_exit instruction encountered
|
||||
@ -0,0 +1,426 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 5.112043 # Number of seconds simulated
|
||||
sim_ticks 5112043255000 # Number of ticks simulated
|
||||
final_tick 5112043255000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1304311 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2670670 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 33369516688 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 357276 # Number of bytes of host memory used
|
||||
host_seconds 153.20 # Real time elapsed on the host
|
||||
sim_insts 199813913 # Number of instructions simulated
|
||||
sim_ops 409133277 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::pc.south_bridge.ide 2786624 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.dtb.walker 1024 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.itb.walker 704 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.inst 972736 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 11807616 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 15568704 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 972736 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 972736 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 12232896 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 12232896 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::pc.south_bridge.ide 43541 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.dtb.walker 16 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.itb.walker 11 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.inst 15199 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 184494 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 243261 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 191139 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 191139 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::pc.south_bridge.ide 545110 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.dtb.walker 200 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.itb.walker 138 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 190283 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 2309764 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 3045495 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 190283 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 190283 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 2392956 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 2392956 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 2392956 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::pc.south_bridge.ide 545110 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.dtb.walker 200 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.itb.walker 138 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 190283 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 2309764 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 5438452 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.l2c.replacements 164044 # number of replacements
|
||||
system.l2c.tagsinuse 36842.944085 # Cycle average of tags in use
|
||||
system.l2c.total_refs 3332458 # Total number of references to valid blocks.
|
||||
system.l2c.sampled_refs 196390 # Sample count of references to valid blocks.
|
||||
system.l2c.avg_refs 16.968573 # Average number of references to valid blocks.
|
||||
system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.l2c.occ_blocks::writebacks 27139.322665 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu.dtb.walker 2.054559 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu.itb.walker 0.003581 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu.inst 1828.819855 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu.data 7872.743425 # Average occupied blocks per requestor
|
||||
system.l2c.occ_percent::writebacks 0.414113 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu.dtb.walker 0.000031 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu.inst 0.027906 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu.data 0.120129 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::total 0.562179 # Average percentage of cache occupancy
|
||||
system.l2c.ReadReq_hits::cpu.dtb.walker 6729 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu.itb.walker 2809 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu.inst 776101 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu.data 1266816 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::total 2052455 # number of ReadReq hits
|
||||
system.l2c.Writeback_hits::writebacks 1529403 # number of Writeback hits
|
||||
system.l2c.Writeback_hits::total 1529403 # number of Writeback hits
|
||||
system.l2c.UpgradeReq_hits::cpu.data 31 # number of UpgradeReq hits
|
||||
system.l2c.UpgradeReq_hits::total 31 # number of UpgradeReq hits
|
||||
system.l2c.ReadExReq_hits::cpu.data 168948 # number of ReadExReq hits
|
||||
system.l2c.ReadExReq_hits::total 168948 # number of ReadExReq hits
|
||||
system.l2c.demand_hits::cpu.dtb.walker 6729 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu.itb.walker 2809 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu.inst 776101 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu.data 1435764 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::total 2221403 # number of demand (read+write) hits
|
||||
system.l2c.overall_hits::cpu.dtb.walker 6729 # number of overall hits
|
||||
system.l2c.overall_hits::cpu.itb.walker 2809 # number of overall hits
|
||||
system.l2c.overall_hits::cpu.inst 776101 # number of overall hits
|
||||
system.l2c.overall_hits::cpu.data 1435764 # number of overall hits
|
||||
system.l2c.overall_hits::total 2221403 # number of overall hits
|
||||
system.l2c.ReadReq_misses::cpu.dtb.walker 16 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu.itb.walker 11 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu.inst 15200 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu.data 40772 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::total 55999 # number of ReadReq misses
|
||||
system.l2c.UpgradeReq_misses::cpu.data 1792 # number of UpgradeReq misses
|
||||
system.l2c.UpgradeReq_misses::total 1792 # number of UpgradeReq misses
|
||||
system.l2c.ReadExReq_misses::cpu.data 144639 # number of ReadExReq misses
|
||||
system.l2c.ReadExReq_misses::total 144639 # number of ReadExReq misses
|
||||
system.l2c.demand_misses::cpu.dtb.walker 16 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu.itb.walker 11 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu.inst 15200 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu.data 185411 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::total 200638 # number of demand (read+write) misses
|
||||
system.l2c.overall_misses::cpu.dtb.walker 16 # number of overall misses
|
||||
system.l2c.overall_misses::cpu.itb.walker 11 # number of overall misses
|
||||
system.l2c.overall_misses::cpu.inst 15200 # number of overall misses
|
||||
system.l2c.overall_misses::cpu.data 185411 # number of overall misses
|
||||
system.l2c.overall_misses::total 200638 # number of overall misses
|
||||
system.l2c.ReadReq_accesses::cpu.dtb.walker 6745 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::cpu.itb.walker 2820 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::cpu.inst 791301 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::cpu.data 1307588 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::total 2108454 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.Writeback_accesses::writebacks 1529403 # number of Writeback accesses(hits+misses)
|
||||
system.l2c.Writeback_accesses::total 1529403 # number of Writeback accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_accesses::cpu.data 1823 # number of UpgradeReq accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_accesses::total 1823 # number of UpgradeReq accesses(hits+misses)
|
||||
system.l2c.ReadExReq_accesses::cpu.data 313587 # number of ReadExReq accesses(hits+misses)
|
||||
system.l2c.ReadExReq_accesses::total 313587 # number of ReadExReq accesses(hits+misses)
|
||||
system.l2c.demand_accesses::cpu.dtb.walker 6745 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu.itb.walker 2820 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu.inst 791301 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu.data 1621175 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::total 2422041 # number of demand (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu.dtb.walker 6745 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu.itb.walker 2820 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu.inst 791301 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu.data 1621175 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::total 2422041 # number of overall (read+write) accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.002372 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.003901 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu.inst 0.019209 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu.data 0.031181 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::total 0.026559 # miss rate for ReadReq accesses
|
||||
system.l2c.UpgradeReq_miss_rate::cpu.data 0.982995 # miss rate for UpgradeReq accesses
|
||||
system.l2c.UpgradeReq_miss_rate::total 0.982995 # miss rate for UpgradeReq accesses
|
||||
system.l2c.ReadExReq_miss_rate::cpu.data 0.461240 # miss rate for ReadExReq accesses
|
||||
system.l2c.ReadExReq_miss_rate::total 0.461240 # miss rate for ReadExReq accesses
|
||||
system.l2c.demand_miss_rate::cpu.dtb.walker 0.002372 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu.itb.walker 0.003901 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu.inst 0.019209 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu.data 0.114368 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::total 0.082838 # miss rate for demand accesses
|
||||
system.l2c.overall_miss_rate::cpu.dtb.walker 0.002372 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu.itb.walker 0.003901 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu.inst 0.019209 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu.data 0.114368 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::total 0.082838 # miss rate for overall accesses
|
||||
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.l2c.fast_writes 0 # number of fast writes performed
|
||||
system.l2c.cache_copies 0 # number of cache copies performed
|
||||
system.l2c.writebacks::writebacks 144472 # number of writebacks
|
||||
system.l2c.writebacks::total 144472 # number of writebacks
|
||||
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.iocache.replacements 47570 # number of replacements
|
||||
system.iocache.tagsinuse 0.042409 # Cycle average of tags in use
|
||||
system.iocache.total_refs 0 # Total number of references to valid blocks.
|
||||
system.iocache.sampled_refs 47586 # Sample count of references to valid blocks.
|
||||
system.iocache.avg_refs 0 # Average number of references to valid blocks.
|
||||
system.iocache.warmup_cycle 4994776740009 # Cycle when the warmup percentage was hit.
|
||||
system.iocache.occ_blocks::pc.south_bridge.ide 0.042409 # Average occupied blocks per requestor
|
||||
system.iocache.occ_percent::pc.south_bridge.ide 0.002651 # Average percentage of cache occupancy
|
||||
system.iocache.occ_percent::total 0.002651 # Average percentage of cache occupancy
|
||||
system.iocache.ReadReq_misses::pc.south_bridge.ide 905 # number of ReadReq misses
|
||||
system.iocache.ReadReq_misses::total 905 # number of ReadReq misses
|
||||
system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses
|
||||
system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses
|
||||
system.iocache.demand_misses::pc.south_bridge.ide 47625 # number of demand (read+write) misses
|
||||
system.iocache.demand_misses::total 47625 # number of demand (read+write) misses
|
||||
system.iocache.overall_misses::pc.south_bridge.ide 47625 # number of overall misses
|
||||
system.iocache.overall_misses::total 47625 # number of overall misses
|
||||
system.iocache.ReadReq_accesses::pc.south_bridge.ide 905 # number of ReadReq accesses(hits+misses)
|
||||
system.iocache.ReadReq_accesses::total 905 # number of ReadReq accesses(hits+misses)
|
||||
system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses)
|
||||
system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses)
|
||||
system.iocache.demand_accesses::pc.south_bridge.ide 47625 # number of demand (read+write) accesses
|
||||
system.iocache.demand_accesses::total 47625 # number of demand (read+write) accesses
|
||||
system.iocache.overall_accesses::pc.south_bridge.ide 47625 # number of overall (read+write) accesses
|
||||
system.iocache.overall_accesses::total 47625 # number of overall (read+write) accesses
|
||||
system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
|
||||
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
|
||||
system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses
|
||||
system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
|
||||
system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses
|
||||
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
|
||||
system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
|
||||
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
|
||||
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.iocache.fast_writes 0 # number of fast writes performed
|
||||
system.iocache.cache_copies 0 # number of cache copies performed
|
||||
system.iocache.writebacks::writebacks 46667 # number of writebacks
|
||||
system.iocache.writebacks::total 46667 # number of writebacks
|
||||
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
||||
system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
|
||||
system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD).
|
||||
system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes.
|
||||
system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes.
|
||||
system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions.
|
||||
system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
||||
system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
|
||||
system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD).
|
||||
system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
|
||||
system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
|
||||
system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
|
||||
system.cpu.numCycles 10224086531 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 199813913 # Number of instructions committed
|
||||
system.cpu.committedOps 409133277 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 374297244 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 0 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 39954968 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 374297244 # number of integer instructions
|
||||
system.cpu.num_fp_insts 0 # number of float instructions
|
||||
system.cpu.num_int_register_reads 1159028861 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 636431619 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
|
||||
system.cpu.num_mem_refs 35626519 # number of memory refs
|
||||
system.cpu.num_load_insts 27217784 # Number of load instructions
|
||||
system.cpu.num_store_insts 8408735 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 9770605338.086651 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 453481192.913350 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 0.044354 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0.955646 # Percentage of idle cycles
|
||||
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
||||
system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
|
||||
system.cpu.icache.replacements 790795 # number of replacements
|
||||
system.cpu.icache.tagsinuse 510.627676 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 243365777 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 791307 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 307.549127 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 148763105500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 510.627676 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.997320 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.997320 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 243365777 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 243365777 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 243365777 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 243365777 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 243365777 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 243365777 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 791314 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 791314 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 791314 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 791314 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 791314 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 791314 # number of overall misses
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 244157091 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 244157091 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 244157091 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 244157091 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 244157091 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 244157091 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003241 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.003241 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.003241 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.003241 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.003241 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.003241 # miss rate for overall accesses
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks::writebacks 809 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 809 # number of writebacks
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.itb_walker_cache.replacements 3435 # number of replacements
|
||||
system.cpu.itb_walker_cache.tagsinuse 3.021701 # Cycle average of tags in use
|
||||
system.cpu.itb_walker_cache.total_refs 7940 # Total number of references to valid blocks.
|
||||
system.cpu.itb_walker_cache.sampled_refs 3444 # Sample count of references to valid blocks.
|
||||
system.cpu.itb_walker_cache.avg_refs 2.305459 # Average number of references to valid blocks.
|
||||
system.cpu.itb_walker_cache.warmup_cycle 5105275407500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 3.021701 # Average occupied blocks per requestor
|
||||
system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.188856 # Average percentage of cache occupancy
|
||||
system.cpu.itb_walker_cache.occ_percent::total 0.188856 # Average percentage of cache occupancy
|
||||
system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7947 # number of ReadReq hits
|
||||
system.cpu.itb_walker_cache.ReadReq_hits::total 7947 # number of ReadReq hits
|
||||
system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits
|
||||
system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits
|
||||
system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7949 # number of demand (read+write) hits
|
||||
system.cpu.itb_walker_cache.demand_hits::total 7949 # number of demand (read+write) hits
|
||||
system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7949 # number of overall hits
|
||||
system.cpu.itb_walker_cache.overall_hits::total 7949 # number of overall hits
|
||||
system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4278 # number of ReadReq misses
|
||||
system.cpu.itb_walker_cache.ReadReq_misses::total 4278 # number of ReadReq misses
|
||||
system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4278 # number of demand (read+write) misses
|
||||
system.cpu.itb_walker_cache.demand_misses::total 4278 # number of demand (read+write) misses
|
||||
system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4278 # number of overall misses
|
||||
system.cpu.itb_walker_cache.overall_misses::total 4278 # number of overall misses
|
||||
system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12225 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.itb_walker_cache.ReadReq_accesses::total 12225 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12227 # number of demand (read+write) accesses
|
||||
system.cpu.itb_walker_cache.demand_accesses::total 12227 # number of demand (read+write) accesses
|
||||
system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12227 # number of overall (read+write) accesses
|
||||
system.cpu.itb_walker_cache.overall_accesses::total 12227 # number of overall (read+write) accesses
|
||||
system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.349939 # miss rate for ReadReq accesses
|
||||
system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.349939 # miss rate for ReadReq accesses
|
||||
system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.349881 # miss rate for demand accesses
|
||||
system.cpu.itb_walker_cache.demand_miss_rate::total 0.349881 # miss rate for demand accesses
|
||||
system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.349881 # miss rate for overall accesses
|
||||
system.cpu.itb_walker_cache.overall_miss_rate::total 0.349881 # miss rate for overall accesses
|
||||
system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.itb_walker_cache.writebacks::writebacks 518 # number of writebacks
|
||||
system.cpu.itb_walker_cache.writebacks::total 518 # number of writebacks
|
||||
system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dtb_walker_cache.replacements 7755 # number of replacements
|
||||
system.cpu.dtb_walker_cache.tagsinuse 5.010998 # Cycle average of tags in use
|
||||
system.cpu.dtb_walker_cache.total_refs 12854 # Total number of references to valid blocks.
|
||||
system.cpu.dtb_walker_cache.sampled_refs 7767 # Sample count of references to valid blocks.
|
||||
system.cpu.dtb_walker_cache.avg_refs 1.654950 # Average number of references to valid blocks.
|
||||
system.cpu.dtb_walker_cache.warmup_cycle 5101232849000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 5.010998 # Average occupied blocks per requestor
|
||||
system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.313187 # Average percentage of cache occupancy
|
||||
system.cpu.dtb_walker_cache.occ_percent::total 0.313187 # Average percentage of cache occupancy
|
||||
system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 12875 # number of ReadReq hits
|
||||
system.cpu.dtb_walker_cache.ReadReq_hits::total 12875 # number of ReadReq hits
|
||||
system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 12875 # number of demand (read+write) hits
|
||||
system.cpu.dtb_walker_cache.demand_hits::total 12875 # number of demand (read+write) hits
|
||||
system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 12875 # number of overall hits
|
||||
system.cpu.dtb_walker_cache.overall_hits::total 12875 # number of overall hits
|
||||
system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8933 # number of ReadReq misses
|
||||
system.cpu.dtb_walker_cache.ReadReq_misses::total 8933 # number of ReadReq misses
|
||||
system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8933 # number of demand (read+write) misses
|
||||
system.cpu.dtb_walker_cache.demand_misses::total 8933 # number of demand (read+write) misses
|
||||
system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8933 # number of overall misses
|
||||
system.cpu.dtb_walker_cache.overall_misses::total 8933 # number of overall misses
|
||||
system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21808 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dtb_walker_cache.ReadReq_accesses::total 21808 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21808 # number of demand (read+write) accesses
|
||||
system.cpu.dtb_walker_cache.demand_accesses::total 21808 # number of demand (read+write) accesses
|
||||
system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21808 # number of overall (read+write) accesses
|
||||
system.cpu.dtb_walker_cache.overall_accesses::total 21808 # number of overall (read+write) accesses
|
||||
system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.409620 # miss rate for ReadReq accesses
|
||||
system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.409620 # miss rate for ReadReq accesses
|
||||
system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.409620 # miss rate for demand accesses
|
||||
system.cpu.dtb_walker_cache.demand_miss_rate::total 0.409620 # miss rate for demand accesses
|
||||
system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.409620 # miss rate for overall accesses
|
||||
system.cpu.dtb_walker_cache.overall_miss_rate::total 0.409620 # miss rate for overall accesses
|
||||
system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dtb_walker_cache.writebacks::writebacks 2517 # number of writebacks
|
||||
system.cpu.dtb_walker_cache.writebacks::total 2517 # number of writebacks
|
||||
system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 1621277 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 511.999417 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 20142220 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 1621789 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 12.419754 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 7549500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 511.999417 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.999999 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.999999 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 12057024 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 12057024 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 8082938 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 8082938 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 20139962 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 20139962 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 20139962 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 20139962 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 1308207 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 1308207 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 315850 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 315850 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 1624057 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 1624057 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 1624057 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 1624057 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 13365231 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 13365231 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 8398788 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 8398788 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 21764019 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 21764019 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 21764019 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 21764019 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097881 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.097881 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037607 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.037607 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.074621 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.074621 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.074621 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.074621 # miss rate for overall accesses
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 1525559 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 1525559 # number of writebacks
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
@ -0,0 +1,133 @@
|
||||
Linux version 2.6.22.9 (blackga@nacho) (gcc version 4.1.2 (Gentoo 4.1.2)) #2 Mon Oct 8 13:13:00 PDT 2007
|
||||
Command line: earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1
|
||||
BIOS-provided physical RAM map:
|
||||
BIOS-e820: 0000000000000000 - 0000000000100000 (reserved)
|
||||
BIOS-e820: 0000000000100000 - 0000000008000000 (usable)
|
||||
end_pfn_map = 32768
|
||||
kernel direct mapping tables up to 8000000 @ 100000-102000
|
||||
DMI 2.5 present.
|
||||
Zone PFN ranges:
|
||||
DMA 256 -> 4096
|
||||
DMA32 4096 -> 1048576
|
||||
Normal 1048576 -> 1048576
|
||||
early_node_map[1] active PFN ranges
|
||||
0: 256 -> 32768
|
||||
Intel MultiProcessor Specification v1.4
|
||||
MPTABLE: OEM ID: MPTABLE: Product ID: MPTABLE: APIC at: 0xFEE00000
|
||||
Processor #0 (Bootup-CPU)
|
||||
I/O APIC #1 at 0xFEC00000.
|
||||
Setting APIC routing to flat
|
||||
Processors: 1
|
||||
Allocating PCI resources starting at 10000000 (gap: 8000000:f8000000)
|
||||
Built 1 zonelists. Total pages: 30458
|
||||
Kernel command line: earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1
|
||||
Initializing CPU#0
|
||||
PID hash table entries: 512 (order: 9, 4096 bytes)
|
||||
time.c: Detected 1999.998 MHz processor.
|
||||
Console: colour dummy device 80x25
|
||||
console handover: boot [earlyser0] -> real [ttyS0]
|
||||
Dentry cache hash table entries: 16384 (order: 5, 131072 bytes)
|
||||
Inode-cache hash table entries: 8192 (order: 4, 65536 bytes)
|
||||
Checking aperture...
|
||||
Memory: 121556k/131072k available (3742k kernel code, 8456k reserved, 1874k data, 232k init)
|
||||
Calibrating delay loop (skipped)... 3999.96 BogoMIPS preset
|
||||
Mount-cache hash table entries: 256
|
||||
CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)
|
||||
CPU: L2 Cache: 1024K (64 bytes/line)
|
||||
CPU: Fake M5 x86_64 CPU stepping 01
|
||||
ACPI: Core revision 20070126
|
||||
ACPI Exception (tbxface-0618): AE_NO_ACPI_TABLES, While loading namespace from ACPI tables [20070126]
|
||||
ACPI: Unable to load the System Description Tables
|
||||
Using local APIC timer interrupts.
|
||||
result 7812490
|
||||
Detected 7.812 MHz APIC timer.
|
||||
NET: Registered protocol family 16
|
||||
PCI: Using configuration type 1
|
||||
ACPI: Interpreter disabled.
|
||||
Linux Plug and Play Support v0.97 (c) Adam Belay
|
||||
pnp: PnP ACPI: disabled
|
||||
SCSI subsystem initialized
|
||||
usbcore: registered new interface driver usbfs
|
||||
usbcore: registered new interface driver hub
|
||||
usbcore: registered new device driver usb
|
||||
PCI: Probing PCI hardware
|
||||
PCI-GART: No AMD northbridge found.
|
||||
NET: Registered protocol family 2
|
||||
Time: tsc clocksource has been installed.
|
||||
IP route cache hash table entries: 1024 (order: 1, 8192 bytes)
|
||||
TCP established hash table entries: 4096 (order: 4, 65536 bytes)
|
||||
TCP bind hash table entries: 4096 (order: 3, 32768 bytes)
|
||||
TCP: Hash tables configured (established 4096 bind 4096)
|
||||
TCP reno registered
|
||||
Total HugeTLB memory allocated, 0
|
||||
Installing knfsd (copyright (C) 1996 okir@monad.swb.de).
|
||||
io scheduler noop registered
|
||||
io scheduler deadline registered
|
||||
io scheduler cfq registered (default)
|
||||
Real Time Clock Driver v1.12ac
|
||||
Linux agpgart interface v0.102 (c) Dave Jones
|
||||
Serial: 8250/16550 driver $Revision: 1.90 $ 4 ports, IRQ sharing disabled
|
||||
serial8250: ttyS0 at I/O 0x3f8 (irq = 4) is a 8250
|
||||
floppy0: no floppy controllers found
|
||||
RAMDISK driver initialized: 16 RAM disks of 4096K size 1024 blocksize
|
||||
loop: module loaded
|
||||
Intel(R) PRO/1000 Network Driver - version 7.3.20-k2
|
||||
Copyright (c) 1999-2006 Intel Corporation.
|
||||
e100: Intel(R) PRO/100 Network Driver, 3.5.17-k4-NAPI
|
||||
e100: Copyright(c) 1999-2006 Intel Corporation
|
||||
forcedeth.c: Reverse Engineered nForce ethernet driver. Version 0.60.
|
||||
tun: Universal TUN/TAP device driver, 1.6
|
||||
tun: (C) 1999-2004 Max Krasnyansky <maxk@qualcomm.com>
|
||||
netconsole: not configured, aborting
|
||||
Uniform Multi-Platform E-IDE driver Revision: 7.00alpha2
|
||||
ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx
|
||||
PIIX4: IDE controller at PCI slot 0000:00:04.0
|
||||
PCI: Enabling device 0000:00:04.0 (0000 -> 0001)
|
||||
PIIX4: chipset revision 0
|
||||
PIIX4: not 100% native mode: will probe irqs later
|
||||
ide0: BM-DMA at 0x1000-0x1007, BIOS settings: hda:DMA, hdb:DMA
|
||||
ide1: BM-DMA at 0x1008-0x100f, BIOS settings: hdc:DMA, hdd:DMA
|
||||
hda: M5 IDE Disk, ATA DISK drive
|
||||
hdb: M5 IDE Disk, ATA DISK drive
|
||||
ide0 at 0x1f0-0x1f7,0x3f6 on irq 14
|
||||
hda: max request size: 128KiB
|
||||
hda: 1048320 sectors (536 MB), CHS=1040/16/63, UDMA(33)
|
||||
hda: hda1
|
||||
hdb: max request size: 128KiB
|
||||
hdb: 4177920 sectors (2139 MB), CHS=4144/16/63, UDMA(33)
|
||||
hdb: unknown partition table
|
||||
megaraid cmm: 2.20.2.7 (Release Date: Sun Jul 16 00:01:03 EST 2006)
|
||||
megaraid: 2.20.5.1 (Release Date: Thu Nov 16 15:32:35 EST 2006)
|
||||
megasas: 00.00.03.10-rc5 Thu May 17 10:09:32 PDT 2007
|
||||
Fusion MPT base driver 3.04.04
|
||||
Copyright (c) 1999-2007 LSI Logic Corporation
|
||||
Fusion MPT SPI Host driver 3.04.04
|
||||
Fusion MPT SAS Host driver 3.04.04
|
||||
ieee1394: raw1394: /dev/raw1394 device initialized
|
||||
USB Universal Host Controller Interface driver v3.0
|
||||
usbcore: registered new interface driver usblp
|
||||
drivers/usb/class/usblp.c: v0.13: USB Printer Device Class driver
|
||||
Initializing USB Mass Storage driver...
|
||||
usbcore: registered new interface driver usb-storage
|
||||
USB Mass Storage support registered.
|
||||
PNP: No PS/2 controller found. Probing ports directly.
|
||||
serio: i8042 KBD port at 0x60,0x64 irq 1
|
||||
serio: i8042 AUX port at 0x60,0x64 irq 12
|
||||
mice: PS/2 mouse device common for all mice
|
||||
input: AT Translated Set 2 keyboard as /class/input/input0
|
||||
device-mapper: ioctl: 4.11.0-ioctl (2006-10-12) initialised: dm-devel@redhat.com
|
||||
input: PS/2 Generic Mouse as /class/input/input1
|
||||
usbcore: registered new interface driver usbhid
|
||||
drivers/hid/usbhid/hid-core.c: v2.6:USB HID core driver
|
||||
oprofile: using timer interrupt.
|
||||
TCP cubic registered
|
||||
NET: Registered protocol family 1
|
||||
NET: Registered protocol family 10
|
||||
IPv6 over IPv4 tunneling driver
|
||||
NET: Registered protocol family 17
|
||||
EXT2-fs warning: mounting unchecked fs, running e2fsck is recommended
|
||||
VFS: Mounted root (ext2 filesystem).
|
||||
Freeing unused kernel memory: 232k freed
|
||||
|
||||
INIT: version 2.86 booting
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,9 @@
|
||||
warn: Sockets disabled, not accepting terminal connections
|
||||
warn: Reading current count from inactive timer.
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: Don't know what interrupt to clear for console.
|
||||
warn: instruction 'fxsave' unimplemented
|
||||
warn: Tried to clear PCI interrupt 14
|
||||
warn: Unknown mouse command 0xe1.
|
||||
warn: instruction 'wbinvd' unimplemented
|
||||
hack: be nice to actually delete the event here
|
||||
@ -0,0 +1,13 @@
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jun 4 2012 13:44:28
|
||||
gem5 started Jun 4 2012 15:05:12
|
||||
gem5 executing on zizzer
|
||||
command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-timing -re tests/run.py build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-timing
|
||||
warning: add_child('terminal'): child 'terminal' already has parent
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
|
||||
0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 5195470393000 because m5_exit instruction encountered
|
||||
@ -0,0 +1,768 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 5.195470 # Number of seconds simulated
|
||||
sim_ticks 5195470393000 # Number of ticks simulated
|
||||
final_tick 5195470393000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 792632 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1521406 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 29811367673 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 354100 # Number of bytes of host memory used
|
||||
host_seconds 174.28 # Real time elapsed on the host
|
||||
sim_insts 138138472 # Number of instructions simulated
|
||||
sim_ops 265147881 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::pc.south_bridge.ide 2876352 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.dtb.walker 832 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.itb.walker 640 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.inst 974400 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 9911872 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 13764096 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 974400 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 974400 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 10427072 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 10427072 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::pc.south_bridge.ide 44943 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.dtb.walker 13 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.itb.walker 10 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.inst 15225 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 154873 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 215064 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 162923 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 162923 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::pc.south_bridge.ide 553627 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.dtb.walker 160 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.itb.walker 123 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 187548 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 1907791 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 2649249 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 187548 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 187548 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 2006954 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 2006954 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 2006954 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::pc.south_bridge.ide 553627 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.dtb.walker 160 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.itb.walker 123 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 187548 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 1907791 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 4656204 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.l2c.replacements 136133 # number of replacements
|
||||
system.l2c.tagsinuse 31389.895470 # Cycle average of tags in use
|
||||
system.l2c.total_refs 3363370 # Total number of references to valid blocks.
|
||||
system.l2c.sampled_refs 168244 # Sample count of references to valid blocks.
|
||||
system.l2c.avg_refs 19.991025 # Average number of references to valid blocks.
|
||||
system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.l2c.occ_blocks::writebacks 23478.740830 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu.dtb.walker 0.248367 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu.itb.walker 0.010497 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu.inst 1900.597036 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu.data 6010.298740 # Average occupied blocks per requestor
|
||||
system.l2c.occ_percent::writebacks 0.358257 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu.dtb.walker 0.000004 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu.inst 0.029001 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu.data 0.091710 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::total 0.478972 # Average percentage of cache occupancy
|
||||
system.l2c.ReadReq_hits::cpu.dtb.walker 6528 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu.itb.walker 3033 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu.inst 773419 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu.data 1274463 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::total 2057443 # number of ReadReq hits
|
||||
system.l2c.Writeback_hits::writebacks 1534567 # number of Writeback hits
|
||||
system.l2c.Writeback_hits::total 1534567 # number of Writeback hits
|
||||
system.l2c.UpgradeReq_hits::cpu.data 320 # number of UpgradeReq hits
|
||||
system.l2c.UpgradeReq_hits::total 320 # number of UpgradeReq hits
|
||||
system.l2c.ReadExReq_hits::cpu.data 192958 # number of ReadExReq hits
|
||||
system.l2c.ReadExReq_hits::total 192958 # number of ReadExReq hits
|
||||
system.l2c.demand_hits::cpu.dtb.walker 6528 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu.itb.walker 3033 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu.inst 773419 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu.data 1467421 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::total 2250401 # number of demand (read+write) hits
|
||||
system.l2c.overall_hits::cpu.dtb.walker 6528 # number of overall hits
|
||||
system.l2c.overall_hits::cpu.itb.walker 3033 # number of overall hits
|
||||
system.l2c.overall_hits::cpu.inst 773419 # number of overall hits
|
||||
system.l2c.overall_hits::cpu.data 1467421 # number of overall hits
|
||||
system.l2c.overall_hits::total 2250401 # number of overall hits
|
||||
system.l2c.ReadReq_misses::cpu.dtb.walker 13 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu.itb.walker 10 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu.inst 15226 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu.data 35581 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::total 50830 # number of ReadReq misses
|
||||
system.l2c.UpgradeReq_misses::cpu.data 1369 # number of UpgradeReq misses
|
||||
system.l2c.UpgradeReq_misses::total 1369 # number of UpgradeReq misses
|
||||
system.l2c.ReadExReq_misses::cpu.data 120168 # number of ReadExReq misses
|
||||
system.l2c.ReadExReq_misses::total 120168 # number of ReadExReq misses
|
||||
system.l2c.demand_misses::cpu.dtb.walker 13 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu.itb.walker 10 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu.inst 15226 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu.data 155749 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::total 170998 # number of demand (read+write) misses
|
||||
system.l2c.overall_misses::cpu.dtb.walker 13 # number of overall misses
|
||||
system.l2c.overall_misses::cpu.itb.walker 10 # number of overall misses
|
||||
system.l2c.overall_misses::cpu.inst 15226 # number of overall misses
|
||||
system.l2c.overall_misses::cpu.data 155749 # number of overall misses
|
||||
system.l2c.overall_misses::total 170998 # number of overall misses
|
||||
system.l2c.ReadReq_miss_latency::cpu.dtb.walker 676000 # number of ReadReq miss cycles
|
||||
system.l2c.ReadReq_miss_latency::cpu.itb.walker 520000 # number of ReadReq miss cycles
|
||||
system.l2c.ReadReq_miss_latency::cpu.inst 791868000 # number of ReadReq miss cycles
|
||||
system.l2c.ReadReq_miss_latency::cpu.data 1863058500 # number of ReadReq miss cycles
|
||||
system.l2c.ReadReq_miss_latency::total 2656122500 # number of ReadReq miss cycles
|
||||
system.l2c.UpgradeReq_miss_latency::cpu.data 33778000 # number of UpgradeReq miss cycles
|
||||
system.l2c.UpgradeReq_miss_latency::total 33778000 # number of UpgradeReq miss cycles
|
||||
system.l2c.ReadExReq_miss_latency::cpu.data 6249324500 # number of ReadExReq miss cycles
|
||||
system.l2c.ReadExReq_miss_latency::total 6249324500 # number of ReadExReq miss cycles
|
||||
system.l2c.demand_miss_latency::cpu.dtb.walker 676000 # number of demand (read+write) miss cycles
|
||||
system.l2c.demand_miss_latency::cpu.itb.walker 520000 # number of demand (read+write) miss cycles
|
||||
system.l2c.demand_miss_latency::cpu.inst 791868000 # number of demand (read+write) miss cycles
|
||||
system.l2c.demand_miss_latency::cpu.data 8112383000 # number of demand (read+write) miss cycles
|
||||
system.l2c.demand_miss_latency::total 8905447000 # number of demand (read+write) miss cycles
|
||||
system.l2c.overall_miss_latency::cpu.dtb.walker 676000 # number of overall miss cycles
|
||||
system.l2c.overall_miss_latency::cpu.itb.walker 520000 # number of overall miss cycles
|
||||
system.l2c.overall_miss_latency::cpu.inst 791868000 # number of overall miss cycles
|
||||
system.l2c.overall_miss_latency::cpu.data 8112383000 # number of overall miss cycles
|
||||
system.l2c.overall_miss_latency::total 8905447000 # number of overall miss cycles
|
||||
system.l2c.ReadReq_accesses::cpu.dtb.walker 6541 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::cpu.itb.walker 3043 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::cpu.inst 788645 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::cpu.data 1310044 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::total 2108273 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.Writeback_accesses::writebacks 1534567 # number of Writeback accesses(hits+misses)
|
||||
system.l2c.Writeback_accesses::total 1534567 # number of Writeback accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_accesses::cpu.data 1689 # number of UpgradeReq accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_accesses::total 1689 # number of UpgradeReq accesses(hits+misses)
|
||||
system.l2c.ReadExReq_accesses::cpu.data 313126 # number of ReadExReq accesses(hits+misses)
|
||||
system.l2c.ReadExReq_accesses::total 313126 # number of ReadExReq accesses(hits+misses)
|
||||
system.l2c.demand_accesses::cpu.dtb.walker 6541 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu.itb.walker 3043 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu.inst 788645 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu.data 1623170 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::total 2421399 # number of demand (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu.dtb.walker 6541 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu.itb.walker 3043 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu.inst 788645 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu.data 1623170 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::total 2421399 # number of overall (read+write) accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.001987 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.003286 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu.inst 0.019307 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu.data 0.027160 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::total 0.024110 # miss rate for ReadReq accesses
|
||||
system.l2c.UpgradeReq_miss_rate::cpu.data 0.810539 # miss rate for UpgradeReq accesses
|
||||
system.l2c.UpgradeReq_miss_rate::total 0.810539 # miss rate for UpgradeReq accesses
|
||||
system.l2c.ReadExReq_miss_rate::cpu.data 0.383769 # miss rate for ReadExReq accesses
|
||||
system.l2c.ReadExReq_miss_rate::total 0.383769 # miss rate for ReadExReq accesses
|
||||
system.l2c.demand_miss_rate::cpu.dtb.walker 0.001987 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu.itb.walker 0.003286 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu.inst 0.019307 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu.data 0.095954 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::total 0.070620 # miss rate for demand accesses
|
||||
system.l2c.overall_miss_rate::cpu.dtb.walker 0.001987 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu.itb.walker 0.003286 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu.inst 0.019307 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu.data 0.095954 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::total 0.070620 # miss rate for overall accesses
|
||||
system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52000 # average ReadReq miss latency
|
||||
system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 52000 # average ReadReq miss latency
|
||||
system.l2c.ReadReq_avg_miss_latency::cpu.inst 52007.618547 # average ReadReq miss latency
|
||||
system.l2c.ReadReq_avg_miss_latency::cpu.data 52361.049436 # average ReadReq miss latency
|
||||
system.l2c.ReadReq_avg_miss_latency::total 52255.016722 # average ReadReq miss latency
|
||||
system.l2c.UpgradeReq_avg_miss_latency::cpu.data 24673.484295 # average UpgradeReq miss latency
|
||||
system.l2c.UpgradeReq_avg_miss_latency::total 24673.484295 # average UpgradeReq miss latency
|
||||
system.l2c.ReadExReq_avg_miss_latency::cpu.data 52004.897310 # average ReadExReq miss latency
|
||||
system.l2c.ReadExReq_avg_miss_latency::total 52004.897310 # average ReadExReq miss latency
|
||||
system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52000 # average overall miss latency
|
||||
system.l2c.demand_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency
|
||||
system.l2c.demand_avg_miss_latency::cpu.inst 52007.618547 # average overall miss latency
|
||||
system.l2c.demand_avg_miss_latency::cpu.data 52086.260586 # average overall miss latency
|
||||
system.l2c.demand_avg_miss_latency::total 52079.246541 # average overall miss latency
|
||||
system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52000 # average overall miss latency
|
||||
system.l2c.overall_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency
|
||||
system.l2c.overall_avg_miss_latency::cpu.inst 52007.618547 # average overall miss latency
|
||||
system.l2c.overall_avg_miss_latency::cpu.data 52086.260586 # average overall miss latency
|
||||
system.l2c.overall_avg_miss_latency::total 52079.246541 # average overall miss latency
|
||||
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.l2c.fast_writes 0 # number of fast writes performed
|
||||
system.l2c.cache_copies 0 # number of cache copies performed
|
||||
system.l2c.writebacks::writebacks 116255 # number of writebacks
|
||||
system.l2c.writebacks::total 116255 # number of writebacks
|
||||
system.l2c.ReadReq_mshr_misses::cpu.dtb.walker 13 # number of ReadReq MSHR misses
|
||||
system.l2c.ReadReq_mshr_misses::cpu.itb.walker 10 # number of ReadReq MSHR misses
|
||||
system.l2c.ReadReq_mshr_misses::cpu.inst 15226 # number of ReadReq MSHR misses
|
||||
system.l2c.ReadReq_mshr_misses::cpu.data 35581 # number of ReadReq MSHR misses
|
||||
system.l2c.ReadReq_mshr_misses::total 50830 # number of ReadReq MSHR misses
|
||||
system.l2c.UpgradeReq_mshr_misses::cpu.data 1369 # number of UpgradeReq MSHR misses
|
||||
system.l2c.UpgradeReq_mshr_misses::total 1369 # number of UpgradeReq MSHR misses
|
||||
system.l2c.ReadExReq_mshr_misses::cpu.data 120168 # number of ReadExReq MSHR misses
|
||||
system.l2c.ReadExReq_mshr_misses::total 120168 # number of ReadExReq MSHR misses
|
||||
system.l2c.demand_mshr_misses::cpu.dtb.walker 13 # number of demand (read+write) MSHR misses
|
||||
system.l2c.demand_mshr_misses::cpu.itb.walker 10 # number of demand (read+write) MSHR misses
|
||||
system.l2c.demand_mshr_misses::cpu.inst 15226 # number of demand (read+write) MSHR misses
|
||||
system.l2c.demand_mshr_misses::cpu.data 155749 # number of demand (read+write) MSHR misses
|
||||
system.l2c.demand_mshr_misses::total 170998 # number of demand (read+write) MSHR misses
|
||||
system.l2c.overall_mshr_misses::cpu.dtb.walker 13 # number of overall MSHR misses
|
||||
system.l2c.overall_mshr_misses::cpu.itb.walker 10 # number of overall MSHR misses
|
||||
system.l2c.overall_mshr_misses::cpu.inst 15226 # number of overall MSHR misses
|
||||
system.l2c.overall_mshr_misses::cpu.data 155749 # number of overall MSHR misses
|
||||
system.l2c.overall_mshr_misses::total 170998 # number of overall MSHR misses
|
||||
system.l2c.ReadReq_mshr_miss_latency::cpu.dtb.walker 520000 # number of ReadReq MSHR miss cycles
|
||||
system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker 400000 # number of ReadReq MSHR miss cycles
|
||||
system.l2c.ReadReq_mshr_miss_latency::cpu.inst 609142000 # number of ReadReq MSHR miss cycles
|
||||
system.l2c.ReadReq_mshr_miss_latency::cpu.data 1436082000 # number of ReadReq MSHR miss cycles
|
||||
system.l2c.ReadReq_mshr_miss_latency::total 2046144000 # number of ReadReq MSHR miss cycles
|
||||
system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 55109000 # number of UpgradeReq MSHR miss cycles
|
||||
system.l2c.UpgradeReq_mshr_miss_latency::total 55109000 # number of UpgradeReq MSHR miss cycles
|
||||
system.l2c.ReadExReq_mshr_miss_latency::cpu.data 4807305000 # number of ReadExReq MSHR miss cycles
|
||||
system.l2c.ReadExReq_mshr_miss_latency::total 4807305000 # number of ReadExReq MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_latency::cpu.dtb.walker 520000 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_latency::cpu.itb.walker 400000 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_latency::cpu.inst 609142000 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_latency::cpu.data 6243387000 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_latency::total 6853449000 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency::cpu.dtb.walker 520000 # number of overall MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency::cpu.itb.walker 400000 # number of overall MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency::cpu.inst 609142000 # number of overall MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency::cpu.data 6243387000 # number of overall MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency::total 6853449000 # number of overall MSHR miss cycles
|
||||
system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 56051785000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.l2c.ReadReq_mshr_uncacheable_latency::total 56051785000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 1218050000 # number of WriteReq MSHR uncacheable cycles
|
||||
system.l2c.WriteReq_mshr_uncacheable_latency::total 1218050000 # number of WriteReq MSHR uncacheable cycles
|
||||
system.l2c.overall_mshr_uncacheable_latency::cpu.data 57269835000 # number of overall MSHR uncacheable cycles
|
||||
system.l2c.overall_mshr_uncacheable_latency::total 57269835000 # number of overall MSHR uncacheable cycles
|
||||
system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001987 # mshr miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.003286 # mshr miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.019307 # mshr miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.027160 # mshr miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_mshr_miss_rate::total 0.024110 # mshr miss rate for ReadReq accesses
|
||||
system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.810539 # mshr miss rate for UpgradeReq accesses
|
||||
system.l2c.UpgradeReq_mshr_miss_rate::total 0.810539 # mshr miss rate for UpgradeReq accesses
|
||||
system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.383769 # mshr miss rate for ReadExReq accesses
|
||||
system.l2c.ReadExReq_mshr_miss_rate::total 0.383769 # mshr miss rate for ReadExReq accesses
|
||||
system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.001987 # mshr miss rate for demand accesses
|
||||
system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.003286 # mshr miss rate for demand accesses
|
||||
system.l2c.demand_mshr_miss_rate::cpu.inst 0.019307 # mshr miss rate for demand accesses
|
||||
system.l2c.demand_mshr_miss_rate::cpu.data 0.095954 # mshr miss rate for demand accesses
|
||||
system.l2c.demand_mshr_miss_rate::total 0.070620 # mshr miss rate for demand accesses
|
||||
system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.001987 # mshr miss rate for overall accesses
|
||||
system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.003286 # mshr miss rate for overall accesses
|
||||
system.l2c.overall_mshr_miss_rate::cpu.inst 0.019307 # mshr miss rate for overall accesses
|
||||
system.l2c.overall_mshr_miss_rate::cpu.data 0.095954 # mshr miss rate for overall accesses
|
||||
system.l2c.overall_mshr_miss_rate::total 0.070620 # mshr miss rate for overall accesses
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average ReadReq mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40000 # average ReadReq mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40006.699067 # average ReadReq mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40360.922965 # average ReadReq mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::total 40254.652764 # average ReadReq mshr miss latency
|
||||
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40254.930606 # average UpgradeReq mshr miss latency
|
||||
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40254.930606 # average UpgradeReq mshr miss latency
|
||||
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40004.868185 # average ReadExReq mshr miss latency
|
||||
system.l2c.ReadExReq_avg_mshr_miss_latency::total 40004.868185 # average ReadExReq mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40006.699067 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu.data 40086.209221 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::total 40079.117884 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40006.699067 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu.data 40086.209221 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::total 40079.117884 # average overall mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
|
||||
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
||||
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
|
||||
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
||||
system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
|
||||
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
||||
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.iocache.replacements 47510 # number of replacements
|
||||
system.iocache.tagsinuse 0.120586 # Cycle average of tags in use
|
||||
system.iocache.total_refs 0 # Total number of references to valid blocks.
|
||||
system.iocache.sampled_refs 47526 # Sample count of references to valid blocks.
|
||||
system.iocache.avg_refs 0 # Average number of references to valid blocks.
|
||||
system.iocache.warmup_cycle 5048756072000 # Cycle when the warmup percentage was hit.
|
||||
system.iocache.occ_blocks::pc.south_bridge.ide 0.120586 # Average occupied blocks per requestor
|
||||
system.iocache.occ_percent::pc.south_bridge.ide 0.007537 # Average percentage of cache occupancy
|
||||
system.iocache.occ_percent::total 0.007537 # Average percentage of cache occupancy
|
||||
system.iocache.ReadReq_misses::pc.south_bridge.ide 844 # number of ReadReq misses
|
||||
system.iocache.ReadReq_misses::total 844 # number of ReadReq misses
|
||||
system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses
|
||||
system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses
|
||||
system.iocache.demand_misses::pc.south_bridge.ide 47564 # number of demand (read+write) misses
|
||||
system.iocache.demand_misses::total 47564 # number of demand (read+write) misses
|
||||
system.iocache.overall_misses::pc.south_bridge.ide 47564 # number of overall misses
|
||||
system.iocache.overall_misses::total 47564 # number of overall misses
|
||||
system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 106575932 # number of ReadReq miss cycles
|
||||
system.iocache.ReadReq_miss_latency::total 106575932 # number of ReadReq miss cycles
|
||||
system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 6391379160 # number of WriteReq miss cycles
|
||||
system.iocache.WriteReq_miss_latency::total 6391379160 # number of WriteReq miss cycles
|
||||
system.iocache.demand_miss_latency::pc.south_bridge.ide 6497955092 # number of demand (read+write) miss cycles
|
||||
system.iocache.demand_miss_latency::total 6497955092 # number of demand (read+write) miss cycles
|
||||
system.iocache.overall_miss_latency::pc.south_bridge.ide 6497955092 # number of overall miss cycles
|
||||
system.iocache.overall_miss_latency::total 6497955092 # number of overall miss cycles
|
||||
system.iocache.ReadReq_accesses::pc.south_bridge.ide 844 # number of ReadReq accesses(hits+misses)
|
||||
system.iocache.ReadReq_accesses::total 844 # number of ReadReq accesses(hits+misses)
|
||||
system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses)
|
||||
system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses)
|
||||
system.iocache.demand_accesses::pc.south_bridge.ide 47564 # number of demand (read+write) accesses
|
||||
system.iocache.demand_accesses::total 47564 # number of demand (read+write) accesses
|
||||
system.iocache.overall_accesses::pc.south_bridge.ide 47564 # number of overall (read+write) accesses
|
||||
system.iocache.overall_accesses::total 47564 # number of overall (read+write) accesses
|
||||
system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
|
||||
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
|
||||
system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses
|
||||
system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
|
||||
system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses
|
||||
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
|
||||
system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
|
||||
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
|
||||
system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 126274.800948 # average ReadReq miss latency
|
||||
system.iocache.ReadReq_avg_miss_latency::total 126274.800948 # average ReadReq miss latency
|
||||
system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 136801.779966 # average WriteReq miss latency
|
||||
system.iocache.WriteReq_avg_miss_latency::total 136801.779966 # average WriteReq miss latency
|
||||
system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 136614.983853 # average overall miss latency
|
||||
system.iocache.demand_avg_miss_latency::total 136614.983853 # average overall miss latency
|
||||
system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 136614.983853 # average overall miss latency
|
||||
system.iocache.overall_avg_miss_latency::total 136614.983853 # average overall miss latency
|
||||
system.iocache.blocked_cycles::no_mshrs 69564644 # number of cycles access was blocked
|
||||
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.iocache.blocked::no_mshrs 11299 # number of cycles access was blocked
|
||||
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.iocache.avg_blocked_cycles::no_mshrs 6156.708027 # average number of cycles each access was blocked
|
||||
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.iocache.fast_writes 0 # number of fast writes performed
|
||||
system.iocache.cache_copies 0 # number of cache copies performed
|
||||
system.iocache.writebacks::writebacks 46668 # number of writebacks
|
||||
system.iocache.writebacks::total 46668 # number of writebacks
|
||||
system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 844 # number of ReadReq MSHR misses
|
||||
system.iocache.ReadReq_mshr_misses::total 844 # number of ReadReq MSHR misses
|
||||
system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses
|
||||
system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses
|
||||
system.iocache.demand_mshr_misses::pc.south_bridge.ide 47564 # number of demand (read+write) MSHR misses
|
||||
system.iocache.demand_mshr_misses::total 47564 # number of demand (read+write) MSHR misses
|
||||
system.iocache.overall_mshr_misses::pc.south_bridge.ide 47564 # number of overall MSHR misses
|
||||
system.iocache.overall_mshr_misses::total 47564 # number of overall MSHR misses
|
||||
system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 62666978 # number of ReadReq MSHR miss cycles
|
||||
system.iocache.ReadReq_mshr_miss_latency::total 62666978 # number of ReadReq MSHR miss cycles
|
||||
system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 3961676998 # number of WriteReq MSHR miss cycles
|
||||
system.iocache.WriteReq_mshr_miss_latency::total 3961676998 # number of WriteReq MSHR miss cycles
|
||||
system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 4024343976 # number of demand (read+write) MSHR miss cycles
|
||||
system.iocache.demand_mshr_miss_latency::total 4024343976 # number of demand (read+write) MSHR miss cycles
|
||||
system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 4024343976 # number of overall MSHR miss cycles
|
||||
system.iocache.overall_mshr_miss_latency::total 4024343976 # number of overall MSHR miss cycles
|
||||
system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses
|
||||
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
|
||||
system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses
|
||||
system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
|
||||
system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses
|
||||
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
|
||||
system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses
|
||||
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
|
||||
system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 74249.973934 # average ReadReq mshr miss latency
|
||||
system.iocache.ReadReq_avg_mshr_miss_latency::total 74249.973934 # average ReadReq mshr miss latency
|
||||
system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 84796.168622 # average WriteReq mshr miss latency
|
||||
system.iocache.WriteReq_avg_mshr_miss_latency::total 84796.168622 # average WriteReq mshr miss latency
|
||||
system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 84609.031536 # average overall mshr miss latency
|
||||
system.iocache.demand_avg_mshr_miss_latency::total 84609.031536 # average overall mshr miss latency
|
||||
system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 84609.031536 # average overall mshr miss latency
|
||||
system.iocache.overall_avg_mshr_miss_latency::total 84609.031536 # average overall mshr miss latency
|
||||
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
||||
system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
|
||||
system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD).
|
||||
system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes.
|
||||
system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes.
|
||||
system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions.
|
||||
system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
||||
system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
|
||||
system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD).
|
||||
system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
|
||||
system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
|
||||
system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
|
||||
system.cpu.numCycles 10390940786 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 138138472 # Number of instructions committed
|
||||
system.cpu.committedOps 265147881 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 249556386 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 0 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 24882695 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 249556386 # number of integer instructions
|
||||
system.cpu.num_fp_insts 0 # number of float instructions
|
||||
system.cpu.num_int_register_reads 778086007 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 422921187 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
|
||||
system.cpu.num_mem_refs 23169904 # number of memory refs
|
||||
system.cpu.num_load_insts 14812525 # Number of load instructions
|
||||
system.cpu.num_store_insts 8357379 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 9787777240.878117 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 603163545.121884 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 0.058047 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0.941953 # Percentage of idle cycles
|
||||
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
||||
system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
|
||||
system.cpu.icache.replacements 788139 # number of replacements
|
||||
system.cpu.icache.tagsinuse 510.361283 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 158433932 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 788651 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 200.892324 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 160047116000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 510.361283 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.996799 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.996799 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 158433932 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 158433932 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 158433932 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 158433932 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 158433932 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 158433932 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 788658 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 788658 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 788658 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 788658 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 788658 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 788658 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 11681762500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 11681762500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 11681762500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 11681762500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 11681762500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 11681762500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 159222590 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 159222590 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 159222590 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 159222590 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 159222590 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 159222590 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.004953 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.004953 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.004953 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.004953 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.004953 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.004953 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14812.203135 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 14812.203135 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 14812.203135 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 14812.203135 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 14812.203135 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 14812.203135 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks::writebacks 805 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 805 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 788658 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 788658 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 788658 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 788658 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 788658 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 788658 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9314744000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 9314744000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9314744000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 9314744000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9314744000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 9314744000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.004953 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.004953 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.004953 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.004953 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.004953 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.004953 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11810.878733 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11810.878733 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11810.878733 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 11810.878733 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11810.878733 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 11810.878733 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.itb_walker_cache.replacements 3754 # number of replacements
|
||||
system.cpu.itb_walker_cache.tagsinuse 3.070606 # Cycle average of tags in use
|
||||
system.cpu.itb_walker_cache.total_refs 7549 # Total number of references to valid blocks.
|
||||
system.cpu.itb_walker_cache.sampled_refs 3765 # Sample count of references to valid blocks.
|
||||
system.cpu.itb_walker_cache.avg_refs 2.005046 # Average number of references to valid blocks.
|
||||
system.cpu.itb_walker_cache.warmup_cycle 5178573163000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 3.070606 # Average occupied blocks per requestor
|
||||
system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.191913 # Average percentage of cache occupancy
|
||||
system.cpu.itb_walker_cache.occ_percent::total 0.191913 # Average percentage of cache occupancy
|
||||
system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7619 # number of ReadReq hits
|
||||
system.cpu.itb_walker_cache.ReadReq_hits::total 7619 # number of ReadReq hits
|
||||
system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits
|
||||
system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits
|
||||
system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7621 # number of demand (read+write) hits
|
||||
system.cpu.itb_walker_cache.demand_hits::total 7621 # number of demand (read+write) hits
|
||||
system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7621 # number of overall hits
|
||||
system.cpu.itb_walker_cache.overall_hits::total 7621 # number of overall hits
|
||||
system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4602 # number of ReadReq misses
|
||||
system.cpu.itb_walker_cache.ReadReq_misses::total 4602 # number of ReadReq misses
|
||||
system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4602 # number of demand (read+write) misses
|
||||
system.cpu.itb_walker_cache.demand_misses::total 4602 # number of demand (read+write) misses
|
||||
system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4602 # number of overall misses
|
||||
system.cpu.itb_walker_cache.overall_misses::total 4602 # number of overall misses
|
||||
system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 50817000 # number of ReadReq miss cycles
|
||||
system.cpu.itb_walker_cache.ReadReq_miss_latency::total 50817000 # number of ReadReq miss cycles
|
||||
system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 50817000 # number of demand (read+write) miss cycles
|
||||
system.cpu.itb_walker_cache.demand_miss_latency::total 50817000 # number of demand (read+write) miss cycles
|
||||
system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 50817000 # number of overall miss cycles
|
||||
system.cpu.itb_walker_cache.overall_miss_latency::total 50817000 # number of overall miss cycles
|
||||
system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12221 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.itb_walker_cache.ReadReq_accesses::total 12221 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12223 # number of demand (read+write) accesses
|
||||
system.cpu.itb_walker_cache.demand_accesses::total 12223 # number of demand (read+write) accesses
|
||||
system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12223 # number of overall (read+write) accesses
|
||||
system.cpu.itb_walker_cache.overall_accesses::total 12223 # number of overall (read+write) accesses
|
||||
system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.376565 # miss rate for ReadReq accesses
|
||||
system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.376565 # miss rate for ReadReq accesses
|
||||
system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.376503 # miss rate for demand accesses
|
||||
system.cpu.itb_walker_cache.demand_miss_rate::total 0.376503 # miss rate for demand accesses
|
||||
system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.376503 # miss rate for overall accesses
|
||||
system.cpu.itb_walker_cache.overall_miss_rate::total 0.376503 # miss rate for overall accesses
|
||||
system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11042.372881 # average ReadReq miss latency
|
||||
system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11042.372881 # average ReadReq miss latency
|
||||
system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11042.372881 # average overall miss latency
|
||||
system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11042.372881 # average overall miss latency
|
||||
system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11042.372881 # average overall miss latency
|
||||
system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11042.372881 # average overall miss latency
|
||||
system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.itb_walker_cache.writebacks::writebacks 826 # number of writebacks
|
||||
system.cpu.itb_walker_cache.writebacks::total 826 # number of writebacks
|
||||
system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 4602 # number of ReadReq MSHR misses
|
||||
system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 4602 # number of ReadReq MSHR misses
|
||||
system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 4602 # number of demand (read+write) MSHR misses
|
||||
system.cpu.itb_walker_cache.demand_mshr_misses::total 4602 # number of demand (read+write) MSHR misses
|
||||
system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 4602 # number of overall MSHR misses
|
||||
system.cpu.itb_walker_cache.overall_mshr_misses::total 4602 # number of overall MSHR misses
|
||||
system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 37011000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 37011000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 37011000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 37011000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 37011000 # number of overall MSHR miss cycles
|
||||
system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 37011000 # number of overall MSHR miss cycles
|
||||
system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.376565 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.376565 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.376503 # mshr miss rate for demand accesses
|
||||
system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.376503 # mshr miss rate for demand accesses
|
||||
system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.376503 # mshr miss rate for overall accesses
|
||||
system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.376503 # mshr miss rate for overall accesses
|
||||
system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 8042.372881 # average ReadReq mshr miss latency
|
||||
system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8042.372881 # average ReadReq mshr miss latency
|
||||
system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 8042.372881 # average overall mshr miss latency
|
||||
system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 8042.372881 # average overall mshr miss latency
|
||||
system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 8042.372881 # average overall mshr miss latency
|
||||
system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 8042.372881 # average overall mshr miss latency
|
||||
system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dtb_walker_cache.replacements 7704 # number of replacements
|
||||
system.cpu.dtb_walker_cache.tagsinuse 5.052403 # Cycle average of tags in use
|
||||
system.cpu.dtb_walker_cache.total_refs 13051 # Total number of references to valid blocks.
|
||||
system.cpu.dtb_walker_cache.sampled_refs 7716 # Sample count of references to valid blocks.
|
||||
system.cpu.dtb_walker_cache.avg_refs 1.691420 # Average number of references to valid blocks.
|
||||
system.cpu.dtb_walker_cache.warmup_cycle 5160674969000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 5.052403 # Average occupied blocks per requestor
|
||||
system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.315775 # Average percentage of cache occupancy
|
||||
system.cpu.dtb_walker_cache.occ_percent::total 0.315775 # Average percentage of cache occupancy
|
||||
system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13051 # number of ReadReq hits
|
||||
system.cpu.dtb_walker_cache.ReadReq_hits::total 13051 # number of ReadReq hits
|
||||
system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13051 # number of demand (read+write) hits
|
||||
system.cpu.dtb_walker_cache.demand_hits::total 13051 # number of demand (read+write) hits
|
||||
system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13051 # number of overall hits
|
||||
system.cpu.dtb_walker_cache.overall_hits::total 13051 # number of overall hits
|
||||
system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8896 # number of ReadReq misses
|
||||
system.cpu.dtb_walker_cache.ReadReq_misses::total 8896 # number of ReadReq misses
|
||||
system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8896 # number of demand (read+write) misses
|
||||
system.cpu.dtb_walker_cache.demand_misses::total 8896 # number of demand (read+write) misses
|
||||
system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8896 # number of overall misses
|
||||
system.cpu.dtb_walker_cache.overall_misses::total 8896 # number of overall misses
|
||||
system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 103895500 # number of ReadReq miss cycles
|
||||
system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 103895500 # number of ReadReq miss cycles
|
||||
system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 103895500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dtb_walker_cache.demand_miss_latency::total 103895500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 103895500 # number of overall miss cycles
|
||||
system.cpu.dtb_walker_cache.overall_miss_latency::total 103895500 # number of overall miss cycles
|
||||
system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21947 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dtb_walker_cache.ReadReq_accesses::total 21947 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21947 # number of demand (read+write) accesses
|
||||
system.cpu.dtb_walker_cache.demand_accesses::total 21947 # number of demand (read+write) accesses
|
||||
system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21947 # number of overall (read+write) accesses
|
||||
system.cpu.dtb_walker_cache.overall_accesses::total 21947 # number of overall (read+write) accesses
|
||||
system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.405340 # miss rate for ReadReq accesses
|
||||
system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.405340 # miss rate for ReadReq accesses
|
||||
system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.405340 # miss rate for demand accesses
|
||||
system.cpu.dtb_walker_cache.demand_miss_rate::total 0.405340 # miss rate for demand accesses
|
||||
system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.405340 # miss rate for overall accesses
|
||||
system.cpu.dtb_walker_cache.overall_miss_rate::total 0.405340 # miss rate for overall accesses
|
||||
system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 11678.900629 # average ReadReq miss latency
|
||||
system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 11678.900629 # average ReadReq miss latency
|
||||
system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 11678.900629 # average overall miss latency
|
||||
system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 11678.900629 # average overall miss latency
|
||||
system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 11678.900629 # average overall miss latency
|
||||
system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 11678.900629 # average overall miss latency
|
||||
system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dtb_walker_cache.writebacks::writebacks 2985 # number of writebacks
|
||||
system.cpu.dtb_walker_cache.writebacks::total 2985 # number of writebacks
|
||||
system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 8896 # number of ReadReq MSHR misses
|
||||
system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 8896 # number of ReadReq MSHR misses
|
||||
system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 8896 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dtb_walker_cache.demand_mshr_misses::total 8896 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 8896 # number of overall MSHR misses
|
||||
system.cpu.dtb_walker_cache.overall_mshr_misses::total 8896 # number of overall MSHR misses
|
||||
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 77207000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 77207000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 77207000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 77207000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 77207000 # number of overall MSHR miss cycles
|
||||
system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 77207000 # number of overall MSHR miss cycles
|
||||
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.405340 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.405340 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.405340 # mshr miss rate for demand accesses
|
||||
system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.405340 # mshr miss rate for demand accesses
|
||||
system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.405340 # mshr miss rate for overall accesses
|
||||
system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.405340 # mshr miss rate for overall accesses
|
||||
system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 8678.844424 # average ReadReq mshr miss latency
|
||||
system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8678.844424 # average ReadReq mshr miss latency
|
||||
system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 8678.844424 # average overall mshr miss latency
|
||||
system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 8678.844424 # average overall mshr miss latency
|
||||
system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 8678.844424 # average overall mshr miss latency
|
||||
system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 8678.844424 # average overall mshr miss latency
|
||||
system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 1623424 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 511.997312 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 20011404 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 1623936 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 12.322779 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 44345000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 511.997312 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.999995 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.999995 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 11977182 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 11977182 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 8032009 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 8032009 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 20009191 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 20009191 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 20009191 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 20009191 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 1310824 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 1310824 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 315344 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 315344 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 1626168 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 1626168 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 1626168 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 1626168 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 19851809000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 19851809000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 9514837000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 9514837000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 29366646000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 29366646000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 29366646000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 29366646000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 13288006 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 13288006 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 8347353 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 8347353 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 21635359 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 21635359 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 21635359 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 21635359 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098647 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.098647 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037778 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.037778 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.075163 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.075163 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.075163 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.075163 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15144.526649 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 15144.526649 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30172.881044 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 30172.881044 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 18058.802043 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 18058.802043 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 18058.802043 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 18058.802043 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 1529951 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 1529951 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1310824 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 1310824 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 315344 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 315344 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 1626168 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 1626168 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 1626168 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 1626168 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 15919294500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 15919294500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8568794500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 8568794500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 24488089000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 24488089000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 24488089000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 24488089000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 75925324500 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 75925324500 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1379728500 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1379728500 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 77305053000 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency::total 77305053000 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.098647 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.098647 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037778 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037778 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.075163 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.075163 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.075163 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.075163 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12144.494227 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12144.494227 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27172.847747 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27172.847747 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15058.769451 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 15058.769451 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15058.769451 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 15058.769451 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
@ -0,0 +1,133 @@
|
||||
Linux version 2.6.22.9 (blackga@nacho) (gcc version 4.1.2 (Gentoo 4.1.2)) #2 Mon Oct 8 13:13:00 PDT 2007
|
||||
Command line: earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1
|
||||
BIOS-provided physical RAM map:
|
||||
BIOS-e820: 0000000000000000 - 0000000000100000 (reserved)
|
||||
BIOS-e820: 0000000000100000 - 0000000008000000 (usable)
|
||||
end_pfn_map = 32768
|
||||
kernel direct mapping tables up to 8000000 @ 100000-102000
|
||||
DMI 2.5 present.
|
||||
Zone PFN ranges:
|
||||
DMA 256 -> 4096
|
||||
DMA32 4096 -> 1048576
|
||||
Normal 1048576 -> 1048576
|
||||
early_node_map[1] active PFN ranges
|
||||
0: 256 -> 32768
|
||||
Intel MultiProcessor Specification v1.4
|
||||
MPTABLE: OEM ID: MPTABLE: Product ID: MPTABLE: APIC at: 0xFEE00000
|
||||
Processor #0 (Bootup-CPU)
|
||||
I/O APIC #1 at 0xFEC00000.
|
||||
Setting APIC routing to flat
|
||||
Processors: 1
|
||||
Allocating PCI resources starting at 10000000 (gap: 8000000:f8000000)
|
||||
Built 1 zonelists. Total pages: 30458
|
||||
Kernel command line: earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1
|
||||
Initializing CPU#0
|
||||
PID hash table entries: 512 (order: 9, 4096 bytes)
|
||||
time.c: Detected 1999.998 MHz processor.
|
||||
Console: colour dummy device 80x25
|
||||
console handover: boot [earlyser0] -> real [ttyS0]
|
||||
Dentry cache hash table entries: 16384 (order: 5, 131072 bytes)
|
||||
Inode-cache hash table entries: 8192 (order: 4, 65536 bytes)
|
||||
Checking aperture...
|
||||
Memory: 121556k/131072k available (3742k kernel code, 8456k reserved, 1874k data, 232k init)
|
||||
Calibrating delay loop (skipped)... 3999.96 BogoMIPS preset
|
||||
Mount-cache hash table entries: 256
|
||||
CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)
|
||||
CPU: L2 Cache: 1024K (64 bytes/line)
|
||||
CPU: Fake M5 x86_64 CPU stepping 01
|
||||
ACPI: Core revision 20070126
|
||||
ACPI Exception (tbxface-0618): AE_NO_ACPI_TABLES, While loading namespace from ACPI tables [20070126]
|
||||
ACPI: Unable to load the System Description Tables
|
||||
Using local APIC timer interrupts.
|
||||
result 7812489
|
||||
Detected 7.812 MHz APIC timer.
|
||||
NET: Registered protocol family 16
|
||||
PCI: Using configuration type 1
|
||||
ACPI: Interpreter disabled.
|
||||
Linux Plug and Play Support v0.97 (c) Adam Belay
|
||||
pnp: PnP ACPI: disabled
|
||||
SCSI subsystem initialized
|
||||
usbcore: registered new interface driver usbfs
|
||||
usbcore: registered new interface driver hub
|
||||
usbcore: registered new device driver usb
|
||||
PCI: Probing PCI hardware
|
||||
PCI-GART: No AMD northbridge found.
|
||||
Time: tsc clocksource has been installed.
|
||||
NET: Registered protocol family 2
|
||||
IP route cache hash table entries: 1024 (order: 1, 8192 bytes)
|
||||
TCP established hash table entries: 4096 (order: 4, 65536 bytes)
|
||||
TCP bind hash table entries: 4096 (order: 3, 32768 bytes)
|
||||
TCP: Hash tables configured (established 4096 bind 4096)
|
||||
TCP reno registered
|
||||
Total HugeTLB memory allocated, 0
|
||||
Installing knfsd (copyright (C) 1996 okir@monad.swb.de).
|
||||
io scheduler noop registered
|
||||
io scheduler deadline registered
|
||||
io scheduler cfq registered (default)
|
||||
Real Time Clock Driver v1.12ac
|
||||
Linux agpgart interface v0.102 (c) Dave Jones
|
||||
Serial: 8250/16550 driver $Revision: 1.90 $ 4 ports, IRQ sharing disabled
|
||||
serial8250: ttyS0 at I/O 0x3f8 (irq = 4) is a 8250
|
||||
floppy0: no floppy controllers found
|
||||
RAMDISK driver initialized: 16 RAM disks of 4096K size 1024 blocksize
|
||||
loop: module loaded
|
||||
Intel(R) PRO/1000 Network Driver - version 7.3.20-k2
|
||||
Copyright (c) 1999-2006 Intel Corporation.
|
||||
e100: Intel(R) PRO/100 Network Driver, 3.5.17-k4-NAPI
|
||||
e100: Copyright(c) 1999-2006 Intel Corporation
|
||||
forcedeth.c: Reverse Engineered nForce ethernet driver. Version 0.60.
|
||||
tun: Universal TUN/TAP device driver, 1.6
|
||||
tun: (C) 1999-2004 Max Krasnyansky <maxk@qualcomm.com>
|
||||
netconsole: not configured, aborting
|
||||
Uniform Multi-Platform E-IDE driver Revision: 7.00alpha2
|
||||
ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx
|
||||
PIIX4: IDE controller at PCI slot 0000:00:04.0
|
||||
PCI: Enabling device 0000:00:04.0 (0000 -> 0001)
|
||||
PIIX4: chipset revision 0
|
||||
PIIX4: not 100% native mode: will probe irqs later
|
||||
ide0: BM-DMA at 0x1000-0x1007, BIOS settings: hda:DMA, hdb:DMA
|
||||
ide1: BM-DMA at 0x1008-0x100f, BIOS settings: hdc:DMA, hdd:DMA
|
||||
hda: M5 IDE Disk, ATA DISK drive
|
||||
hdb: M5 IDE Disk, ATA DISK drive
|
||||
ide0 at 0x1f0-0x1f7,0x3f6 on irq 14
|
||||
hda: max request size: 128KiB
|
||||
hda: 1048320 sectors (536 MB), CHS=1040/16/63, UDMA(33)
|
||||
hda: hda1
|
||||
hdb: max request size: 128KiB
|
||||
hdb: 4177920 sectors (2139 MB), CHS=4144/16/63, UDMA(33)
|
||||
hdb: unknown partition table
|
||||
megaraid cmm: 2.20.2.7 (Release Date: Sun Jul 16 00:01:03 EST 2006)
|
||||
megaraid: 2.20.5.1 (Release Date: Thu Nov 16 15:32:35 EST 2006)
|
||||
megasas: 00.00.03.10-rc5 Thu May 17 10:09:32 PDT 2007
|
||||
Fusion MPT base driver 3.04.04
|
||||
Copyright (c) 1999-2007 LSI Logic Corporation
|
||||
Fusion MPT SPI Host driver 3.04.04
|
||||
Fusion MPT SAS Host driver 3.04.04
|
||||
ieee1394: raw1394: /dev/raw1394 device initialized
|
||||
USB Universal Host Controller Interface driver v3.0
|
||||
usbcore: registered new interface driver usblp
|
||||
drivers/usb/class/usblp.c: v0.13: USB Printer Device Class driver
|
||||
Initializing USB Mass Storage driver...
|
||||
usbcore: registered new interface driver usb-storage
|
||||
USB Mass Storage support registered.
|
||||
PNP: No PS/2 controller found. Probing ports directly.
|
||||
serio: i8042 KBD port at 0x60,0x64 irq 1
|
||||
serio: i8042 AUX port at 0x60,0x64 irq 12
|
||||
mice: PS/2 mouse device common for all mice
|
||||
input: AT Translated Set 2 keyboard as /class/input/input0
|
||||
device-mapper: ioctl: 4.11.0-ioctl (2006-10-12) initialised: dm-devel@redhat.com
|
||||
input: PS/2 Generic Mouse as /class/input/input1
|
||||
usbcore: registered new interface driver usbhid
|
||||
drivers/hid/usbhid/hid-core.c: v2.6:USB HID core driver
|
||||
oprofile: using timer interrupt.
|
||||
TCP cubic registered
|
||||
NET: Registered protocol family 1
|
||||
NET: Registered protocol family 10
|
||||
IPv6 over IPv4 tunneling driver
|
||||
NET: Registered protocol family 17
|
||||
EXT2-fs warning: mounting unchecked fs, running e2fsck is recommended
|
||||
VFS: Mounted root (ext2 filesystem).
|
||||
Freeing unused kernel memory: 232k freed
|
||||
|
||||
INIT: version 2.86 booting
|
||||
|
||||
Reference in New Issue
Block a user