Adding gem5 source to svn.
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1819 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
This commit is contained in:
friemel
@ -0,0 +1,913 @@
|
||||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
full_system=true
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
||||
[system]
|
||||
type=LinuxAlphaSystem
|
||||
children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami
|
||||
boot_cpu_frequency=500
|
||||
boot_osflags=root=/dev/hda1 console=ttyS0
|
||||
console=/dist/m5/system/binaries/console
|
||||
init_param=0
|
||||
kernel=/dist/m5/system/binaries/vmlinux
|
||||
load_addr_mask=1099511627775
|
||||
mem_mode=atomic
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
pal=/dist/m5/system/binaries/ts_osfpal
|
||||
readfile=tests/halt.sh
|
||||
symbolfile=
|
||||
system_rev=1024
|
||||
system_type=34
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.membus.slave[0]
|
||||
|
||||
[system.bridge]
|
||||
type=Bridge
|
||||
delay=50000
|
||||
nack_delay=4000
|
||||
ranges=8796093022208:18446744073709551615
|
||||
req_size=16
|
||||
resp_size=16
|
||||
write_ack=false
|
||||
master=system.iobus.slave[0]
|
||||
slave=system.membus.master[0]
|
||||
|
||||
[system.cpu0]
|
||||
type=AtomicSimpleCPU
|
||||
children=dcache dtb icache interrupts itb tracer
|
||||
checker=Null
|
||||
clock=500
|
||||
cpu_id=0
|
||||
defer_registration=false
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu0.dtb
|
||||
fastmem=false
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
interrupts=system.cpu0.interrupts
|
||||
itb=system.cpu0.itb
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
phase=0
|
||||
profile=0
|
||||
progress_interval=0
|
||||
simulate_data_stalls=false
|
||||
simulate_inst_stalls=false
|
||||
system=system
|
||||
tracer=system.cpu0.tracer
|
||||
width=1
|
||||
workload=
|
||||
dcache_port=system.cpu0.dcache.cpu_side
|
||||
icache_port=system.cpu0.icache.cpu_side
|
||||
|
||||
[system.cpu0.dcache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=4
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=32768
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=8
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu0.dcache_port
|
||||
mem_side=system.toL2Bus.slave[1]
|
||||
|
||||
[system.cpu0.dtb]
|
||||
type=AlphaTLB
|
||||
size=64
|
||||
|
||||
[system.cpu0.icache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=1
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=32768
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=8
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu0.icache_port
|
||||
mem_side=system.toL2Bus.slave[0]
|
||||
|
||||
[system.cpu0.interrupts]
|
||||
type=AlphaInterrupts
|
||||
|
||||
[system.cpu0.itb]
|
||||
type=AlphaTLB
|
||||
size=48
|
||||
|
||||
[system.cpu0.tracer]
|
||||
type=ExeTracer
|
||||
|
||||
[system.cpu1]
|
||||
type=AtomicSimpleCPU
|
||||
children=dcache dtb icache interrupts itb tracer
|
||||
checker=Null
|
||||
clock=500
|
||||
cpu_id=1
|
||||
defer_registration=false
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu1.dtb
|
||||
fastmem=false
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
interrupts=system.cpu1.interrupts
|
||||
itb=system.cpu1.itb
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
phase=0
|
||||
profile=0
|
||||
progress_interval=0
|
||||
simulate_data_stalls=false
|
||||
simulate_inst_stalls=false
|
||||
system=system
|
||||
tracer=system.cpu1.tracer
|
||||
width=1
|
||||
workload=
|
||||
dcache_port=system.cpu1.dcache.cpu_side
|
||||
icache_port=system.cpu1.icache.cpu_side
|
||||
|
||||
[system.cpu1.dcache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=4
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=32768
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=8
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu1.dcache_port
|
||||
mem_side=system.toL2Bus.slave[3]
|
||||
|
||||
[system.cpu1.dtb]
|
||||
type=AlphaTLB
|
||||
size=64
|
||||
|
||||
[system.cpu1.icache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=1
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=32768
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=8
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu1.icache_port
|
||||
mem_side=system.toL2Bus.slave[2]
|
||||
|
||||
[system.cpu1.interrupts]
|
||||
type=AlphaInterrupts
|
||||
|
||||
[system.cpu1.itb]
|
||||
type=AlphaTLB
|
||||
size=48
|
||||
|
||||
[system.cpu1.tracer]
|
||||
type=ExeTracer
|
||||
|
||||
[system.disk0]
|
||||
type=IdeDisk
|
||||
children=image
|
||||
delay=1000000
|
||||
driveID=master
|
||||
image=system.disk0.image
|
||||
|
||||
[system.disk0.image]
|
||||
type=CowDiskImage
|
||||
children=child
|
||||
child=system.disk0.image.child
|
||||
image_file=
|
||||
read_only=false
|
||||
table_size=65536
|
||||
|
||||
[system.disk0.image.child]
|
||||
type=RawDiskImage
|
||||
image_file=/dist/m5/system/disks/linux-latest.img
|
||||
read_only=true
|
||||
|
||||
[system.disk2]
|
||||
type=IdeDisk
|
||||
children=image
|
||||
delay=1000000
|
||||
driveID=master
|
||||
image=system.disk2.image
|
||||
|
||||
[system.disk2.image]
|
||||
type=CowDiskImage
|
||||
children=child
|
||||
child=system.disk2.image.child
|
||||
image_file=
|
||||
read_only=false
|
||||
table_size=65536
|
||||
|
||||
[system.disk2.image.child]
|
||||
type=RawDiskImage
|
||||
image_file=/dist/m5/system/disks/linux-bigswap2.img
|
||||
read_only=true
|
||||
|
||||
[system.intrctrl]
|
||||
type=IntrControl
|
||||
sys=system
|
||||
|
||||
[system.iobus]
|
||||
type=NoncoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
use_default_range=true
|
||||
width=64
|
||||
default=system.tsunami.pciconfig.pio
|
||||
master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ethernet.pio system.tsunami.ethernet.config system.iocache.cpu_side
|
||||
slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma
|
||||
|
||||
[system.iocache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:8589934591
|
||||
assoc=8
|
||||
block_size=64
|
||||
forward_snoops=false
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=50000
|
||||
max_miss_count=0
|
||||
mshrs=20
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=1024
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=12
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.iobus.master[29]
|
||||
mem_side=system.membus.slave[1]
|
||||
|
||||
[system.l2c]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=8
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=false
|
||||
latency=10000
|
||||
max_miss_count=0
|
||||
mshrs=92
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=4194304
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=16
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.toL2Bus.master[0]
|
||||
mem_side=system.membus.slave[2]
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
children=badaddr_responder
|
||||
block_size=64
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
default=system.membus.badaddr_responder.pio
|
||||
master=system.bridge.slave system.physmem.port[0]
|
||||
slave=system.system_port system.iocache.mem_side system.l2c.mem_side
|
||||
|
||||
[system.membus.badaddr_responder]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=0
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=true
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.membus.default
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.membus.master[1]
|
||||
|
||||
[system.simple_disk]
|
||||
type=SimpleDisk
|
||||
children=disk
|
||||
disk=system.simple_disk.disk
|
||||
system=system
|
||||
|
||||
[system.simple_disk.disk]
|
||||
type=RawDiskImage
|
||||
image_file=/dist/m5/system/disks/linux-latest.img
|
||||
read_only=true
|
||||
|
||||
[system.terminal]
|
||||
type=Terminal
|
||||
intr_control=system.intrctrl
|
||||
number=0
|
||||
output=true
|
||||
port=3456
|
||||
|
||||
[system.toL2Bus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
master=system.l2c.cpu_side
|
||||
slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side
|
||||
|
||||
[system.tsunami]
|
||||
type=Tsunami
|
||||
children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart
|
||||
intrctrl=system.intrctrl
|
||||
system=system
|
||||
|
||||
[system.tsunami.backdoor]
|
||||
type=AlphaBackdoor
|
||||
cpu=system.cpu0
|
||||
disk=system.simple_disk
|
||||
pio_addr=8804682956800
|
||||
pio_latency=1000
|
||||
platform=system.tsunami
|
||||
system=system
|
||||
terminal=system.terminal
|
||||
pio=system.iobus.master[24]
|
||||
|
||||
[system.tsunami.cchip]
|
||||
type=TsunamiCChip
|
||||
pio_addr=8803072344064
|
||||
pio_latency=1000
|
||||
system=system
|
||||
tsunami=system.tsunami
|
||||
pio=system.iobus.master[0]
|
||||
|
||||
[system.tsunami.ethernet]
|
||||
type=NSGigE
|
||||
BAR0=1
|
||||
BAR0LegacyIO=false
|
||||
BAR0Size=256
|
||||
BAR1=0
|
||||
BAR1LegacyIO=false
|
||||
BAR1Size=4096
|
||||
BAR2=0
|
||||
BAR2LegacyIO=false
|
||||
BAR2Size=0
|
||||
BAR3=0
|
||||
BAR3LegacyIO=false
|
||||
BAR3Size=0
|
||||
BAR4=0
|
||||
BAR4LegacyIO=false
|
||||
BAR4Size=0
|
||||
BAR5=0
|
||||
BAR5LegacyIO=false
|
||||
BAR5Size=0
|
||||
BIST=0
|
||||
CacheLineSize=0
|
||||
CardbusCIS=0
|
||||
ClassCode=2
|
||||
Command=0
|
||||
DeviceID=34
|
||||
ExpansionROM=0
|
||||
HeaderType=0
|
||||
InterruptLine=30
|
||||
InterruptPin=1
|
||||
LatencyTimer=0
|
||||
MaximumLatency=52
|
||||
MinimumGrant=176
|
||||
ProgIF=0
|
||||
Revision=0
|
||||
Status=656
|
||||
SubClassCode=0
|
||||
SubsystemID=0
|
||||
SubsystemVendorID=0
|
||||
VendorID=4107
|
||||
clock=0
|
||||
config_latency=20000
|
||||
dma_data_free=false
|
||||
dma_desc_free=false
|
||||
dma_no_allocate=true
|
||||
dma_read_delay=0
|
||||
dma_read_factor=0
|
||||
dma_write_delay=0
|
||||
dma_write_factor=0
|
||||
hardware_address=00:90:00:00:00:01
|
||||
intr_delay=10000000
|
||||
max_backoff_delay=10000000
|
||||
min_backoff_delay=4000
|
||||
pci_bus=0
|
||||
pci_dev=1
|
||||
pci_func=0
|
||||
pio_latency=1000
|
||||
platform=system.tsunami
|
||||
rss=false
|
||||
rx_delay=1000000
|
||||
rx_fifo_size=524288
|
||||
rx_filter=true
|
||||
rx_thread=false
|
||||
system=system
|
||||
tx_delay=1000000
|
||||
tx_fifo_size=524288
|
||||
tx_thread=false
|
||||
config=system.iobus.master[28]
|
||||
dma=system.iobus.slave[2]
|
||||
pio=system.iobus.master[27]
|
||||
|
||||
[system.tsunami.fake_OROM]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8796093677568
|
||||
pio_latency=1000
|
||||
pio_size=393216
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[8]
|
||||
|
||||
[system.tsunami.fake_ata0]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615848432
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[19]
|
||||
|
||||
[system.tsunami.fake_ata1]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615848304
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[20]
|
||||
|
||||
[system.tsunami.fake_pnp_addr]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615848569
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[9]
|
||||
|
||||
[system.tsunami.fake_pnp_read0]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615848451
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[11]
|
||||
|
||||
[system.tsunami.fake_pnp_read1]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615848515
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[12]
|
||||
|
||||
[system.tsunami.fake_pnp_read2]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615848579
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[13]
|
||||
|
||||
[system.tsunami.fake_pnp_read3]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615848643
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[14]
|
||||
|
||||
[system.tsunami.fake_pnp_read4]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615848707
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[15]
|
||||
|
||||
[system.tsunami.fake_pnp_read5]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615848771
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[16]
|
||||
|
||||
[system.tsunami.fake_pnp_read6]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615848835
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[17]
|
||||
|
||||
[system.tsunami.fake_pnp_read7]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615848899
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[18]
|
||||
|
||||
[system.tsunami.fake_pnp_write]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615850617
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[10]
|
||||
|
||||
[system.tsunami.fake_ppc]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615848891
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[7]
|
||||
|
||||
[system.tsunami.fake_sm_chip]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615848816
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[2]
|
||||
|
||||
[system.tsunami.fake_uart1]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615848696
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[3]
|
||||
|
||||
[system.tsunami.fake_uart2]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615848936
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[4]
|
||||
|
||||
[system.tsunami.fake_uart3]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615848680
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[5]
|
||||
|
||||
[system.tsunami.fake_uart4]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615848944
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[6]
|
||||
|
||||
[system.tsunami.fb]
|
||||
type=BadDevice
|
||||
devicename=FrameBuffer
|
||||
pio_addr=8804615848912
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.iobus.master[21]
|
||||
|
||||
[system.tsunami.ide]
|
||||
type=IdeController
|
||||
BAR0=1
|
||||
BAR0LegacyIO=false
|
||||
BAR0Size=8
|
||||
BAR1=1
|
||||
BAR1LegacyIO=false
|
||||
BAR1Size=4
|
||||
BAR2=1
|
||||
BAR2LegacyIO=false
|
||||
BAR2Size=8
|
||||
BAR3=1
|
||||
BAR3LegacyIO=false
|
||||
BAR3Size=4
|
||||
BAR4=1
|
||||
BAR4LegacyIO=false
|
||||
BAR4Size=16
|
||||
BAR5=1
|
||||
BAR5LegacyIO=false
|
||||
BAR5Size=0
|
||||
BIST=0
|
||||
CacheLineSize=0
|
||||
CardbusCIS=0
|
||||
ClassCode=1
|
||||
Command=0
|
||||
DeviceID=28945
|
||||
ExpansionROM=0
|
||||
HeaderType=0
|
||||
InterruptLine=31
|
||||
InterruptPin=1
|
||||
LatencyTimer=0
|
||||
MaximumLatency=0
|
||||
MinimumGrant=0
|
||||
ProgIF=133
|
||||
Revision=0
|
||||
Status=640
|
||||
SubClassCode=1
|
||||
SubsystemID=0
|
||||
SubsystemVendorID=0
|
||||
VendorID=32902
|
||||
config_latency=20000
|
||||
ctrl_offset=0
|
||||
disks=system.disk0 system.disk2
|
||||
io_shift=0
|
||||
max_backoff_delay=10000000
|
||||
min_backoff_delay=4000
|
||||
pci_bus=0
|
||||
pci_dev=0
|
||||
pci_func=0
|
||||
pio_latency=1000
|
||||
platform=system.tsunami
|
||||
system=system
|
||||
config=system.iobus.master[26]
|
||||
dma=system.iobus.slave[1]
|
||||
pio=system.iobus.master[25]
|
||||
|
||||
[system.tsunami.io]
|
||||
type=TsunamiIO
|
||||
frequency=976562500
|
||||
pio_addr=8804615847936
|
||||
pio_latency=1000
|
||||
system=system
|
||||
time=Thu Jan 1 00:00:00 2009
|
||||
tsunami=system.tsunami
|
||||
year_is_bcd=false
|
||||
pio=system.iobus.master[22]
|
||||
|
||||
[system.tsunami.pchip]
|
||||
type=TsunamiPChip
|
||||
pio_addr=8802535473152
|
||||
pio_latency=1000
|
||||
system=system
|
||||
tsunami=system.tsunami
|
||||
pio=system.iobus.master[1]
|
||||
|
||||
[system.tsunami.pciconfig]
|
||||
type=PciConfigAll
|
||||
bus=0
|
||||
pio_latency=1
|
||||
platform=system.tsunami
|
||||
size=16777216
|
||||
system=system
|
||||
pio=system.iobus.default
|
||||
|
||||
[system.tsunami.uart]
|
||||
type=Uart8250
|
||||
pio_addr=8804615848952
|
||||
pio_latency=1000
|
||||
platform=system.tsunami
|
||||
system=system
|
||||
terminal=system.terminal
|
||||
pio=system.iobus.master[23]
|
||||
|
||||
@ -0,0 +1,5 @@
|
||||
warn: Sockets disabled, not accepting terminal connections
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: Prefetch instructions in Alpha do not do anything
|
||||
warn: Prefetch instructions in Alpha do not do anything
|
||||
hack: be nice to actually delete the event here
|
||||
@ -0,0 +1,13 @@
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jun 4 2012 11:50:11
|
||||
gem5 started Jun 4 2012 14:39:49
|
||||
gem5 executing on zizzer
|
||||
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual -re tests/run.py build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: kernel located at: /dist/m5/system/binaries/vmlinux
|
||||
0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Launching CPU 1 @ 97861500
|
||||
Exiting @ tick 1870335522500 because m5_exit instruction encountered
|
||||
@ -0,0 +1,762 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 1.870336 # Number of seconds simulated
|
||||
sim_ticks 1870335522500 # Number of ticks simulated
|
||||
final_tick 1870335522500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 2870976 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2870973 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 85025108641 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 298608 # Number of bytes of host memory used
|
||||
host_seconds 22.00 # Real time elapsed on the host
|
||||
sim_insts 63154034 # Number of instructions simulated
|
||||
sim_ops 63154034 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu0.inst 855168 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu0.data 67882688 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::tsunami.ide 2649600 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu1.inst 139840 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu1.data 770176 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 72297472 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu0.inst 855168 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu1.inst 139840 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 995008 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 10452352 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 10452352 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu0.inst 13362 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu0.data 1060667 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::tsunami.ide 41400 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu1.inst 2185 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu1.data 12034 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 1129648 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 163318 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 163318 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu0.inst 457227 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu0.data 36294391 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::tsunami.ide 1416644 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu1.inst 74767 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu1.data 411785 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 38654814 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu0.inst 457227 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu1.inst 74767 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 531994 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 5588490 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 5588490 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 5588490 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu0.inst 457227 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu0.data 36294391 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::tsunami.ide 1416644 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu1.inst 74767 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu1.data 411785 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 44243304 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.l2c.replacements 1051788 # number of replacements
|
||||
system.l2c.tagsinuse 34117.721410 # Cycle average of tags in use
|
||||
system.l2c.total_refs 2341203 # Total number of references to valid blocks.
|
||||
system.l2c.sampled_refs 1087985 # Sample count of references to valid blocks.
|
||||
system.l2c.avg_refs 2.151871 # Average number of references to valid blocks.
|
||||
system.l2c.warmup_cycle 990121000 # Cycle when the warmup percentage was hit.
|
||||
system.l2c.occ_blocks::writebacks 23831.931773 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu0.inst 3683.485712 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu0.data 6336.188239 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu1.inst 152.381317 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu1.data 113.734368 # Average occupied blocks per requestor
|
||||
system.l2c.occ_percent::writebacks 0.363646 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu0.inst 0.056206 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu0.data 0.096683 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu1.inst 0.002325 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu1.data 0.001735 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::total 0.520595 # Average percentage of cache occupancy
|
||||
system.l2c.ReadReq_hits::cpu0.inst 871618 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu0.data 748887 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu1.inst 101445 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu1.data 35685 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::total 1757635 # number of ReadReq hits
|
||||
system.l2c.Writeback_hits::writebacks 811846 # number of Writeback hits
|
||||
system.l2c.Writeback_hits::total 811846 # number of Writeback hits
|
||||
system.l2c.UpgradeReq_hits::cpu0.data 134 # number of UpgradeReq hits
|
||||
system.l2c.UpgradeReq_hits::cpu1.data 39 # number of UpgradeReq hits
|
||||
system.l2c.UpgradeReq_hits::total 173 # number of UpgradeReq hits
|
||||
system.l2c.SCUpgradeReq_hits::cpu0.data 15 # number of SCUpgradeReq hits
|
||||
system.l2c.SCUpgradeReq_hits::cpu1.data 9 # number of SCUpgradeReq hits
|
||||
system.l2c.SCUpgradeReq_hits::total 24 # number of SCUpgradeReq hits
|
||||
system.l2c.ReadExReq_hits::cpu0.data 164417 # number of ReadExReq hits
|
||||
system.l2c.ReadExReq_hits::cpu1.data 14126 # number of ReadExReq hits
|
||||
system.l2c.ReadExReq_hits::total 178543 # number of ReadExReq hits
|
||||
system.l2c.demand_hits::cpu0.inst 871618 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu0.data 913304 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu1.inst 101445 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu1.data 49811 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::total 1936178 # number of demand (read+write) hits
|
||||
system.l2c.overall_hits::cpu0.inst 871618 # number of overall hits
|
||||
system.l2c.overall_hits::cpu0.data 913304 # number of overall hits
|
||||
system.l2c.overall_hits::cpu1.inst 101445 # number of overall hits
|
||||
system.l2c.overall_hits::cpu1.data 49811 # number of overall hits
|
||||
system.l2c.overall_hits::total 1936178 # number of overall hits
|
||||
system.l2c.ReadReq_misses::cpu0.inst 13362 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu0.data 943555 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu1.inst 2185 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu1.data 2326 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::total 961428 # number of ReadReq misses
|
||||
system.l2c.UpgradeReq_misses::cpu0.data 2441 # number of UpgradeReq misses
|
||||
system.l2c.UpgradeReq_misses::cpu1.data 567 # number of UpgradeReq misses
|
||||
system.l2c.UpgradeReq_misses::total 3008 # number of UpgradeReq misses
|
||||
system.l2c.SCUpgradeReq_misses::cpu0.data 65 # number of SCUpgradeReq misses
|
||||
system.l2c.SCUpgradeReq_misses::cpu1.data 101 # number of SCUpgradeReq misses
|
||||
system.l2c.SCUpgradeReq_misses::total 166 # number of SCUpgradeReq misses
|
||||
system.l2c.ReadExReq_misses::cpu0.data 117481 # number of ReadExReq misses
|
||||
system.l2c.ReadExReq_misses::cpu1.data 9826 # number of ReadExReq misses
|
||||
system.l2c.ReadExReq_misses::total 127307 # number of ReadExReq misses
|
||||
system.l2c.demand_misses::cpu0.inst 13362 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu0.data 1061036 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu1.inst 2185 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu1.data 12152 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::total 1088735 # number of demand (read+write) misses
|
||||
system.l2c.overall_misses::cpu0.inst 13362 # number of overall misses
|
||||
system.l2c.overall_misses::cpu0.data 1061036 # number of overall misses
|
||||
system.l2c.overall_misses::cpu1.inst 2185 # number of overall misses
|
||||
system.l2c.overall_misses::cpu1.data 12152 # number of overall misses
|
||||
system.l2c.overall_misses::total 1088735 # number of overall misses
|
||||
system.l2c.ReadReq_accesses::cpu0.inst 884980 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::cpu0.data 1692442 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::cpu1.inst 103630 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::cpu1.data 38011 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::total 2719063 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.Writeback_accesses::writebacks 811846 # number of Writeback accesses(hits+misses)
|
||||
system.l2c.Writeback_accesses::total 811846 # number of Writeback accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_accesses::cpu0.data 2575 # number of UpgradeReq accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_accesses::cpu1.data 606 # number of UpgradeReq accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_accesses::total 3181 # number of UpgradeReq accesses(hits+misses)
|
||||
system.l2c.SCUpgradeReq_accesses::cpu0.data 80 # number of SCUpgradeReq accesses(hits+misses)
|
||||
system.l2c.SCUpgradeReq_accesses::cpu1.data 110 # number of SCUpgradeReq accesses(hits+misses)
|
||||
system.l2c.SCUpgradeReq_accesses::total 190 # number of SCUpgradeReq accesses(hits+misses)
|
||||
system.l2c.ReadExReq_accesses::cpu0.data 281898 # number of ReadExReq accesses(hits+misses)
|
||||
system.l2c.ReadExReq_accesses::cpu1.data 23952 # number of ReadExReq accesses(hits+misses)
|
||||
system.l2c.ReadExReq_accesses::total 305850 # number of ReadExReq accesses(hits+misses)
|
||||
system.l2c.demand_accesses::cpu0.inst 884980 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu0.data 1974340 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu1.inst 103630 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu1.data 61963 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::total 3024913 # number of demand (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu0.inst 884980 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu0.data 1974340 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu1.inst 103630 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu1.data 61963 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::total 3024913 # number of overall (read+write) accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu0.inst 0.015099 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu0.data 0.557511 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu1.inst 0.021085 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu1.data 0.061193 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::total 0.353588 # miss rate for ReadReq accesses
|
||||
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.947961 # miss rate for UpgradeReq accesses
|
||||
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.935644 # miss rate for UpgradeReq accesses
|
||||
system.l2c.UpgradeReq_miss_rate::total 0.945615 # miss rate for UpgradeReq accesses
|
||||
system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.812500 # miss rate for SCUpgradeReq accesses
|
||||
system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.918182 # miss rate for SCUpgradeReq accesses
|
||||
system.l2c.SCUpgradeReq_miss_rate::total 0.873684 # miss rate for SCUpgradeReq accesses
|
||||
system.l2c.ReadExReq_miss_rate::cpu0.data 0.416750 # miss rate for ReadExReq accesses
|
||||
system.l2c.ReadExReq_miss_rate::cpu1.data 0.410237 # miss rate for ReadExReq accesses
|
||||
system.l2c.ReadExReq_miss_rate::total 0.416240 # miss rate for ReadExReq accesses
|
||||
system.l2c.demand_miss_rate::cpu0.inst 0.015099 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu0.data 0.537413 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu1.inst 0.021085 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu1.data 0.196117 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::total 0.359923 # miss rate for demand accesses
|
||||
system.l2c.overall_miss_rate::cpu0.inst 0.015099 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu0.data 0.537413 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu1.inst 0.021085 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu1.data 0.196117 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::total 0.359923 # miss rate for overall accesses
|
||||
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.l2c.fast_writes 0 # number of fast writes performed
|
||||
system.l2c.cache_copies 0 # number of cache copies performed
|
||||
system.l2c.writebacks::writebacks 121798 # number of writebacks
|
||||
system.l2c.writebacks::total 121798 # number of writebacks
|
||||
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.iocache.replacements 41695 # number of replacements
|
||||
system.iocache.tagsinuse 0.435437 # Cycle average of tags in use
|
||||
system.iocache.total_refs 0 # Total number of references to valid blocks.
|
||||
system.iocache.sampled_refs 41711 # Sample count of references to valid blocks.
|
||||
system.iocache.avg_refs 0 # Average number of references to valid blocks.
|
||||
system.iocache.warmup_cycle 1685787165017 # Cycle when the warmup percentage was hit.
|
||||
system.iocache.occ_blocks::tsunami.ide 0.435437 # Average occupied blocks per requestor
|
||||
system.iocache.occ_percent::tsunami.ide 0.027215 # Average percentage of cache occupancy
|
||||
system.iocache.occ_percent::total 0.027215 # Average percentage of cache occupancy
|
||||
system.iocache.ReadReq_misses::tsunami.ide 175 # number of ReadReq misses
|
||||
system.iocache.ReadReq_misses::total 175 # number of ReadReq misses
|
||||
system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses
|
||||
system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses
|
||||
system.iocache.demand_misses::tsunami.ide 41727 # number of demand (read+write) misses
|
||||
system.iocache.demand_misses::total 41727 # number of demand (read+write) misses
|
||||
system.iocache.overall_misses::tsunami.ide 41727 # number of overall misses
|
||||
system.iocache.overall_misses::total 41727 # number of overall misses
|
||||
system.iocache.ReadReq_accesses::tsunami.ide 175 # number of ReadReq accesses(hits+misses)
|
||||
system.iocache.ReadReq_accesses::total 175 # number of ReadReq accesses(hits+misses)
|
||||
system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses)
|
||||
system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses)
|
||||
system.iocache.demand_accesses::tsunami.ide 41727 # number of demand (read+write) accesses
|
||||
system.iocache.demand_accesses::total 41727 # number of demand (read+write) accesses
|
||||
system.iocache.overall_accesses::tsunami.ide 41727 # number of overall (read+write) accesses
|
||||
system.iocache.overall_accesses::total 41727 # number of overall (read+write) accesses
|
||||
system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
|
||||
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
|
||||
system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses
|
||||
system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
|
||||
system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses
|
||||
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
|
||||
system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
|
||||
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
|
||||
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.iocache.fast_writes 0 # number of fast writes performed
|
||||
system.iocache.cache_copies 0 # number of cache copies performed
|
||||
system.iocache.writebacks::writebacks 41520 # number of writebacks
|
||||
system.iocache.writebacks::total 41520 # number of writebacks
|
||||
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
||||
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
|
||||
system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
|
||||
system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
|
||||
system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
|
||||
system.disk0.dma_write_txs 395 # Number of DMA write transactions.
|
||||
system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
||||
system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
|
||||
system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
|
||||
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
|
||||
system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
|
||||
system.disk2.dma_write_txs 1 # Number of DMA write transactions.
|
||||
system.cpu0.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu0.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu0.dtb.fetch_acv 0 # ITB acv
|
||||
system.cpu0.dtb.fetch_accesses 0 # ITB accesses
|
||||
system.cpu0.dtb.read_hits 9154530 # DTB read hits
|
||||
system.cpu0.dtb.read_misses 7079 # DTB read misses
|
||||
system.cpu0.dtb.read_acv 152 # DTB read access violations
|
||||
system.cpu0.dtb.read_accesses 508987 # DTB read accesses
|
||||
system.cpu0.dtb.write_hits 5936899 # DTB write hits
|
||||
system.cpu0.dtb.write_misses 726 # DTB write misses
|
||||
system.cpu0.dtb.write_acv 99 # DTB write access violations
|
||||
system.cpu0.dtb.write_accesses 189050 # DTB write accesses
|
||||
system.cpu0.dtb.data_hits 15091429 # DTB hits
|
||||
system.cpu0.dtb.data_misses 7805 # DTB misses
|
||||
system.cpu0.dtb.data_acv 251 # DTB access violations
|
||||
system.cpu0.dtb.data_accesses 698037 # DTB accesses
|
||||
system.cpu0.itb.fetch_hits 3855556 # ITB hits
|
||||
system.cpu0.itb.fetch_misses 3485 # ITB misses
|
||||
system.cpu0.itb.fetch_acv 127 # ITB acv
|
||||
system.cpu0.itb.fetch_accesses 3859041 # ITB accesses
|
||||
system.cpu0.itb.read_hits 0 # DTB read hits
|
||||
system.cpu0.itb.read_misses 0 # DTB read misses
|
||||
system.cpu0.itb.read_acv 0 # DTB read access violations
|
||||
system.cpu0.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu0.itb.write_hits 0 # DTB write hits
|
||||
system.cpu0.itb.write_misses 0 # DTB write misses
|
||||
system.cpu0.itb.write_acv 0 # DTB write access violations
|
||||
system.cpu0.itb.write_accesses 0 # DTB write accesses
|
||||
system.cpu0.itb.data_hits 0 # DTB hits
|
||||
system.cpu0.itb.data_misses 0 # DTB misses
|
||||
system.cpu0.itb.data_acv 0 # DTB access violations
|
||||
system.cpu0.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu0.numCycles 3740670933 # number of cpu cycles simulated
|
||||
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu0.committedInsts 57222076 # Number of instructions committed
|
||||
system.cpu0.committedOps 57222076 # Number of ops (including micro ops) committed
|
||||
system.cpu0.num_int_alu_accesses 53249924 # Number of integer alu accesses
|
||||
system.cpu0.num_fp_alu_accesses 299810 # Number of float alu accesses
|
||||
system.cpu0.num_func_calls 1399585 # number of times a function call or return occured
|
||||
system.cpu0.num_conditional_control_insts 6808233 # number of instructions that are conditional controls
|
||||
system.cpu0.num_int_insts 53249924 # number of integer instructions
|
||||
system.cpu0.num_fp_insts 299810 # number of float instructions
|
||||
system.cpu0.num_int_register_reads 73318596 # number of times the integer registers were read
|
||||
system.cpu0.num_int_register_writes 39827534 # number of times the integer registers were written
|
||||
system.cpu0.num_fp_register_reads 147724 # number of times the floating registers were read
|
||||
system.cpu0.num_fp_register_writes 150835 # number of times the floating registers were written
|
||||
system.cpu0.num_mem_refs 15135515 # number of memory refs
|
||||
system.cpu0.num_load_insts 9184477 # Number of load instructions
|
||||
system.cpu0.num_store_insts 5951038 # Number of store instructions
|
||||
system.cpu0.num_idle_cycles 3683437089.313678 # Number of idle cycles
|
||||
system.cpu0.num_busy_cycles 57233843.686322 # Number of busy cycles
|
||||
system.cpu0.not_idle_fraction 0.015300 # Percentage of non-idle cycles
|
||||
system.cpu0.idle_fraction 0.984700 # Percentage of idle cycles
|
||||
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
|
||||
system.cpu0.kern.inst.quiesce 6283 # number of quiesce instructions executed
|
||||
system.cpu0.kern.inst.hwrei 197120 # number of hwrei instructions executed
|
||||
system.cpu0.kern.ipl_count::0 71004 40.60% 40.60% # number of times we switched to this ipl
|
||||
system.cpu0.kern.ipl_count::21 243 0.14% 40.74% # number of times we switched to this ipl
|
||||
system.cpu0.kern.ipl_count::22 1908 1.09% 41.83% # number of times we switched to this ipl
|
||||
system.cpu0.kern.ipl_count::30 8 0.00% 41.84% # number of times we switched to this ipl
|
||||
system.cpu0.kern.ipl_count::31 101705 58.16% 100.00% # number of times we switched to this ipl
|
||||
system.cpu0.kern.ipl_count::total 174868 # number of times we switched to this ipl
|
||||
system.cpu0.kern.ipl_good::0 69637 49.24% 49.24% # number of times we switched to this ipl from a different ipl
|
||||
system.cpu0.kern.ipl_good::21 243 0.17% 49.41% # number of times we switched to this ipl from a different ipl
|
||||
system.cpu0.kern.ipl_good::22 1908 1.35% 50.76% # number of times we switched to this ipl from a different ipl
|
||||
system.cpu0.kern.ipl_good::30 8 0.01% 50.77% # number of times we switched to this ipl from a different ipl
|
||||
system.cpu0.kern.ipl_good::31 69629 49.23% 100.00% # number of times we switched to this ipl from a different ipl
|
||||
system.cpu0.kern.ipl_good::total 141425 # number of times we switched to this ipl from a different ipl
|
||||
system.cpu0.kern.ipl_ticks::0 1852989766500 99.07% 99.07% # number of cycles we spent at this ipl
|
||||
system.cpu0.kern.ipl_ticks::21 20110000 0.00% 99.07% # number of cycles we spent at this ipl
|
||||
system.cpu0.kern.ipl_ticks::22 82044000 0.00% 99.08% # number of cycles we spent at this ipl
|
||||
system.cpu0.kern.ipl_ticks::30 949500 0.00% 99.08% # number of cycles we spent at this ipl
|
||||
system.cpu0.kern.ipl_ticks::31 17242445000 0.92% 100.00% # number of cycles we spent at this ipl
|
||||
system.cpu0.kern.ipl_ticks::total 1870335315000 # number of cycles we spent at this ipl
|
||||
system.cpu0.kern.ipl_used::0 0.980748 # fraction of swpipl calls that actually changed the ipl
|
||||
system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
|
||||
system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
|
||||
system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
|
||||
system.cpu0.kern.ipl_used::31 0.684617 # fraction of swpipl calls that actually changed the ipl
|
||||
system.cpu0.kern.ipl_used::total 0.808753 # fraction of swpipl calls that actually changed the ipl
|
||||
system.cpu0.kern.syscall::2 6 2.65% 2.65% # number of syscalls executed
|
||||
system.cpu0.kern.syscall::3 19 8.41% 11.06% # number of syscalls executed
|
||||
system.cpu0.kern.syscall::4 2 0.88% 11.95% # number of syscalls executed
|
||||
system.cpu0.kern.syscall::6 32 14.16% 26.11% # number of syscalls executed
|
||||
system.cpu0.kern.syscall::12 1 0.44% 26.55% # number of syscalls executed
|
||||
system.cpu0.kern.syscall::15 1 0.44% 26.99% # number of syscalls executed
|
||||
system.cpu0.kern.syscall::17 9 3.98% 30.97% # number of syscalls executed
|
||||
system.cpu0.kern.syscall::19 8 3.54% 34.51% # number of syscalls executed
|
||||
system.cpu0.kern.syscall::20 6 2.65% 37.17% # number of syscalls executed
|
||||
system.cpu0.kern.syscall::23 2 0.88% 38.05% # number of syscalls executed
|
||||
system.cpu0.kern.syscall::24 4 1.77% 39.82% # number of syscalls executed
|
||||
system.cpu0.kern.syscall::33 7 3.10% 42.92% # number of syscalls executed
|
||||
system.cpu0.kern.syscall::41 2 0.88% 43.81% # number of syscalls executed
|
||||
system.cpu0.kern.syscall::45 37 16.37% 60.18% # number of syscalls executed
|
||||
system.cpu0.kern.syscall::47 4 1.77% 61.95% # number of syscalls executed
|
||||
system.cpu0.kern.syscall::48 8 3.54% 65.49% # number of syscalls executed
|
||||
system.cpu0.kern.syscall::54 10 4.42% 69.91% # number of syscalls executed
|
||||
system.cpu0.kern.syscall::58 1 0.44% 70.35% # number of syscalls executed
|
||||
system.cpu0.kern.syscall::59 4 1.77% 72.12% # number of syscalls executed
|
||||
system.cpu0.kern.syscall::71 30 13.27% 85.40% # number of syscalls executed
|
||||
system.cpu0.kern.syscall::73 3 1.33% 86.73% # number of syscalls executed
|
||||
system.cpu0.kern.syscall::74 8 3.54% 90.27% # number of syscalls executed
|
||||
system.cpu0.kern.syscall::87 1 0.44% 90.71% # number of syscalls executed
|
||||
system.cpu0.kern.syscall::90 2 0.88% 91.59% # number of syscalls executed
|
||||
system.cpu0.kern.syscall::92 9 3.98% 95.58% # number of syscalls executed
|
||||
system.cpu0.kern.syscall::97 2 0.88% 96.46% # number of syscalls executed
|
||||
system.cpu0.kern.syscall::98 2 0.88% 97.35% # number of syscalls executed
|
||||
system.cpu0.kern.syscall::132 2 0.88% 98.23% # number of syscalls executed
|
||||
system.cpu0.kern.syscall::144 2 0.88% 99.12% # number of syscalls executed
|
||||
system.cpu0.kern.syscall::147 2 0.88% 100.00% # number of syscalls executed
|
||||
system.cpu0.kern.syscall::total 226 # number of syscalls executed
|
||||
system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
|
||||
system.cpu0.kern.callpal::wripir 110 0.06% 0.06% # number of callpals executed
|
||||
system.cpu0.kern.callpal::wrmces 1 0.00% 0.06% # number of callpals executed
|
||||
system.cpu0.kern.callpal::wrfen 1 0.00% 0.06% # number of callpals executed
|
||||
system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.06% # number of callpals executed
|
||||
system.cpu0.kern.callpal::swpctx 3762 2.05% 2.11% # number of callpals executed
|
||||
system.cpu0.kern.callpal::tbi 38 0.02% 2.14% # number of callpals executed
|
||||
system.cpu0.kern.callpal::wrent 7 0.00% 2.14% # number of callpals executed
|
||||
system.cpu0.kern.callpal::swpipl 168035 91.68% 93.82% # number of callpals executed
|
||||
system.cpu0.kern.callpal::rdps 6150 3.36% 97.17% # number of callpals executed
|
||||
system.cpu0.kern.callpal::wrkgp 1 0.00% 97.17% # number of callpals executed
|
||||
system.cpu0.kern.callpal::wrusp 3 0.00% 97.17% # number of callpals executed
|
||||
system.cpu0.kern.callpal::rdusp 7 0.00% 97.18% # number of callpals executed
|
||||
system.cpu0.kern.callpal::whami 2 0.00% 97.18% # number of callpals executed
|
||||
system.cpu0.kern.callpal::rti 4673 2.55% 99.73% # number of callpals executed
|
||||
system.cpu0.kern.callpal::callsys 357 0.19% 99.92% # number of callpals executed
|
||||
system.cpu0.kern.callpal::imb 142 0.08% 100.00% # number of callpals executed
|
||||
system.cpu0.kern.callpal::total 183291 # number of callpals executed
|
||||
system.cpu0.kern.mode_switch::kernel 7091 # number of protection mode switches
|
||||
system.cpu0.kern.mode_switch::user 1158 # number of protection mode switches
|
||||
system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches
|
||||
system.cpu0.kern.mode_good::kernel 1157
|
||||
system.cpu0.kern.mode_good::user 1158
|
||||
system.cpu0.kern.mode_good::idle 0
|
||||
system.cpu0.kern.mode_switch_good::kernel 0.163165 # fraction of useful protection mode switches
|
||||
system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
|
||||
system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches
|
||||
system.cpu0.kern.mode_switch_good::total 0.280640 # fraction of useful protection mode switches
|
||||
system.cpu0.kern.mode_ticks::kernel 1869378305000 99.95% 99.95% # number of ticks spent at the given mode
|
||||
system.cpu0.kern.mode_ticks::user 957009000 0.05% 100.00% # number of ticks spent at the given mode
|
||||
system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode
|
||||
system.cpu0.kern.swap_context 3763 # number of times the context was actually changed
|
||||
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
|
||||
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
|
||||
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
|
||||
system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
|
||||
system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
|
||||
system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
|
||||
system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
|
||||
system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
|
||||
system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
|
||||
system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
|
||||
system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
|
||||
system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
|
||||
system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
|
||||
system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
|
||||
system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
|
||||
system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
|
||||
system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
|
||||
system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
|
||||
system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
|
||||
system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
|
||||
system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
|
||||
system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
|
||||
system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
|
||||
system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
|
||||
system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
|
||||
system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
|
||||
system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
|
||||
system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
|
||||
system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
|
||||
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
|
||||
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
|
||||
system.cpu0.icache.replacements 884404 # number of replacements
|
||||
system.cpu0.icache.tagsinuse 511.244754 # Cycle average of tags in use
|
||||
system.cpu0.icache.total_refs 56345132 # Total number of references to valid blocks.
|
||||
system.cpu0.icache.sampled_refs 884916 # Sample count of references to valid blocks.
|
||||
system.cpu0.icache.avg_refs 63.672859 # Average number of references to valid blocks.
|
||||
system.cpu0.icache.warmup_cycle 9786576500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu0.icache.occ_blocks::cpu0.inst 511.244754 # Average occupied blocks per requestor
|
||||
system.cpu0.icache.occ_percent::cpu0.inst 0.998525 # Average percentage of cache occupancy
|
||||
system.cpu0.icache.occ_percent::total 0.998525 # Average percentage of cache occupancy
|
||||
system.cpu0.icache.ReadReq_hits::cpu0.inst 56345132 # number of ReadReq hits
|
||||
system.cpu0.icache.ReadReq_hits::total 56345132 # number of ReadReq hits
|
||||
system.cpu0.icache.demand_hits::cpu0.inst 56345132 # number of demand (read+write) hits
|
||||
system.cpu0.icache.demand_hits::total 56345132 # number of demand (read+write) hits
|
||||
system.cpu0.icache.overall_hits::cpu0.inst 56345132 # number of overall hits
|
||||
system.cpu0.icache.overall_hits::total 56345132 # number of overall hits
|
||||
system.cpu0.icache.ReadReq_misses::cpu0.inst 885000 # number of ReadReq misses
|
||||
system.cpu0.icache.ReadReq_misses::total 885000 # number of ReadReq misses
|
||||
system.cpu0.icache.demand_misses::cpu0.inst 885000 # number of demand (read+write) misses
|
||||
system.cpu0.icache.demand_misses::total 885000 # number of demand (read+write) misses
|
||||
system.cpu0.icache.overall_misses::cpu0.inst 885000 # number of overall misses
|
||||
system.cpu0.icache.overall_misses::total 885000 # number of overall misses
|
||||
system.cpu0.icache.ReadReq_accesses::cpu0.inst 57230132 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu0.icache.ReadReq_accesses::total 57230132 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu0.icache.demand_accesses::cpu0.inst 57230132 # number of demand (read+write) accesses
|
||||
system.cpu0.icache.demand_accesses::total 57230132 # number of demand (read+write) accesses
|
||||
system.cpu0.icache.overall_accesses::cpu0.inst 57230132 # number of overall (read+write) accesses
|
||||
system.cpu0.icache.overall_accesses::total 57230132 # number of overall (read+write) accesses
|
||||
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.015464 # miss rate for ReadReq accesses
|
||||
system.cpu0.icache.ReadReq_miss_rate::total 0.015464 # miss rate for ReadReq accesses
|
||||
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.015464 # miss rate for demand accesses
|
||||
system.cpu0.icache.demand_miss_rate::total 0.015464 # miss rate for demand accesses
|
||||
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.015464 # miss rate for overall accesses
|
||||
system.cpu0.icache.overall_miss_rate::total 0.015464 # miss rate for overall accesses
|
||||
system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu0.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu0.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu0.icache.writebacks::writebacks 95 # number of writebacks
|
||||
system.cpu0.icache.writebacks::total 95 # number of writebacks
|
||||
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu0.dcache.replacements 1978962 # number of replacements
|
||||
system.cpu0.dcache.tagsinuse 504.827058 # Cycle average of tags in use
|
||||
system.cpu0.dcache.total_refs 13123502 # Total number of references to valid blocks.
|
||||
system.cpu0.dcache.sampled_refs 1979474 # Sample count of references to valid blocks.
|
||||
system.cpu0.dcache.avg_refs 6.629793 # Average number of references to valid blocks.
|
||||
system.cpu0.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu0.dcache.occ_blocks::cpu0.data 504.827058 # Average occupied blocks per requestor
|
||||
system.cpu0.dcache.occ_percent::cpu0.data 0.985990 # Average percentage of cache occupancy
|
||||
system.cpu0.dcache.occ_percent::total 0.985990 # Average percentage of cache occupancy
|
||||
system.cpu0.dcache.ReadReq_hits::cpu0.data 7298106 # number of ReadReq hits
|
||||
system.cpu0.dcache.ReadReq_hits::total 7298106 # number of ReadReq hits
|
||||
system.cpu0.dcache.WriteReq_hits::cpu0.data 5462265 # number of WriteReq hits
|
||||
system.cpu0.dcache.WriteReq_hits::total 5462265 # number of WriteReq hits
|
||||
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 172138 # number of LoadLockedReq hits
|
||||
system.cpu0.dcache.LoadLockedReq_hits::total 172138 # number of LoadLockedReq hits
|
||||
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 186635 # number of StoreCondReq hits
|
||||
system.cpu0.dcache.StoreCondReq_hits::total 186635 # number of StoreCondReq hits
|
||||
system.cpu0.dcache.demand_hits::cpu0.data 12760371 # number of demand (read+write) hits
|
||||
system.cpu0.dcache.demand_hits::total 12760371 # number of demand (read+write) hits
|
||||
system.cpu0.dcache.overall_hits::cpu0.data 12760371 # number of overall hits
|
||||
system.cpu0.dcache.overall_hits::total 12760371 # number of overall hits
|
||||
system.cpu0.dcache.ReadReq_misses::cpu0.data 1683563 # number of ReadReq misses
|
||||
system.cpu0.dcache.ReadReq_misses::total 1683563 # number of ReadReq misses
|
||||
system.cpu0.dcache.WriteReq_misses::cpu0.data 285996 # number of WriteReq misses
|
||||
system.cpu0.dcache.WriteReq_misses::total 285996 # number of WriteReq misses
|
||||
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 16159 # number of LoadLockedReq misses
|
||||
system.cpu0.dcache.LoadLockedReq_misses::total 16159 # number of LoadLockedReq misses
|
||||
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 703 # number of StoreCondReq misses
|
||||
system.cpu0.dcache.StoreCondReq_misses::total 703 # number of StoreCondReq misses
|
||||
system.cpu0.dcache.demand_misses::cpu0.data 1969559 # number of demand (read+write) misses
|
||||
system.cpu0.dcache.demand_misses::total 1969559 # number of demand (read+write) misses
|
||||
system.cpu0.dcache.overall_misses::cpu0.data 1969559 # number of overall misses
|
||||
system.cpu0.dcache.overall_misses::total 1969559 # number of overall misses
|
||||
system.cpu0.dcache.ReadReq_accesses::cpu0.data 8981669 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu0.dcache.ReadReq_accesses::total 8981669 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu0.dcache.WriteReq_accesses::cpu0.data 5748261 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu0.dcache.WriteReq_accesses::total 5748261 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 188297 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu0.dcache.LoadLockedReq_accesses::total 188297 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 187338 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu0.dcache.StoreCondReq_accesses::total 187338 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu0.dcache.demand_accesses::cpu0.data 14729930 # number of demand (read+write) accesses
|
||||
system.cpu0.dcache.demand_accesses::total 14729930 # number of demand (read+write) accesses
|
||||
system.cpu0.dcache.overall_accesses::cpu0.data 14729930 # number of overall (read+write) accesses
|
||||
system.cpu0.dcache.overall_accesses::total 14729930 # number of overall (read+write) accesses
|
||||
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.187444 # miss rate for ReadReq accesses
|
||||
system.cpu0.dcache.ReadReq_miss_rate::total 0.187444 # miss rate for ReadReq accesses
|
||||
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049753 # miss rate for WriteReq accesses
|
||||
system.cpu0.dcache.WriteReq_miss_rate::total 0.049753 # miss rate for WriteReq accesses
|
||||
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.085817 # miss rate for LoadLockedReq accesses
|
||||
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.085817 # miss rate for LoadLockedReq accesses
|
||||
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.003753 # miss rate for StoreCondReq accesses
|
||||
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.003753 # miss rate for StoreCondReq accesses
|
||||
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.133711 # miss rate for demand accesses
|
||||
system.cpu0.dcache.demand_miss_rate::total 0.133711 # miss rate for demand accesses
|
||||
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.133711 # miss rate for overall accesses
|
||||
system.cpu0.dcache.overall_miss_rate::total 0.133711 # miss rate for overall accesses
|
||||
system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu0.dcache.writebacks::writebacks 771740 # number of writebacks
|
||||
system.cpu0.dcache.writebacks::total 771740 # number of writebacks
|
||||
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu1.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu1.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu1.dtb.fetch_acv 0 # ITB acv
|
||||
system.cpu1.dtb.fetch_accesses 0 # ITB accesses
|
||||
system.cpu1.dtb.read_hits 1163439 # DTB read hits
|
||||
system.cpu1.dtb.read_misses 3277 # DTB read misses
|
||||
system.cpu1.dtb.read_acv 58 # DTB read access violations
|
||||
system.cpu1.dtb.read_accesses 220342 # DTB read accesses
|
||||
system.cpu1.dtb.write_hits 751446 # DTB write hits
|
||||
system.cpu1.dtb.write_misses 415 # DTB write misses
|
||||
system.cpu1.dtb.write_acv 58 # DTB write access violations
|
||||
system.cpu1.dtb.write_accesses 103280 # DTB write accesses
|
||||
system.cpu1.dtb.data_hits 1914885 # DTB hits
|
||||
system.cpu1.dtb.data_misses 3692 # DTB misses
|
||||
system.cpu1.dtb.data_acv 116 # DTB access violations
|
||||
system.cpu1.dtb.data_accesses 323622 # DTB accesses
|
||||
system.cpu1.itb.fetch_hits 1468399 # ITB hits
|
||||
system.cpu1.itb.fetch_misses 1539 # ITB misses
|
||||
system.cpu1.itb.fetch_acv 57 # ITB acv
|
||||
system.cpu1.itb.fetch_accesses 1469938 # ITB accesses
|
||||
system.cpu1.itb.read_hits 0 # DTB read hits
|
||||
system.cpu1.itb.read_misses 0 # DTB read misses
|
||||
system.cpu1.itb.read_acv 0 # DTB read access violations
|
||||
system.cpu1.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu1.itb.write_hits 0 # DTB write hits
|
||||
system.cpu1.itb.write_misses 0 # DTB write misses
|
||||
system.cpu1.itb.write_acv 0 # DTB write access violations
|
||||
system.cpu1.itb.write_accesses 0 # DTB write accesses
|
||||
system.cpu1.itb.data_hits 0 # DTB hits
|
||||
system.cpu1.itb.data_misses 0 # DTB misses
|
||||
system.cpu1.itb.data_acv 0 # DTB access violations
|
||||
system.cpu1.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu1.numCycles 3740248881 # number of cpu cycles simulated
|
||||
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu1.committedInsts 5931958 # Number of instructions committed
|
||||
system.cpu1.committedOps 5931958 # Number of ops (including micro ops) committed
|
||||
system.cpu1.num_int_alu_accesses 5550578 # Number of integer alu accesses
|
||||
system.cpu1.num_fp_alu_accesses 28590 # Number of float alu accesses
|
||||
system.cpu1.num_func_calls 182742 # number of times a function call or return occured
|
||||
system.cpu1.num_conditional_control_insts 577190 # number of instructions that are conditional controls
|
||||
system.cpu1.num_int_insts 5550578 # number of integer instructions
|
||||
system.cpu1.num_fp_insts 28590 # number of float instructions
|
||||
system.cpu1.num_int_register_reads 7657288 # number of times the integer registers were read
|
||||
system.cpu1.num_int_register_writes 4163275 # number of times the integer registers were written
|
||||
system.cpu1.num_fp_register_reads 17889 # number of times the floating registers were read
|
||||
system.cpu1.num_fp_register_writes 17683 # number of times the floating registers were written
|
||||
system.cpu1.num_mem_refs 1926244 # number of memory refs
|
||||
system.cpu1.num_load_insts 1170888 # Number of load instructions
|
||||
system.cpu1.num_store_insts 755356 # Number of store instructions
|
||||
system.cpu1.num_idle_cycles 3734312190.077655 # Number of idle cycles
|
||||
system.cpu1.num_busy_cycles 5936690.922345 # Number of busy cycles
|
||||
system.cpu1.not_idle_fraction 0.001587 # Percentage of non-idle cycles
|
||||
system.cpu1.idle_fraction 0.998413 # Percentage of idle cycles
|
||||
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
|
||||
system.cpu1.kern.inst.quiesce 2204 # number of quiesce instructions executed
|
||||
system.cpu1.kern.inst.hwrei 39554 # number of hwrei instructions executed
|
||||
system.cpu1.kern.ipl_count::0 10328 33.46% 33.46% # number of times we switched to this ipl
|
||||
system.cpu1.kern.ipl_count::22 1907 6.18% 39.64% # number of times we switched to this ipl
|
||||
system.cpu1.kern.ipl_count::30 110 0.36% 40.00% # number of times we switched to this ipl
|
||||
system.cpu1.kern.ipl_count::31 18518 60.00% 100.00% # number of times we switched to this ipl
|
||||
system.cpu1.kern.ipl_count::total 30863 # number of times we switched to this ipl
|
||||
system.cpu1.kern.ipl_good::0 10318 45.77% 45.77% # number of times we switched to this ipl from a different ipl
|
||||
system.cpu1.kern.ipl_good::22 1907 8.46% 54.23% # number of times we switched to this ipl from a different ipl
|
||||
system.cpu1.kern.ipl_good::30 110 0.49% 54.72% # number of times we switched to this ipl from a different ipl
|
||||
system.cpu1.kern.ipl_good::31 10208 45.28% 100.00% # number of times we switched to this ipl from a different ipl
|
||||
system.cpu1.kern.ipl_good::total 22543 # number of times we switched to this ipl from a different ipl
|
||||
system.cpu1.kern.ipl_ticks::0 1859123008500 99.41% 99.41% # number of cycles we spent at this ipl
|
||||
system.cpu1.kern.ipl_ticks::22 82001000 0.00% 99.42% # number of cycles we spent at this ipl
|
||||
system.cpu1.kern.ipl_ticks::30 14064500 0.00% 99.42% # number of cycles we spent at this ipl
|
||||
system.cpu1.kern.ipl_ticks::31 10905353000 0.58% 100.00% # number of cycles we spent at this ipl
|
||||
system.cpu1.kern.ipl_ticks::total 1870124427000 # number of cycles we spent at this ipl
|
||||
system.cpu1.kern.ipl_used::0 0.999032 # fraction of swpipl calls that actually changed the ipl
|
||||
system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
|
||||
system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
|
||||
system.cpu1.kern.ipl_used::31 0.551247 # fraction of swpipl calls that actually changed the ipl
|
||||
system.cpu1.kern.ipl_used::total 0.730422 # fraction of swpipl calls that actually changed the ipl
|
||||
system.cpu1.kern.syscall::2 2 2.00% 2.00% # number of syscalls executed
|
||||
system.cpu1.kern.syscall::3 11 11.00% 13.00% # number of syscalls executed
|
||||
system.cpu1.kern.syscall::4 2 2.00% 15.00% # number of syscalls executed
|
||||
system.cpu1.kern.syscall::6 10 10.00% 25.00% # number of syscalls executed
|
||||
system.cpu1.kern.syscall::17 6 6.00% 31.00% # number of syscalls executed
|
||||
system.cpu1.kern.syscall::19 2 2.00% 33.00% # number of syscalls executed
|
||||
system.cpu1.kern.syscall::23 2 2.00% 35.00% # number of syscalls executed
|
||||
system.cpu1.kern.syscall::24 2 2.00% 37.00% # number of syscalls executed
|
||||
system.cpu1.kern.syscall::33 4 4.00% 41.00% # number of syscalls executed
|
||||
system.cpu1.kern.syscall::45 17 17.00% 58.00% # number of syscalls executed
|
||||
system.cpu1.kern.syscall::47 2 2.00% 60.00% # number of syscalls executed
|
||||
system.cpu1.kern.syscall::48 2 2.00% 62.00% # number of syscalls executed
|
||||
system.cpu1.kern.syscall::59 3 3.00% 65.00% # number of syscalls executed
|
||||
system.cpu1.kern.syscall::71 24 24.00% 89.00% # number of syscalls executed
|
||||
system.cpu1.kern.syscall::74 8 8.00% 97.00% # number of syscalls executed
|
||||
system.cpu1.kern.syscall::90 1 1.00% 98.00% # number of syscalls executed
|
||||
system.cpu1.kern.syscall::132 2 2.00% 100.00% # number of syscalls executed
|
||||
system.cpu1.kern.syscall::total 100 # number of syscalls executed
|
||||
system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
|
||||
system.cpu1.kern.callpal::wripir 8 0.02% 0.03% # number of callpals executed
|
||||
system.cpu1.kern.callpal::wrmces 1 0.00% 0.03% # number of callpals executed
|
||||
system.cpu1.kern.callpal::wrfen 1 0.00% 0.03% # number of callpals executed
|
||||
system.cpu1.kern.callpal::swpctx 470 1.46% 1.50% # number of callpals executed
|
||||
system.cpu1.kern.callpal::tbi 15 0.05% 1.54% # number of callpals executed
|
||||
system.cpu1.kern.callpal::wrent 7 0.02% 1.57% # number of callpals executed
|
||||
system.cpu1.kern.callpal::swpipl 26238 81.66% 83.22% # number of callpals executed
|
||||
system.cpu1.kern.callpal::rdps 2576 8.02% 91.24% # number of callpals executed
|
||||
system.cpu1.kern.callpal::wrkgp 1 0.00% 91.25% # number of callpals executed
|
||||
system.cpu1.kern.callpal::wrusp 4 0.01% 91.26% # number of callpals executed
|
||||
system.cpu1.kern.callpal::rdusp 2 0.01% 91.26% # number of callpals executed
|
||||
system.cpu1.kern.callpal::whami 3 0.01% 91.27% # number of callpals executed
|
||||
system.cpu1.kern.callpal::rti 2607 8.11% 99.39% # number of callpals executed
|
||||
system.cpu1.kern.callpal::callsys 158 0.49% 99.88% # number of callpals executed
|
||||
system.cpu1.kern.callpal::imb 38 0.12% 100.00% # number of callpals executed
|
||||
system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed
|
||||
system.cpu1.kern.callpal::total 32131 # number of callpals executed
|
||||
system.cpu1.kern.mode_switch::kernel 1033 # number of protection mode switches
|
||||
system.cpu1.kern.mode_switch::user 580 # number of protection mode switches
|
||||
system.cpu1.kern.mode_switch::idle 2046 # number of protection mode switches
|
||||
system.cpu1.kern.mode_good::kernel 612
|
||||
system.cpu1.kern.mode_good::user 580
|
||||
system.cpu1.kern.mode_good::idle 32
|
||||
system.cpu1.kern.mode_switch_good::kernel 0.592449 # fraction of useful protection mode switches
|
||||
system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
|
||||
system.cpu1.kern.mode_switch_good::idle 0.015640 # fraction of useful protection mode switches
|
||||
system.cpu1.kern.mode_switch_good::total 0.334518 # fraction of useful protection mode switches
|
||||
system.cpu1.kern.mode_ticks::kernel 1373917500 0.07% 0.07% # number of ticks spent at the given mode
|
||||
system.cpu1.kern.mode_ticks::user 508289000 0.03% 0.10% # number of ticks spent at the given mode
|
||||
system.cpu1.kern.mode_ticks::idle 1868002549000 99.90% 100.00% # number of ticks spent at the given mode
|
||||
system.cpu1.kern.swap_context 471 # number of times the context was actually changed
|
||||
system.cpu1.icache.replacements 103091 # number of replacements
|
||||
system.cpu1.icache.tagsinuse 427.126317 # Cycle average of tags in use
|
||||
system.cpu1.icache.total_refs 5832136 # Total number of references to valid blocks.
|
||||
system.cpu1.icache.sampled_refs 103603 # Sample count of references to valid blocks.
|
||||
system.cpu1.icache.avg_refs 56.293119 # Average number of references to valid blocks.
|
||||
system.cpu1.icache.warmup_cycle 1868933059000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu1.icache.occ_blocks::cpu1.inst 427.126317 # Average occupied blocks per requestor
|
||||
system.cpu1.icache.occ_percent::cpu1.inst 0.834231 # Average percentage of cache occupancy
|
||||
system.cpu1.icache.occ_percent::total 0.834231 # Average percentage of cache occupancy
|
||||
system.cpu1.icache.ReadReq_hits::cpu1.inst 5832136 # number of ReadReq hits
|
||||
system.cpu1.icache.ReadReq_hits::total 5832136 # number of ReadReq hits
|
||||
system.cpu1.icache.demand_hits::cpu1.inst 5832136 # number of demand (read+write) hits
|
||||
system.cpu1.icache.demand_hits::total 5832136 # number of demand (read+write) hits
|
||||
system.cpu1.icache.overall_hits::cpu1.inst 5832136 # number of overall hits
|
||||
system.cpu1.icache.overall_hits::total 5832136 # number of overall hits
|
||||
system.cpu1.icache.ReadReq_misses::cpu1.inst 103630 # number of ReadReq misses
|
||||
system.cpu1.icache.ReadReq_misses::total 103630 # number of ReadReq misses
|
||||
system.cpu1.icache.demand_misses::cpu1.inst 103630 # number of demand (read+write) misses
|
||||
system.cpu1.icache.demand_misses::total 103630 # number of demand (read+write) misses
|
||||
system.cpu1.icache.overall_misses::cpu1.inst 103630 # number of overall misses
|
||||
system.cpu1.icache.overall_misses::total 103630 # number of overall misses
|
||||
system.cpu1.icache.ReadReq_accesses::cpu1.inst 5935766 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu1.icache.ReadReq_accesses::total 5935766 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu1.icache.demand_accesses::cpu1.inst 5935766 # number of demand (read+write) accesses
|
||||
system.cpu1.icache.demand_accesses::total 5935766 # number of demand (read+write) accesses
|
||||
system.cpu1.icache.overall_accesses::cpu1.inst 5935766 # number of overall (read+write) accesses
|
||||
system.cpu1.icache.overall_accesses::total 5935766 # number of overall (read+write) accesses
|
||||
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.017459 # miss rate for ReadReq accesses
|
||||
system.cpu1.icache.ReadReq_miss_rate::total 0.017459 # miss rate for ReadReq accesses
|
||||
system.cpu1.icache.demand_miss_rate::cpu1.inst 0.017459 # miss rate for demand accesses
|
||||
system.cpu1.icache.demand_miss_rate::total 0.017459 # miss rate for demand accesses
|
||||
system.cpu1.icache.overall_miss_rate::cpu1.inst 0.017459 # miss rate for overall accesses
|
||||
system.cpu1.icache.overall_miss_rate::total 0.017459 # miss rate for overall accesses
|
||||
system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu1.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu1.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu1.icache.writebacks::writebacks 15 # number of writebacks
|
||||
system.cpu1.icache.writebacks::total 15 # number of writebacks
|
||||
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu1.dcache.replacements 62338 # number of replacements
|
||||
system.cpu1.dcache.tagsinuse 391.951263 # Cycle average of tags in use
|
||||
system.cpu1.dcache.total_refs 1834544 # Total number of references to valid blocks.
|
||||
system.cpu1.dcache.sampled_refs 62657 # Sample count of references to valid blocks.
|
||||
system.cpu1.dcache.avg_refs 29.279155 # Average number of references to valid blocks.
|
||||
system.cpu1.dcache.warmup_cycle 1851267520500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu1.dcache.occ_blocks::cpu1.data 391.951263 # Average occupied blocks per requestor
|
||||
system.cpu1.dcache.occ_percent::cpu1.data 0.765530 # Average percentage of cache occupancy
|
||||
system.cpu1.dcache.occ_percent::total 0.765530 # Average percentage of cache occupancy
|
||||
system.cpu1.dcache.ReadReq_hits::cpu1.data 1109315 # number of ReadReq hits
|
||||
system.cpu1.dcache.ReadReq_hits::total 1109315 # number of ReadReq hits
|
||||
system.cpu1.dcache.WriteReq_hits::cpu1.data 707444 # number of WriteReq hits
|
||||
system.cpu1.dcache.WriteReq_hits::total 707444 # number of WriteReq hits
|
||||
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 15129 # number of LoadLockedReq hits
|
||||
system.cpu1.dcache.LoadLockedReq_hits::total 15129 # number of LoadLockedReq hits
|
||||
system.cpu1.dcache.StoreCondReq_hits::cpu1.data 15613 # number of StoreCondReq hits
|
||||
system.cpu1.dcache.StoreCondReq_hits::total 15613 # number of StoreCondReq hits
|
||||
system.cpu1.dcache.demand_hits::cpu1.data 1816759 # number of demand (read+write) hits
|
||||
system.cpu1.dcache.demand_hits::total 1816759 # number of demand (read+write) hits
|
||||
system.cpu1.dcache.overall_hits::cpu1.data 1816759 # number of overall hits
|
||||
system.cpu1.dcache.overall_hits::total 1816759 # number of overall hits
|
||||
system.cpu1.dcache.ReadReq_misses::cpu1.data 41650 # number of ReadReq misses
|
||||
system.cpu1.dcache.ReadReq_misses::total 41650 # number of ReadReq misses
|
||||
system.cpu1.dcache.WriteReq_misses::cpu1.data 25861 # number of WriteReq misses
|
||||
system.cpu1.dcache.WriteReq_misses::total 25861 # number of WriteReq misses
|
||||
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 1289 # number of LoadLockedReq misses
|
||||
system.cpu1.dcache.LoadLockedReq_misses::total 1289 # number of LoadLockedReq misses
|
||||
system.cpu1.dcache.StoreCondReq_misses::cpu1.data 732 # number of StoreCondReq misses
|
||||
system.cpu1.dcache.StoreCondReq_misses::total 732 # number of StoreCondReq misses
|
||||
system.cpu1.dcache.demand_misses::cpu1.data 67511 # number of demand (read+write) misses
|
||||
system.cpu1.dcache.demand_misses::total 67511 # number of demand (read+write) misses
|
||||
system.cpu1.dcache.overall_misses::cpu1.data 67511 # number of overall misses
|
||||
system.cpu1.dcache.overall_misses::total 67511 # number of overall misses
|
||||
system.cpu1.dcache.ReadReq_accesses::cpu1.data 1150965 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu1.dcache.ReadReq_accesses::total 1150965 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu1.dcache.WriteReq_accesses::cpu1.data 733305 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu1.dcache.WriteReq_accesses::total 733305 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 16418 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu1.dcache.LoadLockedReq_accesses::total 16418 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 16345 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu1.dcache.StoreCondReq_accesses::total 16345 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu1.dcache.demand_accesses::cpu1.data 1884270 # number of demand (read+write) accesses
|
||||
system.cpu1.dcache.demand_accesses::total 1884270 # number of demand (read+write) accesses
|
||||
system.cpu1.dcache.overall_accesses::cpu1.data 1884270 # number of overall (read+write) accesses
|
||||
system.cpu1.dcache.overall_accesses::total 1884270 # number of overall (read+write) accesses
|
||||
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.036187 # miss rate for ReadReq accesses
|
||||
system.cpu1.dcache.ReadReq_miss_rate::total 0.036187 # miss rate for ReadReq accesses
|
||||
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.035266 # miss rate for WriteReq accesses
|
||||
system.cpu1.dcache.WriteReq_miss_rate::total 0.035266 # miss rate for WriteReq accesses
|
||||
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.078511 # miss rate for LoadLockedReq accesses
|
||||
system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.078511 # miss rate for LoadLockedReq accesses
|
||||
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.044784 # miss rate for StoreCondReq accesses
|
||||
system.cpu1.dcache.StoreCondReq_miss_rate::total 0.044784 # miss rate for StoreCondReq accesses
|
||||
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.035829 # miss rate for demand accesses
|
||||
system.cpu1.dcache.demand_miss_rate::total 0.035829 # miss rate for demand accesses
|
||||
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.035829 # miss rate for overall accesses
|
||||
system.cpu1.dcache.overall_miss_rate::total 0.035829 # miss rate for overall accesses
|
||||
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu1.dcache.writebacks::writebacks 39996 # number of writebacks
|
||||
system.cpu1.dcache.writebacks::total 39996 # number of writebacks
|
||||
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
@ -0,0 +1,112 @@
|
||||
M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
|
||||
|
||||
Got Configuration 623
|
||||
|
||||
memsize 8000000 pages 4000
|
||||
|
||||
First free page after ROM 0xFFFFFC0000018000
|
||||
|
||||
HWRPB 0xFFFFFC0000018000 l1pt 0xFFFFFC0000040000 l2pt 0xFFFFFC0000042000 l3pt_rpb 0xFFFFFC0000044000 l3pt_kernel 0xFFFFFC0000048000 l2reserv 0xFFFFFC0000046000
|
||||
|
||||
kstart = 0xFFFFFC0000310000, kend = 0xFFFFFC0000855898, kentry = 0xFFFFFC0000310000, numCPUs = 0x2
|
||||
|
||||
CPU Clock at 2000 MHz IntrClockFrequency=1024
|
||||
|
||||
Booting with 2 processor(s)
|
||||
|
||||
KSP: 0x20043FE8 PTBR 0x20
|
||||
|
||||
KSP: 0x20043FE8 PTBR 0x20
|
||||
|
||||
Console Callback at 0x0, fixup at 0x0, crb offset: 0x790
|
||||
|
||||
Memory cluster 0 [0 - 392]
|
||||
|
||||
Memory cluster 1 [392 - 15992]
|
||||
|
||||
Initalizing mdt_bitmap addr 0xFFFFFC0000038000 mem_pages 4000
|
||||
|
||||
ConsoleDispatch at virt 100008D8 phys 188D8 val FFFFFC00000100A8
|
||||
|
||||
Bootstraping CPU 1 with sp=0xFFFFFC0000076000
|
||||
|
||||
unix_boot_mem ends at FFFFFC0000078000
|
||||
|
||||
k_argc = 0
|
||||
|
||||
jumping to kernel at 0xFFFFFC0000310000, (PCBB 0xFFFFFC0000018180 pfn 1067)
|
||||
|
||||
CallbackFixup 0 18000, t7=FFFFFC000070C000
|
||||
|
||||
Entering slaveloop for cpu 1 my_rpb=FFFFFC0000018400
|
||||
|
||||
Linux version 2.6.13 (hsul@zed.eecs.umich.edu) (gcc version 3.4.3) #1 SMP Sun Oct 8 19:52:07 EDT 2006
|
||||
|
||||
Booting GENERIC on Tsunami variation DP264 using machine vector DP264 from SRM
|
||||
|
||||
Major Options: SMP LEGACY_START VERBOSE_MCHECK
|
||||
|
||||
Command line: root=/dev/hda1 console=ttyS0
|
||||
|
||||
memcluster 0, usage 1, start 0, end 392
|
||||
|
||||
memcluster 1, usage 0, start 392, end 16384
|
||||
|
||||
freeing pages 1069:16384
|
||||
|
||||
reserving pages 1069:1070
|
||||
|
||||
SMP: 2 CPUs probed -- cpu_present_mask = 3
|
||||
|
||||
Built 1 zonelists
|
||||
|
||||
Kernel command line: root=/dev/hda1 console=ttyS0
|
||||
|
||||
PID hash table entries: 1024 (order: 10, 32768 bytes)
|
||||
|
||||
Using epoch = 1900
|
||||
|
||||
Console: colour dummy device 80x25
|
||||
|
||||
Dentry cache hash table entries: 32768 (order: 5, 262144 bytes)
|
||||
|
||||
Inode-cache hash table entries: 16384 (order: 4, 131072 bytes)
|
||||
|
||||
Memory: 118784k/131072k available (3314k kernel code, 8952k reserved, 983k data, 224k init)
|
||||
|
||||
Mount-cache hash table entries: 512
|
||||
|
||||
SMP starting up secondaries.
|
||||
|
||||
Slave CPU 1 console command START
|
||||
SlaveCmd: restart FFFFFC0000310020 FFFFFC0000310020 vptb FFFFFFFE00000000 my_rpb FFFFFC0000018400 my_rpb_phys 18400
|
||||
|
||||
Brought up 2 CPUs
|
||||
|
||||
SMP: Total of 2 processors activated (8000.15 BogoMIPS).
|
||||
|
||||
NET: Registered protocol family 16
|
||||
|
||||
EISA bus registered
|
||||
|
||||
pci: enabling save/restore of SRM state
|
||||
|
||||
SCSI subsystem initialized
|
||||
|
||||
srm_env: version 0.0.5 loaded successfully
|
||||
|
||||
Installing knfsd (copyright (C) 1996 okir@monad.swb.de).
|
||||
|
||||
Initializing Cryptographic API
|
||||
|
||||
rtc: Standard PC (1900) epoch (1900) detected
|
||||
|
||||
Real Time Clock Driver v1.12
|
||||
|
||||
Serial: 8250/16550 driver $Revision: 1.90 $ 1 ports, IRQ sharing disabled
|
||||
|
||||
ttyS0 at I/O 0x3f8 (irq = 4) is a 8250
|
||||
|
||||
io scheduler noop registered
|
||||
|
||||
io scheduler anticipatory registered
|
||||
@ -0,0 +1,816 @@
|
||||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
full_system=true
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
||||
[system]
|
||||
type=LinuxAlphaSystem
|
||||
children=bridge cpu disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami
|
||||
boot_cpu_frequency=500
|
||||
boot_osflags=root=/dev/hda1 console=ttyS0
|
||||
console=/dist/m5/system/binaries/console
|
||||
init_param=0
|
||||
kernel=/dist/m5/system/binaries/vmlinux
|
||||
load_addr_mask=1099511627775
|
||||
mem_mode=atomic
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
pal=/dist/m5/system/binaries/ts_osfpal
|
||||
readfile=tests/halt.sh
|
||||
symbolfile=
|
||||
system_rev=1024
|
||||
system_type=34
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.membus.slave[0]
|
||||
|
||||
[system.bridge]
|
||||
type=Bridge
|
||||
delay=50000
|
||||
nack_delay=4000
|
||||
ranges=8796093022208:18446744073709551615
|
||||
req_size=16
|
||||
resp_size=16
|
||||
write_ack=false
|
||||
master=system.iobus.slave[0]
|
||||
slave=system.membus.master[0]
|
||||
|
||||
[system.cpu]
|
||||
type=AtomicSimpleCPU
|
||||
children=dcache dtb icache interrupts itb tracer
|
||||
checker=Null
|
||||
clock=500
|
||||
cpu_id=0
|
||||
defer_registration=false
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
fastmem=false
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
interrupts=system.cpu.interrupts
|
||||
itb=system.cpu.itb
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
phase=0
|
||||
profile=0
|
||||
progress_interval=0
|
||||
simulate_data_stalls=false
|
||||
simulate_inst_stalls=false
|
||||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
width=1
|
||||
workload=
|
||||
dcache_port=system.cpu.dcache.cpu_side
|
||||
icache_port=system.cpu.icache.cpu_side
|
||||
|
||||
[system.cpu.dcache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=4
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=32768
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=8
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.dcache_port
|
||||
mem_side=system.toL2Bus.slave[1]
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=AlphaTLB
|
||||
size=64
|
||||
|
||||
[system.cpu.icache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=1
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=32768
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=8
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.icache_port
|
||||
mem_side=system.toL2Bus.slave[0]
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=AlphaInterrupts
|
||||
|
||||
[system.cpu.itb]
|
||||
type=AlphaTLB
|
||||
size=48
|
||||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
|
||||
[system.disk0]
|
||||
type=IdeDisk
|
||||
children=image
|
||||
delay=1000000
|
||||
driveID=master
|
||||
image=system.disk0.image
|
||||
|
||||
[system.disk0.image]
|
||||
type=CowDiskImage
|
||||
children=child
|
||||
child=system.disk0.image.child
|
||||
image_file=
|
||||
read_only=false
|
||||
table_size=65536
|
||||
|
||||
[system.disk0.image.child]
|
||||
type=RawDiskImage
|
||||
image_file=/dist/m5/system/disks/linux-latest.img
|
||||
read_only=true
|
||||
|
||||
[system.disk2]
|
||||
type=IdeDisk
|
||||
children=image
|
||||
delay=1000000
|
||||
driveID=master
|
||||
image=system.disk2.image
|
||||
|
||||
[system.disk2.image]
|
||||
type=CowDiskImage
|
||||
children=child
|
||||
child=system.disk2.image.child
|
||||
image_file=
|
||||
read_only=false
|
||||
table_size=65536
|
||||
|
||||
[system.disk2.image.child]
|
||||
type=RawDiskImage
|
||||
image_file=/dist/m5/system/disks/linux-bigswap2.img
|
||||
read_only=true
|
||||
|
||||
[system.intrctrl]
|
||||
type=IntrControl
|
||||
sys=system
|
||||
|
||||
[system.iobus]
|
||||
type=NoncoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
use_default_range=true
|
||||
width=64
|
||||
default=system.tsunami.pciconfig.pio
|
||||
master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ethernet.pio system.tsunami.ethernet.config system.iocache.cpu_side
|
||||
slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma
|
||||
|
||||
[system.iocache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:8589934591
|
||||
assoc=8
|
||||
block_size=64
|
||||
forward_snoops=false
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=50000
|
||||
max_miss_count=0
|
||||
mshrs=20
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=1024
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=12
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.iobus.master[29]
|
||||
mem_side=system.membus.slave[1]
|
||||
|
||||
[system.l2c]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=8
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=false
|
||||
latency=10000
|
||||
max_miss_count=0
|
||||
mshrs=92
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=4194304
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=16
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.toL2Bus.master[0]
|
||||
mem_side=system.membus.slave[2]
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
children=badaddr_responder
|
||||
block_size=64
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
default=system.membus.badaddr_responder.pio
|
||||
master=system.bridge.slave system.physmem.port[0]
|
||||
slave=system.system_port system.iocache.mem_side system.l2c.mem_side
|
||||
|
||||
[system.membus.badaddr_responder]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=0
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=true
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.membus.default
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.membus.master[1]
|
||||
|
||||
[system.simple_disk]
|
||||
type=SimpleDisk
|
||||
children=disk
|
||||
disk=system.simple_disk.disk
|
||||
system=system
|
||||
|
||||
[system.simple_disk.disk]
|
||||
type=RawDiskImage
|
||||
image_file=/dist/m5/system/disks/linux-latest.img
|
||||
read_only=true
|
||||
|
||||
[system.terminal]
|
||||
type=Terminal
|
||||
intr_control=system.intrctrl
|
||||
number=0
|
||||
output=true
|
||||
port=3456
|
||||
|
||||
[system.toL2Bus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
master=system.l2c.cpu_side
|
||||
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
|
||||
|
||||
[system.tsunami]
|
||||
type=Tsunami
|
||||
children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart
|
||||
intrctrl=system.intrctrl
|
||||
system=system
|
||||
|
||||
[system.tsunami.backdoor]
|
||||
type=AlphaBackdoor
|
||||
cpu=system.cpu
|
||||
disk=system.simple_disk
|
||||
pio_addr=8804682956800
|
||||
pio_latency=1000
|
||||
platform=system.tsunami
|
||||
system=system
|
||||
terminal=system.terminal
|
||||
pio=system.iobus.master[24]
|
||||
|
||||
[system.tsunami.cchip]
|
||||
type=TsunamiCChip
|
||||
pio_addr=8803072344064
|
||||
pio_latency=1000
|
||||
system=system
|
||||
tsunami=system.tsunami
|
||||
pio=system.iobus.master[0]
|
||||
|
||||
[system.tsunami.ethernet]
|
||||
type=NSGigE
|
||||
BAR0=1
|
||||
BAR0LegacyIO=false
|
||||
BAR0Size=256
|
||||
BAR1=0
|
||||
BAR1LegacyIO=false
|
||||
BAR1Size=4096
|
||||
BAR2=0
|
||||
BAR2LegacyIO=false
|
||||
BAR2Size=0
|
||||
BAR3=0
|
||||
BAR3LegacyIO=false
|
||||
BAR3Size=0
|
||||
BAR4=0
|
||||
BAR4LegacyIO=false
|
||||
BAR4Size=0
|
||||
BAR5=0
|
||||
BAR5LegacyIO=false
|
||||
BAR5Size=0
|
||||
BIST=0
|
||||
CacheLineSize=0
|
||||
CardbusCIS=0
|
||||
ClassCode=2
|
||||
Command=0
|
||||
DeviceID=34
|
||||
ExpansionROM=0
|
||||
HeaderType=0
|
||||
InterruptLine=30
|
||||
InterruptPin=1
|
||||
LatencyTimer=0
|
||||
MaximumLatency=52
|
||||
MinimumGrant=176
|
||||
ProgIF=0
|
||||
Revision=0
|
||||
Status=656
|
||||
SubClassCode=0
|
||||
SubsystemID=0
|
||||
SubsystemVendorID=0
|
||||
VendorID=4107
|
||||
clock=0
|
||||
config_latency=20000
|
||||
dma_data_free=false
|
||||
dma_desc_free=false
|
||||
dma_no_allocate=true
|
||||
dma_read_delay=0
|
||||
dma_read_factor=0
|
||||
dma_write_delay=0
|
||||
dma_write_factor=0
|
||||
hardware_address=00:90:00:00:00:01
|
||||
intr_delay=10000000
|
||||
max_backoff_delay=10000000
|
||||
min_backoff_delay=4000
|
||||
pci_bus=0
|
||||
pci_dev=1
|
||||
pci_func=0
|
||||
pio_latency=1000
|
||||
platform=system.tsunami
|
||||
rss=false
|
||||
rx_delay=1000000
|
||||
rx_fifo_size=524288
|
||||
rx_filter=true
|
||||
rx_thread=false
|
||||
system=system
|
||||
tx_delay=1000000
|
||||
tx_fifo_size=524288
|
||||
tx_thread=false
|
||||
config=system.iobus.master[28]
|
||||
dma=system.iobus.slave[2]
|
||||
pio=system.iobus.master[27]
|
||||
|
||||
[system.tsunami.fake_OROM]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8796093677568
|
||||
pio_latency=1000
|
||||
pio_size=393216
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[8]
|
||||
|
||||
[system.tsunami.fake_ata0]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615848432
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[19]
|
||||
|
||||
[system.tsunami.fake_ata1]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615848304
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[20]
|
||||
|
||||
[system.tsunami.fake_pnp_addr]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615848569
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[9]
|
||||
|
||||
[system.tsunami.fake_pnp_read0]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615848451
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[11]
|
||||
|
||||
[system.tsunami.fake_pnp_read1]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615848515
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[12]
|
||||
|
||||
[system.tsunami.fake_pnp_read2]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615848579
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[13]
|
||||
|
||||
[system.tsunami.fake_pnp_read3]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615848643
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[14]
|
||||
|
||||
[system.tsunami.fake_pnp_read4]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615848707
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[15]
|
||||
|
||||
[system.tsunami.fake_pnp_read5]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615848771
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[16]
|
||||
|
||||
[system.tsunami.fake_pnp_read6]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615848835
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[17]
|
||||
|
||||
[system.tsunami.fake_pnp_read7]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615848899
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[18]
|
||||
|
||||
[system.tsunami.fake_pnp_write]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615850617
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[10]
|
||||
|
||||
[system.tsunami.fake_ppc]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615848891
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[7]
|
||||
|
||||
[system.tsunami.fake_sm_chip]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615848816
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[2]
|
||||
|
||||
[system.tsunami.fake_uart1]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615848696
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[3]
|
||||
|
||||
[system.tsunami.fake_uart2]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615848936
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[4]
|
||||
|
||||
[system.tsunami.fake_uart3]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615848680
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[5]
|
||||
|
||||
[system.tsunami.fake_uart4]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615848944
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[6]
|
||||
|
||||
[system.tsunami.fb]
|
||||
type=BadDevice
|
||||
devicename=FrameBuffer
|
||||
pio_addr=8804615848912
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.iobus.master[21]
|
||||
|
||||
[system.tsunami.ide]
|
||||
type=IdeController
|
||||
BAR0=1
|
||||
BAR0LegacyIO=false
|
||||
BAR0Size=8
|
||||
BAR1=1
|
||||
BAR1LegacyIO=false
|
||||
BAR1Size=4
|
||||
BAR2=1
|
||||
BAR2LegacyIO=false
|
||||
BAR2Size=8
|
||||
BAR3=1
|
||||
BAR3LegacyIO=false
|
||||
BAR3Size=4
|
||||
BAR4=1
|
||||
BAR4LegacyIO=false
|
||||
BAR4Size=16
|
||||
BAR5=1
|
||||
BAR5LegacyIO=false
|
||||
BAR5Size=0
|
||||
BIST=0
|
||||
CacheLineSize=0
|
||||
CardbusCIS=0
|
||||
ClassCode=1
|
||||
Command=0
|
||||
DeviceID=28945
|
||||
ExpansionROM=0
|
||||
HeaderType=0
|
||||
InterruptLine=31
|
||||
InterruptPin=1
|
||||
LatencyTimer=0
|
||||
MaximumLatency=0
|
||||
MinimumGrant=0
|
||||
ProgIF=133
|
||||
Revision=0
|
||||
Status=640
|
||||
SubClassCode=1
|
||||
SubsystemID=0
|
||||
SubsystemVendorID=0
|
||||
VendorID=32902
|
||||
config_latency=20000
|
||||
ctrl_offset=0
|
||||
disks=system.disk0 system.disk2
|
||||
io_shift=0
|
||||
max_backoff_delay=10000000
|
||||
min_backoff_delay=4000
|
||||
pci_bus=0
|
||||
pci_dev=0
|
||||
pci_func=0
|
||||
pio_latency=1000
|
||||
platform=system.tsunami
|
||||
system=system
|
||||
config=system.iobus.master[26]
|
||||
dma=system.iobus.slave[1]
|
||||
pio=system.iobus.master[25]
|
||||
|
||||
[system.tsunami.io]
|
||||
type=TsunamiIO
|
||||
frequency=976562500
|
||||
pio_addr=8804615847936
|
||||
pio_latency=1000
|
||||
system=system
|
||||
time=Thu Jan 1 00:00:00 2009
|
||||
tsunami=system.tsunami
|
||||
year_is_bcd=false
|
||||
pio=system.iobus.master[22]
|
||||
|
||||
[system.tsunami.pchip]
|
||||
type=TsunamiPChip
|
||||
pio_addr=8802535473152
|
||||
pio_latency=1000
|
||||
system=system
|
||||
tsunami=system.tsunami
|
||||
pio=system.iobus.master[1]
|
||||
|
||||
[system.tsunami.pciconfig]
|
||||
type=PciConfigAll
|
||||
bus=0
|
||||
pio_latency=1
|
||||
platform=system.tsunami
|
||||
size=16777216
|
||||
system=system
|
||||
pio=system.iobus.default
|
||||
|
||||
[system.tsunami.uart]
|
||||
type=Uart8250
|
||||
pio_addr=8804615848952
|
||||
pio_latency=1000
|
||||
platform=system.tsunami
|
||||
system=system
|
||||
terminal=system.terminal
|
||||
pio=system.iobus.master[23]
|
||||
|
||||
@ -0,0 +1,5 @@
|
||||
warn: Sockets disabled, not accepting terminal connections
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: Prefetch instructions in Alpha do not do anything
|
||||
warn: Prefetch instructions in Alpha do not do anything
|
||||
hack: be nice to actually delete the event here
|
||||
@ -0,0 +1,12 @@
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jun 4 2012 11:50:11
|
||||
gem5 started Jun 4 2012 14:07:23
|
||||
gem5 executing on zizzer
|
||||
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic -re tests/run.py build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: kernel located at: /dist/m5/system/binaries/vmlinux
|
||||
0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 1829332258000 because m5_exit instruction encountered
|
||||
@ -0,0 +1,456 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 1.829332 # Number of seconds simulated
|
||||
sim_ticks 1829332258000 # Number of ticks simulated
|
||||
final_tick 1829332258000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 2878195 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2878193 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 87696777763 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 296144 # Number of bytes of host memory used
|
||||
host_seconds 20.86 # Real time elapsed on the host
|
||||
sim_insts 60038305 # Number of instructions simulated
|
||||
sim_ops 60038305 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 955904 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 68042304 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::tsunami.ide 2652608 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 71650816 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 955904 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 955904 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 10156864 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 10156864 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 14936 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 1063161 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::tsunami.ide 41447 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 1119544 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 158701 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 158701 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 522543 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 37195159 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::tsunami.ide 1450042 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 39167743 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 522543 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 522543 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 5552225 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 5552225 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 5552225 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 522543 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 37195159 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::tsunami.ide 1450042 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 44719968 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.l2c.replacements 1045877 # number of replacements
|
||||
system.l2c.tagsinuse 33807.015903 # Cycle average of tags in use
|
||||
system.l2c.total_refs 2291835 # Total number of references to valid blocks.
|
||||
system.l2c.sampled_refs 1077848 # Sample count of references to valid blocks.
|
||||
system.l2c.avg_refs 2.126306 # Average number of references to valid blocks.
|
||||
system.l2c.warmup_cycle 765422500 # Cycle when the warmup percentage was hit.
|
||||
system.l2c.occ_blocks::writebacks 23613.410409 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu.inst 3680.391656 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu.data 6513.213838 # Average occupied blocks per requestor
|
||||
system.l2c.occ_percent::writebacks 0.360312 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu.inst 0.056158 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu.data 0.099384 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::total 0.515854 # Average percentage of cache occupancy
|
||||
system.l2c.ReadReq_hits::cpu.inst 905267 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu.data 794128 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::total 1699395 # number of ReadReq hits
|
||||
system.l2c.Writeback_hits::writebacks 825291 # number of Writeback hits
|
||||
system.l2c.Writeback_hits::total 825291 # number of Writeback hits
|
||||
system.l2c.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits
|
||||
system.l2c.UpgradeReq_hits::total 1 # number of UpgradeReq hits
|
||||
system.l2c.ReadExReq_hits::cpu.data 185383 # number of ReadExReq hits
|
||||
system.l2c.ReadExReq_hits::total 185383 # number of ReadExReq hits
|
||||
system.l2c.demand_hits::cpu.inst 905267 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu.data 979511 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::total 1884778 # number of demand (read+write) hits
|
||||
system.l2c.overall_hits::cpu.inst 905267 # number of overall hits
|
||||
system.l2c.overall_hits::cpu.data 979511 # number of overall hits
|
||||
system.l2c.overall_hits::total 1884778 # number of overall hits
|
||||
system.l2c.ReadReq_misses::cpu.inst 14936 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu.data 944693 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::total 959629 # number of ReadReq misses
|
||||
system.l2c.UpgradeReq_misses::cpu.data 12 # number of UpgradeReq misses
|
||||
system.l2c.UpgradeReq_misses::total 12 # number of UpgradeReq misses
|
||||
system.l2c.ReadExReq_misses::cpu.data 118859 # number of ReadExReq misses
|
||||
system.l2c.ReadExReq_misses::total 118859 # number of ReadExReq misses
|
||||
system.l2c.demand_misses::cpu.inst 14936 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu.data 1063552 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::total 1078488 # number of demand (read+write) misses
|
||||
system.l2c.overall_misses::cpu.inst 14936 # number of overall misses
|
||||
system.l2c.overall_misses::cpu.data 1063552 # number of overall misses
|
||||
system.l2c.overall_misses::total 1078488 # number of overall misses
|
||||
system.l2c.ReadReq_accesses::cpu.inst 920203 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::cpu.data 1738821 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::total 2659024 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.Writeback_accesses::writebacks 825291 # number of Writeback accesses(hits+misses)
|
||||
system.l2c.Writeback_accesses::total 825291 # number of Writeback accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_accesses::cpu.data 13 # number of UpgradeReq accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_accesses::total 13 # number of UpgradeReq accesses(hits+misses)
|
||||
system.l2c.ReadExReq_accesses::cpu.data 304242 # number of ReadExReq accesses(hits+misses)
|
||||
system.l2c.ReadExReq_accesses::total 304242 # number of ReadExReq accesses(hits+misses)
|
||||
system.l2c.demand_accesses::cpu.inst 920203 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu.data 2043063 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::total 2963266 # number of demand (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu.inst 920203 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu.data 2043063 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::total 2963266 # number of overall (read+write) accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu.inst 0.016231 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu.data 0.543295 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::total 0.360895 # miss rate for ReadReq accesses
|
||||
system.l2c.UpgradeReq_miss_rate::cpu.data 0.923077 # miss rate for UpgradeReq accesses
|
||||
system.l2c.UpgradeReq_miss_rate::total 0.923077 # miss rate for UpgradeReq accesses
|
||||
system.l2c.ReadExReq_miss_rate::cpu.data 0.390673 # miss rate for ReadExReq accesses
|
||||
system.l2c.ReadExReq_miss_rate::total 0.390673 # miss rate for ReadExReq accesses
|
||||
system.l2c.demand_miss_rate::cpu.inst 0.016231 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu.data 0.520567 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::total 0.363952 # miss rate for demand accesses
|
||||
system.l2c.overall_miss_rate::cpu.inst 0.016231 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu.data 0.520567 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::total 0.363952 # miss rate for overall accesses
|
||||
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.l2c.fast_writes 0 # number of fast writes performed
|
||||
system.l2c.cache_copies 0 # number of cache copies performed
|
||||
system.l2c.writebacks::writebacks 117189 # number of writebacks
|
||||
system.l2c.writebacks::total 117189 # number of writebacks
|
||||
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.iocache.replacements 41686 # number of replacements
|
||||
system.iocache.tagsinuse 1.225570 # Cycle average of tags in use
|
||||
system.iocache.total_refs 0 # Total number of references to valid blocks.
|
||||
system.iocache.sampled_refs 41702 # Sample count of references to valid blocks.
|
||||
system.iocache.avg_refs 0 # Average number of references to valid blocks.
|
||||
system.iocache.warmup_cycle 1685780659017 # Cycle when the warmup percentage was hit.
|
||||
system.iocache.occ_blocks::tsunami.ide 1.225570 # Average occupied blocks per requestor
|
||||
system.iocache.occ_percent::tsunami.ide 0.076598 # Average percentage of cache occupancy
|
||||
system.iocache.occ_percent::total 0.076598 # Average percentage of cache occupancy
|
||||
system.iocache.ReadReq_misses::tsunami.ide 174 # number of ReadReq misses
|
||||
system.iocache.ReadReq_misses::total 174 # number of ReadReq misses
|
||||
system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses
|
||||
system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses
|
||||
system.iocache.demand_misses::tsunami.ide 41726 # number of demand (read+write) misses
|
||||
system.iocache.demand_misses::total 41726 # number of demand (read+write) misses
|
||||
system.iocache.overall_misses::tsunami.ide 41726 # number of overall misses
|
||||
system.iocache.overall_misses::total 41726 # number of overall misses
|
||||
system.iocache.ReadReq_accesses::tsunami.ide 174 # number of ReadReq accesses(hits+misses)
|
||||
system.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses)
|
||||
system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses)
|
||||
system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses)
|
||||
system.iocache.demand_accesses::tsunami.ide 41726 # number of demand (read+write) accesses
|
||||
system.iocache.demand_accesses::total 41726 # number of demand (read+write) accesses
|
||||
system.iocache.overall_accesses::tsunami.ide 41726 # number of overall (read+write) accesses
|
||||
system.iocache.overall_accesses::total 41726 # number of overall (read+write) accesses
|
||||
system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
|
||||
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
|
||||
system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses
|
||||
system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
|
||||
system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses
|
||||
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
|
||||
system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
|
||||
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
|
||||
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.iocache.fast_writes 0 # number of fast writes performed
|
||||
system.iocache.cache_copies 0 # number of cache copies performed
|
||||
system.iocache.writebacks::writebacks 41512 # number of writebacks
|
||||
system.iocache.writebacks::total 41512 # number of writebacks
|
||||
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
||||
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
|
||||
system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
|
||||
system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
|
||||
system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
|
||||
system.disk0.dma_write_txs 395 # Number of DMA write transactions.
|
||||
system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
||||
system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
|
||||
system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
|
||||
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
|
||||
system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
|
||||
system.disk2.dma_write_txs 1 # Number of DMA write transactions.
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
||||
system.cpu.dtb.read_hits 9710427 # DTB read hits
|
||||
system.cpu.dtb.read_misses 10329 # DTB read misses
|
||||
system.cpu.dtb.read_acv 210 # DTB read access violations
|
||||
system.cpu.dtb.read_accesses 728856 # DTB read accesses
|
||||
system.cpu.dtb.write_hits 6352498 # DTB write hits
|
||||
system.cpu.dtb.write_misses 1142 # DTB write misses
|
||||
system.cpu.dtb.write_acv 157 # DTB write access violations
|
||||
system.cpu.dtb.write_accesses 291931 # DTB write accesses
|
||||
system.cpu.dtb.data_hits 16062925 # DTB hits
|
||||
system.cpu.dtb.data_misses 11471 # DTB misses
|
||||
system.cpu.dtb.data_acv 367 # DTB access violations
|
||||
system.cpu.dtb.data_accesses 1020787 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 4974648 # ITB hits
|
||||
system.cpu.itb.fetch_misses 5006 # ITB misses
|
||||
system.cpu.itb.fetch_acv 184 # ITB acv
|
||||
system.cpu.itb.fetch_accesses 4979654 # ITB accesses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.itb.write_hits 0 # DTB write hits
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.itb.write_acv 0 # DTB write access violations
|
||||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.itb.data_hits 0 # DTB hits
|
||||
system.cpu.itb.data_misses 0 # DTB misses
|
||||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.numCycles 3658664408 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 60038305 # Number of instructions committed
|
||||
system.cpu.committedOps 60038305 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 55913521 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 324460 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 1484182 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 7110746 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 55913521 # number of integer instructions
|
||||
system.cpu.num_fp_insts 324460 # number of float instructions
|
||||
system.cpu.num_int_register_reads 76953934 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 41740225 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 163642 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 166520 # number of times the floating registers were written
|
||||
system.cpu.num_mem_refs 16115709 # number of memory refs
|
||||
system.cpu.num_load_insts 9747513 # Number of load instructions
|
||||
system.cpu.num_store_insts 6368196 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 3598608979.180807 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 60055428.819193 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 0.016415 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0.983585 # Percentage of idle cycles
|
||||
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
||||
system.cpu.kern.inst.quiesce 6357 # number of quiesce instructions executed
|
||||
system.cpu.kern.inst.hwrei 211319 # number of hwrei instructions executed
|
||||
system.cpu.kern.ipl_count::0 74830 40.99% 40.99% # number of times we switched to this ipl
|
||||
system.cpu.kern.ipl_count::21 243 0.13% 41.12% # number of times we switched to this ipl
|
||||
system.cpu.kern.ipl_count::22 1866 1.02% 42.14% # number of times we switched to this ipl
|
||||
system.cpu.kern.ipl_count::31 105623 57.86% 100.00% # number of times we switched to this ipl
|
||||
system.cpu.kern.ipl_count::total 182562 # number of times we switched to this ipl
|
||||
system.cpu.kern.ipl_good::0 73463 49.29% 49.29% # number of times we switched to this ipl from a different ipl
|
||||
system.cpu.kern.ipl_good::21 243 0.16% 49.46% # number of times we switched to this ipl from a different ipl
|
||||
system.cpu.kern.ipl_good::22 1866 1.25% 50.71% # number of times we switched to this ipl from a different ipl
|
||||
system.cpu.kern.ipl_good::31 73463 49.29% 100.00% # number of times we switched to this ipl from a different ipl
|
||||
system.cpu.kern.ipl_good::total 149035 # number of times we switched to this ipl from a different ipl
|
||||
system.cpu.kern.ipl_ticks::0 1811927407500 99.05% 99.05% # number of cycles we spent at this ipl
|
||||
system.cpu.kern.ipl_ticks::21 20110000 0.00% 99.05% # number of cycles we spent at this ipl
|
||||
system.cpu.kern.ipl_ticks::22 80238000 0.00% 99.05% # number of cycles we spent at this ipl
|
||||
system.cpu.kern.ipl_ticks::31 17304295000 0.95% 100.00% # number of cycles we spent at this ipl
|
||||
system.cpu.kern.ipl_ticks::total 1829332050500 # number of cycles we spent at this ipl
|
||||
system.cpu.kern.ipl_used::0 0.981732 # fraction of swpipl calls that actually changed the ipl
|
||||
system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
|
||||
system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
|
||||
system.cpu.kern.ipl_used::31 0.695521 # fraction of swpipl calls that actually changed the ipl
|
||||
system.cpu.kern.ipl_used::total 0.816353 # fraction of swpipl calls that actually changed the ipl
|
||||
system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed
|
||||
system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed
|
||||
system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed
|
||||
system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed
|
||||
system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed
|
||||
system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed
|
||||
system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed
|
||||
system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed
|
||||
system.cpu.kern.syscall::20 6 1.84% 35.89% # number of syscalls executed
|
||||
system.cpu.kern.syscall::23 4 1.23% 37.12% # number of syscalls executed
|
||||
system.cpu.kern.syscall::24 6 1.84% 38.96% # number of syscalls executed
|
||||
system.cpu.kern.syscall::33 11 3.37% 42.33% # number of syscalls executed
|
||||
system.cpu.kern.syscall::41 2 0.61% 42.94% # number of syscalls executed
|
||||
system.cpu.kern.syscall::45 54 16.56% 59.51% # number of syscalls executed
|
||||
system.cpu.kern.syscall::47 6 1.84% 61.35% # number of syscalls executed
|
||||
system.cpu.kern.syscall::48 10 3.07% 64.42% # number of syscalls executed
|
||||
system.cpu.kern.syscall::54 10 3.07% 67.48% # number of syscalls executed
|
||||
system.cpu.kern.syscall::58 1 0.31% 67.79% # number of syscalls executed
|
||||
system.cpu.kern.syscall::59 7 2.15% 69.94% # number of syscalls executed
|
||||
system.cpu.kern.syscall::71 54 16.56% 86.50% # number of syscalls executed
|
||||
system.cpu.kern.syscall::73 3 0.92% 87.42% # number of syscalls executed
|
||||
system.cpu.kern.syscall::74 16 4.91% 92.33% # number of syscalls executed
|
||||
system.cpu.kern.syscall::87 1 0.31% 92.64% # number of syscalls executed
|
||||
system.cpu.kern.syscall::90 3 0.92% 93.56% # number of syscalls executed
|
||||
system.cpu.kern.syscall::92 9 2.76% 96.32% # number of syscalls executed
|
||||
system.cpu.kern.syscall::97 2 0.61% 96.93% # number of syscalls executed
|
||||
system.cpu.kern.syscall::98 2 0.61% 97.55% # number of syscalls executed
|
||||
system.cpu.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed
|
||||
system.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed
|
||||
system.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed
|
||||
system.cpu.kern.syscall::total 326 # number of syscalls executed
|
||||
system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
|
||||
system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed
|
||||
system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed
|
||||
system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed
|
||||
system.cpu.kern.callpal::swpctx 4177 2.17% 2.18% # number of callpals executed
|
||||
system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed
|
||||
system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed
|
||||
system.cpu.kern.callpal::swpipl 175249 91.19% 93.40% # number of callpals executed
|
||||
system.cpu.kern.callpal::rdps 6771 3.52% 96.92% # number of callpals executed
|
||||
system.cpu.kern.callpal::wrkgp 1 0.00% 96.92% # number of callpals executed
|
||||
system.cpu.kern.callpal::wrusp 7 0.00% 96.92% # number of callpals executed
|
||||
system.cpu.kern.callpal::rdusp 9 0.00% 96.93% # number of callpals executed
|
||||
system.cpu.kern.callpal::whami 2 0.00% 96.93% # number of callpals executed
|
||||
system.cpu.kern.callpal::rti 5203 2.71% 99.64% # number of callpals executed
|
||||
system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed
|
||||
system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed
|
||||
system.cpu.kern.callpal::total 192180 # number of callpals executed
|
||||
system.cpu.kern.mode_switch::kernel 5949 # number of protection mode switches
|
||||
system.cpu.kern.mode_switch::user 1738 # number of protection mode switches
|
||||
system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches
|
||||
system.cpu.kern.mode_good::kernel 1909
|
||||
system.cpu.kern.mode_good::user 1738
|
||||
system.cpu.kern.mode_good::idle 171
|
||||
system.cpu.kern.mode_switch_good::kernel 0.320894 # fraction of useful protection mode switches
|
||||
system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
|
||||
system.cpu.kern.mode_switch_good::idle 0.081545 # fraction of useful protection mode switches
|
||||
system.cpu.kern.mode_switch_good::total 0.390229 # fraction of useful protection mode switches
|
||||
system.cpu.kern.mode_ticks::kernel 26834202500 1.47% 1.47% # number of ticks spent at the given mode
|
||||
system.cpu.kern.mode_ticks::user 1465074000 0.08% 1.55% # number of ticks spent at the given mode
|
||||
system.cpu.kern.mode_ticks::idle 1801032773000 98.45% 100.00% # number of ticks spent at the given mode
|
||||
system.cpu.kern.swap_context 4178 # number of times the context was actually changed
|
||||
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
|
||||
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
|
||||
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
|
||||
system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
|
||||
system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
|
||||
system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
|
||||
system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
|
||||
system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
|
||||
system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
|
||||
system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
|
||||
system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
|
||||
system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
|
||||
system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
|
||||
system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
|
||||
system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
|
||||
system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
|
||||
system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
|
||||
system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
|
||||
system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
|
||||
system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
|
||||
system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
|
||||
system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
|
||||
system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
|
||||
system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
|
||||
system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
|
||||
system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
|
||||
system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
|
||||
system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
|
||||
system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
|
||||
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
|
||||
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
|
||||
system.cpu.icache.replacements 919594 # number of replacements
|
||||
system.cpu.icache.tagsinuse 511.215243 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 59129922 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 920106 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 64.264250 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 9686972500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 511.215243 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.998467 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.998467 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 59129922 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 59129922 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 59129922 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 59129922 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 59129922 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 59129922 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 920221 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 920221 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 920221 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 920221 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 920221 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 920221 # number of overall misses
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 60050143 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 60050143 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 60050143 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 60050143 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 60050143 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 60050143 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015324 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.015324 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.015324 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.015324 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.015324 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.015324 # miss rate for overall accesses
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks::writebacks 108 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 108 # number of writebacks
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 2042700 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 511.997802 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 14038433 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 2043212 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 6.870767 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 511.997802 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.999996 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 7807782 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 7807782 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 5848212 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 5848212 # number of WriteReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::cpu.data 183141 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::total 183141 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::cpu.data 199282 # number of StoreCondReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::total 199282 # number of StoreCondReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 13655994 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 13655994 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 13655994 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 13655994 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 1721705 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 1721705 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 304362 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 304362 # number of WriteReq misses
|
||||
system.cpu.dcache.LoadLockedReq_misses::cpu.data 17162 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.LoadLockedReq_misses::total 17162 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 2026067 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 2026067 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 2026067 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 2026067 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 9529487 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 9529487 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 6152574 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 6152574 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200303 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::total 200303 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::cpu.data 199282 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::total 199282 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 15682061 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 15682061 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 15682061 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 15682061 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.180671 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.180671 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049469 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.049469 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085680 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.085680 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.129196 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.129196 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.129196 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.129196 # miss rate for overall accesses
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 825183 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 825183 # number of writebacks
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
@ -0,0 +1,107 @@
|
||||
M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
|
||||
|
||||
Got Configuration 623
|
||||
|
||||
memsize 8000000 pages 4000
|
||||
|
||||
First free page after ROM 0xFFFFFC0000018000
|
||||
|
||||
HWRPB 0xFFFFFC0000018000 l1pt 0xFFFFFC0000040000 l2pt 0xFFFFFC0000042000 l3pt_rpb 0xFFFFFC0000044000 l3pt_kernel 0xFFFFFC0000048000 l2reserv 0xFFFFFC0000046000
|
||||
|
||||
kstart = 0xFFFFFC0000310000, kend = 0xFFFFFC0000855898, kentry = 0xFFFFFC0000310000, numCPUs = 0x1
|
||||
|
||||
CPU Clock at 2000 MHz IntrClockFrequency=1024
|
||||
|
||||
Booting with 1 processor(s)
|
||||
|
||||
KSP: 0x20043FE8 PTBR 0x20
|
||||
|
||||
Console Callback at 0x0, fixup at 0x0, crb offset: 0x510
|
||||
|
||||
Memory cluster 0 [0 - 392]
|
||||
|
||||
Memory cluster 1 [392 - 15992]
|
||||
|
||||
Initalizing mdt_bitmap addr 0xFFFFFC0000038000 mem_pages 4000
|
||||
|
||||
ConsoleDispatch at virt 10000658 phys 18658 val FFFFFC00000100A8
|
||||
|
||||
unix_boot_mem ends at FFFFFC0000076000
|
||||
|
||||
k_argc = 0
|
||||
|
||||
jumping to kernel at 0xFFFFFC0000310000, (PCBB 0xFFFFFC0000018180 pfn 1067)
|
||||
|
||||
CallbackFixup 0 18000, t7=FFFFFC000070C000
|
||||
|
||||
Linux version 2.6.13 (hsul@zed.eecs.umich.edu) (gcc version 3.4.3) #1 SMP Sun Oct 8 19:52:07 EDT 2006
|
||||
|
||||
Booting GENERIC on Tsunami variation DP264 using machine vector DP264 from SRM
|
||||
|
||||
Major Options: SMP LEGACY_START VERBOSE_MCHECK
|
||||
|
||||
Command line: root=/dev/hda1 console=ttyS0
|
||||
|
||||
memcluster 0, usage 1, start 0, end 392
|
||||
|
||||
memcluster 1, usage 0, start 392, end 16384
|
||||
|
||||
freeing pages 1069:16384
|
||||
|
||||
reserving pages 1069:1070
|
||||
|
||||
SMP: 1 CPUs probed -- cpu_present_mask = 1
|
||||
|
||||
Built 1 zonelists
|
||||
|
||||
Kernel command line: root=/dev/hda1 console=ttyS0
|
||||
|
||||
PID hash table entries: 1024 (order: 10, 32768 bytes)
|
||||
|
||||
Using epoch = 1900
|
||||
|
||||
Console: colour dummy device 80x25
|
||||
|
||||
Dentry cache hash table entries: 32768 (order: 5, 262144 bytes)
|
||||
|
||||
Inode-cache hash table entries: 16384 (order: 4, 131072 bytes)
|
||||
|
||||
Memory: 118784k/131072k available (3314k kernel code, 8952k reserved, 983k data, 224k init)
|
||||
|
||||
Mount-cache hash table entries: 512
|
||||
|
||||
SMP mode deactivated.
|
||||
|
||||
Brought up 1 CPUs
|
||||
|
||||
SMP: Total of 1 processors activated (4002.20 BogoMIPS).
|
||||
|
||||
NET: Registered protocol family 16
|
||||
|
||||
EISA bus registered
|
||||
|
||||
pci: enabling save/restore of SRM state
|
||||
|
||||
SCSI subsystem initialized
|
||||
|
||||
srm_env: version 0.0.5 loaded successfully
|
||||
|
||||
Installing knfsd (copyright (C) 1996 okir@monad.swb.de).
|
||||
|
||||
Initializing Cryptographic API
|
||||
|
||||
rtc: Standard PC (1900) epoch (1900) detected
|
||||
|
||||
Real Time Clock Driver v1.12
|
||||
|
||||
Serial: 8250/16550 driver $Revision: 1.90 $ 1 ports, IRQ sharing disabled
|
||||
|
||||
ttyS0 at I/O 0x3f8 (irq = 4) is a 8250
|
||||
|
||||
io scheduler noop registered
|
||||
|
||||
io scheduler anticipatory registered
|
||||
|
||||
io scheduler deadline registered
|
||||
|
||||
io scheduler cfq registered
|
||||
@ -0,0 +1,905 @@
|
||||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
full_system=true
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
||||
[system]
|
||||
type=LinuxAlphaSystem
|
||||
children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami
|
||||
boot_cpu_frequency=500
|
||||
boot_osflags=root=/dev/hda1 console=ttyS0
|
||||
console=/dist/m5/system/binaries/console
|
||||
init_param=0
|
||||
kernel=/dist/m5/system/binaries/vmlinux
|
||||
load_addr_mask=1099511627775
|
||||
mem_mode=timing
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
pal=/dist/m5/system/binaries/ts_osfpal
|
||||
readfile=tests/halt.sh
|
||||
symbolfile=
|
||||
system_rev=1024
|
||||
system_type=34
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.membus.slave[0]
|
||||
|
||||
[system.bridge]
|
||||
type=Bridge
|
||||
delay=50000
|
||||
nack_delay=4000
|
||||
ranges=8796093022208:18446744073709551615
|
||||
req_size=16
|
||||
resp_size=16
|
||||
write_ack=false
|
||||
master=system.iobus.slave[0]
|
||||
slave=system.membus.master[0]
|
||||
|
||||
[system.cpu0]
|
||||
type=TimingSimpleCPU
|
||||
children=dcache dtb icache interrupts itb tracer
|
||||
checker=Null
|
||||
clock=500
|
||||
cpu_id=0
|
||||
defer_registration=false
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu0.dtb
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
interrupts=system.cpu0.interrupts
|
||||
itb=system.cpu0.itb
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
phase=0
|
||||
profile=0
|
||||
progress_interval=0
|
||||
system=system
|
||||
tracer=system.cpu0.tracer
|
||||
workload=
|
||||
dcache_port=system.cpu0.dcache.cpu_side
|
||||
icache_port=system.cpu0.icache.cpu_side
|
||||
|
||||
[system.cpu0.dcache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=4
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=32768
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=8
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu0.dcache_port
|
||||
mem_side=system.toL2Bus.slave[1]
|
||||
|
||||
[system.cpu0.dtb]
|
||||
type=AlphaTLB
|
||||
size=64
|
||||
|
||||
[system.cpu0.icache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=1
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=32768
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=8
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu0.icache_port
|
||||
mem_side=system.toL2Bus.slave[0]
|
||||
|
||||
[system.cpu0.interrupts]
|
||||
type=AlphaInterrupts
|
||||
|
||||
[system.cpu0.itb]
|
||||
type=AlphaTLB
|
||||
size=48
|
||||
|
||||
[system.cpu0.tracer]
|
||||
type=ExeTracer
|
||||
|
||||
[system.cpu1]
|
||||
type=TimingSimpleCPU
|
||||
children=dcache dtb icache interrupts itb tracer
|
||||
checker=Null
|
||||
clock=500
|
||||
cpu_id=1
|
||||
defer_registration=false
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu1.dtb
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
interrupts=system.cpu1.interrupts
|
||||
itb=system.cpu1.itb
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
phase=0
|
||||
profile=0
|
||||
progress_interval=0
|
||||
system=system
|
||||
tracer=system.cpu1.tracer
|
||||
workload=
|
||||
dcache_port=system.cpu1.dcache.cpu_side
|
||||
icache_port=system.cpu1.icache.cpu_side
|
||||
|
||||
[system.cpu1.dcache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=4
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=32768
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=8
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu1.dcache_port
|
||||
mem_side=system.toL2Bus.slave[3]
|
||||
|
||||
[system.cpu1.dtb]
|
||||
type=AlphaTLB
|
||||
size=64
|
||||
|
||||
[system.cpu1.icache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=1
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=32768
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=8
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu1.icache_port
|
||||
mem_side=system.toL2Bus.slave[2]
|
||||
|
||||
[system.cpu1.interrupts]
|
||||
type=AlphaInterrupts
|
||||
|
||||
[system.cpu1.itb]
|
||||
type=AlphaTLB
|
||||
size=48
|
||||
|
||||
[system.cpu1.tracer]
|
||||
type=ExeTracer
|
||||
|
||||
[system.disk0]
|
||||
type=IdeDisk
|
||||
children=image
|
||||
delay=1000000
|
||||
driveID=master
|
||||
image=system.disk0.image
|
||||
|
||||
[system.disk0.image]
|
||||
type=CowDiskImage
|
||||
children=child
|
||||
child=system.disk0.image.child
|
||||
image_file=
|
||||
read_only=false
|
||||
table_size=65536
|
||||
|
||||
[system.disk0.image.child]
|
||||
type=RawDiskImage
|
||||
image_file=/dist/m5/system/disks/linux-latest.img
|
||||
read_only=true
|
||||
|
||||
[system.disk2]
|
||||
type=IdeDisk
|
||||
children=image
|
||||
delay=1000000
|
||||
driveID=master
|
||||
image=system.disk2.image
|
||||
|
||||
[system.disk2.image]
|
||||
type=CowDiskImage
|
||||
children=child
|
||||
child=system.disk2.image.child
|
||||
image_file=
|
||||
read_only=false
|
||||
table_size=65536
|
||||
|
||||
[system.disk2.image.child]
|
||||
type=RawDiskImage
|
||||
image_file=/dist/m5/system/disks/linux-bigswap2.img
|
||||
read_only=true
|
||||
|
||||
[system.intrctrl]
|
||||
type=IntrControl
|
||||
sys=system
|
||||
|
||||
[system.iobus]
|
||||
type=NoncoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
use_default_range=true
|
||||
width=64
|
||||
default=system.tsunami.pciconfig.pio
|
||||
master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ethernet.pio system.tsunami.ethernet.config system.iocache.cpu_side
|
||||
slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma
|
||||
|
||||
[system.iocache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:8589934591
|
||||
assoc=8
|
||||
block_size=64
|
||||
forward_snoops=false
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=50000
|
||||
max_miss_count=0
|
||||
mshrs=20
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=1024
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=12
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.iobus.master[29]
|
||||
mem_side=system.membus.slave[1]
|
||||
|
||||
[system.l2c]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=8
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=false
|
||||
latency=10000
|
||||
max_miss_count=0
|
||||
mshrs=92
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=4194304
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=16
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.toL2Bus.master[0]
|
||||
mem_side=system.membus.slave[2]
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
children=badaddr_responder
|
||||
block_size=64
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
default=system.membus.badaddr_responder.pio
|
||||
master=system.bridge.slave system.physmem.port[0]
|
||||
slave=system.system_port system.iocache.mem_side system.l2c.mem_side
|
||||
|
||||
[system.membus.badaddr_responder]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=0
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=true
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.membus.default
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.membus.master[1]
|
||||
|
||||
[system.simple_disk]
|
||||
type=SimpleDisk
|
||||
children=disk
|
||||
disk=system.simple_disk.disk
|
||||
system=system
|
||||
|
||||
[system.simple_disk.disk]
|
||||
type=RawDiskImage
|
||||
image_file=/dist/m5/system/disks/linux-latest.img
|
||||
read_only=true
|
||||
|
||||
[system.terminal]
|
||||
type=Terminal
|
||||
intr_control=system.intrctrl
|
||||
number=0
|
||||
output=true
|
||||
port=3456
|
||||
|
||||
[system.toL2Bus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
master=system.l2c.cpu_side
|
||||
slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side
|
||||
|
||||
[system.tsunami]
|
||||
type=Tsunami
|
||||
children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart
|
||||
intrctrl=system.intrctrl
|
||||
system=system
|
||||
|
||||
[system.tsunami.backdoor]
|
||||
type=AlphaBackdoor
|
||||
cpu=system.cpu0
|
||||
disk=system.simple_disk
|
||||
pio_addr=8804682956800
|
||||
pio_latency=1000
|
||||
platform=system.tsunami
|
||||
system=system
|
||||
terminal=system.terminal
|
||||
pio=system.iobus.master[24]
|
||||
|
||||
[system.tsunami.cchip]
|
||||
type=TsunamiCChip
|
||||
pio_addr=8803072344064
|
||||
pio_latency=1000
|
||||
system=system
|
||||
tsunami=system.tsunami
|
||||
pio=system.iobus.master[0]
|
||||
|
||||
[system.tsunami.ethernet]
|
||||
type=NSGigE
|
||||
BAR0=1
|
||||
BAR0LegacyIO=false
|
||||
BAR0Size=256
|
||||
BAR1=0
|
||||
BAR1LegacyIO=false
|
||||
BAR1Size=4096
|
||||
BAR2=0
|
||||
BAR2LegacyIO=false
|
||||
BAR2Size=0
|
||||
BAR3=0
|
||||
BAR3LegacyIO=false
|
||||
BAR3Size=0
|
||||
BAR4=0
|
||||
BAR4LegacyIO=false
|
||||
BAR4Size=0
|
||||
BAR5=0
|
||||
BAR5LegacyIO=false
|
||||
BAR5Size=0
|
||||
BIST=0
|
||||
CacheLineSize=0
|
||||
CardbusCIS=0
|
||||
ClassCode=2
|
||||
Command=0
|
||||
DeviceID=34
|
||||
ExpansionROM=0
|
||||
HeaderType=0
|
||||
InterruptLine=30
|
||||
InterruptPin=1
|
||||
LatencyTimer=0
|
||||
MaximumLatency=52
|
||||
MinimumGrant=176
|
||||
ProgIF=0
|
||||
Revision=0
|
||||
Status=656
|
||||
SubClassCode=0
|
||||
SubsystemID=0
|
||||
SubsystemVendorID=0
|
||||
VendorID=4107
|
||||
clock=0
|
||||
config_latency=20000
|
||||
dma_data_free=false
|
||||
dma_desc_free=false
|
||||
dma_no_allocate=true
|
||||
dma_read_delay=0
|
||||
dma_read_factor=0
|
||||
dma_write_delay=0
|
||||
dma_write_factor=0
|
||||
hardware_address=00:90:00:00:00:01
|
||||
intr_delay=10000000
|
||||
max_backoff_delay=10000000
|
||||
min_backoff_delay=4000
|
||||
pci_bus=0
|
||||
pci_dev=1
|
||||
pci_func=0
|
||||
pio_latency=1000
|
||||
platform=system.tsunami
|
||||
rss=false
|
||||
rx_delay=1000000
|
||||
rx_fifo_size=524288
|
||||
rx_filter=true
|
||||
rx_thread=false
|
||||
system=system
|
||||
tx_delay=1000000
|
||||
tx_fifo_size=524288
|
||||
tx_thread=false
|
||||
config=system.iobus.master[28]
|
||||
dma=system.iobus.slave[2]
|
||||
pio=system.iobus.master[27]
|
||||
|
||||
[system.tsunami.fake_OROM]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8796093677568
|
||||
pio_latency=1000
|
||||
pio_size=393216
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[8]
|
||||
|
||||
[system.tsunami.fake_ata0]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615848432
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[19]
|
||||
|
||||
[system.tsunami.fake_ata1]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615848304
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[20]
|
||||
|
||||
[system.tsunami.fake_pnp_addr]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615848569
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[9]
|
||||
|
||||
[system.tsunami.fake_pnp_read0]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615848451
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[11]
|
||||
|
||||
[system.tsunami.fake_pnp_read1]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615848515
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[12]
|
||||
|
||||
[system.tsunami.fake_pnp_read2]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615848579
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[13]
|
||||
|
||||
[system.tsunami.fake_pnp_read3]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615848643
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[14]
|
||||
|
||||
[system.tsunami.fake_pnp_read4]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615848707
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[15]
|
||||
|
||||
[system.tsunami.fake_pnp_read5]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615848771
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[16]
|
||||
|
||||
[system.tsunami.fake_pnp_read6]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615848835
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[17]
|
||||
|
||||
[system.tsunami.fake_pnp_read7]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615848899
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[18]
|
||||
|
||||
[system.tsunami.fake_pnp_write]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615850617
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[10]
|
||||
|
||||
[system.tsunami.fake_ppc]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615848891
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[7]
|
||||
|
||||
[system.tsunami.fake_sm_chip]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615848816
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[2]
|
||||
|
||||
[system.tsunami.fake_uart1]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615848696
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[3]
|
||||
|
||||
[system.tsunami.fake_uart2]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615848936
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[4]
|
||||
|
||||
[system.tsunami.fake_uart3]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615848680
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[5]
|
||||
|
||||
[system.tsunami.fake_uart4]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615848944
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[6]
|
||||
|
||||
[system.tsunami.fb]
|
||||
type=BadDevice
|
||||
devicename=FrameBuffer
|
||||
pio_addr=8804615848912
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.iobus.master[21]
|
||||
|
||||
[system.tsunami.ide]
|
||||
type=IdeController
|
||||
BAR0=1
|
||||
BAR0LegacyIO=false
|
||||
BAR0Size=8
|
||||
BAR1=1
|
||||
BAR1LegacyIO=false
|
||||
BAR1Size=4
|
||||
BAR2=1
|
||||
BAR2LegacyIO=false
|
||||
BAR2Size=8
|
||||
BAR3=1
|
||||
BAR3LegacyIO=false
|
||||
BAR3Size=4
|
||||
BAR4=1
|
||||
BAR4LegacyIO=false
|
||||
BAR4Size=16
|
||||
BAR5=1
|
||||
BAR5LegacyIO=false
|
||||
BAR5Size=0
|
||||
BIST=0
|
||||
CacheLineSize=0
|
||||
CardbusCIS=0
|
||||
ClassCode=1
|
||||
Command=0
|
||||
DeviceID=28945
|
||||
ExpansionROM=0
|
||||
HeaderType=0
|
||||
InterruptLine=31
|
||||
InterruptPin=1
|
||||
LatencyTimer=0
|
||||
MaximumLatency=0
|
||||
MinimumGrant=0
|
||||
ProgIF=133
|
||||
Revision=0
|
||||
Status=640
|
||||
SubClassCode=1
|
||||
SubsystemID=0
|
||||
SubsystemVendorID=0
|
||||
VendorID=32902
|
||||
config_latency=20000
|
||||
ctrl_offset=0
|
||||
disks=system.disk0 system.disk2
|
||||
io_shift=0
|
||||
max_backoff_delay=10000000
|
||||
min_backoff_delay=4000
|
||||
pci_bus=0
|
||||
pci_dev=0
|
||||
pci_func=0
|
||||
pio_latency=1000
|
||||
platform=system.tsunami
|
||||
system=system
|
||||
config=system.iobus.master[26]
|
||||
dma=system.iobus.slave[1]
|
||||
pio=system.iobus.master[25]
|
||||
|
||||
[system.tsunami.io]
|
||||
type=TsunamiIO
|
||||
frequency=976562500
|
||||
pio_addr=8804615847936
|
||||
pio_latency=1000
|
||||
system=system
|
||||
time=Thu Jan 1 00:00:00 2009
|
||||
tsunami=system.tsunami
|
||||
year_is_bcd=false
|
||||
pio=system.iobus.master[22]
|
||||
|
||||
[system.tsunami.pchip]
|
||||
type=TsunamiPChip
|
||||
pio_addr=8802535473152
|
||||
pio_latency=1000
|
||||
system=system
|
||||
tsunami=system.tsunami
|
||||
pio=system.iobus.master[1]
|
||||
|
||||
[system.tsunami.pciconfig]
|
||||
type=PciConfigAll
|
||||
bus=0
|
||||
pio_latency=1
|
||||
platform=system.tsunami
|
||||
size=16777216
|
||||
system=system
|
||||
pio=system.iobus.default
|
||||
|
||||
[system.tsunami.uart]
|
||||
type=Uart8250
|
||||
pio_addr=8804615848952
|
||||
pio_latency=1000
|
||||
platform=system.tsunami
|
||||
system=system
|
||||
terminal=system.terminal
|
||||
pio=system.iobus.master[23]
|
||||
|
||||
@ -0,0 +1,5 @@
|
||||
warn: Sockets disabled, not accepting terminal connections
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: Prefetch instructions in Alpha do not do anything
|
||||
warn: Prefetch instructions in Alpha do not do anything
|
||||
hack: be nice to actually delete the event here
|
||||
@ -0,0 +1,13 @@
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jun 4 2012 11:50:11
|
||||
gem5 started Jun 4 2012 13:42:45
|
||||
gem5 executing on zizzer
|
||||
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual -re tests/run.py build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: kernel located at: /dist/m5/system/binaries/vmlinux
|
||||
0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Launching CPU 1 @ 562628000
|
||||
Exiting @ tick 1958647095000 because m5_exit instruction encountered
|
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,113 @@
|
||||
M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
|
||||
|
||||
Got Configuration 623
|
||||
|
||||
memsize 8000000 pages 4000
|
||||
|
||||
First free page after ROM 0xFFFFFC0000018000
|
||||
|
||||
HWRPB 0xFFFFFC0000018000 l1pt 0xFFFFFC0000040000 l2pt 0xFFFFFC0000042000 l3pt_rpb 0xFFFFFC0000044000 l3pt_kernel 0xFFFFFC0000048000 l2reserv 0xFFFFFC0000046000
|
||||
|
||||
kstart = 0xFFFFFC0000310000, kend = 0xFFFFFC0000855898, kentry = 0xFFFFFC0000310000, numCPUs = 0x2
|
||||
|
||||
CPU Clock at 2000 MHz IntrClockFrequency=1024
|
||||
|
||||
Booting with 2 processor(s)
|
||||
|
||||
KSP: 0x20043FE8 PTBR 0x20
|
||||
|
||||
KSP: 0x20043FE8 PTBR 0x20
|
||||
|
||||
Console Callback at 0x0, fixup at 0x0, crb offset: 0x790
|
||||
|
||||
Memory cluster 0 [0 - 392]
|
||||
|
||||
Memory cluster 1 [392 - 15992]
|
||||
|
||||
Initalizing mdt_bitmap addr 0xFFFFFC0000038000 mem_pages 4000
|
||||
|
||||
ConsoleDispatch at virt 100008D8 phys 188D8 val FFFFFC00000100A8
|
||||
|
||||
Bootstraping CPU 1 with sp=0xFFFFFC0000076000
|
||||
|
||||
unix_boot_mem ends at FFFFFC0000078000
|
||||
|
||||
k_argc = 0
|
||||
|
||||
jumping to kernel at 0xFFFFFC0000310000, (PCBB 0xFFFFFC0000018180 pfn 1067)
|
||||
|
||||
Entering slaveloop for cpu 1 my_rpb=FFFFFC0000018400
|
||||
|
||||
CallbackFixup 0 18000, t7=FFFFFC000070C000
|
||||
|
||||
Linux version 2.6.13 (hsul@zed.eecs.umich.edu) (gcc version 3.4.3) #1 SMP Sun Oct 8 19:52:07 EDT 2006
|
||||
|
||||
Booting GENERIC on Tsunami variation DP264 using machine vector DP264 from SRM
|
||||
|
||||
Major Options: SMP LEGACY_START VERBOSE_MCHECK
|
||||
|
||||
Command line: root=/dev/hda1 console=ttyS0
|
||||
|
||||
memcluster 0, usage 1, start 0, end 392
|
||||
|
||||
memcluster 1, usage 0, start 392, end 16384
|
||||
|
||||
freeing pages 1069:16384
|
||||
|
||||
reserving pages 1069:1070
|
||||
|
||||
4096K Bcache detected; load hit latency 40 cycles, load miss latency 123 cycles
|
||||
|
||||
SMP: 2 CPUs probed -- cpu_present_mask = 3
|
||||
|
||||
Built 1 zonelists
|
||||
|
||||
Kernel command line: root=/dev/hda1 console=ttyS0
|
||||
|
||||
PID hash table entries: 1024 (order: 10, 32768 bytes)
|
||||
|
||||
Using epoch = 1900
|
||||
|
||||
Console: colour dummy device 80x25
|
||||
|
||||
Dentry cache hash table entries: 32768 (order: 5, 262144 bytes)
|
||||
|
||||
Inode-cache hash table entries: 16384 (order: 4, 131072 bytes)
|
||||
|
||||
Memory: 118784k/131072k available (3314k kernel code, 8952k reserved, 983k data, 224k init)
|
||||
|
||||
Mount-cache hash table entries: 512
|
||||
|
||||
SMP starting up secondaries.
|
||||
|
||||
Slave CPU 1 console command START
|
||||
SlaveCmd: restart FFFFFC0000310020 FFFFFC0000310020 vptb FFFFFFFE00000000 my_rpb FFFFFC0000018400 my_rpb_phys 18400
|
||||
|
||||
Brought up 2 CPUs
|
||||
|
||||
SMP: Total of 2 processors activated (8000.15 BogoMIPS).
|
||||
|
||||
NET: Registered protocol family 16
|
||||
|
||||
EISA bus registered
|
||||
|
||||
pci: enabling save/restore of SRM state
|
||||
|
||||
SCSI subsystem initialized
|
||||
|
||||
srm_env: version 0.0.5 loaded successfully
|
||||
|
||||
Installing knfsd (copyright (C) 1996 okir@monad.swb.de).
|
||||
|
||||
Initializing Cryptographic API
|
||||
|
||||
rtc: Standard PC (1900) epoch (1900) detected
|
||||
|
||||
Real Time Clock Driver v1.12
|
||||
|
||||
Serial: 8250/16550 driver $Revision: 1.90 $ 1 ports, IRQ sharing disabled
|
||||
|
||||
ttyS0 at I/O 0x3f8 (irq = 4) is a 8250
|
||||
|
||||
io scheduler noop registered
|
||||
|
||||
@ -0,0 +1,812 @@
|
||||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
full_system=true
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
||||
[system]
|
||||
type=LinuxAlphaSystem
|
||||
children=bridge cpu disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami
|
||||
boot_cpu_frequency=500
|
||||
boot_osflags=root=/dev/hda1 console=ttyS0
|
||||
console=/dist/m5/system/binaries/console
|
||||
init_param=0
|
||||
kernel=/dist/m5/system/binaries/vmlinux
|
||||
load_addr_mask=1099511627775
|
||||
mem_mode=timing
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
pal=/dist/m5/system/binaries/ts_osfpal
|
||||
readfile=tests/halt.sh
|
||||
symbolfile=
|
||||
system_rev=1024
|
||||
system_type=34
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.membus.slave[0]
|
||||
|
||||
[system.bridge]
|
||||
type=Bridge
|
||||
delay=50000
|
||||
nack_delay=4000
|
||||
ranges=8796093022208:18446744073709551615
|
||||
req_size=16
|
||||
resp_size=16
|
||||
write_ack=false
|
||||
master=system.iobus.slave[0]
|
||||
slave=system.membus.master[0]
|
||||
|
||||
[system.cpu]
|
||||
type=TimingSimpleCPU
|
||||
children=dcache dtb icache interrupts itb tracer
|
||||
checker=Null
|
||||
clock=500
|
||||
cpu_id=0
|
||||
defer_registration=false
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
interrupts=system.cpu.interrupts
|
||||
itb=system.cpu.itb
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
phase=0
|
||||
profile=0
|
||||
progress_interval=0
|
||||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
workload=
|
||||
dcache_port=system.cpu.dcache.cpu_side
|
||||
icache_port=system.cpu.icache.cpu_side
|
||||
|
||||
[system.cpu.dcache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=4
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=32768
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=8
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.dcache_port
|
||||
mem_side=system.toL2Bus.slave[1]
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=AlphaTLB
|
||||
size=64
|
||||
|
||||
[system.cpu.icache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=1
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=32768
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=8
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.icache_port
|
||||
mem_side=system.toL2Bus.slave[0]
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=AlphaInterrupts
|
||||
|
||||
[system.cpu.itb]
|
||||
type=AlphaTLB
|
||||
size=48
|
||||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
|
||||
[system.disk0]
|
||||
type=IdeDisk
|
||||
children=image
|
||||
delay=1000000
|
||||
driveID=master
|
||||
image=system.disk0.image
|
||||
|
||||
[system.disk0.image]
|
||||
type=CowDiskImage
|
||||
children=child
|
||||
child=system.disk0.image.child
|
||||
image_file=
|
||||
read_only=false
|
||||
table_size=65536
|
||||
|
||||
[system.disk0.image.child]
|
||||
type=RawDiskImage
|
||||
image_file=/dist/m5/system/disks/linux-latest.img
|
||||
read_only=true
|
||||
|
||||
[system.disk2]
|
||||
type=IdeDisk
|
||||
children=image
|
||||
delay=1000000
|
||||
driveID=master
|
||||
image=system.disk2.image
|
||||
|
||||
[system.disk2.image]
|
||||
type=CowDiskImage
|
||||
children=child
|
||||
child=system.disk2.image.child
|
||||
image_file=
|
||||
read_only=false
|
||||
table_size=65536
|
||||
|
||||
[system.disk2.image.child]
|
||||
type=RawDiskImage
|
||||
image_file=/dist/m5/system/disks/linux-bigswap2.img
|
||||
read_only=true
|
||||
|
||||
[system.intrctrl]
|
||||
type=IntrControl
|
||||
sys=system
|
||||
|
||||
[system.iobus]
|
||||
type=NoncoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
use_default_range=true
|
||||
width=64
|
||||
default=system.tsunami.pciconfig.pio
|
||||
master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ethernet.pio system.tsunami.ethernet.config system.iocache.cpu_side
|
||||
slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma
|
||||
|
||||
[system.iocache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:8589934591
|
||||
assoc=8
|
||||
block_size=64
|
||||
forward_snoops=false
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=50000
|
||||
max_miss_count=0
|
||||
mshrs=20
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=1024
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=12
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.iobus.master[29]
|
||||
mem_side=system.membus.slave[1]
|
||||
|
||||
[system.l2c]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=8
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=false
|
||||
latency=10000
|
||||
max_miss_count=0
|
||||
mshrs=92
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=4194304
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=16
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.toL2Bus.master[0]
|
||||
mem_side=system.membus.slave[2]
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
children=badaddr_responder
|
||||
block_size=64
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
default=system.membus.badaddr_responder.pio
|
||||
master=system.bridge.slave system.physmem.port[0]
|
||||
slave=system.system_port system.iocache.mem_side system.l2c.mem_side
|
||||
|
||||
[system.membus.badaddr_responder]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=0
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=true
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.membus.default
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.membus.master[1]
|
||||
|
||||
[system.simple_disk]
|
||||
type=SimpleDisk
|
||||
children=disk
|
||||
disk=system.simple_disk.disk
|
||||
system=system
|
||||
|
||||
[system.simple_disk.disk]
|
||||
type=RawDiskImage
|
||||
image_file=/dist/m5/system/disks/linux-latest.img
|
||||
read_only=true
|
||||
|
||||
[system.terminal]
|
||||
type=Terminal
|
||||
intr_control=system.intrctrl
|
||||
number=0
|
||||
output=true
|
||||
port=3456
|
||||
|
||||
[system.toL2Bus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
master=system.l2c.cpu_side
|
||||
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
|
||||
|
||||
[system.tsunami]
|
||||
type=Tsunami
|
||||
children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart
|
||||
intrctrl=system.intrctrl
|
||||
system=system
|
||||
|
||||
[system.tsunami.backdoor]
|
||||
type=AlphaBackdoor
|
||||
cpu=system.cpu
|
||||
disk=system.simple_disk
|
||||
pio_addr=8804682956800
|
||||
pio_latency=1000
|
||||
platform=system.tsunami
|
||||
system=system
|
||||
terminal=system.terminal
|
||||
pio=system.iobus.master[24]
|
||||
|
||||
[system.tsunami.cchip]
|
||||
type=TsunamiCChip
|
||||
pio_addr=8803072344064
|
||||
pio_latency=1000
|
||||
system=system
|
||||
tsunami=system.tsunami
|
||||
pio=system.iobus.master[0]
|
||||
|
||||
[system.tsunami.ethernet]
|
||||
type=NSGigE
|
||||
BAR0=1
|
||||
BAR0LegacyIO=false
|
||||
BAR0Size=256
|
||||
BAR1=0
|
||||
BAR1LegacyIO=false
|
||||
BAR1Size=4096
|
||||
BAR2=0
|
||||
BAR2LegacyIO=false
|
||||
BAR2Size=0
|
||||
BAR3=0
|
||||
BAR3LegacyIO=false
|
||||
BAR3Size=0
|
||||
BAR4=0
|
||||
BAR4LegacyIO=false
|
||||
BAR4Size=0
|
||||
BAR5=0
|
||||
BAR5LegacyIO=false
|
||||
BAR5Size=0
|
||||
BIST=0
|
||||
CacheLineSize=0
|
||||
CardbusCIS=0
|
||||
ClassCode=2
|
||||
Command=0
|
||||
DeviceID=34
|
||||
ExpansionROM=0
|
||||
HeaderType=0
|
||||
InterruptLine=30
|
||||
InterruptPin=1
|
||||
LatencyTimer=0
|
||||
MaximumLatency=52
|
||||
MinimumGrant=176
|
||||
ProgIF=0
|
||||
Revision=0
|
||||
Status=656
|
||||
SubClassCode=0
|
||||
SubsystemID=0
|
||||
SubsystemVendorID=0
|
||||
VendorID=4107
|
||||
clock=0
|
||||
config_latency=20000
|
||||
dma_data_free=false
|
||||
dma_desc_free=false
|
||||
dma_no_allocate=true
|
||||
dma_read_delay=0
|
||||
dma_read_factor=0
|
||||
dma_write_delay=0
|
||||
dma_write_factor=0
|
||||
hardware_address=00:90:00:00:00:01
|
||||
intr_delay=10000000
|
||||
max_backoff_delay=10000000
|
||||
min_backoff_delay=4000
|
||||
pci_bus=0
|
||||
pci_dev=1
|
||||
pci_func=0
|
||||
pio_latency=1000
|
||||
platform=system.tsunami
|
||||
rss=false
|
||||
rx_delay=1000000
|
||||
rx_fifo_size=524288
|
||||
rx_filter=true
|
||||
rx_thread=false
|
||||
system=system
|
||||
tx_delay=1000000
|
||||
tx_fifo_size=524288
|
||||
tx_thread=false
|
||||
config=system.iobus.master[28]
|
||||
dma=system.iobus.slave[2]
|
||||
pio=system.iobus.master[27]
|
||||
|
||||
[system.tsunami.fake_OROM]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8796093677568
|
||||
pio_latency=1000
|
||||
pio_size=393216
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[8]
|
||||
|
||||
[system.tsunami.fake_ata0]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615848432
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[19]
|
||||
|
||||
[system.tsunami.fake_ata1]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615848304
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[20]
|
||||
|
||||
[system.tsunami.fake_pnp_addr]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615848569
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[9]
|
||||
|
||||
[system.tsunami.fake_pnp_read0]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615848451
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[11]
|
||||
|
||||
[system.tsunami.fake_pnp_read1]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615848515
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[12]
|
||||
|
||||
[system.tsunami.fake_pnp_read2]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615848579
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[13]
|
||||
|
||||
[system.tsunami.fake_pnp_read3]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615848643
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[14]
|
||||
|
||||
[system.tsunami.fake_pnp_read4]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615848707
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[15]
|
||||
|
||||
[system.tsunami.fake_pnp_read5]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615848771
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[16]
|
||||
|
||||
[system.tsunami.fake_pnp_read6]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615848835
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[17]
|
||||
|
||||
[system.tsunami.fake_pnp_read7]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615848899
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[18]
|
||||
|
||||
[system.tsunami.fake_pnp_write]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615850617
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[10]
|
||||
|
||||
[system.tsunami.fake_ppc]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615848891
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[7]
|
||||
|
||||
[system.tsunami.fake_sm_chip]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615848816
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[2]
|
||||
|
||||
[system.tsunami.fake_uart1]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615848696
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[3]
|
||||
|
||||
[system.tsunami.fake_uart2]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615848936
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[4]
|
||||
|
||||
[system.tsunami.fake_uart3]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615848680
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[5]
|
||||
|
||||
[system.tsunami.fake_uart4]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=8804615848944
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[6]
|
||||
|
||||
[system.tsunami.fb]
|
||||
type=BadDevice
|
||||
devicename=FrameBuffer
|
||||
pio_addr=8804615848912
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.iobus.master[21]
|
||||
|
||||
[system.tsunami.ide]
|
||||
type=IdeController
|
||||
BAR0=1
|
||||
BAR0LegacyIO=false
|
||||
BAR0Size=8
|
||||
BAR1=1
|
||||
BAR1LegacyIO=false
|
||||
BAR1Size=4
|
||||
BAR2=1
|
||||
BAR2LegacyIO=false
|
||||
BAR2Size=8
|
||||
BAR3=1
|
||||
BAR3LegacyIO=false
|
||||
BAR3Size=4
|
||||
BAR4=1
|
||||
BAR4LegacyIO=false
|
||||
BAR4Size=16
|
||||
BAR5=1
|
||||
BAR5LegacyIO=false
|
||||
BAR5Size=0
|
||||
BIST=0
|
||||
CacheLineSize=0
|
||||
CardbusCIS=0
|
||||
ClassCode=1
|
||||
Command=0
|
||||
DeviceID=28945
|
||||
ExpansionROM=0
|
||||
HeaderType=0
|
||||
InterruptLine=31
|
||||
InterruptPin=1
|
||||
LatencyTimer=0
|
||||
MaximumLatency=0
|
||||
MinimumGrant=0
|
||||
ProgIF=133
|
||||
Revision=0
|
||||
Status=640
|
||||
SubClassCode=1
|
||||
SubsystemID=0
|
||||
SubsystemVendorID=0
|
||||
VendorID=32902
|
||||
config_latency=20000
|
||||
ctrl_offset=0
|
||||
disks=system.disk0 system.disk2
|
||||
io_shift=0
|
||||
max_backoff_delay=10000000
|
||||
min_backoff_delay=4000
|
||||
pci_bus=0
|
||||
pci_dev=0
|
||||
pci_func=0
|
||||
pio_latency=1000
|
||||
platform=system.tsunami
|
||||
system=system
|
||||
config=system.iobus.master[26]
|
||||
dma=system.iobus.slave[1]
|
||||
pio=system.iobus.master[25]
|
||||
|
||||
[system.tsunami.io]
|
||||
type=TsunamiIO
|
||||
frequency=976562500
|
||||
pio_addr=8804615847936
|
||||
pio_latency=1000
|
||||
system=system
|
||||
time=Thu Jan 1 00:00:00 2009
|
||||
tsunami=system.tsunami
|
||||
year_is_bcd=false
|
||||
pio=system.iobus.master[22]
|
||||
|
||||
[system.tsunami.pchip]
|
||||
type=TsunamiPChip
|
||||
pio_addr=8802535473152
|
||||
pio_latency=1000
|
||||
system=system
|
||||
tsunami=system.tsunami
|
||||
pio=system.iobus.master[1]
|
||||
|
||||
[system.tsunami.pciconfig]
|
||||
type=PciConfigAll
|
||||
bus=0
|
||||
pio_latency=1
|
||||
platform=system.tsunami
|
||||
size=16777216
|
||||
system=system
|
||||
pio=system.iobus.default
|
||||
|
||||
[system.tsunami.uart]
|
||||
type=Uart8250
|
||||
pio_addr=8804615848952
|
||||
pio_latency=1000
|
||||
platform=system.tsunami
|
||||
system=system
|
||||
terminal=system.terminal
|
||||
pio=system.iobus.master[23]
|
||||
|
||||
@ -0,0 +1,5 @@
|
||||
warn: Sockets disabled, not accepting terminal connections
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: Prefetch instructions in Alpha do not do anything
|
||||
warn: Prefetch instructions in Alpha do not do anything
|
||||
hack: be nice to actually delete the event here
|
||||
@ -0,0 +1,12 @@
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jun 4 2012 11:50:11
|
||||
gem5 started Jun 4 2012 14:23:20
|
||||
gem5 executing on zizzer
|
||||
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing -re tests/run.py build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: kernel located at: /dist/m5/system/binaries/vmlinux
|
||||
0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 1915548867000 because m5_exit instruction encountered
|
||||
@ -0,0 +1,702 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 1.915549 # Number of seconds simulated
|
||||
sim_ticks 1915548867000 # Number of ticks simulated
|
||||
final_tick 1915548867000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1238015 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1238014 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 42244373047 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 292960 # Number of bytes of host memory used
|
||||
host_seconds 45.34 # Real time elapsed on the host
|
||||
sim_insts 56137087 # Number of instructions simulated
|
||||
sim_ops 56137087 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 943040 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 26067904 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::tsunami.ide 2652416 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 29663360 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 943040 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 943040 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 10122368 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 10122368 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 14735 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 407311 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::tsunami.ide 41444 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 463490 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 158162 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 158162 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 492308 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 13608582 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::tsunami.ide 1384677 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 15485567 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 492308 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 492308 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 5284317 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 5284317 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 5284317 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 492308 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 13608582 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::tsunami.ide 1384677 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 20769884 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.l2c.replacements 389289 # number of replacements
|
||||
system.l2c.tagsinuse 34352.038344 # Cycle average of tags in use
|
||||
system.l2c.total_refs 2311163 # Total number of references to valid blocks.
|
||||
system.l2c.sampled_refs 421794 # Sample count of references to valid blocks.
|
||||
system.l2c.avg_refs 5.479364 # Average number of references to valid blocks.
|
||||
system.l2c.warmup_cycle 6937912000 # Cycle when the warmup percentage was hit.
|
||||
system.l2c.occ_blocks::writebacks 23110.665097 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu.inst 3746.363547 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu.data 7495.009700 # Average occupied blocks per requestor
|
||||
system.l2c.occ_percent::writebacks 0.352641 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu.inst 0.057165 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu.data 0.114365 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::total 0.524171 # Average percentage of cache occupancy
|
||||
system.l2c.ReadReq_hits::cpu.inst 913599 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu.data 796862 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::total 1710461 # number of ReadReq hits
|
||||
system.l2c.Writeback_hits::writebacks 826671 # number of Writeback hits
|
||||
system.l2c.Writeback_hits::total 826671 # number of Writeback hits
|
||||
system.l2c.UpgradeReq_hits::cpu.data 6 # number of UpgradeReq hits
|
||||
system.l2c.UpgradeReq_hits::total 6 # number of UpgradeReq hits
|
||||
system.l2c.ReadExReq_hits::cpu.data 185878 # number of ReadExReq hits
|
||||
system.l2c.ReadExReq_hits::total 185878 # number of ReadExReq hits
|
||||
system.l2c.demand_hits::cpu.inst 913599 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu.data 982740 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::total 1896339 # number of demand (read+write) hits
|
||||
system.l2c.overall_hits::cpu.inst 913599 # number of overall hits
|
||||
system.l2c.overall_hits::cpu.data 982740 # number of overall hits
|
||||
system.l2c.overall_hits::total 1896339 # number of overall hits
|
||||
system.l2c.ReadReq_misses::cpu.inst 14735 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu.data 289403 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::total 304138 # number of ReadReq misses
|
||||
system.l2c.UpgradeReq_misses::cpu.data 7 # number of UpgradeReq misses
|
||||
system.l2c.UpgradeReq_misses::total 7 # number of UpgradeReq misses
|
||||
system.l2c.ReadExReq_misses::cpu.data 118294 # number of ReadExReq misses
|
||||
system.l2c.ReadExReq_misses::total 118294 # number of ReadExReq misses
|
||||
system.l2c.demand_misses::cpu.inst 14735 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu.data 407697 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::total 422432 # number of demand (read+write) misses
|
||||
system.l2c.overall_misses::cpu.inst 14735 # number of overall misses
|
||||
system.l2c.overall_misses::cpu.data 407697 # number of overall misses
|
||||
system.l2c.overall_misses::total 422432 # number of overall misses
|
||||
system.l2c.ReadReq_miss_latency::cpu.inst 766261500 # number of ReadReq miss cycles
|
||||
system.l2c.ReadReq_miss_latency::cpu.data 15053945000 # number of ReadReq miss cycles
|
||||
system.l2c.ReadReq_miss_latency::total 15820206500 # number of ReadReq miss cycles
|
||||
system.l2c.UpgradeReq_miss_latency::cpu.data 248000 # number of UpgradeReq miss cycles
|
||||
system.l2c.UpgradeReq_miss_latency::total 248000 # number of UpgradeReq miss cycles
|
||||
system.l2c.ReadExReq_miss_latency::cpu.data 6151753000 # number of ReadExReq miss cycles
|
||||
system.l2c.ReadExReq_miss_latency::total 6151753000 # number of ReadExReq miss cycles
|
||||
system.l2c.demand_miss_latency::cpu.inst 766261500 # number of demand (read+write) miss cycles
|
||||
system.l2c.demand_miss_latency::cpu.data 21205698000 # number of demand (read+write) miss cycles
|
||||
system.l2c.demand_miss_latency::total 21971959500 # number of demand (read+write) miss cycles
|
||||
system.l2c.overall_miss_latency::cpu.inst 766261500 # number of overall miss cycles
|
||||
system.l2c.overall_miss_latency::cpu.data 21205698000 # number of overall miss cycles
|
||||
system.l2c.overall_miss_latency::total 21971959500 # number of overall miss cycles
|
||||
system.l2c.ReadReq_accesses::cpu.inst 928334 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::cpu.data 1086265 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::total 2014599 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.Writeback_accesses::writebacks 826671 # number of Writeback accesses(hits+misses)
|
||||
system.l2c.Writeback_accesses::total 826671 # number of Writeback accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_accesses::cpu.data 13 # number of UpgradeReq accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_accesses::total 13 # number of UpgradeReq accesses(hits+misses)
|
||||
system.l2c.ReadExReq_accesses::cpu.data 304172 # number of ReadExReq accesses(hits+misses)
|
||||
system.l2c.ReadExReq_accesses::total 304172 # number of ReadExReq accesses(hits+misses)
|
||||
system.l2c.demand_accesses::cpu.inst 928334 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu.data 1390437 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::total 2318771 # number of demand (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu.inst 928334 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu.data 1390437 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::total 2318771 # number of overall (read+write) accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu.inst 0.015873 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu.data 0.266420 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::total 0.150967 # miss rate for ReadReq accesses
|
||||
system.l2c.UpgradeReq_miss_rate::cpu.data 0.538462 # miss rate for UpgradeReq accesses
|
||||
system.l2c.UpgradeReq_miss_rate::total 0.538462 # miss rate for UpgradeReq accesses
|
||||
system.l2c.ReadExReq_miss_rate::cpu.data 0.388905 # miss rate for ReadExReq accesses
|
||||
system.l2c.ReadExReq_miss_rate::total 0.388905 # miss rate for ReadExReq accesses
|
||||
system.l2c.demand_miss_rate::cpu.inst 0.015873 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu.data 0.293215 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::total 0.182179 # miss rate for demand accesses
|
||||
system.l2c.overall_miss_rate::cpu.inst 0.015873 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu.data 0.293215 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::total 0.182179 # miss rate for overall accesses
|
||||
system.l2c.ReadReq_avg_miss_latency::cpu.inst 52002.816423 # average ReadReq miss latency
|
||||
system.l2c.ReadReq_avg_miss_latency::cpu.data 52017.238937 # average ReadReq miss latency
|
||||
system.l2c.ReadReq_avg_miss_latency::total 52016.540189 # average ReadReq miss latency
|
||||
system.l2c.UpgradeReq_avg_miss_latency::cpu.data 35428.571429 # average UpgradeReq miss latency
|
||||
system.l2c.UpgradeReq_avg_miss_latency::total 35428.571429 # average UpgradeReq miss latency
|
||||
system.l2c.ReadExReq_avg_miss_latency::cpu.data 52003.930884 # average ReadExReq miss latency
|
||||
system.l2c.ReadExReq_avg_miss_latency::total 52003.930884 # average ReadExReq miss latency
|
||||
system.l2c.demand_avg_miss_latency::cpu.inst 52002.816423 # average overall miss latency
|
||||
system.l2c.demand_avg_miss_latency::cpu.data 52013.377582 # average overall miss latency
|
||||
system.l2c.demand_avg_miss_latency::total 52013.009194 # average overall miss latency
|
||||
system.l2c.overall_avg_miss_latency::cpu.inst 52002.816423 # average overall miss latency
|
||||
system.l2c.overall_avg_miss_latency::cpu.data 52013.377582 # average overall miss latency
|
||||
system.l2c.overall_avg_miss_latency::total 52013.009194 # average overall miss latency
|
||||
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.l2c.fast_writes 0 # number of fast writes performed
|
||||
system.l2c.cache_copies 0 # number of cache copies performed
|
||||
system.l2c.writebacks::writebacks 116650 # number of writebacks
|
||||
system.l2c.writebacks::total 116650 # number of writebacks
|
||||
system.l2c.ReadReq_mshr_misses::cpu.inst 14735 # number of ReadReq MSHR misses
|
||||
system.l2c.ReadReq_mshr_misses::cpu.data 289403 # number of ReadReq MSHR misses
|
||||
system.l2c.ReadReq_mshr_misses::total 304138 # number of ReadReq MSHR misses
|
||||
system.l2c.UpgradeReq_mshr_misses::cpu.data 7 # number of UpgradeReq MSHR misses
|
||||
system.l2c.UpgradeReq_mshr_misses::total 7 # number of UpgradeReq MSHR misses
|
||||
system.l2c.ReadExReq_mshr_misses::cpu.data 118294 # number of ReadExReq MSHR misses
|
||||
system.l2c.ReadExReq_mshr_misses::total 118294 # number of ReadExReq MSHR misses
|
||||
system.l2c.demand_mshr_misses::cpu.inst 14735 # number of demand (read+write) MSHR misses
|
||||
system.l2c.demand_mshr_misses::cpu.data 407697 # number of demand (read+write) MSHR misses
|
||||
system.l2c.demand_mshr_misses::total 422432 # number of demand (read+write) MSHR misses
|
||||
system.l2c.overall_mshr_misses::cpu.inst 14735 # number of overall MSHR misses
|
||||
system.l2c.overall_mshr_misses::cpu.data 407697 # number of overall MSHR misses
|
||||
system.l2c.overall_mshr_misses::total 422432 # number of overall MSHR misses
|
||||
system.l2c.ReadReq_mshr_miss_latency::cpu.inst 589436000 # number of ReadReq MSHR miss cycles
|
||||
system.l2c.ReadReq_mshr_miss_latency::cpu.data 11581109000 # number of ReadReq MSHR miss cycles
|
||||
system.l2c.ReadReq_mshr_miss_latency::total 12170545000 # number of ReadReq MSHR miss cycles
|
||||
system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 320000 # number of UpgradeReq MSHR miss cycles
|
||||
system.l2c.UpgradeReq_mshr_miss_latency::total 320000 # number of UpgradeReq MSHR miss cycles
|
||||
system.l2c.ReadExReq_mshr_miss_latency::cpu.data 4732225000 # number of ReadExReq MSHR miss cycles
|
||||
system.l2c.ReadExReq_mshr_miss_latency::total 4732225000 # number of ReadExReq MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_latency::cpu.inst 589436000 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_latency::cpu.data 16313334000 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_latency::total 16902770000 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency::cpu.inst 589436000 # number of overall MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency::cpu.data 16313334000 # number of overall MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency::total 16902770000 # number of overall MSHR miss cycles
|
||||
system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 772673000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.l2c.ReadReq_mshr_uncacheable_latency::total 772673000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 1083819500 # number of WriteReq MSHR uncacheable cycles
|
||||
system.l2c.WriteReq_mshr_uncacheable_latency::total 1083819500 # number of WriteReq MSHR uncacheable cycles
|
||||
system.l2c.overall_mshr_uncacheable_latency::cpu.data 1856492500 # number of overall MSHR uncacheable cycles
|
||||
system.l2c.overall_mshr_uncacheable_latency::total 1856492500 # number of overall MSHR uncacheable cycles
|
||||
system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.015873 # mshr miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.266420 # mshr miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_mshr_miss_rate::total 0.150967 # mshr miss rate for ReadReq accesses
|
||||
system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.538462 # mshr miss rate for UpgradeReq accesses
|
||||
system.l2c.UpgradeReq_mshr_miss_rate::total 0.538462 # mshr miss rate for UpgradeReq accesses
|
||||
system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.388905 # mshr miss rate for ReadExReq accesses
|
||||
system.l2c.ReadExReq_mshr_miss_rate::total 0.388905 # mshr miss rate for ReadExReq accesses
|
||||
system.l2c.demand_mshr_miss_rate::cpu.inst 0.015873 # mshr miss rate for demand accesses
|
||||
system.l2c.demand_mshr_miss_rate::cpu.data 0.293215 # mshr miss rate for demand accesses
|
||||
system.l2c.demand_mshr_miss_rate::total 0.182179 # mshr miss rate for demand accesses
|
||||
system.l2c.overall_mshr_miss_rate::cpu.inst 0.015873 # mshr miss rate for overall accesses
|
||||
system.l2c.overall_mshr_miss_rate::cpu.data 0.293215 # mshr miss rate for overall accesses
|
||||
system.l2c.overall_mshr_miss_rate::total 0.182179 # mshr miss rate for overall accesses
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40002.443163 # average ReadReq mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40017.238937 # average ReadReq mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::total 40016.522105 # average ReadReq mshr miss latency
|
||||
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 45714.285714 # average UpgradeReq mshr miss latency
|
||||
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 45714.285714 # average UpgradeReq mshr miss latency
|
||||
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40003.930884 # average ReadExReq mshr miss latency
|
||||
system.l2c.ReadExReq_avg_mshr_miss_latency::total 40003.930884 # average ReadExReq mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40002.443163 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu.data 40013.377582 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::total 40012.996175 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40002.443163 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu.data 40013.377582 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::total 40012.996175 # average overall mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
|
||||
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
||||
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
|
||||
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
||||
system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
|
||||
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
||||
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.iocache.replacements 41685 # number of replacements
|
||||
system.iocache.tagsinuse 1.340325 # Cycle average of tags in use
|
||||
system.iocache.total_refs 0 # Total number of references to valid blocks.
|
||||
system.iocache.sampled_refs 41701 # Sample count of references to valid blocks.
|
||||
system.iocache.avg_refs 0 # Average number of references to valid blocks.
|
||||
system.iocache.warmup_cycle 1750545944000 # Cycle when the warmup percentage was hit.
|
||||
system.iocache.occ_blocks::tsunami.ide 1.340325 # Average occupied blocks per requestor
|
||||
system.iocache.occ_percent::tsunami.ide 0.083770 # Average percentage of cache occupancy
|
||||
system.iocache.occ_percent::total 0.083770 # Average percentage of cache occupancy
|
||||
system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses
|
||||
system.iocache.ReadReq_misses::total 173 # number of ReadReq misses
|
||||
system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses
|
||||
system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses
|
||||
system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses
|
||||
system.iocache.demand_misses::total 41725 # number of demand (read+write) misses
|
||||
system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses
|
||||
system.iocache.overall_misses::total 41725 # number of overall misses
|
||||
system.iocache.ReadReq_miss_latency::tsunami.ide 19940998 # number of ReadReq miss cycles
|
||||
system.iocache.ReadReq_miss_latency::total 19940998 # number of ReadReq miss cycles
|
||||
system.iocache.WriteReq_miss_latency::tsunami.ide 5722300806 # number of WriteReq miss cycles
|
||||
system.iocache.WriteReq_miss_latency::total 5722300806 # number of WriteReq miss cycles
|
||||
system.iocache.demand_miss_latency::tsunami.ide 5742241804 # number of demand (read+write) miss cycles
|
||||
system.iocache.demand_miss_latency::total 5742241804 # number of demand (read+write) miss cycles
|
||||
system.iocache.overall_miss_latency::tsunami.ide 5742241804 # number of overall miss cycles
|
||||
system.iocache.overall_miss_latency::total 5742241804 # number of overall miss cycles
|
||||
system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses)
|
||||
system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses)
|
||||
system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses)
|
||||
system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses)
|
||||
system.iocache.demand_accesses::tsunami.ide 41725 # number of demand (read+write) accesses
|
||||
system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses
|
||||
system.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses
|
||||
system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses
|
||||
system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
|
||||
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
|
||||
system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses
|
||||
system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
|
||||
system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses
|
||||
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
|
||||
system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
|
||||
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
|
||||
system.iocache.ReadReq_avg_miss_latency::tsunami.ide 115265.884393 # average ReadReq miss latency
|
||||
system.iocache.ReadReq_avg_miss_latency::total 115265.884393 # average ReadReq miss latency
|
||||
system.iocache.WriteReq_avg_miss_latency::tsunami.ide 137714.208847 # average WriteReq miss latency
|
||||
system.iocache.WriteReq_avg_miss_latency::total 137714.208847 # average WriteReq miss latency
|
||||
system.iocache.demand_avg_miss_latency::tsunami.ide 137621.133709 # average overall miss latency
|
||||
system.iocache.demand_avg_miss_latency::total 137621.133709 # average overall miss latency
|
||||
system.iocache.overall_avg_miss_latency::tsunami.ide 137621.133709 # average overall miss latency
|
||||
system.iocache.overall_avg_miss_latency::total 137621.133709 # average overall miss latency
|
||||
system.iocache.blocked_cycles::no_mshrs 64604060 # number of cycles access was blocked
|
||||
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.iocache.blocked::no_mshrs 10476 # number of cycles access was blocked
|
||||
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.iocache.avg_blocked_cycles::no_mshrs 6166.863307 # average number of cycles each access was blocked
|
||||
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.iocache.fast_writes 0 # number of fast writes performed
|
||||
system.iocache.cache_copies 0 # number of cache copies performed
|
||||
system.iocache.writebacks::writebacks 41512 # number of writebacks
|
||||
system.iocache.writebacks::total 41512 # number of writebacks
|
||||
system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses
|
||||
system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses
|
||||
system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses
|
||||
system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses
|
||||
system.iocache.demand_mshr_misses::tsunami.ide 41725 # number of demand (read+write) MSHR misses
|
||||
system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses
|
||||
system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses
|
||||
system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses
|
||||
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 10944998 # number of ReadReq MSHR miss cycles
|
||||
system.iocache.ReadReq_mshr_miss_latency::total 10944998 # number of ReadReq MSHR miss cycles
|
||||
system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 3561447990 # number of WriteReq MSHR miss cycles
|
||||
system.iocache.WriteReq_mshr_miss_latency::total 3561447990 # number of WriteReq MSHR miss cycles
|
||||
system.iocache.demand_mshr_miss_latency::tsunami.ide 3572392988 # number of demand (read+write) MSHR miss cycles
|
||||
system.iocache.demand_mshr_miss_latency::total 3572392988 # number of demand (read+write) MSHR miss cycles
|
||||
system.iocache.overall_mshr_miss_latency::tsunami.ide 3572392988 # number of overall MSHR miss cycles
|
||||
system.iocache.overall_mshr_miss_latency::total 3572392988 # number of overall MSHR miss cycles
|
||||
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
|
||||
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
|
||||
system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses
|
||||
system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
|
||||
system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses
|
||||
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
|
||||
system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses
|
||||
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
|
||||
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 63265.884393 # average ReadReq mshr miss latency
|
||||
system.iocache.ReadReq_avg_mshr_miss_latency::total 63265.884393 # average ReadReq mshr miss latency
|
||||
system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 85710.627407 # average WriteReq mshr miss latency
|
||||
system.iocache.WriteReq_avg_mshr_miss_latency::total 85710.627407 # average WriteReq mshr miss latency
|
||||
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 85617.567118 # average overall mshr miss latency
|
||||
system.iocache.demand_avg_mshr_miss_latency::total 85617.567118 # average overall mshr miss latency
|
||||
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 85617.567118 # average overall mshr miss latency
|
||||
system.iocache.overall_avg_mshr_miss_latency::total 85617.567118 # average overall mshr miss latency
|
||||
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
||||
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
|
||||
system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
|
||||
system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
|
||||
system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
|
||||
system.disk0.dma_write_txs 395 # Number of DMA write transactions.
|
||||
system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
||||
system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
|
||||
system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
|
||||
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
|
||||
system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
|
||||
system.disk2.dma_write_txs 1 # Number of DMA write transactions.
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
||||
system.cpu.dtb.read_hits 9057511 # DTB read hits
|
||||
system.cpu.dtb.read_misses 10312 # DTB read misses
|
||||
system.cpu.dtb.read_acv 210 # DTB read access violations
|
||||
system.cpu.dtb.read_accesses 728817 # DTB read accesses
|
||||
system.cpu.dtb.write_hits 6352446 # DTB write hits
|
||||
system.cpu.dtb.write_misses 1140 # DTB write misses
|
||||
system.cpu.dtb.write_acv 157 # DTB write access violations
|
||||
system.cpu.dtb.write_accesses 291929 # DTB write accesses
|
||||
system.cpu.dtb.data_hits 15409957 # DTB hits
|
||||
system.cpu.dtb.data_misses 11452 # DTB misses
|
||||
system.cpu.dtb.data_acv 367 # DTB access violations
|
||||
system.cpu.dtb.data_accesses 1020746 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 4973520 # ITB hits
|
||||
system.cpu.itb.fetch_misses 4997 # ITB misses
|
||||
system.cpu.itb.fetch_acv 184 # ITB acv
|
||||
system.cpu.itb.fetch_accesses 4978517 # ITB accesses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.itb.write_hits 0 # DTB write hits
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.itb.write_acv 0 # DTB write access violations
|
||||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.itb.data_hits 0 # DTB hits
|
||||
system.cpu.itb.data_misses 0 # DTB misses
|
||||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.numCycles 3831097734 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 56137087 # Number of instructions committed
|
||||
system.cpu.committedOps 56137087 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 52011214 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 324192 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 1482242 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 6464616 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 52011214 # number of integer instructions
|
||||
system.cpu.num_fp_insts 324192 # number of float instructions
|
||||
system.cpu.num_int_register_reads 71259077 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 38485860 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 163510 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 166384 # number of times the floating registers were written
|
||||
system.cpu.num_mem_refs 15462519 # number of memory refs
|
||||
system.cpu.num_load_insts 9094324 # Number of load instructions
|
||||
system.cpu.num_store_insts 6368195 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 3587943187.998127 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 243154546.001873 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 0.063469 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0.936531 # Percentage of idle cycles
|
||||
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
||||
system.cpu.kern.inst.quiesce 6379 # number of quiesce instructions executed
|
||||
system.cpu.kern.inst.hwrei 211932 # number of hwrei instructions executed
|
||||
system.cpu.kern.ipl_count::0 74887 40.89% 40.89% # number of times we switched to this ipl
|
||||
system.cpu.kern.ipl_count::21 131 0.07% 40.96% # number of times we switched to this ipl
|
||||
system.cpu.kern.ipl_count::22 1931 1.05% 42.02% # number of times we switched to this ipl
|
||||
system.cpu.kern.ipl_count::31 106197 57.98% 100.00% # number of times we switched to this ipl
|
||||
system.cpu.kern.ipl_count::total 183146 # number of times we switched to this ipl
|
||||
system.cpu.kern.ipl_good::0 73520 49.31% 49.31% # number of times we switched to this ipl from a different ipl
|
||||
system.cpu.kern.ipl_good::21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl
|
||||
system.cpu.kern.ipl_good::22 1931 1.30% 50.69% # number of times we switched to this ipl from a different ipl
|
||||
system.cpu.kern.ipl_good::31 73520 49.31% 100.00% # number of times we switched to this ipl from a different ipl
|
||||
system.cpu.kern.ipl_good::total 149102 # number of times we switched to this ipl from a different ipl
|
||||
system.cpu.kern.ipl_ticks::0 1857816228500 96.99% 96.99% # number of cycles we spent at this ipl
|
||||
system.cpu.kern.ipl_ticks::21 79988500 0.00% 96.99% # number of cycles we spent at this ipl
|
||||
system.cpu.kern.ipl_ticks::22 554693000 0.03% 97.02% # number of cycles we spent at this ipl
|
||||
system.cpu.kern.ipl_ticks::31 57097199000 2.98% 100.00% # number of cycles we spent at this ipl
|
||||
system.cpu.kern.ipl_ticks::total 1915548109000 # number of cycles we spent at this ipl
|
||||
system.cpu.kern.ipl_used::0 0.981746 # fraction of swpipl calls that actually changed the ipl
|
||||
system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
|
||||
system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
|
||||
system.cpu.kern.ipl_used::31 0.692298 # fraction of swpipl calls that actually changed the ipl
|
||||
system.cpu.kern.ipl_used::total 0.814116 # fraction of swpipl calls that actually changed the ipl
|
||||
system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed
|
||||
system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed
|
||||
system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed
|
||||
system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed
|
||||
system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed
|
||||
system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed
|
||||
system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed
|
||||
system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed
|
||||
system.cpu.kern.syscall::20 6 1.84% 35.89% # number of syscalls executed
|
||||
system.cpu.kern.syscall::23 4 1.23% 37.12% # number of syscalls executed
|
||||
system.cpu.kern.syscall::24 6 1.84% 38.96% # number of syscalls executed
|
||||
system.cpu.kern.syscall::33 11 3.37% 42.33% # number of syscalls executed
|
||||
system.cpu.kern.syscall::41 2 0.61% 42.94% # number of syscalls executed
|
||||
system.cpu.kern.syscall::45 54 16.56% 59.51% # number of syscalls executed
|
||||
system.cpu.kern.syscall::47 6 1.84% 61.35% # number of syscalls executed
|
||||
system.cpu.kern.syscall::48 10 3.07% 64.42% # number of syscalls executed
|
||||
system.cpu.kern.syscall::54 10 3.07% 67.48% # number of syscalls executed
|
||||
system.cpu.kern.syscall::58 1 0.31% 67.79% # number of syscalls executed
|
||||
system.cpu.kern.syscall::59 7 2.15% 69.94% # number of syscalls executed
|
||||
system.cpu.kern.syscall::71 54 16.56% 86.50% # number of syscalls executed
|
||||
system.cpu.kern.syscall::73 3 0.92% 87.42% # number of syscalls executed
|
||||
system.cpu.kern.syscall::74 16 4.91% 92.33% # number of syscalls executed
|
||||
system.cpu.kern.syscall::87 1 0.31% 92.64% # number of syscalls executed
|
||||
system.cpu.kern.syscall::90 3 0.92% 93.56% # number of syscalls executed
|
||||
system.cpu.kern.syscall::92 9 2.76% 96.32% # number of syscalls executed
|
||||
system.cpu.kern.syscall::97 2 0.61% 96.93% # number of syscalls executed
|
||||
system.cpu.kern.syscall::98 2 0.61% 97.55% # number of syscalls executed
|
||||
system.cpu.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed
|
||||
system.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed
|
||||
system.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed
|
||||
system.cpu.kern.syscall::total 326 # number of syscalls executed
|
||||
system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
|
||||
system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed
|
||||
system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed
|
||||
system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed
|
||||
system.cpu.kern.callpal::swpctx 4173 2.16% 2.17% # number of callpals executed
|
||||
system.cpu.kern.callpal::tbi 54 0.03% 2.19% # number of callpals executed
|
||||
system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed
|
||||
system.cpu.kern.callpal::swpipl 175927 91.22% 93.41% # number of callpals executed
|
||||
system.cpu.kern.callpal::rdps 6832 3.54% 96.96% # number of callpals executed
|
||||
system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed
|
||||
system.cpu.kern.callpal::wrusp 7 0.00% 96.96% # number of callpals executed
|
||||
system.cpu.kern.callpal::rdusp 9 0.00% 96.96% # number of callpals executed
|
||||
system.cpu.kern.callpal::whami 2 0.00% 96.97% # number of callpals executed
|
||||
system.cpu.kern.callpal::rti 5156 2.67% 99.64% # number of callpals executed
|
||||
system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed
|
||||
system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed
|
||||
system.cpu.kern.callpal::total 192868 # number of callpals executed
|
||||
system.cpu.kern.mode_switch::kernel 5903 # number of protection mode switches
|
||||
system.cpu.kern.mode_switch::user 1738 # number of protection mode switches
|
||||
system.cpu.kern.mode_switch::idle 2092 # number of protection mode switches
|
||||
system.cpu.kern.mode_good::kernel 1906
|
||||
system.cpu.kern.mode_good::user 1738
|
||||
system.cpu.kern.mode_good::idle 168
|
||||
system.cpu.kern.mode_switch_good::kernel 0.322887 # fraction of useful protection mode switches
|
||||
system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
|
||||
system.cpu.kern.mode_switch_good::idle 0.080306 # fraction of useful protection mode switches
|
||||
system.cpu.kern.mode_switch_good::total 0.391657 # fraction of useful protection mode switches
|
||||
system.cpu.kern.mode_ticks::kernel 45253274000 2.36% 2.36% # number of ticks spent at the given mode
|
||||
system.cpu.kern.mode_ticks::user 5124228000 0.27% 2.63% # number of ticks spent at the given mode
|
||||
system.cpu.kern.mode_ticks::idle 1865170605000 97.37% 100.00% # number of ticks spent at the given mode
|
||||
system.cpu.kern.swap_context 4174 # number of times the context was actually changed
|
||||
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
|
||||
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
|
||||
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
|
||||
system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
|
||||
system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
|
||||
system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
|
||||
system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
|
||||
system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
|
||||
system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
|
||||
system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
|
||||
system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
|
||||
system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
|
||||
system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
|
||||
system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
|
||||
system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
|
||||
system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
|
||||
system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
|
||||
system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
|
||||
system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
|
||||
system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
|
||||
system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
|
||||
system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
|
||||
system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
|
||||
system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
|
||||
system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
|
||||
system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
|
||||
system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
|
||||
system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
|
||||
system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
|
||||
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
|
||||
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
|
||||
system.cpu.icache.replacements 927683 # number of replacements
|
||||
system.cpu.icache.tagsinuse 508.721464 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 55220553 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 928194 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 59.492469 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 36307428000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 508.721464 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.993597 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.993597 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 55220553 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 55220553 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 55220553 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 55220553 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 55220553 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 55220553 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 928354 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 928354 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 928354 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 928354 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 928354 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 928354 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 13616370500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 13616370500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 13616370500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 13616370500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 13616370500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 13616370500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 56148907 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 56148907 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 56148907 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 56148907 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 56148907 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 56148907 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016534 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.016534 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.016534 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.016534 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.016534 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.016534 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14667.218001 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 14667.218001 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 14667.218001 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 14667.218001 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 14667.218001 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 14667.218001 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks::writebacks 85 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 85 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 928354 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 928354 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 928354 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 928354 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 928354 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 928354 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10830625500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 10830625500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10830625500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 10830625500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10830625500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 10830625500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016534 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016534 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016534 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.016534 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016534 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.016534 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11666.482290 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11666.482290 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11666.482290 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 11666.482290 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11666.482290 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 11666.482290 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 1390115 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 511.984023 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 14038335 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 1390627 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 10.094968 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 84029000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 511.984023 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.999969 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.999969 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 7807536 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 7807536 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 5848554 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 5848554 # number of WriteReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::cpu.data 183025 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::total 183025 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::cpu.data 199203 # number of StoreCondReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::total 199203 # number of StoreCondReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 13656090 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 13656090 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 13656090 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 13656090 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 1069110 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 1069110 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 304335 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 304335 # number of WriteReq misses
|
||||
system.cpu.dcache.LoadLockedReq_misses::cpu.data 17201 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.LoadLockedReq_misses::total 17201 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 1373445 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 1373445 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 1373445 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 1373445 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 27121920500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 27121920500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 9228484000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 9228484000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 245980000 # number of LoadLockedReq miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_miss_latency::total 245980000 # number of LoadLockedReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 36350404500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 36350404500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 36350404500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 36350404500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 8876646 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 8876646 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 6152889 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 6152889 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200226 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::total 200226 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::cpu.data 199203 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::total 199203 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 15029535 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 15029535 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 15029535 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 15029535 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120441 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.120441 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049462 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.049462 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085908 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.085908 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.091383 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.091383 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.091383 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.091383 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 25368.690313 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 25368.690313 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30323.439631 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 30323.439631 # average WriteReq miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14300.331376 # average LoadLockedReq miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14300.331376 # average LoadLockedReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 26466.589124 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 26466.589124 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 26466.589124 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 26466.589124 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 826586 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 826586 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069110 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 1069110 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304335 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 304335 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17201 # number of LoadLockedReq MSHR misses
|
||||
system.cpu.dcache.LoadLockedReq_mshr_misses::total 17201 # number of LoadLockedReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 1373445 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 1373445 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 1373445 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 1373445 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23914545000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 23914545000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8315479000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 8315479000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 194377000 # number of LoadLockedReq MSHR miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 194377000 # number of LoadLockedReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 32230024000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 32230024000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 32230024000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 32230024000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 862763000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 862763000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1199607500 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1199607500 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 2062370500 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency::total 2062370500 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120441 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120441 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049462 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049462 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.085908 # mshr miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.085908 # mshr miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091383 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.091383 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091383 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.091383 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22368.647754 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22368.647754 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27323.439631 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27323.439631 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11300.331376 # average LoadLockedReq mshr miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11300.331376 # average LoadLockedReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23466.555996 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 23466.555996 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23466.555996 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 23466.555996 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
@ -0,0 +1,108 @@
|
||||
M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
|
||||
|
||||
Got Configuration 623
|
||||
|
||||
memsize 8000000 pages 4000
|
||||
|
||||
First free page after ROM 0xFFFFFC0000018000
|
||||
|
||||
HWRPB 0xFFFFFC0000018000 l1pt 0xFFFFFC0000040000 l2pt 0xFFFFFC0000042000 l3pt_rpb 0xFFFFFC0000044000 l3pt_kernel 0xFFFFFC0000048000 l2reserv 0xFFFFFC0000046000
|
||||
|
||||
kstart = 0xFFFFFC0000310000, kend = 0xFFFFFC0000855898, kentry = 0xFFFFFC0000310000, numCPUs = 0x1
|
||||
|
||||
CPU Clock at 2000 MHz IntrClockFrequency=1024
|
||||
|
||||
Booting with 1 processor(s)
|
||||
|
||||
KSP: 0x20043FE8 PTBR 0x20
|
||||
|
||||
Console Callback at 0x0, fixup at 0x0, crb offset: 0x510
|
||||
|
||||
Memory cluster 0 [0 - 392]
|
||||
|
||||
Memory cluster 1 [392 - 15992]
|
||||
|
||||
Initalizing mdt_bitmap addr 0xFFFFFC0000038000 mem_pages 4000
|
||||
|
||||
ConsoleDispatch at virt 10000658 phys 18658 val FFFFFC00000100A8
|
||||
|
||||
unix_boot_mem ends at FFFFFC0000076000
|
||||
|
||||
k_argc = 0
|
||||
|
||||
jumping to kernel at 0xFFFFFC0000310000, (PCBB 0xFFFFFC0000018180 pfn 1067)
|
||||
|
||||
CallbackFixup 0 18000, t7=FFFFFC000070C000
|
||||
|
||||
Linux version 2.6.13 (hsul@zed.eecs.umich.edu) (gcc version 3.4.3) #1 SMP Sun Oct 8 19:52:07 EDT 2006
|
||||
|
||||
Booting GENERIC on Tsunami variation DP264 using machine vector DP264 from SRM
|
||||
|
||||
Major Options: SMP LEGACY_START VERBOSE_MCHECK
|
||||
|
||||
Command line: root=/dev/hda1 console=ttyS0
|
||||
|
||||
memcluster 0, usage 1, start 0, end 392
|
||||
|
||||
memcluster 1, usage 0, start 392, end 16384
|
||||
|
||||
freeing pages 1069:16384
|
||||
|
||||
reserving pages 1069:1070
|
||||
|
||||
4096K Bcache detected; load hit latency 40 cycles, load miss latency 124 cycles
|
||||
|
||||
SMP: 1 CPUs probed -- cpu_present_mask = 1
|
||||
|
||||
Built 1 zonelists
|
||||
|
||||
Kernel command line: root=/dev/hda1 console=ttyS0
|
||||
|
||||
PID hash table entries: 1024 (order: 10, 32768 bytes)
|
||||
|
||||
Using epoch = 1900
|
||||
|
||||
Console: colour dummy device 80x25
|
||||
|
||||
Dentry cache hash table entries: 32768 (order: 5, 262144 bytes)
|
||||
|
||||
Inode-cache hash table entries: 16384 (order: 4, 131072 bytes)
|
||||
|
||||
Memory: 118784k/131072k available (3314k kernel code, 8952k reserved, 983k data, 224k init)
|
||||
|
||||
Mount-cache hash table entries: 512
|
||||
|
||||
SMP mode deactivated.
|
||||
|
||||
Brought up 1 CPUs
|
||||
|
||||
SMP: Total of 1 processors activated (4002.20 BogoMIPS).
|
||||
|
||||
NET: Registered protocol family 16
|
||||
|
||||
EISA bus registered
|
||||
|
||||
pci: enabling save/restore of SRM state
|
||||
|
||||
SCSI subsystem initialized
|
||||
|
||||
srm_env: version 0.0.5 loaded successfully
|
||||
|
||||
Installing knfsd (copyright (C) 1996 okir@monad.swb.de).
|
||||
|
||||
Initializing Cryptographic API
|
||||
|
||||
rtc: Standard PC (1900) epoch (1900) detected
|
||||
|
||||
Real Time Clock Driver v1.12
|
||||
|
||||
Serial: 8250/16550 driver $Revision: 1.90 $ 1 ports, IRQ sharing disabled
|
||||
|
||||
ttyS0 at I/O 0x3f8 (irq = 4) is a 8250
|
||||
|
||||
io scheduler noop registered
|
||||
|
||||
io scheduler anticipatory registered
|
||||
|
||||
io scheduler deadline registered
|
||||
|
||||
@ -0,0 +1,791 @@
|
||||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
full_system=true
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
||||
[system]
|
||||
type=LinuxArmSystem
|
||||
children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver
|
||||
atags_addr=256
|
||||
boot_loader=/dist/m5/system/binaries/boot.arm
|
||||
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
|
||||
early_kernel_symbols=false
|
||||
flags_addr=268435504
|
||||
gic_cpu_addr=520093952
|
||||
init_param=0
|
||||
kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
|
||||
load_addr_mask=268435455
|
||||
machine_type=RealView_PBX
|
||||
mem_mode=atomic
|
||||
memories=system.realview.nvmem system.physmem
|
||||
midr_regval=890224640
|
||||
num_work_ids=16
|
||||
readfile=tests/halt.sh
|
||||
symbolfile=
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.membus.slave[0]
|
||||
|
||||
[system.bridge]
|
||||
type=Bridge
|
||||
delay=50000
|
||||
nack_delay=4000
|
||||
ranges=268435456:520093695 1073741824:1610612735
|
||||
req_size=16
|
||||
resp_size=16
|
||||
write_ack=false
|
||||
master=system.iobus.slave[0]
|
||||
slave=system.membus.master[0]
|
||||
|
||||
[system.cf0]
|
||||
type=IdeDisk
|
||||
children=image
|
||||
delay=1000000
|
||||
driveID=master
|
||||
image=system.cf0.image
|
||||
|
||||
[system.cf0.image]
|
||||
type=CowDiskImage
|
||||
children=child
|
||||
child=system.cf0.image.child
|
||||
image_file=
|
||||
read_only=false
|
||||
table_size=65536
|
||||
|
||||
[system.cf0.image.child]
|
||||
type=RawDiskImage
|
||||
image_file=/dist/m5/system/disks/linux-arm-ael.img
|
||||
read_only=true
|
||||
|
||||
[system.cpu0]
|
||||
type=AtomicSimpleCPU
|
||||
children=dcache dtb icache interrupts itb tracer
|
||||
checker=Null
|
||||
clock=500
|
||||
cpu_id=0
|
||||
defer_registration=false
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu0.dtb
|
||||
fastmem=false
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
interrupts=system.cpu0.interrupts
|
||||
itb=system.cpu0.itb
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
phase=0
|
||||
profile=0
|
||||
progress_interval=0
|
||||
simulate_data_stalls=false
|
||||
simulate_inst_stalls=false
|
||||
system=system
|
||||
tracer=system.cpu0.tracer
|
||||
width=1
|
||||
workload=
|
||||
dcache_port=system.cpu0.dcache.cpu_side
|
||||
icache_port=system.cpu0.icache.cpu_side
|
||||
|
||||
[system.cpu0.dcache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=4
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=32768
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=8
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu0.dcache_port
|
||||
mem_side=system.toL2Bus.slave[1]
|
||||
|
||||
[system.cpu0.dtb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
size=64
|
||||
walker=system.cpu0.dtb.walker
|
||||
|
||||
[system.cpu0.dtb.walker]
|
||||
type=ArmTableWalker
|
||||
max_backoff=100000
|
||||
min_backoff=0
|
||||
sys=system
|
||||
port=system.toL2Bus.slave[3]
|
||||
|
||||
[system.cpu0.icache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=1
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=32768
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=8
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu0.icache_port
|
||||
mem_side=system.toL2Bus.slave[0]
|
||||
|
||||
[system.cpu0.interrupts]
|
||||
type=ArmInterrupts
|
||||
|
||||
[system.cpu0.itb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
size=64
|
||||
walker=system.cpu0.itb.walker
|
||||
|
||||
[system.cpu0.itb.walker]
|
||||
type=ArmTableWalker
|
||||
max_backoff=100000
|
||||
min_backoff=0
|
||||
sys=system
|
||||
port=system.toL2Bus.slave[2]
|
||||
|
||||
[system.cpu0.tracer]
|
||||
type=ExeTracer
|
||||
|
||||
[system.cpu1]
|
||||
type=AtomicSimpleCPU
|
||||
children=dcache dtb icache interrupts itb tracer
|
||||
checker=Null
|
||||
clock=500
|
||||
cpu_id=1
|
||||
defer_registration=false
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu1.dtb
|
||||
fastmem=false
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
interrupts=system.cpu1.interrupts
|
||||
itb=system.cpu1.itb
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
phase=0
|
||||
profile=0
|
||||
progress_interval=0
|
||||
simulate_data_stalls=false
|
||||
simulate_inst_stalls=false
|
||||
system=system
|
||||
tracer=system.cpu1.tracer
|
||||
width=1
|
||||
workload=
|
||||
dcache_port=system.cpu1.dcache.cpu_side
|
||||
icache_port=system.cpu1.icache.cpu_side
|
||||
|
||||
[system.cpu1.dcache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=4
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=32768
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=8
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu1.dcache_port
|
||||
mem_side=system.toL2Bus.slave[5]
|
||||
|
||||
[system.cpu1.dtb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
size=64
|
||||
walker=system.cpu1.dtb.walker
|
||||
|
||||
[system.cpu1.dtb.walker]
|
||||
type=ArmTableWalker
|
||||
max_backoff=100000
|
||||
min_backoff=0
|
||||
sys=system
|
||||
port=system.toL2Bus.slave[7]
|
||||
|
||||
[system.cpu1.icache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=1
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=32768
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=8
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu1.icache_port
|
||||
mem_side=system.toL2Bus.slave[4]
|
||||
|
||||
[system.cpu1.interrupts]
|
||||
type=ArmInterrupts
|
||||
|
||||
[system.cpu1.itb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
size=64
|
||||
walker=system.cpu1.itb.walker
|
||||
|
||||
[system.cpu1.itb.walker]
|
||||
type=ArmTableWalker
|
||||
max_backoff=100000
|
||||
min_backoff=0
|
||||
sys=system
|
||||
port=system.toL2Bus.slave[6]
|
||||
|
||||
[system.cpu1.tracer]
|
||||
type=ExeTracer
|
||||
|
||||
[system.intrctrl]
|
||||
type=IntrControl
|
||||
sys=system
|
||||
|
||||
[system.iobus]
|
||||
type=NoncoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side
|
||||
slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
|
||||
|
||||
[system.iocache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:268435455
|
||||
assoc=8
|
||||
block_size=64
|
||||
forward_snoops=false
|
||||
hash_delay=1
|
||||
is_top_level=false
|
||||
latency=50000
|
||||
max_miss_count=0
|
||||
mshrs=20
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=1024
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=12
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.iobus.master[25]
|
||||
mem_side=system.membus.slave[1]
|
||||
|
||||
[system.l2c]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=8
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=false
|
||||
latency=10000
|
||||
max_miss_count=0
|
||||
mshrs=92
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=4194304
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=16
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.toL2Bus.master[0]
|
||||
mem_side=system.membus.slave[2]
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
children=badaddr_responder
|
||||
block_size=64
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
default=system.membus.badaddr_responder.pio
|
||||
master=system.bridge.slave system.realview.nvmem.port[0] system.physmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio
|
||||
slave=system.system_port system.iocache.mem_side system.l2c.mem_side
|
||||
|
||||
[system.membus.badaddr_responder]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=0
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=true
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=warn
|
||||
pio=system.membus.default
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
conf_table_reported=true
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.membus.master[2]
|
||||
|
||||
[system.realview]
|
||||
type=RealView
|
||||
children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
|
||||
intrctrl=system.intrctrl
|
||||
max_mem_size=268435456
|
||||
mem_start_addr=0
|
||||
pci_cfg_base=0
|
||||
system=system
|
||||
|
||||
[system.realview.a9scu]
|
||||
type=A9SCU
|
||||
pio_addr=520093696
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.membus.master[5]
|
||||
|
||||
[system.realview.aaci_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
ignore_access=false
|
||||
pio_addr=268451840
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.iobus.master[21]
|
||||
|
||||
[system.realview.cf_ctrl]
|
||||
type=IdeController
|
||||
BAR0=402653184
|
||||
BAR0LegacyIO=true
|
||||
BAR0Size=16
|
||||
BAR1=402653440
|
||||
BAR1LegacyIO=true
|
||||
BAR1Size=1
|
||||
BAR2=1
|
||||
BAR2LegacyIO=false
|
||||
BAR2Size=8
|
||||
BAR3=1
|
||||
BAR3LegacyIO=false
|
||||
BAR3Size=4
|
||||
BAR4=1
|
||||
BAR4LegacyIO=false
|
||||
BAR4Size=16
|
||||
BAR5=1
|
||||
BAR5LegacyIO=false
|
||||
BAR5Size=0
|
||||
BIST=0
|
||||
CacheLineSize=0
|
||||
CardbusCIS=0
|
||||
ClassCode=1
|
||||
Command=1
|
||||
DeviceID=28945
|
||||
ExpansionROM=0
|
||||
HeaderType=0
|
||||
InterruptLine=31
|
||||
InterruptPin=1
|
||||
LatencyTimer=0
|
||||
MaximumLatency=0
|
||||
MinimumGrant=0
|
||||
ProgIF=133
|
||||
Revision=0
|
||||
Status=640
|
||||
SubClassCode=1
|
||||
SubsystemID=0
|
||||
SubsystemVendorID=0
|
||||
VendorID=32902
|
||||
config_latency=20000
|
||||
ctrl_offset=2
|
||||
disks=system.cf0
|
||||
io_shift=1
|
||||
max_backoff_delay=10000000
|
||||
min_backoff_delay=4000
|
||||
pci_bus=2
|
||||
pci_dev=7
|
||||
pci_func=0
|
||||
pio_latency=1000
|
||||
platform=system.realview
|
||||
system=system
|
||||
config=system.iobus.master[8]
|
||||
dma=system.iobus.slave[2]
|
||||
pio=system.iobus.master[7]
|
||||
|
||||
[system.realview.clcd]
|
||||
type=Pl111
|
||||
amba_id=1315089
|
||||
clock=41667
|
||||
gic=system.realview.gic
|
||||
int_num=55
|
||||
max_backoff_delay=10000000
|
||||
min_backoff_delay=4000
|
||||
pio_addr=268566528
|
||||
pio_latency=10000
|
||||
system=system
|
||||
vnc=system.vncserver
|
||||
dma=system.iobus.slave[1]
|
||||
pio=system.iobus.master[4]
|
||||
|
||||
[system.realview.dmac_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
ignore_access=false
|
||||
pio_addr=268632064
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.iobus.master[9]
|
||||
|
||||
[system.realview.flash_fake]
|
||||
type=IsaFake
|
||||
fake_mem=true
|
||||
pio_addr=1073741824
|
||||
pio_latency=1000
|
||||
pio_size=536870912
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[24]
|
||||
|
||||
[system.realview.gic]
|
||||
type=Gic
|
||||
cpu_addr=520093952
|
||||
cpu_pio_delay=10000
|
||||
dist_addr=520097792
|
||||
dist_pio_delay=10000
|
||||
int_latency=10000
|
||||
it_lines=128
|
||||
platform=system.realview
|
||||
system=system
|
||||
pio=system.membus.master[3]
|
||||
|
||||
[system.realview.gpio0_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
ignore_access=false
|
||||
pio_addr=268513280
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.iobus.master[16]
|
||||
|
||||
[system.realview.gpio1_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
ignore_access=false
|
||||
pio_addr=268517376
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.iobus.master[17]
|
||||
|
||||
[system.realview.gpio2_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
ignore_access=false
|
||||
pio_addr=268521472
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.iobus.master[18]
|
||||
|
||||
[system.realview.kmi0]
|
||||
type=Pl050
|
||||
amba_id=1314896
|
||||
gic=system.realview.gic
|
||||
int_delay=1000000
|
||||
int_num=52
|
||||
is_mouse=false
|
||||
pio_addr=268460032
|
||||
pio_latency=1000
|
||||
system=system
|
||||
vnc=system.vncserver
|
||||
pio=system.iobus.master[5]
|
||||
|
||||
[system.realview.kmi1]
|
||||
type=Pl050
|
||||
amba_id=1314896
|
||||
gic=system.realview.gic
|
||||
int_delay=1000000
|
||||
int_num=53
|
||||
is_mouse=true
|
||||
pio_addr=268464128
|
||||
pio_latency=1000
|
||||
system=system
|
||||
vnc=system.vncserver
|
||||
pio=system.iobus.master[6]
|
||||
|
||||
[system.realview.l2x0_fake]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=520101888
|
||||
pio_latency=1000
|
||||
pio_size=4095
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.membus.master[4]
|
||||
|
||||
[system.realview.local_cpu_timer]
|
||||
type=CpuLocalTimer
|
||||
clock=1000
|
||||
gic=system.realview.gic
|
||||
int_num_timer=29
|
||||
int_num_watchdog=30
|
||||
pio_addr=520095232
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.membus.master[6]
|
||||
|
||||
[system.realview.mmc_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
ignore_access=false
|
||||
pio_addr=268455936
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.iobus.master[22]
|
||||
|
||||
[system.realview.nvmem]
|
||||
type=SimpleMemory
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
range=2147483648:2214592511
|
||||
zero=true
|
||||
port=system.membus.master[1]
|
||||
|
||||
[system.realview.realview_io]
|
||||
type=RealViewCtrl
|
||||
idreg=0
|
||||
pio_addr=268435456
|
||||
pio_latency=1000
|
||||
proc_id0=201326592
|
||||
proc_id1=201327138
|
||||
system=system
|
||||
pio=system.iobus.master[1]
|
||||
|
||||
[system.realview.rtc]
|
||||
type=PL031
|
||||
amba_id=3412017
|
||||
gic=system.realview.gic
|
||||
int_delay=100000
|
||||
int_num=42
|
||||
pio_addr=268529664
|
||||
pio_latency=1000
|
||||
system=system
|
||||
time=Thu Jan 1 00:00:00 2009
|
||||
pio=system.iobus.master[23]
|
||||
|
||||
[system.realview.sci_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
ignore_access=false
|
||||
pio_addr=268492800
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.iobus.master[20]
|
||||
|
||||
[system.realview.smc_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
ignore_access=false
|
||||
pio_addr=269357056
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.iobus.master[13]
|
||||
|
||||
[system.realview.sp810_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
ignore_access=true
|
||||
pio_addr=268439552
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.iobus.master[14]
|
||||
|
||||
[system.realview.ssp_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
ignore_access=false
|
||||
pio_addr=268488704
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.iobus.master[19]
|
||||
|
||||
[system.realview.timer0]
|
||||
type=Sp804
|
||||
amba_id=1316868
|
||||
clock0=1000000
|
||||
clock1=1000000
|
||||
gic=system.realview.gic
|
||||
int_num0=36
|
||||
int_num1=36
|
||||
pio_addr=268505088
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.iobus.master[2]
|
||||
|
||||
[system.realview.timer1]
|
||||
type=Sp804
|
||||
amba_id=1316868
|
||||
clock0=1000000
|
||||
clock1=1000000
|
||||
gic=system.realview.gic
|
||||
int_num0=37
|
||||
int_num1=37
|
||||
pio_addr=268509184
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.iobus.master[3]
|
||||
|
||||
[system.realview.uart]
|
||||
type=Pl011
|
||||
end_on_eot=false
|
||||
gic=system.realview.gic
|
||||
int_delay=100000
|
||||
int_num=44
|
||||
pio_addr=268472320
|
||||
pio_latency=1000
|
||||
platform=system.realview
|
||||
system=system
|
||||
terminal=system.terminal
|
||||
pio=system.iobus.master[0]
|
||||
|
||||
[system.realview.uart1_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
ignore_access=false
|
||||
pio_addr=268476416
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.iobus.master[10]
|
||||
|
||||
[system.realview.uart2_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
ignore_access=false
|
||||
pio_addr=268480512
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.iobus.master[11]
|
||||
|
||||
[system.realview.uart3_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
ignore_access=false
|
||||
pio_addr=268484608
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.iobus.master[12]
|
||||
|
||||
[system.realview.watchdog_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
ignore_access=false
|
||||
pio_addr=268500992
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.iobus.master[15]
|
||||
|
||||
[system.terminal]
|
||||
type=Terminal
|
||||
intr_control=system.intrctrl
|
||||
number=0
|
||||
output=true
|
||||
port=3456
|
||||
|
||||
[system.toL2Bus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
master=system.l2c.cpu_side
|
||||
slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port
|
||||
|
||||
[system.vncserver]
|
||||
type=VncServer
|
||||
frame_capture=false
|
||||
number=0
|
||||
port=5900
|
||||
|
||||
@ -0,0 +1,18 @@
|
||||
warn: Sockets disabled, not accepting vnc client connections
|
||||
warn: Sockets disabled, not accepting terminal connections
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: The clidr register always reports 0 caches.
|
||||
warn: clidr LoUIS field of 0b001 to match current ARM implementations.
|
||||
warn: The csselr register isn't implemented.
|
||||
warn: The ccsidr register isn't implemented and always reads as 0.
|
||||
warn: instruction 'mcr bpiallis' unimplemented
|
||||
warn: instruction 'mcr icialluis' unimplemented
|
||||
warn: instruction 'mcr dccimvac' unimplemented
|
||||
warn: instruction 'mcr dccmvau' unimplemented
|
||||
warn: instruction 'mcr icimvau' unimplemented
|
||||
warn: instruction 'mcr bpiallis' unimplemented
|
||||
warn: LCD dual screen mode not supported
|
||||
warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
|
||||
warn: instruction 'mcr icialluis' unimplemented
|
||||
warn: instruction 'mcr icialluis' unimplemented
|
||||
hack: be nice to actually delete the event here
|
||||
@ -0,0 +1,12 @@
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jun 4 2012 12:14:06
|
||||
gem5 started Jun 4 2012 17:25:17
|
||||
gem5 executing on zizzer
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
|
||||
info: Using bootloader at address 0x80000000
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 911653589000 because m5_exit instruction encountered
|
||||
@ -0,0 +1,653 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.911654 # Number of seconds simulated
|
||||
sim_ticks 911653589000 # Number of ticks simulated
|
||||
final_tick 911653589000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1520101 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1964640 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 22862175544 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 382804 # Number of bytes of host memory used
|
||||
host_seconds 39.88 # Real time elapsed on the host
|
||||
sim_insts 60615585 # Number of instructions simulated
|
||||
sim_ops 78342060 # Number of ops (including micro ops) simulated
|
||||
system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
|
||||
system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory
|
||||
system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory
|
||||
system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
|
||||
system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory
|
||||
system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory
|
||||
system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory
|
||||
system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory
|
||||
system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory
|
||||
system.realview.nvmem.bw_read::cpu0.inst 22 # Total read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_read::cpu1.inst 53 # Total read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_read::total 75 # Total read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_inst_read::cpu0.inst 22 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_inst_read::cpu1.inst 53 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_inst_read::total 75 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_total::cpu0.inst 22 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_total::cpu1.inst 53 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_total::total 75 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bytes_read::realview.clcd 39321600 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu0.dtb.walker 768 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu0.itb.walker 512 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu0.inst 661924 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu0.data 6760756 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu1.dtb.walker 1024 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu1.itb.walker 1152 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu1.inst 341852 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu1.data 3873968 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 50963556 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu0.inst 661924 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu1.inst 341852 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 1003776 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 7197696 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::cpu1.data 3010088 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 10224784 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::realview.clcd 4915200 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu0.dtb.walker 12 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu0.itb.walker 8 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu0.inst 16561 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu0.data 105709 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu1.dtb.walker 16 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu1.itb.walker 18 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu1.inst 5423 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu1.data 60557 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 5103504 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 112464 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::cpu1.data 752522 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 869236 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::realview.clcd 43132173 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu0.dtb.walker 842 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu0.itb.walker 562 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu0.inst 726070 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu0.data 7415926 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu1.dtb.walker 1123 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu1.itb.walker 1264 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu1.inst 374980 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu1.data 4249386 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 55902326 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu0.inst 726070 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu1.inst 374980 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 1101050 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 7895209 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::cpu0.data 18647 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::cpu1.data 3301789 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 11215646 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 7895209 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::realview.clcd 43132173 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu0.dtb.walker 842 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu0.itb.walker 562 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu0.inst 726070 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu0.data 7434574 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu1.dtb.walker 1123 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu1.itb.walker 1264 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu1.inst 374980 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu1.data 7551175 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 67117972 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.l2c.replacements 127935 # number of replacements
|
||||
system.l2c.tagsinuse 26245.835103 # Cycle average of tags in use
|
||||
system.l2c.total_refs 1477463 # Total number of references to valid blocks.
|
||||
system.l2c.sampled_refs 156884 # Sample count of references to valid blocks.
|
||||
system.l2c.avg_refs 9.417551 # Average number of references to valid blocks.
|
||||
system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.l2c.occ_blocks::writebacks 16687.001530 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu0.dtb.walker 1.397314 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu0.itb.walker 0.122168 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu0.inst 2780.380300 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu0.data 1123.317941 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu1.dtb.walker 4.426009 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu1.itb.walker 0.092136 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu1.inst 1942.464102 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu1.data 3706.633603 # Average occupied blocks per requestor
|
||||
system.l2c.occ_percent::writebacks 0.254623 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu0.dtb.walker 0.000021 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu0.itb.walker 0.000002 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu0.inst 0.042425 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu0.data 0.017140 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu1.dtb.walker 0.000068 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu1.itb.walker 0.000001 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu1.inst 0.029640 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu1.data 0.056559 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::total 0.400480 # Average percentage of cache occupancy
|
||||
system.l2c.ReadReq_hits::cpu0.dtb.walker 5294 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu0.itb.walker 2199 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu0.inst 485527 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu0.data 213776 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu1.dtb.walker 4291 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu1.itb.walker 1552 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu1.inst 359854 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu1.data 128180 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::total 1200673 # number of ReadReq hits
|
||||
system.l2c.Writeback_hits::writebacks 578200 # number of Writeback hits
|
||||
system.l2c.Writeback_hits::total 578200 # number of Writeback hits
|
||||
system.l2c.UpgradeReq_hits::cpu0.data 835 # number of UpgradeReq hits
|
||||
system.l2c.UpgradeReq_hits::cpu1.data 757 # number of UpgradeReq hits
|
||||
system.l2c.UpgradeReq_hits::total 1592 # number of UpgradeReq hits
|
||||
system.l2c.SCUpgradeReq_hits::cpu0.data 134 # number of SCUpgradeReq hits
|
||||
system.l2c.SCUpgradeReq_hits::cpu1.data 214 # number of SCUpgradeReq hits
|
||||
system.l2c.SCUpgradeReq_hits::total 348 # number of SCUpgradeReq hits
|
||||
system.l2c.ReadExReq_hits::cpu0.data 68011 # number of ReadExReq hits
|
||||
system.l2c.ReadExReq_hits::cpu1.data 33233 # number of ReadExReq hits
|
||||
system.l2c.ReadExReq_hits::total 101244 # number of ReadExReq hits
|
||||
system.l2c.demand_hits::cpu0.dtb.walker 5294 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu0.itb.walker 2199 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu0.inst 485527 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu0.data 281787 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu1.dtb.walker 4291 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu1.itb.walker 1552 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu1.inst 359854 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu1.data 161413 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::total 1301917 # number of demand (read+write) hits
|
||||
system.l2c.overall_hits::cpu0.dtb.walker 5294 # number of overall hits
|
||||
system.l2c.overall_hits::cpu0.itb.walker 2199 # number of overall hits
|
||||
system.l2c.overall_hits::cpu0.inst 485527 # number of overall hits
|
||||
system.l2c.overall_hits::cpu0.data 281787 # number of overall hits
|
||||
system.l2c.overall_hits::cpu1.dtb.walker 4291 # number of overall hits
|
||||
system.l2c.overall_hits::cpu1.itb.walker 1552 # number of overall hits
|
||||
system.l2c.overall_hits::cpu1.inst 359854 # number of overall hits
|
||||
system.l2c.overall_hits::cpu1.data 161413 # number of overall hits
|
||||
system.l2c.overall_hits::total 1301917 # number of overall hits
|
||||
system.l2c.ReadReq_misses::cpu0.dtb.walker 12 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu0.itb.walker 8 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu0.inst 9928 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu0.data 9109 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu1.dtb.walker 16 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu1.itb.walker 18 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu1.inst 5336 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu1.data 10106 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::total 34533 # number of ReadReq misses
|
||||
system.l2c.UpgradeReq_misses::cpu0.data 6262 # number of UpgradeReq misses
|
||||
system.l2c.UpgradeReq_misses::cpu1.data 3142 # number of UpgradeReq misses
|
||||
system.l2c.UpgradeReq_misses::total 9404 # number of UpgradeReq misses
|
||||
system.l2c.SCUpgradeReq_misses::cpu0.data 731 # number of SCUpgradeReq misses
|
||||
system.l2c.SCUpgradeReq_misses::cpu1.data 408 # number of SCUpgradeReq misses
|
||||
system.l2c.SCUpgradeReq_misses::total 1139 # number of SCUpgradeReq misses
|
||||
system.l2c.ReadExReq_misses::cpu0.data 98092 # number of ReadExReq misses
|
||||
system.l2c.ReadExReq_misses::cpu1.data 50861 # number of ReadExReq misses
|
||||
system.l2c.ReadExReq_misses::total 148953 # number of ReadExReq misses
|
||||
system.l2c.demand_misses::cpu0.dtb.walker 12 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu0.itb.walker 8 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu0.inst 9928 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu0.data 107201 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu1.dtb.walker 16 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu1.itb.walker 18 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu1.inst 5336 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu1.data 60967 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::total 183486 # number of demand (read+write) misses
|
||||
system.l2c.overall_misses::cpu0.dtb.walker 12 # number of overall misses
|
||||
system.l2c.overall_misses::cpu0.itb.walker 8 # number of overall misses
|
||||
system.l2c.overall_misses::cpu0.inst 9928 # number of overall misses
|
||||
system.l2c.overall_misses::cpu0.data 107201 # number of overall misses
|
||||
system.l2c.overall_misses::cpu1.dtb.walker 16 # number of overall misses
|
||||
system.l2c.overall_misses::cpu1.itb.walker 18 # number of overall misses
|
||||
system.l2c.overall_misses::cpu1.inst 5336 # number of overall misses
|
||||
system.l2c.overall_misses::cpu1.data 60967 # number of overall misses
|
||||
system.l2c.overall_misses::total 183486 # number of overall misses
|
||||
system.l2c.ReadReq_accesses::cpu0.dtb.walker 5306 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::cpu0.itb.walker 2207 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::cpu0.inst 495455 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::cpu0.data 222885 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::cpu1.dtb.walker 4307 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::cpu1.itb.walker 1570 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::cpu1.inst 365190 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::cpu1.data 138286 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::total 1235206 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.Writeback_accesses::writebacks 578200 # number of Writeback accesses(hits+misses)
|
||||
system.l2c.Writeback_accesses::total 578200 # number of Writeback accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_accesses::cpu0.data 7097 # number of UpgradeReq accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_accesses::cpu1.data 3899 # number of UpgradeReq accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_accesses::total 10996 # number of UpgradeReq accesses(hits+misses)
|
||||
system.l2c.SCUpgradeReq_accesses::cpu0.data 865 # number of SCUpgradeReq accesses(hits+misses)
|
||||
system.l2c.SCUpgradeReq_accesses::cpu1.data 622 # number of SCUpgradeReq accesses(hits+misses)
|
||||
system.l2c.SCUpgradeReq_accesses::total 1487 # number of SCUpgradeReq accesses(hits+misses)
|
||||
system.l2c.ReadExReq_accesses::cpu0.data 166103 # number of ReadExReq accesses(hits+misses)
|
||||
system.l2c.ReadExReq_accesses::cpu1.data 84094 # number of ReadExReq accesses(hits+misses)
|
||||
system.l2c.ReadExReq_accesses::total 250197 # number of ReadExReq accesses(hits+misses)
|
||||
system.l2c.demand_accesses::cpu0.dtb.walker 5306 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu0.itb.walker 2207 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu0.inst 495455 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu0.data 388988 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu1.dtb.walker 4307 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu1.itb.walker 1570 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu1.inst 365190 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu1.data 222380 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::total 1485403 # number of demand (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu0.dtb.walker 5306 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu0.itb.walker 2207 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu0.inst 495455 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu0.data 388988 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu1.dtb.walker 4307 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu1.itb.walker 1570 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu1.inst 365190 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu1.data 222380 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::total 1485403 # number of overall (read+write) accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.002262 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.003625 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu0.inst 0.020038 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu0.data 0.040869 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.003715 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.011465 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu1.inst 0.014612 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu1.data 0.073080 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::total 0.027957 # miss rate for ReadReq accesses
|
||||
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.882345 # miss rate for UpgradeReq accesses
|
||||
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.805848 # miss rate for UpgradeReq accesses
|
||||
system.l2c.UpgradeReq_miss_rate::total 0.855220 # miss rate for UpgradeReq accesses
|
||||
system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.845087 # miss rate for SCUpgradeReq accesses
|
||||
system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.655949 # miss rate for SCUpgradeReq accesses
|
||||
system.l2c.SCUpgradeReq_miss_rate::total 0.765972 # miss rate for SCUpgradeReq accesses
|
||||
system.l2c.ReadExReq_miss_rate::cpu0.data 0.590549 # miss rate for ReadExReq accesses
|
||||
system.l2c.ReadExReq_miss_rate::cpu1.data 0.604811 # miss rate for ReadExReq accesses
|
||||
system.l2c.ReadExReq_miss_rate::total 0.595343 # miss rate for ReadExReq accesses
|
||||
system.l2c.demand_miss_rate::cpu0.dtb.walker 0.002262 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu0.itb.walker 0.003625 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu0.inst 0.020038 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu0.data 0.275589 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu1.dtb.walker 0.003715 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu1.itb.walker 0.011465 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu1.inst 0.014612 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu1.data 0.274157 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::total 0.123526 # miss rate for demand accesses
|
||||
system.l2c.overall_miss_rate::cpu0.dtb.walker 0.002262 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu0.itb.walker 0.003625 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu0.inst 0.020038 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu0.data 0.275589 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu1.dtb.walker 0.003715 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu1.itb.walker 0.011465 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu1.inst 0.014612 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu1.data 0.274157 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::total 0.123526 # miss rate for overall accesses
|
||||
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.l2c.fast_writes 0 # number of fast writes performed
|
||||
system.l2c.cache_copies 0 # number of cache copies performed
|
||||
system.l2c.writebacks::writebacks 112464 # number of writebacks
|
||||
system.l2c.writebacks::total 112464 # number of writebacks
|
||||
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
||||
system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
|
||||
system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
|
||||
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
|
||||
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
|
||||
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
|
||||
system.cpu0.dtb.inst_hits 0 # ITB inst hits
|
||||
system.cpu0.dtb.inst_misses 0 # ITB inst misses
|
||||
system.cpu0.dtb.read_hits 9312139 # DTB read hits
|
||||
system.cpu0.dtb.read_misses 5476 # DTB read misses
|
||||
system.cpu0.dtb.write_hits 6895585 # DTB write hits
|
||||
system.cpu0.dtb.write_misses 1137 # DTB write misses
|
||||
system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed
|
||||
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
|
||||
system.cpu0.dtb.flush_entries 2449 # Number of entries that have been flushed from TLB
|
||||
system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu0.dtb.prefetch_faults 187 # Number of TLB faults due to prefetch
|
||||
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu0.dtb.perms_faults 267 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu0.dtb.read_accesses 9317615 # DTB read accesses
|
||||
system.cpu0.dtb.write_accesses 6896722 # DTB write accesses
|
||||
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
|
||||
system.cpu0.dtb.hits 16207724 # DTB hits
|
||||
system.cpu0.dtb.misses 6613 # DTB misses
|
||||
system.cpu0.dtb.accesses 16214337 # DTB accesses
|
||||
system.cpu0.itb.inst_hits 34683994 # ITB inst hits
|
||||
system.cpu0.itb.inst_misses 3170 # ITB inst misses
|
||||
system.cpu0.itb.read_hits 0 # DTB read hits
|
||||
system.cpu0.itb.read_misses 0 # DTB read misses
|
||||
system.cpu0.itb.write_hits 0 # DTB write hits
|
||||
system.cpu0.itb.write_misses 0 # DTB write misses
|
||||
system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed
|
||||
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
|
||||
system.cpu0.itb.flush_entries 1558 # Number of entries that have been flushed from TLB
|
||||
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu0.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu0.itb.write_accesses 0 # DTB write accesses
|
||||
system.cpu0.itb.inst_accesses 34687164 # ITB inst accesses
|
||||
system.cpu0.itb.hits 34683994 # DTB hits
|
||||
system.cpu0.itb.misses 3170 # DTB misses
|
||||
system.cpu0.itb.accesses 34687164 # DTB accesses
|
||||
system.cpu0.numCycles 1823259919 # number of cpu cycles simulated
|
||||
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu0.committedInsts 33900598 # Number of instructions committed
|
||||
system.cpu0.committedOps 44786074 # Number of ops (including micro ops) committed
|
||||
system.cpu0.num_int_alu_accesses 39685287 # Number of integer alu accesses
|
||||
system.cpu0.num_fp_alu_accesses 5074 # Number of float alu accesses
|
||||
system.cpu0.num_func_calls 1296918 # number of times a function call or return occured
|
||||
system.cpu0.num_conditional_control_insts 4494112 # number of instructions that are conditional controls
|
||||
system.cpu0.num_int_insts 39685287 # number of integer instructions
|
||||
system.cpu0.num_fp_insts 5074 # number of float instructions
|
||||
system.cpu0.num_int_register_reads 201262894 # number of times the integer registers were read
|
||||
system.cpu0.num_int_register_writes 42034263 # number of times the integer registers were written
|
||||
system.cpu0.num_fp_register_reads 3706 # number of times the floating registers were read
|
||||
system.cpu0.num_fp_register_writes 1372 # number of times the floating registers were written
|
||||
system.cpu0.num_mem_refs 16978573 # number of memory refs
|
||||
system.cpu0.num_load_insts 9760184 # Number of load instructions
|
||||
system.cpu0.num_store_insts 7218389 # Number of store instructions
|
||||
system.cpu0.num_idle_cycles 1777623684.411826 # Number of idle cycles
|
||||
system.cpu0.num_busy_cycles 45636234.588174 # Number of busy cycles
|
||||
system.cpu0.not_idle_fraction 0.025030 # Percentage of non-idle cycles
|
||||
system.cpu0.idle_fraction 0.974970 # Percentage of idle cycles
|
||||
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
|
||||
system.cpu0.kern.inst.quiesce 58955 # number of quiesce instructions executed
|
||||
system.cpu0.icache.replacements 497177 # number of replacements
|
||||
system.cpu0.icache.tagsinuse 511.014795 # Cycle average of tags in use
|
||||
system.cpu0.icache.total_refs 34187980 # Total number of references to valid blocks.
|
||||
system.cpu0.icache.sampled_refs 497689 # Sample count of references to valid blocks.
|
||||
system.cpu0.icache.avg_refs 68.693461 # Average number of references to valid blocks.
|
||||
system.cpu0.icache.warmup_cycle 64536851000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu0.icache.occ_blocks::cpu0.inst 511.014795 # Average occupied blocks per requestor
|
||||
system.cpu0.icache.occ_percent::cpu0.inst 0.998076 # Average percentage of cache occupancy
|
||||
system.cpu0.icache.occ_percent::total 0.998076 # Average percentage of cache occupancy
|
||||
system.cpu0.icache.ReadReq_hits::cpu0.inst 34187980 # number of ReadReq hits
|
||||
system.cpu0.icache.ReadReq_hits::total 34187980 # number of ReadReq hits
|
||||
system.cpu0.icache.demand_hits::cpu0.inst 34187980 # number of demand (read+write) hits
|
||||
system.cpu0.icache.demand_hits::total 34187980 # number of demand (read+write) hits
|
||||
system.cpu0.icache.overall_hits::cpu0.inst 34187980 # number of overall hits
|
||||
system.cpu0.icache.overall_hits::total 34187980 # number of overall hits
|
||||
system.cpu0.icache.ReadReq_misses::cpu0.inst 497690 # number of ReadReq misses
|
||||
system.cpu0.icache.ReadReq_misses::total 497690 # number of ReadReq misses
|
||||
system.cpu0.icache.demand_misses::cpu0.inst 497690 # number of demand (read+write) misses
|
||||
system.cpu0.icache.demand_misses::total 497690 # number of demand (read+write) misses
|
||||
system.cpu0.icache.overall_misses::cpu0.inst 497690 # number of overall misses
|
||||
system.cpu0.icache.overall_misses::total 497690 # number of overall misses
|
||||
system.cpu0.icache.ReadReq_accesses::cpu0.inst 34685670 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu0.icache.ReadReq_accesses::total 34685670 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu0.icache.demand_accesses::cpu0.inst 34685670 # number of demand (read+write) accesses
|
||||
system.cpu0.icache.demand_accesses::total 34685670 # number of demand (read+write) accesses
|
||||
system.cpu0.icache.overall_accesses::cpu0.inst 34685670 # number of overall (read+write) accesses
|
||||
system.cpu0.icache.overall_accesses::total 34685670 # number of overall (read+write) accesses
|
||||
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014349 # miss rate for ReadReq accesses
|
||||
system.cpu0.icache.ReadReq_miss_rate::total 0.014349 # miss rate for ReadReq accesses
|
||||
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014349 # miss rate for demand accesses
|
||||
system.cpu0.icache.demand_miss_rate::total 0.014349 # miss rate for demand accesses
|
||||
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014349 # miss rate for overall accesses
|
||||
system.cpu0.icache.overall_miss_rate::total 0.014349 # miss rate for overall accesses
|
||||
system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu0.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu0.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu0.icache.writebacks::writebacks 26062 # number of writebacks
|
||||
system.cpu0.icache.writebacks::total 26062 # number of writebacks
|
||||
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu0.dcache.replacements 385595 # number of replacements
|
||||
system.cpu0.dcache.tagsinuse 475.569441 # Cycle average of tags in use
|
||||
system.cpu0.dcache.total_refs 14667576 # Total number of references to valid blocks.
|
||||
system.cpu0.dcache.sampled_refs 386107 # Sample count of references to valid blocks.
|
||||
system.cpu0.dcache.avg_refs 37.988371 # Average number of references to valid blocks.
|
||||
system.cpu0.dcache.warmup_cycle 22115000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu0.dcache.occ_blocks::cpu0.data 475.569441 # Average occupied blocks per requestor
|
||||
system.cpu0.dcache.occ_percent::cpu0.data 0.928847 # Average percentage of cache occupancy
|
||||
system.cpu0.dcache.occ_percent::total 0.928847 # Average percentage of cache occupancy
|
||||
system.cpu0.dcache.ReadReq_hits::cpu0.data 7775792 # number of ReadReq hits
|
||||
system.cpu0.dcache.ReadReq_hits::total 7775792 # number of ReadReq hits
|
||||
system.cpu0.dcache.WriteReq_hits::cpu0.data 6519223 # number of WriteReq hits
|
||||
system.cpu0.dcache.WriteReq_hits::total 6519223 # number of WriteReq hits
|
||||
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 172927 # number of LoadLockedReq hits
|
||||
system.cpu0.dcache.LoadLockedReq_hits::total 172927 # number of LoadLockedReq hits
|
||||
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 175483 # number of StoreCondReq hits
|
||||
system.cpu0.dcache.StoreCondReq_hits::total 175483 # number of StoreCondReq hits
|
||||
system.cpu0.dcache.demand_hits::cpu0.data 14295015 # number of demand (read+write) hits
|
||||
system.cpu0.dcache.demand_hits::total 14295015 # number of demand (read+write) hits
|
||||
system.cpu0.dcache.overall_hits::cpu0.data 14295015 # number of overall hits
|
||||
system.cpu0.dcache.overall_hits::total 14295015 # number of overall hits
|
||||
system.cpu0.dcache.ReadReq_misses::cpu0.data 240570 # number of ReadReq misses
|
||||
system.cpu0.dcache.ReadReq_misses::total 240570 # number of ReadReq misses
|
||||
system.cpu0.dcache.WriteReq_misses::cpu0.data 186007 # number of WriteReq misses
|
||||
system.cpu0.dcache.WriteReq_misses::total 186007 # number of WriteReq misses
|
||||
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9987 # number of LoadLockedReq misses
|
||||
system.cpu0.dcache.LoadLockedReq_misses::total 9987 # number of LoadLockedReq misses
|
||||
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7377 # number of StoreCondReq misses
|
||||
system.cpu0.dcache.StoreCondReq_misses::total 7377 # number of StoreCondReq misses
|
||||
system.cpu0.dcache.demand_misses::cpu0.data 426577 # number of demand (read+write) misses
|
||||
system.cpu0.dcache.demand_misses::total 426577 # number of demand (read+write) misses
|
||||
system.cpu0.dcache.overall_misses::cpu0.data 426577 # number of overall misses
|
||||
system.cpu0.dcache.overall_misses::total 426577 # number of overall misses
|
||||
system.cpu0.dcache.ReadReq_accesses::cpu0.data 8016362 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu0.dcache.ReadReq_accesses::total 8016362 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu0.dcache.WriteReq_accesses::cpu0.data 6705230 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu0.dcache.WriteReq_accesses::total 6705230 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 182914 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu0.dcache.LoadLockedReq_accesses::total 182914 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 182860 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu0.dcache.StoreCondReq_accesses::total 182860 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu0.dcache.demand_accesses::cpu0.data 14721592 # number of demand (read+write) accesses
|
||||
system.cpu0.dcache.demand_accesses::total 14721592 # number of demand (read+write) accesses
|
||||
system.cpu0.dcache.overall_accesses::cpu0.data 14721592 # number of overall (read+write) accesses
|
||||
system.cpu0.dcache.overall_accesses::total 14721592 # number of overall (read+write) accesses
|
||||
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.030010 # miss rate for ReadReq accesses
|
||||
system.cpu0.dcache.ReadReq_miss_rate::total 0.030010 # miss rate for ReadReq accesses
|
||||
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.027741 # miss rate for WriteReq accesses
|
||||
system.cpu0.dcache.WriteReq_miss_rate::total 0.027741 # miss rate for WriteReq accesses
|
||||
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.054599 # miss rate for LoadLockedReq accesses
|
||||
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.054599 # miss rate for LoadLockedReq accesses
|
||||
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.040342 # miss rate for StoreCondReq accesses
|
||||
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.040342 # miss rate for StoreCondReq accesses
|
||||
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.028976 # miss rate for demand accesses
|
||||
system.cpu0.dcache.demand_miss_rate::total 0.028976 # miss rate for demand accesses
|
||||
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.028976 # miss rate for overall accesses
|
||||
system.cpu0.dcache.overall_miss_rate::total 0.028976 # miss rate for overall accesses
|
||||
system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu0.dcache.writebacks::writebacks 342703 # number of writebacks
|
||||
system.cpu0.dcache.writebacks::total 342703 # number of writebacks
|
||||
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu1.dtb.inst_hits 0 # ITB inst hits
|
||||
system.cpu1.dtb.inst_misses 0 # ITB inst misses
|
||||
system.cpu1.dtb.read_hits 6036043 # DTB read hits
|
||||
system.cpu1.dtb.read_misses 1895 # DTB read misses
|
||||
system.cpu1.dtb.write_hits 4565126 # DTB write hits
|
||||
system.cpu1.dtb.write_misses 1147 # DTB write misses
|
||||
system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed
|
||||
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
|
||||
system.cpu1.dtb.flush_entries 1364 # Number of entries that have been flushed from TLB
|
||||
system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu1.dtb.prefetch_faults 95 # Number of TLB faults due to prefetch
|
||||
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu1.dtb.perms_faults 185 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu1.dtb.read_accesses 6037938 # DTB read accesses
|
||||
system.cpu1.dtb.write_accesses 4566273 # DTB write accesses
|
||||
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
|
||||
system.cpu1.dtb.hits 10601169 # DTB hits
|
||||
system.cpu1.dtb.misses 3042 # DTB misses
|
||||
system.cpu1.dtb.accesses 10604211 # DTB accesses
|
||||
system.cpu1.itb.inst_hits 26944447 # ITB inst hits
|
||||
system.cpu1.itb.inst_misses 1203 # ITB inst misses
|
||||
system.cpu1.itb.read_hits 0 # DTB read hits
|
||||
system.cpu1.itb.read_misses 0 # DTB read misses
|
||||
system.cpu1.itb.write_hits 0 # DTB write hits
|
||||
system.cpu1.itb.write_misses 0 # DTB write misses
|
||||
system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed
|
||||
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
|
||||
system.cpu1.itb.flush_entries 1228 # Number of entries that have been flushed from TLB
|
||||
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu1.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu1.itb.write_accesses 0 # DTB write accesses
|
||||
system.cpu1.itb.inst_accesses 26945650 # ITB inst accesses
|
||||
system.cpu1.itb.hits 26944447 # DTB hits
|
||||
system.cpu1.itb.misses 1203 # DTB misses
|
||||
system.cpu1.itb.accesses 26945650 # DTB accesses
|
||||
system.cpu1.numCycles 1822760078 # number of cpu cycles simulated
|
||||
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu1.committedInsts 26714987 # Number of instructions committed
|
||||
system.cpu1.committedOps 33555986 # Number of ops (including micro ops) committed
|
||||
system.cpu1.num_int_alu_accesses 30087808 # Number of integer alu accesses
|
||||
system.cpu1.num_fp_alu_accesses 5643 # Number of float alu accesses
|
||||
system.cpu1.num_func_calls 723750 # number of times a function call or return occured
|
||||
system.cpu1.num_conditional_control_insts 3301562 # number of instructions that are conditional controls
|
||||
system.cpu1.num_int_insts 30087808 # number of integer instructions
|
||||
system.cpu1.num_fp_insts 5643 # number of float instructions
|
||||
system.cpu1.num_int_register_reads 152234781 # number of times the integer registers were read
|
||||
system.cpu1.num_int_register_writes 32495677 # number of times the integer registers were written
|
||||
system.cpu1.num_fp_register_reads 3915 # number of times the floating registers were read
|
||||
system.cpu1.num_fp_register_writes 1728 # number of times the floating registers were written
|
||||
system.cpu1.num_mem_refs 11031013 # number of memory refs
|
||||
system.cpu1.num_load_insts 6247466 # Number of load instructions
|
||||
system.cpu1.num_store_insts 4783547 # Number of store instructions
|
||||
system.cpu1.num_idle_cycles 1788952556.347001 # Number of idle cycles
|
||||
system.cpu1.num_busy_cycles 33807521.652999 # Number of busy cycles
|
||||
system.cpu1.not_idle_fraction 0.018547 # Percentage of non-idle cycles
|
||||
system.cpu1.idle_fraction 0.981453 # Percentage of idle cycles
|
||||
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
|
||||
system.cpu1.kern.inst.quiesce 31471 # number of quiesce instructions executed
|
||||
system.cpu1.icache.replacements 365832 # number of replacements
|
||||
system.cpu1.icache.tagsinuse 475.430525 # Cycle average of tags in use
|
||||
system.cpu1.icache.total_refs 26579068 # Total number of references to valid blocks.
|
||||
system.cpu1.icache.sampled_refs 366344 # Sample count of references to valid blocks.
|
||||
system.cpu1.icache.avg_refs 72.552213 # Average number of references to valid blocks.
|
||||
system.cpu1.icache.warmup_cycle 69967043000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu1.icache.occ_blocks::cpu1.inst 475.430525 # Average occupied blocks per requestor
|
||||
system.cpu1.icache.occ_percent::cpu1.inst 0.928575 # Average percentage of cache occupancy
|
||||
system.cpu1.icache.occ_percent::total 0.928575 # Average percentage of cache occupancy
|
||||
system.cpu1.icache.ReadReq_hits::cpu1.inst 26579068 # number of ReadReq hits
|
||||
system.cpu1.icache.ReadReq_hits::total 26579068 # number of ReadReq hits
|
||||
system.cpu1.icache.demand_hits::cpu1.inst 26579068 # number of demand (read+write) hits
|
||||
system.cpu1.icache.demand_hits::total 26579068 # number of demand (read+write) hits
|
||||
system.cpu1.icache.overall_hits::cpu1.inst 26579068 # number of overall hits
|
||||
system.cpu1.icache.overall_hits::total 26579068 # number of overall hits
|
||||
system.cpu1.icache.ReadReq_misses::cpu1.inst 366344 # number of ReadReq misses
|
||||
system.cpu1.icache.ReadReq_misses::total 366344 # number of ReadReq misses
|
||||
system.cpu1.icache.demand_misses::cpu1.inst 366344 # number of demand (read+write) misses
|
||||
system.cpu1.icache.demand_misses::total 366344 # number of demand (read+write) misses
|
||||
system.cpu1.icache.overall_misses::cpu1.inst 366344 # number of overall misses
|
||||
system.cpu1.icache.overall_misses::total 366344 # number of overall misses
|
||||
system.cpu1.icache.ReadReq_accesses::cpu1.inst 26945412 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu1.icache.ReadReq_accesses::total 26945412 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu1.icache.demand_accesses::cpu1.inst 26945412 # number of demand (read+write) accesses
|
||||
system.cpu1.icache.demand_accesses::total 26945412 # number of demand (read+write) accesses
|
||||
system.cpu1.icache.overall_accesses::cpu1.inst 26945412 # number of overall (read+write) accesses
|
||||
system.cpu1.icache.overall_accesses::total 26945412 # number of overall (read+write) accesses
|
||||
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.013596 # miss rate for ReadReq accesses
|
||||
system.cpu1.icache.ReadReq_miss_rate::total 0.013596 # miss rate for ReadReq accesses
|
||||
system.cpu1.icache.demand_miss_rate::cpu1.inst 0.013596 # miss rate for demand accesses
|
||||
system.cpu1.icache.demand_miss_rate::total 0.013596 # miss rate for demand accesses
|
||||
system.cpu1.icache.overall_miss_rate::cpu1.inst 0.013596 # miss rate for overall accesses
|
||||
system.cpu1.icache.overall_miss_rate::total 0.013596 # miss rate for overall accesses
|
||||
system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu1.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu1.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu1.icache.writebacks::writebacks 12806 # number of writebacks
|
||||
system.cpu1.icache.writebacks::total 12806 # number of writebacks
|
||||
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu1.dcache.replacements 240038 # number of replacements
|
||||
system.cpu1.dcache.tagsinuse 389.638585 # Cycle average of tags in use
|
||||
system.cpu1.dcache.total_refs 9512122 # Total number of references to valid blocks.
|
||||
system.cpu1.dcache.sampled_refs 240396 # Sample count of references to valid blocks.
|
||||
system.cpu1.dcache.avg_refs 39.568554 # Average number of references to valid blocks.
|
||||
system.cpu1.dcache.warmup_cycle 69263687500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu1.dcache.occ_blocks::cpu1.data 389.638585 # Average occupied blocks per requestor
|
||||
system.cpu1.dcache.occ_percent::cpu1.data 0.761013 # Average percentage of cache occupancy
|
||||
system.cpu1.dcache.occ_percent::total 0.761013 # Average percentage of cache occupancy
|
||||
system.cpu1.dcache.ReadReq_hits::cpu1.data 5740038 # number of ReadReq hits
|
||||
system.cpu1.dcache.ReadReq_hits::total 5740038 # number of ReadReq hits
|
||||
system.cpu1.dcache.WriteReq_hits::cpu1.data 3634687 # number of WriteReq hits
|
||||
system.cpu1.dcache.WriteReq_hits::total 3634687 # number of WriteReq hits
|
||||
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 56514 # number of LoadLockedReq hits
|
||||
system.cpu1.dcache.LoadLockedReq_hits::total 56514 # number of LoadLockedReq hits
|
||||
system.cpu1.dcache.StoreCondReq_hits::cpu1.data 57060 # number of StoreCondReq hits
|
||||
system.cpu1.dcache.StoreCondReq_hits::total 57060 # number of StoreCondReq hits
|
||||
system.cpu1.dcache.demand_hits::cpu1.data 9374725 # number of demand (read+write) hits
|
||||
system.cpu1.dcache.demand_hits::total 9374725 # number of demand (read+write) hits
|
||||
system.cpu1.dcache.overall_hits::cpu1.data 9374725 # number of overall hits
|
||||
system.cpu1.dcache.overall_hits::total 9374725 # number of overall hits
|
||||
system.cpu1.dcache.ReadReq_misses::cpu1.data 161066 # number of ReadReq misses
|
||||
system.cpu1.dcache.ReadReq_misses::total 161066 # number of ReadReq misses
|
||||
system.cpu1.dcache.WriteReq_misses::cpu1.data 108913 # number of WriteReq misses
|
||||
system.cpu1.dcache.WriteReq_misses::total 108913 # number of WriteReq misses
|
||||
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 10616 # number of LoadLockedReq misses
|
||||
system.cpu1.dcache.LoadLockedReq_misses::total 10616 # number of LoadLockedReq misses
|
||||
system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10014 # number of StoreCondReq misses
|
||||
system.cpu1.dcache.StoreCondReq_misses::total 10014 # number of StoreCondReq misses
|
||||
system.cpu1.dcache.demand_misses::cpu1.data 269979 # number of demand (read+write) misses
|
||||
system.cpu1.dcache.demand_misses::total 269979 # number of demand (read+write) misses
|
||||
system.cpu1.dcache.overall_misses::cpu1.data 269979 # number of overall misses
|
||||
system.cpu1.dcache.overall_misses::total 269979 # number of overall misses
|
||||
system.cpu1.dcache.ReadReq_accesses::cpu1.data 5901104 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu1.dcache.ReadReq_accesses::total 5901104 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu1.dcache.WriteReq_accesses::cpu1.data 3743600 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu1.dcache.WriteReq_accesses::total 3743600 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 67130 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu1.dcache.LoadLockedReq_accesses::total 67130 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 67074 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu1.dcache.StoreCondReq_accesses::total 67074 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu1.dcache.demand_accesses::cpu1.data 9644704 # number of demand (read+write) accesses
|
||||
system.cpu1.dcache.demand_accesses::total 9644704 # number of demand (read+write) accesses
|
||||
system.cpu1.dcache.overall_accesses::cpu1.data 9644704 # number of overall (read+write) accesses
|
||||
system.cpu1.dcache.overall_accesses::total 9644704 # number of overall (read+write) accesses
|
||||
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.027294 # miss rate for ReadReq accesses
|
||||
system.cpu1.dcache.ReadReq_miss_rate::total 0.027294 # miss rate for ReadReq accesses
|
||||
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.029093 # miss rate for WriteReq accesses
|
||||
system.cpu1.dcache.WriteReq_miss_rate::total 0.029093 # miss rate for WriteReq accesses
|
||||
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.158141 # miss rate for LoadLockedReq accesses
|
||||
system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.158141 # miss rate for LoadLockedReq accesses
|
||||
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.149298 # miss rate for StoreCondReq accesses
|
||||
system.cpu1.dcache.StoreCondReq_miss_rate::total 0.149298 # miss rate for StoreCondReq accesses
|
||||
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.027992 # miss rate for demand accesses
|
||||
system.cpu1.dcache.demand_miss_rate::total 0.027992 # miss rate for demand accesses
|
||||
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.027992 # miss rate for overall accesses
|
||||
system.cpu1.dcache.overall_miss_rate::total 0.027992 # miss rate for overall accesses
|
||||
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu1.dcache.writebacks::writebacks 196629 # number of writebacks
|
||||
system.cpu1.dcache.writebacks::total 196629 # number of writebacks
|
||||
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.iocache.replacements 0 # number of replacements
|
||||
system.iocache.tagsinuse 0 # Cycle average of tags in use
|
||||
system.iocache.total_refs 0 # Total number of references to valid blocks.
|
||||
system.iocache.sampled_refs 0 # Sample count of references to valid blocks.
|
||||
system.iocache.avg_refs nan # Average number of references to valid blocks.
|
||||
system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.iocache.fast_writes 0 # number of fast writes performed
|
||||
system.iocache.cache_copies 0 # number of cache copies performed
|
||||
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
@ -0,0 +1 @@
|
||||
build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual FAILED!
|
||||
Binary file not shown.
@ -0,0 +1,676 @@
|
||||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
full_system=true
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
||||
[system]
|
||||
type=LinuxArmSystem
|
||||
children=bridge cf0 cpu intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver
|
||||
atags_addr=256
|
||||
boot_loader=/dist/m5/system/binaries/boot.arm
|
||||
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
|
||||
early_kernel_symbols=false
|
||||
flags_addr=268435504
|
||||
gic_cpu_addr=520093952
|
||||
init_param=0
|
||||
kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
|
||||
load_addr_mask=268435455
|
||||
machine_type=RealView_PBX
|
||||
mem_mode=atomic
|
||||
memories=system.physmem system.realview.nvmem
|
||||
midr_regval=890224640
|
||||
num_work_ids=16
|
||||
readfile=tests/halt.sh
|
||||
symbolfile=
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.membus.slave[0]
|
||||
|
||||
[system.bridge]
|
||||
type=Bridge
|
||||
delay=50000
|
||||
nack_delay=4000
|
||||
ranges=268435456:520093695 1073741824:1610612735
|
||||
req_size=16
|
||||
resp_size=16
|
||||
write_ack=false
|
||||
master=system.iobus.slave[0]
|
||||
slave=system.membus.master[0]
|
||||
|
||||
[system.cf0]
|
||||
type=IdeDisk
|
||||
children=image
|
||||
delay=1000000
|
||||
driveID=master
|
||||
image=system.cf0.image
|
||||
|
||||
[system.cf0.image]
|
||||
type=CowDiskImage
|
||||
children=child
|
||||
child=system.cf0.image.child
|
||||
image_file=
|
||||
read_only=false
|
||||
table_size=65536
|
||||
|
||||
[system.cf0.image.child]
|
||||
type=RawDiskImage
|
||||
image_file=/dist/m5/system/disks/linux-arm-ael.img
|
||||
read_only=true
|
||||
|
||||
[system.cpu]
|
||||
type=AtomicSimpleCPU
|
||||
children=dcache dtb icache interrupts itb tracer
|
||||
checker=Null
|
||||
clock=500
|
||||
cpu_id=0
|
||||
defer_registration=false
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
fastmem=false
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
interrupts=system.cpu.interrupts
|
||||
itb=system.cpu.itb
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
phase=0
|
||||
profile=0
|
||||
progress_interval=0
|
||||
simulate_data_stalls=false
|
||||
simulate_inst_stalls=false
|
||||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
width=1
|
||||
workload=
|
||||
dcache_port=system.cpu.dcache.cpu_side
|
||||
icache_port=system.cpu.icache.cpu_side
|
||||
|
||||
[system.cpu.dcache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=4
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=32768
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=8
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.dcache_port
|
||||
mem_side=system.toL2Bus.slave[1]
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
size=64
|
||||
walker=system.cpu.dtb.walker
|
||||
|
||||
[system.cpu.dtb.walker]
|
||||
type=ArmTableWalker
|
||||
max_backoff=100000
|
||||
min_backoff=0
|
||||
sys=system
|
||||
port=system.toL2Bus.slave[3]
|
||||
|
||||
[system.cpu.icache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=1
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=32768
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=8
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.icache_port
|
||||
mem_side=system.toL2Bus.slave[0]
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=ArmInterrupts
|
||||
|
||||
[system.cpu.itb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
size=64
|
||||
walker=system.cpu.itb.walker
|
||||
|
||||
[system.cpu.itb.walker]
|
||||
type=ArmTableWalker
|
||||
max_backoff=100000
|
||||
min_backoff=0
|
||||
sys=system
|
||||
port=system.toL2Bus.slave[2]
|
||||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
|
||||
[system.intrctrl]
|
||||
type=IntrControl
|
||||
sys=system
|
||||
|
||||
[system.iobus]
|
||||
type=NoncoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side
|
||||
slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
|
||||
|
||||
[system.iocache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:268435455
|
||||
assoc=8
|
||||
block_size=64
|
||||
forward_snoops=false
|
||||
hash_delay=1
|
||||
is_top_level=false
|
||||
latency=50000
|
||||
max_miss_count=0
|
||||
mshrs=20
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=1024
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=12
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.iobus.master[25]
|
||||
mem_side=system.membus.slave[1]
|
||||
|
||||
[system.l2c]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=8
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=false
|
||||
latency=10000
|
||||
max_miss_count=0
|
||||
mshrs=92
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=4194304
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=16
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.toL2Bus.master[0]
|
||||
mem_side=system.membus.slave[2]
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
children=badaddr_responder
|
||||
block_size=64
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
default=system.membus.badaddr_responder.pio
|
||||
master=system.bridge.slave system.realview.nvmem.port[0] system.physmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio
|
||||
slave=system.system_port system.iocache.mem_side system.l2c.mem_side
|
||||
|
||||
[system.membus.badaddr_responder]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=0
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=true
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=warn
|
||||
pio=system.membus.default
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
conf_table_reported=true
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.membus.master[2]
|
||||
|
||||
[system.realview]
|
||||
type=RealView
|
||||
children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
|
||||
intrctrl=system.intrctrl
|
||||
max_mem_size=268435456
|
||||
mem_start_addr=0
|
||||
pci_cfg_base=0
|
||||
system=system
|
||||
|
||||
[system.realview.a9scu]
|
||||
type=A9SCU
|
||||
pio_addr=520093696
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.membus.master[5]
|
||||
|
||||
[system.realview.aaci_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
ignore_access=false
|
||||
pio_addr=268451840
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.iobus.master[21]
|
||||
|
||||
[system.realview.cf_ctrl]
|
||||
type=IdeController
|
||||
BAR0=402653184
|
||||
BAR0LegacyIO=true
|
||||
BAR0Size=16
|
||||
BAR1=402653440
|
||||
BAR1LegacyIO=true
|
||||
BAR1Size=1
|
||||
BAR2=1
|
||||
BAR2LegacyIO=false
|
||||
BAR2Size=8
|
||||
BAR3=1
|
||||
BAR3LegacyIO=false
|
||||
BAR3Size=4
|
||||
BAR4=1
|
||||
BAR4LegacyIO=false
|
||||
BAR4Size=16
|
||||
BAR5=1
|
||||
BAR5LegacyIO=false
|
||||
BAR5Size=0
|
||||
BIST=0
|
||||
CacheLineSize=0
|
||||
CardbusCIS=0
|
||||
ClassCode=1
|
||||
Command=1
|
||||
DeviceID=28945
|
||||
ExpansionROM=0
|
||||
HeaderType=0
|
||||
InterruptLine=31
|
||||
InterruptPin=1
|
||||
LatencyTimer=0
|
||||
MaximumLatency=0
|
||||
MinimumGrant=0
|
||||
ProgIF=133
|
||||
Revision=0
|
||||
Status=640
|
||||
SubClassCode=1
|
||||
SubsystemID=0
|
||||
SubsystemVendorID=0
|
||||
VendorID=32902
|
||||
config_latency=20000
|
||||
ctrl_offset=2
|
||||
disks=system.cf0
|
||||
io_shift=1
|
||||
max_backoff_delay=10000000
|
||||
min_backoff_delay=4000
|
||||
pci_bus=2
|
||||
pci_dev=7
|
||||
pci_func=0
|
||||
pio_latency=1000
|
||||
platform=system.realview
|
||||
system=system
|
||||
config=system.iobus.master[8]
|
||||
dma=system.iobus.slave[2]
|
||||
pio=system.iobus.master[7]
|
||||
|
||||
[system.realview.clcd]
|
||||
type=Pl111
|
||||
amba_id=1315089
|
||||
clock=41667
|
||||
gic=system.realview.gic
|
||||
int_num=55
|
||||
max_backoff_delay=10000000
|
||||
min_backoff_delay=4000
|
||||
pio_addr=268566528
|
||||
pio_latency=10000
|
||||
system=system
|
||||
vnc=system.vncserver
|
||||
dma=system.iobus.slave[1]
|
||||
pio=system.iobus.master[4]
|
||||
|
||||
[system.realview.dmac_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
ignore_access=false
|
||||
pio_addr=268632064
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.iobus.master[9]
|
||||
|
||||
[system.realview.flash_fake]
|
||||
type=IsaFake
|
||||
fake_mem=true
|
||||
pio_addr=1073741824
|
||||
pio_latency=1000
|
||||
pio_size=536870912
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[24]
|
||||
|
||||
[system.realview.gic]
|
||||
type=Gic
|
||||
cpu_addr=520093952
|
||||
cpu_pio_delay=10000
|
||||
dist_addr=520097792
|
||||
dist_pio_delay=10000
|
||||
int_latency=10000
|
||||
it_lines=128
|
||||
platform=system.realview
|
||||
system=system
|
||||
pio=system.membus.master[3]
|
||||
|
||||
[system.realview.gpio0_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
ignore_access=false
|
||||
pio_addr=268513280
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.iobus.master[16]
|
||||
|
||||
[system.realview.gpio1_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
ignore_access=false
|
||||
pio_addr=268517376
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.iobus.master[17]
|
||||
|
||||
[system.realview.gpio2_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
ignore_access=false
|
||||
pio_addr=268521472
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.iobus.master[18]
|
||||
|
||||
[system.realview.kmi0]
|
||||
type=Pl050
|
||||
amba_id=1314896
|
||||
gic=system.realview.gic
|
||||
int_delay=1000000
|
||||
int_num=52
|
||||
is_mouse=false
|
||||
pio_addr=268460032
|
||||
pio_latency=1000
|
||||
system=system
|
||||
vnc=system.vncserver
|
||||
pio=system.iobus.master[5]
|
||||
|
||||
[system.realview.kmi1]
|
||||
type=Pl050
|
||||
amba_id=1314896
|
||||
gic=system.realview.gic
|
||||
int_delay=1000000
|
||||
int_num=53
|
||||
is_mouse=true
|
||||
pio_addr=268464128
|
||||
pio_latency=1000
|
||||
system=system
|
||||
vnc=system.vncserver
|
||||
pio=system.iobus.master[6]
|
||||
|
||||
[system.realview.l2x0_fake]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=520101888
|
||||
pio_latency=1000
|
||||
pio_size=4095
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.membus.master[4]
|
||||
|
||||
[system.realview.local_cpu_timer]
|
||||
type=CpuLocalTimer
|
||||
clock=1000
|
||||
gic=system.realview.gic
|
||||
int_num_timer=29
|
||||
int_num_watchdog=30
|
||||
pio_addr=520095232
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.membus.master[6]
|
||||
|
||||
[system.realview.mmc_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
ignore_access=false
|
||||
pio_addr=268455936
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.iobus.master[22]
|
||||
|
||||
[system.realview.nvmem]
|
||||
type=SimpleMemory
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
range=2147483648:2214592511
|
||||
zero=true
|
||||
port=system.membus.master[1]
|
||||
|
||||
[system.realview.realview_io]
|
||||
type=RealViewCtrl
|
||||
idreg=0
|
||||
pio_addr=268435456
|
||||
pio_latency=1000
|
||||
proc_id0=201326592
|
||||
proc_id1=201327138
|
||||
system=system
|
||||
pio=system.iobus.master[1]
|
||||
|
||||
[system.realview.rtc]
|
||||
type=PL031
|
||||
amba_id=3412017
|
||||
gic=system.realview.gic
|
||||
int_delay=100000
|
||||
int_num=42
|
||||
pio_addr=268529664
|
||||
pio_latency=1000
|
||||
system=system
|
||||
time=Thu Jan 1 00:00:00 2009
|
||||
pio=system.iobus.master[23]
|
||||
|
||||
[system.realview.sci_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
ignore_access=false
|
||||
pio_addr=268492800
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.iobus.master[20]
|
||||
|
||||
[system.realview.smc_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
ignore_access=false
|
||||
pio_addr=269357056
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.iobus.master[13]
|
||||
|
||||
[system.realview.sp810_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
ignore_access=true
|
||||
pio_addr=268439552
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.iobus.master[14]
|
||||
|
||||
[system.realview.ssp_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
ignore_access=false
|
||||
pio_addr=268488704
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.iobus.master[19]
|
||||
|
||||
[system.realview.timer0]
|
||||
type=Sp804
|
||||
amba_id=1316868
|
||||
clock0=1000000
|
||||
clock1=1000000
|
||||
gic=system.realview.gic
|
||||
int_num0=36
|
||||
int_num1=36
|
||||
pio_addr=268505088
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.iobus.master[2]
|
||||
|
||||
[system.realview.timer1]
|
||||
type=Sp804
|
||||
amba_id=1316868
|
||||
clock0=1000000
|
||||
clock1=1000000
|
||||
gic=system.realview.gic
|
||||
int_num0=37
|
||||
int_num1=37
|
||||
pio_addr=268509184
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.iobus.master[3]
|
||||
|
||||
[system.realview.uart]
|
||||
type=Pl011
|
||||
end_on_eot=false
|
||||
gic=system.realview.gic
|
||||
int_delay=100000
|
||||
int_num=44
|
||||
pio_addr=268472320
|
||||
pio_latency=1000
|
||||
platform=system.realview
|
||||
system=system
|
||||
terminal=system.terminal
|
||||
pio=system.iobus.master[0]
|
||||
|
||||
[system.realview.uart1_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
ignore_access=false
|
||||
pio_addr=268476416
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.iobus.master[10]
|
||||
|
||||
[system.realview.uart2_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
ignore_access=false
|
||||
pio_addr=268480512
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.iobus.master[11]
|
||||
|
||||
[system.realview.uart3_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
ignore_access=false
|
||||
pio_addr=268484608
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.iobus.master[12]
|
||||
|
||||
[system.realview.watchdog_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
ignore_access=false
|
||||
pio_addr=268500992
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.iobus.master[15]
|
||||
|
||||
[system.terminal]
|
||||
type=Terminal
|
||||
intr_control=system.intrctrl
|
||||
number=0
|
||||
output=true
|
||||
port=3456
|
||||
|
||||
[system.toL2Bus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
master=system.l2c.cpu_side
|
||||
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
|
||||
|
||||
[system.vncserver]
|
||||
type=VncServer
|
||||
frame_capture=false
|
||||
number=0
|
||||
port=5900
|
||||
|
||||
@ -0,0 +1,17 @@
|
||||
warn: Sockets disabled, not accepting vnc client connections
|
||||
warn: Sockets disabled, not accepting terminal connections
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: The clidr register always reports 0 caches.
|
||||
warn: clidr LoUIS field of 0b001 to match current ARM implementations.
|
||||
warn: The csselr register isn't implemented.
|
||||
warn: The ccsidr register isn't implemented and always reads as 0.
|
||||
warn: instruction 'mcr bpiallis' unimplemented
|
||||
warn: instruction 'mcr icialluis' unimplemented
|
||||
warn: instruction 'mcr dccimvac' unimplemented
|
||||
warn: instruction 'mcr dccmvau' unimplemented
|
||||
warn: instruction 'mcr icimvau' unimplemented
|
||||
warn: LCD dual screen mode not supported
|
||||
warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
|
||||
warn: instruction 'mcr icialluis' unimplemented
|
||||
warn: instruction 'mcr bpiallis' unimplemented
|
||||
hack: be nice to actually delete the event here
|
||||
@ -0,0 +1,12 @@
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jun 4 2012 12:14:06
|
||||
gem5 started Jun 4 2012 17:24:24
|
||||
gem5 executing on zizzer
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
|
||||
info: Using bootloader at address 0x80000000
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 2332330037000 because m5_exit instruction encountered
|
||||
@ -0,0 +1,368 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 2.332330 # Number of seconds simulated
|
||||
sim_ticks 2332330037000 # Number of ticks simulated
|
||||
final_tick 2332330037000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1412842 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1823742 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 55482154888 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 382804 # Number of bytes of host memory used
|
||||
host_seconds 42.04 # Real time elapsed on the host
|
||||
sim_insts 59392246 # Number of instructions simulated
|
||||
sim_ops 76665494 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::realview.clcd 111673344 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.dtb.walker 1536 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.itb.walker 960 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.inst 941920 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 10043536 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 122661296 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 941920 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 941920 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 6574400 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::cpu.data 3015816 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 9590216 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::realview.clcd 13959168 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.dtb.walker 24 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.itb.walker 15 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.inst 20920 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 156964 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 14137091 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 102725 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::cpu.data 753954 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 856679 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::realview.clcd 47880592 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.dtb.walker 659 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.itb.walker 412 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 403854 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 4306224 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 52591740 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 403854 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 403854 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 2818812 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::cpu.data 1293049 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 4111861 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 2818812 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::realview.clcd 47880592 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.dtb.walker 659 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.itb.walker 412 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 403854 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 5599273 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 56703601 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory
|
||||
system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
|
||||
system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory
|
||||
system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
|
||||
system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory
|
||||
system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
|
||||
system.realview.nvmem.bw_read::cpu.inst 9 # Total read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_read::total 9 # Total read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_inst_read::cpu.inst 9 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_inst_read::total 9 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_total::cpu.inst 9 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_total::total 9 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.l2c.replacements 117012 # number of replacements
|
||||
system.l2c.tagsinuse 24288.656748 # Cycle average of tags in use
|
||||
system.l2c.total_refs 1527554 # Total number of references to valid blocks.
|
||||
system.l2c.sampled_refs 146810 # Sample count of references to valid blocks.
|
||||
system.l2c.avg_refs 10.404972 # Average number of references to valid blocks.
|
||||
system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.l2c.occ_blocks::writebacks 13693.996987 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu.dtb.walker 7.872000 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu.itb.walker 1.975558 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu.inst 5248.163956 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu.data 5336.648246 # Average occupied blocks per requestor
|
||||
system.l2c.occ_percent::writebacks 0.208954 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu.dtb.walker 0.000120 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu.itb.walker 0.000030 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu.inst 0.080081 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu.data 0.081431 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::total 0.370615 # Average percentage of cache occupancy
|
||||
system.l2c.ReadReq_hits::cpu.dtb.walker 7515 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu.itb.walker 3139 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu.inst 835264 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu.data 357385 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::total 1203303 # number of ReadReq hits
|
||||
system.l2c.Writeback_hits::writebacks 605735 # number of Writeback hits
|
||||
system.l2c.Writeback_hits::total 605735 # number of Writeback hits
|
||||
system.l2c.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits
|
||||
system.l2c.UpgradeReq_hits::total 26 # number of UpgradeReq hits
|
||||
system.l2c.ReadExReq_hits::cpu.data 106156 # number of ReadExReq hits
|
||||
system.l2c.ReadExReq_hits::total 106156 # number of ReadExReq hits
|
||||
system.l2c.demand_hits::cpu.dtb.walker 7515 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu.itb.walker 3139 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu.inst 835264 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu.data 463541 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::total 1309459 # number of demand (read+write) hits
|
||||
system.l2c.overall_hits::cpu.dtb.walker 7515 # number of overall hits
|
||||
system.l2c.overall_hits::cpu.itb.walker 3139 # number of overall hits
|
||||
system.l2c.overall_hits::cpu.inst 835264 # number of overall hits
|
||||
system.l2c.overall_hits::cpu.data 463541 # number of overall hits
|
||||
system.l2c.overall_hits::total 1309459 # number of overall hits
|
||||
system.l2c.ReadReq_misses::cpu.dtb.walker 24 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu.itb.walker 15 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu.inst 14304 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu.data 17465 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::total 31808 # number of ReadReq misses
|
||||
system.l2c.UpgradeReq_misses::cpu.data 2918 # number of UpgradeReq misses
|
||||
system.l2c.UpgradeReq_misses::total 2918 # number of UpgradeReq misses
|
||||
system.l2c.ReadExReq_misses::cpu.data 141050 # number of ReadExReq misses
|
||||
system.l2c.ReadExReq_misses::total 141050 # number of ReadExReq misses
|
||||
system.l2c.demand_misses::cpu.dtb.walker 24 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu.itb.walker 15 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu.inst 14304 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu.data 158515 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::total 172858 # number of demand (read+write) misses
|
||||
system.l2c.overall_misses::cpu.dtb.walker 24 # number of overall misses
|
||||
system.l2c.overall_misses::cpu.itb.walker 15 # number of overall misses
|
||||
system.l2c.overall_misses::cpu.inst 14304 # number of overall misses
|
||||
system.l2c.overall_misses::cpu.data 158515 # number of overall misses
|
||||
system.l2c.overall_misses::total 172858 # number of overall misses
|
||||
system.l2c.ReadReq_accesses::cpu.dtb.walker 7539 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::cpu.itb.walker 3154 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::cpu.inst 849568 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::cpu.data 374850 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::total 1235111 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.Writeback_accesses::writebacks 605735 # number of Writeback accesses(hits+misses)
|
||||
system.l2c.Writeback_accesses::total 605735 # number of Writeback accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_accesses::cpu.data 2944 # number of UpgradeReq accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_accesses::total 2944 # number of UpgradeReq accesses(hits+misses)
|
||||
system.l2c.ReadExReq_accesses::cpu.data 247206 # number of ReadExReq accesses(hits+misses)
|
||||
system.l2c.ReadExReq_accesses::total 247206 # number of ReadExReq accesses(hits+misses)
|
||||
system.l2c.demand_accesses::cpu.dtb.walker 7539 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu.itb.walker 3154 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu.inst 849568 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu.data 622056 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::total 1482317 # number of demand (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu.dtb.walker 7539 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu.itb.walker 3154 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu.inst 849568 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu.data 622056 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::total 1482317 # number of overall (read+write) accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.003183 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.004756 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu.inst 0.016837 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu.data 0.046592 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::total 0.025753 # miss rate for ReadReq accesses
|
||||
system.l2c.UpgradeReq_miss_rate::cpu.data 0.991168 # miss rate for UpgradeReq accesses
|
||||
system.l2c.UpgradeReq_miss_rate::total 0.991168 # miss rate for UpgradeReq accesses
|
||||
system.l2c.ReadExReq_miss_rate::cpu.data 0.570577 # miss rate for ReadExReq accesses
|
||||
system.l2c.ReadExReq_miss_rate::total 0.570577 # miss rate for ReadExReq accesses
|
||||
system.l2c.demand_miss_rate::cpu.dtb.walker 0.003183 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu.itb.walker 0.004756 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu.inst 0.016837 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu.data 0.254824 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::total 0.116613 # miss rate for demand accesses
|
||||
system.l2c.overall_miss_rate::cpu.dtb.walker 0.003183 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu.itb.walker 0.004756 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu.inst 0.016837 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu.data 0.254824 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::total 0.116613 # miss rate for overall accesses
|
||||
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.l2c.fast_writes 0 # number of fast writes performed
|
||||
system.l2c.cache_copies 0 # number of cache copies performed
|
||||
system.l2c.writebacks::writebacks 102725 # number of writebacks
|
||||
system.l2c.writebacks::total 102725 # number of writebacks
|
||||
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
||||
system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
|
||||
system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
|
||||
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
|
||||
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
|
||||
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
|
||||
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.dtb.read_hits 14971229 # DTB read hits
|
||||
system.cpu.dtb.read_misses 7293 # DTB read misses
|
||||
system.cpu.dtb.write_hits 11217018 # DTB write hits
|
||||
system.cpu.dtb.write_misses 2181 # DTB write misses
|
||||
system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed
|
||||
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
|
||||
system.cpu.dtb.flush_entries 3492 # Number of entries that have been flushed from TLB
|
||||
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.dtb.prefetch_faults 174 # Number of TLB faults due to prefetch
|
||||
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.dtb.read_accesses 14978522 # DTB read accesses
|
||||
system.cpu.dtb.write_accesses 11219199 # DTB write accesses
|
||||
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
|
||||
system.cpu.dtb.hits 26188247 # DTB hits
|
||||
system.cpu.dtb.misses 9474 # DTB misses
|
||||
system.cpu.dtb.accesses 26197721 # DTB accesses
|
||||
system.cpu.itb.inst_hits 60403303 # ITB inst hits
|
||||
system.cpu.itb.inst_misses 4471 # ITB inst misses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.write_hits 0 # DTB write hits
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed
|
||||
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
|
||||
system.cpu.itb.flush_entries 2343 # Number of entries that have been flushed from TLB
|
||||
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.itb.inst_accesses 60407774 # ITB inst accesses
|
||||
system.cpu.itb.hits 60403303 # DTB hits
|
||||
system.cpu.itb.misses 4471 # DTB misses
|
||||
system.cpu.itb.accesses 60407774 # DTB accesses
|
||||
system.cpu.numCycles 4664583062 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 59392246 # Number of instructions committed
|
||||
system.cpu.committedOps 76665494 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 68281415 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 1972385 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 7647793 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 68281415 # number of integer instructions
|
||||
system.cpu.num_fp_insts 10269 # number of float instructions
|
||||
system.cpu.num_int_register_reads 345981857 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 73062916 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written
|
||||
system.cpu.num_mem_refs 27361692 # number of memory refs
|
||||
system.cpu.num_load_insts 15639569 # Number of load instructions
|
||||
system.cpu.num_store_insts 11722123 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 4586814358.980880 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 77768703.019120 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 0.016672 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0.983328 # Percentage of idle cycles
|
||||
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
||||
system.cpu.kern.inst.quiesce 82795 # number of quiesce instructions executed
|
||||
system.cpu.icache.replacements 850612 # number of replacements
|
||||
system.cpu.icache.tagsinuse 511.678549 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 59554939 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 851124 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 69.972106 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 5708999000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 511.678549 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.999372 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.999372 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 59554939 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 59554939 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 59554939 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 59554939 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 59554939 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 59554939 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 851124 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 851124 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 851124 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 851124 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 851124 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 851124 # number of overall misses
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 60406063 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 60406063 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 60406063 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 60406063 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 60406063 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 60406063 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014090 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.014090 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.014090 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.014090 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.014090 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.014090 # miss rate for overall accesses
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks::writebacks 44595 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 44595 # number of writebacks
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 623347 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 511.997030 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 23628362 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 623859 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 37.874523 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 21763000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 511.997030 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.999994 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 13180074 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 13180074 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 9962087 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 9962087 # number of WriteReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::cpu.data 236035 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::total 236035 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::cpu.data 247222 # number of StoreCondReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::total 247222 # number of StoreCondReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 23142161 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 23142161 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 23142161 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 23142161 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 365465 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 365465 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 250150 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 250150 # number of WriteReq misses
|
||||
system.cpu.dcache.LoadLockedReq_misses::cpu.data 11188 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.LoadLockedReq_misses::total 11188 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 615615 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 615615 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 615615 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 615615 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 13545539 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 13545539 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 10212237 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 10212237 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247223 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::total 247223 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::cpu.data 247222 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::total 247222 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 23757776 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 23757776 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 23757776 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 23757776 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.026980 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.026980 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024495 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.024495 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045255 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045255 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.025912 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.025912 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.025912 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.025912 # miss rate for overall accesses
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 561140 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 561140 # number of writebacks
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.iocache.replacements 0 # number of replacements
|
||||
system.iocache.tagsinuse 0 # Cycle average of tags in use
|
||||
system.iocache.total_refs 0 # Total number of references to valid blocks.
|
||||
system.iocache.sampled_refs 0 # Sample count of references to valid blocks.
|
||||
system.iocache.avg_refs nan # Average number of references to valid blocks.
|
||||
system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.iocache.fast_writes 0 # number of fast writes performed
|
||||
system.iocache.cache_copies 0 # number of cache copies performed
|
||||
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
@ -0,0 +1 @@
|
||||
build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic FAILED!
|
||||
Binary file not shown.
@ -0,0 +1,783 @@
|
||||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
full_system=true
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
||||
[system]
|
||||
type=LinuxArmSystem
|
||||
children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver
|
||||
atags_addr=256
|
||||
boot_loader=/dist/m5/system/binaries/boot.arm
|
||||
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
|
||||
early_kernel_symbols=false
|
||||
flags_addr=268435504
|
||||
gic_cpu_addr=520093952
|
||||
init_param=0
|
||||
kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
|
||||
load_addr_mask=268435455
|
||||
machine_type=RealView_PBX
|
||||
mem_mode=timing
|
||||
memories=system.realview.nvmem system.physmem
|
||||
midr_regval=890224640
|
||||
num_work_ids=16
|
||||
readfile=tests/halt.sh
|
||||
symbolfile=
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.membus.slave[0]
|
||||
|
||||
[system.bridge]
|
||||
type=Bridge
|
||||
delay=50000
|
||||
nack_delay=4000
|
||||
ranges=268435456:520093695 1073741824:1610612735
|
||||
req_size=16
|
||||
resp_size=16
|
||||
write_ack=false
|
||||
master=system.iobus.slave[0]
|
||||
slave=system.membus.master[0]
|
||||
|
||||
[system.cf0]
|
||||
type=IdeDisk
|
||||
children=image
|
||||
delay=1000000
|
||||
driveID=master
|
||||
image=system.cf0.image
|
||||
|
||||
[system.cf0.image]
|
||||
type=CowDiskImage
|
||||
children=child
|
||||
child=system.cf0.image.child
|
||||
image_file=
|
||||
read_only=false
|
||||
table_size=65536
|
||||
|
||||
[system.cf0.image.child]
|
||||
type=RawDiskImage
|
||||
image_file=/dist/m5/system/disks/linux-arm-ael.img
|
||||
read_only=true
|
||||
|
||||
[system.cpu0]
|
||||
type=TimingSimpleCPU
|
||||
children=dcache dtb icache interrupts itb tracer
|
||||
checker=Null
|
||||
clock=500
|
||||
cpu_id=0
|
||||
defer_registration=false
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu0.dtb
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
interrupts=system.cpu0.interrupts
|
||||
itb=system.cpu0.itb
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
phase=0
|
||||
profile=0
|
||||
progress_interval=0
|
||||
system=system
|
||||
tracer=system.cpu0.tracer
|
||||
workload=
|
||||
dcache_port=system.cpu0.dcache.cpu_side
|
||||
icache_port=system.cpu0.icache.cpu_side
|
||||
|
||||
[system.cpu0.dcache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=4
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=32768
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=8
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu0.dcache_port
|
||||
mem_side=system.toL2Bus.slave[1]
|
||||
|
||||
[system.cpu0.dtb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
size=64
|
||||
walker=system.cpu0.dtb.walker
|
||||
|
||||
[system.cpu0.dtb.walker]
|
||||
type=ArmTableWalker
|
||||
max_backoff=100000
|
||||
min_backoff=0
|
||||
sys=system
|
||||
port=system.toL2Bus.slave[3]
|
||||
|
||||
[system.cpu0.icache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=1
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=32768
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=8
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu0.icache_port
|
||||
mem_side=system.toL2Bus.slave[0]
|
||||
|
||||
[system.cpu0.interrupts]
|
||||
type=ArmInterrupts
|
||||
|
||||
[system.cpu0.itb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
size=64
|
||||
walker=system.cpu0.itb.walker
|
||||
|
||||
[system.cpu0.itb.walker]
|
||||
type=ArmTableWalker
|
||||
max_backoff=100000
|
||||
min_backoff=0
|
||||
sys=system
|
||||
port=system.toL2Bus.slave[2]
|
||||
|
||||
[system.cpu0.tracer]
|
||||
type=ExeTracer
|
||||
|
||||
[system.cpu1]
|
||||
type=TimingSimpleCPU
|
||||
children=dcache dtb icache interrupts itb tracer
|
||||
checker=Null
|
||||
clock=500
|
||||
cpu_id=1
|
||||
defer_registration=false
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu1.dtb
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
interrupts=system.cpu1.interrupts
|
||||
itb=system.cpu1.itb
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
phase=0
|
||||
profile=0
|
||||
progress_interval=0
|
||||
system=system
|
||||
tracer=system.cpu1.tracer
|
||||
workload=
|
||||
dcache_port=system.cpu1.dcache.cpu_side
|
||||
icache_port=system.cpu1.icache.cpu_side
|
||||
|
||||
[system.cpu1.dcache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=4
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=32768
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=8
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu1.dcache_port
|
||||
mem_side=system.toL2Bus.slave[5]
|
||||
|
||||
[system.cpu1.dtb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
size=64
|
||||
walker=system.cpu1.dtb.walker
|
||||
|
||||
[system.cpu1.dtb.walker]
|
||||
type=ArmTableWalker
|
||||
max_backoff=100000
|
||||
min_backoff=0
|
||||
sys=system
|
||||
port=system.toL2Bus.slave[7]
|
||||
|
||||
[system.cpu1.icache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=1
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=32768
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=8
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu1.icache_port
|
||||
mem_side=system.toL2Bus.slave[4]
|
||||
|
||||
[system.cpu1.interrupts]
|
||||
type=ArmInterrupts
|
||||
|
||||
[system.cpu1.itb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
size=64
|
||||
walker=system.cpu1.itb.walker
|
||||
|
||||
[system.cpu1.itb.walker]
|
||||
type=ArmTableWalker
|
||||
max_backoff=100000
|
||||
min_backoff=0
|
||||
sys=system
|
||||
port=system.toL2Bus.slave[6]
|
||||
|
||||
[system.cpu1.tracer]
|
||||
type=ExeTracer
|
||||
|
||||
[system.intrctrl]
|
||||
type=IntrControl
|
||||
sys=system
|
||||
|
||||
[system.iobus]
|
||||
type=NoncoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side
|
||||
slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
|
||||
|
||||
[system.iocache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:268435455
|
||||
assoc=8
|
||||
block_size=64
|
||||
forward_snoops=false
|
||||
hash_delay=1
|
||||
is_top_level=false
|
||||
latency=50000
|
||||
max_miss_count=0
|
||||
mshrs=20
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=1024
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=12
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.iobus.master[25]
|
||||
mem_side=system.membus.slave[1]
|
||||
|
||||
[system.l2c]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=8
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=false
|
||||
latency=10000
|
||||
max_miss_count=0
|
||||
mshrs=92
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=4194304
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=16
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.toL2Bus.master[0]
|
||||
mem_side=system.membus.slave[2]
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
children=badaddr_responder
|
||||
block_size=64
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
default=system.membus.badaddr_responder.pio
|
||||
master=system.bridge.slave system.realview.nvmem.port[0] system.physmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio
|
||||
slave=system.system_port system.iocache.mem_side system.l2c.mem_side
|
||||
|
||||
[system.membus.badaddr_responder]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=0
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=true
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=warn
|
||||
pio=system.membus.default
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
conf_table_reported=true
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.membus.master[2]
|
||||
|
||||
[system.realview]
|
||||
type=RealView
|
||||
children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
|
||||
intrctrl=system.intrctrl
|
||||
max_mem_size=268435456
|
||||
mem_start_addr=0
|
||||
pci_cfg_base=0
|
||||
system=system
|
||||
|
||||
[system.realview.a9scu]
|
||||
type=A9SCU
|
||||
pio_addr=520093696
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.membus.master[5]
|
||||
|
||||
[system.realview.aaci_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
ignore_access=false
|
||||
pio_addr=268451840
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.iobus.master[21]
|
||||
|
||||
[system.realview.cf_ctrl]
|
||||
type=IdeController
|
||||
BAR0=402653184
|
||||
BAR0LegacyIO=true
|
||||
BAR0Size=16
|
||||
BAR1=402653440
|
||||
BAR1LegacyIO=true
|
||||
BAR1Size=1
|
||||
BAR2=1
|
||||
BAR2LegacyIO=false
|
||||
BAR2Size=8
|
||||
BAR3=1
|
||||
BAR3LegacyIO=false
|
||||
BAR3Size=4
|
||||
BAR4=1
|
||||
BAR4LegacyIO=false
|
||||
BAR4Size=16
|
||||
BAR5=1
|
||||
BAR5LegacyIO=false
|
||||
BAR5Size=0
|
||||
BIST=0
|
||||
CacheLineSize=0
|
||||
CardbusCIS=0
|
||||
ClassCode=1
|
||||
Command=1
|
||||
DeviceID=28945
|
||||
ExpansionROM=0
|
||||
HeaderType=0
|
||||
InterruptLine=31
|
||||
InterruptPin=1
|
||||
LatencyTimer=0
|
||||
MaximumLatency=0
|
||||
MinimumGrant=0
|
||||
ProgIF=133
|
||||
Revision=0
|
||||
Status=640
|
||||
SubClassCode=1
|
||||
SubsystemID=0
|
||||
SubsystemVendorID=0
|
||||
VendorID=32902
|
||||
config_latency=20000
|
||||
ctrl_offset=2
|
||||
disks=system.cf0
|
||||
io_shift=1
|
||||
max_backoff_delay=10000000
|
||||
min_backoff_delay=4000
|
||||
pci_bus=2
|
||||
pci_dev=7
|
||||
pci_func=0
|
||||
pio_latency=1000
|
||||
platform=system.realview
|
||||
system=system
|
||||
config=system.iobus.master[8]
|
||||
dma=system.iobus.slave[2]
|
||||
pio=system.iobus.master[7]
|
||||
|
||||
[system.realview.clcd]
|
||||
type=Pl111
|
||||
amba_id=1315089
|
||||
clock=41667
|
||||
gic=system.realview.gic
|
||||
int_num=55
|
||||
max_backoff_delay=10000000
|
||||
min_backoff_delay=4000
|
||||
pio_addr=268566528
|
||||
pio_latency=10000
|
||||
system=system
|
||||
vnc=system.vncserver
|
||||
dma=system.iobus.slave[1]
|
||||
pio=system.iobus.master[4]
|
||||
|
||||
[system.realview.dmac_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
ignore_access=false
|
||||
pio_addr=268632064
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.iobus.master[9]
|
||||
|
||||
[system.realview.flash_fake]
|
||||
type=IsaFake
|
||||
fake_mem=true
|
||||
pio_addr=1073741824
|
||||
pio_latency=1000
|
||||
pio_size=536870912
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[24]
|
||||
|
||||
[system.realview.gic]
|
||||
type=Gic
|
||||
cpu_addr=520093952
|
||||
cpu_pio_delay=10000
|
||||
dist_addr=520097792
|
||||
dist_pio_delay=10000
|
||||
int_latency=10000
|
||||
it_lines=128
|
||||
platform=system.realview
|
||||
system=system
|
||||
pio=system.membus.master[3]
|
||||
|
||||
[system.realview.gpio0_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
ignore_access=false
|
||||
pio_addr=268513280
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.iobus.master[16]
|
||||
|
||||
[system.realview.gpio1_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
ignore_access=false
|
||||
pio_addr=268517376
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.iobus.master[17]
|
||||
|
||||
[system.realview.gpio2_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
ignore_access=false
|
||||
pio_addr=268521472
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.iobus.master[18]
|
||||
|
||||
[system.realview.kmi0]
|
||||
type=Pl050
|
||||
amba_id=1314896
|
||||
gic=system.realview.gic
|
||||
int_delay=1000000
|
||||
int_num=52
|
||||
is_mouse=false
|
||||
pio_addr=268460032
|
||||
pio_latency=1000
|
||||
system=system
|
||||
vnc=system.vncserver
|
||||
pio=system.iobus.master[5]
|
||||
|
||||
[system.realview.kmi1]
|
||||
type=Pl050
|
||||
amba_id=1314896
|
||||
gic=system.realview.gic
|
||||
int_delay=1000000
|
||||
int_num=53
|
||||
is_mouse=true
|
||||
pio_addr=268464128
|
||||
pio_latency=1000
|
||||
system=system
|
||||
vnc=system.vncserver
|
||||
pio=system.iobus.master[6]
|
||||
|
||||
[system.realview.l2x0_fake]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=520101888
|
||||
pio_latency=1000
|
||||
pio_size=4095
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.membus.master[4]
|
||||
|
||||
[system.realview.local_cpu_timer]
|
||||
type=CpuLocalTimer
|
||||
clock=1000
|
||||
gic=system.realview.gic
|
||||
int_num_timer=29
|
||||
int_num_watchdog=30
|
||||
pio_addr=520095232
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.membus.master[6]
|
||||
|
||||
[system.realview.mmc_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
ignore_access=false
|
||||
pio_addr=268455936
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.iobus.master[22]
|
||||
|
||||
[system.realview.nvmem]
|
||||
type=SimpleMemory
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
range=2147483648:2214592511
|
||||
zero=true
|
||||
port=system.membus.master[1]
|
||||
|
||||
[system.realview.realview_io]
|
||||
type=RealViewCtrl
|
||||
idreg=0
|
||||
pio_addr=268435456
|
||||
pio_latency=1000
|
||||
proc_id0=201326592
|
||||
proc_id1=201327138
|
||||
system=system
|
||||
pio=system.iobus.master[1]
|
||||
|
||||
[system.realview.rtc]
|
||||
type=PL031
|
||||
amba_id=3412017
|
||||
gic=system.realview.gic
|
||||
int_delay=100000
|
||||
int_num=42
|
||||
pio_addr=268529664
|
||||
pio_latency=1000
|
||||
system=system
|
||||
time=Thu Jan 1 00:00:00 2009
|
||||
pio=system.iobus.master[23]
|
||||
|
||||
[system.realview.sci_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
ignore_access=false
|
||||
pio_addr=268492800
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.iobus.master[20]
|
||||
|
||||
[system.realview.smc_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
ignore_access=false
|
||||
pio_addr=269357056
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.iobus.master[13]
|
||||
|
||||
[system.realview.sp810_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
ignore_access=true
|
||||
pio_addr=268439552
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.iobus.master[14]
|
||||
|
||||
[system.realview.ssp_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
ignore_access=false
|
||||
pio_addr=268488704
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.iobus.master[19]
|
||||
|
||||
[system.realview.timer0]
|
||||
type=Sp804
|
||||
amba_id=1316868
|
||||
clock0=1000000
|
||||
clock1=1000000
|
||||
gic=system.realview.gic
|
||||
int_num0=36
|
||||
int_num1=36
|
||||
pio_addr=268505088
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.iobus.master[2]
|
||||
|
||||
[system.realview.timer1]
|
||||
type=Sp804
|
||||
amba_id=1316868
|
||||
clock0=1000000
|
||||
clock1=1000000
|
||||
gic=system.realview.gic
|
||||
int_num0=37
|
||||
int_num1=37
|
||||
pio_addr=268509184
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.iobus.master[3]
|
||||
|
||||
[system.realview.uart]
|
||||
type=Pl011
|
||||
end_on_eot=false
|
||||
gic=system.realview.gic
|
||||
int_delay=100000
|
||||
int_num=44
|
||||
pio_addr=268472320
|
||||
pio_latency=1000
|
||||
platform=system.realview
|
||||
system=system
|
||||
terminal=system.terminal
|
||||
pio=system.iobus.master[0]
|
||||
|
||||
[system.realview.uart1_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
ignore_access=false
|
||||
pio_addr=268476416
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.iobus.master[10]
|
||||
|
||||
[system.realview.uart2_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
ignore_access=false
|
||||
pio_addr=268480512
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.iobus.master[11]
|
||||
|
||||
[system.realview.uart3_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
ignore_access=false
|
||||
pio_addr=268484608
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.iobus.master[12]
|
||||
|
||||
[system.realview.watchdog_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
ignore_access=false
|
||||
pio_addr=268500992
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.iobus.master[15]
|
||||
|
||||
[system.terminal]
|
||||
type=Terminal
|
||||
intr_control=system.intrctrl
|
||||
number=0
|
||||
output=true
|
||||
port=3456
|
||||
|
||||
[system.toL2Bus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
master=system.l2c.cpu_side
|
||||
slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port
|
||||
|
||||
[system.vncserver]
|
||||
type=VncServer
|
||||
frame_capture=false
|
||||
number=0
|
||||
port=5900
|
||||
|
||||
@ -0,0 +1,18 @@
|
||||
warn: Sockets disabled, not accepting vnc client connections
|
||||
warn: Sockets disabled, not accepting terminal connections
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: The clidr register always reports 0 caches.
|
||||
warn: clidr LoUIS field of 0b001 to match current ARM implementations.
|
||||
warn: The csselr register isn't implemented.
|
||||
warn: The ccsidr register isn't implemented and always reads as 0.
|
||||
warn: instruction 'mcr bpiallis' unimplemented
|
||||
warn: instruction 'mcr icialluis' unimplemented
|
||||
warn: instruction 'mcr dccimvac' unimplemented
|
||||
warn: instruction 'mcr dccmvau' unimplemented
|
||||
warn: instruction 'mcr icimvau' unimplemented
|
||||
warn: instruction 'mcr bpiallis' unimplemented
|
||||
warn: LCD dual screen mode not supported
|
||||
warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
|
||||
warn: instruction 'mcr icialluis' unimplemented
|
||||
warn: instruction 'mcr icialluis' unimplemented
|
||||
hack: be nice to actually delete the event here
|
||||
@ -0,0 +1,12 @@
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jun 4 2012 12:14:06
|
||||
gem5 started Jun 4 2012 17:26:08
|
||||
gem5 executing on zizzer
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
|
||||
info: Using bootloader at address 0x80000000
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 1169707043000 because m5_exit instruction encountered
|
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1 @@
|
||||
build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual FAILED!
|
||||
Binary file not shown.
@ -0,0 +1,672 @@
|
||||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
full_system=true
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
||||
[system]
|
||||
type=LinuxArmSystem
|
||||
children=bridge cf0 cpu intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver
|
||||
atags_addr=256
|
||||
boot_loader=/dist/m5/system/binaries/boot.arm
|
||||
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
|
||||
early_kernel_symbols=false
|
||||
flags_addr=268435504
|
||||
gic_cpu_addr=520093952
|
||||
init_param=0
|
||||
kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
|
||||
load_addr_mask=268435455
|
||||
machine_type=RealView_PBX
|
||||
mem_mode=timing
|
||||
memories=system.physmem system.realview.nvmem
|
||||
midr_regval=890224640
|
||||
num_work_ids=16
|
||||
readfile=tests/halt.sh
|
||||
symbolfile=
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.membus.slave[0]
|
||||
|
||||
[system.bridge]
|
||||
type=Bridge
|
||||
delay=50000
|
||||
nack_delay=4000
|
||||
ranges=268435456:520093695 1073741824:1610612735
|
||||
req_size=16
|
||||
resp_size=16
|
||||
write_ack=false
|
||||
master=system.iobus.slave[0]
|
||||
slave=system.membus.master[0]
|
||||
|
||||
[system.cf0]
|
||||
type=IdeDisk
|
||||
children=image
|
||||
delay=1000000
|
||||
driveID=master
|
||||
image=system.cf0.image
|
||||
|
||||
[system.cf0.image]
|
||||
type=CowDiskImage
|
||||
children=child
|
||||
child=system.cf0.image.child
|
||||
image_file=
|
||||
read_only=false
|
||||
table_size=65536
|
||||
|
||||
[system.cf0.image.child]
|
||||
type=RawDiskImage
|
||||
image_file=/dist/m5/system/disks/linux-arm-ael.img
|
||||
read_only=true
|
||||
|
||||
[system.cpu]
|
||||
type=TimingSimpleCPU
|
||||
children=dcache dtb icache interrupts itb tracer
|
||||
checker=Null
|
||||
clock=500
|
||||
cpu_id=0
|
||||
defer_registration=false
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
interrupts=system.cpu.interrupts
|
||||
itb=system.cpu.itb
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
phase=0
|
||||
profile=0
|
||||
progress_interval=0
|
||||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
workload=
|
||||
dcache_port=system.cpu.dcache.cpu_side
|
||||
icache_port=system.cpu.icache.cpu_side
|
||||
|
||||
[system.cpu.dcache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=4
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=32768
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=8
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.dcache_port
|
||||
mem_side=system.toL2Bus.slave[1]
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
size=64
|
||||
walker=system.cpu.dtb.walker
|
||||
|
||||
[system.cpu.dtb.walker]
|
||||
type=ArmTableWalker
|
||||
max_backoff=100000
|
||||
min_backoff=0
|
||||
sys=system
|
||||
port=system.toL2Bus.slave[3]
|
||||
|
||||
[system.cpu.icache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=1
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=32768
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=8
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.icache_port
|
||||
mem_side=system.toL2Bus.slave[0]
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=ArmInterrupts
|
||||
|
||||
[system.cpu.itb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
size=64
|
||||
walker=system.cpu.itb.walker
|
||||
|
||||
[system.cpu.itb.walker]
|
||||
type=ArmTableWalker
|
||||
max_backoff=100000
|
||||
min_backoff=0
|
||||
sys=system
|
||||
port=system.toL2Bus.slave[2]
|
||||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
|
||||
[system.intrctrl]
|
||||
type=IntrControl
|
||||
sys=system
|
||||
|
||||
[system.iobus]
|
||||
type=NoncoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side
|
||||
slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
|
||||
|
||||
[system.iocache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:268435455
|
||||
assoc=8
|
||||
block_size=64
|
||||
forward_snoops=false
|
||||
hash_delay=1
|
||||
is_top_level=false
|
||||
latency=50000
|
||||
max_miss_count=0
|
||||
mshrs=20
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=1024
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=12
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.iobus.master[25]
|
||||
mem_side=system.membus.slave[1]
|
||||
|
||||
[system.l2c]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=8
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=false
|
||||
latency=10000
|
||||
max_miss_count=0
|
||||
mshrs=92
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=4194304
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=16
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.toL2Bus.master[0]
|
||||
mem_side=system.membus.slave[2]
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
children=badaddr_responder
|
||||
block_size=64
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
default=system.membus.badaddr_responder.pio
|
||||
master=system.bridge.slave system.realview.nvmem.port[0] system.physmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio
|
||||
slave=system.system_port system.iocache.mem_side system.l2c.mem_side
|
||||
|
||||
[system.membus.badaddr_responder]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=0
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
ret_bad_addr=true
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=warn
|
||||
pio=system.membus.default
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
conf_table_reported=true
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.membus.master[2]
|
||||
|
||||
[system.realview]
|
||||
type=RealView
|
||||
children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
|
||||
intrctrl=system.intrctrl
|
||||
max_mem_size=268435456
|
||||
mem_start_addr=0
|
||||
pci_cfg_base=0
|
||||
system=system
|
||||
|
||||
[system.realview.a9scu]
|
||||
type=A9SCU
|
||||
pio_addr=520093696
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.membus.master[5]
|
||||
|
||||
[system.realview.aaci_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
ignore_access=false
|
||||
pio_addr=268451840
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.iobus.master[21]
|
||||
|
||||
[system.realview.cf_ctrl]
|
||||
type=IdeController
|
||||
BAR0=402653184
|
||||
BAR0LegacyIO=true
|
||||
BAR0Size=16
|
||||
BAR1=402653440
|
||||
BAR1LegacyIO=true
|
||||
BAR1Size=1
|
||||
BAR2=1
|
||||
BAR2LegacyIO=false
|
||||
BAR2Size=8
|
||||
BAR3=1
|
||||
BAR3LegacyIO=false
|
||||
BAR3Size=4
|
||||
BAR4=1
|
||||
BAR4LegacyIO=false
|
||||
BAR4Size=16
|
||||
BAR5=1
|
||||
BAR5LegacyIO=false
|
||||
BAR5Size=0
|
||||
BIST=0
|
||||
CacheLineSize=0
|
||||
CardbusCIS=0
|
||||
ClassCode=1
|
||||
Command=1
|
||||
DeviceID=28945
|
||||
ExpansionROM=0
|
||||
HeaderType=0
|
||||
InterruptLine=31
|
||||
InterruptPin=1
|
||||
LatencyTimer=0
|
||||
MaximumLatency=0
|
||||
MinimumGrant=0
|
||||
ProgIF=133
|
||||
Revision=0
|
||||
Status=640
|
||||
SubClassCode=1
|
||||
SubsystemID=0
|
||||
SubsystemVendorID=0
|
||||
VendorID=32902
|
||||
config_latency=20000
|
||||
ctrl_offset=2
|
||||
disks=system.cf0
|
||||
io_shift=1
|
||||
max_backoff_delay=10000000
|
||||
min_backoff_delay=4000
|
||||
pci_bus=2
|
||||
pci_dev=7
|
||||
pci_func=0
|
||||
pio_latency=1000
|
||||
platform=system.realview
|
||||
system=system
|
||||
config=system.iobus.master[8]
|
||||
dma=system.iobus.slave[2]
|
||||
pio=system.iobus.master[7]
|
||||
|
||||
[system.realview.clcd]
|
||||
type=Pl111
|
||||
amba_id=1315089
|
||||
clock=41667
|
||||
gic=system.realview.gic
|
||||
int_num=55
|
||||
max_backoff_delay=10000000
|
||||
min_backoff_delay=4000
|
||||
pio_addr=268566528
|
||||
pio_latency=10000
|
||||
system=system
|
||||
vnc=system.vncserver
|
||||
dma=system.iobus.slave[1]
|
||||
pio=system.iobus.master[4]
|
||||
|
||||
[system.realview.dmac_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
ignore_access=false
|
||||
pio_addr=268632064
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.iobus.master[9]
|
||||
|
||||
[system.realview.flash_fake]
|
||||
type=IsaFake
|
||||
fake_mem=true
|
||||
pio_addr=1073741824
|
||||
pio_latency=1000
|
||||
pio_size=536870912
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[24]
|
||||
|
||||
[system.realview.gic]
|
||||
type=Gic
|
||||
cpu_addr=520093952
|
||||
cpu_pio_delay=10000
|
||||
dist_addr=520097792
|
||||
dist_pio_delay=10000
|
||||
int_latency=10000
|
||||
it_lines=128
|
||||
platform=system.realview
|
||||
system=system
|
||||
pio=system.membus.master[3]
|
||||
|
||||
[system.realview.gpio0_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
ignore_access=false
|
||||
pio_addr=268513280
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.iobus.master[16]
|
||||
|
||||
[system.realview.gpio1_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
ignore_access=false
|
||||
pio_addr=268517376
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.iobus.master[17]
|
||||
|
||||
[system.realview.gpio2_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
ignore_access=false
|
||||
pio_addr=268521472
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.iobus.master[18]
|
||||
|
||||
[system.realview.kmi0]
|
||||
type=Pl050
|
||||
amba_id=1314896
|
||||
gic=system.realview.gic
|
||||
int_delay=1000000
|
||||
int_num=52
|
||||
is_mouse=false
|
||||
pio_addr=268460032
|
||||
pio_latency=1000
|
||||
system=system
|
||||
vnc=system.vncserver
|
||||
pio=system.iobus.master[5]
|
||||
|
||||
[system.realview.kmi1]
|
||||
type=Pl050
|
||||
amba_id=1314896
|
||||
gic=system.realview.gic
|
||||
int_delay=1000000
|
||||
int_num=53
|
||||
is_mouse=true
|
||||
pio_addr=268464128
|
||||
pio_latency=1000
|
||||
system=system
|
||||
vnc=system.vncserver
|
||||
pio=system.iobus.master[6]
|
||||
|
||||
[system.realview.l2x0_fake]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=520101888
|
||||
pio_latency=1000
|
||||
pio_size=4095
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.membus.master[4]
|
||||
|
||||
[system.realview.local_cpu_timer]
|
||||
type=CpuLocalTimer
|
||||
clock=1000
|
||||
gic=system.realview.gic
|
||||
int_num_timer=29
|
||||
int_num_watchdog=30
|
||||
pio_addr=520095232
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.membus.master[6]
|
||||
|
||||
[system.realview.mmc_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
ignore_access=false
|
||||
pio_addr=268455936
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.iobus.master[22]
|
||||
|
||||
[system.realview.nvmem]
|
||||
type=SimpleMemory
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
range=2147483648:2214592511
|
||||
zero=true
|
||||
port=system.membus.master[1]
|
||||
|
||||
[system.realview.realview_io]
|
||||
type=RealViewCtrl
|
||||
idreg=0
|
||||
pio_addr=268435456
|
||||
pio_latency=1000
|
||||
proc_id0=201326592
|
||||
proc_id1=201327138
|
||||
system=system
|
||||
pio=system.iobus.master[1]
|
||||
|
||||
[system.realview.rtc]
|
||||
type=PL031
|
||||
amba_id=3412017
|
||||
gic=system.realview.gic
|
||||
int_delay=100000
|
||||
int_num=42
|
||||
pio_addr=268529664
|
||||
pio_latency=1000
|
||||
system=system
|
||||
time=Thu Jan 1 00:00:00 2009
|
||||
pio=system.iobus.master[23]
|
||||
|
||||
[system.realview.sci_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
ignore_access=false
|
||||
pio_addr=268492800
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.iobus.master[20]
|
||||
|
||||
[system.realview.smc_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
ignore_access=false
|
||||
pio_addr=269357056
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.iobus.master[13]
|
||||
|
||||
[system.realview.sp810_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
ignore_access=true
|
||||
pio_addr=268439552
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.iobus.master[14]
|
||||
|
||||
[system.realview.ssp_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
ignore_access=false
|
||||
pio_addr=268488704
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.iobus.master[19]
|
||||
|
||||
[system.realview.timer0]
|
||||
type=Sp804
|
||||
amba_id=1316868
|
||||
clock0=1000000
|
||||
clock1=1000000
|
||||
gic=system.realview.gic
|
||||
int_num0=36
|
||||
int_num1=36
|
||||
pio_addr=268505088
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.iobus.master[2]
|
||||
|
||||
[system.realview.timer1]
|
||||
type=Sp804
|
||||
amba_id=1316868
|
||||
clock0=1000000
|
||||
clock1=1000000
|
||||
gic=system.realview.gic
|
||||
int_num0=37
|
||||
int_num1=37
|
||||
pio_addr=268509184
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.iobus.master[3]
|
||||
|
||||
[system.realview.uart]
|
||||
type=Pl011
|
||||
end_on_eot=false
|
||||
gic=system.realview.gic
|
||||
int_delay=100000
|
||||
int_num=44
|
||||
pio_addr=268472320
|
||||
pio_latency=1000
|
||||
platform=system.realview
|
||||
system=system
|
||||
terminal=system.terminal
|
||||
pio=system.iobus.master[0]
|
||||
|
||||
[system.realview.uart1_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
ignore_access=false
|
||||
pio_addr=268476416
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.iobus.master[10]
|
||||
|
||||
[system.realview.uart2_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
ignore_access=false
|
||||
pio_addr=268480512
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.iobus.master[11]
|
||||
|
||||
[system.realview.uart3_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
ignore_access=false
|
||||
pio_addr=268484608
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.iobus.master[12]
|
||||
|
||||
[system.realview.watchdog_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
ignore_access=false
|
||||
pio_addr=268500992
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.iobus.master[15]
|
||||
|
||||
[system.terminal]
|
||||
type=Terminal
|
||||
intr_control=system.intrctrl
|
||||
number=0
|
||||
output=true
|
||||
port=3456
|
||||
|
||||
[system.toL2Bus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
master=system.l2c.cpu_side
|
||||
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
|
||||
|
||||
[system.vncserver]
|
||||
type=VncServer
|
||||
frame_capture=false
|
||||
number=0
|
||||
port=5900
|
||||
|
||||
@ -0,0 +1,17 @@
|
||||
warn: Sockets disabled, not accepting vnc client connections
|
||||
warn: Sockets disabled, not accepting terminal connections
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: The clidr register always reports 0 caches.
|
||||
warn: clidr LoUIS field of 0b001 to match current ARM implementations.
|
||||
warn: The csselr register isn't implemented.
|
||||
warn: The ccsidr register isn't implemented and always reads as 0.
|
||||
warn: instruction 'mcr bpiallis' unimplemented
|
||||
warn: instruction 'mcr icialluis' unimplemented
|
||||
warn: instruction 'mcr dccimvac' unimplemented
|
||||
warn: instruction 'mcr dccmvau' unimplemented
|
||||
warn: instruction 'mcr icimvau' unimplemented
|
||||
warn: LCD dual screen mode not supported
|
||||
warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
|
||||
warn: instruction 'mcr icialluis' unimplemented
|
||||
warn: instruction 'mcr bpiallis' unimplemented
|
||||
hack: be nice to actually delete the event here
|
||||
@ -0,0 +1,12 @@
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jun 4 2012 12:14:06
|
||||
gem5 started Jun 4 2012 17:25:42
|
||||
gem5 executing on zizzer
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
|
||||
info: Using bootloader at address 0x80000000
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 2591419000000 because m5_exit instruction encountered
|
||||
@ -0,0 +1,622 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 2.591419 # Number of seconds simulated
|
||||
sim_ticks 2591419000000 # Number of ticks simulated
|
||||
final_tick 2591419000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 555808 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 709857 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 24337050134 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 383104 # Number of bytes of host memory used
|
||||
host_seconds 106.48 # Real time elapsed on the host
|
||||
sim_insts 59182652 # Number of instructions simulated
|
||||
sim_ops 75585847 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::realview.clcd 122683392 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.dtb.walker 1408 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.itb.walker 768 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.inst 955744 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 9990864 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 133632176 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 955744 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 955744 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 6584000 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 9600072 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::realview.clcd 15335424 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.dtb.walker 22 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.itb.walker 12 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.inst 21136 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 156141 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 15512735 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 102875 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 856893 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::realview.clcd 47342167 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.dtb.walker 543 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.itb.walker 296 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 368811 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 3855364 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 51567182 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 368811 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 368811 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 2540693 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::cpu.data 1163869 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 3704562 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 2540693 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::realview.clcd 47342167 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.dtb.walker 543 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.itb.walker 296 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 368811 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 5019233 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 55271744 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory
|
||||
system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
|
||||
system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory
|
||||
system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
|
||||
system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory
|
||||
system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
|
||||
system.realview.nvmem.bw_read::cpu.inst 8 # Total read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_inst_read::cpu.inst 8 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.l2c.replacements 117210 # number of replacements
|
||||
system.l2c.tagsinuse 24850.634634 # Cycle average of tags in use
|
||||
system.l2c.total_refs 1536782 # Total number of references to valid blocks.
|
||||
system.l2c.sampled_refs 146347 # Sample count of references to valid blocks.
|
||||
system.l2c.avg_refs 10.500946 # Average number of references to valid blocks.
|
||||
system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.l2c.occ_blocks::writebacks 14582.980264 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu.dtb.walker 6.964045 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu.itb.walker 0.968003 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu.inst 5130.485110 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu.data 5129.237211 # Average occupied blocks per requestor
|
||||
system.l2c.occ_percent::writebacks 0.222519 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu.dtb.walker 0.000106 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu.itb.walker 0.000015 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu.inst 0.078285 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu.data 0.078266 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::total 0.379191 # Average percentage of cache occupancy
|
||||
system.l2c.ReadReq_hits::cpu.dtb.walker 8714 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu.itb.walker 3541 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu.inst 839785 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu.data 361146 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::total 1213186 # number of ReadReq hits
|
||||
system.l2c.Writeback_hits::writebacks 611793 # number of Writeback hits
|
||||
system.l2c.Writeback_hits::total 611793 # number of Writeback hits
|
||||
system.l2c.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits
|
||||
system.l2c.UpgradeReq_hits::total 26 # number of UpgradeReq hits
|
||||
system.l2c.ReadExReq_hits::cpu.data 106840 # number of ReadExReq hits
|
||||
system.l2c.ReadExReq_hits::total 106840 # number of ReadExReq hits
|
||||
system.l2c.demand_hits::cpu.dtb.walker 8714 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu.itb.walker 3541 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu.inst 839785 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu.data 467986 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::total 1320026 # number of demand (read+write) hits
|
||||
system.l2c.overall_hits::cpu.dtb.walker 8714 # number of overall hits
|
||||
system.l2c.overall_hits::cpu.itb.walker 3541 # number of overall hits
|
||||
system.l2c.overall_hits::cpu.inst 839785 # number of overall hits
|
||||
system.l2c.overall_hits::cpu.data 467986 # number of overall hits
|
||||
system.l2c.overall_hits::total 1320026 # number of overall hits
|
||||
system.l2c.ReadReq_misses::cpu.dtb.walker 22 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu.itb.walker 12 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu.inst 14520 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu.data 16989 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::total 31543 # number of ReadReq misses
|
||||
system.l2c.UpgradeReq_misses::cpu.data 2871 # number of UpgradeReq misses
|
||||
system.l2c.UpgradeReq_misses::total 2871 # number of UpgradeReq misses
|
||||
system.l2c.ReadExReq_misses::cpu.data 140746 # number of ReadExReq misses
|
||||
system.l2c.ReadExReq_misses::total 140746 # number of ReadExReq misses
|
||||
system.l2c.demand_misses::cpu.dtb.walker 22 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu.itb.walker 12 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu.inst 14520 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu.data 157735 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::total 172289 # number of demand (read+write) misses
|
||||
system.l2c.overall_misses::cpu.dtb.walker 22 # number of overall misses
|
||||
system.l2c.overall_misses::cpu.itb.walker 12 # number of overall misses
|
||||
system.l2c.overall_misses::cpu.inst 14520 # number of overall misses
|
||||
system.l2c.overall_misses::cpu.data 157735 # number of overall misses
|
||||
system.l2c.overall_misses::total 172289 # number of overall misses
|
||||
system.l2c.ReadReq_miss_latency::cpu.dtb.walker 1144000 # number of ReadReq miss cycles
|
||||
system.l2c.ReadReq_miss_latency::cpu.itb.walker 624000 # number of ReadReq miss cycles
|
||||
system.l2c.ReadReq_miss_latency::cpu.inst 758001000 # number of ReadReq miss cycles
|
||||
system.l2c.ReadReq_miss_latency::cpu.data 885358500 # number of ReadReq miss cycles
|
||||
system.l2c.ReadReq_miss_latency::total 1645127500 # number of ReadReq miss cycles
|
||||
system.l2c.UpgradeReq_miss_latency::cpu.data 1040000 # number of UpgradeReq miss cycles
|
||||
system.l2c.UpgradeReq_miss_latency::total 1040000 # number of UpgradeReq miss cycles
|
||||
system.l2c.ReadExReq_miss_latency::cpu.data 7328827500 # number of ReadExReq miss cycles
|
||||
system.l2c.ReadExReq_miss_latency::total 7328827500 # number of ReadExReq miss cycles
|
||||
system.l2c.demand_miss_latency::cpu.dtb.walker 1144000 # number of demand (read+write) miss cycles
|
||||
system.l2c.demand_miss_latency::cpu.itb.walker 624000 # number of demand (read+write) miss cycles
|
||||
system.l2c.demand_miss_latency::cpu.inst 758001000 # number of demand (read+write) miss cycles
|
||||
system.l2c.demand_miss_latency::cpu.data 8214186000 # number of demand (read+write) miss cycles
|
||||
system.l2c.demand_miss_latency::total 8973955000 # number of demand (read+write) miss cycles
|
||||
system.l2c.overall_miss_latency::cpu.dtb.walker 1144000 # number of overall miss cycles
|
||||
system.l2c.overall_miss_latency::cpu.itb.walker 624000 # number of overall miss cycles
|
||||
system.l2c.overall_miss_latency::cpu.inst 758001000 # number of overall miss cycles
|
||||
system.l2c.overall_miss_latency::cpu.data 8214186000 # number of overall miss cycles
|
||||
system.l2c.overall_miss_latency::total 8973955000 # number of overall miss cycles
|
||||
system.l2c.ReadReq_accesses::cpu.dtb.walker 8736 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::cpu.itb.walker 3553 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::cpu.inst 854305 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::cpu.data 378135 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::total 1244729 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.Writeback_accesses::writebacks 611793 # number of Writeback accesses(hits+misses)
|
||||
system.l2c.Writeback_accesses::total 611793 # number of Writeback accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_accesses::cpu.data 2897 # number of UpgradeReq accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_accesses::total 2897 # number of UpgradeReq accesses(hits+misses)
|
||||
system.l2c.ReadExReq_accesses::cpu.data 247586 # number of ReadExReq accesses(hits+misses)
|
||||
system.l2c.ReadExReq_accesses::total 247586 # number of ReadExReq accesses(hits+misses)
|
||||
system.l2c.demand_accesses::cpu.dtb.walker 8736 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu.itb.walker 3553 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu.inst 854305 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu.data 625721 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::total 1492315 # number of demand (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu.dtb.walker 8736 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu.itb.walker 3553 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu.inst 854305 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu.data 625721 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::total 1492315 # number of overall (read+write) accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.002518 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.003377 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu.inst 0.016996 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu.data 0.044928 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::total 0.025341 # miss rate for ReadReq accesses
|
||||
system.l2c.UpgradeReq_miss_rate::cpu.data 0.991025 # miss rate for UpgradeReq accesses
|
||||
system.l2c.UpgradeReq_miss_rate::total 0.991025 # miss rate for UpgradeReq accesses
|
||||
system.l2c.ReadExReq_miss_rate::cpu.data 0.568473 # miss rate for ReadExReq accesses
|
||||
system.l2c.ReadExReq_miss_rate::total 0.568473 # miss rate for ReadExReq accesses
|
||||
system.l2c.demand_miss_rate::cpu.dtb.walker 0.002518 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu.itb.walker 0.003377 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu.inst 0.016996 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu.data 0.252085 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::total 0.115451 # miss rate for demand accesses
|
||||
system.l2c.overall_miss_rate::cpu.dtb.walker 0.002518 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu.itb.walker 0.003377 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu.inst 0.016996 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu.data 0.252085 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::total 0.115451 # miss rate for overall accesses
|
||||
system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52000 # average ReadReq miss latency
|
||||
system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 52000 # average ReadReq miss latency
|
||||
system.l2c.ReadReq_avg_miss_latency::cpu.inst 52203.925620 # average ReadReq miss latency
|
||||
system.l2c.ReadReq_avg_miss_latency::cpu.data 52113.632350 # average ReadReq miss latency
|
||||
system.l2c.ReadReq_avg_miss_latency::total 52155.074026 # average ReadReq miss latency
|
||||
system.l2c.UpgradeReq_avg_miss_latency::cpu.data 362.243121 # average UpgradeReq miss latency
|
||||
system.l2c.UpgradeReq_avg_miss_latency::total 362.243121 # average UpgradeReq miss latency
|
||||
system.l2c.ReadExReq_avg_miss_latency::cpu.data 52071.302204 # average ReadExReq miss latency
|
||||
system.l2c.ReadExReq_avg_miss_latency::total 52071.302204 # average ReadExReq miss latency
|
||||
system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52000 # average overall miss latency
|
||||
system.l2c.demand_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency
|
||||
system.l2c.demand_avg_miss_latency::cpu.inst 52203.925620 # average overall miss latency
|
||||
system.l2c.demand_avg_miss_latency::cpu.data 52075.861413 # average overall miss latency
|
||||
system.l2c.demand_avg_miss_latency::total 52086.639310 # average overall miss latency
|
||||
system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52000 # average overall miss latency
|
||||
system.l2c.overall_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency
|
||||
system.l2c.overall_avg_miss_latency::cpu.inst 52203.925620 # average overall miss latency
|
||||
system.l2c.overall_avg_miss_latency::cpu.data 52075.861413 # average overall miss latency
|
||||
system.l2c.overall_avg_miss_latency::total 52086.639310 # average overall miss latency
|
||||
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.l2c.fast_writes 0 # number of fast writes performed
|
||||
system.l2c.cache_copies 0 # number of cache copies performed
|
||||
system.l2c.writebacks::writebacks 102875 # number of writebacks
|
||||
system.l2c.writebacks::total 102875 # number of writebacks
|
||||
system.l2c.ReadReq_mshr_misses::cpu.dtb.walker 22 # number of ReadReq MSHR misses
|
||||
system.l2c.ReadReq_mshr_misses::cpu.itb.walker 12 # number of ReadReq MSHR misses
|
||||
system.l2c.ReadReq_mshr_misses::cpu.inst 14520 # number of ReadReq MSHR misses
|
||||
system.l2c.ReadReq_mshr_misses::cpu.data 16989 # number of ReadReq MSHR misses
|
||||
system.l2c.ReadReq_mshr_misses::total 31543 # number of ReadReq MSHR misses
|
||||
system.l2c.UpgradeReq_mshr_misses::cpu.data 2871 # number of UpgradeReq MSHR misses
|
||||
system.l2c.UpgradeReq_mshr_misses::total 2871 # number of UpgradeReq MSHR misses
|
||||
system.l2c.ReadExReq_mshr_misses::cpu.data 140746 # number of ReadExReq MSHR misses
|
||||
system.l2c.ReadExReq_mshr_misses::total 140746 # number of ReadExReq MSHR misses
|
||||
system.l2c.demand_mshr_misses::cpu.dtb.walker 22 # number of demand (read+write) MSHR misses
|
||||
system.l2c.demand_mshr_misses::cpu.itb.walker 12 # number of demand (read+write) MSHR misses
|
||||
system.l2c.demand_mshr_misses::cpu.inst 14520 # number of demand (read+write) MSHR misses
|
||||
system.l2c.demand_mshr_misses::cpu.data 157735 # number of demand (read+write) MSHR misses
|
||||
system.l2c.demand_mshr_misses::total 172289 # number of demand (read+write) MSHR misses
|
||||
system.l2c.overall_mshr_misses::cpu.dtb.walker 22 # number of overall MSHR misses
|
||||
system.l2c.overall_mshr_misses::cpu.itb.walker 12 # number of overall MSHR misses
|
||||
system.l2c.overall_mshr_misses::cpu.inst 14520 # number of overall MSHR misses
|
||||
system.l2c.overall_mshr_misses::cpu.data 157735 # number of overall MSHR misses
|
||||
system.l2c.overall_mshr_misses::total 172289 # number of overall MSHR misses
|
||||
system.l2c.ReadReq_mshr_miss_latency::cpu.dtb.walker 880000 # number of ReadReq MSHR miss cycles
|
||||
system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker 480000 # number of ReadReq MSHR miss cycles
|
||||
system.l2c.ReadReq_mshr_miss_latency::cpu.inst 583755000 # number of ReadReq MSHR miss cycles
|
||||
system.l2c.ReadReq_mshr_miss_latency::cpu.data 681490000 # number of ReadReq MSHR miss cycles
|
||||
system.l2c.ReadReq_mshr_miss_latency::total 1266605000 # number of ReadReq MSHR miss cycles
|
||||
system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 114997000 # number of UpgradeReq MSHR miss cycles
|
||||
system.l2c.UpgradeReq_mshr_miss_latency::total 114997000 # number of UpgradeReq MSHR miss cycles
|
||||
system.l2c.ReadExReq_mshr_miss_latency::cpu.data 5639875000 # number of ReadExReq MSHR miss cycles
|
||||
system.l2c.ReadExReq_mshr_miss_latency::total 5639875000 # number of ReadExReq MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_latency::cpu.dtb.walker 880000 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_latency::cpu.itb.walker 480000 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_latency::cpu.inst 583755000 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_latency::cpu.data 6321365000 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_latency::total 6906480000 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency::cpu.dtb.walker 880000 # number of overall MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency::cpu.itb.walker 480000 # number of overall MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency::cpu.inst 583755000 # number of overall MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency::cpu.data 6321365000 # number of overall MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency::total 6906480000 # number of overall MSHR miss cycles
|
||||
system.l2c.ReadReq_mshr_uncacheable_latency::cpu.inst 264840000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 131544749000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.l2c.ReadReq_mshr_uncacheable_latency::total 131809589000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 31207839500 # number of WriteReq MSHR uncacheable cycles
|
||||
system.l2c.WriteReq_mshr_uncacheable_latency::total 31207839500 # number of WriteReq MSHR uncacheable cycles
|
||||
system.l2c.overall_mshr_uncacheable_latency::cpu.inst 264840000 # number of overall MSHR uncacheable cycles
|
||||
system.l2c.overall_mshr_uncacheable_latency::cpu.data 162752588500 # number of overall MSHR uncacheable cycles
|
||||
system.l2c.overall_mshr_uncacheable_latency::total 163017428500 # number of overall MSHR uncacheable cycles
|
||||
system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.002518 # mshr miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.003377 # mshr miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.016996 # mshr miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.044928 # mshr miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_mshr_miss_rate::total 0.025341 # mshr miss rate for ReadReq accesses
|
||||
system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.991025 # mshr miss rate for UpgradeReq accesses
|
||||
system.l2c.UpgradeReq_mshr_miss_rate::total 0.991025 # mshr miss rate for UpgradeReq accesses
|
||||
system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.568473 # mshr miss rate for ReadExReq accesses
|
||||
system.l2c.ReadExReq_mshr_miss_rate::total 0.568473 # mshr miss rate for ReadExReq accesses
|
||||
system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.002518 # mshr miss rate for demand accesses
|
||||
system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.003377 # mshr miss rate for demand accesses
|
||||
system.l2c.demand_mshr_miss_rate::cpu.inst 0.016996 # mshr miss rate for demand accesses
|
||||
system.l2c.demand_mshr_miss_rate::cpu.data 0.252085 # mshr miss rate for demand accesses
|
||||
system.l2c.demand_mshr_miss_rate::total 0.115451 # mshr miss rate for demand accesses
|
||||
system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.002518 # mshr miss rate for overall accesses
|
||||
system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.003377 # mshr miss rate for overall accesses
|
||||
system.l2c.overall_mshr_miss_rate::cpu.inst 0.016996 # mshr miss rate for overall accesses
|
||||
system.l2c.overall_mshr_miss_rate::cpu.data 0.252085 # mshr miss rate for overall accesses
|
||||
system.l2c.overall_mshr_miss_rate::total 0.115451 # mshr miss rate for overall accesses
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average ReadReq mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40000 # average ReadReq mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40203.512397 # average ReadReq mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40113.602920 # average ReadReq mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::total 40154.867958 # average ReadReq mshr miss latency
|
||||
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40054.684779 # average UpgradeReq mshr miss latency
|
||||
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40054.684779 # average UpgradeReq mshr miss latency
|
||||
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40071.298651 # average ReadExReq mshr miss latency
|
||||
system.l2c.ReadExReq_avg_mshr_miss_latency::total 40071.298651 # average ReadExReq mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40203.512397 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu.data 40075.855073 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::total 40086.598680 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40203.512397 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu.data 40075.855073 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::total 40086.598680 # average overall mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
|
||||
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
|
||||
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
||||
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
|
||||
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
||||
system.l2c.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
|
||||
system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
|
||||
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
||||
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
||||
system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
|
||||
system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
|
||||
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
|
||||
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
|
||||
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
|
||||
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.dtb.read_hits 14995950 # DTB read hits
|
||||
system.cpu.dtb.read_misses 7342 # DTB read misses
|
||||
system.cpu.dtb.write_hits 11230967 # DTB write hits
|
||||
system.cpu.dtb.write_misses 2209 # DTB write misses
|
||||
system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed
|
||||
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
|
||||
system.cpu.dtb.flush_entries 3488 # Number of entries that have been flushed from TLB
|
||||
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.dtb.prefetch_faults 184 # Number of TLB faults due to prefetch
|
||||
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.dtb.read_accesses 15003292 # DTB read accesses
|
||||
system.cpu.dtb.write_accesses 11233176 # DTB write accesses
|
||||
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
|
||||
system.cpu.dtb.hits 26226917 # DTB hits
|
||||
system.cpu.dtb.misses 9551 # DTB misses
|
||||
system.cpu.dtb.accesses 26236468 # DTB accesses
|
||||
system.cpu.itb.inst_hits 60464458 # ITB inst hits
|
||||
system.cpu.itb.inst_misses 4471 # ITB inst misses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.write_hits 0 # DTB write hits
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed
|
||||
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
|
||||
system.cpu.itb.flush_entries 2343 # Number of entries that have been flushed from TLB
|
||||
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.itb.inst_accesses 60468929 # ITB inst accesses
|
||||
system.cpu.itb.hits 60464458 # DTB hits
|
||||
system.cpu.itb.misses 4471 # DTB misses
|
||||
system.cpu.itb.accesses 60468929 # DTB accesses
|
||||
system.cpu.numCycles 5182838000 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 59182652 # Number of instructions committed
|
||||
system.cpu.committedOps 75585847 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 68355333 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 1976025 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 7653656 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 68355333 # number of integer instructions
|
||||
system.cpu.num_fp_insts 10269 # number of float instructions
|
||||
system.cpu.num_int_register_reads 391421263 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 73137347 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written
|
||||
system.cpu.num_mem_refs 27394170 # number of memory refs
|
||||
system.cpu.num_load_insts 15659823 # Number of load instructions
|
||||
system.cpu.num_store_insts 11734347 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 4573988502.570235 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 608849497.429765 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 0.117474 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0.882526 # Percentage of idle cycles
|
||||
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
||||
system.cpu.kern.inst.quiesce 82997 # number of quiesce instructions executed
|
||||
system.cpu.icache.replacements 855402 # number of replacements
|
||||
system.cpu.icache.tagsinuse 510.943261 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 59608544 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 855914 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 69.643146 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 18524424000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 510.943261 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.997936 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.997936 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 59608544 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 59608544 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 59608544 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 59608544 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 59608544 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 59608544 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 855914 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 855914 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 855914 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 855914 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 855914 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 855914 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 12584924000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 12584924000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 12584924000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 12584924000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 12584924000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 12584924000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 60464458 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 60464458 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 60464458 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 60464458 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 60464458 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 60464458 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014156 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.014156 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.014156 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.014156 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.014156 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.014156 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14703.491239 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 14703.491239 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 14703.491239 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 14703.491239 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 14703.491239 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 14703.491239 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks::writebacks 45705 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 45705 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 855914 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 855914 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 855914 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 855914 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 855914 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 855914 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10014791000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 10014791000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10014791000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 10014791000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10014791000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 10014791000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 350913000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 350913000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 350913000 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency::total 350913000 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014156 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014156 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014156 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.014156 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014156 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.014156 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11700.697734 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11700.697734 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11700.697734 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 11700.697734 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11700.697734 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 11700.697734 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 627094 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 511.875591 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 23655637 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 627606 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 37.691859 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 660309000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 511.875591 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.999757 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.999757 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 13195546 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 13195546 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 9973168 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 9973168 # number of WriteReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::cpu.data 236327 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::total 236327 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::cpu.data 247699 # number of StoreCondReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::total 247699 # number of StoreCondReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 23168714 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 23168714 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 23168714 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 23168714 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 368647 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 368647 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 250483 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 250483 # number of WriteReq misses
|
||||
system.cpu.dcache.LoadLockedReq_misses::cpu.data 11373 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.LoadLockedReq_misses::total 11373 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 619130 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 619130 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 619130 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 619130 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 5836151500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 5836151500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 9546175500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 9546175500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 185299500 # number of LoadLockedReq miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_miss_latency::total 185299500 # number of LoadLockedReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 15382327000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 15382327000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 15382327000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 15382327000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 13564193 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 13564193 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 10223651 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 10223651 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247700 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::total 247700 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::cpu.data 247699 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::total 247699 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 23787844 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 23787844 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 23787844 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 23787844 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.027178 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.027178 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024500 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.024500 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045914 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045914 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.026027 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.026027 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.026027 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.026027 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15831.273549 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 15831.273549 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38111.071410 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 38111.071410 # average WriteReq miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16292.930625 # average LoadLockedReq miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16292.930625 # average LoadLockedReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 24845.068079 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 24845.068079 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 24845.068079 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 24845.068079 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 566088 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 566088 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 368647 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 368647 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250483 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 250483 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11373 # number of LoadLockedReq MSHR misses
|
||||
system.cpu.dcache.LoadLockedReq_mshr_misses::total 11373 # number of LoadLockedReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 619130 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 619130 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 619130 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 619130 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4730079000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 4730079000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8794683000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 8794683000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 151180500 # number of LoadLockedReq MSHR miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 151180500 # number of LoadLockedReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13524762000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 13524762000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13524762000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 13524762000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 146938040000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 146938040000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 40368528500 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 40368528500 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 187306568500 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency::total 187306568500 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027178 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027178 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024500 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024500 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.045914 # mshr miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.045914 # mshr miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026027 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.026027 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026027 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.026027 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12830.916839 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12830.916839 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35110.897746 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35110.897746 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13292.930625 # average LoadLockedReq mshr miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13292.930625 # average LoadLockedReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21844.785425 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 21844.785425 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21844.785425 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 21844.785425 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.iocache.replacements 0 # number of replacements
|
||||
system.iocache.tagsinuse 0 # Cycle average of tags in use
|
||||
system.iocache.total_refs 0 # Total number of references to valid blocks.
|
||||
system.iocache.sampled_refs 0 # Sample count of references to valid blocks.
|
||||
system.iocache.avg_refs nan # Average number of references to valid blocks.
|
||||
system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.iocache.fast_writes 0 # number of fast writes performed
|
||||
system.iocache.cache_copies 0 # number of cache copies performed
|
||||
system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1342278175263 # number of ReadReq MSHR uncacheable cycles
|
||||
system.iocache.ReadReq_mshr_uncacheable_latency::total 1342278175263 # number of ReadReq MSHR uncacheable cycles
|
||||
system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1342278175263 # number of overall MSHR uncacheable cycles
|
||||
system.iocache.overall_mshr_uncacheable_latency::total 1342278175263 # number of overall MSHR uncacheable cycles
|
||||
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
|
||||
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
||||
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
|
||||
system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
||||
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
@ -0,0 +1 @@
|
||||
build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing FAILED!
|
||||
Binary file not shown.
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,9 @@
|
||||
warn: Sockets disabled, not accepting terminal connections
|
||||
warn: Reading current count from inactive timer.
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: Don't know what interrupt to clear for console.
|
||||
warn: instruction 'fxsave' unimplemented
|
||||
warn: Tried to clear PCI interrupt 14
|
||||
warn: Unknown mouse command 0xe1.
|
||||
warn: instruction 'wbinvd' unimplemented
|
||||
hack: be nice to actually delete the event here
|
||||
@ -0,0 +1,13 @@
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jun 4 2012 13:44:28
|
||||
gem5 started Jun 4 2012 15:04:41
|
||||
gem5 executing on zizzer
|
||||
command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-atomic -re tests/run.py build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-atomic
|
||||
warning: add_child('terminal'): child 'terminal' already has parent
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
|
||||
0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 5112043255000 because m5_exit instruction encountered
|
||||
@ -0,0 +1,426 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 5.112043 # Number of seconds simulated
|
||||
sim_ticks 5112043255000 # Number of ticks simulated
|
||||
final_tick 5112043255000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1304311 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2670670 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 33369516688 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 357276 # Number of bytes of host memory used
|
||||
host_seconds 153.20 # Real time elapsed on the host
|
||||
sim_insts 199813913 # Number of instructions simulated
|
||||
sim_ops 409133277 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::pc.south_bridge.ide 2786624 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.dtb.walker 1024 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.itb.walker 704 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.inst 972736 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 11807616 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 15568704 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 972736 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 972736 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 12232896 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 12232896 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::pc.south_bridge.ide 43541 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.dtb.walker 16 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.itb.walker 11 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.inst 15199 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 184494 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 243261 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 191139 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 191139 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::pc.south_bridge.ide 545110 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.dtb.walker 200 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.itb.walker 138 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 190283 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 2309764 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 3045495 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 190283 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 190283 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 2392956 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 2392956 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 2392956 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::pc.south_bridge.ide 545110 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.dtb.walker 200 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.itb.walker 138 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 190283 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 2309764 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 5438452 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.l2c.replacements 164044 # number of replacements
|
||||
system.l2c.tagsinuse 36842.944085 # Cycle average of tags in use
|
||||
system.l2c.total_refs 3332458 # Total number of references to valid blocks.
|
||||
system.l2c.sampled_refs 196390 # Sample count of references to valid blocks.
|
||||
system.l2c.avg_refs 16.968573 # Average number of references to valid blocks.
|
||||
system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.l2c.occ_blocks::writebacks 27139.322665 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu.dtb.walker 2.054559 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu.itb.walker 0.003581 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu.inst 1828.819855 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu.data 7872.743425 # Average occupied blocks per requestor
|
||||
system.l2c.occ_percent::writebacks 0.414113 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu.dtb.walker 0.000031 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu.inst 0.027906 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu.data 0.120129 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::total 0.562179 # Average percentage of cache occupancy
|
||||
system.l2c.ReadReq_hits::cpu.dtb.walker 6729 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu.itb.walker 2809 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu.inst 776101 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu.data 1266816 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::total 2052455 # number of ReadReq hits
|
||||
system.l2c.Writeback_hits::writebacks 1529403 # number of Writeback hits
|
||||
system.l2c.Writeback_hits::total 1529403 # number of Writeback hits
|
||||
system.l2c.UpgradeReq_hits::cpu.data 31 # number of UpgradeReq hits
|
||||
system.l2c.UpgradeReq_hits::total 31 # number of UpgradeReq hits
|
||||
system.l2c.ReadExReq_hits::cpu.data 168948 # number of ReadExReq hits
|
||||
system.l2c.ReadExReq_hits::total 168948 # number of ReadExReq hits
|
||||
system.l2c.demand_hits::cpu.dtb.walker 6729 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu.itb.walker 2809 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu.inst 776101 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu.data 1435764 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::total 2221403 # number of demand (read+write) hits
|
||||
system.l2c.overall_hits::cpu.dtb.walker 6729 # number of overall hits
|
||||
system.l2c.overall_hits::cpu.itb.walker 2809 # number of overall hits
|
||||
system.l2c.overall_hits::cpu.inst 776101 # number of overall hits
|
||||
system.l2c.overall_hits::cpu.data 1435764 # number of overall hits
|
||||
system.l2c.overall_hits::total 2221403 # number of overall hits
|
||||
system.l2c.ReadReq_misses::cpu.dtb.walker 16 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu.itb.walker 11 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu.inst 15200 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu.data 40772 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::total 55999 # number of ReadReq misses
|
||||
system.l2c.UpgradeReq_misses::cpu.data 1792 # number of UpgradeReq misses
|
||||
system.l2c.UpgradeReq_misses::total 1792 # number of UpgradeReq misses
|
||||
system.l2c.ReadExReq_misses::cpu.data 144639 # number of ReadExReq misses
|
||||
system.l2c.ReadExReq_misses::total 144639 # number of ReadExReq misses
|
||||
system.l2c.demand_misses::cpu.dtb.walker 16 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu.itb.walker 11 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu.inst 15200 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu.data 185411 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::total 200638 # number of demand (read+write) misses
|
||||
system.l2c.overall_misses::cpu.dtb.walker 16 # number of overall misses
|
||||
system.l2c.overall_misses::cpu.itb.walker 11 # number of overall misses
|
||||
system.l2c.overall_misses::cpu.inst 15200 # number of overall misses
|
||||
system.l2c.overall_misses::cpu.data 185411 # number of overall misses
|
||||
system.l2c.overall_misses::total 200638 # number of overall misses
|
||||
system.l2c.ReadReq_accesses::cpu.dtb.walker 6745 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::cpu.itb.walker 2820 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::cpu.inst 791301 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::cpu.data 1307588 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::total 2108454 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.Writeback_accesses::writebacks 1529403 # number of Writeback accesses(hits+misses)
|
||||
system.l2c.Writeback_accesses::total 1529403 # number of Writeback accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_accesses::cpu.data 1823 # number of UpgradeReq accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_accesses::total 1823 # number of UpgradeReq accesses(hits+misses)
|
||||
system.l2c.ReadExReq_accesses::cpu.data 313587 # number of ReadExReq accesses(hits+misses)
|
||||
system.l2c.ReadExReq_accesses::total 313587 # number of ReadExReq accesses(hits+misses)
|
||||
system.l2c.demand_accesses::cpu.dtb.walker 6745 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu.itb.walker 2820 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu.inst 791301 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu.data 1621175 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::total 2422041 # number of demand (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu.dtb.walker 6745 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu.itb.walker 2820 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu.inst 791301 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu.data 1621175 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::total 2422041 # number of overall (read+write) accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.002372 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.003901 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu.inst 0.019209 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu.data 0.031181 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::total 0.026559 # miss rate for ReadReq accesses
|
||||
system.l2c.UpgradeReq_miss_rate::cpu.data 0.982995 # miss rate for UpgradeReq accesses
|
||||
system.l2c.UpgradeReq_miss_rate::total 0.982995 # miss rate for UpgradeReq accesses
|
||||
system.l2c.ReadExReq_miss_rate::cpu.data 0.461240 # miss rate for ReadExReq accesses
|
||||
system.l2c.ReadExReq_miss_rate::total 0.461240 # miss rate for ReadExReq accesses
|
||||
system.l2c.demand_miss_rate::cpu.dtb.walker 0.002372 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu.itb.walker 0.003901 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu.inst 0.019209 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu.data 0.114368 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::total 0.082838 # miss rate for demand accesses
|
||||
system.l2c.overall_miss_rate::cpu.dtb.walker 0.002372 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu.itb.walker 0.003901 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu.inst 0.019209 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu.data 0.114368 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::total 0.082838 # miss rate for overall accesses
|
||||
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.l2c.fast_writes 0 # number of fast writes performed
|
||||
system.l2c.cache_copies 0 # number of cache copies performed
|
||||
system.l2c.writebacks::writebacks 144472 # number of writebacks
|
||||
system.l2c.writebacks::total 144472 # number of writebacks
|
||||
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.iocache.replacements 47570 # number of replacements
|
||||
system.iocache.tagsinuse 0.042409 # Cycle average of tags in use
|
||||
system.iocache.total_refs 0 # Total number of references to valid blocks.
|
||||
system.iocache.sampled_refs 47586 # Sample count of references to valid blocks.
|
||||
system.iocache.avg_refs 0 # Average number of references to valid blocks.
|
||||
system.iocache.warmup_cycle 4994776740009 # Cycle when the warmup percentage was hit.
|
||||
system.iocache.occ_blocks::pc.south_bridge.ide 0.042409 # Average occupied blocks per requestor
|
||||
system.iocache.occ_percent::pc.south_bridge.ide 0.002651 # Average percentage of cache occupancy
|
||||
system.iocache.occ_percent::total 0.002651 # Average percentage of cache occupancy
|
||||
system.iocache.ReadReq_misses::pc.south_bridge.ide 905 # number of ReadReq misses
|
||||
system.iocache.ReadReq_misses::total 905 # number of ReadReq misses
|
||||
system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses
|
||||
system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses
|
||||
system.iocache.demand_misses::pc.south_bridge.ide 47625 # number of demand (read+write) misses
|
||||
system.iocache.demand_misses::total 47625 # number of demand (read+write) misses
|
||||
system.iocache.overall_misses::pc.south_bridge.ide 47625 # number of overall misses
|
||||
system.iocache.overall_misses::total 47625 # number of overall misses
|
||||
system.iocache.ReadReq_accesses::pc.south_bridge.ide 905 # number of ReadReq accesses(hits+misses)
|
||||
system.iocache.ReadReq_accesses::total 905 # number of ReadReq accesses(hits+misses)
|
||||
system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses)
|
||||
system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses)
|
||||
system.iocache.demand_accesses::pc.south_bridge.ide 47625 # number of demand (read+write) accesses
|
||||
system.iocache.demand_accesses::total 47625 # number of demand (read+write) accesses
|
||||
system.iocache.overall_accesses::pc.south_bridge.ide 47625 # number of overall (read+write) accesses
|
||||
system.iocache.overall_accesses::total 47625 # number of overall (read+write) accesses
|
||||
system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
|
||||
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
|
||||
system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses
|
||||
system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
|
||||
system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses
|
||||
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
|
||||
system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
|
||||
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
|
||||
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.iocache.fast_writes 0 # number of fast writes performed
|
||||
system.iocache.cache_copies 0 # number of cache copies performed
|
||||
system.iocache.writebacks::writebacks 46667 # number of writebacks
|
||||
system.iocache.writebacks::total 46667 # number of writebacks
|
||||
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
||||
system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
|
||||
system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD).
|
||||
system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes.
|
||||
system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes.
|
||||
system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions.
|
||||
system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
||||
system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
|
||||
system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD).
|
||||
system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
|
||||
system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
|
||||
system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
|
||||
system.cpu.numCycles 10224086531 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 199813913 # Number of instructions committed
|
||||
system.cpu.committedOps 409133277 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 374297244 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 0 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 39954968 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 374297244 # number of integer instructions
|
||||
system.cpu.num_fp_insts 0 # number of float instructions
|
||||
system.cpu.num_int_register_reads 1159028861 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 636431619 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
|
||||
system.cpu.num_mem_refs 35626519 # number of memory refs
|
||||
system.cpu.num_load_insts 27217784 # Number of load instructions
|
||||
system.cpu.num_store_insts 8408735 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 9770605338.086651 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 453481192.913350 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 0.044354 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0.955646 # Percentage of idle cycles
|
||||
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
||||
system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
|
||||
system.cpu.icache.replacements 790795 # number of replacements
|
||||
system.cpu.icache.tagsinuse 510.627676 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 243365777 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 791307 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 307.549127 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 148763105500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 510.627676 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.997320 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.997320 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 243365777 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 243365777 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 243365777 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 243365777 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 243365777 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 243365777 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 791314 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 791314 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 791314 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 791314 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 791314 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 791314 # number of overall misses
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 244157091 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 244157091 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 244157091 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 244157091 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 244157091 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 244157091 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003241 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.003241 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.003241 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.003241 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.003241 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.003241 # miss rate for overall accesses
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks::writebacks 809 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 809 # number of writebacks
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.itb_walker_cache.replacements 3435 # number of replacements
|
||||
system.cpu.itb_walker_cache.tagsinuse 3.021701 # Cycle average of tags in use
|
||||
system.cpu.itb_walker_cache.total_refs 7940 # Total number of references to valid blocks.
|
||||
system.cpu.itb_walker_cache.sampled_refs 3444 # Sample count of references to valid blocks.
|
||||
system.cpu.itb_walker_cache.avg_refs 2.305459 # Average number of references to valid blocks.
|
||||
system.cpu.itb_walker_cache.warmup_cycle 5105275407500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 3.021701 # Average occupied blocks per requestor
|
||||
system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.188856 # Average percentage of cache occupancy
|
||||
system.cpu.itb_walker_cache.occ_percent::total 0.188856 # Average percentage of cache occupancy
|
||||
system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7947 # number of ReadReq hits
|
||||
system.cpu.itb_walker_cache.ReadReq_hits::total 7947 # number of ReadReq hits
|
||||
system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits
|
||||
system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits
|
||||
system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7949 # number of demand (read+write) hits
|
||||
system.cpu.itb_walker_cache.demand_hits::total 7949 # number of demand (read+write) hits
|
||||
system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7949 # number of overall hits
|
||||
system.cpu.itb_walker_cache.overall_hits::total 7949 # number of overall hits
|
||||
system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4278 # number of ReadReq misses
|
||||
system.cpu.itb_walker_cache.ReadReq_misses::total 4278 # number of ReadReq misses
|
||||
system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4278 # number of demand (read+write) misses
|
||||
system.cpu.itb_walker_cache.demand_misses::total 4278 # number of demand (read+write) misses
|
||||
system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4278 # number of overall misses
|
||||
system.cpu.itb_walker_cache.overall_misses::total 4278 # number of overall misses
|
||||
system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12225 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.itb_walker_cache.ReadReq_accesses::total 12225 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12227 # number of demand (read+write) accesses
|
||||
system.cpu.itb_walker_cache.demand_accesses::total 12227 # number of demand (read+write) accesses
|
||||
system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12227 # number of overall (read+write) accesses
|
||||
system.cpu.itb_walker_cache.overall_accesses::total 12227 # number of overall (read+write) accesses
|
||||
system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.349939 # miss rate for ReadReq accesses
|
||||
system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.349939 # miss rate for ReadReq accesses
|
||||
system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.349881 # miss rate for demand accesses
|
||||
system.cpu.itb_walker_cache.demand_miss_rate::total 0.349881 # miss rate for demand accesses
|
||||
system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.349881 # miss rate for overall accesses
|
||||
system.cpu.itb_walker_cache.overall_miss_rate::total 0.349881 # miss rate for overall accesses
|
||||
system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.itb_walker_cache.writebacks::writebacks 518 # number of writebacks
|
||||
system.cpu.itb_walker_cache.writebacks::total 518 # number of writebacks
|
||||
system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dtb_walker_cache.replacements 7755 # number of replacements
|
||||
system.cpu.dtb_walker_cache.tagsinuse 5.010998 # Cycle average of tags in use
|
||||
system.cpu.dtb_walker_cache.total_refs 12854 # Total number of references to valid blocks.
|
||||
system.cpu.dtb_walker_cache.sampled_refs 7767 # Sample count of references to valid blocks.
|
||||
system.cpu.dtb_walker_cache.avg_refs 1.654950 # Average number of references to valid blocks.
|
||||
system.cpu.dtb_walker_cache.warmup_cycle 5101232849000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 5.010998 # Average occupied blocks per requestor
|
||||
system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.313187 # Average percentage of cache occupancy
|
||||
system.cpu.dtb_walker_cache.occ_percent::total 0.313187 # Average percentage of cache occupancy
|
||||
system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 12875 # number of ReadReq hits
|
||||
system.cpu.dtb_walker_cache.ReadReq_hits::total 12875 # number of ReadReq hits
|
||||
system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 12875 # number of demand (read+write) hits
|
||||
system.cpu.dtb_walker_cache.demand_hits::total 12875 # number of demand (read+write) hits
|
||||
system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 12875 # number of overall hits
|
||||
system.cpu.dtb_walker_cache.overall_hits::total 12875 # number of overall hits
|
||||
system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8933 # number of ReadReq misses
|
||||
system.cpu.dtb_walker_cache.ReadReq_misses::total 8933 # number of ReadReq misses
|
||||
system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8933 # number of demand (read+write) misses
|
||||
system.cpu.dtb_walker_cache.demand_misses::total 8933 # number of demand (read+write) misses
|
||||
system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8933 # number of overall misses
|
||||
system.cpu.dtb_walker_cache.overall_misses::total 8933 # number of overall misses
|
||||
system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21808 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dtb_walker_cache.ReadReq_accesses::total 21808 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21808 # number of demand (read+write) accesses
|
||||
system.cpu.dtb_walker_cache.demand_accesses::total 21808 # number of demand (read+write) accesses
|
||||
system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21808 # number of overall (read+write) accesses
|
||||
system.cpu.dtb_walker_cache.overall_accesses::total 21808 # number of overall (read+write) accesses
|
||||
system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.409620 # miss rate for ReadReq accesses
|
||||
system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.409620 # miss rate for ReadReq accesses
|
||||
system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.409620 # miss rate for demand accesses
|
||||
system.cpu.dtb_walker_cache.demand_miss_rate::total 0.409620 # miss rate for demand accesses
|
||||
system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.409620 # miss rate for overall accesses
|
||||
system.cpu.dtb_walker_cache.overall_miss_rate::total 0.409620 # miss rate for overall accesses
|
||||
system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dtb_walker_cache.writebacks::writebacks 2517 # number of writebacks
|
||||
system.cpu.dtb_walker_cache.writebacks::total 2517 # number of writebacks
|
||||
system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 1621277 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 511.999417 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 20142220 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 1621789 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 12.419754 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 7549500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 511.999417 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.999999 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.999999 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 12057024 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 12057024 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 8082938 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 8082938 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 20139962 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 20139962 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 20139962 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 20139962 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 1308207 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 1308207 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 315850 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 315850 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 1624057 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 1624057 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 1624057 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 1624057 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 13365231 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 13365231 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 8398788 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 8398788 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 21764019 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 21764019 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 21764019 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 21764019 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097881 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.097881 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037607 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.037607 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.074621 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.074621 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.074621 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.074621 # miss rate for overall accesses
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 1525559 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 1525559 # number of writebacks
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
@ -0,0 +1,133 @@
|
||||
Linux version 2.6.22.9 (blackga@nacho) (gcc version 4.1.2 (Gentoo 4.1.2)) #2 Mon Oct 8 13:13:00 PDT 2007
|
||||
Command line: earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1
|
||||
BIOS-provided physical RAM map:
|
||||
BIOS-e820: 0000000000000000 - 0000000000100000 (reserved)
|
||||
BIOS-e820: 0000000000100000 - 0000000008000000 (usable)
|
||||
end_pfn_map = 32768
|
||||
kernel direct mapping tables up to 8000000 @ 100000-102000
|
||||
DMI 2.5 present.
|
||||
Zone PFN ranges:
|
||||
DMA 256 -> 4096
|
||||
DMA32 4096 -> 1048576
|
||||
Normal 1048576 -> 1048576
|
||||
early_node_map[1] active PFN ranges
|
||||
0: 256 -> 32768
|
||||
Intel MultiProcessor Specification v1.4
|
||||
MPTABLE: OEM ID: MPTABLE: Product ID: MPTABLE: APIC at: 0xFEE00000
|
||||
Processor #0 (Bootup-CPU)
|
||||
I/O APIC #1 at 0xFEC00000.
|
||||
Setting APIC routing to flat
|
||||
Processors: 1
|
||||
Allocating PCI resources starting at 10000000 (gap: 8000000:f8000000)
|
||||
Built 1 zonelists. Total pages: 30458
|
||||
Kernel command line: earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1
|
||||
Initializing CPU#0
|
||||
PID hash table entries: 512 (order: 9, 4096 bytes)
|
||||
time.c: Detected 1999.998 MHz processor.
|
||||
Console: colour dummy device 80x25
|
||||
console handover: boot [earlyser0] -> real [ttyS0]
|
||||
Dentry cache hash table entries: 16384 (order: 5, 131072 bytes)
|
||||
Inode-cache hash table entries: 8192 (order: 4, 65536 bytes)
|
||||
Checking aperture...
|
||||
Memory: 121556k/131072k available (3742k kernel code, 8456k reserved, 1874k data, 232k init)
|
||||
Calibrating delay loop (skipped)... 3999.96 BogoMIPS preset
|
||||
Mount-cache hash table entries: 256
|
||||
CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)
|
||||
CPU: L2 Cache: 1024K (64 bytes/line)
|
||||
CPU: Fake M5 x86_64 CPU stepping 01
|
||||
ACPI: Core revision 20070126
|
||||
ACPI Exception (tbxface-0618): AE_NO_ACPI_TABLES, While loading namespace from ACPI tables [20070126]
|
||||
ACPI: Unable to load the System Description Tables
|
||||
Using local APIC timer interrupts.
|
||||
result 7812490
|
||||
Detected 7.812 MHz APIC timer.
|
||||
NET: Registered protocol family 16
|
||||
PCI: Using configuration type 1
|
||||
ACPI: Interpreter disabled.
|
||||
Linux Plug and Play Support v0.97 (c) Adam Belay
|
||||
pnp: PnP ACPI: disabled
|
||||
SCSI subsystem initialized
|
||||
usbcore: registered new interface driver usbfs
|
||||
usbcore: registered new interface driver hub
|
||||
usbcore: registered new device driver usb
|
||||
PCI: Probing PCI hardware
|
||||
PCI-GART: No AMD northbridge found.
|
||||
NET: Registered protocol family 2
|
||||
Time: tsc clocksource has been installed.
|
||||
IP route cache hash table entries: 1024 (order: 1, 8192 bytes)
|
||||
TCP established hash table entries: 4096 (order: 4, 65536 bytes)
|
||||
TCP bind hash table entries: 4096 (order: 3, 32768 bytes)
|
||||
TCP: Hash tables configured (established 4096 bind 4096)
|
||||
TCP reno registered
|
||||
Total HugeTLB memory allocated, 0
|
||||
Installing knfsd (copyright (C) 1996 okir@monad.swb.de).
|
||||
io scheduler noop registered
|
||||
io scheduler deadline registered
|
||||
io scheduler cfq registered (default)
|
||||
Real Time Clock Driver v1.12ac
|
||||
Linux agpgart interface v0.102 (c) Dave Jones
|
||||
Serial: 8250/16550 driver $Revision: 1.90 $ 4 ports, IRQ sharing disabled
|
||||
serial8250: ttyS0 at I/O 0x3f8 (irq = 4) is a 8250
|
||||
floppy0: no floppy controllers found
|
||||
RAMDISK driver initialized: 16 RAM disks of 4096K size 1024 blocksize
|
||||
loop: module loaded
|
||||
Intel(R) PRO/1000 Network Driver - version 7.3.20-k2
|
||||
Copyright (c) 1999-2006 Intel Corporation.
|
||||
e100: Intel(R) PRO/100 Network Driver, 3.5.17-k4-NAPI
|
||||
e100: Copyright(c) 1999-2006 Intel Corporation
|
||||
forcedeth.c: Reverse Engineered nForce ethernet driver. Version 0.60.
|
||||
tun: Universal TUN/TAP device driver, 1.6
|
||||
tun: (C) 1999-2004 Max Krasnyansky <maxk@qualcomm.com>
|
||||
netconsole: not configured, aborting
|
||||
Uniform Multi-Platform E-IDE driver Revision: 7.00alpha2
|
||||
ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx
|
||||
PIIX4: IDE controller at PCI slot 0000:00:04.0
|
||||
PCI: Enabling device 0000:00:04.0 (0000 -> 0001)
|
||||
PIIX4: chipset revision 0
|
||||
PIIX4: not 100% native mode: will probe irqs later
|
||||
ide0: BM-DMA at 0x1000-0x1007, BIOS settings: hda:DMA, hdb:DMA
|
||||
ide1: BM-DMA at 0x1008-0x100f, BIOS settings: hdc:DMA, hdd:DMA
|
||||
hda: M5 IDE Disk, ATA DISK drive
|
||||
hdb: M5 IDE Disk, ATA DISK drive
|
||||
ide0 at 0x1f0-0x1f7,0x3f6 on irq 14
|
||||
hda: max request size: 128KiB
|
||||
hda: 1048320 sectors (536 MB), CHS=1040/16/63, UDMA(33)
|
||||
hda: hda1
|
||||
hdb: max request size: 128KiB
|
||||
hdb: 4177920 sectors (2139 MB), CHS=4144/16/63, UDMA(33)
|
||||
hdb: unknown partition table
|
||||
megaraid cmm: 2.20.2.7 (Release Date: Sun Jul 16 00:01:03 EST 2006)
|
||||
megaraid: 2.20.5.1 (Release Date: Thu Nov 16 15:32:35 EST 2006)
|
||||
megasas: 00.00.03.10-rc5 Thu May 17 10:09:32 PDT 2007
|
||||
Fusion MPT base driver 3.04.04
|
||||
Copyright (c) 1999-2007 LSI Logic Corporation
|
||||
Fusion MPT SPI Host driver 3.04.04
|
||||
Fusion MPT SAS Host driver 3.04.04
|
||||
ieee1394: raw1394: /dev/raw1394 device initialized
|
||||
USB Universal Host Controller Interface driver v3.0
|
||||
usbcore: registered new interface driver usblp
|
||||
drivers/usb/class/usblp.c: v0.13: USB Printer Device Class driver
|
||||
Initializing USB Mass Storage driver...
|
||||
usbcore: registered new interface driver usb-storage
|
||||
USB Mass Storage support registered.
|
||||
PNP: No PS/2 controller found. Probing ports directly.
|
||||
serio: i8042 KBD port at 0x60,0x64 irq 1
|
||||
serio: i8042 AUX port at 0x60,0x64 irq 12
|
||||
mice: PS/2 mouse device common for all mice
|
||||
input: AT Translated Set 2 keyboard as /class/input/input0
|
||||
device-mapper: ioctl: 4.11.0-ioctl (2006-10-12) initialised: dm-devel@redhat.com
|
||||
input: PS/2 Generic Mouse as /class/input/input1
|
||||
usbcore: registered new interface driver usbhid
|
||||
drivers/hid/usbhid/hid-core.c: v2.6:USB HID core driver
|
||||
oprofile: using timer interrupt.
|
||||
TCP cubic registered
|
||||
NET: Registered protocol family 1
|
||||
NET: Registered protocol family 10
|
||||
IPv6 over IPv4 tunneling driver
|
||||
NET: Registered protocol family 17
|
||||
EXT2-fs warning: mounting unchecked fs, running e2fsck is recommended
|
||||
VFS: Mounted root (ext2 filesystem).
|
||||
Freeing unused kernel memory: 232k freed
|
||||
|
||||
INIT: version 2.86 booting
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,9 @@
|
||||
warn: Sockets disabled, not accepting terminal connections
|
||||
warn: Reading current count from inactive timer.
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: Don't know what interrupt to clear for console.
|
||||
warn: instruction 'fxsave' unimplemented
|
||||
warn: Tried to clear PCI interrupt 14
|
||||
warn: Unknown mouse command 0xe1.
|
||||
warn: instruction 'wbinvd' unimplemented
|
||||
hack: be nice to actually delete the event here
|
||||
@ -0,0 +1,13 @@
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jun 4 2012 13:44:28
|
||||
gem5 started Jun 4 2012 15:05:12
|
||||
gem5 executing on zizzer
|
||||
command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-timing -re tests/run.py build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-timing
|
||||
warning: add_child('terminal'): child 'terminal' already has parent
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
|
||||
0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 5195470393000 because m5_exit instruction encountered
|
||||
@ -0,0 +1,768 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 5.195470 # Number of seconds simulated
|
||||
sim_ticks 5195470393000 # Number of ticks simulated
|
||||
final_tick 5195470393000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 792632 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1521406 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 29811367673 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 354100 # Number of bytes of host memory used
|
||||
host_seconds 174.28 # Real time elapsed on the host
|
||||
sim_insts 138138472 # Number of instructions simulated
|
||||
sim_ops 265147881 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::pc.south_bridge.ide 2876352 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.dtb.walker 832 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.itb.walker 640 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.inst 974400 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 9911872 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 13764096 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 974400 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 974400 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 10427072 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 10427072 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::pc.south_bridge.ide 44943 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.dtb.walker 13 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.itb.walker 10 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.inst 15225 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 154873 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 215064 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 162923 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 162923 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::pc.south_bridge.ide 553627 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.dtb.walker 160 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.itb.walker 123 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 187548 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 1907791 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 2649249 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 187548 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 187548 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 2006954 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 2006954 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 2006954 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::pc.south_bridge.ide 553627 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.dtb.walker 160 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.itb.walker 123 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 187548 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 1907791 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 4656204 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.l2c.replacements 136133 # number of replacements
|
||||
system.l2c.tagsinuse 31389.895470 # Cycle average of tags in use
|
||||
system.l2c.total_refs 3363370 # Total number of references to valid blocks.
|
||||
system.l2c.sampled_refs 168244 # Sample count of references to valid blocks.
|
||||
system.l2c.avg_refs 19.991025 # Average number of references to valid blocks.
|
||||
system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.l2c.occ_blocks::writebacks 23478.740830 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu.dtb.walker 0.248367 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu.itb.walker 0.010497 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu.inst 1900.597036 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu.data 6010.298740 # Average occupied blocks per requestor
|
||||
system.l2c.occ_percent::writebacks 0.358257 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu.dtb.walker 0.000004 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu.inst 0.029001 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu.data 0.091710 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::total 0.478972 # Average percentage of cache occupancy
|
||||
system.l2c.ReadReq_hits::cpu.dtb.walker 6528 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu.itb.walker 3033 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu.inst 773419 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu.data 1274463 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::total 2057443 # number of ReadReq hits
|
||||
system.l2c.Writeback_hits::writebacks 1534567 # number of Writeback hits
|
||||
system.l2c.Writeback_hits::total 1534567 # number of Writeback hits
|
||||
system.l2c.UpgradeReq_hits::cpu.data 320 # number of UpgradeReq hits
|
||||
system.l2c.UpgradeReq_hits::total 320 # number of UpgradeReq hits
|
||||
system.l2c.ReadExReq_hits::cpu.data 192958 # number of ReadExReq hits
|
||||
system.l2c.ReadExReq_hits::total 192958 # number of ReadExReq hits
|
||||
system.l2c.demand_hits::cpu.dtb.walker 6528 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu.itb.walker 3033 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu.inst 773419 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu.data 1467421 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::total 2250401 # number of demand (read+write) hits
|
||||
system.l2c.overall_hits::cpu.dtb.walker 6528 # number of overall hits
|
||||
system.l2c.overall_hits::cpu.itb.walker 3033 # number of overall hits
|
||||
system.l2c.overall_hits::cpu.inst 773419 # number of overall hits
|
||||
system.l2c.overall_hits::cpu.data 1467421 # number of overall hits
|
||||
system.l2c.overall_hits::total 2250401 # number of overall hits
|
||||
system.l2c.ReadReq_misses::cpu.dtb.walker 13 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu.itb.walker 10 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu.inst 15226 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu.data 35581 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::total 50830 # number of ReadReq misses
|
||||
system.l2c.UpgradeReq_misses::cpu.data 1369 # number of UpgradeReq misses
|
||||
system.l2c.UpgradeReq_misses::total 1369 # number of UpgradeReq misses
|
||||
system.l2c.ReadExReq_misses::cpu.data 120168 # number of ReadExReq misses
|
||||
system.l2c.ReadExReq_misses::total 120168 # number of ReadExReq misses
|
||||
system.l2c.demand_misses::cpu.dtb.walker 13 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu.itb.walker 10 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu.inst 15226 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu.data 155749 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::total 170998 # number of demand (read+write) misses
|
||||
system.l2c.overall_misses::cpu.dtb.walker 13 # number of overall misses
|
||||
system.l2c.overall_misses::cpu.itb.walker 10 # number of overall misses
|
||||
system.l2c.overall_misses::cpu.inst 15226 # number of overall misses
|
||||
system.l2c.overall_misses::cpu.data 155749 # number of overall misses
|
||||
system.l2c.overall_misses::total 170998 # number of overall misses
|
||||
system.l2c.ReadReq_miss_latency::cpu.dtb.walker 676000 # number of ReadReq miss cycles
|
||||
system.l2c.ReadReq_miss_latency::cpu.itb.walker 520000 # number of ReadReq miss cycles
|
||||
system.l2c.ReadReq_miss_latency::cpu.inst 791868000 # number of ReadReq miss cycles
|
||||
system.l2c.ReadReq_miss_latency::cpu.data 1863058500 # number of ReadReq miss cycles
|
||||
system.l2c.ReadReq_miss_latency::total 2656122500 # number of ReadReq miss cycles
|
||||
system.l2c.UpgradeReq_miss_latency::cpu.data 33778000 # number of UpgradeReq miss cycles
|
||||
system.l2c.UpgradeReq_miss_latency::total 33778000 # number of UpgradeReq miss cycles
|
||||
system.l2c.ReadExReq_miss_latency::cpu.data 6249324500 # number of ReadExReq miss cycles
|
||||
system.l2c.ReadExReq_miss_latency::total 6249324500 # number of ReadExReq miss cycles
|
||||
system.l2c.demand_miss_latency::cpu.dtb.walker 676000 # number of demand (read+write) miss cycles
|
||||
system.l2c.demand_miss_latency::cpu.itb.walker 520000 # number of demand (read+write) miss cycles
|
||||
system.l2c.demand_miss_latency::cpu.inst 791868000 # number of demand (read+write) miss cycles
|
||||
system.l2c.demand_miss_latency::cpu.data 8112383000 # number of demand (read+write) miss cycles
|
||||
system.l2c.demand_miss_latency::total 8905447000 # number of demand (read+write) miss cycles
|
||||
system.l2c.overall_miss_latency::cpu.dtb.walker 676000 # number of overall miss cycles
|
||||
system.l2c.overall_miss_latency::cpu.itb.walker 520000 # number of overall miss cycles
|
||||
system.l2c.overall_miss_latency::cpu.inst 791868000 # number of overall miss cycles
|
||||
system.l2c.overall_miss_latency::cpu.data 8112383000 # number of overall miss cycles
|
||||
system.l2c.overall_miss_latency::total 8905447000 # number of overall miss cycles
|
||||
system.l2c.ReadReq_accesses::cpu.dtb.walker 6541 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::cpu.itb.walker 3043 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::cpu.inst 788645 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::cpu.data 1310044 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::total 2108273 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.Writeback_accesses::writebacks 1534567 # number of Writeback accesses(hits+misses)
|
||||
system.l2c.Writeback_accesses::total 1534567 # number of Writeback accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_accesses::cpu.data 1689 # number of UpgradeReq accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_accesses::total 1689 # number of UpgradeReq accesses(hits+misses)
|
||||
system.l2c.ReadExReq_accesses::cpu.data 313126 # number of ReadExReq accesses(hits+misses)
|
||||
system.l2c.ReadExReq_accesses::total 313126 # number of ReadExReq accesses(hits+misses)
|
||||
system.l2c.demand_accesses::cpu.dtb.walker 6541 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu.itb.walker 3043 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu.inst 788645 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu.data 1623170 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::total 2421399 # number of demand (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu.dtb.walker 6541 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu.itb.walker 3043 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu.inst 788645 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu.data 1623170 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::total 2421399 # number of overall (read+write) accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.001987 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.003286 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu.inst 0.019307 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu.data 0.027160 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::total 0.024110 # miss rate for ReadReq accesses
|
||||
system.l2c.UpgradeReq_miss_rate::cpu.data 0.810539 # miss rate for UpgradeReq accesses
|
||||
system.l2c.UpgradeReq_miss_rate::total 0.810539 # miss rate for UpgradeReq accesses
|
||||
system.l2c.ReadExReq_miss_rate::cpu.data 0.383769 # miss rate for ReadExReq accesses
|
||||
system.l2c.ReadExReq_miss_rate::total 0.383769 # miss rate for ReadExReq accesses
|
||||
system.l2c.demand_miss_rate::cpu.dtb.walker 0.001987 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu.itb.walker 0.003286 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu.inst 0.019307 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu.data 0.095954 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::total 0.070620 # miss rate for demand accesses
|
||||
system.l2c.overall_miss_rate::cpu.dtb.walker 0.001987 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu.itb.walker 0.003286 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu.inst 0.019307 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu.data 0.095954 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::total 0.070620 # miss rate for overall accesses
|
||||
system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52000 # average ReadReq miss latency
|
||||
system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 52000 # average ReadReq miss latency
|
||||
system.l2c.ReadReq_avg_miss_latency::cpu.inst 52007.618547 # average ReadReq miss latency
|
||||
system.l2c.ReadReq_avg_miss_latency::cpu.data 52361.049436 # average ReadReq miss latency
|
||||
system.l2c.ReadReq_avg_miss_latency::total 52255.016722 # average ReadReq miss latency
|
||||
system.l2c.UpgradeReq_avg_miss_latency::cpu.data 24673.484295 # average UpgradeReq miss latency
|
||||
system.l2c.UpgradeReq_avg_miss_latency::total 24673.484295 # average UpgradeReq miss latency
|
||||
system.l2c.ReadExReq_avg_miss_latency::cpu.data 52004.897310 # average ReadExReq miss latency
|
||||
system.l2c.ReadExReq_avg_miss_latency::total 52004.897310 # average ReadExReq miss latency
|
||||
system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52000 # average overall miss latency
|
||||
system.l2c.demand_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency
|
||||
system.l2c.demand_avg_miss_latency::cpu.inst 52007.618547 # average overall miss latency
|
||||
system.l2c.demand_avg_miss_latency::cpu.data 52086.260586 # average overall miss latency
|
||||
system.l2c.demand_avg_miss_latency::total 52079.246541 # average overall miss latency
|
||||
system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52000 # average overall miss latency
|
||||
system.l2c.overall_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency
|
||||
system.l2c.overall_avg_miss_latency::cpu.inst 52007.618547 # average overall miss latency
|
||||
system.l2c.overall_avg_miss_latency::cpu.data 52086.260586 # average overall miss latency
|
||||
system.l2c.overall_avg_miss_latency::total 52079.246541 # average overall miss latency
|
||||
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.l2c.fast_writes 0 # number of fast writes performed
|
||||
system.l2c.cache_copies 0 # number of cache copies performed
|
||||
system.l2c.writebacks::writebacks 116255 # number of writebacks
|
||||
system.l2c.writebacks::total 116255 # number of writebacks
|
||||
system.l2c.ReadReq_mshr_misses::cpu.dtb.walker 13 # number of ReadReq MSHR misses
|
||||
system.l2c.ReadReq_mshr_misses::cpu.itb.walker 10 # number of ReadReq MSHR misses
|
||||
system.l2c.ReadReq_mshr_misses::cpu.inst 15226 # number of ReadReq MSHR misses
|
||||
system.l2c.ReadReq_mshr_misses::cpu.data 35581 # number of ReadReq MSHR misses
|
||||
system.l2c.ReadReq_mshr_misses::total 50830 # number of ReadReq MSHR misses
|
||||
system.l2c.UpgradeReq_mshr_misses::cpu.data 1369 # number of UpgradeReq MSHR misses
|
||||
system.l2c.UpgradeReq_mshr_misses::total 1369 # number of UpgradeReq MSHR misses
|
||||
system.l2c.ReadExReq_mshr_misses::cpu.data 120168 # number of ReadExReq MSHR misses
|
||||
system.l2c.ReadExReq_mshr_misses::total 120168 # number of ReadExReq MSHR misses
|
||||
system.l2c.demand_mshr_misses::cpu.dtb.walker 13 # number of demand (read+write) MSHR misses
|
||||
system.l2c.demand_mshr_misses::cpu.itb.walker 10 # number of demand (read+write) MSHR misses
|
||||
system.l2c.demand_mshr_misses::cpu.inst 15226 # number of demand (read+write) MSHR misses
|
||||
system.l2c.demand_mshr_misses::cpu.data 155749 # number of demand (read+write) MSHR misses
|
||||
system.l2c.demand_mshr_misses::total 170998 # number of demand (read+write) MSHR misses
|
||||
system.l2c.overall_mshr_misses::cpu.dtb.walker 13 # number of overall MSHR misses
|
||||
system.l2c.overall_mshr_misses::cpu.itb.walker 10 # number of overall MSHR misses
|
||||
system.l2c.overall_mshr_misses::cpu.inst 15226 # number of overall MSHR misses
|
||||
system.l2c.overall_mshr_misses::cpu.data 155749 # number of overall MSHR misses
|
||||
system.l2c.overall_mshr_misses::total 170998 # number of overall MSHR misses
|
||||
system.l2c.ReadReq_mshr_miss_latency::cpu.dtb.walker 520000 # number of ReadReq MSHR miss cycles
|
||||
system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker 400000 # number of ReadReq MSHR miss cycles
|
||||
system.l2c.ReadReq_mshr_miss_latency::cpu.inst 609142000 # number of ReadReq MSHR miss cycles
|
||||
system.l2c.ReadReq_mshr_miss_latency::cpu.data 1436082000 # number of ReadReq MSHR miss cycles
|
||||
system.l2c.ReadReq_mshr_miss_latency::total 2046144000 # number of ReadReq MSHR miss cycles
|
||||
system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 55109000 # number of UpgradeReq MSHR miss cycles
|
||||
system.l2c.UpgradeReq_mshr_miss_latency::total 55109000 # number of UpgradeReq MSHR miss cycles
|
||||
system.l2c.ReadExReq_mshr_miss_latency::cpu.data 4807305000 # number of ReadExReq MSHR miss cycles
|
||||
system.l2c.ReadExReq_mshr_miss_latency::total 4807305000 # number of ReadExReq MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_latency::cpu.dtb.walker 520000 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_latency::cpu.itb.walker 400000 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_latency::cpu.inst 609142000 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_latency::cpu.data 6243387000 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_latency::total 6853449000 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency::cpu.dtb.walker 520000 # number of overall MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency::cpu.itb.walker 400000 # number of overall MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency::cpu.inst 609142000 # number of overall MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency::cpu.data 6243387000 # number of overall MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency::total 6853449000 # number of overall MSHR miss cycles
|
||||
system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 56051785000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.l2c.ReadReq_mshr_uncacheable_latency::total 56051785000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 1218050000 # number of WriteReq MSHR uncacheable cycles
|
||||
system.l2c.WriteReq_mshr_uncacheable_latency::total 1218050000 # number of WriteReq MSHR uncacheable cycles
|
||||
system.l2c.overall_mshr_uncacheable_latency::cpu.data 57269835000 # number of overall MSHR uncacheable cycles
|
||||
system.l2c.overall_mshr_uncacheable_latency::total 57269835000 # number of overall MSHR uncacheable cycles
|
||||
system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001987 # mshr miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.003286 # mshr miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.019307 # mshr miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.027160 # mshr miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_mshr_miss_rate::total 0.024110 # mshr miss rate for ReadReq accesses
|
||||
system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.810539 # mshr miss rate for UpgradeReq accesses
|
||||
system.l2c.UpgradeReq_mshr_miss_rate::total 0.810539 # mshr miss rate for UpgradeReq accesses
|
||||
system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.383769 # mshr miss rate for ReadExReq accesses
|
||||
system.l2c.ReadExReq_mshr_miss_rate::total 0.383769 # mshr miss rate for ReadExReq accesses
|
||||
system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.001987 # mshr miss rate for demand accesses
|
||||
system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.003286 # mshr miss rate for demand accesses
|
||||
system.l2c.demand_mshr_miss_rate::cpu.inst 0.019307 # mshr miss rate for demand accesses
|
||||
system.l2c.demand_mshr_miss_rate::cpu.data 0.095954 # mshr miss rate for demand accesses
|
||||
system.l2c.demand_mshr_miss_rate::total 0.070620 # mshr miss rate for demand accesses
|
||||
system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.001987 # mshr miss rate for overall accesses
|
||||
system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.003286 # mshr miss rate for overall accesses
|
||||
system.l2c.overall_mshr_miss_rate::cpu.inst 0.019307 # mshr miss rate for overall accesses
|
||||
system.l2c.overall_mshr_miss_rate::cpu.data 0.095954 # mshr miss rate for overall accesses
|
||||
system.l2c.overall_mshr_miss_rate::total 0.070620 # mshr miss rate for overall accesses
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average ReadReq mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40000 # average ReadReq mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40006.699067 # average ReadReq mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40360.922965 # average ReadReq mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::total 40254.652764 # average ReadReq mshr miss latency
|
||||
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40254.930606 # average UpgradeReq mshr miss latency
|
||||
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40254.930606 # average UpgradeReq mshr miss latency
|
||||
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40004.868185 # average ReadExReq mshr miss latency
|
||||
system.l2c.ReadExReq_avg_mshr_miss_latency::total 40004.868185 # average ReadExReq mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40006.699067 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu.data 40086.209221 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::total 40079.117884 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40006.699067 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu.data 40086.209221 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::total 40079.117884 # average overall mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
|
||||
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
||||
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
|
||||
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
||||
system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
|
||||
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
||||
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.iocache.replacements 47510 # number of replacements
|
||||
system.iocache.tagsinuse 0.120586 # Cycle average of tags in use
|
||||
system.iocache.total_refs 0 # Total number of references to valid blocks.
|
||||
system.iocache.sampled_refs 47526 # Sample count of references to valid blocks.
|
||||
system.iocache.avg_refs 0 # Average number of references to valid blocks.
|
||||
system.iocache.warmup_cycle 5048756072000 # Cycle when the warmup percentage was hit.
|
||||
system.iocache.occ_blocks::pc.south_bridge.ide 0.120586 # Average occupied blocks per requestor
|
||||
system.iocache.occ_percent::pc.south_bridge.ide 0.007537 # Average percentage of cache occupancy
|
||||
system.iocache.occ_percent::total 0.007537 # Average percentage of cache occupancy
|
||||
system.iocache.ReadReq_misses::pc.south_bridge.ide 844 # number of ReadReq misses
|
||||
system.iocache.ReadReq_misses::total 844 # number of ReadReq misses
|
||||
system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses
|
||||
system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses
|
||||
system.iocache.demand_misses::pc.south_bridge.ide 47564 # number of demand (read+write) misses
|
||||
system.iocache.demand_misses::total 47564 # number of demand (read+write) misses
|
||||
system.iocache.overall_misses::pc.south_bridge.ide 47564 # number of overall misses
|
||||
system.iocache.overall_misses::total 47564 # number of overall misses
|
||||
system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 106575932 # number of ReadReq miss cycles
|
||||
system.iocache.ReadReq_miss_latency::total 106575932 # number of ReadReq miss cycles
|
||||
system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 6391379160 # number of WriteReq miss cycles
|
||||
system.iocache.WriteReq_miss_latency::total 6391379160 # number of WriteReq miss cycles
|
||||
system.iocache.demand_miss_latency::pc.south_bridge.ide 6497955092 # number of demand (read+write) miss cycles
|
||||
system.iocache.demand_miss_latency::total 6497955092 # number of demand (read+write) miss cycles
|
||||
system.iocache.overall_miss_latency::pc.south_bridge.ide 6497955092 # number of overall miss cycles
|
||||
system.iocache.overall_miss_latency::total 6497955092 # number of overall miss cycles
|
||||
system.iocache.ReadReq_accesses::pc.south_bridge.ide 844 # number of ReadReq accesses(hits+misses)
|
||||
system.iocache.ReadReq_accesses::total 844 # number of ReadReq accesses(hits+misses)
|
||||
system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses)
|
||||
system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses)
|
||||
system.iocache.demand_accesses::pc.south_bridge.ide 47564 # number of demand (read+write) accesses
|
||||
system.iocache.demand_accesses::total 47564 # number of demand (read+write) accesses
|
||||
system.iocache.overall_accesses::pc.south_bridge.ide 47564 # number of overall (read+write) accesses
|
||||
system.iocache.overall_accesses::total 47564 # number of overall (read+write) accesses
|
||||
system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
|
||||
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
|
||||
system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses
|
||||
system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
|
||||
system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses
|
||||
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
|
||||
system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
|
||||
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
|
||||
system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 126274.800948 # average ReadReq miss latency
|
||||
system.iocache.ReadReq_avg_miss_latency::total 126274.800948 # average ReadReq miss latency
|
||||
system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 136801.779966 # average WriteReq miss latency
|
||||
system.iocache.WriteReq_avg_miss_latency::total 136801.779966 # average WriteReq miss latency
|
||||
system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 136614.983853 # average overall miss latency
|
||||
system.iocache.demand_avg_miss_latency::total 136614.983853 # average overall miss latency
|
||||
system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 136614.983853 # average overall miss latency
|
||||
system.iocache.overall_avg_miss_latency::total 136614.983853 # average overall miss latency
|
||||
system.iocache.blocked_cycles::no_mshrs 69564644 # number of cycles access was blocked
|
||||
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.iocache.blocked::no_mshrs 11299 # number of cycles access was blocked
|
||||
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.iocache.avg_blocked_cycles::no_mshrs 6156.708027 # average number of cycles each access was blocked
|
||||
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.iocache.fast_writes 0 # number of fast writes performed
|
||||
system.iocache.cache_copies 0 # number of cache copies performed
|
||||
system.iocache.writebacks::writebacks 46668 # number of writebacks
|
||||
system.iocache.writebacks::total 46668 # number of writebacks
|
||||
system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 844 # number of ReadReq MSHR misses
|
||||
system.iocache.ReadReq_mshr_misses::total 844 # number of ReadReq MSHR misses
|
||||
system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses
|
||||
system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses
|
||||
system.iocache.demand_mshr_misses::pc.south_bridge.ide 47564 # number of demand (read+write) MSHR misses
|
||||
system.iocache.demand_mshr_misses::total 47564 # number of demand (read+write) MSHR misses
|
||||
system.iocache.overall_mshr_misses::pc.south_bridge.ide 47564 # number of overall MSHR misses
|
||||
system.iocache.overall_mshr_misses::total 47564 # number of overall MSHR misses
|
||||
system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 62666978 # number of ReadReq MSHR miss cycles
|
||||
system.iocache.ReadReq_mshr_miss_latency::total 62666978 # number of ReadReq MSHR miss cycles
|
||||
system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 3961676998 # number of WriteReq MSHR miss cycles
|
||||
system.iocache.WriteReq_mshr_miss_latency::total 3961676998 # number of WriteReq MSHR miss cycles
|
||||
system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 4024343976 # number of demand (read+write) MSHR miss cycles
|
||||
system.iocache.demand_mshr_miss_latency::total 4024343976 # number of demand (read+write) MSHR miss cycles
|
||||
system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 4024343976 # number of overall MSHR miss cycles
|
||||
system.iocache.overall_mshr_miss_latency::total 4024343976 # number of overall MSHR miss cycles
|
||||
system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses
|
||||
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
|
||||
system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses
|
||||
system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
|
||||
system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses
|
||||
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
|
||||
system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses
|
||||
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
|
||||
system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 74249.973934 # average ReadReq mshr miss latency
|
||||
system.iocache.ReadReq_avg_mshr_miss_latency::total 74249.973934 # average ReadReq mshr miss latency
|
||||
system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 84796.168622 # average WriteReq mshr miss latency
|
||||
system.iocache.WriteReq_avg_mshr_miss_latency::total 84796.168622 # average WriteReq mshr miss latency
|
||||
system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 84609.031536 # average overall mshr miss latency
|
||||
system.iocache.demand_avg_mshr_miss_latency::total 84609.031536 # average overall mshr miss latency
|
||||
system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 84609.031536 # average overall mshr miss latency
|
||||
system.iocache.overall_avg_mshr_miss_latency::total 84609.031536 # average overall mshr miss latency
|
||||
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
||||
system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
|
||||
system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD).
|
||||
system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes.
|
||||
system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes.
|
||||
system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions.
|
||||
system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
||||
system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
|
||||
system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD).
|
||||
system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
|
||||
system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
|
||||
system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
|
||||
system.cpu.numCycles 10390940786 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 138138472 # Number of instructions committed
|
||||
system.cpu.committedOps 265147881 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 249556386 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 0 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 24882695 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 249556386 # number of integer instructions
|
||||
system.cpu.num_fp_insts 0 # number of float instructions
|
||||
system.cpu.num_int_register_reads 778086007 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 422921187 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
|
||||
system.cpu.num_mem_refs 23169904 # number of memory refs
|
||||
system.cpu.num_load_insts 14812525 # Number of load instructions
|
||||
system.cpu.num_store_insts 8357379 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 9787777240.878117 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 603163545.121884 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 0.058047 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0.941953 # Percentage of idle cycles
|
||||
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
||||
system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
|
||||
system.cpu.icache.replacements 788139 # number of replacements
|
||||
system.cpu.icache.tagsinuse 510.361283 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 158433932 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 788651 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 200.892324 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 160047116000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 510.361283 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.996799 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.996799 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 158433932 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 158433932 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 158433932 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 158433932 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 158433932 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 158433932 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 788658 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 788658 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 788658 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 788658 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 788658 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 788658 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 11681762500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 11681762500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 11681762500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 11681762500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 11681762500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 11681762500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 159222590 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 159222590 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 159222590 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 159222590 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 159222590 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 159222590 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.004953 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.004953 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.004953 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.004953 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.004953 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.004953 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14812.203135 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 14812.203135 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 14812.203135 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 14812.203135 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 14812.203135 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 14812.203135 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks::writebacks 805 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 805 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 788658 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 788658 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 788658 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 788658 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 788658 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 788658 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9314744000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 9314744000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9314744000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 9314744000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9314744000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 9314744000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.004953 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.004953 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.004953 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.004953 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.004953 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.004953 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11810.878733 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11810.878733 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11810.878733 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 11810.878733 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11810.878733 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 11810.878733 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.itb_walker_cache.replacements 3754 # number of replacements
|
||||
system.cpu.itb_walker_cache.tagsinuse 3.070606 # Cycle average of tags in use
|
||||
system.cpu.itb_walker_cache.total_refs 7549 # Total number of references to valid blocks.
|
||||
system.cpu.itb_walker_cache.sampled_refs 3765 # Sample count of references to valid blocks.
|
||||
system.cpu.itb_walker_cache.avg_refs 2.005046 # Average number of references to valid blocks.
|
||||
system.cpu.itb_walker_cache.warmup_cycle 5178573163000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 3.070606 # Average occupied blocks per requestor
|
||||
system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.191913 # Average percentage of cache occupancy
|
||||
system.cpu.itb_walker_cache.occ_percent::total 0.191913 # Average percentage of cache occupancy
|
||||
system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7619 # number of ReadReq hits
|
||||
system.cpu.itb_walker_cache.ReadReq_hits::total 7619 # number of ReadReq hits
|
||||
system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits
|
||||
system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits
|
||||
system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7621 # number of demand (read+write) hits
|
||||
system.cpu.itb_walker_cache.demand_hits::total 7621 # number of demand (read+write) hits
|
||||
system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7621 # number of overall hits
|
||||
system.cpu.itb_walker_cache.overall_hits::total 7621 # number of overall hits
|
||||
system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4602 # number of ReadReq misses
|
||||
system.cpu.itb_walker_cache.ReadReq_misses::total 4602 # number of ReadReq misses
|
||||
system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4602 # number of demand (read+write) misses
|
||||
system.cpu.itb_walker_cache.demand_misses::total 4602 # number of demand (read+write) misses
|
||||
system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4602 # number of overall misses
|
||||
system.cpu.itb_walker_cache.overall_misses::total 4602 # number of overall misses
|
||||
system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 50817000 # number of ReadReq miss cycles
|
||||
system.cpu.itb_walker_cache.ReadReq_miss_latency::total 50817000 # number of ReadReq miss cycles
|
||||
system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 50817000 # number of demand (read+write) miss cycles
|
||||
system.cpu.itb_walker_cache.demand_miss_latency::total 50817000 # number of demand (read+write) miss cycles
|
||||
system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 50817000 # number of overall miss cycles
|
||||
system.cpu.itb_walker_cache.overall_miss_latency::total 50817000 # number of overall miss cycles
|
||||
system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12221 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.itb_walker_cache.ReadReq_accesses::total 12221 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12223 # number of demand (read+write) accesses
|
||||
system.cpu.itb_walker_cache.demand_accesses::total 12223 # number of demand (read+write) accesses
|
||||
system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12223 # number of overall (read+write) accesses
|
||||
system.cpu.itb_walker_cache.overall_accesses::total 12223 # number of overall (read+write) accesses
|
||||
system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.376565 # miss rate for ReadReq accesses
|
||||
system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.376565 # miss rate for ReadReq accesses
|
||||
system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.376503 # miss rate for demand accesses
|
||||
system.cpu.itb_walker_cache.demand_miss_rate::total 0.376503 # miss rate for demand accesses
|
||||
system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.376503 # miss rate for overall accesses
|
||||
system.cpu.itb_walker_cache.overall_miss_rate::total 0.376503 # miss rate for overall accesses
|
||||
system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11042.372881 # average ReadReq miss latency
|
||||
system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11042.372881 # average ReadReq miss latency
|
||||
system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11042.372881 # average overall miss latency
|
||||
system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11042.372881 # average overall miss latency
|
||||
system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11042.372881 # average overall miss latency
|
||||
system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11042.372881 # average overall miss latency
|
||||
system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.itb_walker_cache.writebacks::writebacks 826 # number of writebacks
|
||||
system.cpu.itb_walker_cache.writebacks::total 826 # number of writebacks
|
||||
system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 4602 # number of ReadReq MSHR misses
|
||||
system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 4602 # number of ReadReq MSHR misses
|
||||
system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 4602 # number of demand (read+write) MSHR misses
|
||||
system.cpu.itb_walker_cache.demand_mshr_misses::total 4602 # number of demand (read+write) MSHR misses
|
||||
system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 4602 # number of overall MSHR misses
|
||||
system.cpu.itb_walker_cache.overall_mshr_misses::total 4602 # number of overall MSHR misses
|
||||
system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 37011000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 37011000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 37011000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 37011000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 37011000 # number of overall MSHR miss cycles
|
||||
system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 37011000 # number of overall MSHR miss cycles
|
||||
system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.376565 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.376565 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.376503 # mshr miss rate for demand accesses
|
||||
system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.376503 # mshr miss rate for demand accesses
|
||||
system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.376503 # mshr miss rate for overall accesses
|
||||
system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.376503 # mshr miss rate for overall accesses
|
||||
system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 8042.372881 # average ReadReq mshr miss latency
|
||||
system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8042.372881 # average ReadReq mshr miss latency
|
||||
system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 8042.372881 # average overall mshr miss latency
|
||||
system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 8042.372881 # average overall mshr miss latency
|
||||
system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 8042.372881 # average overall mshr miss latency
|
||||
system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 8042.372881 # average overall mshr miss latency
|
||||
system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dtb_walker_cache.replacements 7704 # number of replacements
|
||||
system.cpu.dtb_walker_cache.tagsinuse 5.052403 # Cycle average of tags in use
|
||||
system.cpu.dtb_walker_cache.total_refs 13051 # Total number of references to valid blocks.
|
||||
system.cpu.dtb_walker_cache.sampled_refs 7716 # Sample count of references to valid blocks.
|
||||
system.cpu.dtb_walker_cache.avg_refs 1.691420 # Average number of references to valid blocks.
|
||||
system.cpu.dtb_walker_cache.warmup_cycle 5160674969000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 5.052403 # Average occupied blocks per requestor
|
||||
system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.315775 # Average percentage of cache occupancy
|
||||
system.cpu.dtb_walker_cache.occ_percent::total 0.315775 # Average percentage of cache occupancy
|
||||
system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13051 # number of ReadReq hits
|
||||
system.cpu.dtb_walker_cache.ReadReq_hits::total 13051 # number of ReadReq hits
|
||||
system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13051 # number of demand (read+write) hits
|
||||
system.cpu.dtb_walker_cache.demand_hits::total 13051 # number of demand (read+write) hits
|
||||
system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13051 # number of overall hits
|
||||
system.cpu.dtb_walker_cache.overall_hits::total 13051 # number of overall hits
|
||||
system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8896 # number of ReadReq misses
|
||||
system.cpu.dtb_walker_cache.ReadReq_misses::total 8896 # number of ReadReq misses
|
||||
system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8896 # number of demand (read+write) misses
|
||||
system.cpu.dtb_walker_cache.demand_misses::total 8896 # number of demand (read+write) misses
|
||||
system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8896 # number of overall misses
|
||||
system.cpu.dtb_walker_cache.overall_misses::total 8896 # number of overall misses
|
||||
system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 103895500 # number of ReadReq miss cycles
|
||||
system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 103895500 # number of ReadReq miss cycles
|
||||
system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 103895500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dtb_walker_cache.demand_miss_latency::total 103895500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 103895500 # number of overall miss cycles
|
||||
system.cpu.dtb_walker_cache.overall_miss_latency::total 103895500 # number of overall miss cycles
|
||||
system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21947 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dtb_walker_cache.ReadReq_accesses::total 21947 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21947 # number of demand (read+write) accesses
|
||||
system.cpu.dtb_walker_cache.demand_accesses::total 21947 # number of demand (read+write) accesses
|
||||
system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21947 # number of overall (read+write) accesses
|
||||
system.cpu.dtb_walker_cache.overall_accesses::total 21947 # number of overall (read+write) accesses
|
||||
system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.405340 # miss rate for ReadReq accesses
|
||||
system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.405340 # miss rate for ReadReq accesses
|
||||
system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.405340 # miss rate for demand accesses
|
||||
system.cpu.dtb_walker_cache.demand_miss_rate::total 0.405340 # miss rate for demand accesses
|
||||
system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.405340 # miss rate for overall accesses
|
||||
system.cpu.dtb_walker_cache.overall_miss_rate::total 0.405340 # miss rate for overall accesses
|
||||
system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 11678.900629 # average ReadReq miss latency
|
||||
system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 11678.900629 # average ReadReq miss latency
|
||||
system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 11678.900629 # average overall miss latency
|
||||
system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 11678.900629 # average overall miss latency
|
||||
system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 11678.900629 # average overall miss latency
|
||||
system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 11678.900629 # average overall miss latency
|
||||
system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dtb_walker_cache.writebacks::writebacks 2985 # number of writebacks
|
||||
system.cpu.dtb_walker_cache.writebacks::total 2985 # number of writebacks
|
||||
system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 8896 # number of ReadReq MSHR misses
|
||||
system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 8896 # number of ReadReq MSHR misses
|
||||
system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 8896 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dtb_walker_cache.demand_mshr_misses::total 8896 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 8896 # number of overall MSHR misses
|
||||
system.cpu.dtb_walker_cache.overall_mshr_misses::total 8896 # number of overall MSHR misses
|
||||
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 77207000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 77207000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 77207000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 77207000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 77207000 # number of overall MSHR miss cycles
|
||||
system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 77207000 # number of overall MSHR miss cycles
|
||||
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.405340 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.405340 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.405340 # mshr miss rate for demand accesses
|
||||
system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.405340 # mshr miss rate for demand accesses
|
||||
system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.405340 # mshr miss rate for overall accesses
|
||||
system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.405340 # mshr miss rate for overall accesses
|
||||
system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 8678.844424 # average ReadReq mshr miss latency
|
||||
system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8678.844424 # average ReadReq mshr miss latency
|
||||
system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 8678.844424 # average overall mshr miss latency
|
||||
system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 8678.844424 # average overall mshr miss latency
|
||||
system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 8678.844424 # average overall mshr miss latency
|
||||
system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 8678.844424 # average overall mshr miss latency
|
||||
system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 1623424 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 511.997312 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 20011404 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 1623936 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 12.322779 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 44345000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 511.997312 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.999995 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.999995 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 11977182 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 11977182 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 8032009 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 8032009 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 20009191 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 20009191 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 20009191 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 20009191 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 1310824 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 1310824 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 315344 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 315344 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 1626168 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 1626168 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 1626168 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 1626168 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 19851809000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 19851809000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 9514837000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 9514837000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 29366646000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 29366646000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 29366646000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 29366646000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 13288006 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 13288006 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 8347353 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 8347353 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 21635359 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 21635359 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 21635359 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 21635359 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098647 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.098647 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037778 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.037778 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.075163 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.075163 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.075163 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.075163 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15144.526649 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 15144.526649 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30172.881044 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 30172.881044 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 18058.802043 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 18058.802043 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 18058.802043 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 18058.802043 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 1529951 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 1529951 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1310824 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 1310824 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 315344 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 315344 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 1626168 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 1626168 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 1626168 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 1626168 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 15919294500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 15919294500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8568794500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 8568794500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 24488089000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 24488089000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 24488089000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 24488089000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 75925324500 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 75925324500 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1379728500 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1379728500 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 77305053000 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency::total 77305053000 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.098647 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.098647 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037778 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037778 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.075163 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.075163 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.075163 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.075163 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12144.494227 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12144.494227 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27172.847747 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27172.847747 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15058.769451 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 15058.769451 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15058.769451 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 15058.769451 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
@ -0,0 +1,133 @@
|
||||
Linux version 2.6.22.9 (blackga@nacho) (gcc version 4.1.2 (Gentoo 4.1.2)) #2 Mon Oct 8 13:13:00 PDT 2007
|
||||
Command line: earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1
|
||||
BIOS-provided physical RAM map:
|
||||
BIOS-e820: 0000000000000000 - 0000000000100000 (reserved)
|
||||
BIOS-e820: 0000000000100000 - 0000000008000000 (usable)
|
||||
end_pfn_map = 32768
|
||||
kernel direct mapping tables up to 8000000 @ 100000-102000
|
||||
DMI 2.5 present.
|
||||
Zone PFN ranges:
|
||||
DMA 256 -> 4096
|
||||
DMA32 4096 -> 1048576
|
||||
Normal 1048576 -> 1048576
|
||||
early_node_map[1] active PFN ranges
|
||||
0: 256 -> 32768
|
||||
Intel MultiProcessor Specification v1.4
|
||||
MPTABLE: OEM ID: MPTABLE: Product ID: MPTABLE: APIC at: 0xFEE00000
|
||||
Processor #0 (Bootup-CPU)
|
||||
I/O APIC #1 at 0xFEC00000.
|
||||
Setting APIC routing to flat
|
||||
Processors: 1
|
||||
Allocating PCI resources starting at 10000000 (gap: 8000000:f8000000)
|
||||
Built 1 zonelists. Total pages: 30458
|
||||
Kernel command line: earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1
|
||||
Initializing CPU#0
|
||||
PID hash table entries: 512 (order: 9, 4096 bytes)
|
||||
time.c: Detected 1999.998 MHz processor.
|
||||
Console: colour dummy device 80x25
|
||||
console handover: boot [earlyser0] -> real [ttyS0]
|
||||
Dentry cache hash table entries: 16384 (order: 5, 131072 bytes)
|
||||
Inode-cache hash table entries: 8192 (order: 4, 65536 bytes)
|
||||
Checking aperture...
|
||||
Memory: 121556k/131072k available (3742k kernel code, 8456k reserved, 1874k data, 232k init)
|
||||
Calibrating delay loop (skipped)... 3999.96 BogoMIPS preset
|
||||
Mount-cache hash table entries: 256
|
||||
CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)
|
||||
CPU: L2 Cache: 1024K (64 bytes/line)
|
||||
CPU: Fake M5 x86_64 CPU stepping 01
|
||||
ACPI: Core revision 20070126
|
||||
ACPI Exception (tbxface-0618): AE_NO_ACPI_TABLES, While loading namespace from ACPI tables [20070126]
|
||||
ACPI: Unable to load the System Description Tables
|
||||
Using local APIC timer interrupts.
|
||||
result 7812489
|
||||
Detected 7.812 MHz APIC timer.
|
||||
NET: Registered protocol family 16
|
||||
PCI: Using configuration type 1
|
||||
ACPI: Interpreter disabled.
|
||||
Linux Plug and Play Support v0.97 (c) Adam Belay
|
||||
pnp: PnP ACPI: disabled
|
||||
SCSI subsystem initialized
|
||||
usbcore: registered new interface driver usbfs
|
||||
usbcore: registered new interface driver hub
|
||||
usbcore: registered new device driver usb
|
||||
PCI: Probing PCI hardware
|
||||
PCI-GART: No AMD northbridge found.
|
||||
Time: tsc clocksource has been installed.
|
||||
NET: Registered protocol family 2
|
||||
IP route cache hash table entries: 1024 (order: 1, 8192 bytes)
|
||||
TCP established hash table entries: 4096 (order: 4, 65536 bytes)
|
||||
TCP bind hash table entries: 4096 (order: 3, 32768 bytes)
|
||||
TCP: Hash tables configured (established 4096 bind 4096)
|
||||
TCP reno registered
|
||||
Total HugeTLB memory allocated, 0
|
||||
Installing knfsd (copyright (C) 1996 okir@monad.swb.de).
|
||||
io scheduler noop registered
|
||||
io scheduler deadline registered
|
||||
io scheduler cfq registered (default)
|
||||
Real Time Clock Driver v1.12ac
|
||||
Linux agpgart interface v0.102 (c) Dave Jones
|
||||
Serial: 8250/16550 driver $Revision: 1.90 $ 4 ports, IRQ sharing disabled
|
||||
serial8250: ttyS0 at I/O 0x3f8 (irq = 4) is a 8250
|
||||
floppy0: no floppy controllers found
|
||||
RAMDISK driver initialized: 16 RAM disks of 4096K size 1024 blocksize
|
||||
loop: module loaded
|
||||
Intel(R) PRO/1000 Network Driver - version 7.3.20-k2
|
||||
Copyright (c) 1999-2006 Intel Corporation.
|
||||
e100: Intel(R) PRO/100 Network Driver, 3.5.17-k4-NAPI
|
||||
e100: Copyright(c) 1999-2006 Intel Corporation
|
||||
forcedeth.c: Reverse Engineered nForce ethernet driver. Version 0.60.
|
||||
tun: Universal TUN/TAP device driver, 1.6
|
||||
tun: (C) 1999-2004 Max Krasnyansky <maxk@qualcomm.com>
|
||||
netconsole: not configured, aborting
|
||||
Uniform Multi-Platform E-IDE driver Revision: 7.00alpha2
|
||||
ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx
|
||||
PIIX4: IDE controller at PCI slot 0000:00:04.0
|
||||
PCI: Enabling device 0000:00:04.0 (0000 -> 0001)
|
||||
PIIX4: chipset revision 0
|
||||
PIIX4: not 100% native mode: will probe irqs later
|
||||
ide0: BM-DMA at 0x1000-0x1007, BIOS settings: hda:DMA, hdb:DMA
|
||||
ide1: BM-DMA at 0x1008-0x100f, BIOS settings: hdc:DMA, hdd:DMA
|
||||
hda: M5 IDE Disk, ATA DISK drive
|
||||
hdb: M5 IDE Disk, ATA DISK drive
|
||||
ide0 at 0x1f0-0x1f7,0x3f6 on irq 14
|
||||
hda: max request size: 128KiB
|
||||
hda: 1048320 sectors (536 MB), CHS=1040/16/63, UDMA(33)
|
||||
hda: hda1
|
||||
hdb: max request size: 128KiB
|
||||
hdb: 4177920 sectors (2139 MB), CHS=4144/16/63, UDMA(33)
|
||||
hdb: unknown partition table
|
||||
megaraid cmm: 2.20.2.7 (Release Date: Sun Jul 16 00:01:03 EST 2006)
|
||||
megaraid: 2.20.5.1 (Release Date: Thu Nov 16 15:32:35 EST 2006)
|
||||
megasas: 00.00.03.10-rc5 Thu May 17 10:09:32 PDT 2007
|
||||
Fusion MPT base driver 3.04.04
|
||||
Copyright (c) 1999-2007 LSI Logic Corporation
|
||||
Fusion MPT SPI Host driver 3.04.04
|
||||
Fusion MPT SAS Host driver 3.04.04
|
||||
ieee1394: raw1394: /dev/raw1394 device initialized
|
||||
USB Universal Host Controller Interface driver v3.0
|
||||
usbcore: registered new interface driver usblp
|
||||
drivers/usb/class/usblp.c: v0.13: USB Printer Device Class driver
|
||||
Initializing USB Mass Storage driver...
|
||||
usbcore: registered new interface driver usb-storage
|
||||
USB Mass Storage support registered.
|
||||
PNP: No PS/2 controller found. Probing ports directly.
|
||||
serio: i8042 KBD port at 0x60,0x64 irq 1
|
||||
serio: i8042 AUX port at 0x60,0x64 irq 12
|
||||
mice: PS/2 mouse device common for all mice
|
||||
input: AT Translated Set 2 keyboard as /class/input/input0
|
||||
device-mapper: ioctl: 4.11.0-ioctl (2006-10-12) initialised: dm-devel@redhat.com
|
||||
input: PS/2 Generic Mouse as /class/input/input1
|
||||
usbcore: registered new interface driver usbhid
|
||||
drivers/hid/usbhid/hid-core.c: v2.6:USB HID core driver
|
||||
oprofile: using timer interrupt.
|
||||
TCP cubic registered
|
||||
NET: Registered protocol family 1
|
||||
NET: Registered protocol family 10
|
||||
IPv6 over IPv4 tunneling driver
|
||||
NET: Registered protocol family 17
|
||||
EXT2-fs warning: mounting unchecked fs, running e2fsck is recommended
|
||||
VFS: Mounted root (ext2 filesystem).
|
||||
Freeing unused kernel memory: 232k freed
|
||||
|
||||
INIT: version 2.86 booting
|
||||
|
||||
29
simulators/gem5/tests/quick/fs/10.linux-boot/test.py
Normal file
29
simulators/gem5/tests/quick/fs/10.linux-boot/test.py
Normal file
@ -0,0 +1,29 @@
|
||||
# Copyright (c) 2006 The Regents of The University of Michigan
|
||||
# All rights reserved.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are
|
||||
# met: redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer;
|
||||
# redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in the
|
||||
# documentation and/or other materials provided with the distribution;
|
||||
# neither the name of the copyright holders nor the names of its
|
||||
# contributors may be used to endorse or promote products derived from
|
||||
# this software without specific prior written permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
#
|
||||
# Authors: Steve Reinhardt
|
||||
|
||||
root.system.readfile = os.path.join(tests_root, 'halt.sh')
|
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,114 @@
|
||||
M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
|
||||
|
||||
Got Configuration 623
|
||||
|
||||
memsize 8000000 pages 4000
|
||||
|
||||
First free page after ROM 0xFFFFFC0000018000
|
||||
|
||||
HWRPB 0xFFFFFC0000018000 l1pt 0xFFFFFC0000040000 l2pt 0xFFFFFC0000042000 l3pt_rpb 0xFFFFFC0000044000 l3pt_kernel 0xFFFFFC0000048000 l2reserv 0xFFFFFC0000046000
|
||||
|
||||
kstart = 0xFFFFFC0000310000, kend = 0xFFFFFC0000855898, kentry = 0xFFFFFC0000310000, numCPUs = 0x1
|
||||
|
||||
CPU Clock at 1000000 MHz IntrClockFrequency=1024
|
||||
|
||||
Booting with 1 processor(s)
|
||||
|
||||
KSP: 0x20043FE8 PTBR 0x20
|
||||
|
||||
Console Callback at 0x0, fixup at 0x0, crb offset: 0x510
|
||||
|
||||
Memory cluster 0 [0 - 392]
|
||||
|
||||
Memory cluster 1 [392 - 15992]
|
||||
|
||||
Initalizing mdt_bitmap addr 0xFFFFFC0000038000 mem_pages 4000
|
||||
|
||||
ConsoleDispatch at virt 10000658 phys 18658 val FFFFFC00000100A8
|
||||
|
||||
unix_boot_mem ends at FFFFFC0000076000
|
||||
|
||||
k_argc = 0
|
||||
|
||||
jumping to kernel at 0xFFFFFC0000310000, (PCBB 0xFFFFFC0000018180 pfn 1067)
|
||||
|
||||
CallbackFixup 0 18000, t7=FFFFFC000070C000
|
||||
|
||||
Linux version 2.6.13 (hsul@zed.eecs.umich.edu) (gcc version 3.4.3) #1 SMP Sun Oct 8 19:52:07 EDT 2006
|
||||
|
||||
Booting GENERIC on Tsunami variation DP264 using machine vector DP264 from SRM
|
||||
|
||||
Major Options: SMP LEGACY_START VERBOSE_MCHECK
|
||||
|
||||
Command line: root=/dev/hda1 console=ttyS0
|
||||
|
||||
memcluster 0, usage 1, start 0, end 392
|
||||
|
||||
memcluster 1, usage 0, start 392, end 16384
|
||||
|
||||
freeing pages 1069:16384
|
||||
|
||||
reserving pages 1069:1070
|
||||
|
||||
SMP: 1 CPUs probed -- cpu_present_mask = 1
|
||||
|
||||
Built 1 zonelists
|
||||
|
||||
Kernel command line: root=/dev/hda1 console=ttyS0
|
||||
|
||||
PID hash table entries: 1024 (order: 10, 32768 bytes)
|
||||
|
||||
Using epoch = 1900
|
||||
|
||||
Console: colour dummy device 80x25
|
||||
|
||||
Dentry cache hash table entries: 32768 (order: 5, 262144 bytes)
|
||||
|
||||
Inode-cache hash table entries: 16384 (order: 4, 131072 bytes)
|
||||
|
||||
Memory: 118784k/131072k available (3314k kernel code, 8952k reserved, 983k data, 224k init)
|
||||
|
||||
Mount-cache hash table entries: 512
|
||||
|
||||
SMP mode deactivated.
|
||||
|
||||
Brought up 1 CPUs
|
||||
|
||||
SMP: Total of 1 processors activated (1998756.81 BogoMIPS).
|
||||
|
||||
NET: Registered protocol family 16
|
||||
|
||||
EISA bus registered
|
||||
|
||||
pci: enabling save/restore of SRM state
|
||||
|
||||
SCSI subsystem initialized
|
||||
|
||||
srm_env: version 0.0.5 loaded successfully
|
||||
|
||||
Installing knfsd (copyright (C) 1996 okir@monad.swb.de).
|
||||
|
||||
Initializing Cryptographic API
|
||||
|
||||
rtc: Standard PC (1900) epoch (1900) detected
|
||||
|
||||
Real Time Clock Driver v1.12
|
||||
|
||||
Serial: 8250/16550 driver $Revision: 1.90 $ 1 ports, IRQ sharing disabled
|
||||
|
||||
ttyS0 at I/O 0x3f8 (irq = 4) is a 8250
|
||||
|
||||
io scheduler noop registered
|
||||
|
||||
io scheduler anticipatory registered
|
||||
|
||||
io scheduler deadline registered
|
||||
|
||||
io scheduler cfq registered
|
||||
|
||||
loop: loaded (max 8 devices)
|
||||
|
||||
nbd: registered device at major 43
|
||||
|
||||
ns83820.c: National Semiconductor DP83820 10/100/1000 driver.
|
||||
|
||||
@ -0,0 +1,8 @@
|
||||
warn: Sockets disabled, not accepting terminal connections
|
||||
warn: CoherentBus testsys.membus has no snooping ports attached!
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: CoherentBus drivesys.membus has no snooping ports attached!
|
||||
warn: Prefetch instructions in Alpha do not do anything
|
||||
warn: Prefetch instructions in Alpha do not do anything
|
||||
warn: Obsolete M5 ivlb instruction encountered.
|
||||
hack: be nice to actually delete the event here
|
||||
@ -0,0 +1,14 @@
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jun 4 2012 11:50:11
|
||||
gem5 started Jun 4 2012 14:20:01
|
||||
gem5 executing on zizzer
|
||||
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic -re tests/run.py build/ALPHA/tests/opt/quick/fs/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: kernel located at: /dist/m5/system/binaries/vmlinux
|
||||
0: testsys.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
|
||||
info: kernel located at: /dist/m5/system/binaries/vmlinux
|
||||
0: drivesys.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 4300236804024 because checkpoint
|
||||
@ -0,0 +1,674 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.200001 # Number of seconds simulated
|
||||
sim_ticks 200000789468 # Number of ticks simulated
|
||||
final_tick 4300236018046 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 165824466 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 165822505 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 121314189503 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 480536 # Number of bytes of host memory used
|
||||
host_seconds 1.65 # Real time elapsed on the host
|
||||
sim_insts 273374833 # Number of instructions simulated
|
||||
sim_ops 273374833 # Number of ops (including micro ops) simulated
|
||||
testsys.physmem.bytes_read::cpu.inst 14257548 # Number of bytes read from this memory
|
||||
testsys.physmem.bytes_read::cpu.data 4845244 # Number of bytes read from this memory
|
||||
testsys.physmem.bytes_read::tsunami.ethernet 1416 # Number of bytes read from this memory
|
||||
testsys.physmem.bytes_read::total 19104208 # Number of bytes read from this memory
|
||||
testsys.physmem.bytes_inst_read::cpu.inst 14257548 # Number of instructions bytes read from this memory
|
||||
testsys.physmem.bytes_inst_read::total 14257548 # Number of instructions bytes read from this memory
|
||||
testsys.physmem.bytes_written::cpu.data 3887080 # Number of bytes written to this memory
|
||||
testsys.physmem.bytes_written::tsunami.ethernet 902 # Number of bytes written to this memory
|
||||
testsys.physmem.bytes_written::total 3887982 # Number of bytes written to this memory
|
||||
testsys.physmem.num_reads::cpu.inst 3564387 # Number of read requests responded to by this memory
|
||||
testsys.physmem.num_reads::cpu.data 661796 # Number of read requests responded to by this memory
|
||||
testsys.physmem.num_reads::tsunami.ethernet 41 # Number of read requests responded to by this memory
|
||||
testsys.physmem.num_reads::total 4226224 # Number of read requests responded to by this memory
|
||||
testsys.physmem.num_writes::cpu.data 504387 # Number of write requests responded to by this memory
|
||||
testsys.physmem.num_writes::tsunami.ethernet 31 # Number of write requests responded to by this memory
|
||||
testsys.physmem.num_writes::total 504418 # Number of write requests responded to by this memory
|
||||
testsys.physmem.bw_read::cpu.inst 71287459 # Total read bandwidth from this memory (bytes/s)
|
||||
testsys.physmem.bw_read::cpu.data 24226124 # Total read bandwidth from this memory (bytes/s)
|
||||
testsys.physmem.bw_read::tsunami.ethernet 7080 # Total read bandwidth from this memory (bytes/s)
|
||||
testsys.physmem.bw_read::total 95520663 # Total read bandwidth from this memory (bytes/s)
|
||||
testsys.physmem.bw_inst_read::cpu.inst 71287459 # Instruction read bandwidth from this memory (bytes/s)
|
||||
testsys.physmem.bw_inst_read::total 71287459 # Instruction read bandwidth from this memory (bytes/s)
|
||||
testsys.physmem.bw_write::cpu.data 19435323 # Write bandwidth from this memory (bytes/s)
|
||||
testsys.physmem.bw_write::tsunami.ethernet 4510 # Write bandwidth from this memory (bytes/s)
|
||||
testsys.physmem.bw_write::total 19439833 # Write bandwidth from this memory (bytes/s)
|
||||
testsys.physmem.bw_total::cpu.inst 71287459 # Total bandwidth to/from this memory (bytes/s)
|
||||
testsys.physmem.bw_total::cpu.data 43661448 # Total bandwidth to/from this memory (bytes/s)
|
||||
testsys.physmem.bw_total::tsunami.ethernet 11590 # Total bandwidth to/from this memory (bytes/s)
|
||||
testsys.physmem.bw_total::total 114960496 # Total bandwidth to/from this memory (bytes/s)
|
||||
testsys.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
||||
testsys.disk0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
|
||||
testsys.disk0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
|
||||
testsys.disk0.dma_write_full_pages 0 # Number of full page size DMA writes.
|
||||
testsys.disk0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
|
||||
testsys.disk0.dma_write_txs 0 # Number of DMA write transactions.
|
||||
testsys.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
||||
testsys.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
|
||||
testsys.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
|
||||
testsys.disk2.dma_write_full_pages 0 # Number of full page size DMA writes.
|
||||
testsys.disk2.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
|
||||
testsys.disk2.dma_write_txs 0 # Number of DMA write transactions.
|
||||
testsys.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
testsys.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
testsys.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
testsys.cpu.dtb.fetch_accesses 0 # ITB accesses
|
||||
testsys.cpu.dtb.read_hits 658435 # DTB read hits
|
||||
testsys.cpu.dtb.read_misses 3287 # DTB read misses
|
||||
testsys.cpu.dtb.read_acv 80 # DTB read access violations
|
||||
testsys.cpu.dtb.read_accesses 225414 # DTB read accesses
|
||||
testsys.cpu.dtb.write_hits 504853 # DTB write hits
|
||||
testsys.cpu.dtb.write_misses 528 # DTB write misses
|
||||
testsys.cpu.dtb.write_acv 81 # DTB write access violations
|
||||
testsys.cpu.dtb.write_accesses 109988 # DTB write accesses
|
||||
testsys.cpu.dtb.data_hits 1163288 # DTB hits
|
||||
testsys.cpu.dtb.data_misses 3815 # DTB misses
|
||||
testsys.cpu.dtb.data_acv 161 # DTB access violations
|
||||
testsys.cpu.dtb.data_accesses 335402 # DTB accesses
|
||||
testsys.cpu.itb.fetch_hits 1248325 # ITB hits
|
||||
testsys.cpu.itb.fetch_misses 1497 # ITB misses
|
||||
testsys.cpu.itb.fetch_acv 69 # ITB acv
|
||||
testsys.cpu.itb.fetch_accesses 1249822 # ITB accesses
|
||||
testsys.cpu.itb.read_hits 0 # DTB read hits
|
||||
testsys.cpu.itb.read_misses 0 # DTB read misses
|
||||
testsys.cpu.itb.read_acv 0 # DTB read access violations
|
||||
testsys.cpu.itb.read_accesses 0 # DTB read accesses
|
||||
testsys.cpu.itb.write_hits 0 # DTB write hits
|
||||
testsys.cpu.itb.write_misses 0 # DTB write misses
|
||||
testsys.cpu.itb.write_acv 0 # DTB write access violations
|
||||
testsys.cpu.itb.write_accesses 0 # DTB write accesses
|
||||
testsys.cpu.itb.data_hits 0 # DTB hits
|
||||
testsys.cpu.itb.data_misses 0 # DTB misses
|
||||
testsys.cpu.itb.data_acv 0 # DTB access violations
|
||||
testsys.cpu.itb.data_accesses 0 # DTB accesses
|
||||
testsys.cpu.numCycles 199569460393 # number of cpu cycles simulated
|
||||
testsys.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
testsys.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
testsys.cpu.committedInsts 3560411 # Number of instructions committed
|
||||
testsys.cpu.committedOps 3560411 # Number of ops (including micro ops) committed
|
||||
testsys.cpu.num_int_alu_accesses 3348322 # Number of integer alu accesses
|
||||
testsys.cpu.num_fp_alu_accesses 17380 # Number of float alu accesses
|
||||
testsys.cpu.num_func_calls 107994 # number of times a function call or return occured
|
||||
testsys.cpu.num_conditional_control_insts 361828 # number of instructions that are conditional controls
|
||||
testsys.cpu.num_int_insts 3348322 # number of integer instructions
|
||||
testsys.cpu.num_fp_insts 17380 # number of float instructions
|
||||
testsys.cpu.num_int_register_reads 4592571 # number of times the integer registers were read
|
||||
testsys.cpu.num_int_register_writes 2442795 # number of times the integer registers were written
|
||||
testsys.cpu.num_fp_register_reads 11166 # number of times the floating registers were read
|
||||
testsys.cpu.num_fp_register_writes 10823 # number of times the floating registers were written
|
||||
testsys.cpu.num_mem_refs 1173234 # number of memory refs
|
||||
testsys.cpu.num_load_insts 666253 # Number of load instructions
|
||||
testsys.cpu.num_store_insts 506981 # Number of store instructions
|
||||
testsys.cpu.num_idle_cycles 199565902130.465698 # Number of idle cycles
|
||||
testsys.cpu.num_busy_cycles 3558262.534294 # Number of busy cycles
|
||||
testsys.cpu.not_idle_fraction 0.000018 # Percentage of non-idle cycles
|
||||
testsys.cpu.idle_fraction 0.999982 # Percentage of idle cycles
|
||||
testsys.cpu.kern.inst.arm 0 # number of arm instructions executed
|
||||
testsys.cpu.kern.inst.quiesce 376 # number of quiesce instructions executed
|
||||
testsys.cpu.kern.inst.hwrei 19053 # number of hwrei instructions executed
|
||||
testsys.cpu.kern.ipl_count::0 5061 40.48% 40.48% # number of times we switched to this ipl
|
||||
testsys.cpu.kern.ipl_count::21 184 1.47% 41.95% # number of times we switched to this ipl
|
||||
testsys.cpu.kern.ipl_count::22 205 1.64% 43.59% # number of times we switched to this ipl
|
||||
testsys.cpu.kern.ipl_count::31 7054 56.41% 100.00% # number of times we switched to this ipl
|
||||
testsys.cpu.kern.ipl_count::total 12504 # number of times we switched to this ipl
|
||||
testsys.cpu.kern.ipl_good::0 5055 48.15% 48.15% # number of times we switched to this ipl from a different ipl
|
||||
testsys.cpu.kern.ipl_good::21 184 1.75% 49.90% # number of times we switched to this ipl from a different ipl
|
||||
testsys.cpu.kern.ipl_good::22 205 1.95% 51.85% # number of times we switched to this ipl from a different ipl
|
||||
testsys.cpu.kern.ipl_good::31 5055 48.15% 100.00% # number of times we switched to this ipl from a different ipl
|
||||
testsys.cpu.kern.ipl_good::total 10499 # number of times we switched to this ipl from a different ipl
|
||||
testsys.cpu.kern.ipl_ticks::0 199568845670 100.00% 100.00% # number of cycles we spent at this ipl
|
||||
testsys.cpu.kern.ipl_ticks::21 31026 0.00% 100.00% # number of cycles we spent at this ipl
|
||||
testsys.cpu.kern.ipl_ticks::22 17630 0.00% 100.00% # number of cycles we spent at this ipl
|
||||
testsys.cpu.kern.ipl_ticks::31 566504 0.00% 100.00% # number of cycles we spent at this ipl
|
||||
testsys.cpu.kern.ipl_ticks::total 199569460830 # number of cycles we spent at this ipl
|
||||
testsys.cpu.kern.ipl_used::0 0.998814 # fraction of swpipl calls that actually changed the ipl
|
||||
testsys.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
|
||||
testsys.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
|
||||
testsys.cpu.kern.ipl_used::31 0.716615 # fraction of swpipl calls that actually changed the ipl
|
||||
testsys.cpu.kern.ipl_used::total 0.839651 # fraction of swpipl calls that actually changed the ipl
|
||||
testsys.cpu.kern.syscall::2 3 3.61% 3.61% # number of syscalls executed
|
||||
testsys.cpu.kern.syscall::3 7 8.43% 12.05% # number of syscalls executed
|
||||
testsys.cpu.kern.syscall::4 1 1.20% 13.25% # number of syscalls executed
|
||||
testsys.cpu.kern.syscall::6 7 8.43% 21.69% # number of syscalls executed
|
||||
testsys.cpu.kern.syscall::17 7 8.43% 30.12% # number of syscalls executed
|
||||
testsys.cpu.kern.syscall::19 2 2.41% 32.53% # number of syscalls executed
|
||||
testsys.cpu.kern.syscall::20 1 1.20% 33.73% # number of syscalls executed
|
||||
testsys.cpu.kern.syscall::33 3 3.61% 37.35% # number of syscalls executed
|
||||
testsys.cpu.kern.syscall::45 10 12.05% 49.40% # number of syscalls executed
|
||||
testsys.cpu.kern.syscall::48 5 6.02% 55.42% # number of syscalls executed
|
||||
testsys.cpu.kern.syscall::54 1 1.20% 56.63% # number of syscalls executed
|
||||
testsys.cpu.kern.syscall::59 3 3.61% 60.24% # number of syscalls executed
|
||||
testsys.cpu.kern.syscall::71 15 18.07% 78.31% # number of syscalls executed
|
||||
testsys.cpu.kern.syscall::74 4 4.82% 83.13% # number of syscalls executed
|
||||
testsys.cpu.kern.syscall::97 2 2.41% 85.54% # number of syscalls executed
|
||||
testsys.cpu.kern.syscall::98 2 2.41% 87.95% # number of syscalls executed
|
||||
testsys.cpu.kern.syscall::101 2 2.41% 90.36% # number of syscalls executed
|
||||
testsys.cpu.kern.syscall::102 2 2.41% 92.77% # number of syscalls executed
|
||||
testsys.cpu.kern.syscall::104 1 1.20% 93.98% # number of syscalls executed
|
||||
testsys.cpu.kern.syscall::105 3 3.61% 97.59% # number of syscalls executed
|
||||
testsys.cpu.kern.syscall::118 2 2.41% 100.00% # number of syscalls executed
|
||||
testsys.cpu.kern.syscall::total 83 # number of syscalls executed
|
||||
testsys.cpu.kern.callpal::swpctx 438 3.34% 3.34% # number of callpals executed
|
||||
testsys.cpu.kern.callpal::tbi 20 0.15% 3.49% # number of callpals executed
|
||||
testsys.cpu.kern.callpal::swpipl 11074 84.39% 87.88% # number of callpals executed
|
||||
testsys.cpu.kern.callpal::rdps 359 2.74% 90.62% # number of callpals executed
|
||||
testsys.cpu.kern.callpal::wrusp 3 0.02% 90.64% # number of callpals executed
|
||||
testsys.cpu.kern.callpal::rdusp 3 0.02% 90.66% # number of callpals executed
|
||||
testsys.cpu.kern.callpal::rti 1041 7.93% 98.60% # number of callpals executed
|
||||
testsys.cpu.kern.callpal::callsys 140 1.07% 99.66% # number of callpals executed
|
||||
testsys.cpu.kern.callpal::imb 44 0.34% 100.00% # number of callpals executed
|
||||
testsys.cpu.kern.callpal::total 13122 # number of callpals executed
|
||||
testsys.cpu.kern.mode_switch::kernel 1099 # number of protection mode switches
|
||||
testsys.cpu.kern.mode_switch::user 649 # number of protection mode switches
|
||||
testsys.cpu.kern.mode_switch::idle 381 # number of protection mode switches
|
||||
testsys.cpu.kern.mode_good::kernel 654
|
||||
testsys.cpu.kern.mode_good::user 649
|
||||
testsys.cpu.kern.mode_good::idle 5
|
||||
testsys.cpu.kern.mode_switch_good::kernel 0.595086 # fraction of useful protection mode switches
|
||||
testsys.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
|
||||
testsys.cpu.kern.mode_switch_good::idle 0.013123 # fraction of useful protection mode switches
|
||||
testsys.cpu.kern.mode_switch_good::total 0.614373 # fraction of useful protection mode switches
|
||||
testsys.cpu.kern.mode_ticks::kernel 1821131 2.10% 2.10% # number of ticks spent at the given mode
|
||||
testsys.cpu.kern.mode_ticks::user 1065606 1.23% 3.32% # number of ticks spent at the given mode
|
||||
testsys.cpu.kern.mode_ticks::idle 83963628 96.68% 100.00% # number of ticks spent at the given mode
|
||||
testsys.cpu.kern.swap_context 438 # number of times the context was actually changed
|
||||
testsys.tsunami.ethernet.txBytes 960 # Bytes Transmitted
|
||||
testsys.tsunami.ethernet.rxBytes 798 # Bytes Received
|
||||
testsys.tsunami.ethernet.txPackets 8 # Number of Packets Transmitted
|
||||
testsys.tsunami.ethernet.rxPackets 5 # Number of Packets Received
|
||||
testsys.tsunami.ethernet.txIpChecksums 2 # Number of tx IP Checksums done by device
|
||||
testsys.tsunami.ethernet.rxIpChecksums 5 # Number of rx IP Checksums done by device
|
||||
testsys.tsunami.ethernet.txTcpChecksums 2 # Number of tx TCP Checksums done by device
|
||||
testsys.tsunami.ethernet.rxTcpChecksums 5 # Number of rx TCP Checksums done by device
|
||||
testsys.tsunami.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
|
||||
testsys.tsunami.ethernet.rxUdpChecksums 0 # Number of rx UDP Checksums done by device
|
||||
testsys.tsunami.ethernet.descDMAReads 6 # Number of descriptors the device read w/ DMA
|
||||
testsys.tsunami.ethernet.descDMAWrites 13 # Number of descriptors the device wrote w/ DMA
|
||||
testsys.tsunami.ethernet.descDmaReadBytes 144 # number of descriptor bytes read w/ DMA
|
||||
testsys.tsunami.ethernet.descDmaWriteBytes 104 # number of descriptor bytes write w/ DMA
|
||||
testsys.tsunami.ethernet.totBandwidth 70320 # Total Bandwidth (bits/s)
|
||||
testsys.tsunami.ethernet.totPackets 13 # Total Packets
|
||||
testsys.tsunami.ethernet.totBytes 1758 # Total Bytes
|
||||
testsys.tsunami.ethernet.totPPS 65 # Total Tranmission Rate (packets/s)
|
||||
testsys.tsunami.ethernet.txBandwidth 38400 # Transmit Bandwidth (bits/s)
|
||||
testsys.tsunami.ethernet.rxBandwidth 31920 # Receive Bandwidth (bits/s)
|
||||
testsys.tsunami.ethernet.txPPS 40 # Packet Tranmission Rate (packets/s)
|
||||
testsys.tsunami.ethernet.rxPPS 25 # Packet Reception Rate (packets/s)
|
||||
testsys.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
|
||||
testsys.tsunami.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
|
||||
testsys.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
|
||||
testsys.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
|
||||
testsys.tsunami.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post
|
||||
testsys.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
|
||||
testsys.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
|
||||
testsys.tsunami.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post
|
||||
testsys.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
|
||||
testsys.tsunami.ethernet.postedRxDesc 4 # number of RxDesc interrupts posted to CPU
|
||||
testsys.tsunami.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post
|
||||
testsys.tsunami.ethernet.totalRxDesc 5 # total number of RxDesc written to ISR
|
||||
testsys.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
|
||||
testsys.tsunami.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
|
||||
testsys.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
|
||||
testsys.tsunami.ethernet.postedTxIdle 6 # number of TxIdle interrupts posted to CPU
|
||||
testsys.tsunami.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post
|
||||
testsys.tsunami.ethernet.totalTxIdle 6 # total number of TxIdle written to ISR
|
||||
testsys.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
|
||||
testsys.tsunami.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
|
||||
testsys.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
|
||||
testsys.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
|
||||
testsys.tsunami.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
|
||||
testsys.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
|
||||
testsys.tsunami.ethernet.coalescedTotal 1 # average number of interrupts coalesced into each post
|
||||
testsys.tsunami.ethernet.postedInterrupts 15 # number of posts to CPU
|
||||
testsys.tsunami.ethernet.droppedPackets 0 # number of packets dropped
|
||||
drivesys.physmem.bytes_read::cpu.inst 7834952 # Number of bytes read from this memory
|
||||
drivesys.physmem.bytes_read::cpu.data 2784156 # Number of bytes read from this memory
|
||||
drivesys.physmem.bytes_read::tsunami.ethernet 1206 # Number of bytes read from this memory
|
||||
drivesys.physmem.bytes_read::total 10620314 # Number of bytes read from this memory
|
||||
drivesys.physmem.bytes_inst_read::cpu.inst 7834952 # Number of instructions bytes read from this memory
|
||||
drivesys.physmem.bytes_inst_read::total 7834952 # Number of instructions bytes read from this memory
|
||||
drivesys.physmem.bytes_written::cpu.data 1606660 # Number of bytes written to this memory
|
||||
drivesys.physmem.bytes_written::tsunami.ethernet 1064 # Number of bytes written to this memory
|
||||
drivesys.physmem.bytes_written::total 1607724 # Number of bytes written to this memory
|
||||
drivesys.physmem.num_reads::cpu.inst 1958738 # Number of read requests responded to by this memory
|
||||
drivesys.physmem.num_reads::cpu.data 394136 # Number of read requests responded to by this memory
|
||||
drivesys.physmem.num_reads::tsunami.ethernet 33 # Number of read requests responded to by this memory
|
||||
drivesys.physmem.num_reads::total 2352907 # Number of read requests responded to by this memory
|
||||
drivesys.physmem.num_writes::cpu.data 230580 # Number of write requests responded to by this memory
|
||||
drivesys.physmem.num_writes::tsunami.ethernet 37 # Number of write requests responded to by this memory
|
||||
drivesys.physmem.num_writes::total 230617 # Number of write requests responded to by this memory
|
||||
drivesys.physmem.bw_read::cpu.inst 39174605 # Total read bandwidth from this memory (bytes/s)
|
||||
drivesys.physmem.bw_read::cpu.data 13920725 # Total read bandwidth from this memory (bytes/s)
|
||||
drivesys.physmem.bw_read::tsunami.ethernet 6030 # Total read bandwidth from this memory (bytes/s)
|
||||
drivesys.physmem.bw_read::total 53101360 # Total read bandwidth from this memory (bytes/s)
|
||||
drivesys.physmem.bw_inst_read::cpu.inst 39174605 # Instruction read bandwidth from this memory (bytes/s)
|
||||
drivesys.physmem.bw_inst_read::total 39174605 # Instruction read bandwidth from this memory (bytes/s)
|
||||
drivesys.physmem.bw_write::cpu.data 8033268 # Write bandwidth from this memory (bytes/s)
|
||||
drivesys.physmem.bw_write::tsunami.ethernet 5320 # Write bandwidth from this memory (bytes/s)
|
||||
drivesys.physmem.bw_write::total 8038588 # Write bandwidth from this memory (bytes/s)
|
||||
drivesys.physmem.bw_total::cpu.inst 39174605 # Total bandwidth to/from this memory (bytes/s)
|
||||
drivesys.physmem.bw_total::cpu.data 21953993 # Total bandwidth to/from this memory (bytes/s)
|
||||
drivesys.physmem.bw_total::tsunami.ethernet 11350 # Total bandwidth to/from this memory (bytes/s)
|
||||
drivesys.physmem.bw_total::total 61139949 # Total bandwidth to/from this memory (bytes/s)
|
||||
drivesys.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
||||
drivesys.disk0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
|
||||
drivesys.disk0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
|
||||
drivesys.disk0.dma_write_full_pages 0 # Number of full page size DMA writes.
|
||||
drivesys.disk0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
|
||||
drivesys.disk0.dma_write_txs 0 # Number of DMA write transactions.
|
||||
drivesys.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
||||
drivesys.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
|
||||
drivesys.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
|
||||
drivesys.disk2.dma_write_full_pages 0 # Number of full page size DMA writes.
|
||||
drivesys.disk2.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
|
||||
drivesys.disk2.dma_write_txs 0 # Number of DMA write transactions.
|
||||
drivesys.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
drivesys.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
drivesys.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
drivesys.cpu.dtb.fetch_accesses 0 # ITB accesses
|
||||
drivesys.cpu.dtb.read_hits 393500 # DTB read hits
|
||||
drivesys.cpu.dtb.read_misses 487 # DTB read misses
|
||||
drivesys.cpu.dtb.read_acv 30 # DTB read access violations
|
||||
drivesys.cpu.dtb.read_accesses 268057 # DTB read accesses
|
||||
drivesys.cpu.dtb.write_hits 230735 # DTB write hits
|
||||
drivesys.cpu.dtb.write_misses 82 # DTB write misses
|
||||
drivesys.cpu.dtb.write_acv 10 # DTB write access violations
|
||||
drivesys.cpu.dtb.write_accesses 133245 # DTB write accesses
|
||||
drivesys.cpu.dtb.data_hits 624235 # DTB hits
|
||||
drivesys.cpu.dtb.data_misses 569 # DTB misses
|
||||
drivesys.cpu.dtb.data_acv 40 # DTB access violations
|
||||
drivesys.cpu.dtb.data_accesses 401302 # DTB accesses
|
||||
drivesys.cpu.itb.fetch_hits 1337786 # ITB hits
|
||||
drivesys.cpu.itb.fetch_misses 194 # ITB misses
|
||||
drivesys.cpu.itb.fetch_acv 22 # ITB acv
|
||||
drivesys.cpu.itb.fetch_accesses 1337980 # ITB accesses
|
||||
drivesys.cpu.itb.read_hits 0 # DTB read hits
|
||||
drivesys.cpu.itb.read_misses 0 # DTB read misses
|
||||
drivesys.cpu.itb.read_acv 0 # DTB read access violations
|
||||
drivesys.cpu.itb.read_accesses 0 # DTB read accesses
|
||||
drivesys.cpu.itb.write_hits 0 # DTB write hits
|
||||
drivesys.cpu.itb.write_misses 0 # DTB write misses
|
||||
drivesys.cpu.itb.write_acv 0 # DTB write access violations
|
||||
drivesys.cpu.itb.write_accesses 0 # DTB write accesses
|
||||
drivesys.cpu.itb.data_hits 0 # DTB hits
|
||||
drivesys.cpu.itb.data_misses 0 # DTB misses
|
||||
drivesys.cpu.itb.data_acv 0 # DTB access violations
|
||||
drivesys.cpu.itb.data_accesses 0 # DTB accesses
|
||||
drivesys.cpu.numCycles 199571362884 # number of cpu cycles simulated
|
||||
drivesys.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
drivesys.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
drivesys.cpu.committedInsts 1958129 # Number of instructions committed
|
||||
drivesys.cpu.committedOps 1958129 # Number of ops (including micro ops) committed
|
||||
drivesys.cpu.num_int_alu_accesses 1889973 # Number of integer alu accesses
|
||||
drivesys.cpu.num_fp_alu_accesses 1278 # Number of float alu accesses
|
||||
drivesys.cpu.num_func_calls 121650 # number of times a function call or return occured
|
||||
drivesys.cpu.num_conditional_control_insts 161093 # number of instructions that are conditional controls
|
||||
drivesys.cpu.num_int_insts 1889973 # number of integer instructions
|
||||
drivesys.cpu.num_fp_insts 1278 # number of float instructions
|
||||
drivesys.cpu.num_int_register_reads 2411030 # number of times the integer registers were read
|
||||
drivesys.cpu.num_int_register_writes 1442447 # number of times the integer registers were written
|
||||
drivesys.cpu.num_fp_register_reads 694 # number of times the floating registers were read
|
||||
drivesys.cpu.num_fp_register_writes 698 # number of times the floating registers were written
|
||||
drivesys.cpu.num_mem_refs 625939 # number of memory refs
|
||||
drivesys.cpu.num_load_insts 394697 # Number of load instructions
|
||||
drivesys.cpu.num_store_insts 231242 # Number of store instructions
|
||||
drivesys.cpu.num_idle_cycles 199569408136.118042 # Number of idle cycles
|
||||
drivesys.cpu.num_busy_cycles 1954747.881971 # Number of busy cycles
|
||||
drivesys.cpu.not_idle_fraction 0.000010 # Percentage of non-idle cycles
|
||||
drivesys.cpu.idle_fraction 0.999990 # Percentage of idle cycles
|
||||
drivesys.cpu.kern.inst.arm 0 # number of arm instructions executed
|
||||
drivesys.cpu.kern.inst.quiesce 215 # number of quiesce instructions executed
|
||||
drivesys.cpu.kern.inst.hwrei 5483 # number of hwrei instructions executed
|
||||
drivesys.cpu.kern.ipl_count::0 1189 28.37% 28.37% # number of times we switched to this ipl
|
||||
drivesys.cpu.kern.ipl_count::21 10 0.24% 28.61% # number of times we switched to this ipl
|
||||
drivesys.cpu.kern.ipl_count::22 205 4.89% 33.50% # number of times we switched to this ipl
|
||||
drivesys.cpu.kern.ipl_count::31 2787 66.50% 100.00% # number of times we switched to this ipl
|
||||
drivesys.cpu.kern.ipl_count::total 4191 # number of times we switched to this ipl
|
||||
drivesys.cpu.kern.ipl_good::0 1189 45.85% 45.85% # number of times we switched to this ipl from a different ipl
|
||||
drivesys.cpu.kern.ipl_good::21 10 0.39% 46.24% # number of times we switched to this ipl from a different ipl
|
||||
drivesys.cpu.kern.ipl_good::22 205 7.91% 54.15% # number of times we switched to this ipl from a different ipl
|
||||
drivesys.cpu.kern.ipl_good::31 1189 45.85% 100.00% # number of times we switched to this ipl from a different ipl
|
||||
drivesys.cpu.kern.ipl_good::total 2593 # number of times we switched to this ipl from a different ipl
|
||||
drivesys.cpu.kern.ipl_ticks::0 199571043172 100.00% 100.00% # number of cycles we spent at this ipl
|
||||
drivesys.cpu.kern.ipl_ticks::21 1620 0.00% 100.00% # number of cycles we spent at this ipl
|
||||
drivesys.cpu.kern.ipl_ticks::22 17630 0.00% 100.00% # number of cycles we spent at this ipl
|
||||
drivesys.cpu.kern.ipl_ticks::31 300462 0.00% 100.00% # number of cycles we spent at this ipl
|
||||
drivesys.cpu.kern.ipl_ticks::total 199571362884 # number of cycles we spent at this ipl
|
||||
drivesys.cpu.kern.ipl_used::0 1 # fraction of swpipl calls that actually changed the ipl
|
||||
drivesys.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
|
||||
drivesys.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
|
||||
drivesys.cpu.kern.ipl_used::31 0.426624 # fraction of swpipl calls that actually changed the ipl
|
||||
drivesys.cpu.kern.ipl_used::total 0.618707 # fraction of swpipl calls that actually changed the ipl
|
||||
drivesys.cpu.kern.syscall::2 1 4.55% 4.55% # number of syscalls executed
|
||||
drivesys.cpu.kern.syscall::6 3 13.64% 18.18% # number of syscalls executed
|
||||
drivesys.cpu.kern.syscall::17 2 9.09% 27.27% # number of syscalls executed
|
||||
drivesys.cpu.kern.syscall::97 1 4.55% 31.82% # number of syscalls executed
|
||||
drivesys.cpu.kern.syscall::99 2 9.09% 40.91% # number of syscalls executed
|
||||
drivesys.cpu.kern.syscall::101 2 9.09% 50.00% # number of syscalls executed
|
||||
drivesys.cpu.kern.syscall::102 3 13.64% 63.64% # number of syscalls executed
|
||||
drivesys.cpu.kern.syscall::104 1 4.55% 68.18% # number of syscalls executed
|
||||
drivesys.cpu.kern.syscall::105 3 13.64% 81.82% # number of syscalls executed
|
||||
drivesys.cpu.kern.syscall::106 1 4.55% 86.36% # number of syscalls executed
|
||||
drivesys.cpu.kern.syscall::118 2 9.09% 95.45% # number of syscalls executed
|
||||
drivesys.cpu.kern.syscall::150 1 4.55% 100.00% # number of syscalls executed
|
||||
drivesys.cpu.kern.syscall::total 22 # number of syscalls executed
|
||||
drivesys.cpu.kern.callpal::swpctx 70 1.58% 1.58% # number of callpals executed
|
||||
drivesys.cpu.kern.callpal::tbi 5 0.11% 1.69% # number of callpals executed
|
||||
drivesys.cpu.kern.callpal::swpipl 3654 82.24% 83.93% # number of callpals executed
|
||||
drivesys.cpu.kern.callpal::rdps 359 8.08% 92.01% # number of callpals executed
|
||||
drivesys.cpu.kern.callpal::rdusp 1 0.02% 92.03% # number of callpals executed
|
||||
drivesys.cpu.kern.callpal::rti 322 7.25% 99.28% # number of callpals executed
|
||||
drivesys.cpu.kern.callpal::callsys 25 0.56% 99.84% # number of callpals executed
|
||||
drivesys.cpu.kern.callpal::imb 7 0.16% 100.00% # number of callpals executed
|
||||
drivesys.cpu.kern.callpal::total 4443 # number of callpals executed
|
||||
drivesys.cpu.kern.mode_switch::kernel 174 # number of protection mode switches
|
||||
drivesys.cpu.kern.mode_switch::user 107 # number of protection mode switches
|
||||
drivesys.cpu.kern.mode_switch::idle 218 # number of protection mode switches
|
||||
drivesys.cpu.kern.mode_good::kernel 110
|
||||
drivesys.cpu.kern.mode_good::user 107
|
||||
drivesys.cpu.kern.mode_good::idle 3
|
||||
drivesys.cpu.kern.mode_switch_good::kernel 0.632184 # fraction of useful protection mode switches
|
||||
drivesys.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
|
||||
drivesys.cpu.kern.mode_switch_good::idle 0.013761 # fraction of useful protection mode switches
|
||||
drivesys.cpu.kern.mode_switch_good::total 0.440882 # fraction of useful protection mode switches
|
||||
drivesys.cpu.kern.mode_ticks::kernel 263256 0.24% 0.24% # number of ticks spent at the given mode
|
||||
drivesys.cpu.kern.mode_ticks::user 1278343 1.15% 1.39% # number of ticks spent at the given mode
|
||||
drivesys.cpu.kern.mode_ticks::idle 109686421 98.61% 100.00% # number of ticks spent at the given mode
|
||||
drivesys.cpu.kern.swap_context 70 # number of times the context was actually changed
|
||||
drivesys.tsunami.ethernet.txBytes 798 # Bytes Transmitted
|
||||
drivesys.tsunami.ethernet.rxBytes 960 # Bytes Received
|
||||
drivesys.tsunami.ethernet.txPackets 5 # Number of Packets Transmitted
|
||||
drivesys.tsunami.ethernet.rxPackets 8 # Number of Packets Received
|
||||
drivesys.tsunami.ethernet.txIpChecksums 2 # Number of tx IP Checksums done by device
|
||||
drivesys.tsunami.ethernet.rxIpChecksums 8 # Number of rx IP Checksums done by device
|
||||
drivesys.tsunami.ethernet.txTcpChecksums 2 # Number of tx TCP Checksums done by device
|
||||
drivesys.tsunami.ethernet.rxTcpChecksums 8 # Number of rx TCP Checksums done by device
|
||||
drivesys.tsunami.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
|
||||
drivesys.tsunami.ethernet.rxUdpChecksums 0 # Number of rx UDP Checksums done by device
|
||||
drivesys.tsunami.ethernet.descDMAReads 4 # Number of descriptors the device read w/ DMA
|
||||
drivesys.tsunami.ethernet.descDMAWrites 13 # Number of descriptors the device wrote w/ DMA
|
||||
drivesys.tsunami.ethernet.descDmaReadBytes 96 # number of descriptor bytes read w/ DMA
|
||||
drivesys.tsunami.ethernet.descDmaWriteBytes 104 # number of descriptor bytes write w/ DMA
|
||||
drivesys.tsunami.ethernet.totBandwidth 70320 # Total Bandwidth (bits/s)
|
||||
drivesys.tsunami.ethernet.totPackets 13 # Total Packets
|
||||
drivesys.tsunami.ethernet.totBytes 1758 # Total Bytes
|
||||
drivesys.tsunami.ethernet.totPPS 65 # Total Tranmission Rate (packets/s)
|
||||
drivesys.tsunami.ethernet.txBandwidth 31920 # Transmit Bandwidth (bits/s)
|
||||
drivesys.tsunami.ethernet.rxBandwidth 38400 # Receive Bandwidth (bits/s)
|
||||
drivesys.tsunami.ethernet.txPPS 25 # Packet Tranmission Rate (packets/s)
|
||||
drivesys.tsunami.ethernet.rxPPS 40 # Packet Reception Rate (packets/s)
|
||||
drivesys.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
|
||||
drivesys.tsunami.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
|
||||
drivesys.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
|
||||
drivesys.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
|
||||
drivesys.tsunami.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post
|
||||
drivesys.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
|
||||
drivesys.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
|
||||
drivesys.tsunami.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post
|
||||
drivesys.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
|
||||
drivesys.tsunami.ethernet.postedRxDesc 6 # number of RxDesc interrupts posted to CPU
|
||||
drivesys.tsunami.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post
|
||||
drivesys.tsunami.ethernet.totalRxDesc 8 # total number of RxDesc written to ISR
|
||||
drivesys.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
|
||||
drivesys.tsunami.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
|
||||
drivesys.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
|
||||
drivesys.tsunami.ethernet.postedTxIdle 4 # number of TxIdle interrupts posted to CPU
|
||||
drivesys.tsunami.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post
|
||||
drivesys.tsunami.ethernet.totalTxIdle 4 # total number of TxIdle written to ISR
|
||||
drivesys.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
|
||||
drivesys.tsunami.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
|
||||
drivesys.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
|
||||
drivesys.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
|
||||
drivesys.tsunami.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
|
||||
drivesys.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
|
||||
drivesys.tsunami.ethernet.coalescedTotal 1 # average number of interrupts coalesced into each post
|
||||
drivesys.tsunami.ethernet.postedInterrupts 16 # number of posts to CPU
|
||||
drivesys.tsunami.ethernet.droppedPackets 0 # number of packets dropped
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000001 # Number of seconds simulated
|
||||
sim_ticks 785978 # Number of ticks simulated
|
||||
final_tick 4300236804024 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 831242365640 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 739004692869 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2025669508 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 480536 # Number of bytes of host memory used
|
||||
host_seconds 0.00 # Real time elapsed on the host
|
||||
sim_insts 273374833 # Number of instructions simulated
|
||||
sim_ops 273374833 # Number of ops (including micro ops) simulated
|
||||
testsys.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
||||
testsys.disk0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
|
||||
testsys.disk0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
|
||||
testsys.disk0.dma_write_full_pages 0 # Number of full page size DMA writes.
|
||||
testsys.disk0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
|
||||
testsys.disk0.dma_write_txs 0 # Number of DMA write transactions.
|
||||
testsys.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
||||
testsys.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
|
||||
testsys.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
|
||||
testsys.disk2.dma_write_full_pages 0 # Number of full page size DMA writes.
|
||||
testsys.disk2.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
|
||||
testsys.disk2.dma_write_txs 0 # Number of DMA write transactions.
|
||||
testsys.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
testsys.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
testsys.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
testsys.cpu.dtb.fetch_accesses 0 # ITB accesses
|
||||
testsys.cpu.dtb.read_hits 0 # DTB read hits
|
||||
testsys.cpu.dtb.read_misses 0 # DTB read misses
|
||||
testsys.cpu.dtb.read_acv 0 # DTB read access violations
|
||||
testsys.cpu.dtb.read_accesses 0 # DTB read accesses
|
||||
testsys.cpu.dtb.write_hits 0 # DTB write hits
|
||||
testsys.cpu.dtb.write_misses 0 # DTB write misses
|
||||
testsys.cpu.dtb.write_acv 0 # DTB write access violations
|
||||
testsys.cpu.dtb.write_accesses 0 # DTB write accesses
|
||||
testsys.cpu.dtb.data_hits 0 # DTB hits
|
||||
testsys.cpu.dtb.data_misses 0 # DTB misses
|
||||
testsys.cpu.dtb.data_acv 0 # DTB access violations
|
||||
testsys.cpu.dtb.data_accesses 0 # DTB accesses
|
||||
testsys.cpu.itb.fetch_hits 0 # ITB hits
|
||||
testsys.cpu.itb.fetch_misses 0 # ITB misses
|
||||
testsys.cpu.itb.fetch_acv 0 # ITB acv
|
||||
testsys.cpu.itb.fetch_accesses 0 # ITB accesses
|
||||
testsys.cpu.itb.read_hits 0 # DTB read hits
|
||||
testsys.cpu.itb.read_misses 0 # DTB read misses
|
||||
testsys.cpu.itb.read_acv 0 # DTB read access violations
|
||||
testsys.cpu.itb.read_accesses 0 # DTB read accesses
|
||||
testsys.cpu.itb.write_hits 0 # DTB write hits
|
||||
testsys.cpu.itb.write_misses 0 # DTB write misses
|
||||
testsys.cpu.itb.write_acv 0 # DTB write access violations
|
||||
testsys.cpu.itb.write_accesses 0 # DTB write accesses
|
||||
testsys.cpu.itb.data_hits 0 # DTB hits
|
||||
testsys.cpu.itb.data_misses 0 # DTB misses
|
||||
testsys.cpu.itb.data_acv 0 # DTB access violations
|
||||
testsys.cpu.itb.data_accesses 0 # DTB accesses
|
||||
testsys.cpu.numCycles 0 # number of cpu cycles simulated
|
||||
testsys.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
testsys.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
testsys.cpu.committedInsts 0 # Number of instructions committed
|
||||
testsys.cpu.committedOps 0 # Number of ops (including micro ops) committed
|
||||
testsys.cpu.num_int_alu_accesses 0 # Number of integer alu accesses
|
||||
testsys.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
|
||||
testsys.cpu.num_func_calls 0 # number of times a function call or return occured
|
||||
testsys.cpu.num_conditional_control_insts 0 # number of instructions that are conditional controls
|
||||
testsys.cpu.num_int_insts 0 # number of integer instructions
|
||||
testsys.cpu.num_fp_insts 0 # number of float instructions
|
||||
testsys.cpu.num_int_register_reads 0 # number of times the integer registers were read
|
||||
testsys.cpu.num_int_register_writes 0 # number of times the integer registers were written
|
||||
testsys.cpu.num_fp_register_reads 0 # number of times the floating registers were read
|
||||
testsys.cpu.num_fp_register_writes 0 # number of times the floating registers were written
|
||||
testsys.cpu.num_mem_refs 0 # number of memory refs
|
||||
testsys.cpu.num_load_insts 0 # Number of load instructions
|
||||
testsys.cpu.num_store_insts 0 # Number of store instructions
|
||||
testsys.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
testsys.cpu.num_busy_cycles 0 # Number of busy cycles
|
||||
testsys.cpu.not_idle_fraction 0 # Percentage of non-idle cycles
|
||||
testsys.cpu.idle_fraction 1 # Percentage of idle cycles
|
||||
testsys.cpu.kern.inst.arm 0 # number of arm instructions executed
|
||||
testsys.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
|
||||
testsys.cpu.kern.inst.hwrei 0 # number of hwrei instructions executed
|
||||
testsys.cpu.kern.mode_switch::kernel 0 # number of protection mode switches
|
||||
testsys.cpu.kern.mode_switch::user 0 # number of protection mode switches
|
||||
testsys.cpu.kern.mode_switch::idle 0 # number of protection mode switches
|
||||
testsys.cpu.kern.mode_good::kernel 0
|
||||
testsys.cpu.kern.mode_good::user 0
|
||||
testsys.cpu.kern.mode_good::idle 0
|
||||
testsys.cpu.kern.mode_switch_good::kernel nan # fraction of useful protection mode switches
|
||||
testsys.cpu.kern.mode_switch_good::user nan # fraction of useful protection mode switches
|
||||
testsys.cpu.kern.mode_switch_good::idle nan # fraction of useful protection mode switches
|
||||
testsys.cpu.kern.mode_switch_good::total nan # fraction of useful protection mode switches
|
||||
testsys.cpu.kern.mode_ticks::kernel 0 # number of ticks spent at the given mode
|
||||
testsys.cpu.kern.mode_ticks::user 0 # number of ticks spent at the given mode
|
||||
testsys.cpu.kern.mode_ticks::idle 0 # number of ticks spent at the given mode
|
||||
testsys.cpu.kern.swap_context 0 # number of times the context was actually changed
|
||||
testsys.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
|
||||
testsys.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
|
||||
testsys.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
|
||||
testsys.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
|
||||
testsys.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
|
||||
testsys.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
|
||||
testsys.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
|
||||
testsys.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
|
||||
testsys.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
|
||||
testsys.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
|
||||
testsys.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
|
||||
testsys.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
|
||||
testsys.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
|
||||
testsys.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
|
||||
testsys.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
|
||||
testsys.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
|
||||
testsys.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
|
||||
testsys.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
|
||||
testsys.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
|
||||
testsys.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
|
||||
testsys.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
|
||||
testsys.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
|
||||
testsys.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
|
||||
testsys.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
|
||||
testsys.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
|
||||
testsys.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
|
||||
testsys.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
|
||||
testsys.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
|
||||
testsys.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
|
||||
testsys.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
|
||||
testsys.tsunami.ethernet.droppedPackets 0 # number of packets dropped
|
||||
drivesys.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
||||
drivesys.disk0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
|
||||
drivesys.disk0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
|
||||
drivesys.disk0.dma_write_full_pages 0 # Number of full page size DMA writes.
|
||||
drivesys.disk0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
|
||||
drivesys.disk0.dma_write_txs 0 # Number of DMA write transactions.
|
||||
drivesys.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
||||
drivesys.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
|
||||
drivesys.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
|
||||
drivesys.disk2.dma_write_full_pages 0 # Number of full page size DMA writes.
|
||||
drivesys.disk2.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
|
||||
drivesys.disk2.dma_write_txs 0 # Number of DMA write transactions.
|
||||
drivesys.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
drivesys.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
drivesys.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
drivesys.cpu.dtb.fetch_accesses 0 # ITB accesses
|
||||
drivesys.cpu.dtb.read_hits 0 # DTB read hits
|
||||
drivesys.cpu.dtb.read_misses 0 # DTB read misses
|
||||
drivesys.cpu.dtb.read_acv 0 # DTB read access violations
|
||||
drivesys.cpu.dtb.read_accesses 0 # DTB read accesses
|
||||
drivesys.cpu.dtb.write_hits 0 # DTB write hits
|
||||
drivesys.cpu.dtb.write_misses 0 # DTB write misses
|
||||
drivesys.cpu.dtb.write_acv 0 # DTB write access violations
|
||||
drivesys.cpu.dtb.write_accesses 0 # DTB write accesses
|
||||
drivesys.cpu.dtb.data_hits 0 # DTB hits
|
||||
drivesys.cpu.dtb.data_misses 0 # DTB misses
|
||||
drivesys.cpu.dtb.data_acv 0 # DTB access violations
|
||||
drivesys.cpu.dtb.data_accesses 0 # DTB accesses
|
||||
drivesys.cpu.itb.fetch_hits 0 # ITB hits
|
||||
drivesys.cpu.itb.fetch_misses 0 # ITB misses
|
||||
drivesys.cpu.itb.fetch_acv 0 # ITB acv
|
||||
drivesys.cpu.itb.fetch_accesses 0 # ITB accesses
|
||||
drivesys.cpu.itb.read_hits 0 # DTB read hits
|
||||
drivesys.cpu.itb.read_misses 0 # DTB read misses
|
||||
drivesys.cpu.itb.read_acv 0 # DTB read access violations
|
||||
drivesys.cpu.itb.read_accesses 0 # DTB read accesses
|
||||
drivesys.cpu.itb.write_hits 0 # DTB write hits
|
||||
drivesys.cpu.itb.write_misses 0 # DTB write misses
|
||||
drivesys.cpu.itb.write_acv 0 # DTB write access violations
|
||||
drivesys.cpu.itb.write_accesses 0 # DTB write accesses
|
||||
drivesys.cpu.itb.data_hits 0 # DTB hits
|
||||
drivesys.cpu.itb.data_misses 0 # DTB misses
|
||||
drivesys.cpu.itb.data_acv 0 # DTB access violations
|
||||
drivesys.cpu.itb.data_accesses 0 # DTB accesses
|
||||
drivesys.cpu.numCycles 0 # number of cpu cycles simulated
|
||||
drivesys.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
drivesys.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
drivesys.cpu.committedInsts 0 # Number of instructions committed
|
||||
drivesys.cpu.committedOps 0 # Number of ops (including micro ops) committed
|
||||
drivesys.cpu.num_int_alu_accesses 0 # Number of integer alu accesses
|
||||
drivesys.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
|
||||
drivesys.cpu.num_func_calls 0 # number of times a function call or return occured
|
||||
drivesys.cpu.num_conditional_control_insts 0 # number of instructions that are conditional controls
|
||||
drivesys.cpu.num_int_insts 0 # number of integer instructions
|
||||
drivesys.cpu.num_fp_insts 0 # number of float instructions
|
||||
drivesys.cpu.num_int_register_reads 0 # number of times the integer registers were read
|
||||
drivesys.cpu.num_int_register_writes 0 # number of times the integer registers were written
|
||||
drivesys.cpu.num_fp_register_reads 0 # number of times the floating registers were read
|
||||
drivesys.cpu.num_fp_register_writes 0 # number of times the floating registers were written
|
||||
drivesys.cpu.num_mem_refs 0 # number of memory refs
|
||||
drivesys.cpu.num_load_insts 0 # Number of load instructions
|
||||
drivesys.cpu.num_store_insts 0 # Number of store instructions
|
||||
drivesys.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
drivesys.cpu.num_busy_cycles 0 # Number of busy cycles
|
||||
drivesys.cpu.not_idle_fraction 0 # Percentage of non-idle cycles
|
||||
drivesys.cpu.idle_fraction 1 # Percentage of idle cycles
|
||||
drivesys.cpu.kern.inst.arm 0 # number of arm instructions executed
|
||||
drivesys.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
|
||||
drivesys.cpu.kern.inst.hwrei 0 # number of hwrei instructions executed
|
||||
drivesys.cpu.kern.mode_switch::kernel 0 # number of protection mode switches
|
||||
drivesys.cpu.kern.mode_switch::user 0 # number of protection mode switches
|
||||
drivesys.cpu.kern.mode_switch::idle 0 # number of protection mode switches
|
||||
drivesys.cpu.kern.mode_good::kernel 0
|
||||
drivesys.cpu.kern.mode_good::user 0
|
||||
drivesys.cpu.kern.mode_good::idle 0
|
||||
drivesys.cpu.kern.mode_switch_good::kernel nan # fraction of useful protection mode switches
|
||||
drivesys.cpu.kern.mode_switch_good::user nan # fraction of useful protection mode switches
|
||||
drivesys.cpu.kern.mode_switch_good::idle nan # fraction of useful protection mode switches
|
||||
drivesys.cpu.kern.mode_switch_good::total nan # fraction of useful protection mode switches
|
||||
drivesys.cpu.kern.mode_ticks::kernel 0 # number of ticks spent at the given mode
|
||||
drivesys.cpu.kern.mode_ticks::user 0 # number of ticks spent at the given mode
|
||||
drivesys.cpu.kern.mode_ticks::idle 0 # number of ticks spent at the given mode
|
||||
drivesys.cpu.kern.swap_context 0 # number of times the context was actually changed
|
||||
drivesys.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
|
||||
drivesys.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
|
||||
drivesys.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
|
||||
drivesys.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
|
||||
drivesys.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
|
||||
drivesys.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
|
||||
drivesys.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
|
||||
drivesys.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
|
||||
drivesys.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
|
||||
drivesys.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
|
||||
drivesys.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
|
||||
drivesys.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
|
||||
drivesys.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
|
||||
drivesys.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
|
||||
drivesys.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
|
||||
drivesys.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
|
||||
drivesys.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
|
||||
drivesys.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
|
||||
drivesys.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
|
||||
drivesys.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
|
||||
drivesys.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
|
||||
drivesys.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
|
||||
drivesys.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
|
||||
drivesys.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
|
||||
drivesys.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
|
||||
drivesys.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
|
||||
drivesys.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
|
||||
drivesys.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
|
||||
drivesys.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
|
||||
drivesys.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
|
||||
drivesys.tsunami.ethernet.droppedPackets 0 # number of packets dropped
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
@ -0,0 +1,123 @@
|
||||
M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
|
||||
|
||||
Got Configuration 623
|
||||
|
||||
memsize 8000000 pages 4000
|
||||
|
||||
First free page after ROM 0xFFFFFC0000018000
|
||||
|
||||
HWRPB 0xFFFFFC0000018000 l1pt 0xFFFFFC0000040000 l2pt 0xFFFFFC0000042000 l3pt_rpb 0xFFFFFC0000044000 l3pt_kernel 0xFFFFFC0000048000 l2reserv 0xFFFFFC0000046000
|
||||
|
||||
kstart = 0xFFFFFC0000310000, kend = 0xFFFFFC0000855898, kentry = 0xFFFFFC0000310000, numCPUs = 0x1
|
||||
|
||||
CPU Clock at 1000000 MHz IntrClockFrequency=1024
|
||||
|
||||
Booting with 1 processor(s)
|
||||
|
||||
KSP: 0x20043FE8 PTBR 0x20
|
||||
|
||||
Console Callback at 0x0, fixup at 0x0, crb offset: 0x510
|
||||
|
||||
Memory cluster 0 [0 - 392]
|
||||
|
||||
Memory cluster 1 [392 - 15992]
|
||||
|
||||
Initalizing mdt_bitmap addr 0xFFFFFC0000038000 mem_pages 4000
|
||||
|
||||
ConsoleDispatch at virt 10000658 phys 18658 val FFFFFC00000100A8
|
||||
|
||||
unix_boot_mem ends at FFFFFC0000076000
|
||||
|
||||
k_argc = 0
|
||||
|
||||
jumping to kernel at 0xFFFFFC0000310000, (PCBB 0xFFFFFC0000018180 pfn 1067)
|
||||
|
||||
CallbackFixup 0 18000, t7=FFFFFC000070C000
|
||||
|
||||
Linux version 2.6.13 (hsul@zed.eecs.umich.edu) (gcc version 3.4.3) #1 SMP Sun Oct 8 19:52:07 EDT 2006
|
||||
|
||||
Booting GENERIC on Tsunami variation DP264 using machine vector DP264 from SRM
|
||||
|
||||
Major Options: SMP LEGACY_START VERBOSE_MCHECK
|
||||
|
||||
Command line: root=/dev/hda1 console=ttyS0
|
||||
|
||||
memcluster 0, usage 1, start 0, end 392
|
||||
|
||||
memcluster 1, usage 0, start 392, end 16384
|
||||
|
||||
freeing pages 1069:16384
|
||||
|
||||
reserving pages 1069:1070
|
||||
|
||||
SMP: 1 CPUs probed -- cpu_present_mask = 1
|
||||
|
||||
Built 1 zonelists
|
||||
|
||||
Kernel command line: root=/dev/hda1 console=ttyS0
|
||||
|
||||
PID hash table entries: 1024 (order: 10, 32768 bytes)
|
||||
|
||||
Using epoch = 1900
|
||||
|
||||
Console: colour dummy device 80x25
|
||||
|
||||
Dentry cache hash table entries: 32768 (order: 5, 262144 bytes)
|
||||
|
||||
Inode-cache hash table entries: 16384 (order: 4, 131072 bytes)
|
||||
|
||||
Memory: 118784k/131072k available (3314k kernel code, 8952k reserved, 983k data, 224k init)
|
||||
|
||||
Mount-cache hash table entries: 512
|
||||
|
||||
SMP mode deactivated.
|
||||
|
||||
Brought up 1 CPUs
|
||||
|
||||
SMP: Total of 1 processors activated (1998756.81 BogoMIPS).
|
||||
|
||||
NET: Registered protocol family 16
|
||||
|
||||
EISA bus registered
|
||||
|
||||
pci: enabling save/restore of SRM state
|
||||
|
||||
SCSI subsystem initialized
|
||||
|
||||
srm_env: version 0.0.5 loaded successfully
|
||||
|
||||
Installing knfsd (copyright (C) 1996 okir@monad.swb.de).
|
||||
|
||||
Initializing Cryptographic API
|
||||
|
||||
rtc: Standard PC (1900) epoch (1900) detected
|
||||
|
||||
Real Time Clock Driver v1.12
|
||||
|
||||
Serial: 8250/16550 driver $Revision: 1.90 $ 1 ports, IRQ sharing disabled
|
||||
|
||||
ttyS0 at I/O 0x3f8 (irq = 4) is a 8250
|
||||
|
||||
io scheduler noop registered
|
||||
|
||||
io scheduler anticipatory registered
|
||||
|
||||
io scheduler deadline registered
|
||||
|
||||
io scheduler cfq registered
|
||||
|
||||
loop: loaded (max 8 devices)
|
||||
|
||||
nbd: registered device at major 43
|
||||
|
||||
ns83820.c: National Semiconductor DP83820 10/100/1000 driver.
|
||||
|
||||
PCI: Setting latency timer of device 0000:00:01.0 to 64
|
||||
|
||||
eth0: ns83820.c: 0x22c: 00000000, subsystem: 0000:0000
|
||||
|
||||
eth0: enabling optical transceiver
|
||||
|
||||
eth0: using 64 bit addressing.
|
||||
|
||||
eth0: ns83820 v0.22: DP83820 v1.3: 00:90:00:00:00:01 io=0x09000000 irq=30 f=h,sg
|
||||
28
simulators/gem5/tests/quick/fs/80.netperf-stream/test.py
Normal file
28
simulators/gem5/tests/quick/fs/80.netperf-stream/test.py
Normal file
@ -0,0 +1,28 @@
|
||||
# Copyright (c) 2006 The Regents of The University of Michigan
|
||||
# All rights reserved.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are
|
||||
# met: redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer;
|
||||
# redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in the
|
||||
# documentation and/or other materials provided with the distribution;
|
||||
# neither the name of the copyright holders nor the names of its
|
||||
# contributors may be used to endorse or promote products derived from
|
||||
# this software without specific prior written permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
#
|
||||
# Authors: Lisa Hsu
|
||||
|
||||
44
simulators/gem5/tests/quick/se/00.hello.mp/test.py
Normal file
44
simulators/gem5/tests/quick/se/00.hello.mp/test.py
Normal file
@ -0,0 +1,44 @@
|
||||
# Copyright (c) 2006 The Regents of The University of Michigan
|
||||
# All rights reserved.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are
|
||||
# met: redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer;
|
||||
# redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in the
|
||||
# documentation and/or other materials provided with the distribution;
|
||||
# neither the name of the copyright holders nor the names of its
|
||||
# contributors may be used to endorse or promote products derived from
|
||||
# this software without specific prior written permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
#
|
||||
# Authors: Ron Dreslinski
|
||||
|
||||
# workload
|
||||
benchmarks = [
|
||||
"tests/test-progs/hello/bin/alpha/linux/hello", "'hello'",
|
||||
"tests/test-progs/hello/bin/alpha/linux/hello", "'hello'",
|
||||
"tests/test-progs/hello/bin/alpha/linux/hello", "'hello'",
|
||||
"tests/test-progs/hello/bin/alpha/linux/hello", "'hello'",
|
||||
]
|
||||
|
||||
for i, cpu in zip(range(len(cpus)), root.system.cpu):
|
||||
p = LiveProcess()
|
||||
p.executable = benchmarks[i*2]
|
||||
p.cmd = benchmarks[(i*2)+1]
|
||||
root.system.cpu[i].workload = p
|
||||
root.system.cpu[i].max_insts_all_threads = 10000000
|
||||
#root.system.cpu.workload = LiveProcess(cmd = 'hello',
|
||||
# executable = binpath('hello'))
|
||||
@ -0,0 +1,231 @@
|
||||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
full_system=false
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
||||
[system]
|
||||
type=System
|
||||
children=cpu membus physmem
|
||||
boot_osflags=a
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
mem_mode=atomic
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
readfile=
|
||||
symbolfile=
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.membus.slave[0]
|
||||
|
||||
[system.cpu]
|
||||
type=InOrderCPU
|
||||
children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
|
||||
BTBEntries=4096
|
||||
BTBTagSize=16
|
||||
RASSize=16
|
||||
activity=0
|
||||
cachePorts=2
|
||||
checker=Null
|
||||
choiceCtrBits=2
|
||||
choicePredictorSize=8192
|
||||
clock=500
|
||||
cpu_id=0
|
||||
defer_registration=false
|
||||
div16Latency=1
|
||||
div16RepeatRate=1
|
||||
div24Latency=1
|
||||
div24RepeatRate=1
|
||||
div32Latency=1
|
||||
div32RepeatRate=1
|
||||
div8Latency=1
|
||||
div8RepeatRate=1
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
fetchBuffSize=4
|
||||
functionTrace=false
|
||||
functionTraceStart=0
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
globalCtrBits=2
|
||||
globalHistoryBits=13
|
||||
globalPredictorSize=8192
|
||||
instShiftAmt=2
|
||||
interrupts=system.cpu.interrupts
|
||||
itb=system.cpu.itb
|
||||
localCtrBits=2
|
||||
localHistoryBits=11
|
||||
localHistoryTableSize=2048
|
||||
localPredictorSize=2048
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
memBlockSize=64
|
||||
multLatency=1
|
||||
multRepeatRate=1
|
||||
numThreads=1
|
||||
phase=0
|
||||
predType=tournament
|
||||
profile=0
|
||||
progress_interval=0
|
||||
stageTracing=false
|
||||
stageWidth=4
|
||||
system=system
|
||||
threadModel=SMT
|
||||
tracer=system.cpu.tracer
|
||||
workload=system.cpu.workload
|
||||
dcache_port=system.cpu.dcache.cpu_side
|
||||
icache_port=system.cpu.icache.cpu_side
|
||||
|
||||
[system.cpu.dcache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=262144
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.dcache_port
|
||||
mem_side=system.cpu.toL2Bus.slave[1]
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=AlphaTLB
|
||||
size=64
|
||||
|
||||
[system.cpu.icache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=131072
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.icache_port
|
||||
mem_side=system.cpu.toL2Bus.slave[0]
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=AlphaInterrupts
|
||||
|
||||
[system.cpu.itb]
|
||||
type=AlphaTLB
|
||||
size=48
|
||||
|
||||
[system.cpu.l2cache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=false
|
||||
latency=10000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=2097152
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.toL2Bus.master[0]
|
||||
mem_side=system.membus.slave[1]
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
master=system.cpu.l2cache.cpu_side
|
||||
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
|
||||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
|
||||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=hello
|
||||
cwd=
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
ppid=99
|
||||
simpoint=0
|
||||
system=system
|
||||
uid=100
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
master=system.physmem.port[0]
|
||||
slave=system.system_port system.cpu.l2cache.mem_side
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.membus.master[0]
|
||||
|
||||
@ -0,0 +1,2 @@
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
hack: be nice to actually delete the event here
|
||||
@ -0,0 +1,12 @@
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jun 4 2012 11:50:11
|
||||
gem5 started Jun 4 2012 14:15:31
|
||||
gem5 executing on zizzer
|
||||
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/inorder-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/inorder-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
Hello world!
|
||||
Exiting @ tick 21234500 because target called exit()
|
||||
@ -0,0 +1,447 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000021 # Number of seconds simulated
|
||||
sim_ticks 21234500 # Number of ticks simulated
|
||||
final_tick 21234500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 73768 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 73752 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 244499363 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 214444 # Number of bytes of host memory used
|
||||
host_seconds 0.09 # Real time elapsed on the host
|
||||
sim_insts 6404 # Number of instructions simulated
|
||||
sim_ops 6404 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 19264 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 10752 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 30016 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 19264 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 19264 # Number of instructions bytes read from this memory
|
||||
system.physmem.num_reads::cpu.inst 301 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 168 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 469 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 907202901 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 506345805 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 1413548706 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 907202901 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 907202901 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 907202901 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 506345805 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1413548706 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
||||
system.cpu.dtb.read_hits 1186 # DTB read hits
|
||||
system.cpu.dtb.read_misses 7 # DTB read misses
|
||||
system.cpu.dtb.read_acv 0 # DTB read access violations
|
||||
system.cpu.dtb.read_accesses 1193 # DTB read accesses
|
||||
system.cpu.dtb.write_hits 898 # DTB write hits
|
||||
system.cpu.dtb.write_misses 3 # DTB write misses
|
||||
system.cpu.dtb.write_acv 0 # DTB write access violations
|
||||
system.cpu.dtb.write_accesses 901 # DTB write accesses
|
||||
system.cpu.dtb.data_hits 2084 # DTB hits
|
||||
system.cpu.dtb.data_misses 10 # DTB misses
|
||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
||||
system.cpu.dtb.data_accesses 2094 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 908 # ITB hits
|
||||
system.cpu.itb.fetch_misses 17 # ITB misses
|
||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
||||
system.cpu.itb.fetch_accesses 925 # ITB accesses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.itb.write_hits 0 # DTB write hits
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.itb.write_acv 0 # DTB write access violations
|
||||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.itb.data_hits 0 # DTB hits
|
||||
system.cpu.itb.data_misses 0 # DTB misses
|
||||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 17 # Number of system calls
|
||||
system.cpu.numCycles 42470 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.branch_predictor.lookups 1608 # Number of BP lookups
|
||||
system.cpu.branch_predictor.condPredicted 1127 # Number of conditional branches predicted
|
||||
system.cpu.branch_predictor.condIncorrect 712 # Number of conditional branches incorrect
|
||||
system.cpu.branch_predictor.BTBLookups 1187 # Number of BTB lookups
|
||||
system.cpu.branch_predictor.BTBHits 314 # Number of BTB hits
|
||||
system.cpu.branch_predictor.usedRAS 126 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branch_predictor.RASInCorrect 0 # Number of incorrect RAS predictions.
|
||||
system.cpu.branch_predictor.BTBHitPct 26.453243 # BTB Hit Percentage
|
||||
system.cpu.branch_predictor.predictedTaken 464 # Number of Branches Predicted As Taken (True).
|
||||
system.cpu.branch_predictor.predictedNotTaken 1144 # Number of Branches Predicted As Not Taken (False).
|
||||
system.cpu.regfile_manager.intRegFileReads 5213 # Number of Reads from Int. Register File
|
||||
system.cpu.regfile_manager.intRegFileWrites 4580 # Number of Writes to Int. Register File
|
||||
system.cpu.regfile_manager.intRegFileAccesses 9793 # Total Accesses (Read+Write) to the Int. Register File
|
||||
system.cpu.regfile_manager.floatRegFileReads 8 # Number of Reads from FP Register File
|
||||
system.cpu.regfile_manager.floatRegFileWrites 2 # Number of Writes to FP Register File
|
||||
system.cpu.regfile_manager.floatRegFileAccesses 10 # Total Accesses (Read+Write) to the FP Register File
|
||||
system.cpu.regfile_manager.regForwards 2970 # Number of Registers Read Through Forwarding Logic
|
||||
system.cpu.agen_unit.agens 2183 # Number of Address Generations
|
||||
system.cpu.execution_unit.predictedTakenIncorrect 284 # Number of Branches Incorrectly Predicted As Taken.
|
||||
system.cpu.execution_unit.predictedNotTakenIncorrect 367 # Number of Branches Incorrectly Predicted As Not Taken).
|
||||
system.cpu.execution_unit.mispredicted 651 # Number of Branches Incorrectly Predicted
|
||||
system.cpu.execution_unit.predicted 401 # Number of Branches Incorrectly Predicted
|
||||
system.cpu.execution_unit.mispredictPct 61.882129 # Percentage of Incorrect Branches Predicts
|
||||
system.cpu.execution_unit.executions 4474 # Number of Instructions Executed.
|
||||
system.cpu.mult_div_unit.multiplies 1 # Number of Multipy Operations Executed
|
||||
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
|
||||
system.cpu.contextSwitches 1 # Number of context switches
|
||||
system.cpu.threadCycles 11434 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
|
||||
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
|
||||
system.cpu.timesIdled 443 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 35079 # Number of cycles cpu's stages were not processed
|
||||
system.cpu.runCycles 7391 # Number of cycles cpu stages are processed.
|
||||
system.cpu.activity 17.402873 # Percentage of cycles cpu is active
|
||||
system.cpu.comLoads 1185 # Number of Load instructions committed
|
||||
system.cpu.comStores 865 # Number of Store instructions committed
|
||||
system.cpu.comBranches 1051 # Number of Branches instructions committed
|
||||
system.cpu.comNops 17 # Number of Nop instructions committed
|
||||
system.cpu.comNonSpec 17 # Number of Non-Speculative instructions committed
|
||||
system.cpu.comInts 3265 # Number of Integer instructions committed
|
||||
system.cpu.comFloats 2 # Number of Floating Point instructions committed
|
||||
system.cpu.committedInsts 6404 # Number of Instructions committed (Per-Thread)
|
||||
system.cpu.committedOps 6404 # Number of Ops committed (Per-Thread)
|
||||
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
|
||||
system.cpu.committedInsts_total 6404 # Number of Instructions committed (Total)
|
||||
system.cpu.cpi 6.631793 # CPI: Cycles Per Instruction (Per-Thread)
|
||||
system.cpu.smt_cpi nan # CPI: Total SMT-CPI
|
||||
system.cpu.cpi_total 6.631793 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 0.150789 # IPC: Instructions Per Cycle (Per-Thread)
|
||||
system.cpu.smt_ipc nan # IPC: Total SMT-IPC
|
||||
system.cpu.ipc_total 0.150789 # IPC: Total IPC of All Threads
|
||||
system.cpu.stage0.idleCycles 37550 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage0.runCycles 4920 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage0.utilization 11.584648 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage1.idleCycles 38585 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage1.runCycles 3885 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage1.utilization 9.147634 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage2.idleCycles 38290 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage2.runCycles 4180 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage2.utilization 9.842242 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage3.idleCycles 41130 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage3.runCycles 1340 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage3.utilization 3.155168 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage4.idleCycles 38002 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage4.runCycles 4468 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage4.utilization 10.520367 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.icache.replacements 0 # number of replacements
|
||||
system.cpu.icache.tagsinuse 138.955928 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 558 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 301 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 1.853821 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 138.955928 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.067850 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.067850 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 558 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 558 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 558 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 558 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 558 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 558 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 350 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 350 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 350 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 350 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 350 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 350 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 19343500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 19343500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 19343500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 19343500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 19343500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 19343500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 908 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 908 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 908 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 908 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 908 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 908 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.385463 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.385463 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.385463 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.385463 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.385463 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.385463 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55267.142857 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 55267.142857 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 55267.142857 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 55267.142857 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 55267.142857 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 55267.142857 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 48 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::total 48 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::cpu.inst 48 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::total 48 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::cpu.inst 48 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::total 48 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 302 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 302 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 302 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 302 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 302 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 302 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16051500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 16051500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16051500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 16051500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16051500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 16051500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.332599 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.332599 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.332599 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.332599 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.332599 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.332599 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53150.662252 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53150.662252 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53150.662252 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 53150.662252 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53150.662252 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 53150.662252 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 102.711534 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 1703 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 168 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 10.136905 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 102.711534 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.025076 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.025076 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 1088 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 1088 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 615 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 615 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 1703 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 1703 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 1703 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 1703 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 97 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 97 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 250 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 250 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 347 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 347 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 347 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 347 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 5507500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 5507500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 13555000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 13555000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 19062500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 19062500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 19062500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 19062500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 1185 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 1185 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 2050 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 2050 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 2050 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 2050 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.081857 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.081857 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289017 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.289017 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.169268 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.169268 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.169268 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.169268 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56778.350515 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 56778.350515 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54220 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 54220 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 54935.158501 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 54935.158501 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 54935.158501 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 54935.158501 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 1656000 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 36 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets 46000 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 2 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 177 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 177 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 179 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 179 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 179 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 179 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 95 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 95 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 168 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 168 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 168 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5113000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 5113000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3909500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3909500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9022500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 9022500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9022500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 9022500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.080169 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.080169 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.081951 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.081951 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.081951 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.081951 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53821.052632 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53821.052632 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53554.794521 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53554.794521 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53705.357143 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 53705.357143 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53705.357143 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 53705.357143 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 195.300582 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 395 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 0.002532 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 139.031748 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 56.268833 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.004243 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.001717 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.005960 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 1 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 301 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.data 95 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 396 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 73 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 73 # number of ReadExReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 301 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 168 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 469 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 301 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 168 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 469 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15708000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4994000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 20702000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3821500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 3821500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 15708000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 8815500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 24523500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 15708000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 8815500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 24523500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 302 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 95 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 397 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 73 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 302 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 168 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 470 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 302 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 168 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 470 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996689 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.997481 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996689 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.997872 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996689 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.997872 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52186.046512 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52568.421053 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52277.777778 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52349.315068 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52349.315068 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52186.046512 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52473.214286 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52288.912580 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52186.046512 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52473.214286 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52288.912580 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 301 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 95 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::total 396 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 73 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 73 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 301 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 168 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 469 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 301 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 469 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12038500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3838000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15876500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2942500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2942500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12038500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6780500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 18819000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12038500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6780500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 18819000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997481 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.997872 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.997872 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39995.016611 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40400 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40092.171717 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40308.219178 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40308.219178 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39995.016611 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40360.119048 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40125.799574 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39995.016611 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40360.119048 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40125.799574 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
@ -0,0 +1,529 @@
|
||||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
full_system=false
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
||||
[system]
|
||||
type=System
|
||||
children=cpu membus physmem
|
||||
boot_osflags=a
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
mem_mode=atomic
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
readfile=
|
||||
symbolfile=
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.membus.slave[0]
|
||||
|
||||
[system.cpu]
|
||||
type=DerivO3CPU
|
||||
children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
|
||||
BTBEntries=4096
|
||||
BTBTagSize=16
|
||||
LFSTSize=1024
|
||||
LQEntries=32
|
||||
LSQCheckLoads=true
|
||||
LSQDepCheckShift=4
|
||||
RASSize=16
|
||||
SQEntries=32
|
||||
SSITSize=1024
|
||||
activity=0
|
||||
backComSize=5
|
||||
cachePorts=200
|
||||
checker=Null
|
||||
choiceCtrBits=2
|
||||
choicePredictorSize=8192
|
||||
clock=500
|
||||
commitToDecodeDelay=1
|
||||
commitToFetchDelay=1
|
||||
commitToIEWDelay=1
|
||||
commitToRenameDelay=1
|
||||
commitWidth=8
|
||||
cpu_id=0
|
||||
decodeToFetchDelay=1
|
||||
decodeToRenameDelay=1
|
||||
decodeWidth=8
|
||||
defer_registration=false
|
||||
dispatchWidth=8
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
fetchToDecodeDelay=1
|
||||
fetchTrapLatency=1
|
||||
fetchWidth=8
|
||||
forwardComSize=5
|
||||
fuPool=system.cpu.fuPool
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
globalCtrBits=2
|
||||
globalHistoryBits=13
|
||||
globalPredictorSize=8192
|
||||
iewToCommitDelay=1
|
||||
iewToDecodeDelay=1
|
||||
iewToFetchDelay=1
|
||||
iewToRenameDelay=1
|
||||
instShiftAmt=2
|
||||
interrupts=system.cpu.interrupts
|
||||
issueToExecuteDelay=1
|
||||
issueWidth=8
|
||||
itb=system.cpu.itb
|
||||
localCtrBits=2
|
||||
localHistoryBits=11
|
||||
localHistoryTableSize=2048
|
||||
localPredictorSize=2048
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
needsTSO=false
|
||||
numIQEntries=64
|
||||
numPhysFloatRegs=256
|
||||
numPhysIntRegs=256
|
||||
numROBEntries=192
|
||||
numRobs=1
|
||||
numThreads=1
|
||||
phase=0
|
||||
predType=tournament
|
||||
profile=0
|
||||
progress_interval=0
|
||||
renameToDecodeDelay=1
|
||||
renameToFetchDelay=1
|
||||
renameToIEWDelay=2
|
||||
renameToROBDelay=1
|
||||
renameWidth=8
|
||||
smtCommitPolicy=RoundRobin
|
||||
smtFetchPolicy=SingleThread
|
||||
smtIQPolicy=Partitioned
|
||||
smtIQThreshold=100
|
||||
smtLSQPolicy=Partitioned
|
||||
smtLSQThreshold=100
|
||||
smtNumFetchingThreads=1
|
||||
smtROBPolicy=Partitioned
|
||||
smtROBThreshold=100
|
||||
squashWidth=8
|
||||
store_set_clear_period=250000
|
||||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
trapLatency=13
|
||||
wbDepth=1
|
||||
wbWidth=8
|
||||
workload=system.cpu.workload
|
||||
dcache_port=system.cpu.dcache.cpu_side
|
||||
icache_port=system.cpu.icache.cpu_side
|
||||
|
||||
[system.cpu.dcache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=262144
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=20
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.dcache_port
|
||||
mem_side=system.cpu.toL2Bus.slave[1]
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=AlphaTLB
|
||||
size=64
|
||||
|
||||
[system.cpu.fuPool]
|
||||
type=FUPool
|
||||
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
|
||||
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
|
||||
|
||||
[system.cpu.fuPool.FUList0]
|
||||
type=FUDesc
|
||||
children=opList
|
||||
count=6
|
||||
opList=system.cpu.fuPool.FUList0.opList
|
||||
|
||||
[system.cpu.fuPool.FUList0.opList]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=IntAlu
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList1]
|
||||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=2
|
||||
opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=IntMult
|
||||
opLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList1]
|
||||
type=OpDesc
|
||||
issueLat=19
|
||||
opClass=IntDiv
|
||||
opLat=20
|
||||
|
||||
[system.cpu.fuPool.FUList2]
|
||||
type=FUDesc
|
||||
children=opList0 opList1 opList2
|
||||
count=4
|
||||
opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=FloatAdd
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList1]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=FloatCmp
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList2]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=FloatCvt
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList3]
|
||||
type=FUDesc
|
||||
children=opList0 opList1 opList2
|
||||
count=2
|
||||
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=FloatMult
|
||||
opLat=4
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList1]
|
||||
type=OpDesc
|
||||
issueLat=12
|
||||
opClass=FloatDiv
|
||||
opLat=12
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList2]
|
||||
type=OpDesc
|
||||
issueLat=24
|
||||
opClass=FloatSqrt
|
||||
opLat=24
|
||||
|
||||
[system.cpu.fuPool.FUList4]
|
||||
type=FUDesc
|
||||
children=opList
|
||||
count=0
|
||||
opList=system.cpu.fuPool.FUList4.opList
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5]
|
||||
type=FUDesc
|
||||
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
|
||||
count=4
|
||||
opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList00]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdAdd
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList01]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdAddAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList02]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdAlu
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList03]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdCmp
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList04]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdCvt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList05]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdMisc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList06]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdMult
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList07]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdMultAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList08]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdShift
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList09]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdShiftAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList10]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdSqrt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList11]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatAdd
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList12]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatAlu
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList13]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatCmp
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList14]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatCvt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList15]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatDiv
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList16]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatMisc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList17]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatMult
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList18]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatMultAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList19]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatSqrt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList6]
|
||||
type=FUDesc
|
||||
children=opList
|
||||
count=0
|
||||
opList=system.cpu.fuPool.FUList6.opList
|
||||
|
||||
[system.cpu.fuPool.FUList6.opList]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList7]
|
||||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=4
|
||||
opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList1]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList8]
|
||||
type=FUDesc
|
||||
children=opList
|
||||
count=1
|
||||
opList=system.cpu.fuPool.FUList8.opList
|
||||
|
||||
[system.cpu.fuPool.FUList8.opList]
|
||||
type=OpDesc
|
||||
issueLat=3
|
||||
opClass=IprAccess
|
||||
opLat=3
|
||||
|
||||
[system.cpu.icache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=131072
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=20
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.icache_port
|
||||
mem_side=system.cpu.toL2Bus.slave[0]
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=AlphaInterrupts
|
||||
|
||||
[system.cpu.itb]
|
||||
type=AlphaTLB
|
||||
size=48
|
||||
|
||||
[system.cpu.l2cache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=false
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=2097152
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.toL2Bus.master[0]
|
||||
mem_side=system.membus.slave[1]
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
master=system.cpu.l2cache.cpu_side
|
||||
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
|
||||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
|
||||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=hello
|
||||
cwd=
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
ppid=99
|
||||
simpoint=0
|
||||
system=system
|
||||
uid=100
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
master=system.physmem.port[0]
|
||||
slave=system.system_port system.cpu.l2cache.mem_side
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.membus.master[0]
|
||||
|
||||
2
simulators/gem5/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simerr
Executable file
2
simulators/gem5/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simerr
Executable file
@ -0,0 +1,2 @@
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
hack: be nice to actually delete the event here
|
||||
12
simulators/gem5/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout
Executable file
12
simulators/gem5/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout
Executable file
@ -0,0 +1,12 @@
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jun 4 2012 11:50:11
|
||||
gem5 started Jun 4 2012 14:03:27
|
||||
gem5 executing on zizzer
|
||||
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
Hello world!
|
||||
Exiting @ tick 12450500 because target called exit()
|
||||
@ -0,0 +1,648 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000012 # Number of seconds simulated
|
||||
sim_ticks 12450500 # Number of ticks simulated
|
||||
final_tick 12450500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 73568 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 73552 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 143373020 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 215332 # Number of bytes of host memory used
|
||||
host_seconds 0.09 # Real time elapsed on the host
|
||||
sim_insts 6386 # Number of instructions simulated
|
||||
sim_ops 6386 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 20096 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 11264 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 31360 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 20096 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 20096 # Number of instructions bytes read from this memory
|
||||
system.physmem.num_reads::cpu.inst 314 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 176 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 490 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 1614071724 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 904702622 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 2518774346 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 1614071724 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 1614071724 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 1614071724 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 904702622 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 2518774346 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
||||
system.cpu.dtb.read_hits 1943 # DTB read hits
|
||||
system.cpu.dtb.read_misses 53 # DTB read misses
|
||||
system.cpu.dtb.read_acv 0 # DTB read access violations
|
||||
system.cpu.dtb.read_accesses 1996 # DTB read accesses
|
||||
system.cpu.dtb.write_hits 1071 # DTB write hits
|
||||
system.cpu.dtb.write_misses 32 # DTB write misses
|
||||
system.cpu.dtb.write_acv 0 # DTB write access violations
|
||||
system.cpu.dtb.write_accesses 1103 # DTB write accesses
|
||||
system.cpu.dtb.data_hits 3014 # DTB hits
|
||||
system.cpu.dtb.data_misses 85 # DTB misses
|
||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
||||
system.cpu.dtb.data_accesses 3099 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 2367 # ITB hits
|
||||
system.cpu.itb.fetch_misses 26 # ITB misses
|
||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
||||
system.cpu.itb.fetch_accesses 2393 # ITB accesses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.itb.write_hits 0 # DTB write hits
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.itb.write_acv 0 # DTB write access violations
|
||||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.itb.data_hits 0 # DTB hits
|
||||
system.cpu.itb.data_misses 0 # DTB misses
|
||||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 17 # Number of system calls
|
||||
system.cpu.numCycles 24902 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.BPredUnit.lookups 2873 # Number of BP lookups
|
||||
system.cpu.BPredUnit.condPredicted 1642 # Number of conditional branches predicted
|
||||
system.cpu.BPredUnit.condIncorrect 561 # Number of conditional branches incorrect
|
||||
system.cpu.BPredUnit.BTBLookups 2186 # Number of BTB lookups
|
||||
system.cpu.BPredUnit.BTBHits 748 # Number of BTB hits
|
||||
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu.BPredUnit.usedRAS 430 # Number of times the RAS was used to get a target.
|
||||
system.cpu.BPredUnit.RASInCorrect 100 # Number of incorrect RAS predictions.
|
||||
system.cpu.fetch.icacheStallCycles 7799 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.Insts 16643 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.Branches 2873 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.predictedBranches 1178 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.Cycles 2979 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.SquashCycles 1864 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.BlockedCycles 854 # Number of cycles fetch has spent blocked
|
||||
system.cpu.fetch.MiscStallCycles 22 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
||||
system.cpu.fetch.PendingTrapStallCycles 590 # Number of stall cycles due to pending traps
|
||||
system.cpu.fetch.CacheLines 2367 # Number of cache lines fetched
|
||||
system.cpu.fetch.IcacheSquashes 368 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.rateDist::samples 13505 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 1.232358 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 2.611762 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 10526 77.94% 77.94% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 289 2.14% 80.08% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 251 1.86% 81.94% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 257 1.90% 83.84% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 272 2.01% 85.86% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 206 1.53% 87.38% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 248 1.84% 89.22% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 173 1.28% 90.50% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 1283 9.50% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::total 13505 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.branchRate 0.115372 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.rate 0.668340 # Number of inst fetches per cycle
|
||||
system.cpu.decode.IdleCycles 8546 # Number of cycles decode is idle
|
||||
system.cpu.decode.BlockedCycles 938 # Number of cycles decode is blocked
|
||||
system.cpu.decode.RunCycles 2784 # Number of cycles decode is running
|
||||
system.cpu.decode.UnblockCycles 62 # Number of cycles decode is unblocking
|
||||
system.cpu.decode.SquashCycles 1175 # Number of cycles decode is squashing
|
||||
system.cpu.decode.BranchResolved 292 # Number of times decode resolved a branch
|
||||
system.cpu.decode.BranchMispred 96 # Number of times decode detected a branch misprediction
|
||||
system.cpu.decode.DecodedInsts 15310 # Number of instructions handled by decode
|
||||
system.cpu.decode.SquashedInsts 265 # Number of squashed instructions handled by decode
|
||||
system.cpu.rename.SquashCycles 1175 # Number of cycles rename is squashing
|
||||
system.cpu.rename.IdleCycles 8782 # Number of cycles rename is idle
|
||||
system.cpu.rename.BlockCycles 334 # Number of cycles rename is blocking
|
||||
system.cpu.rename.serializeStallCycles 357 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RunCycles 2587 # Number of cycles rename is running
|
||||
system.cpu.rename.UnblockCycles 270 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RenamedInsts 14488 # Number of instructions processed by rename
|
||||
system.cpu.rename.IQFullEvents 7 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.LSQFullEvents 212 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RenamedOperands 10864 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RenameLookups 18125 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.int_rename_lookups 18108 # Number of integer rename lookups
|
||||
system.cpu.rename.fp_rename_lookups 17 # Number of floating rename lookups
|
||||
system.cpu.rename.CommittedMaps 4583 # Number of HB maps that are committed
|
||||
system.cpu.rename.UndoneMaps 6281 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.serializingInsts 28 # count of serializing insts renamed
|
||||
system.cpu.rename.tempSerializingInsts 22 # count of temporary serializing insts renamed
|
||||
system.cpu.rename.skidInsts 777 # count of insts added to the skid buffer
|
||||
system.cpu.memDep0.insertedLoads 2616 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 1352 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.conflictingLoads 7 # Number of conflicting loads.
|
||||
system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores.
|
||||
system.cpu.iq.iqInstsAdded 12765 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqNonSpecInstsAdded 26 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqInstsIssued 10522 # Number of instructions issued
|
||||
system.cpu.iq.iqSquashedInstsIssued 44 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedInstsExamined 6026 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedOperandsExamined 3602 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 9 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.issued_per_cycle::samples 13505 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::mean 0.779119 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::stdev 1.404443 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::0 9165 67.86% 67.86% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::1 1484 10.99% 78.85% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::2 1164 8.62% 87.47% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::3 762 5.64% 93.11% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::4 469 3.47% 96.59% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::5 274 2.03% 98.62% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::6 142 1.05% 99.67% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::7 34 0.25% 99.92% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::8 11 0.08% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::total 13505 # Number of insts issued each cycle
|
||||
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntAlu 10 8.93% 8.93% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntMult 0 0.00% 8.93% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntDiv 0 0.00% 8.93% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.93% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.93% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.93% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatMult 0 0.00% 8.93% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.93% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.93% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.93% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.93% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.93% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.93% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.93% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.93% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdMult 0 0.00% 8.93% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.93% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdShift 0 0.00% 8.93% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.93% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.93% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.93% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.93% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.93% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.93% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.93% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.93% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.93% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.93% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.93% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::MemRead 65 58.04% 66.96% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::MemWrite 37 33.04% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntAlu 7148 67.93% 67.95% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.96% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.96% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.98% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.98% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.98% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.98% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.98% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.98% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.98% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.98% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.98% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.98% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.98% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.98% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.98% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.98% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.98% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.98% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.98% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.98% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.98% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.98% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.98% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.98% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.98% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.98% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.98% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.98% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::MemRead 2225 21.15% 89.13% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::MemWrite 1144 10.87% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::total 10522 # Type of FU issued
|
||||
system.cpu.iq.rate 0.422536 # Inst issue rate
|
||||
system.cpu.iq.fu_busy_cnt 112 # FU busy when requested
|
||||
system.cpu.iq.fu_busy_rate 0.010644 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.int_inst_queue_reads 34684 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_writes 18825 # Number of integer instruction queue writes
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 9477 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads
|
||||
system.cpu.iq.fp_inst_queue_writes 10 # Number of floating instruction queue writes
|
||||
system.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses
|
||||
system.cpu.iq.int_alu_accesses 10621 # Number of integer alu accesses
|
||||
system.cpu.iq.fp_alu_accesses 11 # Number of floating point alu accesses
|
||||
system.cpu.iew.lsq.thread0.forwLoads 63 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread0.squashedLoads 1431 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread0.squashedStores 487 # Number of stores squashed
|
||||
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
||||
system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||||
system.cpu.iew.iewSquashCycles 1175 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewBlockCycles 41 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewUnblockCycles 1 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.iewDispatchedInsts 12870 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewDispSquashedInsts 183 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispLoadInsts 2616 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispStoreInsts 1352 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 26 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.memOrderViolationEvents 19 # Number of memory order violations
|
||||
system.cpu.iew.predictedTakenIncorrect 166 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.iew.predictedNotTakenIncorrect 401 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.branchMispredicts 567 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewExecutedInsts 9878 # Number of executed instructions
|
||||
system.cpu.iew.iewExecLoadInsts 2009 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 644 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
||||
system.cpu.iew.exec_nop 79 # number of nop insts executed
|
||||
system.cpu.iew.exec_refs 3117 # number of memory reference insts executed
|
||||
system.cpu.iew.exec_branches 1605 # Number of branches executed
|
||||
system.cpu.iew.exec_stores 1108 # Number of stores executed
|
||||
system.cpu.iew.exec_rate 0.396675 # Inst execution rate
|
||||
system.cpu.iew.wb_sent 9634 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.wb_count 9487 # cumulative count of insts written-back
|
||||
system.cpu.iew.wb_producers 4957 # num instructions producing a value
|
||||
system.cpu.iew.wb_consumers 6732 # num instructions consuming a value
|
||||
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
||||
system.cpu.iew.wb_rate 0.380973 # insts written-back per cycle
|
||||
system.cpu.iew.wb_fanout 0.736334 # average fanout of values written-back
|
||||
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||
system.cpu.commit.commitCommittedInsts 6403 # The number of committed instructions
|
||||
system.cpu.commit.commitCommittedOps 6403 # The number of committed instructions
|
||||
system.cpu.commit.commitSquashedInsts 6436 # The number of squashed insts skipped by commit
|
||||
system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu.commit.branchMispredicts 475 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.committed_per_cycle::samples 12330 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::mean 0.519303 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::stdev 1.354208 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::0 9591 77.79% 77.79% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::1 1448 11.74% 89.53% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::2 489 3.97% 93.50% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::3 259 2.10% 95.60% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::4 152 1.23% 96.83% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::5 96 0.78% 97.61% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::6 104 0.84% 98.45% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::7 40 0.32% 98.78% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::8 151 1.22% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::total 12330 # Number of insts commited each cycle
|
||||
system.cpu.commit.committedInsts 6403 # Number of instructions committed
|
||||
system.cpu.commit.committedOps 6403 # Number of ops (including micro ops) committed
|
||||
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
||||
system.cpu.commit.refs 2050 # Number of memory references committed
|
||||
system.cpu.commit.loads 1185 # Number of loads committed
|
||||
system.cpu.commit.membars 0 # Number of memory barriers committed
|
||||
system.cpu.commit.branches 1051 # Number of branches committed
|
||||
system.cpu.commit.fp_insts 10 # Number of committed floating point instructions.
|
||||
system.cpu.commit.int_insts 6321 # Number of committed integer instructions.
|
||||
system.cpu.commit.function_calls 127 # Number of function calls committed.
|
||||
system.cpu.commit.bw_lim_events 151 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
||||
system.cpu.rob.rob_reads 24667 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 26868 # The number of ROB writes
|
||||
system.cpu.timesIdled 232 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 11397 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.committedInsts 6386 # Number of Instructions Simulated
|
||||
system.cpu.committedOps 6386 # Number of Ops (including micro ops) Simulated
|
||||
system.cpu.committedInsts_total 6386 # Number of Instructions Simulated
|
||||
system.cpu.cpi 3.899468 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 3.899468 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 0.256445 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.256445 # IPC: Total IPC of All Threads
|
||||
system.cpu.int_regfile_reads 12526 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 7116 # number of integer regfile writes
|
||||
system.cpu.fp_regfile_reads 8 # number of floating regfile reads
|
||||
system.cpu.fp_regfile_writes 2 # number of floating regfile writes
|
||||
system.cpu.misc_regfile_reads 1 # number of misc regfile reads
|
||||
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
|
||||
system.cpu.icache.replacements 0 # number of replacements
|
||||
system.cpu.icache.tagsinuse 162.256588 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 1909 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 315 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 6.060317 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 162.256588 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.079227 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.079227 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 1909 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 1909 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 1909 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 1909 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 1909 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 1909 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 458 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 458 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 458 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 458 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 458 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 458 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 16026500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 16026500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 16026500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 16026500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 16026500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 16026500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 2367 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 2367 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 2367 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 2367 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 2367 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 2367 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.193494 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.193494 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.193494 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.193494 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.193494 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.193494 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34992.358079 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 34992.358079 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 34992.358079 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 34992.358079 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 34992.358079 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 34992.358079 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 143 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::total 143 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::cpu.inst 143 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::total 143 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::cpu.inst 143 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::total 143 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 315 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 315 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 315 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 315 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 315 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 315 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11133500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 11133500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11133500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 11133500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11133500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 11133500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.133080 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.133080 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.133080 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.133080 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.133080 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.133080 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35344.444444 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35344.444444 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35344.444444 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 35344.444444 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35344.444444 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 35344.444444 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 109.847039 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 2244 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 175 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 12.822857 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 109.847039 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.026818 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.026818 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 1735 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 1735 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 509 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 509 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 2244 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 2244 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 2244 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 2244 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 144 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 144 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 356 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 356 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 500 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 500 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 500 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 500 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 5240000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 5240000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 12485500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 12485500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 17725500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 17725500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 17725500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 17725500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 1879 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 1879 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 2744 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 2744 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 2744 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 2744 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.076637 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.076637 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.411561 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.411561 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.182216 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.182216 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.182216 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.182216 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36388.888889 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 36388.888889 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35071.629213 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 35071.629213 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 35451 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 35451 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 35451 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 35451 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 40 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 40 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 284 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 284 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 324 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 324 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 324 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 324 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 104 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 104 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 72 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 72 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 176 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 176 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 176 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 176 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3722000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 3722000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2575500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 2575500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6297500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 6297500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6297500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 6297500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.055349 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.055349 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083237 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.083237 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.064140 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.064140 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.064140 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.064140 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35788.461538 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 35788.461538 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35770.833333 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35770.833333 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35781.250000 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 35781.250000 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 35781.250000 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 35781.250000 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 224.787735 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 418 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 0.002392 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 162.229240 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 62.558495 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.004951 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.001909 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.006860 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 1 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 314 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.data 104 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 418 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 72 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 72 # number of ReadExReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 314 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 176 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 490 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 314 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 176 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 490 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 10779500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3600000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 14379500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2488500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 2488500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 10779500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 6088500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 16868000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 10779500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 6088500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 16868000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 315 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 104 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 419 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 72 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 72 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 315 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 176 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 491 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 315 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 176 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 491 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996825 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.997613 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996825 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.997963 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996825 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.997963 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34329.617834 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34615.384615 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 34400.717703 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34562.500000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34562.500000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34329.617834 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34593.750000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 34424.489796 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34329.617834 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34593.750000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 34424.489796 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 314 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 104 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::total 418 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 72 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 72 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 314 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 176 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 490 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 314 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 176 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 490 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9770500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3273500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13044000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2264000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2264000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9770500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5537500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 15308000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9770500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5537500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 15308000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996825 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997613 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996825 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.997963 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996825 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.997963 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31116.242038 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31475.961538 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31205.741627 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31444.444444 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31444.444444 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31116.242038 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31463.068182 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31240.816327 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31116.242038 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31463.068182 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31240.816327 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
@ -0,0 +1,117 @@
|
||||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
full_system=false
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
||||
[system]
|
||||
type=System
|
||||
children=cpu membus physmem
|
||||
boot_osflags=a
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
mem_mode=atomic
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
readfile=
|
||||
symbolfile=
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.membus.slave[0]
|
||||
|
||||
[system.cpu]
|
||||
type=AtomicSimpleCPU
|
||||
children=dtb interrupts itb tracer workload
|
||||
checker=Null
|
||||
clock=500
|
||||
cpu_id=0
|
||||
defer_registration=false
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
fastmem=false
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
interrupts=system.cpu.interrupts
|
||||
itb=system.cpu.itb
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
phase=0
|
||||
profile=0
|
||||
progress_interval=0
|
||||
simulate_data_stalls=false
|
||||
simulate_inst_stalls=false
|
||||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
width=1
|
||||
workload=system.cpu.workload
|
||||
dcache_port=system.membus.slave[2]
|
||||
icache_port=system.membus.slave[1]
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=AlphaTLB
|
||||
size=64
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=AlphaInterrupts
|
||||
|
||||
[system.cpu.itb]
|
||||
type=AlphaTLB
|
||||
size=48
|
||||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
|
||||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=hello
|
||||
cwd=
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
ppid=99
|
||||
simpoint=0
|
||||
system=system
|
||||
uid=100
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
master=system.physmem.port[0]
|
||||
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.membus.master[0]
|
||||
|
||||
@ -0,0 +1,3 @@
|
||||
warn: CoherentBus system.membus has no snooping ports attached!
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
hack: be nice to actually delete the event here
|
||||
12
simulators/gem5/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simout
Executable file
12
simulators/gem5/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simout
Executable file
@ -0,0 +1,12 @@
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jun 4 2012 11:50:11
|
||||
gem5 started Jun 4 2012 13:46:44
|
||||
gem5 executing on zizzer
|
||||
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-atomic -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-atomic
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
Hello world!
|
||||
Exiting @ tick 3215000 because target called exit()
|
||||
@ -0,0 +1,92 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000003 # Number of seconds simulated
|
||||
sim_ticks 3215000 # Number of ticks simulated
|
||||
final_tick 3215000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1264163 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1259559 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 630191855 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 205200 # Number of bytes of host memory used
|
||||
host_seconds 0.01 # Real time elapsed on the host
|
||||
sim_insts 6404 # Number of instructions simulated
|
||||
sim_ops 6404 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 25656 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 8804 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 34460 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 25656 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 25656 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::cpu.data 6696 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 6696 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 6414 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 1185 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 7599 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::cpu.data 865 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 865 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 7980093313 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 2738413686 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 10718506998 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 7980093313 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 7980093313 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::cpu.data 2082737170 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 2082737170 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 7980093313 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 4821150855 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 12801244168 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
||||
system.cpu.dtb.read_hits 1185 # DTB read hits
|
||||
system.cpu.dtb.read_misses 7 # DTB read misses
|
||||
system.cpu.dtb.read_acv 0 # DTB read access violations
|
||||
system.cpu.dtb.read_accesses 1192 # DTB read accesses
|
||||
system.cpu.dtb.write_hits 865 # DTB write hits
|
||||
system.cpu.dtb.write_misses 3 # DTB write misses
|
||||
system.cpu.dtb.write_acv 0 # DTB write access violations
|
||||
system.cpu.dtb.write_accesses 868 # DTB write accesses
|
||||
system.cpu.dtb.data_hits 2050 # DTB hits
|
||||
system.cpu.dtb.data_misses 10 # DTB misses
|
||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
||||
system.cpu.dtb.data_accesses 2060 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 6414 # ITB hits
|
||||
system.cpu.itb.fetch_misses 17 # ITB misses
|
||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
||||
system.cpu.itb.fetch_accesses 6431 # ITB accesses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.itb.write_hits 0 # DTB write hits
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.itb.write_acv 0 # DTB write access violations
|
||||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.itb.data_hits 0 # DTB hits
|
||||
system.cpu.itb.data_misses 0 # DTB misses
|
||||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 17 # Number of system calls
|
||||
system.cpu.numCycles 6431 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 6404 # Number of instructions committed
|
||||
system.cpu.committedOps 6404 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 6331 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 251 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 750 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 6331 # number of integer instructions
|
||||
system.cpu.num_fp_insts 10 # number of float instructions
|
||||
system.cpu.num_int_register_reads 8304 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 4581 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 8 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 2 # number of times the floating registers were written
|
||||
system.cpu.num_mem_refs 2060 # number of memory refs
|
||||
system.cpu.num_load_insts 1192 # Number of load instructions
|
||||
system.cpu.num_store_insts 868 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 6431 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
@ -0,0 +1,343 @@
|
||||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
full_system=false
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000
|
||||
time_sync_spin_threshold=100000
|
||||
|
||||
[system]
|
||||
type=System
|
||||
children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby sys_port_proxy
|
||||
boot_osflags=a
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
mem_mode=timing
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
readfile=
|
||||
symbolfile=
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.sys_port_proxy.slave[0]
|
||||
|
||||
[system.cpu]
|
||||
type=TimingSimpleCPU
|
||||
children=dtb interrupts itb tracer workload
|
||||
checker=Null
|
||||
clock=1
|
||||
cpu_id=0
|
||||
defer_registration=false
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
interrupts=system.cpu.interrupts
|
||||
itb=system.cpu.itb
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
phase=0
|
||||
profile=0
|
||||
progress_interval=0
|
||||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
workload=system.cpu.workload
|
||||
dcache_port=system.l1_cntrl0.sequencer.slave[1]
|
||||
icache_port=system.l1_cntrl0.sequencer.slave[0]
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=AlphaTLB
|
||||
size=64
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=AlphaInterrupts
|
||||
|
||||
[system.cpu.itb]
|
||||
type=AlphaTLB
|
||||
size=48
|
||||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
|
||||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=hello
|
||||
cwd=
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
ppid=99
|
||||
simpoint=0
|
||||
system=system
|
||||
uid=100
|
||||
|
||||
[system.dir_cntrl0]
|
||||
type=Directory_Controller
|
||||
children=directory memBuffer
|
||||
buffer_size=0
|
||||
cntrl_id=2
|
||||
directory=system.dir_cntrl0.directory
|
||||
directory_latency=6
|
||||
memBuffer=system.dir_cntrl0.memBuffer
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
ruby_system=system.ruby
|
||||
to_mem_ctrl_latency=1
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.dir_cntrl0.directory]
|
||||
type=RubyDirectoryMemory
|
||||
map_levels=4
|
||||
numa_high_bit=6
|
||||
size=134217728
|
||||
use_map=false
|
||||
version=0
|
||||
|
||||
[system.dir_cntrl0.memBuffer]
|
||||
type=RubyMemoryControl
|
||||
bank_bit_0=8
|
||||
bank_busy_time=11
|
||||
bank_queue_size=12
|
||||
banks_per_rank=8
|
||||
basic_bus_busy_time=2
|
||||
dimm_bit_0=12
|
||||
dimms_per_channel=2
|
||||
mem_bus_cycle_multiplier=10
|
||||
mem_ctl_latency=12
|
||||
mem_fixed_delay=0
|
||||
mem_random_arbitrate=0
|
||||
rank_bit_0=11
|
||||
rank_rank_delay=1
|
||||
ranks_per_dimm=2
|
||||
read_write_delay=2
|
||||
refresh_period=1560
|
||||
tFaw=0
|
||||
version=0
|
||||
|
||||
[system.l1_cntrl0]
|
||||
type=L1Cache_Controller
|
||||
children=L1DcacheMemory L1IcacheMemory sequencer
|
||||
L1DcacheMemory=system.l1_cntrl0.L1DcacheMemory
|
||||
L1IcacheMemory=system.l1_cntrl0.L1IcacheMemory
|
||||
buffer_size=0
|
||||
cntrl_id=0
|
||||
l1_request_latency=2
|
||||
l1_response_latency=2
|
||||
l2_select_num_bits=0
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
ruby_system=system.ruby
|
||||
send_evictions=false
|
||||
sequencer=system.l1_cntrl0.sequencer
|
||||
to_l2_latency=1
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.l1_cntrl0.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
is_icache=false
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl0.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
is_icache=false
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl0.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=true
|
||||
dcache=system.l1_cntrl0.L1DcacheMemory
|
||||
deadlock_threshold=500000
|
||||
icache=system.l1_cntrl0.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
ruby_system=system.ruby
|
||||
support_data_reqs=true
|
||||
support_inst_reqs=true
|
||||
system=system
|
||||
using_network_tester=false
|
||||
using_ruby_tester=false
|
||||
version=0
|
||||
slave=system.cpu.icache_port system.cpu.dcache_port
|
||||
|
||||
[system.l2_cntrl0]
|
||||
type=L2Cache_Controller
|
||||
children=L2cacheMemory
|
||||
L2cacheMemory=system.l2_cntrl0.L2cacheMemory
|
||||
buffer_size=0
|
||||
cntrl_id=1
|
||||
l2_request_latency=2
|
||||
l2_response_latency=2
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
ruby_system=system.ruby
|
||||
to_l1_latency=1
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.l2_cntrl0.L2cacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
is_icache=false
|
||||
latency=15
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=512
|
||||
start_index_bit=6
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=30
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
|
||||
[system.ruby]
|
||||
type=RubySystem
|
||||
children=network profiler
|
||||
block_size_bytes=64
|
||||
clock=1
|
||||
mem_size=134217728
|
||||
no_mem_vec=false
|
||||
random_seed=1234
|
||||
randomization=false
|
||||
stats_filename=ruby.stats
|
||||
|
||||
[system.ruby.network]
|
||||
type=SimpleNetwork
|
||||
children=topology
|
||||
adaptive_routing=false
|
||||
buffer_size=0
|
||||
control_msg_size=8
|
||||
endpoint_bandwidth=1000
|
||||
number_of_virtual_networks=10
|
||||
ruby_system=system.ruby
|
||||
topology=system.ruby.network.topology
|
||||
|
||||
[system.ruby.network.topology]
|
||||
type=Topology
|
||||
children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2 routers0 routers1 routers2 routers3
|
||||
description=Crossbar
|
||||
ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2
|
||||
int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2
|
||||
print_config=false
|
||||
routers=system.ruby.network.topology.routers0 system.ruby.network.topology.routers1 system.ruby.network.topology.routers2 system.ruby.network.topology.routers3
|
||||
|
||||
[system.ruby.network.topology.ext_links0]
|
||||
type=SimpleExtLink
|
||||
bandwidth_factor=16
|
||||
ext_node=system.l1_cntrl0
|
||||
int_node=system.ruby.network.topology.routers0
|
||||
latency=1
|
||||
link_id=0
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links1]
|
||||
type=SimpleExtLink
|
||||
bandwidth_factor=16
|
||||
ext_node=system.l2_cntrl0
|
||||
int_node=system.ruby.network.topology.routers1
|
||||
latency=1
|
||||
link_id=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links2]
|
||||
type=SimpleExtLink
|
||||
bandwidth_factor=16
|
||||
ext_node=system.dir_cntrl0
|
||||
int_node=system.ruby.network.topology.routers2
|
||||
latency=1
|
||||
link_id=2
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.int_links0]
|
||||
type=SimpleIntLink
|
||||
bandwidth_factor=16
|
||||
latency=1
|
||||
link_id=3
|
||||
node_a=system.ruby.network.topology.routers0
|
||||
node_b=system.ruby.network.topology.routers3
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.int_links1]
|
||||
type=SimpleIntLink
|
||||
bandwidth_factor=16
|
||||
latency=1
|
||||
link_id=4
|
||||
node_a=system.ruby.network.topology.routers1
|
||||
node_b=system.ruby.network.topology.routers3
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.int_links2]
|
||||
type=SimpleIntLink
|
||||
bandwidth_factor=16
|
||||
latency=1
|
||||
link_id=5
|
||||
node_a=system.ruby.network.topology.routers2
|
||||
node_b=system.ruby.network.topology.routers3
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.routers0]
|
||||
type=BasicRouter
|
||||
router_id=0
|
||||
|
||||
[system.ruby.network.topology.routers1]
|
||||
type=BasicRouter
|
||||
router_id=1
|
||||
|
||||
[system.ruby.network.topology.routers2]
|
||||
type=BasicRouter
|
||||
router_id=2
|
||||
|
||||
[system.ruby.network.topology.routers3]
|
||||
type=BasicRouter
|
||||
router_id=3
|
||||
|
||||
[system.ruby.profiler]
|
||||
type=RubyProfiler
|
||||
all_instructions=false
|
||||
hot_lines=false
|
||||
num_of_sequencers=1
|
||||
ruby_system=system.ruby
|
||||
|
||||
[system.sys_port_proxy]
|
||||
type=RubyPortProxy
|
||||
access_phys_mem=true
|
||||
ruby_system=system.ruby
|
||||
support_data_reqs=true
|
||||
support_inst_reqs=true
|
||||
system=system
|
||||
using_network_tester=false
|
||||
using_ruby_tester=false
|
||||
version=0
|
||||
slave=system.system_port
|
||||
|
||||
@ -0,0 +1,636 @@
|
||||
|
||||
================ Begin RubySystem Configuration Print ================
|
||||
|
||||
RubySystem config:
|
||||
random_seed: 1234
|
||||
randomization: 0
|
||||
cycle_period: 1
|
||||
block_size_bytes: 64
|
||||
block_size_bits: 6
|
||||
memory_size_bytes: 134217728
|
||||
memory_size_bits: 27
|
||||
|
||||
Network Configuration
|
||||
---------------------
|
||||
network: SIMPLE_NETWORK
|
||||
topology:
|
||||
|
||||
virtual_net_0: active, unordered
|
||||
virtual_net_1: active, unordered
|
||||
virtual_net_2: active, unordered
|
||||
virtual_net_3: inactive
|
||||
virtual_net_4: inactive
|
||||
virtual_net_5: inactive
|
||||
virtual_net_6: inactive
|
||||
virtual_net_7: inactive
|
||||
virtual_net_8: inactive
|
||||
virtual_net_9: inactive
|
||||
|
||||
|
||||
Profiler Configuration
|
||||
----------------------
|
||||
periodic_stats_period: 1000000
|
||||
|
||||
================ End RubySystem Configuration Print ================
|
||||
|
||||
|
||||
Real time: Jun/04/2012 13:42:36
|
||||
|
||||
Profiler Stats
|
||||
--------------
|
||||
Elapsed_time_in_seconds: 1
|
||||
Elapsed_time_in_minutes: 0.0166667
|
||||
Elapsed_time_in_hours: 0.000277778
|
||||
Elapsed_time_in_days: 1.15741e-05
|
||||
|
||||
Virtual_time_in_seconds: 0.43
|
||||
Virtual_time_in_minutes: 0.00716667
|
||||
Virtual_time_in_hours: 0.000119444
|
||||
Virtual_time_in_days: 4.97685e-06
|
||||
|
||||
Ruby_current_time: 279353
|
||||
Ruby_start_time: 0
|
||||
Ruby_cycles: 279353
|
||||
|
||||
mbytes_resident: 49.4727
|
||||
mbytes_total: 221.031
|
||||
resident_ratio: 0.223827
|
||||
|
||||
ruby_cycles_executed: [ 279354 ]
|
||||
|
||||
Busy Controller Counts:
|
||||
L1Cache-0:0
|
||||
L2Cache-0:0
|
||||
Directory-0:0
|
||||
|
||||
|
||||
Busy Bank Count:0
|
||||
|
||||
sequencer_requests_outstanding: [binsize: 1 max: 1 count: 8465 average: 1 | standard deviation: 0 | 0 8465 ]
|
||||
|
||||
All Non-Zero Cycle Demand Cache Accesses
|
||||
----------------------------------------
|
||||
miss_latency: [binsize: 2 max: 297 count: 8464 average: 32.0048 | standard deviation: 63.6079 | 0 6974 0 0 0 0 0 0 0 29 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 118 380 227 310 190 17 40 4 7 11 8 23 23 28 22 21 12 0 0 0 2 2 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 3 3 0 0 1 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_LD: [binsize: 2 max: 287 count: 1185 average: 83.8878 | standard deviation: 84.2176 | 0 602 0 0 0 0 0 0 0 12 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 54 155 70 110 81 8 29 3 2 5 2 9 4 12 7 5 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 3 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_ST: [binsize: 2 max: 297 count: 865 average: 43.8439 | standard deviation: 73.6087 | 0 649 0 0 0 0 0 0 0 12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 35 63 19 18 8 4 0 0 1 1 3 15 1 3 16 4 0 0 0 2 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_IFETCH: [binsize: 2 max: 295 count: 6414 average: 20.8227 | standard deviation: 51.5606 | 0 5723 0 0 0 0 0 0 0 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 58 190 94 181 91 1 7 1 5 5 5 11 4 15 12 0 0 0 0 0 0 2 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_NULL: [binsize: 2 max: 297 count: 8464 average: 32.0048 | standard deviation: 63.6079 | 0 6974 0 0 0 0 0 0 0 29 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 118 380 227 310 190 17 40 4 7 11 8 23 23 28 22 21 12 0 0 0 2 2 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 3 3 0 0 1 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
imcomplete_wCC_Times: 0
|
||||
miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
imcomplete_dir_Times: 0
|
||||
miss_latency_LD_NULL: [binsize: 2 max: 287 count: 1185 average: 83.8878 | standard deviation: 84.2176 | 0 602 0 0 0 0 0 0 0 12 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 54 155 70 110 81 8 29 3 2 5 2 9 4 12 7 5 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 3 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_ST_NULL: [binsize: 2 max: 297 count: 865 average: 43.8439 | standard deviation: 73.6087 | 0 649 0 0 0 0 0 0 0 12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 35 63 19 18 8 4 0 0 1 1 3 15 1 3 16 4 0 0 0 2 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_IFETCH_NULL: [binsize: 2 max: 295 count: 6414 average: 20.8227 | standard deviation: 51.5606 | 0 5723 0 0 0 0 0 0 0 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 58 190 94 181 91 1 7 1 5 5 5 11 4 15 12 0 0 0 0 0 0 2 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
|
||||
All Non-Zero Cycle SW Prefetch Requests
|
||||
------------------------------------
|
||||
prefetch_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
prefetch_latency_L2Miss:[binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
Request vs. RubySystem State Profile
|
||||
--------------------------------
|
||||
|
||||
|
||||
filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
||||
Message Delayed Cycles
|
||||
----------------------
|
||||
Total_delay_cycles: [binsize: 1 max: 18 count: 9645 average: 0.0636599 | standard deviation: 0.52686 | 9495 0 1 0 147 0 1 0 0 0 0 0 0 0 0 0 0 0 1 ]
|
||||
Total_nonPF_delay_cycles: [binsize: 1 max: 2 count: 6920 average: 0.000289017 | standard deviation: 0.0240441 | 6919 0 1 ]
|
||||
virtual_network_0_delay_cycles: [binsize: 1 max: 18 count: 2725 average: 0.224587 | standard deviation: 0.972266 | 2576 0 0 0 147 0 1 0 0 0 0 0 0 0 0 0 0 0 1 ]
|
||||
virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 1041 average: 0 | standard deviation: 0 | 1041 ]
|
||||
virtual_network_3_delay_cycles: [binsize: 1 max: 2 count: 5879 average: 0.000340194 | standard deviation: 0.0260865 | 5878 0 1 ]
|
||||
virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_6_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_7_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_8_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_9_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
||||
Resource Usage
|
||||
--------------
|
||||
page_size: 4096
|
||||
user_time: 0
|
||||
system_time: 0
|
||||
page_reclaims: 13079
|
||||
page_faults: 9
|
||||
swaps: 0
|
||||
block_inputs: 1264
|
||||
block_outputs: 96
|
||||
|
||||
Network Stats
|
||||
-------------
|
||||
|
||||
total_msg_count_Control: 8850 70800
|
||||
total_msg_count_Request_Control: 3123 24984
|
||||
total_msg_count_Response_Data: 9681 697032
|
||||
total_msg_count_Response_Control: 14286 114288
|
||||
total_msg_count_Writeback_Data: 864 62208
|
||||
total_msg_count_Writeback_Control: 867 6936
|
||||
total_msgs: 37671 total_bytes: 976248
|
||||
|
||||
switch_0_inlinks: 2
|
||||
switch_0_outlinks: 2
|
||||
links_utilized_percent_switch_0: 1.87549
|
||||
links_utilized_percent_switch_0_link_0: 2.66455 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_0_link_1: 1.08644 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_0_link_0_Request_Control: 1041 8328 [ 1041 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Response_Data: 1490 107280 [ 0 1490 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Response_Control: 436 3488 [ 0 436 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Control: 1490 11920 [ 1490 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Response_Control: 1699 13592 [ 0 900 799 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Writeback_Data: 288 20736 [ 147 141 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Writeback_Control: 289 2312 [ 289 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_1_inlinks: 2
|
||||
switch_1_outlinks: 2
|
||||
links_utilized_percent_switch_1: 3.64029
|
||||
links_utilized_percent_switch_1_link_0: 3.69819 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_1_link_1: 3.58239 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_1_link_0_Control: 1490 11920 [ 1490 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Response_Data: 1460 105120 [ 0 1460 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Response_Control: 3151 25208 [ 0 2352 799 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Writeback_Data: 288 20736 [ 147 141 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Writeback_Control: 289 2312 [ 289 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Control: 1460 11680 [ 1460 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Request_Control: 1041 8328 [ 1041 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Response_Data: 1767 127224 [ 0 1767 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Response_Control: 1611 12888 [ 0 1611 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_2_inlinks: 2
|
||||
switch_2_outlinks: 2
|
||||
links_utilized_percent_switch_2: 1.76479
|
||||
links_utilized_percent_switch_2_link_0: 0.917835 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_2_link_1: 2.61175 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_2_link_0_Control: 1460 11680 [ 1460 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Response_Data: 277 19944 [ 0 277 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Response_Control: 1175 9400 [ 0 1175 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Response_Data: 1460 105120 [ 0 1460 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Response_Control: 1452 11616 [ 0 1452 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_3_inlinks: 3
|
||||
switch_3_outlinks: 3
|
||||
links_utilized_percent_switch_3: 2.42686
|
||||
links_utilized_percent_switch_3_link_0: 2.66455 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_3_link_1: 3.69819 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_3_link_2: 0.917835 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_3_link_0_Request_Control: 1041 8328 [ 1041 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_Response_Data: 1490 107280 [ 0 1490 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_Response_Control: 436 3488 [ 0 436 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Control: 1490 11920 [ 1490 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Response_Data: 1460 105120 [ 0 1460 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Response_Control: 3151 25208 [ 0 2352 799 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Writeback_Data: 288 20736 [ 147 141 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Writeback_Control: 289 2312 [ 289 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_2_Control: 1460 11680 [ 1460 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_2_Response_Data: 277 19944 [ 0 277 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_2_Response_Control: 1175 9400 [ 0 1175 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
Cache Stats: system.l1_cntrl0.L1IcacheMemory
|
||||
system.l1_cntrl0.L1IcacheMemory_total_misses: 691
|
||||
system.l1_cntrl0.L1IcacheMemory_total_demand_misses: 691
|
||||
system.l1_cntrl0.L1IcacheMemory_total_prefetches: 0
|
||||
system.l1_cntrl0.L1IcacheMemory_total_sw_prefetches: 0
|
||||
system.l1_cntrl0.L1IcacheMemory_total_hw_prefetches: 0
|
||||
|
||||
system.l1_cntrl0.L1IcacheMemory_request_type_IFETCH: 100%
|
||||
|
||||
system.l1_cntrl0.L1IcacheMemory_access_mode_type_Supervisor: 691 100%
|
||||
|
||||
Cache Stats: system.l1_cntrl0.L1DcacheMemory
|
||||
system.l1_cntrl0.L1DcacheMemory_total_misses: 799
|
||||
system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 799
|
||||
system.l1_cntrl0.L1DcacheMemory_total_prefetches: 0
|
||||
system.l1_cntrl0.L1DcacheMemory_total_sw_prefetches: 0
|
||||
system.l1_cntrl0.L1DcacheMemory_total_hw_prefetches: 0
|
||||
|
||||
system.l1_cntrl0.L1DcacheMemory_request_type_LD: 72.9662%
|
||||
system.l1_cntrl0.L1DcacheMemory_request_type_ST: 27.0338%
|
||||
|
||||
system.l1_cntrl0.L1DcacheMemory_access_mode_type_Supervisor: 799 100%
|
||||
|
||||
--- L1Cache ---
|
||||
- Event Counts -
|
||||
Load [1185 ] 1185
|
||||
Ifetch [6414 ] 6414
|
||||
Store [865 ] 865
|
||||
Inv [1041 ] 1041
|
||||
L1_Replacement [1354 ] 1354
|
||||
Fwd_GETX [0 ] 0
|
||||
Fwd_GETS [0 ] 0
|
||||
Fwd_GET_INSTR [0 ] 0
|
||||
Data [0 ] 0
|
||||
Data_Exclusive [583 ] 583
|
||||
DataS_fromL1 [0 ] 0
|
||||
Data_all_Acks [907 ] 907
|
||||
Ack [0 ] 0
|
||||
Ack_all [0 ] 0
|
||||
WB_Ack [436 ] 436
|
||||
|
||||
- Transitions -
|
||||
NP Load [525 ] 525
|
||||
NP Ifetch [646 ] 646
|
||||
NP Store [191 ] 191
|
||||
NP Inv [356 ] 356
|
||||
NP L1_Replacement [0 ] 0
|
||||
|
||||
I Load [58 ] 58
|
||||
I Ifetch [45 ] 45
|
||||
I Store [25 ] 25
|
||||
I Inv [0 ] 0
|
||||
I L1_Replacement [556 ] 556
|
||||
|
||||
S Load [0 ] 0
|
||||
S Ifetch [5723 ] 5723
|
||||
S Store [0 ] 0
|
||||
S Inv [325 ] 325
|
||||
S L1_Replacement [362 ] 362
|
||||
|
||||
E Load [454 ] 454
|
||||
E Ifetch [0 ] 0
|
||||
E Store [71 ] 71
|
||||
E Inv [219 ] 219
|
||||
E L1_Replacement [291 ] 291
|
||||
E Fwd_GETX [0 ] 0
|
||||
E Fwd_GETS [0 ] 0
|
||||
E Fwd_GET_INSTR [0 ] 0
|
||||
|
||||
M Load [148 ] 148
|
||||
M Ifetch [0 ] 0
|
||||
M Store [578 ] 578
|
||||
M Inv [141 ] 141
|
||||
M L1_Replacement [145 ] 145
|
||||
M Fwd_GETX [0 ] 0
|
||||
M Fwd_GETS [0 ] 0
|
||||
M Fwd_GET_INSTR [0 ] 0
|
||||
|
||||
IS Load [0 ] 0
|
||||
IS Ifetch [0 ] 0
|
||||
IS Store [0 ] 0
|
||||
IS Inv [0 ] 0
|
||||
IS L1_Replacement [0 ] 0
|
||||
IS Data_Exclusive [583 ] 583
|
||||
IS DataS_fromL1 [0 ] 0
|
||||
IS Data_all_Acks [691 ] 691
|
||||
|
||||
IM Load [0 ] 0
|
||||
IM Ifetch [0 ] 0
|
||||
IM Store [0 ] 0
|
||||
IM Inv [0 ] 0
|
||||
IM L1_Replacement [0 ] 0
|
||||
IM Data [0 ] 0
|
||||
IM Data_all_Acks [216 ] 216
|
||||
IM Ack [0 ] 0
|
||||
|
||||
SM Load [0 ] 0
|
||||
SM Ifetch [0 ] 0
|
||||
SM Store [0 ] 0
|
||||
SM Inv [0 ] 0
|
||||
SM L1_Replacement [0 ] 0
|
||||
SM Ack [0 ] 0
|
||||
SM Ack_all [0 ] 0
|
||||
|
||||
IS_I Load [0 ] 0
|
||||
IS_I Ifetch [0 ] 0
|
||||
IS_I Store [0 ] 0
|
||||
IS_I Inv [0 ] 0
|
||||
IS_I L1_Replacement [0 ] 0
|
||||
IS_I Data_Exclusive [0 ] 0
|
||||
IS_I DataS_fromL1 [0 ] 0
|
||||
IS_I Data_all_Acks [0 ] 0
|
||||
|
||||
M_I Load [0 ] 0
|
||||
M_I Ifetch [0 ] 0
|
||||
M_I Store [0 ] 0
|
||||
M_I Inv [0 ] 0
|
||||
M_I L1_Replacement [0 ] 0
|
||||
M_I Fwd_GETX [0 ] 0
|
||||
M_I Fwd_GETS [0 ] 0
|
||||
M_I Fwd_GET_INSTR [0 ] 0
|
||||
M_I WB_Ack [436 ] 436
|
||||
|
||||
SINK_WB_ACK Load [0 ] 0
|
||||
SINK_WB_ACK Ifetch [0 ] 0
|
||||
SINK_WB_ACK Store [0 ] 0
|
||||
SINK_WB_ACK Inv [0 ] 0
|
||||
SINK_WB_ACK L1_Replacement [0 ] 0
|
||||
SINK_WB_ACK WB_Ack [0 ] 0
|
||||
|
||||
Cache Stats: system.l2_cntrl0.L2cacheMemory
|
||||
system.l2_cntrl0.L2cacheMemory_total_misses: 1460
|
||||
system.l2_cntrl0.L2cacheMemory_total_demand_misses: 1460
|
||||
system.l2_cntrl0.L2cacheMemory_total_prefetches: 0
|
||||
system.l2_cntrl0.L2cacheMemory_total_sw_prefetches: 0
|
||||
system.l2_cntrl0.L2cacheMemory_total_hw_prefetches: 0
|
||||
|
||||
system.l2_cntrl0.L2cacheMemory_request_type_GETS: 39.0411%
|
||||
system.l2_cntrl0.L2cacheMemory_request_type_GET_INSTR: 46.9863%
|
||||
system.l2_cntrl0.L2cacheMemory_request_type_GETX: 13.9726%
|
||||
|
||||
system.l2_cntrl0.L2cacheMemory_access_mode_type_Supervisor: 1460 100%
|
||||
|
||||
--- L2Cache ---
|
||||
- Event Counts -
|
||||
L1_GET_INSTR [691 ] 691
|
||||
L1_GETS [585 ] 585
|
||||
L1_GETX [216 ] 216
|
||||
L1_UPGRADE [0 ] 0
|
||||
L1_PUTX [436 ] 436
|
||||
L1_PUTX_old [0 ] 0
|
||||
Fwd_L1_GETX [0 ] 0
|
||||
Fwd_L1_GETS [0 ] 0
|
||||
Fwd_L1_GET_INSTR [0 ] 0
|
||||
L2_Replacement [142 ] 142
|
||||
L2_Replacement_clean [1310 ] 1310
|
||||
Mem_Data [1460 ] 1460
|
||||
Mem_Ack [1452 ] 1452
|
||||
WB_Data [141 ] 141
|
||||
WB_Data_clean [0 ] 0
|
||||
Ack [0 ] 0
|
||||
Ack_all [900 ] 900
|
||||
Unblock [0 ] 0
|
||||
Unblock_Cancel [0 ] 0
|
||||
Exclusive_Unblock [799 ] 799
|
||||
MEM_Inv [0 ] 0
|
||||
|
||||
- Transitions -
|
||||
NP L1_GET_INSTR [686 ] 686
|
||||
NP L1_GETS [570 ] 570
|
||||
NP L1_GETX [204 ] 204
|
||||
NP L1_PUTX [0 ] 0
|
||||
NP L1_PUTX_old [0 ] 0
|
||||
|
||||
SS L1_GET_INSTR [5 ] 5
|
||||
SS L1_GETS [0 ] 0
|
||||
SS L1_GETX [0 ] 0
|
||||
SS L1_UPGRADE [0 ] 0
|
||||
SS L1_PUTX [0 ] 0
|
||||
SS L1_PUTX_old [0 ] 0
|
||||
SS L2_Replacement [0 ] 0
|
||||
SS L2_Replacement_clean [681 ] 681
|
||||
SS MEM_Inv [0 ] 0
|
||||
|
||||
M L1_GET_INSTR [0 ] 0
|
||||
M L1_GETS [13 ] 13
|
||||
M L1_GETX [12 ] 12
|
||||
M L1_PUTX [0 ] 0
|
||||
M L1_PUTX_old [0 ] 0
|
||||
M L2_Replacement [134 ] 134
|
||||
M L2_Replacement_clean [277 ] 277
|
||||
M MEM_Inv [0 ] 0
|
||||
|
||||
MT L1_GET_INSTR [0 ] 0
|
||||
MT L1_GETS [0 ] 0
|
||||
MT L1_GETX [0 ] 0
|
||||
MT L1_PUTX [436 ] 436
|
||||
MT L1_PUTX_old [0 ] 0
|
||||
MT L2_Replacement [8 ] 8
|
||||
MT L2_Replacement_clean [352 ] 352
|
||||
MT MEM_Inv [0 ] 0
|
||||
|
||||
M_I L1_GET_INSTR [0 ] 0
|
||||
M_I L1_GETS [2 ] 2
|
||||
M_I L1_GETX [0 ] 0
|
||||
M_I L1_UPGRADE [0 ] 0
|
||||
M_I L1_PUTX [0 ] 0
|
||||
M_I L1_PUTX_old [0 ] 0
|
||||
M_I Mem_Ack [1452 ] 1452
|
||||
M_I MEM_Inv [0 ] 0
|
||||
|
||||
MT_I L1_GET_INSTR [0 ] 0
|
||||
MT_I L1_GETS [0 ] 0
|
||||
MT_I L1_GETX [0 ] 0
|
||||
MT_I L1_UPGRADE [0 ] 0
|
||||
MT_I L1_PUTX [0 ] 0
|
||||
MT_I L1_PUTX_old [0 ] 0
|
||||
MT_I WB_Data [6 ] 6
|
||||
MT_I WB_Data_clean [0 ] 0
|
||||
MT_I Ack_all [2 ] 2
|
||||
MT_I MEM_Inv [0 ] 0
|
||||
|
||||
MCT_I L1_GET_INSTR [0 ] 0
|
||||
MCT_I L1_GETS [0 ] 0
|
||||
MCT_I L1_GETX [0 ] 0
|
||||
MCT_I L1_UPGRADE [0 ] 0
|
||||
MCT_I L1_PUTX [0 ] 0
|
||||
MCT_I L1_PUTX_old [0 ] 0
|
||||
MCT_I WB_Data [135 ] 135
|
||||
MCT_I WB_Data_clean [0 ] 0
|
||||
MCT_I Ack_all [217 ] 217
|
||||
|
||||
I_I L1_GET_INSTR [0 ] 0
|
||||
I_I L1_GETS [0 ] 0
|
||||
I_I L1_GETX [0 ] 0
|
||||
I_I L1_UPGRADE [0 ] 0
|
||||
I_I L1_PUTX [0 ] 0
|
||||
I_I L1_PUTX_old [0 ] 0
|
||||
I_I Ack [0 ] 0
|
||||
I_I Ack_all [681 ] 681
|
||||
|
||||
S_I L1_GET_INSTR [0 ] 0
|
||||
S_I L1_GETS [0 ] 0
|
||||
S_I L1_GETX [0 ] 0
|
||||
S_I L1_UPGRADE [0 ] 0
|
||||
S_I L1_PUTX [0 ] 0
|
||||
S_I L1_PUTX_old [0 ] 0
|
||||
S_I Ack [0 ] 0
|
||||
S_I Ack_all [0 ] 0
|
||||
S_I MEM_Inv [0 ] 0
|
||||
|
||||
ISS L1_GET_INSTR [0 ] 0
|
||||
ISS L1_GETS [0 ] 0
|
||||
ISS L1_GETX [0 ] 0
|
||||
ISS L1_PUTX [0 ] 0
|
||||
ISS L1_PUTX_old [0 ] 0
|
||||
ISS L2_Replacement [0 ] 0
|
||||
ISS L2_Replacement_clean [0 ] 0
|
||||
ISS Mem_Data [570 ] 570
|
||||
ISS MEM_Inv [0 ] 0
|
||||
|
||||
IS L1_GET_INSTR [0 ] 0
|
||||
IS L1_GETS [0 ] 0
|
||||
IS L1_GETX [0 ] 0
|
||||
IS L1_PUTX [0 ] 0
|
||||
IS L1_PUTX_old [0 ] 0
|
||||
IS L2_Replacement [0 ] 0
|
||||
IS L2_Replacement_clean [0 ] 0
|
||||
IS Mem_Data [686 ] 686
|
||||
IS MEM_Inv [0 ] 0
|
||||
|
||||
IM L1_GET_INSTR [0 ] 0
|
||||
IM L1_GETS [0 ] 0
|
||||
IM L1_GETX [0 ] 0
|
||||
IM L1_PUTX [0 ] 0
|
||||
IM L1_PUTX_old [0 ] 0
|
||||
IM L2_Replacement [0 ] 0
|
||||
IM L2_Replacement_clean [0 ] 0
|
||||
IM Mem_Data [204 ] 204
|
||||
IM MEM_Inv [0 ] 0
|
||||
|
||||
SS_MB L1_GET_INSTR [0 ] 0
|
||||
SS_MB L1_GETS [0 ] 0
|
||||
SS_MB L1_GETX [0 ] 0
|
||||
SS_MB L1_UPGRADE [0 ] 0
|
||||
SS_MB L1_PUTX [0 ] 0
|
||||
SS_MB L1_PUTX_old [0 ] 0
|
||||
SS_MB L2_Replacement [0 ] 0
|
||||
SS_MB L2_Replacement_clean [0 ] 0
|
||||
SS_MB Unblock_Cancel [0 ] 0
|
||||
SS_MB Exclusive_Unblock [0 ] 0
|
||||
SS_MB MEM_Inv [0 ] 0
|
||||
|
||||
MT_MB L1_GET_INSTR [0 ] 0
|
||||
MT_MB L1_GETS [0 ] 0
|
||||
MT_MB L1_GETX [0 ] 0
|
||||
MT_MB L1_UPGRADE [0 ] 0
|
||||
MT_MB L1_PUTX [0 ] 0
|
||||
MT_MB L1_PUTX_old [0 ] 0
|
||||
MT_MB L2_Replacement [0 ] 0
|
||||
MT_MB L2_Replacement_clean [0 ] 0
|
||||
MT_MB Unblock_Cancel [0 ] 0
|
||||
MT_MB Exclusive_Unblock [799 ] 799
|
||||
MT_MB MEM_Inv [0 ] 0
|
||||
|
||||
M_MB L1_GET_INSTR [0 ] 0
|
||||
M_MB L1_GETS [0 ] 0
|
||||
M_MB L1_GETX [0 ] 0
|
||||
M_MB L1_UPGRADE [0 ] 0
|
||||
M_MB L1_PUTX [0 ] 0
|
||||
M_MB L1_PUTX_old [0 ] 0
|
||||
M_MB L2_Replacement [0 ] 0
|
||||
M_MB L2_Replacement_clean [0 ] 0
|
||||
M_MB Exclusive_Unblock [0 ] 0
|
||||
M_MB MEM_Inv [0 ] 0
|
||||
|
||||
MT_IIB L1_GET_INSTR [0 ] 0
|
||||
MT_IIB L1_GETS [0 ] 0
|
||||
MT_IIB L1_GETX [0 ] 0
|
||||
MT_IIB L1_UPGRADE [0 ] 0
|
||||
MT_IIB L1_PUTX [0 ] 0
|
||||
MT_IIB L1_PUTX_old [0 ] 0
|
||||
MT_IIB L2_Replacement [0 ] 0
|
||||
MT_IIB L2_Replacement_clean [0 ] 0
|
||||
MT_IIB WB_Data [0 ] 0
|
||||
MT_IIB WB_Data_clean [0 ] 0
|
||||
MT_IIB Unblock [0 ] 0
|
||||
MT_IIB MEM_Inv [0 ] 0
|
||||
|
||||
MT_IB L1_GET_INSTR [0 ] 0
|
||||
MT_IB L1_GETS [0 ] 0
|
||||
MT_IB L1_GETX [0 ] 0
|
||||
MT_IB L1_UPGRADE [0 ] 0
|
||||
MT_IB L1_PUTX [0 ] 0
|
||||
MT_IB L1_PUTX_old [0 ] 0
|
||||
MT_IB L2_Replacement [0 ] 0
|
||||
MT_IB L2_Replacement_clean [0 ] 0
|
||||
MT_IB WB_Data [0 ] 0
|
||||
MT_IB WB_Data_clean [0 ] 0
|
||||
MT_IB Unblock_Cancel [0 ] 0
|
||||
MT_IB MEM_Inv [0 ] 0
|
||||
|
||||
MT_SB L1_GET_INSTR [0 ] 0
|
||||
MT_SB L1_GETS [0 ] 0
|
||||
MT_SB L1_GETX [0 ] 0
|
||||
MT_SB L1_UPGRADE [0 ] 0
|
||||
MT_SB L1_PUTX [0 ] 0
|
||||
MT_SB L1_PUTX_old [0 ] 0
|
||||
MT_SB L2_Replacement [0 ] 0
|
||||
MT_SB L2_Replacement_clean [0 ] 0
|
||||
MT_SB Unblock [0 ] 0
|
||||
MT_SB MEM_Inv [0 ] 0
|
||||
|
||||
Memory controller: system.dir_cntrl0.memBuffer:
|
||||
memory_total_requests: 1737
|
||||
memory_reads: 1460
|
||||
memory_writes: 277
|
||||
memory_refreshes: 582
|
||||
memory_total_request_delays: 821
|
||||
memory_delays_per_request: 0.472654
|
||||
memory_delays_in_input_queue: 84
|
||||
memory_delays_behind_head_of_bank_queue: 0
|
||||
memory_delays_stalled_at_head_of_bank_queue: 737
|
||||
memory_stalls_for_bank_busy: 197
|
||||
memory_stalls_for_random_busy: 0
|
||||
memory_stalls_for_anti_starvation: 0
|
||||
memory_stalls_for_arbitration: 40
|
||||
memory_stalls_for_bus: 242
|
||||
memory_stalls_for_tfaw: 0
|
||||
memory_stalls_for_read_write_turnaround: 258
|
||||
memory_stalls_for_read_read_turnaround: 0
|
||||
accesses_per_bank: 92 21 45 54 57 174 48 18 19 22 35 37 56 59 44 36 41 24 22 28 32 48 122 36 32 25 35 96 114 185 19 61
|
||||
|
||||
--- Directory ---
|
||||
- Event Counts -
|
||||
Fetch [1460 ] 1460
|
||||
Data [277 ] 277
|
||||
Memory_Data [1460 ] 1460
|
||||
Memory_Ack [277 ] 277
|
||||
DMA_READ [0 ] 0
|
||||
DMA_WRITE [0 ] 0
|
||||
CleanReplacement [1175 ] 1175
|
||||
|
||||
- Transitions -
|
||||
I Fetch [1460 ] 1460
|
||||
I DMA_READ [0 ] 0
|
||||
I DMA_WRITE [0 ] 0
|
||||
|
||||
ID Fetch [0 ] 0
|
||||
ID Data [0 ] 0
|
||||
ID Memory_Data [0 ] 0
|
||||
ID DMA_READ [0 ] 0
|
||||
ID DMA_WRITE [0 ] 0
|
||||
|
||||
ID_W Fetch [0 ] 0
|
||||
ID_W Data [0 ] 0
|
||||
ID_W Memory_Ack [0 ] 0
|
||||
ID_W DMA_READ [0 ] 0
|
||||
ID_W DMA_WRITE [0 ] 0
|
||||
|
||||
M Data [277 ] 277
|
||||
M DMA_READ [0 ] 0
|
||||
M DMA_WRITE [0 ] 0
|
||||
M CleanReplacement [1175 ] 1175
|
||||
|
||||
IM Fetch [0 ] 0
|
||||
IM Data [0 ] 0
|
||||
IM Memory_Data [1460 ] 1460
|
||||
IM DMA_READ [0 ] 0
|
||||
IM DMA_WRITE [0 ] 0
|
||||
|
||||
MI Fetch [0 ] 0
|
||||
MI Data [0 ] 0
|
||||
MI Memory_Ack [277 ] 277
|
||||
MI DMA_READ [0 ] 0
|
||||
MI DMA_WRITE [0 ] 0
|
||||
|
||||
M_DRD Data [0 ] 0
|
||||
M_DRD DMA_READ [0 ] 0
|
||||
M_DRD DMA_WRITE [0 ] 0
|
||||
|
||||
M_DRDI Fetch [0 ] 0
|
||||
M_DRDI Data [0 ] 0
|
||||
M_DRDI Memory_Ack [0 ] 0
|
||||
M_DRDI DMA_READ [0 ] 0
|
||||
M_DRDI DMA_WRITE [0 ] 0
|
||||
|
||||
M_DWR Data [0 ] 0
|
||||
M_DWR DMA_READ [0 ] 0
|
||||
M_DWR DMA_WRITE [0 ] 0
|
||||
|
||||
M_DWRI Fetch [0 ] 0
|
||||
M_DWRI Data [0 ] 0
|
||||
M_DWRI Memory_Ack [0 ] 0
|
||||
M_DWRI DMA_READ [0 ] 0
|
||||
M_DWRI DMA_WRITE [0 ] 0
|
||||
|
||||
@ -0,0 +1,2 @@
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
hack: be nice to actually delete the event here
|
||||
@ -0,0 +1,12 @@
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jun 4 2012 11:53:20
|
||||
gem5 started Jun 4 2012 13:42:35
|
||||
gem5 executing on zizzer
|
||||
command line: build/ALPHA_MESI_CMP_directory/gem5.opt -d build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MESI_CMP_directory
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
Hello world!
|
||||
Exiting @ tick 279353 because target called exit()
|
||||
@ -0,0 +1,92 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000279 # Number of seconds simulated
|
||||
sim_ticks 279353 # Number of ticks simulated
|
||||
final_tick 279353 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 12119 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 12118 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 528605 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 226340 # Number of bytes of host memory used
|
||||
host_seconds 0.53 # Real time elapsed on the host
|
||||
sim_insts 6404 # Number of instructions simulated
|
||||
sim_ops 6404 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 25656 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 8804 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 34460 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 25656 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 25656 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::cpu.data 6696 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 6696 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 6414 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 1185 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 7599 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::cpu.data 865 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 865 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 91840789 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 31515681 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 123356470 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 91840789 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 91840789 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::cpu.data 23969673 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 23969673 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 91840789 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 55485354 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 147326143 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
||||
system.cpu.dtb.read_hits 1185 # DTB read hits
|
||||
system.cpu.dtb.read_misses 7 # DTB read misses
|
||||
system.cpu.dtb.read_acv 0 # DTB read access violations
|
||||
system.cpu.dtb.read_accesses 1192 # DTB read accesses
|
||||
system.cpu.dtb.write_hits 865 # DTB write hits
|
||||
system.cpu.dtb.write_misses 3 # DTB write misses
|
||||
system.cpu.dtb.write_acv 0 # DTB write access violations
|
||||
system.cpu.dtb.write_accesses 868 # DTB write accesses
|
||||
system.cpu.dtb.data_hits 2050 # DTB hits
|
||||
system.cpu.dtb.data_misses 10 # DTB misses
|
||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
||||
system.cpu.dtb.data_accesses 2060 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 6415 # ITB hits
|
||||
system.cpu.itb.fetch_misses 17 # ITB misses
|
||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
||||
system.cpu.itb.fetch_accesses 6432 # ITB accesses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.itb.write_hits 0 # DTB write hits
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.itb.write_acv 0 # DTB write access violations
|
||||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.itb.data_hits 0 # DTB hits
|
||||
system.cpu.itb.data_misses 0 # DTB misses
|
||||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 17 # Number of system calls
|
||||
system.cpu.numCycles 279353 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 6404 # Number of instructions committed
|
||||
system.cpu.committedOps 6404 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 6331 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 251 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 750 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 6331 # number of integer instructions
|
||||
system.cpu.num_fp_insts 10 # number of float instructions
|
||||
system.cpu.num_int_register_reads 8304 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 4581 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 8 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 2 # number of times the floating registers were written
|
||||
system.cpu.num_mem_refs 2060 # number of memory refs
|
||||
system.cpu.num_load_insts 1192 # Number of load instructions
|
||||
system.cpu.num_store_insts 868 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 279353 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
@ -0,0 +1,339 @@
|
||||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
full_system=false
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000
|
||||
time_sync_spin_threshold=100000
|
||||
|
||||
[system]
|
||||
type=System
|
||||
children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby sys_port_proxy
|
||||
boot_osflags=a
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
mem_mode=timing
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
readfile=
|
||||
symbolfile=
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.sys_port_proxy.slave[0]
|
||||
|
||||
[system.cpu]
|
||||
type=TimingSimpleCPU
|
||||
children=dtb interrupts itb tracer workload
|
||||
checker=Null
|
||||
clock=1
|
||||
cpu_id=0
|
||||
defer_registration=false
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
interrupts=system.cpu.interrupts
|
||||
itb=system.cpu.itb
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
phase=0
|
||||
profile=0
|
||||
progress_interval=0
|
||||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
workload=system.cpu.workload
|
||||
dcache_port=system.l1_cntrl0.sequencer.slave[1]
|
||||
icache_port=system.l1_cntrl0.sequencer.slave[0]
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=AlphaTLB
|
||||
size=64
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=AlphaInterrupts
|
||||
|
||||
[system.cpu.itb]
|
||||
type=AlphaTLB
|
||||
size=48
|
||||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
|
||||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=hello
|
||||
cwd=
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
ppid=99
|
||||
simpoint=0
|
||||
system=system
|
||||
uid=100
|
||||
|
||||
[system.dir_cntrl0]
|
||||
type=Directory_Controller
|
||||
children=directory memBuffer
|
||||
buffer_size=0
|
||||
cntrl_id=2
|
||||
directory=system.dir_cntrl0.directory
|
||||
directory_latency=6
|
||||
memBuffer=system.dir_cntrl0.memBuffer
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
ruby_system=system.ruby
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.dir_cntrl0.directory]
|
||||
type=RubyDirectoryMemory
|
||||
map_levels=4
|
||||
numa_high_bit=6
|
||||
size=134217728
|
||||
use_map=false
|
||||
version=0
|
||||
|
||||
[system.dir_cntrl0.memBuffer]
|
||||
type=RubyMemoryControl
|
||||
bank_bit_0=8
|
||||
bank_busy_time=11
|
||||
bank_queue_size=12
|
||||
banks_per_rank=8
|
||||
basic_bus_busy_time=2
|
||||
dimm_bit_0=12
|
||||
dimms_per_channel=2
|
||||
mem_bus_cycle_multiplier=10
|
||||
mem_ctl_latency=12
|
||||
mem_fixed_delay=0
|
||||
mem_random_arbitrate=0
|
||||
rank_bit_0=11
|
||||
rank_rank_delay=1
|
||||
ranks_per_dimm=2
|
||||
read_write_delay=2
|
||||
refresh_period=1560
|
||||
tFaw=0
|
||||
version=0
|
||||
|
||||
[system.l1_cntrl0]
|
||||
type=L1Cache_Controller
|
||||
children=L1DcacheMemory L1IcacheMemory sequencer
|
||||
L1DcacheMemory=system.l1_cntrl0.L1DcacheMemory
|
||||
L1IcacheMemory=system.l1_cntrl0.L1IcacheMemory
|
||||
buffer_size=0
|
||||
cntrl_id=0
|
||||
l2_select_num_bits=0
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
request_latency=2
|
||||
ruby_system=system.ruby
|
||||
send_evictions=false
|
||||
sequencer=system.l1_cntrl0.sequencer
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.l1_cntrl0.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
is_icache=false
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl0.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
is_icache=false
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl0.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=true
|
||||
dcache=system.l1_cntrl0.L1DcacheMemory
|
||||
deadlock_threshold=500000
|
||||
icache=system.l1_cntrl0.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
ruby_system=system.ruby
|
||||
support_data_reqs=true
|
||||
support_inst_reqs=true
|
||||
system=system
|
||||
using_network_tester=false
|
||||
using_ruby_tester=false
|
||||
version=0
|
||||
slave=system.cpu.icache_port system.cpu.dcache_port
|
||||
|
||||
[system.l2_cntrl0]
|
||||
type=L2Cache_Controller
|
||||
children=L2cacheMemory
|
||||
L2cacheMemory=system.l2_cntrl0.L2cacheMemory
|
||||
buffer_size=0
|
||||
cntrl_id=1
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
request_latency=2
|
||||
response_latency=2
|
||||
ruby_system=system.ruby
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.l2_cntrl0.L2cacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
is_icache=false
|
||||
latency=15
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=512
|
||||
start_index_bit=6
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=30
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
|
||||
[system.ruby]
|
||||
type=RubySystem
|
||||
children=network profiler
|
||||
block_size_bytes=64
|
||||
clock=1
|
||||
mem_size=134217728
|
||||
no_mem_vec=false
|
||||
random_seed=1234
|
||||
randomization=false
|
||||
stats_filename=ruby.stats
|
||||
|
||||
[system.ruby.network]
|
||||
type=SimpleNetwork
|
||||
children=topology
|
||||
adaptive_routing=false
|
||||
buffer_size=0
|
||||
control_msg_size=8
|
||||
endpoint_bandwidth=1000
|
||||
number_of_virtual_networks=10
|
||||
ruby_system=system.ruby
|
||||
topology=system.ruby.network.topology
|
||||
|
||||
[system.ruby.network.topology]
|
||||
type=Topology
|
||||
children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2 routers0 routers1 routers2 routers3
|
||||
description=Crossbar
|
||||
ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2
|
||||
int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2
|
||||
print_config=false
|
||||
routers=system.ruby.network.topology.routers0 system.ruby.network.topology.routers1 system.ruby.network.topology.routers2 system.ruby.network.topology.routers3
|
||||
|
||||
[system.ruby.network.topology.ext_links0]
|
||||
type=SimpleExtLink
|
||||
bandwidth_factor=16
|
||||
ext_node=system.l1_cntrl0
|
||||
int_node=system.ruby.network.topology.routers0
|
||||
latency=1
|
||||
link_id=0
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links1]
|
||||
type=SimpleExtLink
|
||||
bandwidth_factor=16
|
||||
ext_node=system.l2_cntrl0
|
||||
int_node=system.ruby.network.topology.routers1
|
||||
latency=1
|
||||
link_id=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links2]
|
||||
type=SimpleExtLink
|
||||
bandwidth_factor=16
|
||||
ext_node=system.dir_cntrl0
|
||||
int_node=system.ruby.network.topology.routers2
|
||||
latency=1
|
||||
link_id=2
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.int_links0]
|
||||
type=SimpleIntLink
|
||||
bandwidth_factor=16
|
||||
latency=1
|
||||
link_id=3
|
||||
node_a=system.ruby.network.topology.routers0
|
||||
node_b=system.ruby.network.topology.routers3
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.int_links1]
|
||||
type=SimpleIntLink
|
||||
bandwidth_factor=16
|
||||
latency=1
|
||||
link_id=4
|
||||
node_a=system.ruby.network.topology.routers1
|
||||
node_b=system.ruby.network.topology.routers3
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.int_links2]
|
||||
type=SimpleIntLink
|
||||
bandwidth_factor=16
|
||||
latency=1
|
||||
link_id=5
|
||||
node_a=system.ruby.network.topology.routers2
|
||||
node_b=system.ruby.network.topology.routers3
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.routers0]
|
||||
type=BasicRouter
|
||||
router_id=0
|
||||
|
||||
[system.ruby.network.topology.routers1]
|
||||
type=BasicRouter
|
||||
router_id=1
|
||||
|
||||
[system.ruby.network.topology.routers2]
|
||||
type=BasicRouter
|
||||
router_id=2
|
||||
|
||||
[system.ruby.network.topology.routers3]
|
||||
type=BasicRouter
|
||||
router_id=3
|
||||
|
||||
[system.ruby.profiler]
|
||||
type=RubyProfiler
|
||||
all_instructions=false
|
||||
hot_lines=false
|
||||
num_of_sequencers=1
|
||||
ruby_system=system.ruby
|
||||
|
||||
[system.sys_port_proxy]
|
||||
type=RubyPortProxy
|
||||
access_phys_mem=true
|
||||
ruby_system=system.ruby
|
||||
support_data_reqs=true
|
||||
support_inst_reqs=true
|
||||
system=system
|
||||
using_network_tester=false
|
||||
using_ruby_tester=false
|
||||
version=0
|
||||
slave=system.system_port
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,2 @@
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
hack: be nice to actually delete the event here
|
||||
@ -0,0 +1,12 @@
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jun 4 2012 11:54:55
|
||||
gem5 started Jun 4 2012 14:41:04
|
||||
gem5 executing on zizzer
|
||||
command line: build/ALPHA_MOESI_CMP_directory/gem5.opt -d build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
Hello world!
|
||||
Exiting @ tick 223694 because target called exit()
|
||||
@ -0,0 +1,92 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000224 # Number of seconds simulated
|
||||
sim_ticks 223694 # Number of ticks simulated
|
||||
final_tick 223694 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 30014 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 30012 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1048235 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 226460 # Number of bytes of host memory used
|
||||
host_seconds 0.21 # Real time elapsed on the host
|
||||
sim_insts 6404 # Number of instructions simulated
|
||||
sim_ops 6404 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 25656 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 8804 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 34460 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 25656 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 25656 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::cpu.data 6696 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 6696 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 6414 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 1185 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 7599 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::cpu.data 865 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 865 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 114692392 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 39357336 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 154049729 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 114692392 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 114692392 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::cpu.data 29933749 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 29933749 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 114692392 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 69291085 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 183983477 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
||||
system.cpu.dtb.read_hits 1185 # DTB read hits
|
||||
system.cpu.dtb.read_misses 7 # DTB read misses
|
||||
system.cpu.dtb.read_acv 0 # DTB read access violations
|
||||
system.cpu.dtb.read_accesses 1192 # DTB read accesses
|
||||
system.cpu.dtb.write_hits 865 # DTB write hits
|
||||
system.cpu.dtb.write_misses 3 # DTB write misses
|
||||
system.cpu.dtb.write_acv 0 # DTB write access violations
|
||||
system.cpu.dtb.write_accesses 868 # DTB write accesses
|
||||
system.cpu.dtb.data_hits 2050 # DTB hits
|
||||
system.cpu.dtb.data_misses 10 # DTB misses
|
||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
||||
system.cpu.dtb.data_accesses 2060 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 6415 # ITB hits
|
||||
system.cpu.itb.fetch_misses 17 # ITB misses
|
||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
||||
system.cpu.itb.fetch_accesses 6432 # ITB accesses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.itb.write_hits 0 # DTB write hits
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.itb.write_acv 0 # DTB write access violations
|
||||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.itb.data_hits 0 # DTB hits
|
||||
system.cpu.itb.data_misses 0 # DTB misses
|
||||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 17 # Number of system calls
|
||||
system.cpu.numCycles 223694 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 6404 # Number of instructions committed
|
||||
system.cpu.committedOps 6404 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 6331 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 251 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 750 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 6331 # number of integer instructions
|
||||
system.cpu.num_fp_insts 10 # number of float instructions
|
||||
system.cpu.num_int_register_reads 8304 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 4581 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 8 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 2 # number of times the floating registers were written
|
||||
system.cpu.num_mem_refs 2060 # number of memory refs
|
||||
system.cpu.num_load_insts 1192 # Number of load instructions
|
||||
system.cpu.num_store_insts 868 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 223694 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
@ -0,0 +1,350 @@
|
||||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
full_system=false
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000
|
||||
time_sync_spin_threshold=100000
|
||||
|
||||
[system]
|
||||
type=System
|
||||
children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby sys_port_proxy
|
||||
boot_osflags=a
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
mem_mode=timing
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
readfile=
|
||||
symbolfile=
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.sys_port_proxy.slave[0]
|
||||
|
||||
[system.cpu]
|
||||
type=TimingSimpleCPU
|
||||
children=dtb interrupts itb tracer workload
|
||||
checker=Null
|
||||
clock=1
|
||||
cpu_id=0
|
||||
defer_registration=false
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
interrupts=system.cpu.interrupts
|
||||
itb=system.cpu.itb
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
phase=0
|
||||
profile=0
|
||||
progress_interval=0
|
||||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
workload=system.cpu.workload
|
||||
dcache_port=system.l1_cntrl0.sequencer.slave[1]
|
||||
icache_port=system.l1_cntrl0.sequencer.slave[0]
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=AlphaTLB
|
||||
size=64
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=AlphaInterrupts
|
||||
|
||||
[system.cpu.itb]
|
||||
type=AlphaTLB
|
||||
size=48
|
||||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
|
||||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=hello
|
||||
cwd=
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
ppid=99
|
||||
simpoint=0
|
||||
system=system
|
||||
uid=100
|
||||
|
||||
[system.dir_cntrl0]
|
||||
type=Directory_Controller
|
||||
children=directory memBuffer
|
||||
buffer_size=0
|
||||
cntrl_id=2
|
||||
directory=system.dir_cntrl0.directory
|
||||
directory_latency=5
|
||||
distributed_persistent=true
|
||||
fixed_timeout_latency=100
|
||||
l2_select_num_bits=0
|
||||
memBuffer=system.dir_cntrl0.memBuffer
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
ruby_system=system.ruby
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.dir_cntrl0.directory]
|
||||
type=RubyDirectoryMemory
|
||||
map_levels=4
|
||||
numa_high_bit=6
|
||||
size=134217728
|
||||
use_map=false
|
||||
version=0
|
||||
|
||||
[system.dir_cntrl0.memBuffer]
|
||||
type=RubyMemoryControl
|
||||
bank_bit_0=8
|
||||
bank_busy_time=11
|
||||
bank_queue_size=12
|
||||
banks_per_rank=8
|
||||
basic_bus_busy_time=2
|
||||
dimm_bit_0=12
|
||||
dimms_per_channel=2
|
||||
mem_bus_cycle_multiplier=10
|
||||
mem_ctl_latency=12
|
||||
mem_fixed_delay=0
|
||||
mem_random_arbitrate=0
|
||||
rank_bit_0=11
|
||||
rank_rank_delay=1
|
||||
ranks_per_dimm=2
|
||||
read_write_delay=2
|
||||
refresh_period=1560
|
||||
tFaw=0
|
||||
version=0
|
||||
|
||||
[system.l1_cntrl0]
|
||||
type=L1Cache_Controller
|
||||
children=L1DcacheMemory L1IcacheMemory sequencer
|
||||
L1DcacheMemory=system.l1_cntrl0.L1DcacheMemory
|
||||
L1IcacheMemory=system.l1_cntrl0.L1IcacheMemory
|
||||
N_tokens=2
|
||||
buffer_size=0
|
||||
cntrl_id=0
|
||||
dynamic_timeout_enabled=true
|
||||
fixed_timeout_latency=300
|
||||
l1_request_latency=2
|
||||
l1_response_latency=2
|
||||
l2_select_num_bits=0
|
||||
no_mig_atomic=true
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
retry_threshold=1
|
||||
ruby_system=system.ruby
|
||||
send_evictions=false
|
||||
sequencer=system.l1_cntrl0.sequencer
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.l1_cntrl0.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
is_icache=false
|
||||
latency=2
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl0.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
is_icache=false
|
||||
latency=2
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl0.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=true
|
||||
dcache=system.l1_cntrl0.L1DcacheMemory
|
||||
deadlock_threshold=500000
|
||||
icache=system.l1_cntrl0.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
ruby_system=system.ruby
|
||||
support_data_reqs=true
|
||||
support_inst_reqs=true
|
||||
system=system
|
||||
using_network_tester=false
|
||||
using_ruby_tester=false
|
||||
version=0
|
||||
slave=system.cpu.icache_port system.cpu.dcache_port
|
||||
|
||||
[system.l2_cntrl0]
|
||||
type=L2Cache_Controller
|
||||
children=L2cacheMemory
|
||||
L2cacheMemory=system.l2_cntrl0.L2cacheMemory
|
||||
N_tokens=2
|
||||
buffer_size=0
|
||||
cntrl_id=1
|
||||
filtering_enabled=true
|
||||
l2_request_latency=5
|
||||
l2_response_latency=5
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
ruby_system=system.ruby
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.l2_cntrl0.L2cacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
is_icache=false
|
||||
latency=10
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=512
|
||||
start_index_bit=6
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=30
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
|
||||
[system.ruby]
|
||||
type=RubySystem
|
||||
children=network profiler
|
||||
block_size_bytes=64
|
||||
clock=1
|
||||
mem_size=134217728
|
||||
no_mem_vec=false
|
||||
random_seed=1234
|
||||
randomization=false
|
||||
stats_filename=ruby.stats
|
||||
|
||||
[system.ruby.network]
|
||||
type=SimpleNetwork
|
||||
children=topology
|
||||
adaptive_routing=false
|
||||
buffer_size=0
|
||||
control_msg_size=8
|
||||
endpoint_bandwidth=1000
|
||||
number_of_virtual_networks=10
|
||||
ruby_system=system.ruby
|
||||
topology=system.ruby.network.topology
|
||||
|
||||
[system.ruby.network.topology]
|
||||
type=Topology
|
||||
children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2 routers0 routers1 routers2 routers3
|
||||
description=Crossbar
|
||||
ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2
|
||||
int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2
|
||||
print_config=false
|
||||
routers=system.ruby.network.topology.routers0 system.ruby.network.topology.routers1 system.ruby.network.topology.routers2 system.ruby.network.topology.routers3
|
||||
|
||||
[system.ruby.network.topology.ext_links0]
|
||||
type=SimpleExtLink
|
||||
bandwidth_factor=16
|
||||
ext_node=system.l1_cntrl0
|
||||
int_node=system.ruby.network.topology.routers0
|
||||
latency=1
|
||||
link_id=0
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links1]
|
||||
type=SimpleExtLink
|
||||
bandwidth_factor=16
|
||||
ext_node=system.l2_cntrl0
|
||||
int_node=system.ruby.network.topology.routers1
|
||||
latency=1
|
||||
link_id=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links2]
|
||||
type=SimpleExtLink
|
||||
bandwidth_factor=16
|
||||
ext_node=system.dir_cntrl0
|
||||
int_node=system.ruby.network.topology.routers2
|
||||
latency=1
|
||||
link_id=2
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.int_links0]
|
||||
type=SimpleIntLink
|
||||
bandwidth_factor=16
|
||||
latency=1
|
||||
link_id=3
|
||||
node_a=system.ruby.network.topology.routers0
|
||||
node_b=system.ruby.network.topology.routers3
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.int_links1]
|
||||
type=SimpleIntLink
|
||||
bandwidth_factor=16
|
||||
latency=1
|
||||
link_id=4
|
||||
node_a=system.ruby.network.topology.routers1
|
||||
node_b=system.ruby.network.topology.routers3
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.int_links2]
|
||||
type=SimpleIntLink
|
||||
bandwidth_factor=16
|
||||
latency=1
|
||||
link_id=5
|
||||
node_a=system.ruby.network.topology.routers2
|
||||
node_b=system.ruby.network.topology.routers3
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.routers0]
|
||||
type=BasicRouter
|
||||
router_id=0
|
||||
|
||||
[system.ruby.network.topology.routers1]
|
||||
type=BasicRouter
|
||||
router_id=1
|
||||
|
||||
[system.ruby.network.topology.routers2]
|
||||
type=BasicRouter
|
||||
router_id=2
|
||||
|
||||
[system.ruby.network.topology.routers3]
|
||||
type=BasicRouter
|
||||
router_id=3
|
||||
|
||||
[system.ruby.profiler]
|
||||
type=RubyProfiler
|
||||
all_instructions=false
|
||||
hot_lines=false
|
||||
num_of_sequencers=1
|
||||
ruby_system=system.ruby
|
||||
|
||||
[system.sys_port_proxy]
|
||||
type=RubyPortProxy
|
||||
access_phys_mem=true
|
||||
ruby_system=system.ruby
|
||||
support_data_reqs=true
|
||||
support_inst_reqs=true
|
||||
system=system
|
||||
using_network_tester=false
|
||||
using_ruby_tester=false
|
||||
version=0
|
||||
slave=system.system_port
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,2 @@
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
hack: be nice to actually delete the event here
|
||||
@ -0,0 +1,12 @@
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jun 4 2012 11:56:32
|
||||
gem5 started Jun 4 2012 14:42:12
|
||||
gem5 executing on zizzer
|
||||
command line: build/ALPHA_MOESI_CMP_token/gem5.opt -d build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
Hello world!
|
||||
Exiting @ tick 231701 because target called exit()
|
||||
@ -0,0 +1,92 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000232 # Number of seconds simulated
|
||||
sim_ticks 231701 # Number of ticks simulated
|
||||
final_tick 231701 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 50012 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 50005 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1808952 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 224692 # Number of bytes of host memory used
|
||||
host_seconds 0.13 # Real time elapsed on the host
|
||||
sim_insts 6404 # Number of instructions simulated
|
||||
sim_ops 6404 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 25656 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 8804 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 34460 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 25656 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 25656 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::cpu.data 6696 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 6696 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 6414 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 1185 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 7599 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::cpu.data 865 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 865 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 110728914 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 37997246 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 148726160 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 110728914 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 110728914 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::cpu.data 28899314 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 28899314 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 110728914 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 66896561 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 177625474 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
||||
system.cpu.dtb.read_hits 1185 # DTB read hits
|
||||
system.cpu.dtb.read_misses 7 # DTB read misses
|
||||
system.cpu.dtb.read_acv 0 # DTB read access violations
|
||||
system.cpu.dtb.read_accesses 1192 # DTB read accesses
|
||||
system.cpu.dtb.write_hits 865 # DTB write hits
|
||||
system.cpu.dtb.write_misses 3 # DTB write misses
|
||||
system.cpu.dtb.write_acv 0 # DTB write access violations
|
||||
system.cpu.dtb.write_accesses 868 # DTB write accesses
|
||||
system.cpu.dtb.data_hits 2050 # DTB hits
|
||||
system.cpu.dtb.data_misses 10 # DTB misses
|
||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
||||
system.cpu.dtb.data_accesses 2060 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 6415 # ITB hits
|
||||
system.cpu.itb.fetch_misses 17 # ITB misses
|
||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
||||
system.cpu.itb.fetch_accesses 6432 # ITB accesses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.itb.write_hits 0 # DTB write hits
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.itb.write_acv 0 # DTB write access violations
|
||||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.itb.data_hits 0 # DTB hits
|
||||
system.cpu.itb.data_misses 0 # DTB misses
|
||||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 17 # Number of system calls
|
||||
system.cpu.numCycles 231701 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 6404 # Number of instructions committed
|
||||
system.cpu.committedOps 6404 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 6331 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 251 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 750 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 6331 # number of integer instructions
|
||||
system.cpu.num_fp_insts 10 # number of float instructions
|
||||
system.cpu.num_int_register_reads 8304 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 4581 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 8 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 2 # number of times the floating registers were written
|
||||
system.cpu.num_mem_refs 2060 # number of memory refs
|
||||
system.cpu.num_load_insts 1192 # Number of load instructions
|
||||
system.cpu.num_store_insts 868 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 231701 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
@ -0,0 +1,318 @@
|
||||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
full_system=false
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000
|
||||
time_sync_spin_threshold=100000
|
||||
|
||||
[system]
|
||||
type=System
|
||||
children=cpu dir_cntrl0 l1_cntrl0 physmem ruby sys_port_proxy
|
||||
boot_osflags=a
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
mem_mode=timing
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
readfile=
|
||||
symbolfile=
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.sys_port_proxy.slave[0]
|
||||
|
||||
[system.cpu]
|
||||
type=TimingSimpleCPU
|
||||
children=dtb interrupts itb tracer workload
|
||||
checker=Null
|
||||
clock=1
|
||||
cpu_id=0
|
||||
defer_registration=false
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
interrupts=system.cpu.interrupts
|
||||
itb=system.cpu.itb
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
phase=0
|
||||
profile=0
|
||||
progress_interval=0
|
||||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
workload=system.cpu.workload
|
||||
dcache_port=system.l1_cntrl0.sequencer.slave[1]
|
||||
icache_port=system.l1_cntrl0.sequencer.slave[0]
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=AlphaTLB
|
||||
size=64
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=AlphaInterrupts
|
||||
|
||||
[system.cpu.itb]
|
||||
type=AlphaTLB
|
||||
size=48
|
||||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
|
||||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=hello
|
||||
cwd=
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
ppid=99
|
||||
simpoint=0
|
||||
system=system
|
||||
uid=100
|
||||
|
||||
[system.dir_cntrl0]
|
||||
type=Directory_Controller
|
||||
children=directory memBuffer probeFilter
|
||||
buffer_size=0
|
||||
cntrl_id=1
|
||||
directory=system.dir_cntrl0.directory
|
||||
full_bit_dir_enabled=false
|
||||
memBuffer=system.dir_cntrl0.memBuffer
|
||||
memory_controller_latency=2
|
||||
number_of_TBEs=256
|
||||
probeFilter=system.dir_cntrl0.probeFilter
|
||||
probe_filter_enabled=false
|
||||
recycle_latency=10
|
||||
ruby_system=system.ruby
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.dir_cntrl0.directory]
|
||||
type=RubyDirectoryMemory
|
||||
map_levels=4
|
||||
numa_high_bit=6
|
||||
size=134217728
|
||||
use_map=false
|
||||
version=0
|
||||
|
||||
[system.dir_cntrl0.memBuffer]
|
||||
type=RubyMemoryControl
|
||||
bank_bit_0=8
|
||||
bank_busy_time=11
|
||||
bank_queue_size=12
|
||||
banks_per_rank=8
|
||||
basic_bus_busy_time=2
|
||||
dimm_bit_0=12
|
||||
dimms_per_channel=2
|
||||
mem_bus_cycle_multiplier=10
|
||||
mem_ctl_latency=12
|
||||
mem_fixed_delay=0
|
||||
mem_random_arbitrate=0
|
||||
rank_bit_0=11
|
||||
rank_rank_delay=1
|
||||
ranks_per_dimm=2
|
||||
read_write_delay=2
|
||||
refresh_period=1560
|
||||
tFaw=0
|
||||
version=0
|
||||
|
||||
[system.dir_cntrl0.probeFilter]
|
||||
type=RubyCache
|
||||
assoc=4
|
||||
is_icache=false
|
||||
latency=1
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=1024
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl0]
|
||||
type=L1Cache_Controller
|
||||
children=L1DcacheMemory L1IcacheMemory L2cacheMemory sequencer
|
||||
L1DcacheMemory=system.l1_cntrl0.L1DcacheMemory
|
||||
L1IcacheMemory=system.l1_cntrl0.L1IcacheMemory
|
||||
L2cacheMemory=system.l1_cntrl0.L2cacheMemory
|
||||
buffer_size=0
|
||||
cache_response_latency=10
|
||||
cntrl_id=0
|
||||
issue_latency=2
|
||||
l2_cache_hit_latency=10
|
||||
no_mig_atomic=true
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
ruby_system=system.ruby
|
||||
send_evictions=false
|
||||
sequencer=system.l1_cntrl0.sequencer
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.l1_cntrl0.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
is_icache=false
|
||||
latency=2
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl0.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
is_icache=true
|
||||
latency=2
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl0.L2cacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
is_icache=false
|
||||
latency=10
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=512
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl0.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=true
|
||||
dcache=system.l1_cntrl0.L1DcacheMemory
|
||||
deadlock_threshold=500000
|
||||
icache=system.l1_cntrl0.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
ruby_system=system.ruby
|
||||
support_data_reqs=true
|
||||
support_inst_reqs=true
|
||||
system=system
|
||||
using_network_tester=false
|
||||
using_ruby_tester=false
|
||||
version=0
|
||||
slave=system.cpu.icache_port system.cpu.dcache_port
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=30
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
|
||||
[system.ruby]
|
||||
type=RubySystem
|
||||
children=network profiler
|
||||
block_size_bytes=64
|
||||
clock=1
|
||||
mem_size=134217728
|
||||
no_mem_vec=false
|
||||
random_seed=1234
|
||||
randomization=false
|
||||
stats_filename=ruby.stats
|
||||
|
||||
[system.ruby.network]
|
||||
type=SimpleNetwork
|
||||
children=topology
|
||||
adaptive_routing=false
|
||||
buffer_size=0
|
||||
control_msg_size=8
|
||||
endpoint_bandwidth=1000
|
||||
number_of_virtual_networks=10
|
||||
ruby_system=system.ruby
|
||||
topology=system.ruby.network.topology
|
||||
|
||||
[system.ruby.network.topology]
|
||||
type=Topology
|
||||
children=ext_links0 ext_links1 int_links0 int_links1 routers0 routers1 routers2
|
||||
description=Crossbar
|
||||
ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1
|
||||
int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1
|
||||
print_config=false
|
||||
routers=system.ruby.network.topology.routers0 system.ruby.network.topology.routers1 system.ruby.network.topology.routers2
|
||||
|
||||
[system.ruby.network.topology.ext_links0]
|
||||
type=SimpleExtLink
|
||||
bandwidth_factor=16
|
||||
ext_node=system.l1_cntrl0
|
||||
int_node=system.ruby.network.topology.routers0
|
||||
latency=1
|
||||
link_id=0
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links1]
|
||||
type=SimpleExtLink
|
||||
bandwidth_factor=16
|
||||
ext_node=system.dir_cntrl0
|
||||
int_node=system.ruby.network.topology.routers1
|
||||
latency=1
|
||||
link_id=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.int_links0]
|
||||
type=SimpleIntLink
|
||||
bandwidth_factor=16
|
||||
latency=1
|
||||
link_id=2
|
||||
node_a=system.ruby.network.topology.routers0
|
||||
node_b=system.ruby.network.topology.routers2
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.int_links1]
|
||||
type=SimpleIntLink
|
||||
bandwidth_factor=16
|
||||
latency=1
|
||||
link_id=3
|
||||
node_a=system.ruby.network.topology.routers1
|
||||
node_b=system.ruby.network.topology.routers2
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.routers0]
|
||||
type=BasicRouter
|
||||
router_id=0
|
||||
|
||||
[system.ruby.network.topology.routers1]
|
||||
type=BasicRouter
|
||||
router_id=1
|
||||
|
||||
[system.ruby.network.topology.routers2]
|
||||
type=BasicRouter
|
||||
router_id=2
|
||||
|
||||
[system.ruby.profiler]
|
||||
type=RubyProfiler
|
||||
all_instructions=false
|
||||
hot_lines=false
|
||||
num_of_sequencers=1
|
||||
ruby_system=system.ruby
|
||||
|
||||
[system.sys_port_proxy]
|
||||
type=RubyPortProxy
|
||||
access_phys_mem=true
|
||||
ruby_system=system.ruby
|
||||
support_data_reqs=true
|
||||
support_inst_reqs=true
|
||||
system=system
|
||||
using_network_tester=false
|
||||
using_ruby_tester=false
|
||||
version=0
|
||||
slave=system.system_port
|
||||
|
||||
@ -0,0 +1,973 @@
|
||||
|
||||
================ Begin RubySystem Configuration Print ================
|
||||
|
||||
RubySystem config:
|
||||
random_seed: 1234
|
||||
randomization: 0
|
||||
cycle_period: 1
|
||||
block_size_bytes: 64
|
||||
block_size_bits: 6
|
||||
memory_size_bytes: 134217728
|
||||
memory_size_bits: 27
|
||||
|
||||
Network Configuration
|
||||
---------------------
|
||||
network: SIMPLE_NETWORK
|
||||
topology:
|
||||
|
||||
virtual_net_0: active, ordered
|
||||
virtual_net_1: active, ordered
|
||||
virtual_net_2: active, unordered
|
||||
virtual_net_3: active, unordered
|
||||
virtual_net_4: active, unordered
|
||||
virtual_net_5: active, unordered
|
||||
virtual_net_6: inactive
|
||||
virtual_net_7: inactive
|
||||
virtual_net_8: inactive
|
||||
virtual_net_9: inactive
|
||||
|
||||
|
||||
Profiler Configuration
|
||||
----------------------
|
||||
periodic_stats_period: 1000000
|
||||
|
||||
================ End RubySystem Configuration Print ================
|
||||
|
||||
|
||||
Real time: Jun/04/2012 13:41:27
|
||||
|
||||
Profiler Stats
|
||||
--------------
|
||||
Elapsed_time_in_seconds: 0
|
||||
Elapsed_time_in_minutes: 0
|
||||
Elapsed_time_in_hours: 0
|
||||
Elapsed_time_in_days: 0
|
||||
|
||||
Virtual_time_in_seconds: 0.34
|
||||
Virtual_time_in_minutes: 0.00566667
|
||||
Virtual_time_in_hours: 9.44444e-05
|
||||
Virtual_time_in_days: 3.93519e-06
|
||||
|
||||
Ruby_current_time: 208400
|
||||
Ruby_start_time: 0
|
||||
Ruby_cycles: 208400
|
||||
|
||||
mbytes_resident: 47.2969
|
||||
mbytes_total: 218.926
|
||||
resident_ratio: 0.216041
|
||||
|
||||
ruby_cycles_executed: [ 208401 ]
|
||||
|
||||
Busy Controller Counts:
|
||||
L1Cache-0:0
|
||||
Directory-0:0
|
||||
|
||||
|
||||
Busy Bank Count:0
|
||||
|
||||
sequencer_requests_outstanding: [binsize: 1 max: 1 count: 8465 average: 1 | standard deviation: 0 | 0 8465 ]
|
||||
|
||||
All Non-Zero Cycle Demand Cache Accesses
|
||||
----------------------------------------
|
||||
miss_latency: [binsize: 2 max: 340 count: 8464 average: 23.6219 | standard deviation: 54.4451 | 0 7102 0 0 0 0 203 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 81 188 166 188 149 272 6 5 3 5 20 2 4 9 1 15 3 1 0 0 1 1 0 3 2 1 0 1 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 2 3 18 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 ]
|
||||
miss_latency_LD: [binsize: 2 max: 327 count: 1185 average: 57.3924 | standard deviation: 73.6654 | 0 660 0 0 0 0 105 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 37 78 73 59 44 91 2 3 1 3 5 2 2 3 0 6 1 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_ST: [binsize: 2 max: 340 count: 865 average: 34.9399 | standard deviation: 73.2706 | 0 674 0 0 0 0 33 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 8 37 38 7 31 0 0 0 0 1 0 2 1 0 2 0 1 0 0 0 1 0 2 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 3 17 0 0 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_IFETCH: [binsize: 2 max: 206 count: 6414 average: 15.8564 | standard deviation: 43.57 | 0 5768 0 0 0 0 65 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 43 102 56 91 98 150 4 2 2 2 14 0 0 5 1 7 2 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_L1Cache: [binsize: 1 max: 2 count: 7102 average: 2 | standard deviation: 0 | 0 0 7102 ]
|
||||
miss_latency_L2Cache: [binsize: 1 max: 13 count: 203 average: 13 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 203 ]
|
||||
miss_latency_Directory: [binsize: 2 max: 340 count: 1159 average: 157.975 | standard deviation: 26.6537 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 81 188 166 188 149 272 6 5 3 5 20 2 4 9 1 15 3 1 0 0 1 1 0 3 2 1 0 1 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 2 3 18 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 ]
|
||||
miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
imcomplete_wCC_Times: 0
|
||||
miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ]
|
||||
miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ]
|
||||
miss_latency_dir_forward_to_first_response: [binsize: 1 max: 158 count: 1 average: 158 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ]
|
||||
imcomplete_dir_Times: 1158
|
||||
miss_latency_LD_L1Cache: [binsize: 1 max: 2 count: 660 average: 2 | standard deviation: 0 | 0 0 660 ]
|
||||
miss_latency_LD_L2Cache: [binsize: 1 max: 13 count: 105 average: 13 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 105 ]
|
||||
miss_latency_LD_Directory: [binsize: 2 max: 327 count: 420 average: 155.536 | standard deviation: 18.768 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 37 78 73 59 44 91 2 3 1 3 5 2 2 3 0 6 1 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_ST_L1Cache: [binsize: 1 max: 2 count: 674 average: 2 | standard deviation: 0 | 0 0 674 ]
|
||||
miss_latency_ST_L2Cache: [binsize: 1 max: 13 count: 33 average: 13 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 33 ]
|
||||
miss_latency_ST_Directory: [binsize: 2 max: 340 count: 158 average: 180.038 | standard deviation: 59.9794 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 8 37 38 7 31 0 0 0 0 1 0 2 1 0 2 0 1 0 0 0 1 0 2 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 3 17 0 0 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_IFETCH_L1Cache: [binsize: 1 max: 2 count: 5768 average: 2 | standard deviation: 0 | 0 0 5768 ]
|
||||
miss_latency_IFETCH_L2Cache: [binsize: 1 max: 13 count: 65 average: 13 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 65 ]
|
||||
miss_latency_IFETCH_Directory: [binsize: 2 max: 206 count: 581 average: 153.738 | standard deviation: 5.93543 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 43 102 56 91 98 150 4 2 2 2 14 0 0 5 1 7 2 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
|
||||
All Non-Zero Cycle SW Prefetch Requests
|
||||
------------------------------------
|
||||
prefetch_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
prefetch_latency_L2Miss:[binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
Request vs. RubySystem State Profile
|
||||
--------------------------------
|
||||
|
||||
|
||||
filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
||||
Message Delayed Cycles
|
||||
----------------------
|
||||
Total_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_0_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_6_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_7_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_8_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_9_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
||||
Resource Usage
|
||||
--------------
|
||||
page_size: 4096
|
||||
user_time: 0
|
||||
system_time: 0
|
||||
page_reclaims: 12505
|
||||
page_faults: 5
|
||||
swaps: 0
|
||||
block_inputs: 1000
|
||||
block_outputs: 96
|
||||
|
||||
Network Stats
|
||||
-------------
|
||||
|
||||
total_msg_count_Request_Control: 3477 27816
|
||||
total_msg_count_Response_Data: 3477 250344
|
||||
total_msg_count_Writeback_Data: 660 47520
|
||||
total_msg_count_Writeback_Control: 9627 77016
|
||||
total_msg_count_Unblock_Control: 3477 27816
|
||||
total_msgs: 20718 total_bytes: 430512
|
||||
|
||||
switch_0_inlinks: 2
|
||||
switch_0_outlinks: 2
|
||||
links_utilized_percent_switch_0: 2.15187
|
||||
links_utilized_percent_switch_0_link_0: 2.77687 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_0_link_1: 1.52687 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_0_link_0_Response_Data: 1159 83448 [ 0 0 0 0 1159 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Writeback_Control: 1143 9144 [ 0 0 0 1143 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Request_Control: 1159 9272 [ 0 0 1159 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Writeback_Data: 220 15840 [ 0 0 0 0 0 220 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Writeback_Control: 2066 16528 [ 0 0 1143 0 0 923 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Unblock_Control: 1159 9272 [ 0 0 0 0 0 1159 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_1_inlinks: 2
|
||||
switch_1_outlinks: 2
|
||||
links_utilized_percent_switch_1: 2.15187
|
||||
links_utilized_percent_switch_1_link_0: 1.52687 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_1_link_1: 2.77687 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_1_link_0_Request_Control: 1159 9272 [ 0 0 1159 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Writeback_Data: 220 15840 [ 0 0 0 0 0 220 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Writeback_Control: 2066 16528 [ 0 0 1143 0 0 923 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Unblock_Control: 1159 9272 [ 0 0 0 0 0 1159 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Response_Data: 1159 83448 [ 0 0 0 0 1159 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Writeback_Control: 1143 9144 [ 0 0 0 1143 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_2_inlinks: 2
|
||||
switch_2_outlinks: 2
|
||||
links_utilized_percent_switch_2: 2.15187
|
||||
links_utilized_percent_switch_2_link_0: 2.77687 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_2_link_1: 1.52687 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_2_link_0_Response_Data: 1159 83448 [ 0 0 0 0 1159 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Writeback_Control: 1143 9144 [ 0 0 0 1143 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Request_Control: 1159 9272 [ 0 0 1159 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Writeback_Data: 220 15840 [ 0 0 0 0 0 220 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Writeback_Control: 2066 16528 [ 0 0 1143 0 0 923 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Unblock_Control: 1159 9272 [ 0 0 0 0 0 1159 0 0 0 0 ] base_latency: 1
|
||||
|
||||
Cache Stats: system.l1_cntrl0.L1IcacheMemory
|
||||
system.l1_cntrl0.L1IcacheMemory_total_misses: 646
|
||||
system.l1_cntrl0.L1IcacheMemory_total_demand_misses: 646
|
||||
system.l1_cntrl0.L1IcacheMemory_total_prefetches: 0
|
||||
system.l1_cntrl0.L1IcacheMemory_total_sw_prefetches: 0
|
||||
system.l1_cntrl0.L1IcacheMemory_total_hw_prefetches: 0
|
||||
|
||||
system.l1_cntrl0.L1IcacheMemory_request_type_IFETCH: 100%
|
||||
|
||||
system.l1_cntrl0.L1IcacheMemory_access_mode_type_Supervisor: 646 100%
|
||||
|
||||
Cache Stats: system.l1_cntrl0.L1DcacheMemory
|
||||
system.l1_cntrl0.L1DcacheMemory_total_misses: 716
|
||||
system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 716
|
||||
system.l1_cntrl0.L1DcacheMemory_total_prefetches: 0
|
||||
system.l1_cntrl0.L1DcacheMemory_total_sw_prefetches: 0
|
||||
system.l1_cntrl0.L1DcacheMemory_total_hw_prefetches: 0
|
||||
|
||||
system.l1_cntrl0.L1DcacheMemory_request_type_LD: 73.324%
|
||||
system.l1_cntrl0.L1DcacheMemory_request_type_ST: 26.676%
|
||||
|
||||
system.l1_cntrl0.L1DcacheMemory_access_mode_type_Supervisor: 716 100%
|
||||
|
||||
Cache Stats: system.l1_cntrl0.L2cacheMemory
|
||||
system.l1_cntrl0.L2cacheMemory_total_misses: 1362
|
||||
system.l1_cntrl0.L2cacheMemory_total_demand_misses: 1362
|
||||
system.l1_cntrl0.L2cacheMemory_total_prefetches: 0
|
||||
system.l1_cntrl0.L2cacheMemory_total_sw_prefetches: 0
|
||||
system.l1_cntrl0.L2cacheMemory_total_hw_prefetches: 0
|
||||
|
||||
system.l1_cntrl0.L2cacheMemory_request_type_LD: 38.5463%
|
||||
system.l1_cntrl0.L2cacheMemory_request_type_ST: 14.0235%
|
||||
system.l1_cntrl0.L2cacheMemory_request_type_IFETCH: 47.4302%
|
||||
|
||||
system.l1_cntrl0.L2cacheMemory_access_mode_type_Supervisor: 1362 100%
|
||||
|
||||
--- L1Cache ---
|
||||
- Event Counts -
|
||||
Load [1193 ] 1193
|
||||
Ifetch [6425 ] 6425
|
||||
Store [892 ] 892
|
||||
L2_Replacement [1143 ] 1143
|
||||
L1_to_L2 [1354 ] 1354
|
||||
Trigger_L2_to_L1D [138 ] 138
|
||||
Trigger_L2_to_L1I [65 ] 65
|
||||
Complete_L2_to_L1 [203 ] 203
|
||||
Other_GETX [0 ] 0
|
||||
Other_GETS [0 ] 0
|
||||
Merged_GETS [0 ] 0
|
||||
Other_GETS_No_Mig [0 ] 0
|
||||
NC_DMA_GETS [0 ] 0
|
||||
Invalidate [0 ] 0
|
||||
Ack [0 ] 0
|
||||
Shared_Ack [0 ] 0
|
||||
Data [0 ] 0
|
||||
Shared_Data [0 ] 0
|
||||
Exclusive_Data [1159 ] 1159
|
||||
Writeback_Ack [1143 ] 1143
|
||||
Writeback_Nack [0 ] 0
|
||||
All_acks [0 ] 0
|
||||
All_acks_no_sharers [1159 ] 1159
|
||||
Flush_line [0 ] 0
|
||||
Block_Ack [0 ] 0
|
||||
|
||||
- Transitions -
|
||||
I Load [420 ] 420
|
||||
I Ifetch [581 ] 581
|
||||
I Store [158 ] 158
|
||||
I L2_Replacement [0 ] 0
|
||||
I L1_to_L2 [0 ] 0
|
||||
I Trigger_L2_to_L1D [0 ] 0
|
||||
I Trigger_L2_to_L1I [0 ] 0
|
||||
I Other_GETX [0 ] 0
|
||||
I Other_GETS [0 ] 0
|
||||
I Other_GETS_No_Mig [0 ] 0
|
||||
I NC_DMA_GETS [0 ] 0
|
||||
I Invalidate [0 ] 0
|
||||
I Flush_line [0 ] 0
|
||||
|
||||
S Load [0 ] 0
|
||||
S Ifetch [0 ] 0
|
||||
S Store [0 ] 0
|
||||
S L2_Replacement [0 ] 0
|
||||
S L1_to_L2 [0 ] 0
|
||||
S Trigger_L2_to_L1D [0 ] 0
|
||||
S Trigger_L2_to_L1I [0 ] 0
|
||||
S Other_GETX [0 ] 0
|
||||
S Other_GETS [0 ] 0
|
||||
S Other_GETS_No_Mig [0 ] 0
|
||||
S NC_DMA_GETS [0 ] 0
|
||||
S Invalidate [0 ] 0
|
||||
S Flush_line [0 ] 0
|
||||
|
||||
O Load [0 ] 0
|
||||
O Ifetch [0 ] 0
|
||||
O Store [0 ] 0
|
||||
O L2_Replacement [0 ] 0
|
||||
O L1_to_L2 [0 ] 0
|
||||
O Trigger_L2_to_L1D [0 ] 0
|
||||
O Trigger_L2_to_L1I [0 ] 0
|
||||
O Other_GETX [0 ] 0
|
||||
O Other_GETS [0 ] 0
|
||||
O Merged_GETS [0 ] 0
|
||||
O Other_GETS_No_Mig [0 ] 0
|
||||
O NC_DMA_GETS [0 ] 0
|
||||
O Invalidate [0 ] 0
|
||||
O Flush_line [0 ] 0
|
||||
|
||||
M Load [306 ] 306
|
||||
M Ifetch [5768 ] 5768
|
||||
M Store [60 ] 60
|
||||
M L2_Replacement [923 ] 923
|
||||
M L1_to_L2 [1061 ] 1061
|
||||
M Trigger_L2_to_L1D [68 ] 68
|
||||
M Trigger_L2_to_L1I [65 ] 65
|
||||
M Other_GETX [0 ] 0
|
||||
M Other_GETS [0 ] 0
|
||||
M Merged_GETS [0 ] 0
|
||||
M Other_GETS_No_Mig [0 ] 0
|
||||
M NC_DMA_GETS [0 ] 0
|
||||
M Invalidate [0 ] 0
|
||||
M Flush_line [0 ] 0
|
||||
|
||||
MM Load [354 ] 354
|
||||
MM Ifetch [0 ] 0
|
||||
MM Store [614 ] 614
|
||||
MM L2_Replacement [220 ] 220
|
||||
MM L1_to_L2 [293 ] 293
|
||||
MM Trigger_L2_to_L1D [70 ] 70
|
||||
MM Trigger_L2_to_L1I [0 ] 0
|
||||
MM Other_GETX [0 ] 0
|
||||
MM Other_GETS [0 ] 0
|
||||
MM Merged_GETS [0 ] 0
|
||||
MM Other_GETS_No_Mig [0 ] 0
|
||||
MM NC_DMA_GETS [0 ] 0
|
||||
MM Invalidate [0 ] 0
|
||||
MM Flush_line [0 ] 0
|
||||
|
||||
IR Load [0 ] 0
|
||||
IR Ifetch [0 ] 0
|
||||
IR Store [0 ] 0
|
||||
IR L1_to_L2 [0 ] 0
|
||||
IR Flush_line [0 ] 0
|
||||
|
||||
SR Load [0 ] 0
|
||||
SR Ifetch [0 ] 0
|
||||
SR Store [0 ] 0
|
||||
SR L1_to_L2 [0 ] 0
|
||||
SR Flush_line [0 ] 0
|
||||
|
||||
OR Load [0 ] 0
|
||||
OR Ifetch [0 ] 0
|
||||
OR Store [0 ] 0
|
||||
OR L1_to_L2 [0 ] 0
|
||||
OR Flush_line [0 ] 0
|
||||
|
||||
MR Load [62 ] 62
|
||||
MR Ifetch [65 ] 65
|
||||
MR Store [6 ] 6
|
||||
MR L1_to_L2 [0 ] 0
|
||||
MR Flush_line [0 ] 0
|
||||
|
||||
MMR Load [43 ] 43
|
||||
MMR Ifetch [0 ] 0
|
||||
MMR Store [27 ] 27
|
||||
MMR L1_to_L2 [0 ] 0
|
||||
MMR Flush_line [0 ] 0
|
||||
|
||||
IM Load [0 ] 0
|
||||
IM Ifetch [0 ] 0
|
||||
IM Store [0 ] 0
|
||||
IM L2_Replacement [0 ] 0
|
||||
IM L1_to_L2 [0 ] 0
|
||||
IM Other_GETX [0 ] 0
|
||||
IM Other_GETS [0 ] 0
|
||||
IM Other_GETS_No_Mig [0 ] 0
|
||||
IM NC_DMA_GETS [0 ] 0
|
||||
IM Invalidate [0 ] 0
|
||||
IM Ack [0 ] 0
|
||||
IM Data [0 ] 0
|
||||
IM Exclusive_Data [158 ] 158
|
||||
IM Flush_line [0 ] 0
|
||||
|
||||
SM Load [0 ] 0
|
||||
SM Ifetch [0 ] 0
|
||||
SM Store [0 ] 0
|
||||
SM L2_Replacement [0 ] 0
|
||||
SM L1_to_L2 [0 ] 0
|
||||
SM Other_GETX [0 ] 0
|
||||
SM Other_GETS [0 ] 0
|
||||
SM Other_GETS_No_Mig [0 ] 0
|
||||
SM NC_DMA_GETS [0 ] 0
|
||||
SM Invalidate [0 ] 0
|
||||
SM Ack [0 ] 0
|
||||
SM Data [0 ] 0
|
||||
SM Exclusive_Data [0 ] 0
|
||||
SM Flush_line [0 ] 0
|
||||
|
||||
OM Load [0 ] 0
|
||||
OM Ifetch [0 ] 0
|
||||
OM Store [0 ] 0
|
||||
OM L2_Replacement [0 ] 0
|
||||
OM L1_to_L2 [0 ] 0
|
||||
OM Other_GETX [0 ] 0
|
||||
OM Other_GETS [0 ] 0
|
||||
OM Merged_GETS [0 ] 0
|
||||
OM Other_GETS_No_Mig [0 ] 0
|
||||
OM NC_DMA_GETS [0 ] 0
|
||||
OM Invalidate [0 ] 0
|
||||
OM Ack [0 ] 0
|
||||
OM All_acks [0 ] 0
|
||||
OM All_acks_no_sharers [0 ] 0
|
||||
OM Flush_line [0 ] 0
|
||||
|
||||
ISM Load [0 ] 0
|
||||
ISM Ifetch [0 ] 0
|
||||
ISM Store [0 ] 0
|
||||
ISM L2_Replacement [0 ] 0
|
||||
ISM L1_to_L2 [0 ] 0
|
||||
ISM Ack [0 ] 0
|
||||
ISM All_acks_no_sharers [0 ] 0
|
||||
ISM Flush_line [0 ] 0
|
||||
|
||||
M_W Load [0 ] 0
|
||||
M_W Ifetch [0 ] 0
|
||||
M_W Store [0 ] 0
|
||||
M_W L2_Replacement [0 ] 0
|
||||
M_W L1_to_L2 [0 ] 0
|
||||
M_W Ack [0 ] 0
|
||||
M_W All_acks_no_sharers [1001 ] 1001
|
||||
M_W Flush_line [0 ] 0
|
||||
|
||||
MM_W Load [0 ] 0
|
||||
MM_W Ifetch [0 ] 0
|
||||
MM_W Store [0 ] 0
|
||||
MM_W L2_Replacement [0 ] 0
|
||||
MM_W L1_to_L2 [0 ] 0
|
||||
MM_W Ack [0 ] 0
|
||||
MM_W All_acks_no_sharers [158 ] 158
|
||||
MM_W Flush_line [0 ] 0
|
||||
|
||||
IS Load [0 ] 0
|
||||
IS Ifetch [0 ] 0
|
||||
IS Store [0 ] 0
|
||||
IS L2_Replacement [0 ] 0
|
||||
IS L1_to_L2 [0 ] 0
|
||||
IS Other_GETX [0 ] 0
|
||||
IS Other_GETS [0 ] 0
|
||||
IS Other_GETS_No_Mig [0 ] 0
|
||||
IS NC_DMA_GETS [0 ] 0
|
||||
IS Invalidate [0 ] 0
|
||||
IS Ack [0 ] 0
|
||||
IS Shared_Ack [0 ] 0
|
||||
IS Data [0 ] 0
|
||||
IS Shared_Data [0 ] 0
|
||||
IS Exclusive_Data [1001 ] 1001
|
||||
IS Flush_line [0 ] 0
|
||||
|
||||
SS Load [0 ] 0
|
||||
SS Ifetch [0 ] 0
|
||||
SS Store [0 ] 0
|
||||
SS L2_Replacement [0 ] 0
|
||||
SS L1_to_L2 [0 ] 0
|
||||
SS Ack [0 ] 0
|
||||
SS Shared_Ack [0 ] 0
|
||||
SS All_acks [0 ] 0
|
||||
SS All_acks_no_sharers [0 ] 0
|
||||
SS Flush_line [0 ] 0
|
||||
|
||||
OI Load [0 ] 0
|
||||
OI Ifetch [0 ] 0
|
||||
OI Store [0 ] 0
|
||||
OI L2_Replacement [0 ] 0
|
||||
OI L1_to_L2 [0 ] 0
|
||||
OI Other_GETX [0 ] 0
|
||||
OI Other_GETS [0 ] 0
|
||||
OI Merged_GETS [0 ] 0
|
||||
OI Other_GETS_No_Mig [0 ] 0
|
||||
OI NC_DMA_GETS [0 ] 0
|
||||
OI Invalidate [0 ] 0
|
||||
OI Writeback_Ack [0 ] 0
|
||||
OI Flush_line [0 ] 0
|
||||
|
||||
MI Load [8 ] 8
|
||||
MI Ifetch [11 ] 11
|
||||
MI Store [27 ] 27
|
||||
MI L2_Replacement [0 ] 0
|
||||
MI L1_to_L2 [0 ] 0
|
||||
MI Other_GETX [0 ] 0
|
||||
MI Other_GETS [0 ] 0
|
||||
MI Merged_GETS [0 ] 0
|
||||
MI Other_GETS_No_Mig [0 ] 0
|
||||
MI NC_DMA_GETS [0 ] 0
|
||||
MI Invalidate [0 ] 0
|
||||
MI Writeback_Ack [1143 ] 1143
|
||||
MI Flush_line [0 ] 0
|
||||
|
||||
II Load [0 ] 0
|
||||
II Ifetch [0 ] 0
|
||||
II Store [0 ] 0
|
||||
II L2_Replacement [0 ] 0
|
||||
II L1_to_L2 [0 ] 0
|
||||
II Other_GETX [0 ] 0
|
||||
II Other_GETS [0 ] 0
|
||||
II Other_GETS_No_Mig [0 ] 0
|
||||
II NC_DMA_GETS [0 ] 0
|
||||
II Invalidate [0 ] 0
|
||||
II Writeback_Ack [0 ] 0
|
||||
II Writeback_Nack [0 ] 0
|
||||
II Flush_line [0 ] 0
|
||||
|
||||
IT Load [0 ] 0
|
||||
IT Ifetch [0 ] 0
|
||||
IT Store [0 ] 0
|
||||
IT L2_Replacement [0 ] 0
|
||||
IT L1_to_L2 [0 ] 0
|
||||
IT Complete_L2_to_L1 [0 ] 0
|
||||
|
||||
ST Load [0 ] 0
|
||||
ST Ifetch [0 ] 0
|
||||
ST Store [0 ] 0
|
||||
ST L2_Replacement [0 ] 0
|
||||
ST L1_to_L2 [0 ] 0
|
||||
ST Complete_L2_to_L1 [0 ] 0
|
||||
|
||||
OT Load [0 ] 0
|
||||
OT Ifetch [0 ] 0
|
||||
OT Store [0 ] 0
|
||||
OT L2_Replacement [0 ] 0
|
||||
OT L1_to_L2 [0 ] 0
|
||||
OT Complete_L2_to_L1 [0 ] 0
|
||||
|
||||
MT Load [0 ] 0
|
||||
MT Ifetch [0 ] 0
|
||||
MT Store [0 ] 0
|
||||
MT L2_Replacement [0 ] 0
|
||||
MT L1_to_L2 [0 ] 0
|
||||
MT Complete_L2_to_L1 [133 ] 133
|
||||
|
||||
MMT Load [0 ] 0
|
||||
MMT Ifetch [0 ] 0
|
||||
MMT Store [0 ] 0
|
||||
MMT L2_Replacement [0 ] 0
|
||||
MMT L1_to_L2 [0 ] 0
|
||||
MMT Complete_L2_to_L1 [70 ] 70
|
||||
|
||||
MI_F Load [0 ] 0
|
||||
MI_F Ifetch [0 ] 0
|
||||
MI_F Store [0 ] 0
|
||||
MI_F L1_to_L2 [0 ] 0
|
||||
MI_F Writeback_Ack [0 ] 0
|
||||
MI_F Flush_line [0 ] 0
|
||||
|
||||
MM_F Load [0 ] 0
|
||||
MM_F Ifetch [0 ] 0
|
||||
MM_F Store [0 ] 0
|
||||
MM_F L1_to_L2 [0 ] 0
|
||||
MM_F Other_GETX [0 ] 0
|
||||
MM_F Other_GETS [0 ] 0
|
||||
MM_F Merged_GETS [0 ] 0
|
||||
MM_F Other_GETS_No_Mig [0 ] 0
|
||||
MM_F NC_DMA_GETS [0 ] 0
|
||||
MM_F Invalidate [0 ] 0
|
||||
MM_F Ack [0 ] 0
|
||||
MM_F All_acks [0 ] 0
|
||||
MM_F All_acks_no_sharers [0 ] 0
|
||||
MM_F Flush_line [0 ] 0
|
||||
MM_F Block_Ack [0 ] 0
|
||||
|
||||
IM_F Load [0 ] 0
|
||||
IM_F Ifetch [0 ] 0
|
||||
IM_F Store [0 ] 0
|
||||
IM_F L2_Replacement [0 ] 0
|
||||
IM_F L1_to_L2 [0 ] 0
|
||||
IM_F Other_GETX [0 ] 0
|
||||
IM_F Other_GETS [0 ] 0
|
||||
IM_F Other_GETS_No_Mig [0 ] 0
|
||||
IM_F NC_DMA_GETS [0 ] 0
|
||||
IM_F Invalidate [0 ] 0
|
||||
IM_F Ack [0 ] 0
|
||||
IM_F Data [0 ] 0
|
||||
IM_F Exclusive_Data [0 ] 0
|
||||
IM_F Flush_line [0 ] 0
|
||||
|
||||
ISM_F Load [0 ] 0
|
||||
ISM_F Ifetch [0 ] 0
|
||||
ISM_F Store [0 ] 0
|
||||
ISM_F L2_Replacement [0 ] 0
|
||||
ISM_F L1_to_L2 [0 ] 0
|
||||
ISM_F Ack [0 ] 0
|
||||
ISM_F All_acks_no_sharers [0 ] 0
|
||||
ISM_F Flush_line [0 ] 0
|
||||
|
||||
SM_F Load [0 ] 0
|
||||
SM_F Ifetch [0 ] 0
|
||||
SM_F Store [0 ] 0
|
||||
SM_F L2_Replacement [0 ] 0
|
||||
SM_F L1_to_L2 [0 ] 0
|
||||
SM_F Other_GETX [0 ] 0
|
||||
SM_F Other_GETS [0 ] 0
|
||||
SM_F Other_GETS_No_Mig [0 ] 0
|
||||
SM_F NC_DMA_GETS [0 ] 0
|
||||
SM_F Invalidate [0 ] 0
|
||||
SM_F Ack [0 ] 0
|
||||
SM_F Data [0 ] 0
|
||||
SM_F Exclusive_Data [0 ] 0
|
||||
SM_F Flush_line [0 ] 0
|
||||
|
||||
OM_F Load [0 ] 0
|
||||
OM_F Ifetch [0 ] 0
|
||||
OM_F Store [0 ] 0
|
||||
OM_F L2_Replacement [0 ] 0
|
||||
OM_F L1_to_L2 [0 ] 0
|
||||
OM_F Other_GETX [0 ] 0
|
||||
OM_F Other_GETS [0 ] 0
|
||||
OM_F Merged_GETS [0 ] 0
|
||||
OM_F Other_GETS_No_Mig [0 ] 0
|
||||
OM_F NC_DMA_GETS [0 ] 0
|
||||
OM_F Invalidate [0 ] 0
|
||||
OM_F Ack [0 ] 0
|
||||
OM_F All_acks [0 ] 0
|
||||
OM_F All_acks_no_sharers [0 ] 0
|
||||
OM_F Flush_line [0 ] 0
|
||||
|
||||
MM_WF Load [0 ] 0
|
||||
MM_WF Ifetch [0 ] 0
|
||||
MM_WF Store [0 ] 0
|
||||
MM_WF L2_Replacement [0 ] 0
|
||||
MM_WF L1_to_L2 [0 ] 0
|
||||
MM_WF Ack [0 ] 0
|
||||
MM_WF All_acks_no_sharers [0 ] 0
|
||||
MM_WF Flush_line [0 ] 0
|
||||
|
||||
Cache Stats: system.dir_cntrl0.probeFilter
|
||||
system.dir_cntrl0.probeFilter_total_misses: 0
|
||||
system.dir_cntrl0.probeFilter_total_demand_misses: 0
|
||||
system.dir_cntrl0.probeFilter_total_prefetches: 0
|
||||
system.dir_cntrl0.probeFilter_total_sw_prefetches: 0
|
||||
system.dir_cntrl0.probeFilter_total_hw_prefetches: 0
|
||||
|
||||
|
||||
Memory controller: system.dir_cntrl0.memBuffer:
|
||||
memory_total_requests: 1379
|
||||
memory_reads: 1159
|
||||
memory_writes: 220
|
||||
memory_refreshes: 435
|
||||
memory_total_request_delays: 495
|
||||
memory_delays_per_request: 0.358956
|
||||
memory_delays_in_input_queue: 3
|
||||
memory_delays_behind_head_of_bank_queue: 0
|
||||
memory_delays_stalled_at_head_of_bank_queue: 492
|
||||
memory_stalls_for_bank_busy: 124
|
||||
memory_stalls_for_random_busy: 0
|
||||
memory_stalls_for_anti_starvation: 0
|
||||
memory_stalls_for_arbitration: 23
|
||||
memory_stalls_for_bus: 78
|
||||
memory_stalls_for_tfaw: 0
|
||||
memory_stalls_for_read_write_turnaround: 267
|
||||
memory_stalls_for_read_read_turnaround: 0
|
||||
accesses_per_bank: 75 17 45 40 54 101 33 16 20 22 32 34 53 50 39 31 39 22 21 27 28 38 81 22 31 23 32 72 89 126 14 52
|
||||
|
||||
--- Directory ---
|
||||
- Event Counts -
|
||||
GETX [189 ] 189
|
||||
GETS [1027 ] 1027
|
||||
PUT [1143 ] 1143
|
||||
Unblock [0 ] 0
|
||||
UnblockS [0 ] 0
|
||||
UnblockM [1159 ] 1159
|
||||
Writeback_Clean [0 ] 0
|
||||
Writeback_Dirty [0 ] 0
|
||||
Writeback_Exclusive_Clean [923 ] 923
|
||||
Writeback_Exclusive_Dirty [220 ] 220
|
||||
Pf_Replacement [0 ] 0
|
||||
DMA_READ [0 ] 0
|
||||
DMA_WRITE [0 ] 0
|
||||
Memory_Data [1159 ] 1159
|
||||
Memory_Ack [220 ] 220
|
||||
Ack [0 ] 0
|
||||
Shared_Ack [0 ] 0
|
||||
Shared_Data [0 ] 0
|
||||
Data [0 ] 0
|
||||
Exclusive_Data [0 ] 0
|
||||
All_acks_and_shared_data [0 ] 0
|
||||
All_acks_and_owner_data [0 ] 0
|
||||
All_acks_and_data_no_sharers [0 ] 0
|
||||
All_Unblocks [0 ] 0
|
||||
GETF [0 ] 0
|
||||
PUTF [0 ] 0
|
||||
|
||||
- Transitions -
|
||||
NX GETX [0 ] 0
|
||||
NX GETS [0 ] 0
|
||||
NX PUT [0 ] 0
|
||||
NX Pf_Replacement [0 ] 0
|
||||
NX DMA_READ [0 ] 0
|
||||
NX DMA_WRITE [0 ] 0
|
||||
NX GETF [0 ] 0
|
||||
|
||||
NO GETX [0 ] 0
|
||||
NO GETS [0 ] 0
|
||||
NO PUT [1143 ] 1143
|
||||
NO Pf_Replacement [0 ] 0
|
||||
NO DMA_READ [0 ] 0
|
||||
NO DMA_WRITE [0 ] 0
|
||||
NO GETF [0 ] 0
|
||||
|
||||
S GETX [0 ] 0
|
||||
S GETS [0 ] 0
|
||||
S PUT [0 ] 0
|
||||
S Pf_Replacement [0 ] 0
|
||||
S DMA_READ [0 ] 0
|
||||
S DMA_WRITE [0 ] 0
|
||||
S GETF [0 ] 0
|
||||
|
||||
O GETX [0 ] 0
|
||||
O GETS [0 ] 0
|
||||
O PUT [0 ] 0
|
||||
O Pf_Replacement [0 ] 0
|
||||
O DMA_READ [0 ] 0
|
||||
O DMA_WRITE [0 ] 0
|
||||
O GETF [0 ] 0
|
||||
|
||||
E GETX [158 ] 158
|
||||
E GETS [1001 ] 1001
|
||||
E PUT [0 ] 0
|
||||
E DMA_READ [0 ] 0
|
||||
E DMA_WRITE [0 ] 0
|
||||
E GETF [0 ] 0
|
||||
|
||||
O_R GETX [0 ] 0
|
||||
O_R GETS [0 ] 0
|
||||
O_R PUT [0 ] 0
|
||||
O_R Pf_Replacement [0 ] 0
|
||||
O_R DMA_READ [0 ] 0
|
||||
O_R DMA_WRITE [0 ] 0
|
||||
O_R Ack [0 ] 0
|
||||
O_R All_acks_and_data_no_sharers [0 ] 0
|
||||
O_R GETF [0 ] 0
|
||||
|
||||
S_R GETX [0 ] 0
|
||||
S_R GETS [0 ] 0
|
||||
S_R PUT [0 ] 0
|
||||
S_R Pf_Replacement [0 ] 0
|
||||
S_R DMA_READ [0 ] 0
|
||||
S_R DMA_WRITE [0 ] 0
|
||||
S_R Ack [0 ] 0
|
||||
S_R Data [0 ] 0
|
||||
S_R All_acks_and_data_no_sharers [0 ] 0
|
||||
S_R GETF [0 ] 0
|
||||
|
||||
NO_R GETX [0 ] 0
|
||||
NO_R GETS [0 ] 0
|
||||
NO_R PUT [0 ] 0
|
||||
NO_R Pf_Replacement [0 ] 0
|
||||
NO_R DMA_READ [0 ] 0
|
||||
NO_R DMA_WRITE [0 ] 0
|
||||
NO_R Ack [0 ] 0
|
||||
NO_R Data [0 ] 0
|
||||
NO_R Exclusive_Data [0 ] 0
|
||||
NO_R All_acks_and_data_no_sharers [0 ] 0
|
||||
NO_R GETF [0 ] 0
|
||||
|
||||
NO_B GETX [0 ] 0
|
||||
NO_B GETS [0 ] 0
|
||||
NO_B PUT [0 ] 0
|
||||
NO_B UnblockS [0 ] 0
|
||||
NO_B UnblockM [1159 ] 1159
|
||||
NO_B Pf_Replacement [0 ] 0
|
||||
NO_B DMA_READ [0 ] 0
|
||||
NO_B DMA_WRITE [0 ] 0
|
||||
NO_B GETF [0 ] 0
|
||||
|
||||
NO_B_X GETX [0 ] 0
|
||||
NO_B_X GETS [0 ] 0
|
||||
NO_B_X PUT [0 ] 0
|
||||
NO_B_X UnblockS [0 ] 0
|
||||
NO_B_X UnblockM [0 ] 0
|
||||
NO_B_X Pf_Replacement [0 ] 0
|
||||
NO_B_X DMA_READ [0 ] 0
|
||||
NO_B_X DMA_WRITE [0 ] 0
|
||||
NO_B_X GETF [0 ] 0
|
||||
|
||||
NO_B_S GETX [0 ] 0
|
||||
NO_B_S GETS [0 ] 0
|
||||
NO_B_S PUT [0 ] 0
|
||||
NO_B_S UnblockS [0 ] 0
|
||||
NO_B_S UnblockM [0 ] 0
|
||||
NO_B_S Pf_Replacement [0 ] 0
|
||||
NO_B_S DMA_READ [0 ] 0
|
||||
NO_B_S DMA_WRITE [0 ] 0
|
||||
NO_B_S GETF [0 ] 0
|
||||
|
||||
NO_B_S_W GETX [0 ] 0
|
||||
NO_B_S_W GETS [0 ] 0
|
||||
NO_B_S_W PUT [0 ] 0
|
||||
NO_B_S_W UnblockS [0 ] 0
|
||||
NO_B_S_W Pf_Replacement [0 ] 0
|
||||
NO_B_S_W DMA_READ [0 ] 0
|
||||
NO_B_S_W DMA_WRITE [0 ] 0
|
||||
NO_B_S_W All_Unblocks [0 ] 0
|
||||
NO_B_S_W GETF [0 ] 0
|
||||
|
||||
O_B GETX [0 ] 0
|
||||
O_B GETS [0 ] 0
|
||||
O_B PUT [0 ] 0
|
||||
O_B UnblockS [0 ] 0
|
||||
O_B UnblockM [0 ] 0
|
||||
O_B Pf_Replacement [0 ] 0
|
||||
O_B DMA_READ [0 ] 0
|
||||
O_B DMA_WRITE [0 ] 0
|
||||
O_B GETF [0 ] 0
|
||||
|
||||
NO_B_W GETX [0 ] 0
|
||||
NO_B_W GETS [0 ] 0
|
||||
NO_B_W PUT [0 ] 0
|
||||
NO_B_W UnblockS [0 ] 0
|
||||
NO_B_W UnblockM [0 ] 0
|
||||
NO_B_W Pf_Replacement [0 ] 0
|
||||
NO_B_W DMA_READ [0 ] 0
|
||||
NO_B_W DMA_WRITE [0 ] 0
|
||||
NO_B_W Memory_Data [1159 ] 1159
|
||||
NO_B_W GETF [0 ] 0
|
||||
|
||||
O_B_W GETX [0 ] 0
|
||||
O_B_W GETS [0 ] 0
|
||||
O_B_W PUT [0 ] 0
|
||||
O_B_W UnblockS [0 ] 0
|
||||
O_B_W Pf_Replacement [0 ] 0
|
||||
O_B_W DMA_READ [0 ] 0
|
||||
O_B_W DMA_WRITE [0 ] 0
|
||||
O_B_W Memory_Data [0 ] 0
|
||||
O_B_W GETF [0 ] 0
|
||||
|
||||
NO_W GETX [0 ] 0
|
||||
NO_W GETS [0 ] 0
|
||||
NO_W PUT [0 ] 0
|
||||
NO_W Pf_Replacement [0 ] 0
|
||||
NO_W DMA_READ [0 ] 0
|
||||
NO_W DMA_WRITE [0 ] 0
|
||||
NO_W Memory_Data [0 ] 0
|
||||
NO_W GETF [0 ] 0
|
||||
|
||||
O_W GETX [0 ] 0
|
||||
O_W GETS [0 ] 0
|
||||
O_W PUT [0 ] 0
|
||||
O_W Pf_Replacement [0 ] 0
|
||||
O_W DMA_READ [0 ] 0
|
||||
O_W DMA_WRITE [0 ] 0
|
||||
O_W Memory_Data [0 ] 0
|
||||
O_W GETF [0 ] 0
|
||||
|
||||
NO_DW_B_W GETX [0 ] 0
|
||||
NO_DW_B_W GETS [0 ] 0
|
||||
NO_DW_B_W PUT [0 ] 0
|
||||
NO_DW_B_W Pf_Replacement [0 ] 0
|
||||
NO_DW_B_W DMA_READ [0 ] 0
|
||||
NO_DW_B_W DMA_WRITE [0 ] 0
|
||||
NO_DW_B_W Ack [0 ] 0
|
||||
NO_DW_B_W Data [0 ] 0
|
||||
NO_DW_B_W Exclusive_Data [0 ] 0
|
||||
NO_DW_B_W All_acks_and_data_no_sharers [0 ] 0
|
||||
NO_DW_B_W GETF [0 ] 0
|
||||
|
||||
NO_DR_B_W GETX [0 ] 0
|
||||
NO_DR_B_W GETS [0 ] 0
|
||||
NO_DR_B_W PUT [0 ] 0
|
||||
NO_DR_B_W Pf_Replacement [0 ] 0
|
||||
NO_DR_B_W DMA_READ [0 ] 0
|
||||
NO_DR_B_W DMA_WRITE [0 ] 0
|
||||
NO_DR_B_W Memory_Data [0 ] 0
|
||||
NO_DR_B_W Ack [0 ] 0
|
||||
NO_DR_B_W Shared_Ack [0 ] 0
|
||||
NO_DR_B_W Shared_Data [0 ] 0
|
||||
NO_DR_B_W Data [0 ] 0
|
||||
NO_DR_B_W Exclusive_Data [0 ] 0
|
||||
NO_DR_B_W GETF [0 ] 0
|
||||
|
||||
NO_DR_B_D GETX [0 ] 0
|
||||
NO_DR_B_D GETS [0 ] 0
|
||||
NO_DR_B_D PUT [0 ] 0
|
||||
NO_DR_B_D Pf_Replacement [0 ] 0
|
||||
NO_DR_B_D DMA_READ [0 ] 0
|
||||
NO_DR_B_D DMA_WRITE [0 ] 0
|
||||
NO_DR_B_D Ack [0 ] 0
|
||||
NO_DR_B_D Shared_Ack [0 ] 0
|
||||
NO_DR_B_D Shared_Data [0 ] 0
|
||||
NO_DR_B_D Data [0 ] 0
|
||||
NO_DR_B_D Exclusive_Data [0 ] 0
|
||||
NO_DR_B_D All_acks_and_shared_data [0 ] 0
|
||||
NO_DR_B_D All_acks_and_owner_data [0 ] 0
|
||||
NO_DR_B_D All_acks_and_data_no_sharers [0 ] 0
|
||||
NO_DR_B_D GETF [0 ] 0
|
||||
|
||||
NO_DR_B GETX [0 ] 0
|
||||
NO_DR_B GETS [0 ] 0
|
||||
NO_DR_B PUT [0 ] 0
|
||||
NO_DR_B Pf_Replacement [0 ] 0
|
||||
NO_DR_B DMA_READ [0 ] 0
|
||||
NO_DR_B DMA_WRITE [0 ] 0
|
||||
NO_DR_B Ack [0 ] 0
|
||||
NO_DR_B Shared_Ack [0 ] 0
|
||||
NO_DR_B Shared_Data [0 ] 0
|
||||
NO_DR_B Data [0 ] 0
|
||||
NO_DR_B Exclusive_Data [0 ] 0
|
||||
NO_DR_B All_acks_and_shared_data [0 ] 0
|
||||
NO_DR_B All_acks_and_owner_data [0 ] 0
|
||||
NO_DR_B All_acks_and_data_no_sharers [0 ] 0
|
||||
NO_DR_B GETF [0 ] 0
|
||||
|
||||
NO_DW_W GETX [0 ] 0
|
||||
NO_DW_W GETS [0 ] 0
|
||||
NO_DW_W PUT [0 ] 0
|
||||
NO_DW_W Pf_Replacement [0 ] 0
|
||||
NO_DW_W DMA_READ [0 ] 0
|
||||
NO_DW_W DMA_WRITE [0 ] 0
|
||||
NO_DW_W Memory_Ack [0 ] 0
|
||||
NO_DW_W GETF [0 ] 0
|
||||
|
||||
O_DR_B_W GETX [0 ] 0
|
||||
O_DR_B_W GETS [0 ] 0
|
||||
O_DR_B_W PUT [0 ] 0
|
||||
O_DR_B_W Pf_Replacement [0 ] 0
|
||||
O_DR_B_W DMA_READ [0 ] 0
|
||||
O_DR_B_W DMA_WRITE [0 ] 0
|
||||
O_DR_B_W Memory_Data [0 ] 0
|
||||
O_DR_B_W Ack [0 ] 0
|
||||
O_DR_B_W Shared_Ack [0 ] 0
|
||||
O_DR_B_W GETF [0 ] 0
|
||||
|
||||
O_DR_B GETX [0 ] 0
|
||||
O_DR_B GETS [0 ] 0
|
||||
O_DR_B PUT [0 ] 0
|
||||
O_DR_B Pf_Replacement [0 ] 0
|
||||
O_DR_B DMA_READ [0 ] 0
|
||||
O_DR_B DMA_WRITE [0 ] 0
|
||||
O_DR_B Ack [0 ] 0
|
||||
O_DR_B Shared_Ack [0 ] 0
|
||||
O_DR_B All_acks_and_owner_data [0 ] 0
|
||||
O_DR_B All_acks_and_data_no_sharers [0 ] 0
|
||||
O_DR_B GETF [0 ] 0
|
||||
|
||||
WB GETX [27 ] 27
|
||||
WB GETS [19 ] 19
|
||||
WB PUT [0 ] 0
|
||||
WB Unblock [0 ] 0
|
||||
WB Writeback_Clean [0 ] 0
|
||||
WB Writeback_Dirty [0 ] 0
|
||||
WB Writeback_Exclusive_Clean [923 ] 923
|
||||
WB Writeback_Exclusive_Dirty [220 ] 220
|
||||
WB Pf_Replacement [0 ] 0
|
||||
WB DMA_READ [0 ] 0
|
||||
WB DMA_WRITE [0 ] 0
|
||||
WB GETF [0 ] 0
|
||||
|
||||
WB_O_W GETX [0 ] 0
|
||||
WB_O_W GETS [0 ] 0
|
||||
WB_O_W PUT [0 ] 0
|
||||
WB_O_W Pf_Replacement [0 ] 0
|
||||
WB_O_W DMA_READ [0 ] 0
|
||||
WB_O_W DMA_WRITE [0 ] 0
|
||||
WB_O_W Memory_Ack [0 ] 0
|
||||
WB_O_W GETF [0 ] 0
|
||||
|
||||
WB_E_W GETX [4 ] 4
|
||||
WB_E_W GETS [7 ] 7
|
||||
WB_E_W PUT [0 ] 0
|
||||
WB_E_W Pf_Replacement [0 ] 0
|
||||
WB_E_W DMA_READ [0 ] 0
|
||||
WB_E_W DMA_WRITE [0 ] 0
|
||||
WB_E_W Memory_Ack [220 ] 220
|
||||
WB_E_W GETF [0 ] 0
|
||||
|
||||
NO_F GETX [0 ] 0
|
||||
NO_F GETS [0 ] 0
|
||||
NO_F PUT [0 ] 0
|
||||
NO_F UnblockM [0 ] 0
|
||||
NO_F Pf_Replacement [0 ] 0
|
||||
NO_F GETF [0 ] 0
|
||||
NO_F PUTF [0 ] 0
|
||||
|
||||
NO_F_W GETX [0 ] 0
|
||||
NO_F_W GETS [0 ] 0
|
||||
NO_F_W PUT [0 ] 0
|
||||
NO_F_W Pf_Replacement [0 ] 0
|
||||
NO_F_W DMA_READ [0 ] 0
|
||||
NO_F_W DMA_WRITE [0 ] 0
|
||||
NO_F_W Memory_Data [0 ] 0
|
||||
NO_F_W GETF [0 ] 0
|
||||
|
||||
@ -0,0 +1,2 @@
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
hack: be nice to actually delete the event here
|
||||
@ -0,0 +1,12 @@
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jun 4 2012 11:51:44
|
||||
gem5 started Jun 4 2012 13:41:27
|
||||
gem5 executing on zizzer
|
||||
command line: build/ALPHA_MOESI_hammer/gem5.opt -d build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer -re tests/run.py build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
Hello world!
|
||||
Exiting @ tick 208400 because target called exit()
|
||||
@ -0,0 +1,92 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000208 # Number of seconds simulated
|
||||
sim_ticks 208400 # Number of ticks simulated
|
||||
final_tick 208400 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 52133 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 52125 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1696034 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 224184 # Number of bytes of host memory used
|
||||
host_seconds 0.12 # Real time elapsed on the host
|
||||
sim_insts 6404 # Number of instructions simulated
|
||||
sim_ops 6404 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 25656 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 8804 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 34460 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 25656 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 25656 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::cpu.data 6696 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 6696 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 6414 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 1185 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 7599 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::cpu.data 865 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 865 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 123109405 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 42245681 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 165355086 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 123109405 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 123109405 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::cpu.data 32130518 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 32130518 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 123109405 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 74376200 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 197485605 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
||||
system.cpu.dtb.read_hits 1185 # DTB read hits
|
||||
system.cpu.dtb.read_misses 7 # DTB read misses
|
||||
system.cpu.dtb.read_acv 0 # DTB read access violations
|
||||
system.cpu.dtb.read_accesses 1192 # DTB read accesses
|
||||
system.cpu.dtb.write_hits 865 # DTB write hits
|
||||
system.cpu.dtb.write_misses 3 # DTB write misses
|
||||
system.cpu.dtb.write_acv 0 # DTB write access violations
|
||||
system.cpu.dtb.write_accesses 868 # DTB write accesses
|
||||
system.cpu.dtb.data_hits 2050 # DTB hits
|
||||
system.cpu.dtb.data_misses 10 # DTB misses
|
||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
||||
system.cpu.dtb.data_accesses 2060 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 6415 # ITB hits
|
||||
system.cpu.itb.fetch_misses 17 # ITB misses
|
||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
||||
system.cpu.itb.fetch_accesses 6432 # ITB accesses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.itb.write_hits 0 # DTB write hits
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.itb.write_acv 0 # DTB write access violations
|
||||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.itb.data_hits 0 # DTB hits
|
||||
system.cpu.itb.data_misses 0 # DTB misses
|
||||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 17 # Number of system calls
|
||||
system.cpu.numCycles 208400 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 6404 # Number of instructions committed
|
||||
system.cpu.committedOps 6404 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 6331 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 251 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 750 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 6331 # number of integer instructions
|
||||
system.cpu.num_fp_insts 10 # number of float instructions
|
||||
system.cpu.num_int_register_reads 8304 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 4581 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 8 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 2 # number of times the floating registers were written
|
||||
system.cpu.num_mem_refs 2060 # number of memory refs
|
||||
system.cpu.num_load_insts 1192 # Number of load instructions
|
||||
system.cpu.num_store_insts 868 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 208400 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
@ -0,0 +1,284 @@
|
||||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
full_system=false
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000
|
||||
time_sync_spin_threshold=100000
|
||||
|
||||
[system]
|
||||
type=System
|
||||
children=cpu dir_cntrl0 l1_cntrl0 physmem ruby sys_port_proxy
|
||||
boot_osflags=a
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
mem_mode=timing
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
readfile=
|
||||
symbolfile=
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.sys_port_proxy.slave[0]
|
||||
|
||||
[system.cpu]
|
||||
type=TimingSimpleCPU
|
||||
children=dtb interrupts itb tracer workload
|
||||
checker=Null
|
||||
clock=1
|
||||
cpu_id=0
|
||||
defer_registration=false
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
interrupts=system.cpu.interrupts
|
||||
itb=system.cpu.itb
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
phase=0
|
||||
profile=0
|
||||
progress_interval=0
|
||||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
workload=system.cpu.workload
|
||||
dcache_port=system.l1_cntrl0.sequencer.slave[1]
|
||||
icache_port=system.l1_cntrl0.sequencer.slave[0]
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=AlphaTLB
|
||||
size=64
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=AlphaInterrupts
|
||||
|
||||
[system.cpu.itb]
|
||||
type=AlphaTLB
|
||||
size=48
|
||||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
|
||||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=hello
|
||||
cwd=
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
ppid=99
|
||||
simpoint=0
|
||||
system=system
|
||||
uid=100
|
||||
|
||||
[system.dir_cntrl0]
|
||||
type=Directory_Controller
|
||||
children=directory memBuffer
|
||||
buffer_size=0
|
||||
cntrl_id=1
|
||||
directory=system.dir_cntrl0.directory
|
||||
directory_latency=12
|
||||
memBuffer=system.dir_cntrl0.memBuffer
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
ruby_system=system.ruby
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.dir_cntrl0.directory]
|
||||
type=RubyDirectoryMemory
|
||||
map_levels=4
|
||||
numa_high_bit=6
|
||||
size=134217728
|
||||
use_map=false
|
||||
version=0
|
||||
|
||||
[system.dir_cntrl0.memBuffer]
|
||||
type=RubyMemoryControl
|
||||
bank_bit_0=8
|
||||
bank_busy_time=11
|
||||
bank_queue_size=12
|
||||
banks_per_rank=8
|
||||
basic_bus_busy_time=2
|
||||
dimm_bit_0=12
|
||||
dimms_per_channel=2
|
||||
mem_bus_cycle_multiplier=10
|
||||
mem_ctl_latency=12
|
||||
mem_fixed_delay=0
|
||||
mem_random_arbitrate=0
|
||||
rank_bit_0=11
|
||||
rank_rank_delay=1
|
||||
ranks_per_dimm=2
|
||||
read_write_delay=2
|
||||
refresh_period=1560
|
||||
tFaw=0
|
||||
version=0
|
||||
|
||||
[system.l1_cntrl0]
|
||||
type=L1Cache_Controller
|
||||
children=cacheMemory sequencer
|
||||
buffer_size=0
|
||||
cacheMemory=system.l1_cntrl0.cacheMemory
|
||||
cache_response_latency=12
|
||||
cntrl_id=0
|
||||
issue_latency=2
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
ruby_system=system.ruby
|
||||
send_evictions=false
|
||||
sequencer=system.l1_cntrl0.sequencer
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.l1_cntrl0.cacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
is_icache=false
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl0.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=true
|
||||
dcache=system.l1_cntrl0.cacheMemory
|
||||
deadlock_threshold=500000
|
||||
icache=system.l1_cntrl0.cacheMemory
|
||||
max_outstanding_requests=16
|
||||
ruby_system=system.ruby
|
||||
support_data_reqs=true
|
||||
support_inst_reqs=true
|
||||
system=system
|
||||
using_network_tester=false
|
||||
using_ruby_tester=false
|
||||
version=0
|
||||
slave=system.cpu.icache_port system.cpu.dcache_port
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=30
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
|
||||
[system.ruby]
|
||||
type=RubySystem
|
||||
children=network profiler
|
||||
block_size_bytes=64
|
||||
clock=1
|
||||
mem_size=134217728
|
||||
no_mem_vec=false
|
||||
random_seed=1234
|
||||
randomization=false
|
||||
stats_filename=ruby.stats
|
||||
|
||||
[system.ruby.network]
|
||||
type=SimpleNetwork
|
||||
children=topology
|
||||
adaptive_routing=false
|
||||
buffer_size=0
|
||||
control_msg_size=8
|
||||
endpoint_bandwidth=1000
|
||||
number_of_virtual_networks=10
|
||||
ruby_system=system.ruby
|
||||
topology=system.ruby.network.topology
|
||||
|
||||
[system.ruby.network.topology]
|
||||
type=Topology
|
||||
children=ext_links0 ext_links1 int_links0 int_links1 routers0 routers1 routers2
|
||||
description=Crossbar
|
||||
ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1
|
||||
int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1
|
||||
print_config=false
|
||||
routers=system.ruby.network.topology.routers0 system.ruby.network.topology.routers1 system.ruby.network.topology.routers2
|
||||
|
||||
[system.ruby.network.topology.ext_links0]
|
||||
type=SimpleExtLink
|
||||
bandwidth_factor=16
|
||||
ext_node=system.l1_cntrl0
|
||||
int_node=system.ruby.network.topology.routers0
|
||||
latency=1
|
||||
link_id=0
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links1]
|
||||
type=SimpleExtLink
|
||||
bandwidth_factor=16
|
||||
ext_node=system.dir_cntrl0
|
||||
int_node=system.ruby.network.topology.routers1
|
||||
latency=1
|
||||
link_id=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.int_links0]
|
||||
type=SimpleIntLink
|
||||
bandwidth_factor=16
|
||||
latency=1
|
||||
link_id=2
|
||||
node_a=system.ruby.network.topology.routers0
|
||||
node_b=system.ruby.network.topology.routers2
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.int_links1]
|
||||
type=SimpleIntLink
|
||||
bandwidth_factor=16
|
||||
latency=1
|
||||
link_id=3
|
||||
node_a=system.ruby.network.topology.routers1
|
||||
node_b=system.ruby.network.topology.routers2
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.routers0]
|
||||
type=BasicRouter
|
||||
router_id=0
|
||||
|
||||
[system.ruby.network.topology.routers1]
|
||||
type=BasicRouter
|
||||
router_id=1
|
||||
|
||||
[system.ruby.network.topology.routers2]
|
||||
type=BasicRouter
|
||||
router_id=2
|
||||
|
||||
[system.ruby.profiler]
|
||||
type=RubyProfiler
|
||||
all_instructions=false
|
||||
hot_lines=false
|
||||
num_of_sequencers=1
|
||||
ruby_system=system.ruby
|
||||
|
||||
[system.sys_port_proxy]
|
||||
type=RubyPortProxy
|
||||
access_phys_mem=true
|
||||
ruby_system=system.ruby
|
||||
support_data_reqs=true
|
||||
support_inst_reqs=true
|
||||
system=system
|
||||
using_network_tester=false
|
||||
using_ruby_tester=false
|
||||
version=0
|
||||
slave=system.system_port
|
||||
|
||||
@ -0,0 +1,311 @@
|
||||
|
||||
================ Begin RubySystem Configuration Print ================
|
||||
|
||||
RubySystem config:
|
||||
random_seed: 1234
|
||||
randomization: 0
|
||||
cycle_period: 1
|
||||
block_size_bytes: 64
|
||||
block_size_bits: 6
|
||||
memory_size_bytes: 134217728
|
||||
memory_size_bits: 27
|
||||
|
||||
Network Configuration
|
||||
---------------------
|
||||
network: SIMPLE_NETWORK
|
||||
topology:
|
||||
|
||||
virtual_net_0: active, ordered
|
||||
virtual_net_1: active, ordered
|
||||
virtual_net_2: active, ordered
|
||||
virtual_net_3: active, ordered
|
||||
virtual_net_4: active, ordered
|
||||
virtual_net_5: inactive
|
||||
virtual_net_6: inactive
|
||||
virtual_net_7: inactive
|
||||
virtual_net_8: inactive
|
||||
virtual_net_9: inactive
|
||||
|
||||
|
||||
Profiler Configuration
|
||||
----------------------
|
||||
periodic_stats_period: 1000000
|
||||
|
||||
================ End RubySystem Configuration Print ================
|
||||
|
||||
|
||||
Real time: Jun/04/2012 13:42:47
|
||||
|
||||
Profiler Stats
|
||||
--------------
|
||||
Elapsed_time_in_seconds: 0
|
||||
Elapsed_time_in_minutes: 0
|
||||
Elapsed_time_in_hours: 0
|
||||
Elapsed_time_in_days: 0
|
||||
|
||||
Virtual_time_in_seconds: 0.35
|
||||
Virtual_time_in_minutes: 0.00583333
|
||||
Virtual_time_in_hours: 9.72222e-05
|
||||
Virtual_time_in_days: 4.05093e-06
|
||||
|
||||
Ruby_current_time: 342698
|
||||
Ruby_start_time: 0
|
||||
Ruby_cycles: 342698
|
||||
|
||||
mbytes_resident: 48.4648
|
||||
mbytes_total: 219.84
|
||||
resident_ratio: 0.220455
|
||||
|
||||
ruby_cycles_executed: [ 342699 ]
|
||||
|
||||
Busy Controller Counts:
|
||||
L1Cache-0:0
|
||||
Directory-0:0
|
||||
|
||||
|
||||
Busy Bank Count:0
|
||||
|
||||
sequencer_requests_outstanding: [binsize: 1 max: 1 count: 8465 average: 1 | standard deviation: 0 | 0 8465 ]
|
||||
|
||||
All Non-Zero Cycle Demand Cache Accesses
|
||||
----------------------------------------
|
||||
miss_latency: [binsize: 2 max: 377 count: 8464 average: 39.4889 | standard deviation: 72.9776 | 0 6734 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 6 1 3 6 0 334 211 182 529 243 4 4 0 5 2 15 9 4 14 10 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 30 18 15 24 37 2 3 0 0 2 2 1 1 3 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 ]
|
||||
miss_latency_LD: [binsize: 2 max: 375 count: 1185 average: 110.608 | standard deviation: 87.0282 | 0 458 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 3 0 1 2 0 147 90 74 255 81 2 1 0 3 0 12 3 1 9 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 4 2 11 4 0 2 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_ST: [binsize: 2 max: 377 count: 865 average: 62.2439 | standard deviation: 89.6671 | 0 592 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 32 30 31 54 70 0 0 0 1 0 1 0 2 2 4 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 5 8 3 21 0 0 0 0 0 0 0 1 2 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 ]
|
||||
miss_latency_IFETCH: [binsize: 2 max: 285 count: 6414 average: 23.2806 | standard deviation: 57.2661 | 0 5684 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 3 1 2 4 0 155 91 77 220 92 2 3 0 1 2 2 6 1 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 20 9 5 10 12 2 1 0 0 1 2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_L1Cache: [binsize: 1 max: 3 count: 6734 average: 3 | standard deviation: 0 | 0 0 0 6734 ]
|
||||
miss_latency_Directory: [binsize: 2 max: 377 count: 1730 average: 181.521 | standard deviation: 26.4115 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 6 1 3 6 0 334 211 182 529 243 4 4 0 5 2 15 9 4 14 10 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 30 18 15 24 37 2 3 0 0 2 2 1 1 3 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 ]
|
||||
miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
imcomplete_wCC_Times: 0
|
||||
miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ]
|
||||
miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ]
|
||||
miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ]
|
||||
miss_latency_dir_first_response_to_completion: [binsize: 1 max: 159 count: 1 average: 159 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
|
||||
imcomplete_dir_Times: 1729
|
||||
miss_latency_LD_L1Cache: [binsize: 1 max: 3 count: 458 average: 3 | standard deviation: 0 | 0 0 0 458 ]
|
||||
miss_latency_LD_Directory: [binsize: 2 max: 375 count: 727 average: 178.4 | standard deviation: 21.0913 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 3 0 1 2 0 147 90 74 255 81 2 1 0 3 0 12 3 1 9 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 4 2 11 4 0 2 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_ST_L1Cache: [binsize: 1 max: 3 count: 592 average: 3 | standard deviation: 0 | 0 0 0 592 ]
|
||||
miss_latency_ST_Directory: [binsize: 2 max: 377 count: 273 average: 190.714 | standard deviation: 36.5384 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 32 30 31 54 70 0 0 0 1 0 1 0 2 2 4 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 5 8 3 21 0 0 0 0 0 0 0 1 2 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 ]
|
||||
miss_latency_IFETCH_L1Cache: [binsize: 1 max: 3 count: 5684 average: 3 | standard deviation: 0 | 0 0 0 5684 ]
|
||||
miss_latency_IFETCH_Directory: [binsize: 2 max: 285 count: 730 average: 181.192 | standard deviation: 25.9199 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 3 1 2 4 0 155 91 77 220 92 2 3 0 1 2 2 6 1 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 20 9 5 10 12 2 1 0 0 1 2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
|
||||
All Non-Zero Cycle SW Prefetch Requests
|
||||
------------------------------------
|
||||
prefetch_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
prefetch_latency_L2Miss:[binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
Request vs. RubySystem State Profile
|
||||
--------------------------------
|
||||
|
||||
|
||||
filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
||||
Message Delayed Cycles
|
||||
----------------------
|
||||
Total_delay_cycles: [binsize: 1 max: 0 count: 3456 average: 0 | standard deviation: 0 | 3456 ]
|
||||
Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 3456 average: 0 | standard deviation: 0 | 3456 ]
|
||||
virtual_network_0_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 1730 average: 0 | standard deviation: 0 | 1730 ]
|
||||
virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 1726 average: 0 | standard deviation: 0 | 1726 ]
|
||||
virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_6_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_7_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_8_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_9_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
||||
Resource Usage
|
||||
--------------
|
||||
page_size: 4096
|
||||
user_time: 0
|
||||
system_time: 0
|
||||
page_reclaims: 12835
|
||||
page_faults: 0
|
||||
swaps: 0
|
||||
block_inputs: 0
|
||||
block_outputs: 88
|
||||
|
||||
Network Stats
|
||||
-------------
|
||||
|
||||
total_msg_count_Control: 5190 41520
|
||||
total_msg_count_Data: 5178 372816
|
||||
total_msg_count_Response_Data: 5190 373680
|
||||
total_msg_count_Writeback_Control: 5178 41424
|
||||
total_msgs: 20736 total_bytes: 829440
|
||||
|
||||
switch_0_inlinks: 2
|
||||
switch_0_outlinks: 2
|
||||
links_utilized_percent_switch_0: 2.52117
|
||||
links_utilized_percent_switch_0_link_0: 2.5235 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_0_link_1: 2.51884 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_0_link_0_Response_Data: 1730 124560 [ 0 0 0 0 1730 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Writeback_Control: 1726 13808 [ 0 0 0 1726 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Control: 1730 13840 [ 0 0 1730 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Data: 1726 124272 [ 0 0 1726 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_1_inlinks: 2
|
||||
switch_1_outlinks: 2
|
||||
links_utilized_percent_switch_1: 2.52117
|
||||
links_utilized_percent_switch_1_link_0: 2.51884 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_1_link_1: 2.5235 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_1_link_0_Control: 1730 13840 [ 0 0 1730 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Data: 1726 124272 [ 0 0 1726 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Response_Data: 1730 124560 [ 0 0 0 0 1730 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Writeback_Control: 1726 13808 [ 0 0 0 1726 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_2_inlinks: 2
|
||||
switch_2_outlinks: 2
|
||||
links_utilized_percent_switch_2: 2.52117
|
||||
links_utilized_percent_switch_2_link_0: 2.5235 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_2_link_1: 2.51884 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_2_link_0_Response_Data: 1730 124560 [ 0 0 0 0 1730 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Writeback_Control: 1726 13808 [ 0 0 0 1726 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Control: 1730 13840 [ 0 0 1730 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Data: 1726 124272 [ 0 0 1726 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
Cache Stats: system.l1_cntrl0.cacheMemory
|
||||
system.l1_cntrl0.cacheMemory_total_misses: 1730
|
||||
system.l1_cntrl0.cacheMemory_total_demand_misses: 1730
|
||||
system.l1_cntrl0.cacheMemory_total_prefetches: 0
|
||||
system.l1_cntrl0.cacheMemory_total_sw_prefetches: 0
|
||||
system.l1_cntrl0.cacheMemory_total_hw_prefetches: 0
|
||||
|
||||
system.l1_cntrl0.cacheMemory_request_type_LD: 42.0231%
|
||||
system.l1_cntrl0.cacheMemory_request_type_ST: 15.7803%
|
||||
system.l1_cntrl0.cacheMemory_request_type_IFETCH: 42.1965%
|
||||
|
||||
system.l1_cntrl0.cacheMemory_access_mode_type_Supervisor: 1730 100%
|
||||
|
||||
--- L1Cache ---
|
||||
- Event Counts -
|
||||
Load [1185 ] 1185
|
||||
Ifetch [6414 ] 6414
|
||||
Store [865 ] 865
|
||||
Data [1730 ] 1730
|
||||
Fwd_GETX [0 ] 0
|
||||
Inv [0 ] 0
|
||||
Replacement [1726 ] 1726
|
||||
Writeback_Ack [1726 ] 1726
|
||||
Writeback_Nack [0 ] 0
|
||||
|
||||
- Transitions -
|
||||
I Load [727 ] 727
|
||||
I Ifetch [730 ] 730
|
||||
I Store [273 ] 273
|
||||
I Inv [0 ] 0
|
||||
I Replacement [0 ] 0
|
||||
|
||||
II Writeback_Nack [0 ] 0
|
||||
|
||||
M Load [458 ] 458
|
||||
M Ifetch [5684 ] 5684
|
||||
M Store [592 ] 592
|
||||
M Fwd_GETX [0 ] 0
|
||||
M Inv [0 ] 0
|
||||
M Replacement [1726 ] 1726
|
||||
|
||||
MI Fwd_GETX [0 ] 0
|
||||
MI Inv [0 ] 0
|
||||
MI Writeback_Ack [1726 ] 1726
|
||||
MI Writeback_Nack [0 ] 0
|
||||
|
||||
MII Fwd_GETX [0 ] 0
|
||||
|
||||
IS Data [1457 ] 1457
|
||||
|
||||
IM Data [273 ] 273
|
||||
|
||||
Memory controller: system.dir_cntrl0.memBuffer:
|
||||
memory_total_requests: 3456
|
||||
memory_reads: 1730
|
||||
memory_writes: 1726
|
||||
memory_refreshes: 714
|
||||
memory_total_request_delays: 4411
|
||||
memory_delays_per_request: 1.27633
|
||||
memory_delays_in_input_queue: 1083
|
||||
memory_delays_behind_head_of_bank_queue: 8
|
||||
memory_delays_stalled_at_head_of_bank_queue: 3320
|
||||
memory_stalls_for_bank_busy: 1509
|
||||
memory_stalls_for_random_busy: 0
|
||||
memory_stalls_for_anti_starvation: 0
|
||||
memory_stalls_for_arbitration: 99
|
||||
memory_stalls_for_bus: 1677
|
||||
memory_stalls_for_tfaw: 0
|
||||
memory_stalls_for_read_write_turnaround: 35
|
||||
memory_stalls_for_read_read_turnaround: 0
|
||||
accesses_per_bank: 162 36 92 110 106 362 98 36 32 34 83 92 110 104 84 86 83 53 50 58 64 124 212 72 66 50 122 190 220 325 42 98
|
||||
|
||||
--- Directory ---
|
||||
- Event Counts -
|
||||
GETX [1730 ] 1730
|
||||
GETS [0 ] 0
|
||||
PUTX [1726 ] 1726
|
||||
PUTX_NotOwner [0 ] 0
|
||||
DMA_READ [0 ] 0
|
||||
DMA_WRITE [0 ] 0
|
||||
Memory_Data [1730 ] 1730
|
||||
Memory_Ack [1726 ] 1726
|
||||
|
||||
- Transitions -
|
||||
I GETX [1730 ] 1730
|
||||
I PUTX_NotOwner [0 ] 0
|
||||
I DMA_READ [0 ] 0
|
||||
I DMA_WRITE [0 ] 0
|
||||
|
||||
M GETX [0 ] 0
|
||||
M PUTX [1726 ] 1726
|
||||
M PUTX_NotOwner [0 ] 0
|
||||
M DMA_READ [0 ] 0
|
||||
M DMA_WRITE [0 ] 0
|
||||
|
||||
M_DRD GETX [0 ] 0
|
||||
M_DRD PUTX [0 ] 0
|
||||
|
||||
M_DWR GETX [0 ] 0
|
||||
M_DWR PUTX [0 ] 0
|
||||
|
||||
M_DWRI GETX [0 ] 0
|
||||
M_DWRI Memory_Ack [0 ] 0
|
||||
|
||||
M_DRDI GETX [0 ] 0
|
||||
M_DRDI Memory_Ack [0 ] 0
|
||||
|
||||
IM GETX [0 ] 0
|
||||
IM GETS [0 ] 0
|
||||
IM PUTX [0 ] 0
|
||||
IM PUTX_NotOwner [0 ] 0
|
||||
IM DMA_READ [0 ] 0
|
||||
IM DMA_WRITE [0 ] 0
|
||||
IM Memory_Data [1730 ] 1730
|
||||
|
||||
MI GETX [0 ] 0
|
||||
MI GETS [0 ] 0
|
||||
MI PUTX [0 ] 0
|
||||
MI PUTX_NotOwner [0 ] 0
|
||||
MI DMA_READ [0 ] 0
|
||||
MI DMA_WRITE [0 ] 0
|
||||
MI Memory_Ack [1726 ] 1726
|
||||
|
||||
ID GETX [0 ] 0
|
||||
ID GETS [0 ] 0
|
||||
ID PUTX [0 ] 0
|
||||
ID PUTX_NotOwner [0 ] 0
|
||||
ID DMA_READ [0 ] 0
|
||||
ID DMA_WRITE [0 ] 0
|
||||
ID Memory_Data [0 ] 0
|
||||
|
||||
ID_W GETX [0 ] 0
|
||||
ID_W GETS [0 ] 0
|
||||
ID_W PUTX [0 ] 0
|
||||
ID_W PUTX_NotOwner [0 ] 0
|
||||
ID_W DMA_READ [0 ] 0
|
||||
ID_W DMA_WRITE [0 ] 0
|
||||
ID_W Memory_Ack [0 ] 0
|
||||
|
||||
@ -0,0 +1,2 @@
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
hack: be nice to actually delete the event here
|
||||
@ -0,0 +1,12 @@
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jun 4 2012 11:50:11
|
||||
gem5 started Jun 4 2012 13:42:46
|
||||
gem5 executing on zizzer
|
||||
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
Hello world!
|
||||
Exiting @ tick 342698 because target called exit()
|
||||
@ -0,0 +1,92 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000343 # Number of seconds simulated
|
||||
sim_ticks 342698 # Number of ticks simulated
|
||||
final_tick 342698 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 17946 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 17945 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 960252 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 225120 # Number of bytes of host memory used
|
||||
host_seconds 0.36 # Real time elapsed on the host
|
||||
sim_insts 6404 # Number of instructions simulated
|
||||
sim_ops 6404 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 25656 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 8804 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 34460 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 25656 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 25656 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::cpu.data 6696 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 6696 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 6414 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 1185 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 7599 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::cpu.data 865 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 865 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 74864750 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 25690258 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 100555008 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 74864750 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 74864750 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::cpu.data 19539069 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 19539069 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 74864750 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 45229327 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 120094077 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
||||
system.cpu.dtb.read_hits 1185 # DTB read hits
|
||||
system.cpu.dtb.read_misses 7 # DTB read misses
|
||||
system.cpu.dtb.read_acv 0 # DTB read access violations
|
||||
system.cpu.dtb.read_accesses 1192 # DTB read accesses
|
||||
system.cpu.dtb.write_hits 865 # DTB write hits
|
||||
system.cpu.dtb.write_misses 3 # DTB write misses
|
||||
system.cpu.dtb.write_acv 0 # DTB write access violations
|
||||
system.cpu.dtb.write_accesses 868 # DTB write accesses
|
||||
system.cpu.dtb.data_hits 2050 # DTB hits
|
||||
system.cpu.dtb.data_misses 10 # DTB misses
|
||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
||||
system.cpu.dtb.data_accesses 2060 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 6415 # ITB hits
|
||||
system.cpu.itb.fetch_misses 17 # ITB misses
|
||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
||||
system.cpu.itb.fetch_accesses 6432 # ITB accesses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.itb.write_hits 0 # DTB write hits
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.itb.write_acv 0 # DTB write access violations
|
||||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.itb.data_hits 0 # DTB hits
|
||||
system.cpu.itb.data_misses 0 # DTB misses
|
||||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 17 # Number of system calls
|
||||
system.cpu.numCycles 342698 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 6404 # Number of instructions committed
|
||||
system.cpu.committedOps 6404 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 6331 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 251 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 750 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 6331 # number of integer instructions
|
||||
system.cpu.num_fp_insts 10 # number of float instructions
|
||||
system.cpu.num_int_register_reads 8304 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 4581 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 8 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 2 # number of times the floating registers were written
|
||||
system.cpu.num_mem_refs 2060 # number of memory refs
|
||||
system.cpu.num_load_insts 1192 # Number of load instructions
|
||||
system.cpu.num_store_insts 868 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 342698 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
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Reference in New Issue
Block a user