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Adding gem5 source to svn.

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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1819 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
This commit is contained in:
friemel
2012-10-24 19:18:57 +00:00
parent f7ff71bd46
commit b41eec3f65
3222 changed files with 658579 additions and 1 deletions
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231
simulators/gem5/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/config.ini Normal file
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[root]
type=Root
children=system
full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
boot_osflags=a
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
readfile=
symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.cpu]
type=InOrderCPU
children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
BTBEntries=4096
BTBTagSize=16
RASSize=16
activity=0
cachePorts=2
checker=Null
choiceCtrBits=2
choicePredictorSize=8192
clock=500
cpu_id=0
defer_registration=false
div16Latency=1
div16RepeatRate=1
div24Latency=1
div24RepeatRate=1
div32Latency=1
div32RepeatRate=1
div8Latency=1
div8RepeatRate=1
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
fetchBuffSize=4
functionTrace=false
functionTraceStart=0
function_trace=false
function_trace_start=0
globalCtrBits=2
globalHistoryBits=13
globalPredictorSize=8192
instShiftAmt=2
interrupts=system.cpu.interrupts
itb=system.cpu.itb
localCtrBits=2
localHistoryBits=11
localHistoryTableSize=2048
localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
memBlockSize=64
multLatency=1
multRepeatRate=1
numThreads=1
phase=0
predType=tournament
profile=0
progress_interval=0
stageTracing=false
stageWidth=4
system=system
threadModel=SMT
tracer=system.cpu.tracer
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=262144
subblock_size=0
system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
[system.cpu.dtb]
type=AlphaTLB
size=64
[system.cpu.icache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=131072
subblock_size=0
system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.interrupts]
type=AlphaInterrupts
[system.cpu.itb]
type=AlphaTLB
size=48
[system.cpu.l2cache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=false
latency=10000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=2097152
subblock_size=0
system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
[system.cpu.toL2Bus]
type=CoherentBus
block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=twolf smred
cwd=build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/inorder-timing
egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf
gid=100
input=cin
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=0
system=system
uid=100
[system.membus]
type=CoherentBus
block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
master=system.physmem.port[0]
slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=SimpleMemory
conf_table_reported=false
file=
in_addr_map=true
latency=30000
latency_var=0
null=false
range=0:134217727
zero=false
port=system.membus.master[0]

6
simulators/gem5/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simerr Executable file
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warn: Sockets disabled, not accepting gdb connections
warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
hack: be nice to actually delete the event here

26
simulators/gem5/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simout Executable file
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gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 4 2012 11:50:11
gem5 started Jun 4 2012 13:52:53
gem5 executing on zizzer
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/inorder-timing
Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/inorder-timing/smred.sav
Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/inorder-timing/smred.sv2
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
Standard Cell Placement and Global Routing Program
Authors: Carl Sechen, Bill Swartz
Yale University
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
61 62 63 64 65 66 67 68 69 70 71 72 73 74 75
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
122 123 124 Exiting @ tick 42005374000 because target called exit()

276
simulators/gem5/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/smred.out Normal file
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TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
Standard Cell Placement and Global Routing Program
Authors: Carl Sechen, Bill Swartz
Yale University
NOTE: Restart file .rs2 not used
TimberWolf will perform a global route step
rowSep: 1.000000
feedThruWidth: 4
******************
BLOCK DATA
block:1 desire:85
block:2 desire:85
Total Desired Length: 170
total cell length: 168
total block length: 168
block x-span:84 block y-span:78
implicit feed thru range: -84
Using default value of bin.penalty.control:1.000000
numBins automatically set to:5
binWidth = average_cell_width + 0 sigma= 17
average_cell_width is:16
standard deviation of cell length is:23.6305
TimberWolfSC starting from the beginning
THIS IS THE ROUTE COST OF THE ORIGINAL PLACEMENT: 645
The number of nets with 1 pin is 4
The number of nets with 2 pin is 9
The number of nets with 3 pin is 0
The number of nets with 4 pin is 2
The number of nets with 5 pin is 0
The number of nets with 6 pin is 0
The number of nets with 7 pin is 0
The number of nets with 8 pin is 0
The number of nets with 9 pin is 0
The number of nets with 10 pin or more is 0
New Cost Function: Initial Horizontal Cost:242
New Cost Function: FEEDS:0 MISSING_ROWS:-46
bdxlen:86 bdylen:78
l:0 t:78 r:86 b:0
THIS IS THE ROUTE COST OF THE CURRENT PLACEMENT: 645
THIS IS THE PENALTY OF THE CURRENT PLACEMENT: 44
The rand generator seed was at utemp() : 1
tempfile[0][0] = 0.982500 tempfile[0][1] = 90.000000
tempfile[1][0] = 0.915000 tempfile[1][1] = 20.000000
tempfile[2][0] = 0.700000 tempfile[2][1] = 10.000000
tempfile[3][0] = 0.100000 tempfile[3][1] = 0.000000
I T fds Wire Penalty P_lim Epct binC rowC acc s/p early FDs MRs
1 500 0 929 592 160 30.0 1.0 3.0 84.2 34.7 0.0 0 40
2 491 0 876 106 726 0.0 0.8 2.5 80.0 18.5 0.0 0 46
3 482 0 822 273 372 0.0 0.5 1.5 80.8 21.3 0.0 0 46
4 474 0 826 53 247 0.0 0.5 0.9 65.0 21.9 0.0 0 48
5 465 8 987 73 190 0.0 0.5 0.5 50.0 38.3 0.0 0 46
6 457 8 851 67 226 0.0 0.5 0.5 53.8 42.9 0.0 0 52
7 449 8 1067 108 190 0.0 0.5 0.5 46.2 53.8 0.0 0 50
8 441 8 918 106 171 0.0 0.5 0.5 47.1 40.4 0.0 0 48
9 434 8 812 101 197 0.0 0.5 0.5 53.6 21.0 0.0 0 48
10 426 8 1038 121 181 0.0 0.5 0.5 43.6 27.1 0.0 0 48
11 419 8 898 93 187 0.0 0.5 0.5 45.3 47.8 0.0 0 50
12 411 4 857 94 240 0.0 0.5 0.5 62.7 51.6 0.0 0 44
13 404 8 1043 88 185 0.0 0.5 0.5 54.0 52.8 0.0 0 50
14 397 8 767 94 154 0.0 0.5 0.5 33.8 35.0 0.0 0 50
15 390 8 862 89 183 0.0 0.5 0.5 55.6 29.0 0.0 0 46
16 383 4 798 79 173 0.0 0.5 0.5 57.5 35.3 0.0 0 52
17 376 8 827 100 152 0.0 0.5 0.5 35.3 81.8 0.0 0 50
18 370 8 878 101 208 0.0 0.5 0.5 44.7 46.2 0.0 0 48
19 363 4 921 67 167 0.0 0.5 0.5 57.1 34.7 0.0 0 48
20 357 8 933 93 154 0.0 0.5 0.5 46.5 43.6 0.0 0 52
21 351 8 930 89 147 0.0 0.5 0.5 39.4 36.5 0.0 0 52
22 345 8 951 79 142 0.0 0.5 0.5 32.8 51.3 0.0 0 50
23 339 8 1046 87 207 0.0 0.5 0.5 52.8 61.0 0.0 0 48
24 333 4 989 96 185 0.0 0.5 0.5 45.3 43.3 0.0 0 42
25 327 4 577 86 157 0.0 0.5 0.5 31.1 55.3 0.0 0 52
26 321 8 776 97 174 0.0 0.5 0.5 47.9 62.5 0.0 0 52
27 315 8 850 81 188 0.0 0.5 0.5 45.0 55.2 0.0 0 50
28 310 8 898 97 148 0.0 0.5 0.5 43.0 45.8 0.0 0 48
29 304 8 889 65 173 0.0 0.5 0.5 32.5 41.3 0.0 0 50
30 299 8 858 81 153 0.0 0.5 0.5 44.3 29.2 0.0 0 46
31 294 8 871 82 187 0.0 0.5 0.5 45.7 47.7 0.0 0 48
32 289 8 782 109 173 0.0 0.5 0.5 35.2 57.4 0.0 0 48
33 284 8 743 98 189 0.0 0.6 0.5 41.8 64.3 0.0 0 52
34 279 8 943 90 147 0.0 0.5 0.5 38.6 32.8 0.0 0 48
35 274 8 907 57 166 0.0 0.5 0.5 33.6 51.0 0.0 0 48
36 269 8 900 70 148 0.0 0.5 0.5 45.0 41.4 0.0 0 50
37 264 4 875 106 133 0.0 0.5 0.5 31.7 55.3 0.0 0 52
38 260 8 1023 145 149 0.0 0.6 0.5 28.7 65.0 0.0 0 52
39 255 8 801 151 173 0.0 0.9 0.5 41.7 41.2 0.0 0 48
40 251 8 741 104 159 0.0 0.8 0.5 36.3 47.5 0.0 0 48
41 246 8 828 108 149 0.0 0.5 0.5 34.6 50.9 0.0 0 50
42 242 8 947 128 132 0.0 0.7 0.5 34.2 39.0 0.0 0 50
43 238 8 917 101 142 0.0 0.8 0.5 34.4 50.9 0.0 0 48
44 234 8 761 86 129 0.0 0.5 0.5 42.0 36.4 0.0 0 52
45 229 8 979 106 137 0.0 0.5 0.5 29.2 55.3 0.0 0 50
46 225 8 806 74 130 0.0 0.7 0.5 33.1 65.4 0.0 0 52
47 221 8 971 125 114 0.0 0.5 0.5 31.9 45.6 0.0 0 52
48 218 8 869 125 104 0.0 0.9 0.5 30.0 56.0 0.0 0 48
49 214 8 999 153 140 0.0 0.8 0.5 30.4 46.4 0.0 0 52
50 210 8 798 192 139 0.0 1.0 0.5 28.9 50.0 0.0 0 52
51 206 8 860 125 157 0.0 1.2 0.5 31.5 26.9 0.0 0 52
52 203 8 893 186 127 5.9 0.9 0.5 26.4 42.3 0.0 0 46
53 199 8 863 126 141 0.0 1.2 0.5 32.5 44.4 0.0 0 44
54 196 8 788 97 133 0.0 0.9 0.5 37.5 40.0 0.0 0 50
55 192 8 926 119 116 0.0 0.6 0.5 26.1 55.3 0.0 0 52
56 189 8 789 162 107 0.0 0.8 0.5 25.2 40.4 0.0 0 48
57 186 8 878 107 128 0.0 1.1 0.5 23.1 34.0 0.0 0 52
58 182 8 775 105 122 0.0 0.8 0.5 25.5 57.4 0.0 0 50
59 179 8 747 94 129 0.0 0.7 0.5 34.3 37.3 0.0 0 50
60 176 8 845 96 138 0.0 0.6 0.5 28.3 41.7 0.0 0 52
61 173 8 961 121 110 0.0 0.6 0.5 29.0 52.6 0.0 0 48
62 170 4 911 110 109 0.0 0.9 0.5 33.5 33.3 0.0 0 48
63 167 8 656 109 109 0.0 0.8 0.5 21.9 44.7 0.0 0 52
64 164 8 934 117 105 0.0 0.8 0.5 15.5 50.0 0.0 0 52
65 161 8 972 125 95 0.0 0.8 0.5 24.4 50.0 0.0 0 50
66 158 8 894 125 101 0.0 0.9 0.5 27.2 35.9 0.0 0 52
67 155 8 798 146 129 0.0 1.0 0.5 22.8 58.7 0.0 0 52
68 153 8 901 183 92 0.0 1.1 0.5 23.6 34.5 0.0 0 52
69 150 8 977 197 103 0.0 1.4 0.5 23.6 36.8 0.0 0 52
70 147 8 905 262 93 0.0 1.5 0.5 20.3 63.4 0.0 0 52
71 145 8 995 148 122 0.0 1.9 0.5 20.9 35.3 0.0 0 52
72 142 8 934 230 99 0.0 1.6 0.5 20.0 65.9 0.0 0 52
73 140 8 862 173 100 0.0 1.8 0.5 26.8 46.8 0.0 0 52
74 137 8 924 139 90 0.0 1.7 0.5 16.8 42.5 0.0 0 52
75 135 8 888 168 113 0.0 1.6 0.5 22.9 40.4 0.0 0 52
76 133 8 712 212 84 0.0 1.6 0.5 13.4 46.9 0.0 0 52
77 130 8 868 210 91 0.0 1.7 0.5 17.7 51.2 0.0 0 52
78 128 8 952 307 92 0.0 1.9 0.5 19.7 44.9 0.0 0 50
79 126 8 801 157 107 0.0 2.2 0.5 15.8 39.0 0.0 0 52
80 123 8 849 147 93 0.0 2.1 0.5 15.6 51.4 0.0 0 52
81 121 8 799 154 86 0.0 1.9 0.5 12.2 50.0 0.0 0 52
82 119 8 941 213 82 0.0 1.8 0.5 19.5 41.2 0.0 0 50
83 117 8 751 268 94 0.0 2.0 0.5 20.8 42.6 0.0 0 50
84 115 8 828 198 102 0.0 2.2 0.5 15.5 59.5 0.0 0 52
85 113 8 898 266 123 0.0 2.2 0.5 13.2 85.2 0.0 0 52
86 111 8 943 190 93 0.0 2.4 0.5 19.5 45.1 0.0 0 52
87 109 8 864 183 65 0.0 2.4 0.5 14.9 31.8 0.0 0 52
88 107 8 793 203 93 0.0 2.4 0.5 11.8 35.3 0.0 0 52
89 105 8 752 162 74 1.2 2.4 0.5 13.1 21.4 0.0 0 52
90 103 8 801 149 77 0.0 2.3 0.5 9.7 58.3 0.0 0 52
91 102 8 901 230 99 0.0 2.2 0.5 16.0 25.5 0.0 0 52
92 100 8 826 201 87 0.0 2.4 0.5 12.8 45.7 0.0 0 52
93 98 8 810 196 83 0.0 2.5 0.5 14.0 24.4 0.0 0 52
94 96 8 857 209 68 1.0 2.5 0.5 11.5 27.0 5.1 0 52
95 95 8 771 174 91 0.0 2.6 0.5 10.5 26.5 0.0 0 52
96 93 8 955 210 59 0.0 2.6 0.5 10.0 36.7 0.7 0 52
97 91 8 833 206 53 0.0 2.7 0.5 10.2 19.4 1.4 0 52
98 90 8 888 229 86 0.0 2.8 0.5 8.1 36.0 0.0 0 52
99 88 8 794 186 91 1.0 2.9 0.5 8.3 25.0 0.5 0 52
100 81 8 756 170 72 1.0 2.9 0.5 6.0 23.8 7.0 0 52
101 74 8 791 176 67 0.0 2.9 0.5 4.4 58.3 4.0 0 52
102 67 8 813 213 43 0.0 3.0 0.5 7.0 150.0 4.2 0 52
103 62 8 779 245 39 0.0 3.1 0.5 3.2 16.7 13.0 0 52
104 56 8 767 303 63 0.0 3.2 0.5 4.1 20.0 0.7 0 52
105 52 8 757 270 57 0.0 3.5 0.5 6.4 3.7 0.5 0 52
106 47 8 763 283 41 0.0 3.7 0.5 4.5 0.0 0.0 0 52
107 43 8 768 283 36 0.0 3.7 0.5 2.9 18.2 3.6 0 52
108 39 8 804 283 25 0.0 3.7 0.5 3.1 0.0 6.2 0 52
109 36 8 781 283 24 0.0 3.7 0.5 3.6 6.7 6.7 0 52
110 33 8 738 298 42 0.0 3.7 0.5 3.3 15.4 3.5 0 52
111 30 8 761 298 36 0.0 3.7 0.5 2.2 0.0 4.3 0 52
112 27 8 769 298 37 0.0 3.7 0.5 0.9 0.0 2.2 0 52
113 25 8 745 298 31 0.0 3.7 0.5 1.5 0.0 6.6 0 52
114 23 8 753 298 16 0.0 3.7 0.5 1.3 0.0 2.8 0 52
115 21 8 745 298 11 0.0 3.7 0.5 1.5 0.0 14.0 0 52
116 19 8 747 298 21 0.0 3.7 0.5 2.1 0.0 5.8 0 52
117 13 8 737 298 12 0.0 3.7 0.5 1.0 0.0 10.0 0 52
118 9 8 736 298 4 0.0 3.7 0.5 1.5 0.0 18.5 0 52
119 0 8 739 298 0 0.0 3.7 0.5 1.8 0.0 18.0 0 52
120 0 8 732 298 0 0.0 3.7 0.5 1.2 0.0 21.8 0 52
121 0 8 732 19 -1 0.0 0.0 0.5 0.0 100.0 54.8
Initial Wiring Cost: 645 Final Wiring Cost: 732
############## Percent Wire Cost Reduction: -13
Initial Wire Length: 645 Final Wire Length: 732
************** Percent Wire Length Reduction: -13
Initial Horiz. Wire: 216 Final Horiz. Wire: 147
$$$$$$$$$$$ Percent H-Wire Length Reduction: 32
Initial Vert. Wire: 429 Final Vert. Wire: 585
@@@@@@@@@@@ Percent V-Wire Length Reduction: -36
Before Feeds are Added:
BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET
1 82 -20
2 86 -16
LONGEST Block is:2 Its length is:86
BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET
1 86 -16
2 86 -16
LONGEST Block is:1 Its length is:86
Added: 1 feed-through cells
Removed the cell overlaps --- Will do neighbor interchanges only now
TOTAL INTERCONNECT LENGTH: 994
OVERLAP PENALTY: 0
initialRowControl: 1.650
finalRowControl: 0.300
iter T Wire accept
122 0.001 976 16%
123 0.001 971 0%
124 0.001 971 0%
Total Feed-Alignment Movement (Pass 1): 0
Total Feed-Alignment Movement (Pass 2): 0
Total Feed-Alignment Movement (Pass 3): 0
Total Feed-Alignment Movement (Pass 4): 0
Total Feed-Alignment Movement (Pass 5): 0
Total Feed-Alignment Movement (Pass 6): 0
Total Feed-Alignment Movement (Pass 7): 0
Total Feed-Alignment Movement (Pass 8): 0
The rand generator seed was at globroute() : 987654321
Total Number of Net Segments: 9
Number of Switchable Net Segments: 0
Number of channels: 3
THIS IS THE ORIGINAL NUMBER OF TRACKS: 5
no. of accepted flips: 0
no. of attempted flips: 0
THIS IS THE NUMBER OF TRACKS: 5
FINAL NUMBER OF ROUTING TRACKS: 5
MAX OF CHANNEL: 1 is: 0
MAX OF CHANNEL: 2 is: 4
MAX OF CHANNEL: 3 is: 1
FINAL TOTAL INTERCONNECT LENGTH: 978
FINAL OVERLAP PENALTY: 0 FINAL VALUE OF TOTAL COST IS: 978
MAX NUMBER OF ATTEMPTED FLIPS PER T: 55
cost_scale_factor:3.90616
Number of Feed Thrus: 0
Number of Implicit Feed Thrus: 0
Statistics:
Number of Standard Cells: 10
Number of Pads: 0
Number of Nets: 15
Number of Pins: 46
Usage statistics not available

17
simulators/gem5/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/smred.pin Normal file
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$COUNT_1/$AND2_1/$ND2_1$Z 1 $COUNT_1/$AND2_1/$ND2_1 00#Z 17 52 2 1 0
$COUNT_1/$AND2_1/$ND2_1$Z 1 ACOUNT_1 00#A 15 26 2 -1 0
B7 2 $COUNT_1/$FJK3_2 00#K 25 78 3 -1 0
B7 2 $COUNT_1/$FJK3_2 00#J 23 78 3 -1 0
B7 3 $COUNT_1/$AND2_2/$ND2_1 00#A 9 26 2 -1 0
B7 3 ACOUNT_1 01#Z 17 26 2 -1 0
B6 5 $COUNT_1/$FJK3_1 00#K 25 26 2 -1 0
B6 5 $COUNT_1/$FJK3_1 00#J 23 26 2 -1 0
B6 5 $COUNT_1/$AND2_3/$IV_1 01#Z 7 26 2 -1 0
$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$FJK3_1 01#Q 81 26 2 -1 0
$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$AND2_1/$ND2_1 00#B 19 52 2 1 0
$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$FJK3_2 00#Q 81 52 2 1 0
$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$AND2_2/$ND2_1 01#B 11 26 2 -1 0
$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$ND2_1 00#Z 5 52 2 1 0
$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$IV_1 00#A 5 26 2 -1 0
$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$ND2_1 00#Z 7 52 2 1 0
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11
simulators/gem5/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/smred.pl1 Normal file
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$COUNT_1/$AND2_3/$IV_1 4 0 8 26 2 1
$COUNT_1/$AND2_2/$ND2_1 8 0 14 26 0 1
ACOUNT_1 14 0 18 26 2 1
twfeed1 18 0 22 26 0 1
$COUNT_1/$FJK3_1 22 0 86 26 0 1
$COUNT_1/$AND2_3/$ND2_1 0 52 6 78 0 2
$COUNT_1/$AND2_4/$ND2_1 6 52 12 78 2 2
$COUNT_1/$AND2_2/$IV_1 12 52 16 78 2 2
$COUNT_1/$AND2_1/$ND2_1 16 52 22 78 2 2
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simulators/gem5/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/smred.pl2 Normal file
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simulators/gem5/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/smred.sav Normal file
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simulators/gem5/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/smred.sv2 Normal file
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simulators/gem5/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/smred.twf Normal file
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net 1
segment channel 2
pin1 1 pin2 7 0 0
net 2
segment channel 3
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segment channel 2
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net 3
segment channel 2
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segment channel 2
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net 4
segment channel 2
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net 5
net 7
segment channel 2
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net 8
segment channel 2
pin1 23 pin2 17 0 0
net 9
net 11
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net 14
net 15

460
simulators/gem5/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt Normal file
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@ -0,0 +1,460 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.042005 # Number of seconds simulated
sim_ticks 42005374000 # Number of ticks simulated
final_tick 42005374000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 106867 # Simulator instruction rate (inst/s)
host_op_rate 106867 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 48844875 # Simulator tick rate (ticks/s)
host_mem_usage 218932 # Number of bytes of host memory used
host_seconds 859.98 # Real time elapsed on the host
sim_insts 91903056 # Number of instructions simulated
sim_ops 91903056 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 178816 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 137216 # Number of bytes read from this memory
system.physmem.bytes_read::total 316032 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 178816 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 178816 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 2794 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 2144 # Number of read requests responded to by this memory
system.physmem.num_reads::total 4938 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 4256979 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 3266630 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 7523609 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 4256979 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 4256979 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 4256979 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 3266630 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 7523609 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 19996214 # DTB read hits
system.cpu.dtb.read_misses 10 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 19996224 # DTB read accesses
system.cpu.dtb.write_hits 6501905 # DTB write hits
system.cpu.dtb.write_misses 23 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 6501928 # DTB write accesses
system.cpu.dtb.data_hits 26498119 # DTB hits
system.cpu.dtb.data_misses 33 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 26498152 # DTB accesses
system.cpu.itb.fetch_hits 10037351 # ITB hits
system.cpu.itb.fetch_misses 49 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 10037400 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 389 # Number of system calls
system.cpu.numCycles 84010749 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.branch_predictor.lookups 13563923 # Number of BP lookups
system.cpu.branch_predictor.condPredicted 9779691 # Number of conditional branches predicted
system.cpu.branch_predictor.condIncorrect 4496836 # Number of conditional branches incorrect
system.cpu.branch_predictor.BTBLookups 7950423 # Number of BTB lookups
system.cpu.branch_predictor.BTBHits 3848158 # Number of BTB hits
system.cpu.branch_predictor.usedRAS 1029619 # Number of times the RAS was used to get a target.
system.cpu.branch_predictor.RASInCorrect 123 # Number of incorrect RAS predictions.
system.cpu.branch_predictor.BTBHitPct 48.401928 # BTB Hit Percentage
system.cpu.branch_predictor.predictedTaken 5997418 # Number of Branches Predicted As Taken (True).
system.cpu.branch_predictor.predictedNotTaken 7566505 # Number of Branches Predicted As Not Taken (False).
system.cpu.regfile_manager.intRegFileReads 73742077 # Number of Reads from Int. Register File
system.cpu.regfile_manager.intRegFileWrites 62575472 # Number of Writes to Int. Register File
system.cpu.regfile_manager.intRegFileAccesses 136317549 # Total Accesses (Read+Write) to the Int. Register File
system.cpu.regfile_manager.floatRegFileReads 2206798 # Number of Reads from FP Register File
system.cpu.regfile_manager.floatRegFileWrites 5851888 # Number of Writes to FP Register File
system.cpu.regfile_manager.floatRegFileAccesses 8058686 # Total Accesses (Read+Write) to the FP Register File
system.cpu.regfile_manager.regForwards 38530251 # Number of Registers Read Through Forwarding Logic
system.cpu.agen_unit.agens 26765541 # Number of Address Generations
system.cpu.execution_unit.predictedTakenIncorrect 3521133 # Number of Branches Incorrectly Predicted As Taken.
system.cpu.execution_unit.predictedNotTakenIncorrect 974845 # Number of Branches Incorrectly Predicted As Not Taken).
system.cpu.execution_unit.mispredicted 4495978 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.predicted 5744724 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.mispredictPct 43.903025 # Percentage of Incorrect Branches Predicts
system.cpu.execution_unit.executions 57471384 # Number of Instructions Executed.
system.cpu.mult_div_unit.multiplies 458266 # Number of Multipy Operations Executed
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
system.cpu.contextSwitches 1 # Number of context switches
system.cpu.threadCycles 83632403 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
system.cpu.timesIdled 11097 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 7735993 # Number of cycles cpu's stages were not processed
system.cpu.runCycles 76274756 # Number of cycles cpu stages are processed.
system.cpu.activity 90.791663 # Percentage of cycles cpu is active
system.cpu.comLoads 19996198 # Number of Load instructions committed
system.cpu.comStores 6501103 # Number of Store instructions committed
system.cpu.comBranches 10240685 # Number of Branches instructions committed
system.cpu.comNops 7723346 # Number of Nop instructions committed
system.cpu.comNonSpec 389 # Number of Non-Speculative instructions committed
system.cpu.comInts 43665352 # Number of Integer instructions committed
system.cpu.comFloats 3775974 # Number of Floating Point instructions committed
system.cpu.committedInsts 91903056 # Number of Instructions committed (Per-Thread)
system.cpu.committedOps 91903056 # Number of Ops committed (Per-Thread)
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
system.cpu.committedInsts_total 91903056 # Number of Instructions committed (Total)
system.cpu.cpi 0.914124 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.smt_cpi nan # CPI: Total SMT-CPI
system.cpu.cpi_total 0.914124 # CPI: Total CPI of All Threads
system.cpu.ipc 1.093944 # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.smt_ipc nan # IPC: Total SMT-IPC
system.cpu.ipc_total 1.093944 # IPC: Total IPC of All Threads
system.cpu.stage0.idleCycles 27790213 # Number of cycles 0 instructions are processed.
system.cpu.stage0.runCycles 56220536 # Number of cycles 1+ instructions are processed.
system.cpu.stage0.utilization 66.920646 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage1.idleCycles 34560671 # Number of cycles 0 instructions are processed.
system.cpu.stage1.runCycles 49450078 # Number of cycles 1+ instructions are processed.
system.cpu.stage1.utilization 58.861608 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage2.idleCycles 34032650 # Number of cycles 0 instructions are processed.
system.cpu.stage2.runCycles 49978099 # Number of cycles 1+ instructions are processed.
system.cpu.stage2.utilization 59.490124 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage3.idleCycles 65981194 # Number of cycles 0 instructions are processed.
system.cpu.stage3.runCycles 18029555 # Number of cycles 1+ instructions are processed.
system.cpu.stage3.utilization 21.461010 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage4.idleCycles 30068425 # Number of cycles 0 instructions are processed.
system.cpu.stage4.runCycles 53942324 # Number of cycles 1+ instructions are processed.
system.cpu.stage4.utilization 64.208836 # Percentage of cycles stage was utilized (processing insts).
system.cpu.icache.replacements 8111 # number of replacements
system.cpu.icache.tagsinuse 1492.322334 # Cycle average of tags in use
system.cpu.icache.total_refs 10025618 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 9996 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 1002.962985 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 1492.322334 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.728673 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.728673 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 10025618 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 10025618 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 10025618 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 10025618 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 10025618 # number of overall hits
system.cpu.icache.overall_hits::total 10025618 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 11728 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 11728 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 11728 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 11728 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 11728 # number of overall misses
system.cpu.icache.overall_misses::total 11728 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 295393500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 295393500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 295393500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 295393500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 295393500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 295393500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 10037346 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 10037346 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 10037346 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 10037346 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 10037346 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 10037346 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001168 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.001168 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.001168 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.001168 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.001168 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.001168 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25187.031037 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 25187.031037 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 25187.031037 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 25187.031037 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 25187.031037 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 25187.031037 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 97000 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 6 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets 16166.666667 # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1732 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 1732 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 1732 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 1732 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 1732 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 1732 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 9996 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 9996 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 9996 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 9996 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 9996 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 9996 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 228898000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 228898000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 228898000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 228898000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 228898000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 228898000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000996 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000996 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000996 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000996 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000996 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000996 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22898.959584 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22898.959584 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22898.959584 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 22898.959584 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22898.959584 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 22898.959584 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 157 # number of replacements
system.cpu.dcache.tagsinuse 1441.511431 # Cycle average of tags in use
system.cpu.dcache.total_refs 26491208 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 2223 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 11916.872695 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 1441.511431 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.351932 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.351932 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 19995646 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 19995646 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 6495562 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 6495562 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 26491208 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 26491208 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 26491208 # number of overall hits
system.cpu.dcache.overall_hits::total 26491208 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 552 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 552 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 5541 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 5541 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 6093 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 6093 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 6093 # number of overall misses
system.cpu.dcache.overall_misses::total 6093 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 28391500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 28391500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 303790500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 303790500 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 332182000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 332182000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 332182000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 332182000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 19996198 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 19996198 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 26497301 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 26497301 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 26497301 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 26497301 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000028 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.000028 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000852 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.000852 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.000230 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.000230 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.000230 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.000230 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51433.876812 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 51433.876812 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54825.933947 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 54825.933947 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 54518.627934 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 54518.627934 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 54518.627934 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 54518.627934 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 41043500 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 823 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 49870.595383 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 107 # number of writebacks
system.cpu.dcache.writebacks::total 107 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 77 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 77 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3793 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 3793 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 3870 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 3870 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 3870 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 3870 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 475 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 475 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1748 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 1748 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 2223 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 2223 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 2223 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 2223 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23216000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 23216000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 92995500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 92995500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 116211500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 116211500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 116211500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 116211500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000269 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000269 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 48875.789474 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 48875.789474 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53201.086957 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53201.086957 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52276.878093 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 52276.878093 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52276.878093 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 52276.878093 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 2189.730470 # Cycle average of tags in use
system.cpu.l2cache.total_refs 7264 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 3282 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 2.213285 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 17.847253 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 1820.879596 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 351.003621 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.000545 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.055569 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.010712 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.066825 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 7202 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 53 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 7255 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 107 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 107 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 26 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 26 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst 7202 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 79 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 7281 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 7202 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 79 # number of overall hits
system.cpu.l2cache.overall_hits::total 7281 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 2794 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 422 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 3216 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 1722 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 1722 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 2794 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 2144 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 4938 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 2794 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 2144 # number of overall misses
system.cpu.l2cache.overall_misses::total 4938 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 146177000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 22139000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 168316000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 90566000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 90566000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 146177000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 112705000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 258882000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 146177000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 112705000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 258882000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 9996 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 475 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 10471 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 107 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 107 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1748 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 1748 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 9996 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 2223 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 12219 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 9996 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 2223 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 12219 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.279512 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.888421 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.307134 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.985126 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.985126 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.279512 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.964462 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.404125 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.279512 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.964462 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.404125 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52318.181818 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52462.085308 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52337.064677 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52593.495935 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52593.495935 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52318.181818 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52567.630597 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 52426.488457 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52318.181818 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52567.630597 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 52426.488457 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2794 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 422 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 3216 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1722 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 1722 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 2794 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 2144 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 4938 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2794 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 2144 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 4938 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 112070000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 16981000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 129051000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 69345500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 69345500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 112070000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 86326500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 198396500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 112070000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 86326500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 198396500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.279512 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.888421 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.307134 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.985126 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.985126 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.279512 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.404125 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.279512 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.404125 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40110.952040 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40239.336493 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40127.798507 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40270.325203 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40270.325203 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40110.952040 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40264.225746 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40177.501013 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40110.952040 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40264.225746 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40177.501013 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

529
simulators/gem5/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini Normal file
View File

@ -0,0 +1,529 @@
[root]
type=Root
children=system
full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
boot_osflags=a
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
readfile=
symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.cpu]
type=DerivO3CPU
children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
LSQDepCheckShift=4
RASSize=16
SQEntries=32
SSITSize=1024
activity=0
backComSize=5
cachePorts=200
checker=Null
choiceCtrBits=2
choicePredictorSize=8192
clock=500
commitToDecodeDelay=1
commitToFetchDelay=1
commitToIEWDelay=1
commitToRenameDelay=1
commitWidth=8
cpu_id=0
decodeToFetchDelay=1
decodeToRenameDelay=1
decodeWidth=8
defer_registration=false
dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
fetchToDecodeDelay=1
fetchTrapLatency=1
fetchWidth=8
forwardComSize=5
fuPool=system.cpu.fuPool
function_trace=false
function_trace_start=0
globalCtrBits=2
globalHistoryBits=13
globalPredictorSize=8192
iewToCommitDelay=1
iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
instShiftAmt=2
interrupts=system.cpu.interrupts
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
localCtrBits=2
localHistoryBits=11
localHistoryTableSize=2048
localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
needsTSO=false
numIQEntries=64
numPhysFloatRegs=256
numPhysIntRegs=256
numROBEntries=192
numRobs=1
numThreads=1
phase=0
predType=tournament
profile=0
progress_interval=0
renameToDecodeDelay=1
renameToFetchDelay=1
renameToIEWDelay=2
renameToROBDelay=1
renameWidth=8
smtCommitPolicy=RoundRobin
smtFetchPolicy=SingleThread
smtIQPolicy=Partitioned
smtIQThreshold=100
smtLSQPolicy=Partitioned
smtLSQThreshold=100
smtNumFetchingThreads=1
smtROBPolicy=Partitioned
smtROBThreshold=100
squashWidth=8
store_set_clear_period=250000
system=system
tracer=system.cpu.tracer
trapLatency=13
wbDepth=1
wbWidth=8
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=262144
subblock_size=0
system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
[system.cpu.dtb]
type=AlphaTLB
size=64
[system.cpu.fuPool]
type=FUPool
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
[system.cpu.fuPool.FUList0]
type=FUDesc
children=opList
count=6
opList=system.cpu.fuPool.FUList0.opList
[system.cpu.fuPool.FUList0.opList]
type=OpDesc
issueLat=1
opClass=IntAlu
opLat=1
[system.cpu.fuPool.FUList1]
type=FUDesc
children=opList0 opList1
count=2
opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
[system.cpu.fuPool.FUList1.opList0]
type=OpDesc
issueLat=1
opClass=IntMult
opLat=3
[system.cpu.fuPool.FUList1.opList1]
type=OpDesc
issueLat=19
opClass=IntDiv
opLat=20
[system.cpu.fuPool.FUList2]
type=FUDesc
children=opList0 opList1 opList2
count=4
opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
[system.cpu.fuPool.FUList2.opList0]
type=OpDesc
issueLat=1
opClass=FloatAdd
opLat=2
[system.cpu.fuPool.FUList2.opList1]
type=OpDesc
issueLat=1
opClass=FloatCmp
opLat=2
[system.cpu.fuPool.FUList2.opList2]
type=OpDesc
issueLat=1
opClass=FloatCvt
opLat=2
[system.cpu.fuPool.FUList3]
type=FUDesc
children=opList0 opList1 opList2
count=2
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
[system.cpu.fuPool.FUList3.opList0]
type=OpDesc
issueLat=1
opClass=FloatMult
opLat=4
[system.cpu.fuPool.FUList3.opList1]
type=OpDesc
issueLat=12
opClass=FloatDiv
opLat=12
[system.cpu.fuPool.FUList3.opList2]
type=OpDesc
issueLat=24
opClass=FloatSqrt
opLat=24
[system.cpu.fuPool.FUList4]
type=FUDesc
children=opList
count=0
opList=system.cpu.fuPool.FUList4.opList
[system.cpu.fuPool.FUList4.opList]
type=OpDesc
issueLat=1
opClass=MemRead
opLat=1
[system.cpu.fuPool.FUList5]
type=FUDesc
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
count=4
opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
[system.cpu.fuPool.FUList5.opList00]
type=OpDesc
issueLat=1
opClass=SimdAdd
opLat=1
[system.cpu.fuPool.FUList5.opList01]
type=OpDesc
issueLat=1
opClass=SimdAddAcc
opLat=1
[system.cpu.fuPool.FUList5.opList02]
type=OpDesc
issueLat=1
opClass=SimdAlu
opLat=1
[system.cpu.fuPool.FUList5.opList03]
type=OpDesc
issueLat=1
opClass=SimdCmp
opLat=1
[system.cpu.fuPool.FUList5.opList04]
type=OpDesc
issueLat=1
opClass=SimdCvt
opLat=1
[system.cpu.fuPool.FUList5.opList05]
type=OpDesc
issueLat=1
opClass=SimdMisc
opLat=1
[system.cpu.fuPool.FUList5.opList06]
type=OpDesc
issueLat=1
opClass=SimdMult
opLat=1
[system.cpu.fuPool.FUList5.opList07]
type=OpDesc
issueLat=1
opClass=SimdMultAcc
opLat=1
[system.cpu.fuPool.FUList5.opList08]
type=OpDesc
issueLat=1
opClass=SimdShift
opLat=1
[system.cpu.fuPool.FUList5.opList09]
type=OpDesc
issueLat=1
opClass=SimdShiftAcc
opLat=1
[system.cpu.fuPool.FUList5.opList10]
type=OpDesc
issueLat=1
opClass=SimdSqrt
opLat=1
[system.cpu.fuPool.FUList5.opList11]
type=OpDesc
issueLat=1
opClass=SimdFloatAdd
opLat=1
[system.cpu.fuPool.FUList5.opList12]
type=OpDesc
issueLat=1
opClass=SimdFloatAlu
opLat=1
[system.cpu.fuPool.FUList5.opList13]
type=OpDesc
issueLat=1
opClass=SimdFloatCmp
opLat=1
[system.cpu.fuPool.FUList5.opList14]
type=OpDesc
issueLat=1
opClass=SimdFloatCvt
opLat=1
[system.cpu.fuPool.FUList5.opList15]
type=OpDesc
issueLat=1
opClass=SimdFloatDiv
opLat=1
[system.cpu.fuPool.FUList5.opList16]
type=OpDesc
issueLat=1
opClass=SimdFloatMisc
opLat=1
[system.cpu.fuPool.FUList5.opList17]
type=OpDesc
issueLat=1
opClass=SimdFloatMult
opLat=1
[system.cpu.fuPool.FUList5.opList18]
type=OpDesc
issueLat=1
opClass=SimdFloatMultAcc
opLat=1
[system.cpu.fuPool.FUList5.opList19]
type=OpDesc
issueLat=1
opClass=SimdFloatSqrt
opLat=1
[system.cpu.fuPool.FUList6]
type=FUDesc
children=opList
count=0
opList=system.cpu.fuPool.FUList6.opList
[system.cpu.fuPool.FUList6.opList]
type=OpDesc
issueLat=1
opClass=MemWrite
opLat=1
[system.cpu.fuPool.FUList7]
type=FUDesc
children=opList0 opList1
count=4
opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
[system.cpu.fuPool.FUList7.opList0]
type=OpDesc
issueLat=1
opClass=MemRead
opLat=1
[system.cpu.fuPool.FUList7.opList1]
type=OpDesc
issueLat=1
opClass=MemWrite
opLat=1
[system.cpu.fuPool.FUList8]
type=FUDesc
children=opList
count=1
opList=system.cpu.fuPool.FUList8.opList
[system.cpu.fuPool.FUList8.opList]
type=OpDesc
issueLat=3
opClass=IprAccess
opLat=3
[system.cpu.icache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=131072
subblock_size=0
system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.interrupts]
type=AlphaInterrupts
[system.cpu.itb]
type=AlphaTLB
size=48
[system.cpu.l2cache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=false
latency=1000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=2097152
subblock_size=0
system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
[system.cpu.toL2Bus]
type=CoherentBus
block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=twolf smred
cwd=build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing
egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf
gid=100
input=cin
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=0
system=system
uid=100
[system.membus]
type=CoherentBus
block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
master=system.physmem.port[0]
slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=SimpleMemory
conf_table_reported=false
file=
in_addr_map=true
latency=30000
latency_var=0
null=false
range=0:134217727
zero=false
port=system.membus.master[0]

6
simulators/gem5/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simerr Executable file
View File

@ -0,0 +1,6 @@
warn: Sockets disabled, not accepting gdb connections
warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
hack: be nice to actually delete the event here

26
simulators/gem5/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout Executable file
View File

@ -0,0 +1,26 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 4 2012 11:50:11
gem5 started Jun 4 2012 14:06:35
gem5 executing on zizzer
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing
Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing/smred.sav
Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing/smred.sv2
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
Standard Cell Placement and Global Routing Program
Authors: Carl Sechen, Bill Swartz
Yale University
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
61 62 63 64 65 66 67 68 69 70 71 72 73 74 75
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
122 123 124 Exiting @ tick 23638033500 because target called exit()

276
simulators/gem5/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.out Normal file
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@ -0,0 +1,276 @@
TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
Standard Cell Placement and Global Routing Program
Authors: Carl Sechen, Bill Swartz
Yale University
NOTE: Restart file .rs2 not used
TimberWolf will perform a global route step
rowSep: 1.000000
feedThruWidth: 4
******************
BLOCK DATA
block:1 desire:85
block:2 desire:85
Total Desired Length: 170
total cell length: 168
total block length: 168
block x-span:84 block y-span:78
implicit feed thru range: -84
Using default value of bin.penalty.control:1.000000
numBins automatically set to:5
binWidth = average_cell_width + 0 sigma= 17
average_cell_width is:16
standard deviation of cell length is:23.6305
TimberWolfSC starting from the beginning
THIS IS THE ROUTE COST OF THE ORIGINAL PLACEMENT: 645
The number of nets with 1 pin is 4
The number of nets with 2 pin is 9
The number of nets with 3 pin is 0
The number of nets with 4 pin is 2
The number of nets with 5 pin is 0
The number of nets with 6 pin is 0
The number of nets with 7 pin is 0
The number of nets with 8 pin is 0
The number of nets with 9 pin is 0
The number of nets with 10 pin or more is 0
New Cost Function: Initial Horizontal Cost:242
New Cost Function: FEEDS:0 MISSING_ROWS:-46
bdxlen:86 bdylen:78
l:0 t:78 r:86 b:0
THIS IS THE ROUTE COST OF THE CURRENT PLACEMENT: 645
THIS IS THE PENALTY OF THE CURRENT PLACEMENT: 44
The rand generator seed was at utemp() : 1
tempfile[0][0] = 0.982500 tempfile[0][1] = 90.000000
tempfile[1][0] = 0.915000 tempfile[1][1] = 20.000000
tempfile[2][0] = 0.700000 tempfile[2][1] = 10.000000
tempfile[3][0] = 0.100000 tempfile[3][1] = 0.000000
I T fds Wire Penalty P_lim Epct binC rowC acc s/p early FDs MRs
1 500 0 929 592 160 30.0 1.0 3.0 84.2 34.7 0.0 0 40
2 491 0 876 106 726 0.0 0.8 2.5 80.0 18.5 0.0 0 46
3 482 0 822 273 372 0.0 0.5 1.5 80.8 21.3 0.0 0 46
4 474 0 826 53 247 0.0 0.5 0.9 65.0 21.9 0.0 0 48
5 465 8 987 73 190 0.0 0.5 0.5 50.0 38.3 0.0 0 46
6 457 8 851 67 226 0.0 0.5 0.5 53.8 42.9 0.0 0 52
7 449 8 1067 108 190 0.0 0.5 0.5 46.2 53.8 0.0 0 50
8 441 8 918 106 171 0.0 0.5 0.5 47.1 40.4 0.0 0 48
9 434 8 812 101 197 0.0 0.5 0.5 53.6 21.0 0.0 0 48
10 426 8 1038 121 181 0.0 0.5 0.5 43.6 27.1 0.0 0 48
11 419 8 898 93 187 0.0 0.5 0.5 45.3 47.8 0.0 0 50
12 411 4 857 94 240 0.0 0.5 0.5 62.7 51.6 0.0 0 44
13 404 8 1043 88 185 0.0 0.5 0.5 54.0 52.8 0.0 0 50
14 397 8 767 94 154 0.0 0.5 0.5 33.8 35.0 0.0 0 50
15 390 8 862 89 183 0.0 0.5 0.5 55.6 29.0 0.0 0 46
16 383 4 798 79 173 0.0 0.5 0.5 57.5 35.3 0.0 0 52
17 376 8 827 100 152 0.0 0.5 0.5 35.3 81.8 0.0 0 50
18 370 8 878 101 208 0.0 0.5 0.5 44.7 46.2 0.0 0 48
19 363 4 921 67 167 0.0 0.5 0.5 57.1 34.7 0.0 0 48
20 357 8 933 93 154 0.0 0.5 0.5 46.5 43.6 0.0 0 52
21 351 8 930 89 147 0.0 0.5 0.5 39.4 36.5 0.0 0 52
22 345 8 951 79 142 0.0 0.5 0.5 32.8 51.3 0.0 0 50
23 339 8 1046 87 207 0.0 0.5 0.5 52.8 61.0 0.0 0 48
24 333 4 989 96 185 0.0 0.5 0.5 45.3 43.3 0.0 0 42
25 327 4 577 86 157 0.0 0.5 0.5 31.1 55.3 0.0 0 52
26 321 8 776 97 174 0.0 0.5 0.5 47.9 62.5 0.0 0 52
27 315 8 850 81 188 0.0 0.5 0.5 45.0 55.2 0.0 0 50
28 310 8 898 97 148 0.0 0.5 0.5 43.0 45.8 0.0 0 48
29 304 8 889 65 173 0.0 0.5 0.5 32.5 41.3 0.0 0 50
30 299 8 858 81 153 0.0 0.5 0.5 44.3 29.2 0.0 0 46
31 294 8 871 82 187 0.0 0.5 0.5 45.7 47.7 0.0 0 48
32 289 8 782 109 173 0.0 0.5 0.5 35.2 57.4 0.0 0 48
33 284 8 743 98 189 0.0 0.6 0.5 41.8 64.3 0.0 0 52
34 279 8 943 90 147 0.0 0.5 0.5 38.6 32.8 0.0 0 48
35 274 8 907 57 166 0.0 0.5 0.5 33.6 51.0 0.0 0 48
36 269 8 900 70 148 0.0 0.5 0.5 45.0 41.4 0.0 0 50
37 264 4 875 106 133 0.0 0.5 0.5 31.7 55.3 0.0 0 52
38 260 8 1023 145 149 0.0 0.6 0.5 28.7 65.0 0.0 0 52
39 255 8 801 151 173 0.0 0.9 0.5 41.7 41.2 0.0 0 48
40 251 8 741 104 159 0.0 0.8 0.5 36.3 47.5 0.0 0 48
41 246 8 828 108 149 0.0 0.5 0.5 34.6 50.9 0.0 0 50
42 242 8 947 128 132 0.0 0.7 0.5 34.2 39.0 0.0 0 50
43 238 8 917 101 142 0.0 0.8 0.5 34.4 50.9 0.0 0 48
44 234 8 761 86 129 0.0 0.5 0.5 42.0 36.4 0.0 0 52
45 229 8 979 106 137 0.0 0.5 0.5 29.2 55.3 0.0 0 50
46 225 8 806 74 130 0.0 0.7 0.5 33.1 65.4 0.0 0 52
47 221 8 971 125 114 0.0 0.5 0.5 31.9 45.6 0.0 0 52
48 218 8 869 125 104 0.0 0.9 0.5 30.0 56.0 0.0 0 48
49 214 8 999 153 140 0.0 0.8 0.5 30.4 46.4 0.0 0 52
50 210 8 798 192 139 0.0 1.0 0.5 28.9 50.0 0.0 0 52
51 206 8 860 125 157 0.0 1.2 0.5 31.5 26.9 0.0 0 52
52 203 8 893 186 127 5.9 0.9 0.5 26.4 42.3 0.0 0 46
53 199 8 863 126 141 0.0 1.2 0.5 32.5 44.4 0.0 0 44
54 196 8 788 97 133 0.0 0.9 0.5 37.5 40.0 0.0 0 50
55 192 8 926 119 116 0.0 0.6 0.5 26.1 55.3 0.0 0 52
56 189 8 789 162 107 0.0 0.8 0.5 25.2 40.4 0.0 0 48
57 186 8 878 107 128 0.0 1.1 0.5 23.1 34.0 0.0 0 52
58 182 8 775 105 122 0.0 0.8 0.5 25.5 57.4 0.0 0 50
59 179 8 747 94 129 0.0 0.7 0.5 34.3 37.3 0.0 0 50
60 176 8 845 96 138 0.0 0.6 0.5 28.3 41.7 0.0 0 52
61 173 8 961 121 110 0.0 0.6 0.5 29.0 52.6 0.0 0 48
62 170 4 911 110 109 0.0 0.9 0.5 33.5 33.3 0.0 0 48
63 167 8 656 109 109 0.0 0.8 0.5 21.9 44.7 0.0 0 52
64 164 8 934 117 105 0.0 0.8 0.5 15.5 50.0 0.0 0 52
65 161 8 972 125 95 0.0 0.8 0.5 24.4 50.0 0.0 0 50
66 158 8 894 125 101 0.0 0.9 0.5 27.2 35.9 0.0 0 52
67 155 8 798 146 129 0.0 1.0 0.5 22.8 58.7 0.0 0 52
68 153 8 901 183 92 0.0 1.1 0.5 23.6 34.5 0.0 0 52
69 150 8 977 197 103 0.0 1.4 0.5 23.6 36.8 0.0 0 52
70 147 8 905 262 93 0.0 1.5 0.5 20.3 63.4 0.0 0 52
71 145 8 995 148 122 0.0 1.9 0.5 20.9 35.3 0.0 0 52
72 142 8 934 230 99 0.0 1.6 0.5 20.0 65.9 0.0 0 52
73 140 8 862 173 100 0.0 1.8 0.5 26.8 46.8 0.0 0 52
74 137 8 924 139 90 0.0 1.7 0.5 16.8 42.5 0.0 0 52
75 135 8 888 168 113 0.0 1.6 0.5 22.9 40.4 0.0 0 52
76 133 8 712 212 84 0.0 1.6 0.5 13.4 46.9 0.0 0 52
77 130 8 868 210 91 0.0 1.7 0.5 17.7 51.2 0.0 0 52
78 128 8 952 307 92 0.0 1.9 0.5 19.7 44.9 0.0 0 50
79 126 8 801 157 107 0.0 2.2 0.5 15.8 39.0 0.0 0 52
80 123 8 849 147 93 0.0 2.1 0.5 15.6 51.4 0.0 0 52
81 121 8 799 154 86 0.0 1.9 0.5 12.2 50.0 0.0 0 52
82 119 8 941 213 82 0.0 1.8 0.5 19.5 41.2 0.0 0 50
83 117 8 751 268 94 0.0 2.0 0.5 20.8 42.6 0.0 0 50
84 115 8 828 198 102 0.0 2.2 0.5 15.5 59.5 0.0 0 52
85 113 8 898 266 123 0.0 2.2 0.5 13.2 85.2 0.0 0 52
86 111 8 943 190 93 0.0 2.4 0.5 19.5 45.1 0.0 0 52
87 109 8 864 183 65 0.0 2.4 0.5 14.9 31.8 0.0 0 52
88 107 8 793 203 93 0.0 2.4 0.5 11.8 35.3 0.0 0 52
89 105 8 752 162 74 1.2 2.4 0.5 13.1 21.4 0.0 0 52
90 103 8 801 149 77 0.0 2.3 0.5 9.7 58.3 0.0 0 52
91 102 8 901 230 99 0.0 2.2 0.5 16.0 25.5 0.0 0 52
92 100 8 826 201 87 0.0 2.4 0.5 12.8 45.7 0.0 0 52
93 98 8 810 196 83 0.0 2.5 0.5 14.0 24.4 0.0 0 52
94 96 8 857 209 68 1.0 2.5 0.5 11.5 27.0 5.1 0 52
95 95 8 771 174 91 0.0 2.6 0.5 10.5 26.5 0.0 0 52
96 93 8 955 210 59 0.0 2.6 0.5 10.0 36.7 0.7 0 52
97 91 8 833 206 53 0.0 2.7 0.5 10.2 19.4 1.4 0 52
98 90 8 888 229 86 0.0 2.8 0.5 8.1 36.0 0.0 0 52
99 88 8 794 186 91 1.0 2.9 0.5 8.3 25.0 0.5 0 52
100 81 8 756 170 72 1.0 2.9 0.5 6.0 23.8 7.0 0 52
101 74 8 791 176 67 0.0 2.9 0.5 4.4 58.3 4.0 0 52
102 67 8 813 213 43 0.0 3.0 0.5 7.0 150.0 4.2 0 52
103 62 8 779 245 39 0.0 3.1 0.5 3.2 16.7 13.0 0 52
104 56 8 767 303 63 0.0 3.2 0.5 4.1 20.0 0.7 0 52
105 52 8 757 270 57 0.0 3.5 0.5 6.4 3.7 0.5 0 52
106 47 8 763 283 41 0.0 3.7 0.5 4.5 0.0 0.0 0 52
107 43 8 768 283 36 0.0 3.7 0.5 2.9 18.2 3.6 0 52
108 39 8 804 283 25 0.0 3.7 0.5 3.1 0.0 6.2 0 52
109 36 8 781 283 24 0.0 3.7 0.5 3.6 6.7 6.7 0 52
110 33 8 738 298 42 0.0 3.7 0.5 3.3 15.4 3.5 0 52
111 30 8 761 298 36 0.0 3.7 0.5 2.2 0.0 4.3 0 52
112 27 8 769 298 37 0.0 3.7 0.5 0.9 0.0 2.2 0 52
113 25 8 745 298 31 0.0 3.7 0.5 1.5 0.0 6.6 0 52
114 23 8 753 298 16 0.0 3.7 0.5 1.3 0.0 2.8 0 52
115 21 8 745 298 11 0.0 3.7 0.5 1.5 0.0 14.0 0 52
116 19 8 747 298 21 0.0 3.7 0.5 2.1 0.0 5.8 0 52
117 13 8 737 298 12 0.0 3.7 0.5 1.0 0.0 10.0 0 52
118 9 8 736 298 4 0.0 3.7 0.5 1.5 0.0 18.5 0 52
119 0 8 739 298 0 0.0 3.7 0.5 1.8 0.0 18.0 0 52
120 0 8 732 298 0 0.0 3.7 0.5 1.2 0.0 21.8 0 52
121 0 8 732 19 -1 0.0 0.0 0.5 0.0 100.0 54.8
Initial Wiring Cost: 645 Final Wiring Cost: 732
############## Percent Wire Cost Reduction: -13
Initial Wire Length: 645 Final Wire Length: 732
************** Percent Wire Length Reduction: -13
Initial Horiz. Wire: 216 Final Horiz. Wire: 147
$$$$$$$$$$$ Percent H-Wire Length Reduction: 32
Initial Vert. Wire: 429 Final Vert. Wire: 585
@@@@@@@@@@@ Percent V-Wire Length Reduction: -36
Before Feeds are Added:
BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET
1 82 -20
2 86 -16
LONGEST Block is:2 Its length is:86
BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET
1 86 -16
2 86 -16
LONGEST Block is:1 Its length is:86
Added: 1 feed-through cells
Removed the cell overlaps --- Will do neighbor interchanges only now
TOTAL INTERCONNECT LENGTH: 994
OVERLAP PENALTY: 0
initialRowControl: 1.650
finalRowControl: 0.300
iter T Wire accept
122 0.001 976 16%
123 0.001 971 0%
124 0.001 971 0%
Total Feed-Alignment Movement (Pass 1): 0
Total Feed-Alignment Movement (Pass 2): 0
Total Feed-Alignment Movement (Pass 3): 0
Total Feed-Alignment Movement (Pass 4): 0
Total Feed-Alignment Movement (Pass 5): 0
Total Feed-Alignment Movement (Pass 6): 0
Total Feed-Alignment Movement (Pass 7): 0
Total Feed-Alignment Movement (Pass 8): 0
The rand generator seed was at globroute() : 987654321
Total Number of Net Segments: 9
Number of Switchable Net Segments: 0
Number of channels: 3
THIS IS THE ORIGINAL NUMBER OF TRACKS: 5
no. of accepted flips: 0
no. of attempted flips: 0
THIS IS THE NUMBER OF TRACKS: 5
FINAL NUMBER OF ROUTING TRACKS: 5
MAX OF CHANNEL: 1 is: 0
MAX OF CHANNEL: 2 is: 4
MAX OF CHANNEL: 3 is: 1
FINAL TOTAL INTERCONNECT LENGTH: 978
FINAL OVERLAP PENALTY: 0 FINAL VALUE OF TOTAL COST IS: 978
MAX NUMBER OF ATTEMPTED FLIPS PER T: 55
cost_scale_factor:3.90616
Number of Feed Thrus: 0
Number of Implicit Feed Thrus: 0
Statistics:
Number of Standard Cells: 10
Number of Pads: 0
Number of Nets: 15
Number of Pins: 46
Usage statistics not available

17
simulators/gem5/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.pin Normal file
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@ -0,0 +1,17 @@
$COUNT_1/$AND2_1/$ND2_1$Z 1 $COUNT_1/$AND2_1/$ND2_1 00#Z 17 52 2 1 0
$COUNT_1/$AND2_1/$ND2_1$Z 1 ACOUNT_1 00#A 15 26 2 -1 0
B7 2 $COUNT_1/$FJK3_2 00#K 25 78 3 -1 0
B7 2 $COUNT_1/$FJK3_2 00#J 23 78 3 -1 0
B7 3 $COUNT_1/$AND2_2/$ND2_1 00#A 9 26 2 -1 0
B7 3 ACOUNT_1 01#Z 17 26 2 -1 0
B6 5 $COUNT_1/$FJK3_1 00#K 25 26 2 -1 0
B6 5 $COUNT_1/$FJK3_1 00#J 23 26 2 -1 0
B6 5 $COUNT_1/$AND2_3/$IV_1 01#Z 7 26 2 -1 0
$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$FJK3_1 01#Q 81 26 2 -1 0
$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$AND2_1/$ND2_1 00#B 19 52 2 1 0
$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$FJK3_2 00#Q 81 52 2 1 0
$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$AND2_2/$ND2_1 01#B 11 26 2 -1 0
$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$ND2_1 00#Z 5 52 2 1 0
$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$IV_1 00#A 5 26 2 -1 0
$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$ND2_1 00#Z 7 52 2 1 0
$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$IV_1 00#A 3 26 2 -1 0

11
simulators/gem5/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.pl1 Normal file
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@ -0,0 +1,11 @@
$COUNT_1/$AND2_4/$IV_1 0 0 4 26 0 1
$COUNT_1/$AND2_3/$IV_1 4 0 8 26 2 1
$COUNT_1/$AND2_2/$ND2_1 8 0 14 26 0 1
ACOUNT_1 14 0 18 26 2 1
twfeed1 18 0 22 26 0 1
$COUNT_1/$FJK3_1 22 0 86 26 0 1
$COUNT_1/$AND2_3/$ND2_1 0 52 6 78 0 2
$COUNT_1/$AND2_4/$ND2_1 6 52 12 78 2 2
$COUNT_1/$AND2_2/$IV_1 12 52 16 78 2 2
$COUNT_1/$AND2_1/$ND2_1 16 52 22 78 2 2
$COUNT_1/$FJK3_2 22 52 86 78 0 2

2
simulators/gem5/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.pl2 Normal file
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@ -0,0 +1,2 @@
1 0 0 86 26 0 0
2 0 52 86 78 0 0

18
simulators/gem5/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.sav Normal file
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@ -0,0 +1,18 @@
0.009592
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1
0.000000
0.500000
3.906156
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2 2 0 34 65
3 2 2 63 65
4 1 0 59 13
5 1 2 32 13
6 2 0 23 65
7 1 2 12 13
8 2 0 6 65
9 1 0 70 13
10 2 0 70 65

19
simulators/gem5/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.sv2 Normal file
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@ -0,0 +1,19 @@
0.001000
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1 1 2 16 13
2 2 2 19 65
3 2 2 14 65
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5 1 2 6 13
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9 1 0 50 13
10 2 0 54 65
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29
simulators/gem5/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.twf Normal file
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@ -0,0 +1,29 @@
net 1
segment channel 2
pin1 1 pin2 7 0 0
net 2
segment channel 3
pin1 41 pin2 42 0 0
segment channel 2
pin1 12 pin2 3 0 0
net 3
segment channel 2
pin1 35 pin2 36 0 0
segment channel 2
pin1 19 pin2 35 0 0
net 4
segment channel 2
pin1 5 pin2 38 0 0
net 5
net 7
segment channel 2
pin1 14 pin2 43 0 0
net 8
segment channel 2
pin1 23 pin2 17 0 0
net 9
net 11
segment channel 2
pin1 25 pin2 31 0 0
net 14
net 15

682
simulators/gem5/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt Normal file
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@ -0,0 +1,682 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.023638 # Number of seconds simulated
sim_ticks 23638033500 # Number of ticks simulated
final_tick 23638033500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 160213 # Simulator instruction rate (inst/s)
host_op_rate 160213 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 44988546 # Simulator tick rate (ticks/s)
host_mem_usage 220112 # Number of bytes of host memory used
host_seconds 525.42 # Real time elapsed on the host
sim_insts 84179709 # Number of instructions simulated
sim_ops 84179709 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 197952 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 138112 # Number of bytes read from this memory
system.physmem.bytes_read::total 336064 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 197952 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 197952 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 3093 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 2158 # Number of read requests responded to by this memory
system.physmem.num_reads::total 5251 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 8374301 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 5842787 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 14217088 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 8374301 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 8374301 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 8374301 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 5842787 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 14217088 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 23223377 # DTB read hits
system.cpu.dtb.read_misses 198479 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 23421856 # DTB read accesses
system.cpu.dtb.write_hits 7079825 # DTB write hits
system.cpu.dtb.write_misses 1403 # DTB write misses
system.cpu.dtb.write_acv 5 # DTB write access violations
system.cpu.dtb.write_accesses 7081228 # DTB write accesses
system.cpu.dtb.data_hits 30303202 # DTB hits
system.cpu.dtb.data_misses 199882 # DTB misses
system.cpu.dtb.data_acv 5 # DTB access violations
system.cpu.dtb.data_accesses 30503084 # DTB accesses
system.cpu.itb.fetch_hits 14943347 # ITB hits
system.cpu.itb.fetch_misses 91 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 14943438 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 389 # Number of system calls
system.cpu.numCycles 47276068 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.BPredUnit.lookups 15033034 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 10893927 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 965097 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 8612659 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 7067377 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 1490279 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 6040 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 15621230 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 128217007 # Number of instructions fetch has processed
system.cpu.fetch.Branches 15033034 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 8557656 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 22378884 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 4633381 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 5548401 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 48 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 1854 # Number of stall cycles due to pending traps
system.cpu.fetch.CacheLines 14943347 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 336798 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 47185446 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.717300 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.373013 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 24806562 52.57% 52.57% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 2389979 5.07% 57.64% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 1207538 2.56% 60.20% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 1775063 3.76% 63.96% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 2802024 5.94% 69.90% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 1169800 2.48% 72.38% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 1228019 2.60% 74.98% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 790135 1.67% 76.65% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 11016326 23.35% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 47185446 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.317984 # Number of branch fetches per cycle
system.cpu.fetch.rate 2.712091 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 17463925 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 4249040 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 20759249 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 1090184 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 3623048 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 2545357 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 12255 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 125130253 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 31826 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 3623048 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 18629909 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 965094 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 8920 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 20661182 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 3297293 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 122152175 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 11 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 401388 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 2422623 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenamedOperands 89685518 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 158620062 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 148881837 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 9738225 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 68427361 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 21258157 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 1427 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 1434 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 8739521 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 25557847 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 8301356 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 2609711 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 904973 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 106143007 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 2358 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 96975947 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 189226 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 21491456 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 16142477 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 1969 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 47185446 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 2.055209 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.876136 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 12454883 26.40% 26.40% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 9420722 19.97% 46.36% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 8458741 17.93% 64.29% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 6315379 13.38% 77.67% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 4948925 10.49% 88.16% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 2846998 6.03% 94.19% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 1728154 3.66% 97.86% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 801160 1.70% 99.55% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 210484 0.45% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 47185446 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 186828 11.91% 11.91% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 11.91% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 11.91% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 238 0.02% 11.93% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.93% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 7150 0.46% 12.38% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 5464 0.35% 12.73% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 842994 53.75% 66.48% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 66.48% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 66.48% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 66.48% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 66.48% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 66.48% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 66.48% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 66.48% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 66.48% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.48% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 66.48% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.48% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.48% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 66.48% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.48% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 66.48% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 66.48% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 66.48% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 66.48% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 66.48% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 66.48% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.48% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 446294 28.45% 94.93% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 79499 5.07% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 7 0.00% 0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 58979048 60.82% 60.82% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 480591 0.50% 61.31% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.31% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 2800978 2.89% 64.20% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 115548 0.12% 64.32% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 2385848 2.46% 66.78% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 311419 0.32% 67.10% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 759609 0.78% 67.89% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 319 0.00% 67.89% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.89% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.89% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.89% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.89% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.89% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.89% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.89% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.89% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.89% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.89% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.89% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.89% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.89% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.89% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.89% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.89% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.89% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.89% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.89% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.89% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 23970757 24.72% 92.60% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 7171823 7.40% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 96975947 # Type of FU issued
system.cpu.iq.rate 2.051269 # Inst issue rate
system.cpu.iq.fu_busy_cnt 1568467 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.016174 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 227768377 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 118855856 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 87353688 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 15126656 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 8815414 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 7066282 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 90552040 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 7992367 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 1520027 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 5561649 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 19937 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 34563 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 1800253 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 10514 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 3 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 3623048 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 133924 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 17201 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 116441723 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 394323 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 25557847 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 8301356 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 2358 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 2853 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 36 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 34563 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 569788 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 508452 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 1078240 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 95678343 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 23422851 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 1297604 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 10296358 # number of nop insts executed
system.cpu.iew.exec_refs 30504278 # number of memory reference insts executed
system.cpu.iew.exec_branches 12076445 # Number of branches executed
system.cpu.iew.exec_stores 7081427 # Number of stores executed
system.cpu.iew.exec_rate 2.023822 # Inst execution rate
system.cpu.iew.wb_sent 94963988 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 94419970 # cumulative count of insts written-back
system.cpu.iew.wb_producers 64608180 # num instructions producing a value
system.cpu.iew.wb_consumers 89987821 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 1.997204 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.717966 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitCommittedInsts 91903055 # The number of committed instructions
system.cpu.commit.commitCommittedOps 91903055 # The number of committed instructions
system.cpu.commit.commitSquashedInsts 24539814 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 953116 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 43562398 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 2.109688 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.736301 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 17041146 39.12% 39.12% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 9957627 22.86% 61.98% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 4507142 10.35% 72.32% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 2283698 5.24% 77.57% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 1617573 3.71% 81.28% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 1122316 2.58% 83.86% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 722162 1.66% 85.51% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 820666 1.88% 87.40% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 5490068 12.60% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 43562398 # Number of insts commited each cycle
system.cpu.commit.committedInsts 91903055 # Number of instructions committed
system.cpu.commit.committedOps 91903055 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 26497301 # Number of memory references committed
system.cpu.commit.loads 19996198 # Number of loads committed
system.cpu.commit.membars 0 # Number of memory barriers committed
system.cpu.commit.branches 10240685 # Number of branches committed
system.cpu.commit.fp_insts 6862061 # Number of committed floating point instructions.
system.cpu.commit.int_insts 79581076 # Number of committed integer instructions.
system.cpu.commit.function_calls 1029620 # Number of function calls committed.
system.cpu.commit.bw_lim_events 5490068 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 154514159 # The number of ROB reads
system.cpu.rob.rob_writes 236533126 # The number of ROB writes
system.cpu.timesIdled 2183 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 90622 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 84179709 # Number of Instructions Simulated
system.cpu.committedOps 84179709 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 84179709 # Number of Instructions Simulated
system.cpu.cpi 0.561609 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.561609 # CPI: Total CPI of All Threads
system.cpu.ipc 1.780599 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.780599 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 129442497 # number of integer regfile reads
system.cpu.int_regfile_writes 70765525 # number of integer regfile writes
system.cpu.fp_regfile_reads 6190739 # number of floating regfile reads
system.cpu.fp_regfile_writes 6047859 # number of floating regfile writes
system.cpu.misc_regfile_reads 714278 # number of misc regfile reads
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
system.cpu.icache.replacements 10359 # number of replacements
system.cpu.icache.tagsinuse 1607.190165 # Cycle average of tags in use
system.cpu.icache.total_refs 14929668 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 12297 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 1214.090266 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 1607.190165 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.784761 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.784761 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 14929668 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 14929668 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 14929668 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 14929668 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 14929668 # number of overall hits
system.cpu.icache.overall_hits::total 14929668 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 13679 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 13679 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 13679 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 13679 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 13679 # number of overall misses
system.cpu.icache.overall_misses::total 13679 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 203969000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 203969000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 203969000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 203969000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 203969000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 203969000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 14943347 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 14943347 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 14943347 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 14943347 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 14943347 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 14943347 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000915 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000915 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000915 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000915 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000915 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000915 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14911.104613 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 14911.104613 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 14911.104613 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 14911.104613 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 14911.104613 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 14911.104613 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1382 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 1382 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 1382 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 1382 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 1382 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 1382 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 12297 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 12297 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 12297 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 12297 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 12297 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 12297 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 130905500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 130905500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 130905500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 130905500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 130905500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 130905500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000823 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000823 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000823 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000823 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000823 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000823 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 10645.319997 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 10645.319997 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 10645.319997 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 10645.319997 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 10645.319997 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 10645.319997 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 158 # number of replacements
system.cpu.dcache.tagsinuse 1455.343539 # Cycle average of tags in use
system.cpu.dcache.total_refs 28184934 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 2238 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 12593.804290 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 1455.343539 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.355308 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.355308 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 21691339 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 21691339 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 6493048 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 6493048 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 547 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 547 # number of LoadLockedReq hits
system.cpu.dcache.demand_hits::cpu.data 28184387 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 28184387 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 28184387 # number of overall hits
system.cpu.dcache.overall_hits::total 28184387 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 946 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 946 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 8055 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 8055 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data 9001 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 9001 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 9001 # number of overall misses
system.cpu.dcache.overall_misses::total 9001 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 28453500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 28453500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 289283500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 289283500 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 38000 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 38000 # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 317737000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 317737000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 317737000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 317737000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 21692285 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 21692285 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 548 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 548 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 28193388 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 28193388 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 28193388 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 28193388 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000044 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.000044 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001239 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.001239 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001825 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001825 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.000319 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.000319 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.000319 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.000319 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30077.695560 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 30077.695560 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35913.531968 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 35913.531968 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 38000 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 38000 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 35300.188868 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 35300.188868 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 35300.188868 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 35300.188868 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 6500 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 6500 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 108 # number of writebacks
system.cpu.dcache.writebacks::total 108 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 435 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 435 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6329 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 6329 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 6764 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 6764 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 6764 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 6764 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 511 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 511 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1726 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 1726 # number of WriteReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 2237 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 2237 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 2237 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 2237 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 16444500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 16444500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 61474000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 61474000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 35000 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 35000 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 77918500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 77918500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 77918500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 77918500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000265 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000265 # mshr miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.001825 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.001825 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000079 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.000079 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000079 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.000079 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 32181.017613 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 32181.017613 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35616.454229 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35616.454229 # average WriteReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 35000 # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 35000 # average LoadLockedReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34831.694233 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 34831.694233 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34831.694233 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 34831.694233 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 2429.489974 # Cycle average of tags in use
system.cpu.l2cache.total_refs 9270 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 3617 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 2.562897 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 17.697251 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 2033.991651 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 377.801072 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.000540 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.062072 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.011530 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.074142 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 9204 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 54 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 9258 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 108 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 108 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 26 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 26 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst 9204 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 80 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 9284 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 9204 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 80 # number of overall hits
system.cpu.l2cache.overall_hits::total 9284 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 3093 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 458 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 3551 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 1700 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 1700 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 3093 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 2158 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 5251 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 3093 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 2158 # number of overall misses
system.cpu.l2cache.overall_misses::total 5251 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 106153500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 15762000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 121915500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 59022000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 59022000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 106153500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 74784000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 180937500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 106153500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 74784000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 180937500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 12297 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 512 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 12809 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 108 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 108 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1726 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 1726 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 12297 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 2238 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 14535 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 12297 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 2238 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 14535 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.251525 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.894531 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.277227 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.984936 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.984936 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.251525 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.964254 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.361266 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.251525 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.964254 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.361266 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34320.562561 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34414.847162 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 34332.723177 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34718.823529 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34718.823529 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34320.562561 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34654.309546 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 34457.722339 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34320.562561 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34654.309546 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 34457.722339 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 2000 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 2000 # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3093 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 458 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 3551 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1700 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 1700 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 3093 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 2158 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 5251 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3093 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 2158 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 5251 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 96110500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 14313000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 110423500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 53634000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 53634000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 96110500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 67947000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 164057500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 96110500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 67947000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 164057500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.251525 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.894531 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.277227 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.984936 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.984936 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.251525 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964254 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.361266 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.251525 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964254 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.361266 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31073.553185 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31251.091703 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31096.451704 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31549.411765 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31549.411765 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31073.553185 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31486.098239 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31243.096553 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31073.553185 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31486.098239 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31243.096553 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

117
simulators/gem5/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/config.ini Normal file
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@ -0,0 +1,117 @@
[root]
type=Root
children=system
full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
boot_osflags=a
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
readfile=
symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.cpu]
type=AtomicSimpleCPU
children=dtb interrupts itb tracer workload
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
fastmem=false
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
phase=0
profile=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
system=system
tracer=system.cpu.tracer
width=1
workload=system.cpu.workload
dcache_port=system.membus.slave[2]
icache_port=system.membus.slave[1]
[system.cpu.dtb]
type=AlphaTLB
size=64
[system.cpu.interrupts]
type=AlphaInterrupts
[system.cpu.itb]
type=AlphaTLB
size=48
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=twolf smred
cwd=build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-atomic
egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf
gid=100
input=cin
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=0
system=system
uid=100
[system.membus]
type=CoherentBus
block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
master=system.physmem.port[0]
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
[system.physmem]
type=SimpleMemory
conf_table_reported=false
file=
in_addr_map=true
latency=30000
latency_var=0
null=false
range=0:134217727
zero=false
port=system.membus.master[0]

7
simulators/gem5/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/simerr Executable file
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@ -0,0 +1,7 @@
warn: CoherentBus system.membus has no snooping ports attached!
warn: Sockets disabled, not accepting gdb connections
warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
hack: be nice to actually delete the event here

26
simulators/gem5/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/simout Executable file
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@ -0,0 +1,26 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 4 2012 11:50:11
gem5 started Jun 4 2012 13:46:55
gem5 executing on zizzer
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-atomic
Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-atomic/smred.sav
Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-atomic/smred.sv2
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
Standard Cell Placement and Global Routing Program
Authors: Carl Sechen, Bill Swartz
Yale University
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
61 62 63 64 65 66 67 68 69 70 71 72 73 74 75
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
122 123 124 Exiting @ tick 45951567500 because target called exit()

276
simulators/gem5/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.out Normal file
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@ -0,0 +1,276 @@
TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
Standard Cell Placement and Global Routing Program
Authors: Carl Sechen, Bill Swartz
Yale University
NOTE: Restart file .rs2 not used
TimberWolf will perform a global route step
rowSep: 1.000000
feedThruWidth: 4
******************
BLOCK DATA
block:1 desire:85
block:2 desire:85
Total Desired Length: 170
total cell length: 168
total block length: 168
block x-span:84 block y-span:78
implicit feed thru range: -84
Using default value of bin.penalty.control:1.000000
numBins automatically set to:5
binWidth = average_cell_width + 0 sigma= 17
average_cell_width is:16
standard deviation of cell length is:23.6305
TimberWolfSC starting from the beginning
THIS IS THE ROUTE COST OF THE ORIGINAL PLACEMENT: 645
The number of nets with 1 pin is 4
The number of nets with 2 pin is 9
The number of nets with 3 pin is 0
The number of nets with 4 pin is 2
The number of nets with 5 pin is 0
The number of nets with 6 pin is 0
The number of nets with 7 pin is 0
The number of nets with 8 pin is 0
The number of nets with 9 pin is 0
The number of nets with 10 pin or more is 0
New Cost Function: Initial Horizontal Cost:242
New Cost Function: FEEDS:0 MISSING_ROWS:-46
bdxlen:86 bdylen:78
l:0 t:78 r:86 b:0
THIS IS THE ROUTE COST OF THE CURRENT PLACEMENT: 645
THIS IS THE PENALTY OF THE CURRENT PLACEMENT: 44
The rand generator seed was at utemp() : 1
tempfile[0][0] = 0.982500 tempfile[0][1] = 90.000000
tempfile[1][0] = 0.915000 tempfile[1][1] = 20.000000
tempfile[2][0] = 0.700000 tempfile[2][1] = 10.000000
tempfile[3][0] = 0.100000 tempfile[3][1] = 0.000000
I T fds Wire Penalty P_lim Epct binC rowC acc s/p early FDs MRs
1 500 0 929 592 160 30.0 1.0 3.0 84.2 34.7 0.0 0 40
2 491 0 876 106 726 0.0 0.8 2.5 80.0 18.5 0.0 0 46
3 482 0 822 273 372 0.0 0.5 1.5 80.8 21.3 0.0 0 46
4 474 0 826 53 247 0.0 0.5 0.9 65.0 21.9 0.0 0 48
5 465 8 987 73 190 0.0 0.5 0.5 50.0 38.3 0.0 0 46
6 457 8 851 67 226 0.0 0.5 0.5 53.8 42.9 0.0 0 52
7 449 8 1067 108 190 0.0 0.5 0.5 46.2 53.8 0.0 0 50
8 441 8 918 106 171 0.0 0.5 0.5 47.1 40.4 0.0 0 48
9 434 8 812 101 197 0.0 0.5 0.5 53.6 21.0 0.0 0 48
10 426 8 1038 121 181 0.0 0.5 0.5 43.6 27.1 0.0 0 48
11 419 8 898 93 187 0.0 0.5 0.5 45.3 47.8 0.0 0 50
12 411 4 857 94 240 0.0 0.5 0.5 62.7 51.6 0.0 0 44
13 404 8 1043 88 185 0.0 0.5 0.5 54.0 52.8 0.0 0 50
14 397 8 767 94 154 0.0 0.5 0.5 33.8 35.0 0.0 0 50
15 390 8 862 89 183 0.0 0.5 0.5 55.6 29.0 0.0 0 46
16 383 4 798 79 173 0.0 0.5 0.5 57.5 35.3 0.0 0 52
17 376 8 827 100 152 0.0 0.5 0.5 35.3 81.8 0.0 0 50
18 370 8 878 101 208 0.0 0.5 0.5 44.7 46.2 0.0 0 48
19 363 4 921 67 167 0.0 0.5 0.5 57.1 34.7 0.0 0 48
20 357 8 933 93 154 0.0 0.5 0.5 46.5 43.6 0.0 0 52
21 351 8 930 89 147 0.0 0.5 0.5 39.4 36.5 0.0 0 52
22 345 8 951 79 142 0.0 0.5 0.5 32.8 51.3 0.0 0 50
23 339 8 1046 87 207 0.0 0.5 0.5 52.8 61.0 0.0 0 48
24 333 4 989 96 185 0.0 0.5 0.5 45.3 43.3 0.0 0 42
25 327 4 577 86 157 0.0 0.5 0.5 31.1 55.3 0.0 0 52
26 321 8 776 97 174 0.0 0.5 0.5 47.9 62.5 0.0 0 52
27 315 8 850 81 188 0.0 0.5 0.5 45.0 55.2 0.0 0 50
28 310 8 898 97 148 0.0 0.5 0.5 43.0 45.8 0.0 0 48
29 304 8 889 65 173 0.0 0.5 0.5 32.5 41.3 0.0 0 50
30 299 8 858 81 153 0.0 0.5 0.5 44.3 29.2 0.0 0 46
31 294 8 871 82 187 0.0 0.5 0.5 45.7 47.7 0.0 0 48
32 289 8 782 109 173 0.0 0.5 0.5 35.2 57.4 0.0 0 48
33 284 8 743 98 189 0.0 0.6 0.5 41.8 64.3 0.0 0 52
34 279 8 943 90 147 0.0 0.5 0.5 38.6 32.8 0.0 0 48
35 274 8 907 57 166 0.0 0.5 0.5 33.6 51.0 0.0 0 48
36 269 8 900 70 148 0.0 0.5 0.5 45.0 41.4 0.0 0 50
37 264 4 875 106 133 0.0 0.5 0.5 31.7 55.3 0.0 0 52
38 260 8 1023 145 149 0.0 0.6 0.5 28.7 65.0 0.0 0 52
39 255 8 801 151 173 0.0 0.9 0.5 41.7 41.2 0.0 0 48
40 251 8 741 104 159 0.0 0.8 0.5 36.3 47.5 0.0 0 48
41 246 8 828 108 149 0.0 0.5 0.5 34.6 50.9 0.0 0 50
42 242 8 947 128 132 0.0 0.7 0.5 34.2 39.0 0.0 0 50
43 238 8 917 101 142 0.0 0.8 0.5 34.4 50.9 0.0 0 48
44 234 8 761 86 129 0.0 0.5 0.5 42.0 36.4 0.0 0 52
45 229 8 979 106 137 0.0 0.5 0.5 29.2 55.3 0.0 0 50
46 225 8 806 74 130 0.0 0.7 0.5 33.1 65.4 0.0 0 52
47 221 8 971 125 114 0.0 0.5 0.5 31.9 45.6 0.0 0 52
48 218 8 869 125 104 0.0 0.9 0.5 30.0 56.0 0.0 0 48
49 214 8 999 153 140 0.0 0.8 0.5 30.4 46.4 0.0 0 52
50 210 8 798 192 139 0.0 1.0 0.5 28.9 50.0 0.0 0 52
51 206 8 860 125 157 0.0 1.2 0.5 31.5 26.9 0.0 0 52
52 203 8 893 186 127 5.9 0.9 0.5 26.4 42.3 0.0 0 46
53 199 8 863 126 141 0.0 1.2 0.5 32.5 44.4 0.0 0 44
54 196 8 788 97 133 0.0 0.9 0.5 37.5 40.0 0.0 0 50
55 192 8 926 119 116 0.0 0.6 0.5 26.1 55.3 0.0 0 52
56 189 8 789 162 107 0.0 0.8 0.5 25.2 40.4 0.0 0 48
57 186 8 878 107 128 0.0 1.1 0.5 23.1 34.0 0.0 0 52
58 182 8 775 105 122 0.0 0.8 0.5 25.5 57.4 0.0 0 50
59 179 8 747 94 129 0.0 0.7 0.5 34.3 37.3 0.0 0 50
60 176 8 845 96 138 0.0 0.6 0.5 28.3 41.7 0.0 0 52
61 173 8 961 121 110 0.0 0.6 0.5 29.0 52.6 0.0 0 48
62 170 4 911 110 109 0.0 0.9 0.5 33.5 33.3 0.0 0 48
63 167 8 656 109 109 0.0 0.8 0.5 21.9 44.7 0.0 0 52
64 164 8 934 117 105 0.0 0.8 0.5 15.5 50.0 0.0 0 52
65 161 8 972 125 95 0.0 0.8 0.5 24.4 50.0 0.0 0 50
66 158 8 894 125 101 0.0 0.9 0.5 27.2 35.9 0.0 0 52
67 155 8 798 146 129 0.0 1.0 0.5 22.8 58.7 0.0 0 52
68 153 8 901 183 92 0.0 1.1 0.5 23.6 34.5 0.0 0 52
69 150 8 977 197 103 0.0 1.4 0.5 23.6 36.8 0.0 0 52
70 147 8 905 262 93 0.0 1.5 0.5 20.3 63.4 0.0 0 52
71 145 8 995 148 122 0.0 1.9 0.5 20.9 35.3 0.0 0 52
72 142 8 934 230 99 0.0 1.6 0.5 20.0 65.9 0.0 0 52
73 140 8 862 173 100 0.0 1.8 0.5 26.8 46.8 0.0 0 52
74 137 8 924 139 90 0.0 1.7 0.5 16.8 42.5 0.0 0 52
75 135 8 888 168 113 0.0 1.6 0.5 22.9 40.4 0.0 0 52
76 133 8 712 212 84 0.0 1.6 0.5 13.4 46.9 0.0 0 52
77 130 8 868 210 91 0.0 1.7 0.5 17.7 51.2 0.0 0 52
78 128 8 952 307 92 0.0 1.9 0.5 19.7 44.9 0.0 0 50
79 126 8 801 157 107 0.0 2.2 0.5 15.8 39.0 0.0 0 52
80 123 8 849 147 93 0.0 2.1 0.5 15.6 51.4 0.0 0 52
81 121 8 799 154 86 0.0 1.9 0.5 12.2 50.0 0.0 0 52
82 119 8 941 213 82 0.0 1.8 0.5 19.5 41.2 0.0 0 50
83 117 8 751 268 94 0.0 2.0 0.5 20.8 42.6 0.0 0 50
84 115 8 828 198 102 0.0 2.2 0.5 15.5 59.5 0.0 0 52
85 113 8 898 266 123 0.0 2.2 0.5 13.2 85.2 0.0 0 52
86 111 8 943 190 93 0.0 2.4 0.5 19.5 45.1 0.0 0 52
87 109 8 864 183 65 0.0 2.4 0.5 14.9 31.8 0.0 0 52
88 107 8 793 203 93 0.0 2.4 0.5 11.8 35.3 0.0 0 52
89 105 8 752 162 74 1.2 2.4 0.5 13.1 21.4 0.0 0 52
90 103 8 801 149 77 0.0 2.3 0.5 9.7 58.3 0.0 0 52
91 102 8 901 230 99 0.0 2.2 0.5 16.0 25.5 0.0 0 52
92 100 8 826 201 87 0.0 2.4 0.5 12.8 45.7 0.0 0 52
93 98 8 810 196 83 0.0 2.5 0.5 14.0 24.4 0.0 0 52
94 96 8 857 209 68 1.0 2.5 0.5 11.5 27.0 5.1 0 52
95 95 8 771 174 91 0.0 2.6 0.5 10.5 26.5 0.0 0 52
96 93 8 955 210 59 0.0 2.6 0.5 10.0 36.7 0.7 0 52
97 91 8 833 206 53 0.0 2.7 0.5 10.2 19.4 1.4 0 52
98 90 8 888 229 86 0.0 2.8 0.5 8.1 36.0 0.0 0 52
99 88 8 794 186 91 1.0 2.9 0.5 8.3 25.0 0.5 0 52
100 81 8 756 170 72 1.0 2.9 0.5 6.0 23.8 7.0 0 52
101 74 8 791 176 67 0.0 2.9 0.5 4.4 58.3 4.0 0 52
102 67 8 813 213 43 0.0 3.0 0.5 7.0 150.0 4.2 0 52
103 62 8 779 245 39 0.0 3.1 0.5 3.2 16.7 13.0 0 52
104 56 8 767 303 63 0.0 3.2 0.5 4.1 20.0 0.7 0 52
105 52 8 757 270 57 0.0 3.5 0.5 6.4 3.7 0.5 0 52
106 47 8 763 283 41 0.0 3.7 0.5 4.5 0.0 0.0 0 52
107 43 8 768 283 36 0.0 3.7 0.5 2.9 18.2 3.6 0 52
108 39 8 804 283 25 0.0 3.7 0.5 3.1 0.0 6.2 0 52
109 36 8 781 283 24 0.0 3.7 0.5 3.6 6.7 6.7 0 52
110 33 8 738 298 42 0.0 3.7 0.5 3.3 15.4 3.5 0 52
111 30 8 761 298 36 0.0 3.7 0.5 2.2 0.0 4.3 0 52
112 27 8 769 298 37 0.0 3.7 0.5 0.9 0.0 2.2 0 52
113 25 8 745 298 31 0.0 3.7 0.5 1.5 0.0 6.6 0 52
114 23 8 753 298 16 0.0 3.7 0.5 1.3 0.0 2.8 0 52
115 21 8 745 298 11 0.0 3.7 0.5 1.5 0.0 14.0 0 52
116 19 8 747 298 21 0.0 3.7 0.5 2.1 0.0 5.8 0 52
117 13 8 737 298 12 0.0 3.7 0.5 1.0 0.0 10.0 0 52
118 9 8 736 298 4 0.0 3.7 0.5 1.5 0.0 18.5 0 52
119 0 8 739 298 0 0.0 3.7 0.5 1.8 0.0 18.0 0 52
120 0 8 732 298 0 0.0 3.7 0.5 1.2 0.0 21.8 0 52
121 0 8 732 19 -1 0.0 0.0 0.5 0.0 100.0 54.8
Initial Wiring Cost: 645 Final Wiring Cost: 732
############## Percent Wire Cost Reduction: -13
Initial Wire Length: 645 Final Wire Length: 732
************** Percent Wire Length Reduction: -13
Initial Horiz. Wire: 216 Final Horiz. Wire: 147
$$$$$$$$$$$ Percent H-Wire Length Reduction: 32
Initial Vert. Wire: 429 Final Vert. Wire: 585
@@@@@@@@@@@ Percent V-Wire Length Reduction: -36
Before Feeds are Added:
BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET
1 82 -20
2 86 -16
LONGEST Block is:2 Its length is:86
BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET
1 86 -16
2 86 -16
LONGEST Block is:1 Its length is:86
Added: 1 feed-through cells
Removed the cell overlaps --- Will do neighbor interchanges only now
TOTAL INTERCONNECT LENGTH: 994
OVERLAP PENALTY: 0
initialRowControl: 1.650
finalRowControl: 0.300
iter T Wire accept
122 0.001 976 16%
123 0.001 971 0%
124 0.001 971 0%
Total Feed-Alignment Movement (Pass 1): 0
Total Feed-Alignment Movement (Pass 2): 0
Total Feed-Alignment Movement (Pass 3): 0
Total Feed-Alignment Movement (Pass 4): 0
Total Feed-Alignment Movement (Pass 5): 0
Total Feed-Alignment Movement (Pass 6): 0
Total Feed-Alignment Movement (Pass 7): 0
Total Feed-Alignment Movement (Pass 8): 0
The rand generator seed was at globroute() : 987654321
Total Number of Net Segments: 9
Number of Switchable Net Segments: 0
Number of channels: 3
THIS IS THE ORIGINAL NUMBER OF TRACKS: 5
no. of accepted flips: 0
no. of attempted flips: 0
THIS IS THE NUMBER OF TRACKS: 5
FINAL NUMBER OF ROUTING TRACKS: 5
MAX OF CHANNEL: 1 is: 0
MAX OF CHANNEL: 2 is: 4
MAX OF CHANNEL: 3 is: 1
FINAL TOTAL INTERCONNECT LENGTH: 978
FINAL OVERLAP PENALTY: 0 FINAL VALUE OF TOTAL COST IS: 978
MAX NUMBER OF ATTEMPTED FLIPS PER T: 55
cost_scale_factor:3.90616
Number of Feed Thrus: 0
Number of Implicit Feed Thrus: 0
Statistics:
Number of Standard Cells: 10
Number of Pads: 0
Number of Nets: 15
Number of Pins: 46
Usage statistics not available

17
simulators/gem5/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.pin Normal file
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@ -0,0 +1,17 @@
$COUNT_1/$AND2_1/$ND2_1$Z 1 $COUNT_1/$AND2_1/$ND2_1 00#Z 17 52 2 1 0
$COUNT_1/$AND2_1/$ND2_1$Z 1 ACOUNT_1 00#A 15 26 2 -1 0
B7 2 $COUNT_1/$FJK3_2 00#K 25 78 3 -1 0
B7 2 $COUNT_1/$FJK3_2 00#J 23 78 3 -1 0
B7 3 $COUNT_1/$AND2_2/$ND2_1 00#A 9 26 2 -1 0
B7 3 ACOUNT_1 01#Z 17 26 2 -1 0
B6 5 $COUNT_1/$FJK3_1 00#K 25 26 2 -1 0
B6 5 $COUNT_1/$FJK3_1 00#J 23 26 2 -1 0
B6 5 $COUNT_1/$AND2_3/$IV_1 01#Z 7 26 2 -1 0
$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$FJK3_1 01#Q 81 26 2 -1 0
$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$AND2_1/$ND2_1 00#B 19 52 2 1 0
$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$FJK3_2 00#Q 81 52 2 1 0
$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$AND2_2/$ND2_1 01#B 11 26 2 -1 0
$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$ND2_1 00#Z 5 52 2 1 0
$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$IV_1 00#A 5 26 2 -1 0
$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$ND2_1 00#Z 7 52 2 1 0
$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$IV_1 00#A 3 26 2 -1 0

11
simulators/gem5/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.pl1 Normal file
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@ -0,0 +1,11 @@
$COUNT_1/$AND2_4/$IV_1 0 0 4 26 0 1
$COUNT_1/$AND2_3/$IV_1 4 0 8 26 2 1
$COUNT_1/$AND2_2/$ND2_1 8 0 14 26 0 1
ACOUNT_1 14 0 18 26 2 1
twfeed1 18 0 22 26 0 1
$COUNT_1/$FJK3_1 22 0 86 26 0 1
$COUNT_1/$AND2_3/$ND2_1 0 52 6 78 0 2
$COUNT_1/$AND2_4/$ND2_1 6 52 12 78 2 2
$COUNT_1/$AND2_2/$IV_1 12 52 16 78 2 2
$COUNT_1/$AND2_1/$ND2_1 16 52 22 78 2 2
$COUNT_1/$FJK3_2 22 52 86 78 0 2

2
simulators/gem5/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.pl2 Normal file
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@ -0,0 +1,2 @@
1 0 0 86 26 0 0
2 0 52 86 78 0 0

18
simulators/gem5/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.sav Normal file
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@ -0,0 +1,18 @@
0.009592
121
0
1
0.000000
0.500000
3.906156
1
1 1 2 37 13
2 2 0 34 65
3 2 2 63 65
4 1 0 59 13
5 1 2 32 13
6 2 0 23 65
7 1 2 12 13
8 2 0 6 65
9 1 0 70 13
10 2 0 70 65

19
simulators/gem5/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.sv2 Normal file
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@ -0,0 +1,19 @@
0.001000
123
0
2
0.000000
0.500000
3.906156
1
1 1 2 16 13
2 2 2 19 65
3 2 2 14 65
4 1 0 11 13
5 1 2 6 13
6 2 0 3 65
7 1 0 2 13
8 2 2 9 65
9 1 0 50 13
10 2 0 54 65
11 1 0 84 13

29
simulators/gem5/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.twf Normal file
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@ -0,0 +1,29 @@
net 1
segment channel 2
pin1 1 pin2 7 0 0
net 2
segment channel 3
pin1 41 pin2 42 0 0
segment channel 2
pin1 12 pin2 3 0 0
net 3
segment channel 2
pin1 35 pin2 36 0 0
segment channel 2
pin1 19 pin2 35 0 0
net 4
segment channel 2
pin1 5 pin2 38 0 0
net 5
net 7
segment channel 2
pin1 14 pin2 43 0 0
net 8
segment channel 2
pin1 23 pin2 17 0 0
net 9
net 11
segment channel 2
pin1 25 pin2 31 0 0
net 14
net 15

92
simulators/gem5/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt Normal file
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@ -0,0 +1,92 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.045952 # Number of seconds simulated
sim_ticks 45951567500 # Number of ticks simulated
final_tick 45951567500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 3561938 # Simulator instruction rate (inst/s)
host_op_rate 3561935 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1780967913 # Simulator tick rate (ticks/s)
host_mem_usage 209744 # Number of bytes of host memory used
host_seconds 25.80 # Real time elapsed on the host
sim_insts 91903056 # Number of instructions simulated
sim_ops 91903056 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 367612356 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 108337521 # Number of bytes read from this memory
system.physmem.bytes_read::total 475949877 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 367612356 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 367612356 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 30920974 # Number of bytes written to this memory
system.physmem.bytes_written::total 30920974 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 91903089 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 19996198 # Number of read requests responded to by this memory
system.physmem.num_reads::total 111899287 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 6501103 # Number of write requests responded to by this memory
system.physmem.num_writes::total 6501103 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 7999995996 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 2357645819 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 10357641815 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 7999995996 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 7999995996 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 672903574 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 672903574 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 7999995996 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 3030549393 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 11030545389 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 19996198 # DTB read hits
system.cpu.dtb.read_misses 10 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 19996208 # DTB read accesses
system.cpu.dtb.write_hits 6501103 # DTB write hits
system.cpu.dtb.write_misses 23 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 6501126 # DTB write accesses
system.cpu.dtb.data_hits 26497301 # DTB hits
system.cpu.dtb.data_misses 33 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 26497334 # DTB accesses
system.cpu.itb.fetch_hits 91903089 # ITB hits
system.cpu.itb.fetch_misses 47 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 91903136 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 389 # Number of system calls
system.cpu.numCycles 91903136 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 91903056 # Number of instructions committed
system.cpu.committedOps 91903056 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 79581109 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 6862064 # Number of float alu accesses
system.cpu.num_func_calls 2059216 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 7465012 # number of instructions that are conditional controls
system.cpu.num_int_insts 79581109 # number of integer instructions
system.cpu.num_fp_insts 6862064 # number of float instructions
system.cpu.num_int_register_reads 115028592 # number of times the integer registers were read
system.cpu.num_int_register_writes 62575473 # number of times the integer registers were written
system.cpu.num_fp_register_reads 6071661 # number of times the floating registers were read
system.cpu.num_fp_register_writes 5851888 # number of times the floating registers were written
system.cpu.num_mem_refs 26497334 # number of memory refs
system.cpu.num_load_insts 19996208 # Number of load instructions
system.cpu.num_store_insts 6501126 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 91903136 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
---------- End Simulation Statistics ----------

198
simulators/gem5/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/config.ini Normal file
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@ -0,0 +1,198 @@
[root]
type=Root
children=system
full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
boot_osflags=a
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
readfile=
symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.cpu]
type=TimingSimpleCPU
children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
phase=0
profile=0
progress_interval=0
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=262144
subblock_size=0
system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
[system.cpu.dtb]
type=AlphaTLB
size=64
[system.cpu.icache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=131072
subblock_size=0
system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.interrupts]
type=AlphaInterrupts
[system.cpu.itb]
type=AlphaTLB
size=48
[system.cpu.l2cache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=false
latency=10000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=2097152
subblock_size=0
system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
[system.cpu.toL2Bus]
type=CoherentBus
block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=twolf smred
cwd=build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-timing
egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf
gid=100
input=cin
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=0
system=system
uid=100
[system.membus]
type=CoherentBus
block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
master=system.physmem.port[0]
slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=SimpleMemory
conf_table_reported=false
file=
in_addr_map=true
latency=30000
latency_var=0
null=false
range=0:134217727
zero=false
port=system.membus.master[0]

6
simulators/gem5/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/simerr Executable file
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warn: Sockets disabled, not accepting gdb connections
warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
hack: be nice to actually delete the event here

26
simulators/gem5/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/simout Executable file
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gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 4 2012 11:50:11
gem5 started Jun 4 2012 14:18:52
gem5 executing on zizzer
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-timing
Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-timing/smred.sav
Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-timing/smred.sv2
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
Standard Cell Placement and Global Routing Program
Authors: Carl Sechen, Bill Swartz
Yale University
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
61 62 63 64 65 66 67 68 69 70 71 72 73 74 75
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
122 123 124 Exiting @ tick 118740049000 because target called exit()

276
simulators/gem5/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/smred.out Normal file
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TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
Standard Cell Placement and Global Routing Program
Authors: Carl Sechen, Bill Swartz
Yale University
NOTE: Restart file .rs2 not used
TimberWolf will perform a global route step
rowSep: 1.000000
feedThruWidth: 4
******************
BLOCK DATA
block:1 desire:85
block:2 desire:85
Total Desired Length: 170
total cell length: 168
total block length: 168
block x-span:84 block y-span:78
implicit feed thru range: -84
Using default value of bin.penalty.control:1.000000
numBins automatically set to:5
binWidth = average_cell_width + 0 sigma= 17
average_cell_width is:16
standard deviation of cell length is:23.6305
TimberWolfSC starting from the beginning
THIS IS THE ROUTE COST OF THE ORIGINAL PLACEMENT: 645
The number of nets with 1 pin is 4
The number of nets with 2 pin is 9
The number of nets with 3 pin is 0
The number of nets with 4 pin is 2
The number of nets with 5 pin is 0
The number of nets with 6 pin is 0
The number of nets with 7 pin is 0
The number of nets with 8 pin is 0
The number of nets with 9 pin is 0
The number of nets with 10 pin or more is 0
New Cost Function: Initial Horizontal Cost:242
New Cost Function: FEEDS:0 MISSING_ROWS:-46
bdxlen:86 bdylen:78
l:0 t:78 r:86 b:0
THIS IS THE ROUTE COST OF THE CURRENT PLACEMENT: 645
THIS IS THE PENALTY OF THE CURRENT PLACEMENT: 44
The rand generator seed was at utemp() : 1
tempfile[0][0] = 0.982500 tempfile[0][1] = 90.000000
tempfile[1][0] = 0.915000 tempfile[1][1] = 20.000000
tempfile[2][0] = 0.700000 tempfile[2][1] = 10.000000
tempfile[3][0] = 0.100000 tempfile[3][1] = 0.000000
I T fds Wire Penalty P_lim Epct binC rowC acc s/p early FDs MRs
1 500 0 929 592 160 30.0 1.0 3.0 84.2 34.7 0.0 0 40
2 491 0 876 106 726 0.0 0.8 2.5 80.0 18.5 0.0 0 46
3 482 0 822 273 372 0.0 0.5 1.5 80.8 21.3 0.0 0 46
4 474 0 826 53 247 0.0 0.5 0.9 65.0 21.9 0.0 0 48
5 465 8 987 73 190 0.0 0.5 0.5 50.0 38.3 0.0 0 46
6 457 8 851 67 226 0.0 0.5 0.5 53.8 42.9 0.0 0 52
7 449 8 1067 108 190 0.0 0.5 0.5 46.2 53.8 0.0 0 50
8 441 8 918 106 171 0.0 0.5 0.5 47.1 40.4 0.0 0 48
9 434 8 812 101 197 0.0 0.5 0.5 53.6 21.0 0.0 0 48
10 426 8 1038 121 181 0.0 0.5 0.5 43.6 27.1 0.0 0 48
11 419 8 898 93 187 0.0 0.5 0.5 45.3 47.8 0.0 0 50
12 411 4 857 94 240 0.0 0.5 0.5 62.7 51.6 0.0 0 44
13 404 8 1043 88 185 0.0 0.5 0.5 54.0 52.8 0.0 0 50
14 397 8 767 94 154 0.0 0.5 0.5 33.8 35.0 0.0 0 50
15 390 8 862 89 183 0.0 0.5 0.5 55.6 29.0 0.0 0 46
16 383 4 798 79 173 0.0 0.5 0.5 57.5 35.3 0.0 0 52
17 376 8 827 100 152 0.0 0.5 0.5 35.3 81.8 0.0 0 50
18 370 8 878 101 208 0.0 0.5 0.5 44.7 46.2 0.0 0 48
19 363 4 921 67 167 0.0 0.5 0.5 57.1 34.7 0.0 0 48
20 357 8 933 93 154 0.0 0.5 0.5 46.5 43.6 0.0 0 52
21 351 8 930 89 147 0.0 0.5 0.5 39.4 36.5 0.0 0 52
22 345 8 951 79 142 0.0 0.5 0.5 32.8 51.3 0.0 0 50
23 339 8 1046 87 207 0.0 0.5 0.5 52.8 61.0 0.0 0 48
24 333 4 989 96 185 0.0 0.5 0.5 45.3 43.3 0.0 0 42
25 327 4 577 86 157 0.0 0.5 0.5 31.1 55.3 0.0 0 52
26 321 8 776 97 174 0.0 0.5 0.5 47.9 62.5 0.0 0 52
27 315 8 850 81 188 0.0 0.5 0.5 45.0 55.2 0.0 0 50
28 310 8 898 97 148 0.0 0.5 0.5 43.0 45.8 0.0 0 48
29 304 8 889 65 173 0.0 0.5 0.5 32.5 41.3 0.0 0 50
30 299 8 858 81 153 0.0 0.5 0.5 44.3 29.2 0.0 0 46
31 294 8 871 82 187 0.0 0.5 0.5 45.7 47.7 0.0 0 48
32 289 8 782 109 173 0.0 0.5 0.5 35.2 57.4 0.0 0 48
33 284 8 743 98 189 0.0 0.6 0.5 41.8 64.3 0.0 0 52
34 279 8 943 90 147 0.0 0.5 0.5 38.6 32.8 0.0 0 48
35 274 8 907 57 166 0.0 0.5 0.5 33.6 51.0 0.0 0 48
36 269 8 900 70 148 0.0 0.5 0.5 45.0 41.4 0.0 0 50
37 264 4 875 106 133 0.0 0.5 0.5 31.7 55.3 0.0 0 52
38 260 8 1023 145 149 0.0 0.6 0.5 28.7 65.0 0.0 0 52
39 255 8 801 151 173 0.0 0.9 0.5 41.7 41.2 0.0 0 48
40 251 8 741 104 159 0.0 0.8 0.5 36.3 47.5 0.0 0 48
41 246 8 828 108 149 0.0 0.5 0.5 34.6 50.9 0.0 0 50
42 242 8 947 128 132 0.0 0.7 0.5 34.2 39.0 0.0 0 50
43 238 8 917 101 142 0.0 0.8 0.5 34.4 50.9 0.0 0 48
44 234 8 761 86 129 0.0 0.5 0.5 42.0 36.4 0.0 0 52
45 229 8 979 106 137 0.0 0.5 0.5 29.2 55.3 0.0 0 50
46 225 8 806 74 130 0.0 0.7 0.5 33.1 65.4 0.0 0 52
47 221 8 971 125 114 0.0 0.5 0.5 31.9 45.6 0.0 0 52
48 218 8 869 125 104 0.0 0.9 0.5 30.0 56.0 0.0 0 48
49 214 8 999 153 140 0.0 0.8 0.5 30.4 46.4 0.0 0 52
50 210 8 798 192 139 0.0 1.0 0.5 28.9 50.0 0.0 0 52
51 206 8 860 125 157 0.0 1.2 0.5 31.5 26.9 0.0 0 52
52 203 8 893 186 127 5.9 0.9 0.5 26.4 42.3 0.0 0 46
53 199 8 863 126 141 0.0 1.2 0.5 32.5 44.4 0.0 0 44
54 196 8 788 97 133 0.0 0.9 0.5 37.5 40.0 0.0 0 50
55 192 8 926 119 116 0.0 0.6 0.5 26.1 55.3 0.0 0 52
56 189 8 789 162 107 0.0 0.8 0.5 25.2 40.4 0.0 0 48
57 186 8 878 107 128 0.0 1.1 0.5 23.1 34.0 0.0 0 52
58 182 8 775 105 122 0.0 0.8 0.5 25.5 57.4 0.0 0 50
59 179 8 747 94 129 0.0 0.7 0.5 34.3 37.3 0.0 0 50
60 176 8 845 96 138 0.0 0.6 0.5 28.3 41.7 0.0 0 52
61 173 8 961 121 110 0.0 0.6 0.5 29.0 52.6 0.0 0 48
62 170 4 911 110 109 0.0 0.9 0.5 33.5 33.3 0.0 0 48
63 167 8 656 109 109 0.0 0.8 0.5 21.9 44.7 0.0 0 52
64 164 8 934 117 105 0.0 0.8 0.5 15.5 50.0 0.0 0 52
65 161 8 972 125 95 0.0 0.8 0.5 24.4 50.0 0.0 0 50
66 158 8 894 125 101 0.0 0.9 0.5 27.2 35.9 0.0 0 52
67 155 8 798 146 129 0.0 1.0 0.5 22.8 58.7 0.0 0 52
68 153 8 901 183 92 0.0 1.1 0.5 23.6 34.5 0.0 0 52
69 150 8 977 197 103 0.0 1.4 0.5 23.6 36.8 0.0 0 52
70 147 8 905 262 93 0.0 1.5 0.5 20.3 63.4 0.0 0 52
71 145 8 995 148 122 0.0 1.9 0.5 20.9 35.3 0.0 0 52
72 142 8 934 230 99 0.0 1.6 0.5 20.0 65.9 0.0 0 52
73 140 8 862 173 100 0.0 1.8 0.5 26.8 46.8 0.0 0 52
74 137 8 924 139 90 0.0 1.7 0.5 16.8 42.5 0.0 0 52
75 135 8 888 168 113 0.0 1.6 0.5 22.9 40.4 0.0 0 52
76 133 8 712 212 84 0.0 1.6 0.5 13.4 46.9 0.0 0 52
77 130 8 868 210 91 0.0 1.7 0.5 17.7 51.2 0.0 0 52
78 128 8 952 307 92 0.0 1.9 0.5 19.7 44.9 0.0 0 50
79 126 8 801 157 107 0.0 2.2 0.5 15.8 39.0 0.0 0 52
80 123 8 849 147 93 0.0 2.1 0.5 15.6 51.4 0.0 0 52
81 121 8 799 154 86 0.0 1.9 0.5 12.2 50.0 0.0 0 52
82 119 8 941 213 82 0.0 1.8 0.5 19.5 41.2 0.0 0 50
83 117 8 751 268 94 0.0 2.0 0.5 20.8 42.6 0.0 0 50
84 115 8 828 198 102 0.0 2.2 0.5 15.5 59.5 0.0 0 52
85 113 8 898 266 123 0.0 2.2 0.5 13.2 85.2 0.0 0 52
86 111 8 943 190 93 0.0 2.4 0.5 19.5 45.1 0.0 0 52
87 109 8 864 183 65 0.0 2.4 0.5 14.9 31.8 0.0 0 52
88 107 8 793 203 93 0.0 2.4 0.5 11.8 35.3 0.0 0 52
89 105 8 752 162 74 1.2 2.4 0.5 13.1 21.4 0.0 0 52
90 103 8 801 149 77 0.0 2.3 0.5 9.7 58.3 0.0 0 52
91 102 8 901 230 99 0.0 2.2 0.5 16.0 25.5 0.0 0 52
92 100 8 826 201 87 0.0 2.4 0.5 12.8 45.7 0.0 0 52
93 98 8 810 196 83 0.0 2.5 0.5 14.0 24.4 0.0 0 52
94 96 8 857 209 68 1.0 2.5 0.5 11.5 27.0 5.1 0 52
95 95 8 771 174 91 0.0 2.6 0.5 10.5 26.5 0.0 0 52
96 93 8 955 210 59 0.0 2.6 0.5 10.0 36.7 0.7 0 52
97 91 8 833 206 53 0.0 2.7 0.5 10.2 19.4 1.4 0 52
98 90 8 888 229 86 0.0 2.8 0.5 8.1 36.0 0.0 0 52
99 88 8 794 186 91 1.0 2.9 0.5 8.3 25.0 0.5 0 52
100 81 8 756 170 72 1.0 2.9 0.5 6.0 23.8 7.0 0 52
101 74 8 791 176 67 0.0 2.9 0.5 4.4 58.3 4.0 0 52
102 67 8 813 213 43 0.0 3.0 0.5 7.0 150.0 4.2 0 52
103 62 8 779 245 39 0.0 3.1 0.5 3.2 16.7 13.0 0 52
104 56 8 767 303 63 0.0 3.2 0.5 4.1 20.0 0.7 0 52
105 52 8 757 270 57 0.0 3.5 0.5 6.4 3.7 0.5 0 52
106 47 8 763 283 41 0.0 3.7 0.5 4.5 0.0 0.0 0 52
107 43 8 768 283 36 0.0 3.7 0.5 2.9 18.2 3.6 0 52
108 39 8 804 283 25 0.0 3.7 0.5 3.1 0.0 6.2 0 52
109 36 8 781 283 24 0.0 3.7 0.5 3.6 6.7 6.7 0 52
110 33 8 738 298 42 0.0 3.7 0.5 3.3 15.4 3.5 0 52
111 30 8 761 298 36 0.0 3.7 0.5 2.2 0.0 4.3 0 52
112 27 8 769 298 37 0.0 3.7 0.5 0.9 0.0 2.2 0 52
113 25 8 745 298 31 0.0 3.7 0.5 1.5 0.0 6.6 0 52
114 23 8 753 298 16 0.0 3.7 0.5 1.3 0.0 2.8 0 52
115 21 8 745 298 11 0.0 3.7 0.5 1.5 0.0 14.0 0 52
116 19 8 747 298 21 0.0 3.7 0.5 2.1 0.0 5.8 0 52
117 13 8 737 298 12 0.0 3.7 0.5 1.0 0.0 10.0 0 52
118 9 8 736 298 4 0.0 3.7 0.5 1.5 0.0 18.5 0 52
119 0 8 739 298 0 0.0 3.7 0.5 1.8 0.0 18.0 0 52
120 0 8 732 298 0 0.0 3.7 0.5 1.2 0.0 21.8 0 52
121 0 8 732 19 -1 0.0 0.0 0.5 0.0 100.0 54.8
Initial Wiring Cost: 645 Final Wiring Cost: 732
############## Percent Wire Cost Reduction: -13
Initial Wire Length: 645 Final Wire Length: 732
************** Percent Wire Length Reduction: -13
Initial Horiz. Wire: 216 Final Horiz. Wire: 147
$$$$$$$$$$$ Percent H-Wire Length Reduction: 32
Initial Vert. Wire: 429 Final Vert. Wire: 585
@@@@@@@@@@@ Percent V-Wire Length Reduction: -36
Before Feeds are Added:
BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET
1 82 -20
2 86 -16
LONGEST Block is:2 Its length is:86
BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET
1 86 -16
2 86 -16
LONGEST Block is:1 Its length is:86
Added: 1 feed-through cells
Removed the cell overlaps --- Will do neighbor interchanges only now
TOTAL INTERCONNECT LENGTH: 994
OVERLAP PENALTY: 0
initialRowControl: 1.650
finalRowControl: 0.300
iter T Wire accept
122 0.001 976 16%
123 0.001 971 0%
124 0.001 971 0%
Total Feed-Alignment Movement (Pass 1): 0
Total Feed-Alignment Movement (Pass 2): 0
Total Feed-Alignment Movement (Pass 3): 0
Total Feed-Alignment Movement (Pass 4): 0
Total Feed-Alignment Movement (Pass 5): 0
Total Feed-Alignment Movement (Pass 6): 0
Total Feed-Alignment Movement (Pass 7): 0
Total Feed-Alignment Movement (Pass 8): 0
The rand generator seed was at globroute() : 987654321
Total Number of Net Segments: 9
Number of Switchable Net Segments: 0
Number of channels: 3
THIS IS THE ORIGINAL NUMBER OF TRACKS: 5
no. of accepted flips: 0
no. of attempted flips: 0
THIS IS THE NUMBER OF TRACKS: 5
FINAL NUMBER OF ROUTING TRACKS: 5
MAX OF CHANNEL: 1 is: 0
MAX OF CHANNEL: 2 is: 4
MAX OF CHANNEL: 3 is: 1
FINAL TOTAL INTERCONNECT LENGTH: 978
FINAL OVERLAP PENALTY: 0 FINAL VALUE OF TOTAL COST IS: 978
MAX NUMBER OF ATTEMPTED FLIPS PER T: 55
cost_scale_factor:3.90616
Number of Feed Thrus: 0
Number of Implicit Feed Thrus: 0
Statistics:
Number of Standard Cells: 10
Number of Pads: 0
Number of Nets: 15
Number of Pins: 46
Usage statistics not available

17
simulators/gem5/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/smred.pin Normal file
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$COUNT_1/$AND2_1/$ND2_1$Z 1 $COUNT_1/$AND2_1/$ND2_1 00#Z 17 52 2 1 0
$COUNT_1/$AND2_1/$ND2_1$Z 1 ACOUNT_1 00#A 15 26 2 -1 0
B7 2 $COUNT_1/$FJK3_2 00#K 25 78 3 -1 0
B7 2 $COUNT_1/$FJK3_2 00#J 23 78 3 -1 0
B7 3 $COUNT_1/$AND2_2/$ND2_1 00#A 9 26 2 -1 0
B7 3 ACOUNT_1 01#Z 17 26 2 -1 0
B6 5 $COUNT_1/$FJK3_1 00#K 25 26 2 -1 0
B6 5 $COUNT_1/$FJK3_1 00#J 23 26 2 -1 0
B6 5 $COUNT_1/$AND2_3/$IV_1 01#Z 7 26 2 -1 0
$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$FJK3_1 01#Q 81 26 2 -1 0
$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$AND2_1/$ND2_1 00#B 19 52 2 1 0
$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$FJK3_2 00#Q 81 52 2 1 0
$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$AND2_2/$ND2_1 01#B 11 26 2 -1 0
$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$ND2_1 00#Z 5 52 2 1 0
$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$IV_1 00#A 5 26 2 -1 0
$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$ND2_1 00#Z 7 52 2 1 0
$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$IV_1 00#A 3 26 2 -1 0

11
simulators/gem5/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/smred.pl1 Normal file
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$COUNT_1/$AND2_4/$IV_1 0 0 4 26 0 1
$COUNT_1/$AND2_3/$IV_1 4 0 8 26 2 1
$COUNT_1/$AND2_2/$ND2_1 8 0 14 26 0 1
ACOUNT_1 14 0 18 26 2 1
twfeed1 18 0 22 26 0 1
$COUNT_1/$FJK3_1 22 0 86 26 0 1
$COUNT_1/$AND2_3/$ND2_1 0 52 6 78 0 2
$COUNT_1/$AND2_4/$ND2_1 6 52 12 78 2 2
$COUNT_1/$AND2_2/$IV_1 12 52 16 78 2 2
$COUNT_1/$AND2_1/$ND2_1 16 52 22 78 2 2
$COUNT_1/$FJK3_2 22 52 86 78 0 2

2
simulators/gem5/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/smred.pl2 Normal file
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@ -0,0 +1,2 @@
1 0 0 86 26 0 0
2 0 52 86 78 0 0

18
simulators/gem5/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/smred.sav Normal file
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@ -0,0 +1,18 @@
0.009592
121
0
1
0.000000
0.500000
3.906156
1
1 1 2 37 13
2 2 0 34 65
3 2 2 63 65
4 1 0 59 13
5 1 2 32 13
6 2 0 23 65
7 1 2 12 13
8 2 0 6 65
9 1 0 70 13
10 2 0 70 65

19
simulators/gem5/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/smred.sv2 Normal file
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@ -0,0 +1,19 @@
0.001000
123
0
2
0.000000
0.500000
3.906156
1
1 1 2 16 13
2 2 2 19 65
3 2 2 14 65
4 1 0 11 13
5 1 2 6 13
6 2 0 3 65
7 1 0 2 13
8 2 2 9 65
9 1 0 50 13
10 2 0 54 65
11 1 0 84 13

29
simulators/gem5/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/smred.twf Normal file
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@ -0,0 +1,29 @@
net 1
segment channel 2
pin1 1 pin2 7 0 0
net 2
segment channel 3
pin1 41 pin2 42 0 0
segment channel 2
pin1 12 pin2 3 0 0
net 3
segment channel 2
pin1 35 pin2 36 0 0
segment channel 2
pin1 19 pin2 35 0 0
net 4
segment channel 2
pin1 5 pin2 38 0 0
net 5
net 7
segment channel 2
pin1 14 pin2 43 0 0
net 8
segment channel 2
pin1 23 pin2 17 0 0
net 9
net 11
segment channel 2
pin1 25 pin2 31 0 0
net 14
net 15

400
simulators/gem5/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt Normal file
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@ -0,0 +1,400 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.118740 # Number of seconds simulated
sim_ticks 118740049000 # Number of ticks simulated
final_tick 118740049000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1590844 # Simulator instruction rate (inst/s)
host_op_rate 1590843 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 2055391195 # Simulator tick rate (ticks/s)
host_mem_usage 218628 # Number of bytes of host memory used
host_seconds 57.77 # Real time elapsed on the host
sim_insts 91903056 # Number of instructions simulated
sim_ops 91903056 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 167744 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 137216 # Number of bytes read from this memory
system.physmem.bytes_read::total 304960 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 167744 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 167744 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 2621 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 2144 # Number of read requests responded to by this memory
system.physmem.num_reads::total 4765 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 1412699 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 1155600 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 2568299 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 1412699 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 1412699 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 1412699 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 1155600 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 2568299 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 19996198 # DTB read hits
system.cpu.dtb.read_misses 10 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 19996208 # DTB read accesses
system.cpu.dtb.write_hits 6501103 # DTB write hits
system.cpu.dtb.write_misses 23 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 6501126 # DTB write accesses
system.cpu.dtb.data_hits 26497301 # DTB hits
system.cpu.dtb.data_misses 33 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 26497334 # DTB accesses
system.cpu.itb.fetch_hits 91903090 # ITB hits
system.cpu.itb.fetch_misses 47 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 91903137 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 389 # Number of system calls
system.cpu.numCycles 237480098 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 91903056 # Number of instructions committed
system.cpu.committedOps 91903056 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 79581109 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 6862064 # Number of float alu accesses
system.cpu.num_func_calls 2059216 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 7465012 # number of instructions that are conditional controls
system.cpu.num_int_insts 79581109 # number of integer instructions
system.cpu.num_fp_insts 6862064 # number of float instructions
system.cpu.num_int_register_reads 115028592 # number of times the integer registers were read
system.cpu.num_int_register_writes 62575473 # number of times the integer registers were written
system.cpu.num_fp_register_reads 6071661 # number of times the floating registers were read
system.cpu.num_fp_register_writes 5851888 # number of times the floating registers were written
system.cpu.num_mem_refs 26497334 # number of memory refs
system.cpu.num_load_insts 19996208 # Number of load instructions
system.cpu.num_store_insts 6501126 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 237480098 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.icache.replacements 6681 # number of replacements
system.cpu.icache.tagsinuse 1418.037996 # Cycle average of tags in use
system.cpu.icache.total_refs 91894580 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 8510 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 10798.423032 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 1418.037996 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.692401 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.692401 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 91894580 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 91894580 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 91894580 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 91894580 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 91894580 # number of overall hits
system.cpu.icache.overall_hits::total 91894580 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 8510 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 8510 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 8510 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 8510 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 8510 # number of overall misses
system.cpu.icache.overall_misses::total 8510 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 229222000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 229222000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 229222000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 229222000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 229222000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 229222000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 91903090 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 91903090 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 91903090 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 91903090 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 91903090 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 91903090 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000093 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000093 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000093 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000093 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000093 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000093 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 26935.605170 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 26935.605170 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 26935.605170 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 26935.605170 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 26935.605170 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 26935.605170 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 8510 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 8510 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 8510 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 8510 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 8510 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 8510 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 203692000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 203692000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 203692000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 203692000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 203692000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 203692000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000093 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000093 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000093 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000093 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000093 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000093 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 23935.605170 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 23935.605170 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 23935.605170 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 23935.605170 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23935.605170 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 23935.605170 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 157 # number of replacements
system.cpu.dcache.tagsinuse 1442.028823 # Cycle average of tags in use
system.cpu.dcache.total_refs 26495078 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 2223 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 11918.613585 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 1442.028823 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.352058 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.352058 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 19995723 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 19995723 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 6499355 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 6499355 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 26495078 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 26495078 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 26495078 # number of overall hits
system.cpu.dcache.overall_hits::total 26495078 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 475 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 475 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 1748 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 1748 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 2223 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 2223 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 2223 # number of overall misses
system.cpu.dcache.overall_misses::total 2223 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 24374000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 24374000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 96796000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 96796000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 121170000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 121170000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 121170000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 121170000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 19996198 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 19996198 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 26497301 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 26497301 # number of demand (read+write) accesses
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system.cpu.dcache.overall_accesses::total 26497301 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000024 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.000024 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000269 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.000269 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.000084 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.000084 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.000084 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.000084 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51313.684211 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 51313.684211 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55375.286041 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 55375.286041 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 54507.422402 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 54507.422402 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 54507.422402 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 54507.422402 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 107 # number of writebacks
system.cpu.dcache.writebacks::total 107 # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 475 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 475 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1748 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 1748 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 2223 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 2223 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 2223 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 2223 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 22949000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 22949000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 91552000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 91552000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 114501000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 114501000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 114501000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 114501000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000269 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000269 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 48313.684211 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 48313.684211 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52375.286041 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52375.286041 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51507.422402 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 51507.422402 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51507.422402 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 51507.422402 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 2074.048594 # Cycle average of tags in use
system.cpu.l2cache.total_refs 5951 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 3109 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 1.914120 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 17.795183 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 1704.999565 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 351.253845 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.000543 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.052032 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.010719 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.063295 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 5889 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 53 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 5942 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 107 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 107 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 26 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 26 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst 5889 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 79 # number of demand (read+write) hits
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system.cpu.l2cache.overall_hits::cpu.inst 5889 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 79 # number of overall hits
system.cpu.l2cache.overall_hits::total 5968 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 2621 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 422 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 3043 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 1722 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 1722 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 2621 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 2144 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 4765 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 2621 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 2144 # number of overall misses
system.cpu.l2cache.overall_misses::total 4765 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 136292000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 21944000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 158236000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 89544000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 89544000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 136292000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 111488000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 247780000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 136292000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 111488000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 247780000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 8510 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 475 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 8985 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 107 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 107 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1748 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 1748 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 8510 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 2223 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 10733 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 8510 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 2223 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 10733 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.307991 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.888421 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.338676 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.985126 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.985126 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.307991 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.964462 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.443958 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.307991 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.964462 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.443958 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2621 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 422 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 3043 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1722 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 1722 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 2621 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 2144 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 4765 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2621 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 2144 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 4765 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 104840000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 16880000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 121720000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 68880000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 68880000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 104840000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 85760000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 190600000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 104840000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 85760000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 190600000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.307991 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.888421 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.338676 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.985126 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.985126 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.307991 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.443958 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.307991 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.443958 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

547
simulators/gem5/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini Normal file
View File

@ -0,0 +1,547 @@
[root]
type=Root
children=system
full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
boot_osflags=a
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
readfile=
symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.cpu]
type=DerivO3CPU
children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
LSQDepCheckShift=4
RASSize=16
SQEntries=32
SSITSize=1024
activity=0
backComSize=5
cachePorts=200
checker=Null
choiceCtrBits=2
choicePredictorSize=8192
clock=500
commitToDecodeDelay=1
commitToFetchDelay=1
commitToIEWDelay=1
commitToRenameDelay=1
commitWidth=8
cpu_id=0
decodeToFetchDelay=1
decodeToRenameDelay=1
decodeWidth=8
defer_registration=false
dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
fetchToDecodeDelay=1
fetchTrapLatency=1
fetchWidth=8
forwardComSize=5
fuPool=system.cpu.fuPool
function_trace=false
function_trace_start=0
globalCtrBits=2
globalHistoryBits=13
globalPredictorSize=8192
iewToCommitDelay=1
iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
instShiftAmt=2
interrupts=system.cpu.interrupts
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
localCtrBits=2
localHistoryBits=11
localHistoryTableSize=2048
localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
needsTSO=false
numIQEntries=64
numPhysFloatRegs=256
numPhysIntRegs=256
numROBEntries=192
numRobs=1
numThreads=1
phase=0
predType=tournament
profile=0
progress_interval=0
renameToDecodeDelay=1
renameToFetchDelay=1
renameToIEWDelay=2
renameToROBDelay=1
renameWidth=8
smtCommitPolicy=RoundRobin
smtFetchPolicy=SingleThread
smtIQPolicy=Partitioned
smtIQThreshold=100
smtLSQPolicy=Partitioned
smtLSQThreshold=100
smtNumFetchingThreads=1
smtROBPolicy=Partitioned
smtROBThreshold=100
squashWidth=8
store_set_clear_period=250000
system=system
tracer=system.cpu.tracer
trapLatency=13
wbDepth=1
wbWidth=8
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=262144
subblock_size=0
system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
[system.cpu.dtb]
type=ArmTLB
children=walker
size=64
walker=system.cpu.dtb.walker
[system.cpu.dtb.walker]
type=ArmTableWalker
max_backoff=100000
min_backoff=0
sys=system
port=system.cpu.toL2Bus.slave[3]
[system.cpu.fuPool]
type=FUPool
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
[system.cpu.fuPool.FUList0]
type=FUDesc
children=opList
count=6
opList=system.cpu.fuPool.FUList0.opList
[system.cpu.fuPool.FUList0.opList]
type=OpDesc
issueLat=1
opClass=IntAlu
opLat=1
[system.cpu.fuPool.FUList1]
type=FUDesc
children=opList0 opList1
count=2
opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
[system.cpu.fuPool.FUList1.opList0]
type=OpDesc
issueLat=1
opClass=IntMult
opLat=3
[system.cpu.fuPool.FUList1.opList1]
type=OpDesc
issueLat=19
opClass=IntDiv
opLat=20
[system.cpu.fuPool.FUList2]
type=FUDesc
children=opList0 opList1 opList2
count=4
opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
[system.cpu.fuPool.FUList2.opList0]
type=OpDesc
issueLat=1
opClass=FloatAdd
opLat=2
[system.cpu.fuPool.FUList2.opList1]
type=OpDesc
issueLat=1
opClass=FloatCmp
opLat=2
[system.cpu.fuPool.FUList2.opList2]
type=OpDesc
issueLat=1
opClass=FloatCvt
opLat=2
[system.cpu.fuPool.FUList3]
type=FUDesc
children=opList0 opList1 opList2
count=2
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
[system.cpu.fuPool.FUList3.opList0]
type=OpDesc
issueLat=1
opClass=FloatMult
opLat=4
[system.cpu.fuPool.FUList3.opList1]
type=OpDesc
issueLat=12
opClass=FloatDiv
opLat=12
[system.cpu.fuPool.FUList3.opList2]
type=OpDesc
issueLat=24
opClass=FloatSqrt
opLat=24
[system.cpu.fuPool.FUList4]
type=FUDesc
children=opList
count=0
opList=system.cpu.fuPool.FUList4.opList
[system.cpu.fuPool.FUList4.opList]
type=OpDesc
issueLat=1
opClass=MemRead
opLat=1
[system.cpu.fuPool.FUList5]
type=FUDesc
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
count=4
opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
[system.cpu.fuPool.FUList5.opList00]
type=OpDesc
issueLat=1
opClass=SimdAdd
opLat=1
[system.cpu.fuPool.FUList5.opList01]
type=OpDesc
issueLat=1
opClass=SimdAddAcc
opLat=1
[system.cpu.fuPool.FUList5.opList02]
type=OpDesc
issueLat=1
opClass=SimdAlu
opLat=1
[system.cpu.fuPool.FUList5.opList03]
type=OpDesc
issueLat=1
opClass=SimdCmp
opLat=1
[system.cpu.fuPool.FUList5.opList04]
type=OpDesc
issueLat=1
opClass=SimdCvt
opLat=1
[system.cpu.fuPool.FUList5.opList05]
type=OpDesc
issueLat=1
opClass=SimdMisc
opLat=1
[system.cpu.fuPool.FUList5.opList06]
type=OpDesc
issueLat=1
opClass=SimdMult
opLat=1
[system.cpu.fuPool.FUList5.opList07]
type=OpDesc
issueLat=1
opClass=SimdMultAcc
opLat=1
[system.cpu.fuPool.FUList5.opList08]
type=OpDesc
issueLat=1
opClass=SimdShift
opLat=1
[system.cpu.fuPool.FUList5.opList09]
type=OpDesc
issueLat=1
opClass=SimdShiftAcc
opLat=1
[system.cpu.fuPool.FUList5.opList10]
type=OpDesc
issueLat=1
opClass=SimdSqrt
opLat=1
[system.cpu.fuPool.FUList5.opList11]
type=OpDesc
issueLat=1
opClass=SimdFloatAdd
opLat=1
[system.cpu.fuPool.FUList5.opList12]
type=OpDesc
issueLat=1
opClass=SimdFloatAlu
opLat=1
[system.cpu.fuPool.FUList5.opList13]
type=OpDesc
issueLat=1
opClass=SimdFloatCmp
opLat=1
[system.cpu.fuPool.FUList5.opList14]
type=OpDesc
issueLat=1
opClass=SimdFloatCvt
opLat=1
[system.cpu.fuPool.FUList5.opList15]
type=OpDesc
issueLat=1
opClass=SimdFloatDiv
opLat=1
[system.cpu.fuPool.FUList5.opList16]
type=OpDesc
issueLat=1
opClass=SimdFloatMisc
opLat=1
[system.cpu.fuPool.FUList5.opList17]
type=OpDesc
issueLat=1
opClass=SimdFloatMult
opLat=1
[system.cpu.fuPool.FUList5.opList18]
type=OpDesc
issueLat=1
opClass=SimdFloatMultAcc
opLat=1
[system.cpu.fuPool.FUList5.opList19]
type=OpDesc
issueLat=1
opClass=SimdFloatSqrt
opLat=1
[system.cpu.fuPool.FUList6]
type=FUDesc
children=opList
count=0
opList=system.cpu.fuPool.FUList6.opList
[system.cpu.fuPool.FUList6.opList]
type=OpDesc
issueLat=1
opClass=MemWrite
opLat=1
[system.cpu.fuPool.FUList7]
type=FUDesc
children=opList0 opList1
count=4
opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
[system.cpu.fuPool.FUList7.opList0]
type=OpDesc
issueLat=1
opClass=MemRead
opLat=1
[system.cpu.fuPool.FUList7.opList1]
type=OpDesc
issueLat=1
opClass=MemWrite
opLat=1
[system.cpu.fuPool.FUList8]
type=FUDesc
children=opList
count=1
opList=system.cpu.fuPool.FUList8.opList
[system.cpu.fuPool.FUList8.opList]
type=OpDesc
issueLat=3
opClass=IprAccess
opLat=3
[system.cpu.icache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=131072
subblock_size=0
system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.interrupts]
type=ArmInterrupts
[system.cpu.itb]
type=ArmTLB
children=walker
size=64
walker=system.cpu.itb.walker
[system.cpu.itb.walker]
type=ArmTableWalker
max_backoff=100000
min_backoff=0
sys=system
port=system.cpu.toL2Bus.slave[2]
[system.cpu.l2cache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=false
latency=1000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=2097152
subblock_size=0
system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
[system.cpu.toL2Bus]
type=CoherentBus
block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=twolf smred
cwd=build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing
egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/cpu2000/binaries/arm/linux/twolf
gid=100
input=cin
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=0
system=system
uid=100
[system.membus]
type=CoherentBus
block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
master=system.physmem.port[0]
slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=SimpleMemory
conf_table_reported=false
file=
in_addr_map=true
latency=30000
latency_var=0
null=false
range=0:134217727
zero=false
port=system.membus.master[0]

2
simulators/gem5/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simerr Executable file
View File

@ -0,0 +1,2 @@
warn: Sockets disabled, not accepting gdb connections
hack: be nice to actually delete the event here

26
simulators/gem5/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout Executable file
View File

@ -0,0 +1,26 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 4 2012 12:14:06
gem5 started Jun 4 2012 18:52:11
gem5 executing on zizzer
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing
Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing/smred.sav
Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing/smred.sv2
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
Standard Cell Placement and Global Routing Program
Authors: Carl Sechen, Bill Swartz
Yale University
info: Increasing stack size by one page.
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76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
122 123 124 Exiting @ tick 76322764500 because target called exit()

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TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
Standard Cell Placement and Global Routing Program
Authors: Carl Sechen, Bill Swartz
Yale University
NOTE: Restart file .rs2 not used
TimberWolf will perform a global route step
rowSep: 1.000000
feedThruWidth: 4
******************
BLOCK DATA
block:1 desire:85
block:2 desire:85
Total Desired Length: 170
total cell length: 168
total block length: 168
block x-span:84 block y-span:78
implicit feed thru range: -84
Using default value of bin.penalty.control:1.000000
numBins automatically set to:5
binWidth = average_cell_width + 0 sigma= 17
average_cell_width is:16
standard deviation of cell length is:23.6305
TimberWolfSC starting from the beginning
THIS IS THE ROUTE COST OF THE ORIGINAL PLACEMENT: 645
The number of nets with 1 pin is 4
The number of nets with 2 pin is 9
The number of nets with 3 pin is 0
The number of nets with 4 pin is 2
The number of nets with 5 pin is 0
The number of nets with 6 pin is 0
The number of nets with 7 pin is 0
The number of nets with 8 pin is 0
The number of nets with 9 pin is 0
The number of nets with 10 pin or more is 0
New Cost Function: Initial Horizontal Cost:242
New Cost Function: FEEDS:0 MISSING_ROWS:-46
bdxlen:86 bdylen:78
l:0 t:78 r:86 b:0
THIS IS THE ROUTE COST OF THE CURRENT PLACEMENT: 645
THIS IS THE PENALTY OF THE CURRENT PLACEMENT: 44
The rand generator seed was at utemp() : 1
tempfile[0][0] = 0.982500 tempfile[0][1] = 90.000000
tempfile[1][0] = 0.915000 tempfile[1][1] = 20.000000
tempfile[2][0] = 0.700000 tempfile[2][1] = 10.000000
tempfile[3][0] = 0.100000 tempfile[3][1] = 0.000000
I T fds Wire Penalty P_lim Epct binC rowC acc s/p early FDs MRs
1 500 0 929 592 160 30.0 1.0 3.0 84.2 34.7 0.0 0 40
2 491 0 876 106 726 0.0 0.8 2.5 80.0 18.5 0.0 0 46
3 482 0 822 273 372 0.0 0.5 1.5 80.8 21.2 0.0 0 46
4 474 0 826 53 247 0.0 0.5 0.9 65.0 21.9 0.0 0 48
5 465 8 987 73 190 0.0 0.5 0.5 50.0 38.3 0.0 0 46
6 457 8 851 67 226 0.0 0.5 0.5 53.8 42.9 0.0 0 52
7 449 8 1067 108 190 0.0 0.5 0.5 46.2 53.8 0.0 0 50
8 441 8 918 106 171 0.0 0.5 0.5 47.1 40.4 0.0 0 48
9 434 8 812 101 197 0.0 0.5 0.5 53.6 21.0 0.0 0 48
10 426 8 1038 121 181 0.0 0.5 0.5 43.6 27.1 0.0 0 48
11 419 8 898 93 187 0.0 0.5 0.5 45.3 47.8 0.0 0 50
12 411 4 857 94 240 0.0 0.5 0.5 62.7 51.6 0.0 0 44
13 404 8 1043 88 185 0.0 0.5 0.5 54.0 52.8 0.0 0 50
14 397 8 767 94 154 0.0 0.5 0.5 33.8 35.0 0.0 0 50
15 390 8 862 89 183 0.0 0.5 0.5 55.6 29.0 0.0 0 46
16 383 4 798 79 173 0.0 0.5 0.5 57.5 35.3 0.0 0 52
17 376 8 827 100 152 0.0 0.5 0.5 35.3 81.8 0.0 0 50
18 370 8 878 101 208 0.0 0.5 0.5 44.7 46.2 0.0 0 48
19 363 4 921 67 167 0.0 0.5 0.5 57.1 34.7 0.0 0 48
20 357 8 933 93 154 0.0 0.5 0.5 46.5 43.6 0.0 0 52
21 351 8 930 89 147 0.0 0.5 0.5 39.4 36.5 0.0 0 52
22 345 8 951 79 142 0.0 0.5 0.5 32.8 51.3 0.0 0 50
23 339 8 1046 87 207 0.0 0.5 0.5 52.8 61.0 0.0 0 48
24 333 4 989 96 185 0.0 0.5 0.5 45.3 43.3 0.0 0 42
25 327 4 577 86 157 0.0 0.5 0.5 31.1 55.3 0.0 0 52
26 321 8 776 97 174 0.0 0.5 0.5 47.9 62.5 0.0 0 52
27 315 8 850 81 188 0.0 0.5 0.5 45.0 55.2 0.0 0 50
28 310 8 898 97 148 0.0 0.5 0.5 43.0 45.8 0.0 0 48
29 304 8 889 65 173 0.0 0.5 0.5 32.5 41.3 0.0 0 50
30 299 8 858 81 153 0.0 0.5 0.5 44.3 29.2 0.0 0 46
31 294 8 871 82 187 0.0 0.5 0.5 45.7 47.7 0.0 0 48
32 289 8 782 109 173 0.0 0.5 0.5 35.2 57.4 0.0 0 48
33 284 8 743 98 189 0.0 0.6 0.5 41.8 64.3 0.0 0 52
34 279 8 943 90 147 0.0 0.5 0.5 38.6 32.8 0.0 0 48
35 274 8 907 57 166 0.0 0.5 0.5 33.6 51.0 0.0 0 48
36 269 8 900 70 148 0.0 0.5 0.5 45.0 41.4 0.0 0 50
37 264 4 875 106 133 0.0 0.5 0.5 31.7 55.3 0.0 0 52
38 260 8 1023 145 149 0.0 0.6 0.5 28.7 65.0 0.0 0 52
39 255 8 801 151 173 0.0 0.9 0.5 41.7 41.2 0.0 0 48
40 251 8 741 104 159 0.0 0.8 0.5 36.2 47.5 0.0 0 48
41 246 8 828 108 149 0.0 0.5 0.5 34.6 50.9 0.0 0 50
42 242 8 947 128 132 0.0 0.7 0.5 34.2 39.0 0.0 0 50
43 238 8 917 101 142 0.0 0.8 0.5 34.4 50.9 0.0 0 48
44 234 8 761 86 129 0.0 0.5 0.5 42.0 36.4 0.0 0 52
45 229 8 979 106 137 0.0 0.5 0.5 29.2 55.3 0.0 0 50
46 225 8 806 74 130 0.0 0.7 0.5 33.1 65.4 0.0 0 52
47 221 8 971 125 114 0.0 0.5 0.5 31.9 45.6 0.0 0 52
48 218 8 869 125 104 0.0 0.9 0.5 30.0 56.0 0.0 0 48
49 214 8 999 153 140 0.0 0.8 0.5 30.4 46.4 0.0 0 52
50 210 8 798 192 139 0.0 1.0 0.5 28.9 50.0 0.0 0 52
51 206 8 860 125 157 0.0 1.2 0.5 31.5 26.9 0.0 0 52
52 203 8 893 186 127 5.9 0.9 0.5 26.4 42.3 0.0 0 46
53 199 8 863 126 141 0.0 1.2 0.5 32.5 44.4 0.0 0 44
54 196 8 788 97 133 0.0 0.9 0.5 37.5 40.0 0.0 0 50
55 192 8 926 119 116 0.0 0.6 0.5 26.1 55.3 0.0 0 52
56 189 8 789 162 107 0.0 0.8 0.5 25.2 40.4 0.0 0 48
57 186 8 878 107 128 0.0 1.1 0.5 23.1 34.0 0.0 0 52
58 182 8 775 105 122 0.0 0.8 0.5 25.5 57.4 0.0 0 50
59 179 8 747 94 129 0.0 0.7 0.5 34.3 37.3 0.0 0 50
60 176 8 845 96 138 0.0 0.6 0.5 28.3 41.7 0.0 0 52
61 173 8 961 121 110 0.0 0.6 0.5 29.0 52.6 0.0 0 48
62 170 4 911 110 109 0.0 0.9 0.5 33.5 33.3 0.0 0 48
63 167 8 656 109 109 0.0 0.8 0.5 21.9 44.7 0.0 0 52
64 164 8 934 117 105 0.0 0.8 0.5 15.5 50.0 0.0 0 52
65 161 8 972 125 95 0.0 0.8 0.5 24.4 50.0 0.0 0 50
66 158 8 894 125 101 0.0 0.9 0.5 27.2 35.9 0.0 0 52
67 155 8 798 146 129 0.0 1.0 0.5 22.8 58.7 0.0 0 52
68 153 8 901 183 92 0.0 1.1 0.5 23.6 34.5 0.0 0 52
69 150 8 977 197 103 0.0 1.4 0.5 23.6 36.8 0.0 0 52
70 147 8 905 262 93 0.0 1.5 0.5 20.3 63.4 0.0 0 52
71 145 8 995 148 122 0.0 1.9 0.5 20.9 35.3 0.0 0 52
72 142 8 934 230 99 0.0 1.6 0.5 20.0 65.9 0.0 0 52
73 140 8 862 173 100 0.0 1.8 0.5 26.8 46.8 0.0 0 52
74 137 8 924 139 90 0.0 1.7 0.5 16.8 42.5 0.0 0 52
75 135 8 888 168 113 0.0 1.6 0.5 22.9 40.4 0.0 0 52
76 133 8 712 212 84 0.0 1.6 0.5 13.4 46.9 0.0 0 52
77 130 8 868 210 91 0.0 1.7 0.5 17.7 51.2 0.0 0 52
78 128 8 952 307 92 0.0 1.9 0.5 19.7 44.9 0.0 0 50
79 126 8 801 157 107 0.0 2.2 0.5 15.8 39.0 0.0 0 52
80 123 8 849 147 93 0.0 2.1 0.5 15.6 51.4 0.0 0 52
81 121 8 799 154 86 0.0 1.9 0.5 12.2 50.0 0.0 0 52
82 119 8 941 213 82 0.0 1.8 0.5 19.5 41.2 0.0 0 50
83 117 8 751 268 94 0.0 2.0 0.5 20.8 42.6 0.0 0 50
84 115 8 828 198 102 0.0 2.2 0.5 15.5 59.5 0.0 0 52
85 113 8 898 266 123 0.0 2.2 0.5 13.2 85.2 0.0 0 52
86 111 8 943 190 93 0.0 2.4 0.5 19.5 45.1 0.0 0 52
87 109 8 864 183 65 0.0 2.4 0.5 14.9 31.8 0.0 0 52
88 107 8 793 203 93 0.0 2.4 0.5 11.8 35.3 0.0 0 52
89 105 8 752 162 74 1.2 2.4 0.5 13.1 21.4 0.0 0 52
90 103 8 801 149 77 0.0 2.3 0.5 9.7 58.3 0.0 0 52
91 102 8 901 230 99 0.0 2.2 0.5 16.0 25.5 0.0 0 52
92 100 8 826 201 87 0.0 2.4 0.5 12.8 45.7 0.0 0 52
93 98 8 810 196 83 0.0 2.5 0.5 14.0 24.4 0.0 0 52
94 96 8 857 209 68 1.0 2.5 0.5 11.5 27.0 5.1 0 52
95 95 8 771 174 91 0.0 2.6 0.5 10.5 26.5 0.0 0 52
96 93 8 955 210 59 0.0 2.6 0.5 10.0 36.7 0.7 0 52
97 91 8 833 206 53 0.0 2.7 0.5 10.2 19.4 1.4 0 52
98 90 8 888 229 86 0.0 2.8 0.5 8.1 36.0 0.0 0 52
99 88 8 794 186 91 1.0 2.9 0.5 8.3 25.0 0.5 0 52
100 81 8 756 170 72 1.0 2.9 0.5 6.0 23.8 7.0 0 52
101 74 8 791 176 67 0.0 2.9 0.5 4.4 58.3 4.0 0 52
102 67 8 813 213 43 0.0 3.0 0.5 7.0 150.0 4.2 0 52
103 62 8 779 245 39 0.0 3.1 0.5 3.2 16.7 13.0 0 52
104 56 8 767 303 63 0.0 3.2 0.5 4.1 20.0 0.7 0 52
105 52 8 757 270 57 0.0 3.5 0.5 6.4 3.7 0.5 0 52
106 47 8 763 283 41 0.0 3.7 0.5 4.5 0.0 0.0 0 52
107 43 8 768 283 36 0.0 3.7 0.5 2.9 18.2 3.6 0 52
108 39 8 804 283 25 0.0 3.7 0.5 3.1 0.0 6.2 0 52
109 36 8 781 283 24 0.0 3.7 0.5 3.6 6.7 6.7 0 52
110 33 8 738 298 42 0.0 3.7 0.5 3.3 15.4 3.5 0 52
111 30 8 761 298 36 0.0 3.7 0.5 2.2 0.0 4.3 0 52
112 27 8 769 298 37 0.0 3.7 0.5 0.9 0.0 2.2 0 52
113 25 8 745 298 31 0.0 3.7 0.5 1.5 0.0 6.6 0 52
114 23 8 753 298 16 0.0 3.7 0.5 1.3 0.0 2.8 0 52
115 21 8 745 298 11 0.0 3.7 0.5 1.5 0.0 14.0 0 52
116 19 8 747 298 21 0.0 3.7 0.5 2.1 0.0 5.8 0 52
117 13 8 737 298 12 0.0 3.7 0.5 1.0 0.0 10.0 0 52
118 9 8 736 298 4 0.0 3.7 0.5 1.5 0.0 18.5 0 52
119 0 8 739 298 0 0.0 3.7 0.5 1.8 0.0 18.0 0 52
120 0 8 732 298 0 0.0 3.7 0.5 1.2 0.0 21.8 0 52
121 0 8 732 19 -1 0.0 0.0 0.5 0.0 100.0 54.8
Initial Wiring Cost: 645 Final Wiring Cost: 732
############## Percent Wire Cost Reduction: -13
Initial Wire Length: 645 Final Wire Length: 732
************** Percent Wire Length Reduction: -13
Initial Horiz. Wire: 216 Final Horiz. Wire: 147
$$$$$$$$$$$ Percent H-Wire Length Reduction: 32
Initial Vert. Wire: 429 Final Vert. Wire: 585
@@@@@@@@@@@ Percent V-Wire Length Reduction: -36
Before Feeds are Added:
BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET
1 82 -20
2 86 -16
LONGEST Block is:2 Its length is:86
BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET
1 86 -16
2 86 -16
LONGEST Block is:1 Its length is:86
Added: 1 feed-through cells
Removed the cell overlaps --- Will do neighbor interchanges only now
TOTAL INTERCONNECT LENGTH: 994
OVERLAP PENALTY: 0
initialRowControl: 1.650
finalRowControl: 0.300
iter T Wire accept
122 0.001 976 16%
123 0.001 971 0%
124 0.001 971 0%
Total Feed-Alignment Movement (Pass 1): 0
Total Feed-Alignment Movement (Pass 2): 0
Total Feed-Alignment Movement (Pass 3): 0
Total Feed-Alignment Movement (Pass 4): 0
Total Feed-Alignment Movement (Pass 5): 0
Total Feed-Alignment Movement (Pass 6): 0
Total Feed-Alignment Movement (Pass 7): 0
Total Feed-Alignment Movement (Pass 8): 0
The rand generator seed was at globroute() : 987654321
Total Number of Net Segments: 9
Number of Switchable Net Segments: 0
Number of channels: 3
THIS IS THE ORIGINAL NUMBER OF TRACKS: 5
no. of accepted flips: 0
no. of attempted flips: 0
THIS IS THE NUMBER OF TRACKS: 5
FINAL NUMBER OF ROUTING TRACKS: 5
MAX OF CHANNEL: 1 is: 0
MAX OF CHANNEL: 2 is: 4
MAX OF CHANNEL: 3 is: 1
FINAL TOTAL INTERCONNECT LENGTH: 978
FINAL OVERLAP PENALTY: 0 FINAL VALUE OF TOTAL COST IS: 978
MAX NUMBER OF ATTEMPTED FLIPS PER T: 55
cost_scale_factor:3.90616
Number of Feed Thrus: 0
Number of Implicit Feed Thrus: 0
Statistics:
Number of Standard Cells: 10
Number of Pads: 0
Number of Nets: 15
Number of Pins: 46
Usage statistics not available

700
simulators/gem5/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt Normal file
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---------- Begin Simulation Statistics ----------
sim_seconds 0.076323 # Number of seconds simulated
sim_ticks 76322764500 # Number of ticks simulated
final_tick 76322764500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 95790 # Simulator instruction rate (inst/s)
host_op_rate 104880 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 42423254 # Simulator tick rate (ticks/s)
host_mem_usage 235620 # Number of bytes of host memory used
host_seconds 1799.08 # Real time elapsed on the host
sim_insts 172333279 # Number of instructions simulated
sim_ops 188686762 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 133376 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 113216 # Number of bytes read from this memory
system.physmem.bytes_read::total 246592 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 133376 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 133376 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 2084 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 1769 # Number of read requests responded to by this memory
system.physmem.num_reads::total 3853 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 1747526 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 1483384 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 3230910 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 1747526 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 1747526 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 1747526 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 1483384 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 3230910 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 400 # Number of system calls
system.cpu.numCycles 152645530 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.BPredUnit.lookups 97143446 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 76317615 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 6623022 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 46654244 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 44354550 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 4440290 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 115738 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 40856932 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 389909160 # Number of instructions fetch has processed
system.cpu.fetch.Branches 97143446 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 48794840 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 82559996 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 28665024 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 7154273 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 8876 # Number of stall cycles due to pending traps
system.cpu.fetch.PendingQuiesceStallCycles 1 # Number of stall cycles due to pending quiesce instructions
system.cpu.fetch.CacheLines 37841460 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 1897566 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 152586857 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.799629 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.155476 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 70197419 46.00% 46.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 5514909 3.61% 49.62% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 10699531 7.01% 56.63% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 10457896 6.85% 63.48% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 8809329 5.77% 69.26% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 6861836 4.50% 73.76% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 6316245 4.14% 77.89% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 8382546 5.49% 83.39% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 25347146 16.61% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 152586857 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.636399 # Number of branch fetches per cycle
system.cpu.fetch.rate 2.554344 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 46935408 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 5876258 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 76807695 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 1114753 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 21852743 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 14847820 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 163458 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 403001894 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 745204 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 21852743 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 52498514 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 705487 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 794640 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 72299255 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 4436218 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 380239935 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 4 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 319922 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 3547314 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenamedOperands 643715569 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 1619843514 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 1602242427 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 17601087 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 298092552 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 345623017 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 60567 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 60564 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 12828776 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 44110344 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 16988908 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 5691426 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 3676812 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 335623795 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 80679 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 253280777 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 910888 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 145778004 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 375851378 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 29413 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 152586857 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 1.659912 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.759603 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 58969897 38.65% 38.65% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 23051369 15.11% 53.75% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 25143684 16.48% 70.23% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 20551680 13.47% 83.70% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 12918795 8.47% 92.17% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 6596322 4.32% 96.49% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 4048422 2.65% 99.14% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 1113826 0.73% 99.87% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 192862 0.13% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 152586857 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 968336 37.79% 37.79% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 5589 0.22% 38.01% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 38.01% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 38.01% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 38.01% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 38.01% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 38.01% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 38.01% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 38.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 38.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 38.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 38.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 38.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 38.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 38.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 38.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 38.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 38.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 38.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 38.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 91 0.00% 38.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 38.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 38.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 38.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 38.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 33 0.00% 38.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 38.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 38.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 38.01% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 1185185 46.25% 84.27% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 403164 15.73% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 197697657 78.05% 78.05% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 995408 0.39% 78.45% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.45% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.45% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.45% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 78.45% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 78.45% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 78.45% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 78.45% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 78.45% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 78.45% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 78.45% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 78.45% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 78.45% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 78.45% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 78.45% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.45% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.45% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.45% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.45% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 33135 0.01% 78.46% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.46% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 164107 0.06% 78.53% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 254969 0.10% 78.63% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 76438 0.03% 78.66% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 467546 0.18% 78.84% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 206313 0.08% 78.92% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 71855 0.03% 78.95% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 320 0.00% 78.95% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 39090450 15.43% 94.38% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 14222579 5.62% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 253280777 # Type of FU issued
system.cpu.iq.rate 1.659274 # Inst issue rate
system.cpu.iq.fu_busy_cnt 2562398 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.010117 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 658846824 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 479250938 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 240868765 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 3774873 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 2250330 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 1852271 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 253948063 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 1895112 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 2034666 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 14254809 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 18806 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 19550 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 4338224 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 46 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 21852743 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 13300 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 608 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 335763367 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 963800 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 44110344 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 16988908 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 58117 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 150 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 281 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 19550 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 4170846 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 3956659 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 8127505 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 246138856 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 37439094 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 7141921 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 58893 # number of nop insts executed
system.cpu.iew.exec_refs 51255438 # number of memory reference insts executed
system.cpu.iew.exec_branches 54101167 # Number of branches executed
system.cpu.iew.exec_stores 13816344 # Number of stores executed
system.cpu.iew.exec_rate 1.612486 # Inst execution rate
system.cpu.iew.wb_sent 243866975 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 242721036 # cumulative count of insts written-back
system.cpu.iew.wb_producers 150184249 # num instructions producing a value
system.cpu.iew.wb_consumers 269391648 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 1.590096 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.557494 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitCommittedInsts 172347667 # The number of committed instructions
system.cpu.commit.commitCommittedOps 188701150 # The number of committed instructions
system.cpu.commit.commitSquashedInsts 147062192 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 51266 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 6488296 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 130734115 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.443396 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.157229 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 60440090 46.23% 46.23% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 32094015 24.55% 70.78% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 14011020 10.72% 81.50% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 7691837 5.88% 87.38% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 4423613 3.38% 90.76% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 1340820 1.03% 91.79% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 1731909 1.32% 93.12% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 1286910 0.98% 94.10% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 7713901 5.90% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 130734115 # Number of insts commited each cycle
system.cpu.commit.committedInsts 172347667 # Number of instructions committed
system.cpu.commit.committedOps 188701150 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 42506219 # Number of memory references committed
system.cpu.commit.loads 29855535 # Number of loads committed
system.cpu.commit.membars 22408 # Number of memory barriers committed
system.cpu.commit.branches 40287733 # Number of branches committed
system.cpu.commit.fp_insts 1752310 # Number of committed floating point instructions.
system.cpu.commit.int_insts 150130425 # Number of committed integer instructions.
system.cpu.commit.function_calls 1848934 # Number of function calls committed.
system.cpu.commit.bw_lim_events 7713901 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 458778355 # The number of ROB reads
system.cpu.rob.rob_writes 693498788 # The number of ROB writes
system.cpu.timesIdled 1746 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 58673 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 172333279 # Number of Instructions Simulated
system.cpu.committedOps 188686762 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 172333279 # Number of Instructions Simulated
system.cpu.cpi 0.885758 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.885758 # CPI: Total CPI of All Threads
system.cpu.ipc 1.128977 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.128977 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 1093182861 # number of integer regfile reads
system.cpu.int_regfile_writes 388952433 # number of integer regfile writes
system.cpu.fp_regfile_reads 2911975 # number of floating regfile reads
system.cpu.fp_regfile_writes 2511798 # number of floating regfile writes
system.cpu.misc_regfile_reads 476343702 # number of misc regfile reads
system.cpu.misc_regfile_writes 832136 # number of misc regfile writes
system.cpu.icache.replacements 2645 # number of replacements
system.cpu.icache.tagsinuse 1374.603363 # Cycle average of tags in use
system.cpu.icache.total_refs 37836261 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 4394 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 8610.892353 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 1374.603363 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.671193 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.671193 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 37836261 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 37836261 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 37836261 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 37836261 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 37836261 # number of overall hits
system.cpu.icache.overall_hits::total 37836261 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 5199 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 5199 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 5199 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 5199 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 5199 # number of overall misses
system.cpu.icache.overall_misses::total 5199 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 112756500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 112756500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 112756500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 112756500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 112756500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 112756500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 37841460 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 37841460 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 37841460 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 37841460 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 37841460 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 37841460 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000137 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000137 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000137 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000137 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000137 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000137 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21688.113099 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 21688.113099 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 21688.113099 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 21688.113099 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 21688.113099 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 21688.113099 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 804 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 804 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 804 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 804 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 804 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 804 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4395 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 4395 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 4395 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 4395 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 4395 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 4395 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 78893000 # number of ReadReq MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_latency::cpu.inst 78893000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 78893000 # number of overall MSHR miss cycles
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system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17950.625711 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17950.625711 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17950.625711 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 17950.625711 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17950.625711 # average overall mshr miss latency
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system.cpu.dcache.WriteReq_avg_miss_latency::total 31186.530880 # average WriteReq miss latency
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system.cpu.dcache.overall_mshr_miss_latency::total 63473000 # number of overall MSHR miss cycles
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31853.855721 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35155.524605 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35155.524605 # average WriteReq mshr miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency::total 33744.284955 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 33744.284955 # average overall mshr miss latency
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system.cpu.l2cache.demand_mshr_miss_latency::total 119705000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 64692000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 55013000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 119705000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.474175 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.871891 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.535680 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.991643 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.991643 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.474175 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.940457 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.613926 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.474175 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.940457 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.613926 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31042.226488 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31179.743224 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31076.840215 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31044.943820 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31044.943820 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31042.226488 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31098.360656 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31067.998962 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31042.226488 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31098.360656 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31067.998962 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

135
simulators/gem5/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/config.ini Normal file
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@ -0,0 +1,135 @@
[root]
type=Root
children=system
full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
boot_osflags=a
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
readfile=
symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.cpu]
type=AtomicSimpleCPU
children=dtb interrupts itb tracer workload
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
fastmem=false
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
phase=0
profile=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
system=system
tracer=system.cpu.tracer
width=1
workload=system.cpu.workload
dcache_port=system.membus.slave[2]
icache_port=system.membus.slave[1]
[system.cpu.dtb]
type=ArmTLB
children=walker
size=64
walker=system.cpu.dtb.walker
[system.cpu.dtb.walker]
type=ArmTableWalker
max_backoff=100000
min_backoff=0
sys=system
port=system.membus.slave[4]
[system.cpu.interrupts]
type=ArmInterrupts
[system.cpu.itb]
type=ArmTLB
children=walker
size=64
walker=system.cpu.itb.walker
[system.cpu.itb.walker]
type=ArmTableWalker
max_backoff=100000
min_backoff=0
sys=system
port=system.membus.slave[3]
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=twolf smred
cwd=build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-atomic
egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/cpu2000/binaries/arm/linux/twolf
gid=100
input=cin
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=0
system=system
uid=100
[system.membus]
type=CoherentBus
block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
master=system.physmem.port[0]
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port
[system.physmem]
type=SimpleMemory
conf_table_reported=false
file=
in_addr_map=true
latency=30000
latency_var=0
null=false
range=0:134217727
zero=false
port=system.membus.master[0]

2
simulators/gem5/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/simerr Executable file
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warn: Sockets disabled, not accepting gdb connections
hack: be nice to actually delete the event here

26
simulators/gem5/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/simout Executable file
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@ -0,0 +1,26 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 4 2012 12:14:06
gem5 started Jun 4 2012 18:53:41
gem5 executing on zizzer
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-atomic
Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-atomic/smred.sav
Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-atomic/smred.sv2
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
Standard Cell Placement and Global Routing Program
Authors: Carl Sechen, Bill Swartz
Yale University
info: Increasing stack size by one page.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
61 62 63 64 65 66 67 68 69 70 71 72 73 74 75
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
122 123 124 Exiting @ tick 103106771000 because target called exit()

276
simulators/gem5/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/smred.out Normal file
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@ -0,0 +1,276 @@
TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
Standard Cell Placement and Global Routing Program
Authors: Carl Sechen, Bill Swartz
Yale University
NOTE: Restart file .rs2 not used
TimberWolf will perform a global route step
rowSep: 1.000000
feedThruWidth: 4
******************
BLOCK DATA
block:1 desire:85
block:2 desire:85
Total Desired Length: 170
total cell length: 168
total block length: 168
block x-span:84 block y-span:78
implicit feed thru range: -84
Using default value of bin.penalty.control:1.000000
numBins automatically set to:5
binWidth = average_cell_width + 0 sigma= 17
average_cell_width is:16
standard deviation of cell length is:23.6305
TimberWolfSC starting from the beginning
THIS IS THE ROUTE COST OF THE ORIGINAL PLACEMENT: 645
The number of nets with 1 pin is 4
The number of nets with 2 pin is 9
The number of nets with 3 pin is 0
The number of nets with 4 pin is 2
The number of nets with 5 pin is 0
The number of nets with 6 pin is 0
The number of nets with 7 pin is 0
The number of nets with 8 pin is 0
The number of nets with 9 pin is 0
The number of nets with 10 pin or more is 0
New Cost Function: Initial Horizontal Cost:242
New Cost Function: FEEDS:0 MISSING_ROWS:-46
bdxlen:86 bdylen:78
l:0 t:78 r:86 b:0
THIS IS THE ROUTE COST OF THE CURRENT PLACEMENT: 645
THIS IS THE PENALTY OF THE CURRENT PLACEMENT: 44
The rand generator seed was at utemp() : 1
tempfile[0][0] = 0.982500 tempfile[0][1] = 90.000000
tempfile[1][0] = 0.915000 tempfile[1][1] = 20.000000
tempfile[2][0] = 0.700000 tempfile[2][1] = 10.000000
tempfile[3][0] = 0.100000 tempfile[3][1] = 0.000000
I T fds Wire Penalty P_lim Epct binC rowC acc s/p early FDs MRs
1 500 0 929 592 160 30.0 1.0 3.0 84.2 34.7 0.0 0 40
2 491 0 876 106 726 0.0 0.8 2.5 80.0 18.5 0.0 0 46
3 482 0 822 273 372 0.0 0.5 1.5 80.8 21.2 0.0 0 46
4 474 0 826 53 247 0.0 0.5 0.9 65.0 21.9 0.0 0 48
5 465 8 987 73 190 0.0 0.5 0.5 50.0 38.3 0.0 0 46
6 457 8 851 67 226 0.0 0.5 0.5 53.8 42.9 0.0 0 52
7 449 8 1067 108 190 0.0 0.5 0.5 46.2 53.8 0.0 0 50
8 441 8 918 106 171 0.0 0.5 0.5 47.1 40.4 0.0 0 48
9 434 8 812 101 197 0.0 0.5 0.5 53.6 21.0 0.0 0 48
10 426 8 1038 121 181 0.0 0.5 0.5 43.6 27.1 0.0 0 48
11 419 8 898 93 187 0.0 0.5 0.5 45.3 47.8 0.0 0 50
12 411 4 857 94 240 0.0 0.5 0.5 62.7 51.6 0.0 0 44
13 404 8 1043 88 185 0.0 0.5 0.5 54.0 52.8 0.0 0 50
14 397 8 767 94 154 0.0 0.5 0.5 33.8 35.0 0.0 0 50
15 390 8 862 89 183 0.0 0.5 0.5 55.6 29.0 0.0 0 46
16 383 4 798 79 173 0.0 0.5 0.5 57.5 35.3 0.0 0 52
17 376 8 827 100 152 0.0 0.5 0.5 35.3 81.8 0.0 0 50
18 370 8 878 101 208 0.0 0.5 0.5 44.7 46.2 0.0 0 48
19 363 4 921 67 167 0.0 0.5 0.5 57.1 34.7 0.0 0 48
20 357 8 933 93 154 0.0 0.5 0.5 46.5 43.6 0.0 0 52
21 351 8 930 89 147 0.0 0.5 0.5 39.4 36.5 0.0 0 52
22 345 8 951 79 142 0.0 0.5 0.5 32.8 51.3 0.0 0 50
23 339 8 1046 87 207 0.0 0.5 0.5 52.8 61.0 0.0 0 48
24 333 4 989 96 185 0.0 0.5 0.5 45.3 43.3 0.0 0 42
25 327 4 577 86 157 0.0 0.5 0.5 31.1 55.3 0.0 0 52
26 321 8 776 97 174 0.0 0.5 0.5 47.9 62.5 0.0 0 52
27 315 8 850 81 188 0.0 0.5 0.5 45.0 55.2 0.0 0 50
28 310 8 898 97 148 0.0 0.5 0.5 43.0 45.8 0.0 0 48
29 304 8 889 65 173 0.0 0.5 0.5 32.5 41.3 0.0 0 50
30 299 8 858 81 153 0.0 0.5 0.5 44.3 29.2 0.0 0 46
31 294 8 871 82 187 0.0 0.5 0.5 45.7 47.7 0.0 0 48
32 289 8 782 109 173 0.0 0.5 0.5 35.2 57.4 0.0 0 48
33 284 8 743 98 189 0.0 0.6 0.5 41.8 64.3 0.0 0 52
34 279 8 943 90 147 0.0 0.5 0.5 38.6 32.8 0.0 0 48
35 274 8 907 57 166 0.0 0.5 0.5 33.6 51.0 0.0 0 48
36 269 8 900 70 148 0.0 0.5 0.5 45.0 41.4 0.0 0 50
37 264 4 875 106 133 0.0 0.5 0.5 31.7 55.3 0.0 0 52
38 260 8 1023 145 149 0.0 0.6 0.5 28.7 65.0 0.0 0 52
39 255 8 801 151 173 0.0 0.9 0.5 41.7 41.2 0.0 0 48
40 251 8 741 104 159 0.0 0.8 0.5 36.2 47.5 0.0 0 48
41 246 8 828 108 149 0.0 0.5 0.5 34.6 50.9 0.0 0 50
42 242 8 947 128 132 0.0 0.7 0.5 34.2 39.0 0.0 0 50
43 238 8 917 101 142 0.0 0.8 0.5 34.4 50.9 0.0 0 48
44 234 8 761 86 129 0.0 0.5 0.5 42.0 36.4 0.0 0 52
45 229 8 979 106 137 0.0 0.5 0.5 29.2 55.3 0.0 0 50
46 225 8 806 74 130 0.0 0.7 0.5 33.1 65.4 0.0 0 52
47 221 8 971 125 114 0.0 0.5 0.5 31.9 45.6 0.0 0 52
48 218 8 869 125 104 0.0 0.9 0.5 30.0 56.0 0.0 0 48
49 214 8 999 153 140 0.0 0.8 0.5 30.4 46.4 0.0 0 52
50 210 8 798 192 139 0.0 1.0 0.5 28.9 50.0 0.0 0 52
51 206 8 860 125 157 0.0 1.2 0.5 31.5 26.9 0.0 0 52
52 203 8 893 186 127 5.9 0.9 0.5 26.4 42.3 0.0 0 46
53 199 8 863 126 141 0.0 1.2 0.5 32.5 44.4 0.0 0 44
54 196 8 788 97 133 0.0 0.9 0.5 37.5 40.0 0.0 0 50
55 192 8 926 119 116 0.0 0.6 0.5 26.1 55.3 0.0 0 52
56 189 8 789 162 107 0.0 0.8 0.5 25.2 40.4 0.0 0 48
57 186 8 878 107 128 0.0 1.1 0.5 23.1 34.0 0.0 0 52
58 182 8 775 105 122 0.0 0.8 0.5 25.5 57.4 0.0 0 50
59 179 8 747 94 129 0.0 0.7 0.5 34.3 37.3 0.0 0 50
60 176 8 845 96 138 0.0 0.6 0.5 28.3 41.7 0.0 0 52
61 173 8 961 121 110 0.0 0.6 0.5 29.0 52.6 0.0 0 48
62 170 4 911 110 109 0.0 0.9 0.5 33.5 33.3 0.0 0 48
63 167 8 656 109 109 0.0 0.8 0.5 21.9 44.7 0.0 0 52
64 164 8 934 117 105 0.0 0.8 0.5 15.5 50.0 0.0 0 52
65 161 8 972 125 95 0.0 0.8 0.5 24.4 50.0 0.0 0 50
66 158 8 894 125 101 0.0 0.9 0.5 27.2 35.9 0.0 0 52
67 155 8 798 146 129 0.0 1.0 0.5 22.8 58.7 0.0 0 52
68 153 8 901 183 92 0.0 1.1 0.5 23.6 34.5 0.0 0 52
69 150 8 977 197 103 0.0 1.4 0.5 23.6 36.8 0.0 0 52
70 147 8 905 262 93 0.0 1.5 0.5 20.3 63.4 0.0 0 52
71 145 8 995 148 122 0.0 1.9 0.5 20.9 35.3 0.0 0 52
72 142 8 934 230 99 0.0 1.6 0.5 20.0 65.9 0.0 0 52
73 140 8 862 173 100 0.0 1.8 0.5 26.8 46.8 0.0 0 52
74 137 8 924 139 90 0.0 1.7 0.5 16.8 42.5 0.0 0 52
75 135 8 888 168 113 0.0 1.6 0.5 22.9 40.4 0.0 0 52
76 133 8 712 212 84 0.0 1.6 0.5 13.4 46.9 0.0 0 52
77 130 8 868 210 91 0.0 1.7 0.5 17.7 51.2 0.0 0 52
78 128 8 952 307 92 0.0 1.9 0.5 19.7 44.9 0.0 0 50
79 126 8 801 157 107 0.0 2.2 0.5 15.8 39.0 0.0 0 52
80 123 8 849 147 93 0.0 2.1 0.5 15.6 51.4 0.0 0 52
81 121 8 799 154 86 0.0 1.9 0.5 12.2 50.0 0.0 0 52
82 119 8 941 213 82 0.0 1.8 0.5 19.5 41.2 0.0 0 50
83 117 8 751 268 94 0.0 2.0 0.5 20.8 42.6 0.0 0 50
84 115 8 828 198 102 0.0 2.2 0.5 15.5 59.5 0.0 0 52
85 113 8 898 266 123 0.0 2.2 0.5 13.2 85.2 0.0 0 52
86 111 8 943 190 93 0.0 2.4 0.5 19.5 45.1 0.0 0 52
87 109 8 864 183 65 0.0 2.4 0.5 14.9 31.8 0.0 0 52
88 107 8 793 203 93 0.0 2.4 0.5 11.8 35.3 0.0 0 52
89 105 8 752 162 74 1.2 2.4 0.5 13.1 21.4 0.0 0 52
90 103 8 801 149 77 0.0 2.3 0.5 9.7 58.3 0.0 0 52
91 102 8 901 230 99 0.0 2.2 0.5 16.0 25.5 0.0 0 52
92 100 8 826 201 87 0.0 2.4 0.5 12.8 45.7 0.0 0 52
93 98 8 810 196 83 0.0 2.5 0.5 14.0 24.4 0.0 0 52
94 96 8 857 209 68 1.0 2.5 0.5 11.5 27.0 5.1 0 52
95 95 8 771 174 91 0.0 2.6 0.5 10.5 26.5 0.0 0 52
96 93 8 955 210 59 0.0 2.6 0.5 10.0 36.7 0.7 0 52
97 91 8 833 206 53 0.0 2.7 0.5 10.2 19.4 1.4 0 52
98 90 8 888 229 86 0.0 2.8 0.5 8.1 36.0 0.0 0 52
99 88 8 794 186 91 1.0 2.9 0.5 8.3 25.0 0.5 0 52
100 81 8 756 170 72 1.0 2.9 0.5 6.0 23.8 7.0 0 52
101 74 8 791 176 67 0.0 2.9 0.5 4.4 58.3 4.0 0 52
102 67 8 813 213 43 0.0 3.0 0.5 7.0 150.0 4.2 0 52
103 62 8 779 245 39 0.0 3.1 0.5 3.2 16.7 13.0 0 52
104 56 8 767 303 63 0.0 3.2 0.5 4.1 20.0 0.7 0 52
105 52 8 757 270 57 0.0 3.5 0.5 6.4 3.7 0.5 0 52
106 47 8 763 283 41 0.0 3.7 0.5 4.5 0.0 0.0 0 52
107 43 8 768 283 36 0.0 3.7 0.5 2.9 18.2 3.6 0 52
108 39 8 804 283 25 0.0 3.7 0.5 3.1 0.0 6.2 0 52
109 36 8 781 283 24 0.0 3.7 0.5 3.6 6.7 6.7 0 52
110 33 8 738 298 42 0.0 3.7 0.5 3.3 15.4 3.5 0 52
111 30 8 761 298 36 0.0 3.7 0.5 2.2 0.0 4.3 0 52
112 27 8 769 298 37 0.0 3.7 0.5 0.9 0.0 2.2 0 52
113 25 8 745 298 31 0.0 3.7 0.5 1.5 0.0 6.6 0 52
114 23 8 753 298 16 0.0 3.7 0.5 1.3 0.0 2.8 0 52
115 21 8 745 298 11 0.0 3.7 0.5 1.5 0.0 14.0 0 52
116 19 8 747 298 21 0.0 3.7 0.5 2.1 0.0 5.8 0 52
117 13 8 737 298 12 0.0 3.7 0.5 1.0 0.0 10.0 0 52
118 9 8 736 298 4 0.0 3.7 0.5 1.5 0.0 18.5 0 52
119 0 8 739 298 0 0.0 3.7 0.5 1.8 0.0 18.0 0 52
120 0 8 732 298 0 0.0 3.7 0.5 1.2 0.0 21.8 0 52
121 0 8 732 19 -1 0.0 0.0 0.5 0.0 100.0 54.8
Initial Wiring Cost: 645 Final Wiring Cost: 732
############## Percent Wire Cost Reduction: -13
Initial Wire Length: 645 Final Wire Length: 732
************** Percent Wire Length Reduction: -13
Initial Horiz. Wire: 216 Final Horiz. Wire: 147
$$$$$$$$$$$ Percent H-Wire Length Reduction: 32
Initial Vert. Wire: 429 Final Vert. Wire: 585
@@@@@@@@@@@ Percent V-Wire Length Reduction: -36
Before Feeds are Added:
BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET
1 82 -20
2 86 -16
LONGEST Block is:2 Its length is:86
BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET
1 86 -16
2 86 -16
LONGEST Block is:1 Its length is:86
Added: 1 feed-through cells
Removed the cell overlaps --- Will do neighbor interchanges only now
TOTAL INTERCONNECT LENGTH: 994
OVERLAP PENALTY: 0
initialRowControl: 1.650
finalRowControl: 0.300
iter T Wire accept
122 0.001 976 16%
123 0.001 971 0%
124 0.001 971 0%
Total Feed-Alignment Movement (Pass 1): 0
Total Feed-Alignment Movement (Pass 2): 0
Total Feed-Alignment Movement (Pass 3): 0
Total Feed-Alignment Movement (Pass 4): 0
Total Feed-Alignment Movement (Pass 5): 0
Total Feed-Alignment Movement (Pass 6): 0
Total Feed-Alignment Movement (Pass 7): 0
Total Feed-Alignment Movement (Pass 8): 0
The rand generator seed was at globroute() : 987654321
Total Number of Net Segments: 9
Number of Switchable Net Segments: 0
Number of channels: 3
THIS IS THE ORIGINAL NUMBER OF TRACKS: 5
no. of accepted flips: 0
no. of attempted flips: 0
THIS IS THE NUMBER OF TRACKS: 5
FINAL NUMBER OF ROUTING TRACKS: 5
MAX OF CHANNEL: 1 is: 0
MAX OF CHANNEL: 2 is: 4
MAX OF CHANNEL: 3 is: 1
FINAL TOTAL INTERCONNECT LENGTH: 978
FINAL OVERLAP PENALTY: 0 FINAL VALUE OF TOTAL COST IS: 978
MAX NUMBER OF ATTEMPTED FLIPS PER T: 55
cost_scale_factor:3.90616
Number of Feed Thrus: 0
Number of Implicit Feed Thrus: 0
Statistics:
Number of Standard Cells: 10
Number of Pads: 0
Number of Nets: 15
Number of Pins: 46
Usage statistics not available

102
simulators/gem5/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt Normal file
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@ -0,0 +1,102 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.103107 # Number of seconds simulated
sim_ticks 103106771000 # Number of ticks simulated
final_tick 103106771000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 2060024 # Simulator instruction rate (inst/s)
host_op_rate 2255526 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1232622542 # Simulator tick rate (ticks/s)
host_mem_usage 224496 # Number of bytes of host memory used
host_seconds 83.65 # Real time elapsed on the host
sim_insts 172317417 # Number of instructions simulated
sim_ops 188670900 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 759440240 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 110533662 # Number of bytes read from this memory
system.physmem.bytes_read::total 869973902 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 759440240 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 759440240 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 45252940 # Number of bytes written to this memory
system.physmem.bytes_written::total 45252940 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 189860060 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 29622454 # Number of read requests responded to by this memory
system.physmem.num_reads::total 219482514 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 12386694 # Number of write requests responded to by this memory
system.physmem.num_writes::total 12386694 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 7365570977 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 1072031070 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 8437602047 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 7365570977 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 7365570977 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 438893969 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 438893969 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 7365570977 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 1510925039 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 8876496016 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 400 # Number of system calls
system.cpu.numCycles 206213543 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 172317417 # Number of instructions committed
system.cpu.committedOps 188670900 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 150106226 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 1752310 # Number of float alu accesses
system.cpu.num_func_calls 3504894 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 32493891 # number of instructions that are conditional controls
system.cpu.num_int_insts 150106226 # number of integer instructions
system.cpu.num_fp_insts 1752310 # number of float instructions
system.cpu.num_int_register_reads 809396650 # number of times the integer registers were read
system.cpu.num_int_register_writes 294073530 # number of times the integer registers were written
system.cpu.num_fp_register_reads 2822225 # number of times the floating registers were read
system.cpu.num_fp_register_writes 2378039 # number of times the floating registers were written
system.cpu.num_mem_refs 42494120 # number of memory refs
system.cpu.num_load_insts 29849485 # Number of load instructions
system.cpu.num_store_insts 12644635 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 206213543 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
---------- End Simulation Statistics ----------

216
simulators/gem5/tests/long/se/70.twolf/ref/arm/linux/simple-timing/config.ini Normal file
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[root]
type=Root
children=system
full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
boot_osflags=a
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
readfile=
symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.cpu]
type=TimingSimpleCPU
children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
phase=0
profile=0
progress_interval=0
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=262144
subblock_size=0
system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
[system.cpu.dtb]
type=ArmTLB
children=walker
size=64
walker=system.cpu.dtb.walker
[system.cpu.dtb.walker]
type=ArmTableWalker
max_backoff=100000
min_backoff=0
sys=system
port=system.cpu.toL2Bus.slave[3]
[system.cpu.icache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=131072
subblock_size=0
system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.interrupts]
type=ArmInterrupts
[system.cpu.itb]
type=ArmTLB
children=walker
size=64
walker=system.cpu.itb.walker
[system.cpu.itb.walker]
type=ArmTableWalker
max_backoff=100000
min_backoff=0
sys=system
port=system.cpu.toL2Bus.slave[2]
[system.cpu.l2cache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=false
latency=10000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=2097152
subblock_size=0
system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
[system.cpu.toL2Bus]
type=CoherentBus
block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=twolf smred
cwd=build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-timing
egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/cpu2000/binaries/arm/linux/twolf
gid=100
input=cin
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=0
system=system
uid=100
[system.membus]
type=CoherentBus
block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
master=system.physmem.port[0]
slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=SimpleMemory
conf_table_reported=false
file=
in_addr_map=true
latency=30000
latency_var=0
null=false
range=0:134217727
zero=false
port=system.membus.master[0]

2
simulators/gem5/tests/long/se/70.twolf/ref/arm/linux/simple-timing/simerr Executable file
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@ -0,0 +1,2 @@
warn: Sockets disabled, not accepting gdb connections
hack: be nice to actually delete the event here

26
simulators/gem5/tests/long/se/70.twolf/ref/arm/linux/simple-timing/simout Executable file
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@ -0,0 +1,26 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 4 2012 12:14:06
gem5 started Jun 4 2012 18:54:15
gem5 executing on zizzer
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-timing
Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-timing/smred.sav
Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-timing/smred.sv2
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
Standard Cell Placement and Global Routing Program
Authors: Carl Sechen, Bill Swartz
Yale University
info: Increasing stack size by one page.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
61 62 63 64 65 66 67 68 69 70 71 72 73 74 75
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
122 123 124 Exiting @ tick 232077154000 because target called exit()

276
simulators/gem5/tests/long/se/70.twolf/ref/arm/linux/simple-timing/smred.out Normal file
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@ -0,0 +1,276 @@
TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
Standard Cell Placement and Global Routing Program
Authors: Carl Sechen, Bill Swartz
Yale University
NOTE: Restart file .rs2 not used
TimberWolf will perform a global route step
rowSep: 1.000000
feedThruWidth: 4
******************
BLOCK DATA
block:1 desire:85
block:2 desire:85
Total Desired Length: 170
total cell length: 168
total block length: 168
block x-span:84 block y-span:78
implicit feed thru range: -84
Using default value of bin.penalty.control:1.000000
numBins automatically set to:5
binWidth = average_cell_width + 0 sigma= 17
average_cell_width is:16
standard deviation of cell length is:23.6305
TimberWolfSC starting from the beginning
THIS IS THE ROUTE COST OF THE ORIGINAL PLACEMENT: 645
The number of nets with 1 pin is 4
The number of nets with 2 pin is 9
The number of nets with 3 pin is 0
The number of nets with 4 pin is 2
The number of nets with 5 pin is 0
The number of nets with 6 pin is 0
The number of nets with 7 pin is 0
The number of nets with 8 pin is 0
The number of nets with 9 pin is 0
The number of nets with 10 pin or more is 0
New Cost Function: Initial Horizontal Cost:242
New Cost Function: FEEDS:0 MISSING_ROWS:-46
bdxlen:86 bdylen:78
l:0 t:78 r:86 b:0
THIS IS THE ROUTE COST OF THE CURRENT PLACEMENT: 645
THIS IS THE PENALTY OF THE CURRENT PLACEMENT: 44
The rand generator seed was at utemp() : 1
tempfile[0][0] = 0.982500 tempfile[0][1] = 90.000000
tempfile[1][0] = 0.915000 tempfile[1][1] = 20.000000
tempfile[2][0] = 0.700000 tempfile[2][1] = 10.000000
tempfile[3][0] = 0.100000 tempfile[3][1] = 0.000000
I T fds Wire Penalty P_lim Epct binC rowC acc s/p early FDs MRs
1 500 0 929 592 160 30.0 1.0 3.0 84.2 34.7 0.0 0 40
2 491 0 876 106 726 0.0 0.8 2.5 80.0 18.5 0.0 0 46
3 482 0 822 273 372 0.0 0.5 1.5 80.8 21.2 0.0 0 46
4 474 0 826 53 247 0.0 0.5 0.9 65.0 21.9 0.0 0 48
5 465 8 987 73 190 0.0 0.5 0.5 50.0 38.3 0.0 0 46
6 457 8 851 67 226 0.0 0.5 0.5 53.8 42.9 0.0 0 52
7 449 8 1067 108 190 0.0 0.5 0.5 46.2 53.8 0.0 0 50
8 441 8 918 106 171 0.0 0.5 0.5 47.1 40.4 0.0 0 48
9 434 8 812 101 197 0.0 0.5 0.5 53.6 21.0 0.0 0 48
10 426 8 1038 121 181 0.0 0.5 0.5 43.6 27.1 0.0 0 48
11 419 8 898 93 187 0.0 0.5 0.5 45.3 47.8 0.0 0 50
12 411 4 857 94 240 0.0 0.5 0.5 62.7 51.6 0.0 0 44
13 404 8 1043 88 185 0.0 0.5 0.5 54.0 52.8 0.0 0 50
14 397 8 767 94 154 0.0 0.5 0.5 33.8 35.0 0.0 0 50
15 390 8 862 89 183 0.0 0.5 0.5 55.6 29.0 0.0 0 46
16 383 4 798 79 173 0.0 0.5 0.5 57.5 35.3 0.0 0 52
17 376 8 827 100 152 0.0 0.5 0.5 35.3 81.8 0.0 0 50
18 370 8 878 101 208 0.0 0.5 0.5 44.7 46.2 0.0 0 48
19 363 4 921 67 167 0.0 0.5 0.5 57.1 34.7 0.0 0 48
20 357 8 933 93 154 0.0 0.5 0.5 46.5 43.6 0.0 0 52
21 351 8 930 89 147 0.0 0.5 0.5 39.4 36.5 0.0 0 52
22 345 8 951 79 142 0.0 0.5 0.5 32.8 51.3 0.0 0 50
23 339 8 1046 87 207 0.0 0.5 0.5 52.8 61.0 0.0 0 48
24 333 4 989 96 185 0.0 0.5 0.5 45.3 43.3 0.0 0 42
25 327 4 577 86 157 0.0 0.5 0.5 31.1 55.3 0.0 0 52
26 321 8 776 97 174 0.0 0.5 0.5 47.9 62.5 0.0 0 52
27 315 8 850 81 188 0.0 0.5 0.5 45.0 55.2 0.0 0 50
28 310 8 898 97 148 0.0 0.5 0.5 43.0 45.8 0.0 0 48
29 304 8 889 65 173 0.0 0.5 0.5 32.5 41.3 0.0 0 50
30 299 8 858 81 153 0.0 0.5 0.5 44.3 29.2 0.0 0 46
31 294 8 871 82 187 0.0 0.5 0.5 45.7 47.7 0.0 0 48
32 289 8 782 109 173 0.0 0.5 0.5 35.2 57.4 0.0 0 48
33 284 8 743 98 189 0.0 0.6 0.5 41.8 64.3 0.0 0 52
34 279 8 943 90 147 0.0 0.5 0.5 38.6 32.8 0.0 0 48
35 274 8 907 57 166 0.0 0.5 0.5 33.6 51.0 0.0 0 48
36 269 8 900 70 148 0.0 0.5 0.5 45.0 41.4 0.0 0 50
37 264 4 875 106 133 0.0 0.5 0.5 31.7 55.3 0.0 0 52
38 260 8 1023 145 149 0.0 0.6 0.5 28.7 65.0 0.0 0 52
39 255 8 801 151 173 0.0 0.9 0.5 41.7 41.2 0.0 0 48
40 251 8 741 104 159 0.0 0.8 0.5 36.2 47.5 0.0 0 48
41 246 8 828 108 149 0.0 0.5 0.5 34.6 50.9 0.0 0 50
42 242 8 947 128 132 0.0 0.7 0.5 34.2 39.0 0.0 0 50
43 238 8 917 101 142 0.0 0.8 0.5 34.4 50.9 0.0 0 48
44 234 8 761 86 129 0.0 0.5 0.5 42.0 36.4 0.0 0 52
45 229 8 979 106 137 0.0 0.5 0.5 29.2 55.3 0.0 0 50
46 225 8 806 74 130 0.0 0.7 0.5 33.1 65.4 0.0 0 52
47 221 8 971 125 114 0.0 0.5 0.5 31.9 45.6 0.0 0 52
48 218 8 869 125 104 0.0 0.9 0.5 30.0 56.0 0.0 0 48
49 214 8 999 153 140 0.0 0.8 0.5 30.4 46.4 0.0 0 52
50 210 8 798 192 139 0.0 1.0 0.5 28.9 50.0 0.0 0 52
51 206 8 860 125 157 0.0 1.2 0.5 31.5 26.9 0.0 0 52
52 203 8 893 186 127 5.9 0.9 0.5 26.4 42.3 0.0 0 46
53 199 8 863 126 141 0.0 1.2 0.5 32.5 44.4 0.0 0 44
54 196 8 788 97 133 0.0 0.9 0.5 37.5 40.0 0.0 0 50
55 192 8 926 119 116 0.0 0.6 0.5 26.1 55.3 0.0 0 52
56 189 8 789 162 107 0.0 0.8 0.5 25.2 40.4 0.0 0 48
57 186 8 878 107 128 0.0 1.1 0.5 23.1 34.0 0.0 0 52
58 182 8 775 105 122 0.0 0.8 0.5 25.5 57.4 0.0 0 50
59 179 8 747 94 129 0.0 0.7 0.5 34.3 37.3 0.0 0 50
60 176 8 845 96 138 0.0 0.6 0.5 28.3 41.7 0.0 0 52
61 173 8 961 121 110 0.0 0.6 0.5 29.0 52.6 0.0 0 48
62 170 4 911 110 109 0.0 0.9 0.5 33.5 33.3 0.0 0 48
63 167 8 656 109 109 0.0 0.8 0.5 21.9 44.7 0.0 0 52
64 164 8 934 117 105 0.0 0.8 0.5 15.5 50.0 0.0 0 52
65 161 8 972 125 95 0.0 0.8 0.5 24.4 50.0 0.0 0 50
66 158 8 894 125 101 0.0 0.9 0.5 27.2 35.9 0.0 0 52
67 155 8 798 146 129 0.0 1.0 0.5 22.8 58.7 0.0 0 52
68 153 8 901 183 92 0.0 1.1 0.5 23.6 34.5 0.0 0 52
69 150 8 977 197 103 0.0 1.4 0.5 23.6 36.8 0.0 0 52
70 147 8 905 262 93 0.0 1.5 0.5 20.3 63.4 0.0 0 52
71 145 8 995 148 122 0.0 1.9 0.5 20.9 35.3 0.0 0 52
72 142 8 934 230 99 0.0 1.6 0.5 20.0 65.9 0.0 0 52
73 140 8 862 173 100 0.0 1.8 0.5 26.8 46.8 0.0 0 52
74 137 8 924 139 90 0.0 1.7 0.5 16.8 42.5 0.0 0 52
75 135 8 888 168 113 0.0 1.6 0.5 22.9 40.4 0.0 0 52
76 133 8 712 212 84 0.0 1.6 0.5 13.4 46.9 0.0 0 52
77 130 8 868 210 91 0.0 1.7 0.5 17.7 51.2 0.0 0 52
78 128 8 952 307 92 0.0 1.9 0.5 19.7 44.9 0.0 0 50
79 126 8 801 157 107 0.0 2.2 0.5 15.8 39.0 0.0 0 52
80 123 8 849 147 93 0.0 2.1 0.5 15.6 51.4 0.0 0 52
81 121 8 799 154 86 0.0 1.9 0.5 12.2 50.0 0.0 0 52
82 119 8 941 213 82 0.0 1.8 0.5 19.5 41.2 0.0 0 50
83 117 8 751 268 94 0.0 2.0 0.5 20.8 42.6 0.0 0 50
84 115 8 828 198 102 0.0 2.2 0.5 15.5 59.5 0.0 0 52
85 113 8 898 266 123 0.0 2.2 0.5 13.2 85.2 0.0 0 52
86 111 8 943 190 93 0.0 2.4 0.5 19.5 45.1 0.0 0 52
87 109 8 864 183 65 0.0 2.4 0.5 14.9 31.8 0.0 0 52
88 107 8 793 203 93 0.0 2.4 0.5 11.8 35.3 0.0 0 52
89 105 8 752 162 74 1.2 2.4 0.5 13.1 21.4 0.0 0 52
90 103 8 801 149 77 0.0 2.3 0.5 9.7 58.3 0.0 0 52
91 102 8 901 230 99 0.0 2.2 0.5 16.0 25.5 0.0 0 52
92 100 8 826 201 87 0.0 2.4 0.5 12.8 45.7 0.0 0 52
93 98 8 810 196 83 0.0 2.5 0.5 14.0 24.4 0.0 0 52
94 96 8 857 209 68 1.0 2.5 0.5 11.5 27.0 5.1 0 52
95 95 8 771 174 91 0.0 2.6 0.5 10.5 26.5 0.0 0 52
96 93 8 955 210 59 0.0 2.6 0.5 10.0 36.7 0.7 0 52
97 91 8 833 206 53 0.0 2.7 0.5 10.2 19.4 1.4 0 52
98 90 8 888 229 86 0.0 2.8 0.5 8.1 36.0 0.0 0 52
99 88 8 794 186 91 1.0 2.9 0.5 8.3 25.0 0.5 0 52
100 81 8 756 170 72 1.0 2.9 0.5 6.0 23.8 7.0 0 52
101 74 8 791 176 67 0.0 2.9 0.5 4.4 58.3 4.0 0 52
102 67 8 813 213 43 0.0 3.0 0.5 7.0 150.0 4.2 0 52
103 62 8 779 245 39 0.0 3.1 0.5 3.2 16.7 13.0 0 52
104 56 8 767 303 63 0.0 3.2 0.5 4.1 20.0 0.7 0 52
105 52 8 757 270 57 0.0 3.5 0.5 6.4 3.7 0.5 0 52
106 47 8 763 283 41 0.0 3.7 0.5 4.5 0.0 0.0 0 52
107 43 8 768 283 36 0.0 3.7 0.5 2.9 18.2 3.6 0 52
108 39 8 804 283 25 0.0 3.7 0.5 3.1 0.0 6.2 0 52
109 36 8 781 283 24 0.0 3.7 0.5 3.6 6.7 6.7 0 52
110 33 8 738 298 42 0.0 3.7 0.5 3.3 15.4 3.5 0 52
111 30 8 761 298 36 0.0 3.7 0.5 2.2 0.0 4.3 0 52
112 27 8 769 298 37 0.0 3.7 0.5 0.9 0.0 2.2 0 52
113 25 8 745 298 31 0.0 3.7 0.5 1.5 0.0 6.6 0 52
114 23 8 753 298 16 0.0 3.7 0.5 1.3 0.0 2.8 0 52
115 21 8 745 298 11 0.0 3.7 0.5 1.5 0.0 14.0 0 52
116 19 8 747 298 21 0.0 3.7 0.5 2.1 0.0 5.8 0 52
117 13 8 737 298 12 0.0 3.7 0.5 1.0 0.0 10.0 0 52
118 9 8 736 298 4 0.0 3.7 0.5 1.5 0.0 18.5 0 52
119 0 8 739 298 0 0.0 3.7 0.5 1.8 0.0 18.0 0 52
120 0 8 732 298 0 0.0 3.7 0.5 1.2 0.0 21.8 0 52
121 0 8 732 19 -1 0.0 0.0 0.5 0.0 100.0 54.8
Initial Wiring Cost: 645 Final Wiring Cost: 732
############## Percent Wire Cost Reduction: -13
Initial Wire Length: 645 Final Wire Length: 732
************** Percent Wire Length Reduction: -13
Initial Horiz. Wire: 216 Final Horiz. Wire: 147
$$$$$$$$$$$ Percent H-Wire Length Reduction: 32
Initial Vert. Wire: 429 Final Vert. Wire: 585
@@@@@@@@@@@ Percent V-Wire Length Reduction: -36
Before Feeds are Added:
BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET
1 82 -20
2 86 -16
LONGEST Block is:2 Its length is:86
BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET
1 86 -16
2 86 -16
LONGEST Block is:1 Its length is:86
Added: 1 feed-through cells
Removed the cell overlaps --- Will do neighbor interchanges only now
TOTAL INTERCONNECT LENGTH: 994
OVERLAP PENALTY: 0
initialRowControl: 1.650
finalRowControl: 0.300
iter T Wire accept
122 0.001 976 16%
123 0.001 971 0%
124 0.001 971 0%
Total Feed-Alignment Movement (Pass 1): 0
Total Feed-Alignment Movement (Pass 2): 0
Total Feed-Alignment Movement (Pass 3): 0
Total Feed-Alignment Movement (Pass 4): 0
Total Feed-Alignment Movement (Pass 5): 0
Total Feed-Alignment Movement (Pass 6): 0
Total Feed-Alignment Movement (Pass 7): 0
Total Feed-Alignment Movement (Pass 8): 0
The rand generator seed was at globroute() : 987654321
Total Number of Net Segments: 9
Number of Switchable Net Segments: 0
Number of channels: 3
THIS IS THE ORIGINAL NUMBER OF TRACKS: 5
no. of accepted flips: 0
no. of attempted flips: 0
THIS IS THE NUMBER OF TRACKS: 5
FINAL NUMBER OF ROUTING TRACKS: 5
MAX OF CHANNEL: 1 is: 0
MAX OF CHANNEL: 2 is: 4
MAX OF CHANNEL: 3 is: 1
FINAL TOTAL INTERCONNECT LENGTH: 978
FINAL OVERLAP PENALTY: 0 FINAL VALUE OF TOTAL COST IS: 978
MAX NUMBER OF ATTEMPTED FLIPS PER T: 55
cost_scale_factor:3.90616
Number of Feed Thrus: 0
Number of Implicit Feed Thrus: 0
Statistics:
Number of Standard Cells: 10
Number of Pads: 0
Number of Nets: 15
Number of Pins: 46
Usage statistics not available

418
simulators/gem5/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt Normal file
View File

@ -0,0 +1,418 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.232077 # Number of seconds simulated
sim_ticks 232077154000 # Number of ticks simulated
final_tick 232077154000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 665536 # Simulator instruction rate (inst/s)
host_op_rate 728833 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 898821179 # Simulator tick rate (ticks/s)
host_mem_usage 233632 # Number of bytes of host memory used
host_seconds 258.20 # Real time elapsed on the host
sim_insts 171842491 # Number of instructions simulated
sim_ops 188185929 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 110656 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 110336 # Number of bytes read from this memory
system.physmem.bytes_read::total 220992 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 110656 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 110656 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 1729 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 1724 # Number of read requests responded to by this memory
system.physmem.num_reads::total 3453 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 476807 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 475428 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 952235 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 476807 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 476807 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 476807 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 475428 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 952235 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 400 # Number of system calls
system.cpu.numCycles 464154308 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 171842491 # Number of instructions committed
system.cpu.committedOps 188185929 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 150106226 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 1752310 # Number of float alu accesses
system.cpu.num_func_calls 3504894 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 32493891 # number of instructions that are conditional controls
system.cpu.num_int_insts 150106226 # number of integer instructions
system.cpu.num_fp_insts 1752310 # number of float instructions
system.cpu.num_int_register_reads 898652287 # number of times the integer registers were read
system.cpu.num_int_register_writes 294073530 # number of times the integer registers were written
system.cpu.num_fp_register_reads 2822225 # number of times the floating registers were read
system.cpu.num_fp_register_writes 2378039 # number of times the floating registers were written
system.cpu.num_mem_refs 42494120 # number of memory refs
system.cpu.num_load_insts 29849485 # Number of load instructions
system.cpu.num_store_insts 12644635 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 464154308 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.icache.replacements 1506 # number of replacements
system.cpu.icache.tagsinuse 1147.981155 # Cycle average of tags in use
system.cpu.icache.total_refs 189857010 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 3051 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 62227.797443 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 1147.981155 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.560538 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.560538 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 189857010 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 189857010 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 189857010 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 189857010 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 189857010 # number of overall hits
system.cpu.icache.overall_hits::total 189857010 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 3051 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 3051 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 3051 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 3051 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 3051 # number of overall misses
system.cpu.icache.overall_misses::total 3051 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 115332000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 115332000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 115332000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 115332000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 115332000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 115332000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 189860061 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 189860061 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 189860061 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 189860061 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 189860061 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 189860061 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000016 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000016 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000016 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000016 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000016 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000016 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 37801.376598 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 37801.376598 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 37801.376598 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 37801.376598 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 37801.376598 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 37801.376598 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 3051 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 3051 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 3051 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 3051 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 3051 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 3051 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 106179000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 106179000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 106179000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 106179000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 106179000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 106179000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000016 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000016 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000016 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34801.376598 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 34801.376598 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34801.376598 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 34801.376598 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34801.376598 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 34801.376598 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 40 # number of replacements
system.cpu.dcache.tagsinuse 1363.604315 # Cycle average of tags in use
system.cpu.dcache.total_refs 42007359 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 1789 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 23480.916154 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 1363.604315 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.332911 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.332911 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 29599358 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 29599358 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 12363187 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 12363187 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 22407 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 22407 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 41962545 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 41962545 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 41962545 # number of overall hits
system.cpu.dcache.overall_hits::total 41962545 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 689 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 689 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 1100 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 1100 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 1789 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 1789 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 1789 # number of overall misses
system.cpu.dcache.overall_misses::total 1789 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 36190000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 36190000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 61264000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 61264000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 97454000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 97454000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 97454000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 97454000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 29600047 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 29600047 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22407 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 41964334 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 41964334 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 41964334 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 41964334 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000023 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.000023 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000089 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.000089 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.000043 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.000043 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.000043 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.000043 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 52525.399129 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 52525.399129 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55694.545455 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 55694.545455 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 54474.007826 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 54474.007826 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 54474.007826 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 54474.007826 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 16 # number of writebacks
system.cpu.dcache.writebacks::total 16 # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 689 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 689 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1100 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 1100 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 1789 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 1789 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 1789 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 1789 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 34123000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 34123000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 57964000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 57964000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 92087000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 92087000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 92087000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 92087000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000023 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000023 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000089 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000089 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000043 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.000043 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000043 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.000043 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 49525.399129 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 49525.399129 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52694.545455 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52694.545455 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51474.007826 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 51474.007826 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51474.007826 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 51474.007826 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 1675.648030 # Cycle average of tags in use
system.cpu.l2cache.total_refs 1379 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 2369 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.582102 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 3.038048 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 1169.027734 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 503.582248 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.000093 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.035676 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.015368 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.051137 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 1322 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 57 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 1379 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 16 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 16 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 8 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 8 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst 1322 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 65 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 1387 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 1322 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 65 # number of overall hits
system.cpu.l2cache.overall_hits::total 1387 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 1729 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 632 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 2361 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 1092 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 1092 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 1729 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 1724 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 3453 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 1729 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 1724 # number of overall misses
system.cpu.l2cache.overall_misses::total 3453 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 89908000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 32864000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 122772000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 56784000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 56784000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 89908000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 89648000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 179556000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 89908000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 89648000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 179556000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 3051 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 689 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 3740 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 16 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 16 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1100 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 1100 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 3051 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 1789 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 4840 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 3051 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 1789 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 4840 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.566699 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.917271 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.631283 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.992727 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.992727 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.566699 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.963667 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.713430 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.566699 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.963667 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.713430 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1729 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 632 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 2361 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1092 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 1092 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 1729 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 1724 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 3453 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 1729 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 1724 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 3453 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 69160000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 25280000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 94440000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 43680000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 43680000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 69160000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 68960000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 138120000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 69160000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 68960000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 138120000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.566699 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.917271 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.631283 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992727 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992727 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.566699 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.963667 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.713430 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.566699 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.963667 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.713430 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

117
simulators/gem5/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/config.ini Normal file
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@ -0,0 +1,117 @@
[root]
type=Root
children=system
full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
boot_osflags=a
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
readfile=
symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.cpu]
type=AtomicSimpleCPU
children=dtb interrupts itb tracer workload
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
fastmem=false
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
phase=0
profile=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
system=system
tracer=system.cpu.tracer
width=1
workload=system.cpu.workload
dcache_port=system.membus.slave[2]
icache_port=system.membus.slave[1]
[system.cpu.dtb]
type=SparcTLB
size=64
[system.cpu.interrupts]
type=SparcInterrupts
[system.cpu.itb]
type=SparcTLB
size=64
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=twolf smred
cwd=build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-atomic
egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/cpu2000/binaries/sparc/linux/twolf
gid=100
input=cin
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=0
system=system
uid=100
[system.membus]
type=CoherentBus
block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
master=system.physmem.port[0]
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
[system.physmem]
type=SimpleMemory
conf_table_reported=false
file=
in_addr_map=true
latency=30000
latency_var=0
null=false
range=0:134217727
zero=false
port=system.membus.master[0]

3
simulators/gem5/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/simerr Executable file
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@ -0,0 +1,3 @@
warn: CoherentBus system.membus has no snooping ports attached!
warn: Sockets disabled, not accepting gdb connections
hack: be nice to actually delete the event here

26
simulators/gem5/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/simout Executable file
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@ -0,0 +1,26 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 4 2012 12:01:47
gem5 started Jun 4 2012 15:01:23
gem5 executing on zizzer
command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-atomic
Couldn't unlink build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-atomic/smred.sav
Couldn't unlink build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-atomic/smred.sv2
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
Standard Cell Placement and Global Routing Program
Authors: Carl Sechen, Bill Swartz
Yale University
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
61 62 63 64 65 66 67 68 69 70 71 72 73 74 75
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
info: Increasing stack size by one page.
122 123 124 Exiting @ tick 96722951500 because target called exit()

276
simulators/gem5/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/smred.out Normal file
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@ -0,0 +1,276 @@
TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
Standard Cell Placement and Global Routing Program
Authors: Carl Sechen, Bill Swartz
Yale University
NOTE: Restart file .rs2 not used
TimberWolf will perform a global route step
rowSep: 1.000000
feedThruWidth: 4
******************
BLOCK DATA
block:1 desire:85
block:2 desire:85
Total Desired Length: 170
total cell length: 168
total block length: 168
block x-span:84 block y-span:78
implicit feed thru range: -84
Using default value of bin.penalty.control:1.000000
numBins automatically set to:5
binWidth = average_cell_width + 0 sigma= 17
average_cell_width is:16
standard deviation of cell length is:23.6305
TimberWolfSC starting from the beginning
THIS IS THE ROUTE COST OF THE ORIGINAL PLACEMENT: 645
The number of nets with 1 pin is 4
The number of nets with 2 pin is 9
The number of nets with 3 pin is 0
The number of nets with 4 pin is 2
The number of nets with 5 pin is 0
The number of nets with 6 pin is 0
The number of nets with 7 pin is 0
The number of nets with 8 pin is 0
The number of nets with 9 pin is 0
The number of nets with 10 pin or more is 0
New Cost Function: Initial Horizontal Cost:242
New Cost Function: FEEDS:0 MISSING_ROWS:-46
bdxlen:86 bdylen:78
l:0 t:78 r:86 b:0
THIS IS THE ROUTE COST OF THE CURRENT PLACEMENT: 645
THIS IS THE PENALTY OF THE CURRENT PLACEMENT: 44
The rand generator seed was at utemp() : 1
tempfile[0][0] = 0.982500 tempfile[0][1] = 90.000000
tempfile[1][0] = 0.915000 tempfile[1][1] = 20.000000
tempfile[2][0] = 0.700000 tempfile[2][1] = 10.000000
tempfile[3][0] = 0.100000 tempfile[3][1] = 0.000000
I T fds Wire Penalty P_lim Epct binC rowC acc s/p early FDs MRs
1 500 0 929 592 160 30.0 1.0 3.0 84.2 34.7 0.0 0 40
2 491 0 876 106 726 0.0 0.8 2.5 80.0 18.5 0.0 0 46
3 482 0 822 273 372 0.0 0.5 1.5 80.8 21.2 0.0 0 46
4 474 0 826 53 247 0.0 0.5 0.9 65.0 21.9 0.0 0 48
5 465 8 987 73 190 0.0 0.5 0.5 50.0 38.3 0.0 0 46
6 457 8 851 67 226 0.0 0.5 0.5 53.8 42.9 0.0 0 52
7 449 8 1067 108 190 0.0 0.5 0.5 46.2 53.8 0.0 0 50
8 441 8 918 106 171 0.0 0.5 0.5 47.1 40.4 0.0 0 48
9 434 8 812 101 197 0.0 0.5 0.5 53.6 21.0 0.0 0 48
10 426 8 1038 121 181 0.0 0.5 0.5 43.6 27.1 0.0 0 48
11 419 8 898 93 187 0.0 0.5 0.5 45.3 47.8 0.0 0 50
12 411 4 857 94 240 0.0 0.5 0.5 62.7 51.6 0.0 0 44
13 404 8 1043 88 185 0.0 0.5 0.5 54.0 52.8 0.0 0 50
14 397 8 767 94 154 0.0 0.5 0.5 33.8 35.0 0.0 0 50
15 390 8 862 89 183 0.0 0.5 0.5 55.6 29.0 0.0 0 46
16 383 4 798 79 173 0.0 0.5 0.5 57.5 35.3 0.0 0 52
17 376 8 827 100 152 0.0 0.5 0.5 35.3 81.8 0.0 0 50
18 370 8 878 101 208 0.0 0.5 0.5 44.7 46.2 0.0 0 48
19 363 4 921 67 167 0.0 0.5 0.5 57.1 34.7 0.0 0 48
20 357 8 933 93 154 0.0 0.5 0.5 46.5 43.6 0.0 0 52
21 351 8 930 89 147 0.0 0.5 0.5 39.4 36.5 0.0 0 52
22 345 8 951 79 142 0.0 0.5 0.5 32.8 51.3 0.0 0 50
23 339 8 1046 87 207 0.0 0.5 0.5 52.8 61.0 0.0 0 48
24 333 4 989 96 185 0.0 0.5 0.5 45.3 43.3 0.0 0 42
25 327 4 577 86 157 0.0 0.5 0.5 31.1 55.3 0.0 0 52
26 321 8 776 97 174 0.0 0.5 0.5 47.9 62.5 0.0 0 52
27 315 8 850 81 188 0.0 0.5 0.5 45.0 55.2 0.0 0 50
28 310 8 898 97 148 0.0 0.5 0.5 43.0 45.8 0.0 0 48
29 304 8 889 65 173 0.0 0.5 0.5 32.5 41.3 0.0 0 50
30 299 8 858 81 153 0.0 0.5 0.5 44.3 29.2 0.0 0 46
31 294 8 871 82 187 0.0 0.5 0.5 45.7 47.7 0.0 0 48
32 289 8 782 109 173 0.0 0.5 0.5 35.2 57.4 0.0 0 48
33 284 8 743 98 189 0.0 0.6 0.5 41.8 64.3 0.0 0 52
34 279 8 943 90 147 0.0 0.5 0.5 38.6 32.8 0.0 0 48
35 274 8 907 57 166 0.0 0.5 0.5 33.6 51.0 0.0 0 48
36 269 8 900 70 148 0.0 0.5 0.5 45.0 41.4 0.0 0 50
37 264 4 875 106 133 0.0 0.5 0.5 31.7 55.3 0.0 0 52
38 260 8 1023 145 149 0.0 0.6 0.5 28.7 65.0 0.0 0 52
39 255 8 801 151 173 0.0 0.9 0.5 41.7 41.2 0.0 0 48
40 251 8 741 104 159 0.0 0.8 0.5 36.2 47.5 0.0 0 48
41 246 8 828 108 149 0.0 0.5 0.5 34.6 50.9 0.0 0 50
42 242 8 947 128 132 0.0 0.7 0.5 34.2 39.0 0.0 0 50
43 238 8 917 101 142 0.0 0.8 0.5 34.4 50.9 0.0 0 48
44 234 8 761 86 129 0.0 0.5 0.5 42.0 36.4 0.0 0 52
45 229 8 979 106 137 0.0 0.5 0.5 29.2 55.3 0.0 0 50
46 225 8 806 74 130 0.0 0.7 0.5 33.1 65.4 0.0 0 52
47 221 8 971 125 114 0.0 0.5 0.5 31.9 45.6 0.0 0 52
48 218 8 869 125 104 0.0 0.9 0.5 30.0 56.0 0.0 0 48
49 214 8 999 153 140 0.0 0.8 0.5 30.4 46.4 0.0 0 52
50 210 8 798 192 139 0.0 1.0 0.5 28.9 50.0 0.0 0 52
51 206 8 860 125 157 0.0 1.2 0.5 31.5 26.9 0.0 0 52
52 203 8 893 186 127 5.9 0.9 0.5 26.4 42.3 0.0 0 46
53 199 8 863 126 141 0.0 1.2 0.5 32.5 44.4 0.0 0 44
54 196 8 788 97 133 0.0 0.9 0.5 37.5 40.0 0.0 0 50
55 192 8 926 119 116 0.0 0.6 0.5 26.1 55.3 0.0 0 52
56 189 8 789 162 107 0.0 0.8 0.5 25.2 40.4 0.0 0 48
57 186 8 878 107 128 0.0 1.1 0.5 23.1 34.0 0.0 0 52
58 182 8 775 105 122 0.0 0.8 0.5 25.5 57.4 0.0 0 50
59 179 8 747 94 129 0.0 0.7 0.5 34.3 37.3 0.0 0 50
60 176 8 845 96 138 0.0 0.6 0.5 28.3 41.7 0.0 0 52
61 173 8 961 121 110 0.0 0.6 0.5 29.0 52.6 0.0 0 48
62 170 4 911 110 109 0.0 0.9 0.5 33.5 33.3 0.0 0 48
63 167 8 656 109 109 0.0 0.8 0.5 21.9 44.7 0.0 0 52
64 164 8 934 117 105 0.0 0.8 0.5 15.5 50.0 0.0 0 52
65 161 8 972 125 95 0.0 0.8 0.5 24.4 50.0 0.0 0 50
66 158 8 894 125 101 0.0 0.9 0.5 27.2 35.9 0.0 0 52
67 155 8 798 146 129 0.0 1.0 0.5 22.8 58.7 0.0 0 52
68 153 8 901 183 92 0.0 1.1 0.5 23.6 34.5 0.0 0 52
69 150 8 977 197 103 0.0 1.4 0.5 23.6 36.8 0.0 0 52
70 147 8 905 262 93 0.0 1.5 0.5 20.3 63.4 0.0 0 52
71 145 8 995 148 122 0.0 1.9 0.5 20.9 35.3 0.0 0 52
72 142 8 934 230 99 0.0 1.6 0.5 20.0 65.9 0.0 0 52
73 140 8 862 173 100 0.0 1.8 0.5 26.8 46.8 0.0 0 52
74 137 8 924 139 90 0.0 1.7 0.5 16.8 42.5 0.0 0 52
75 135 8 888 168 113 0.0 1.6 0.5 22.9 40.4 0.0 0 52
76 133 8 712 212 84 0.0 1.6 0.5 13.4 46.9 0.0 0 52
77 130 8 868 210 91 0.0 1.7 0.5 17.7 51.2 0.0 0 52
78 128 8 952 307 92 0.0 1.9 0.5 19.7 44.9 0.0 0 50
79 126 8 801 157 107 0.0 2.2 0.5 15.8 39.0 0.0 0 52
80 123 8 849 147 93 0.0 2.1 0.5 15.6 51.4 0.0 0 52
81 121 8 799 154 86 0.0 1.9 0.5 12.2 50.0 0.0 0 52
82 119 8 941 213 82 0.0 1.8 0.5 19.5 41.2 0.0 0 50
83 117 8 751 268 94 0.0 2.0 0.5 20.8 42.6 0.0 0 50
84 115 8 828 198 102 0.0 2.2 0.5 15.5 59.5 0.0 0 52
85 113 8 898 266 123 0.0 2.2 0.5 13.2 85.2 0.0 0 52
86 111 8 943 190 93 0.0 2.4 0.5 19.5 45.1 0.0 0 52
87 109 8 864 183 65 0.0 2.4 0.5 14.9 31.8 0.0 0 52
88 107 8 793 203 93 0.0 2.4 0.5 11.8 35.3 0.0 0 52
89 105 8 752 162 74 1.2 2.4 0.5 13.1 21.4 0.0 0 52
90 103 8 801 149 77 0.0 2.3 0.5 9.7 58.3 0.0 0 52
91 102 8 901 230 99 0.0 2.2 0.5 16.0 25.5 0.0 0 52
92 100 8 826 201 87 0.0 2.4 0.5 12.8 45.7 0.0 0 52
93 98 8 810 196 83 0.0 2.5 0.5 14.0 24.4 0.0 0 52
94 96 8 857 209 68 1.0 2.5 0.5 11.5 27.0 5.1 0 52
95 95 8 771 174 91 0.0 2.6 0.5 10.5 26.5 0.0 0 52
96 93 8 955 210 59 0.0 2.6 0.5 10.0 36.7 0.7 0 52
97 91 8 833 206 53 0.0 2.7 0.5 10.2 19.4 1.4 0 52
98 90 8 888 229 86 0.0 2.8 0.5 8.1 36.0 0.0 0 52
99 88 8 794 186 91 1.0 2.9 0.5 8.3 25.0 0.5 0 52
100 81 8 756 170 72 1.0 2.9 0.5 6.0 23.8 7.0 0 52
101 74 8 791 176 67 0.0 2.9 0.5 4.4 58.3 4.0 0 52
102 67 8 813 213 43 0.0 3.0 0.5 7.0 150.0 4.2 0 52
103 62 8 779 245 39 0.0 3.1 0.5 3.2 16.7 13.0 0 52
104 56 8 767 303 63 0.0 3.2 0.5 4.1 20.0 0.7 0 52
105 52 8 757 270 57 0.0 3.5 0.5 6.4 3.7 0.5 0 52
106 47 8 763 283 41 0.0 3.7 0.5 4.5 0.0 0.0 0 52
107 43 8 768 283 36 0.0 3.7 0.5 2.9 18.2 3.6 0 52
108 39 8 804 283 25 0.0 3.7 0.5 3.1 0.0 6.2 0 52
109 36 8 781 283 24 0.0 3.7 0.5 3.6 6.7 6.7 0 52
110 33 8 738 298 42 0.0 3.7 0.5 3.3 15.4 3.5 0 52
111 30 8 761 298 36 0.0 3.7 0.5 2.2 0.0 4.3 0 52
112 27 8 769 298 37 0.0 3.7 0.5 0.9 0.0 2.2 0 52
113 25 8 745 298 31 0.0 3.7 0.5 1.5 0.0 6.6 0 52
114 23 8 753 298 16 0.0 3.7 0.5 1.3 0.0 2.8 0 52
115 21 8 745 298 11 0.0 3.7 0.5 1.5 0.0 14.0 0 52
116 19 8 747 298 21 0.0 3.7 0.5 2.1 0.0 5.8 0 52
117 13 8 737 298 12 0.0 3.7 0.5 1.0 0.0 10.0 0 52
118 9 8 736 298 4 0.0 3.7 0.5 1.5 0.0 18.5 0 52
119 0 8 739 298 0 0.0 3.7 0.5 1.8 0.0 18.0 0 52
120 0 8 732 298 0 0.0 3.7 0.5 1.2 0.0 21.8 0 52
121 0 8 732 19 -1 0.0 0.0 0.5 0.0 100.0 54.8
Initial Wiring Cost: 645 Final Wiring Cost: 732
############## Percent Wire Cost Reduction: -13
Initial Wire Length: 645 Final Wire Length: 732
************** Percent Wire Length Reduction: -13
Initial Horiz. Wire: 216 Final Horiz. Wire: 147
$$$$$$$$$$$ Percent H-Wire Length Reduction: 32
Initial Vert. Wire: 429 Final Vert. Wire: 585
@@@@@@@@@@@ Percent V-Wire Length Reduction: -36
Before Feeds are Added:
BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET
1 82 -20
2 86 -16
LONGEST Block is:2 Its length is:86
BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET
1 86 -16
2 86 -16
LONGEST Block is:1 Its length is:86
Added: 1 feed-through cells
Removed the cell overlaps --- Will do neighbor interchanges only now
TOTAL INTERCONNECT LENGTH: 994
OVERLAP PENALTY: 0
initialRowControl: 1.650
finalRowControl: 0.300
iter T Wire accept
122 0.001 976 16%
123 0.001 971 0%
124 0.001 971 0%
Total Feed-Alignment Movement (Pass 1): 0
Total Feed-Alignment Movement (Pass 2): 0
Total Feed-Alignment Movement (Pass 3): 0
Total Feed-Alignment Movement (Pass 4): 0
Total Feed-Alignment Movement (Pass 5): 0
Total Feed-Alignment Movement (Pass 6): 0
Total Feed-Alignment Movement (Pass 7): 0
Total Feed-Alignment Movement (Pass 8): 0
The rand generator seed was at globroute() : 987654321
Total Number of Net Segments: 9
Number of Switchable Net Segments: 0
Number of channels: 3
THIS IS THE ORIGINAL NUMBER OF TRACKS: 5
no. of accepted flips: 0
no. of attempted flips: 0
THIS IS THE NUMBER OF TRACKS: 5
FINAL NUMBER OF ROUTING TRACKS: 5
MAX OF CHANNEL: 1 is: 0
MAX OF CHANNEL: 2 is: 4
MAX OF CHANNEL: 3 is: 1
FINAL TOTAL INTERCONNECT LENGTH: 978
FINAL OVERLAP PENALTY: 0 FINAL VALUE OF TOTAL COST IS: 978
MAX NUMBER OF ATTEMPTED FLIPS PER T: 55
cost_scale_factor:3.90616
Number of Feed Thrus: 0
Number of Implicit Feed Thrus: 0
Statistics:
Number of Standard Cells: 10
Number of Pads: 0
Number of Nets: 15
Number of Pins: 46
Usage statistics not available

17
simulators/gem5/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/smred.pin Normal file
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@ -0,0 +1,17 @@
$COUNT_1/$AND2_1/$ND2_1$Z 1 $COUNT_1/$AND2_1/$ND2_1 00#Z 17 52 2 1 0
$COUNT_1/$AND2_1/$ND2_1$Z 1 ACOUNT_1 00#A 15 26 2 -1 0
B7 2 $COUNT_1/$FJK3_2 00#K 25 78 3 -1 0
B7 2 $COUNT_1/$FJK3_2 00#J 23 78 3 -1 0
B7 3 $COUNT_1/$AND2_2/$ND2_1 00#A 9 26 2 -1 0
B7 3 ACOUNT_1 01#Z 17 26 2 -1 0
B6 5 $COUNT_1/$FJK3_1 00#K 25 26 2 -1 0
B6 5 $COUNT_1/$FJK3_1 00#J 23 26 2 -1 0
B6 5 $COUNT_1/$AND2_3/$IV_1 01#Z 7 26 2 -1 0
$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$FJK3_1 01#Q 81 26 2 -1 0
$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$AND2_1/$ND2_1 00#B 19 52 2 1 0
$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$FJK3_2 00#Q 81 52 2 1 0
$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$AND2_2/$ND2_1 01#B 11 26 2 -1 0
$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$ND2_1 00#Z 5 52 2 1 0
$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$IV_1 00#A 5 26 2 -1 0
$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$ND2_1 00#Z 7 52 2 1 0
$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$IV_1 00#A 3 26 2 -1 0

11
simulators/gem5/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/smred.pl1 Normal file
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@ -0,0 +1,11 @@
$COUNT_1/$AND2_4/$IV_1 0 0 4 26 0 1
$COUNT_1/$AND2_3/$IV_1 4 0 8 26 2 1
$COUNT_1/$AND2_2/$ND2_1 8 0 14 26 0 1
ACOUNT_1 14 0 18 26 2 1
twfeed1 18 0 22 26 0 1
$COUNT_1/$FJK3_1 22 0 86 26 0 1
$COUNT_1/$AND2_3/$ND2_1 0 52 6 78 0 2
$COUNT_1/$AND2_4/$ND2_1 6 52 12 78 2 2
$COUNT_1/$AND2_2/$IV_1 12 52 16 78 2 2
$COUNT_1/$AND2_1/$ND2_1 16 52 22 78 2 2
$COUNT_1/$FJK3_2 22 52 86 78 0 2

2
simulators/gem5/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/smred.pl2 Normal file
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@ -0,0 +1,2 @@
1 0 0 86 26 0 0
2 0 52 86 78 0 0

18
simulators/gem5/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/smred.sav Normal file
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@ -0,0 +1,18 @@
0.009592
121
0
1
0.000000
0.500000
3.906156
1
1 1 2 37 13
2 2 0 34 65
3 2 2 63 65
4 1 0 59 13
5 1 2 32 13
6 2 0 23 65
7 1 2 12 13
8 2 0 6 65
9 1 0 70 13
10 2 0 70 65

19
simulators/gem5/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/smred.sv2 Normal file
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@ -0,0 +1,19 @@
0.001000
123
0
2
0.000000
0.500000
3.906156
1
1 1 2 16 13
2 2 2 19 65
3 2 2 14 65
4 1 0 11 13
5 1 2 6 13
6 2 0 3 65
7 1 0 2 13
8 2 2 9 65
9 1 0 50 13
10 2 0 54 65
11 1 0 84 13

29
simulators/gem5/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/smred.twf Normal file
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@ -0,0 +1,29 @@
net 1
segment channel 2
pin1 1 pin2 7 0 0
net 2
segment channel 3
pin1 41 pin2 42 0 0
segment channel 2
pin1 12 pin2 3 0 0
net 3
segment channel 2
pin1 35 pin2 36 0 0
segment channel 2
pin1 19 pin2 35 0 0
net 4
segment channel 2
pin1 5 pin2 38 0 0
net 5
net 7
segment channel 2
pin1 14 pin2 43 0 0
net 8
segment channel 2
pin1 23 pin2 17 0 0
net 9
net 11
segment channel 2
pin1 25 pin2 31 0 0
net 14
net 15

62
simulators/gem5/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt Normal file
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@ -0,0 +1,62 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.096723 # Number of seconds simulated
sim_ticks 96722951500 # Number of ticks simulated
final_tick 96722951500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 2785942 # Simulator instruction rate (inst/s)
host_op_rate 2785945 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1392980356 # Simulator tick rate (ticks/s)
host_mem_usage 218424 # Number of bytes of host memory used
host_seconds 69.44 # Real time elapsed on the host
sim_insts 193444531 # Number of instructions simulated
sim_ops 193444769 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 773782192 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 223463414 # Number of bytes read from this memory
system.physmem.bytes_read::total 997245606 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 773782192 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 773782192 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 72065412 # Number of bytes written to this memory
system.physmem.bytes_written::total 72065412 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 193445548 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 57735069 # Number of read requests responded to by this memory
system.physmem.num_reads::total 251180617 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 18976439 # Number of write requests responded to by this memory
system.physmem.num_writes::total 18976439 # Number of write requests responded to by this memory
system.physmem.num_other::cpu.data 22406 # Number of other requests responded to by this memory
system.physmem.num_other::total 22406 # Number of other requests responded to by this memory
system.physmem.bw_read::cpu.inst 7999985319 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 2310345275 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 10310330594 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 7999985319 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 7999985319 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 745070440 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 745070440 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 7999985319 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 3055415715 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 11055401034 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 401 # Number of system calls
system.cpu.numCycles 193445904 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 193444531 # Number of instructions committed
system.cpu.committedOps 193444769 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 167974818 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 1970372 # Number of float alu accesses
system.cpu.num_func_calls 1957920 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 8665107 # number of instructions that are conditional controls
system.cpu.num_int_insts 167974818 # number of integer instructions
system.cpu.num_fp_insts 1970372 # number of float instructions
system.cpu.num_int_register_reads 352617963 # number of times the integer registers were read
system.cpu.num_int_register_writes 163060137 # number of times the integer registers were written
system.cpu.num_fp_register_reads 3181089 # number of times the floating registers were read
system.cpu.num_fp_register_writes 2974850 # number of times the floating registers were written
system.cpu.num_mem_refs 76733959 # number of memory refs
system.cpu.num_load_insts 57735092 # Number of load instructions
system.cpu.num_store_insts 18998867 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 193445904 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
---------- End Simulation Statistics ----------

198
simulators/gem5/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/config.ini Normal file
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[root]
type=Root
children=system
full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
boot_osflags=a
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
readfile=
symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.cpu]
type=TimingSimpleCPU
children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
phase=0
profile=0
progress_interval=0
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=262144
subblock_size=0
system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
[system.cpu.dtb]
type=SparcTLB
size=64
[system.cpu.icache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=131072
subblock_size=0
system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.interrupts]
type=SparcInterrupts
[system.cpu.itb]
type=SparcTLB
size=64
[system.cpu.l2cache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=false
latency=10000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=2097152
subblock_size=0
system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
[system.cpu.toL2Bus]
type=CoherentBus
block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=twolf smred
cwd=build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-timing
egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/cpu2000/binaries/sparc/linux/twolf
gid=100
input=cin
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=0
system=system
uid=100
[system.membus]
type=CoherentBus
block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
master=system.physmem.port[0]
slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=SimpleMemory
conf_table_reported=false
file=
in_addr_map=true
latency=30000
latency_var=0
null=false
range=0:134217727
zero=false
port=system.membus.master[0]

2
simulators/gem5/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/simerr Executable file
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@ -0,0 +1,2 @@
warn: Sockets disabled, not accepting gdb connections
hack: be nice to actually delete the event here

26
simulators/gem5/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/simout Executable file
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@ -0,0 +1,26 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 4 2012 12:01:47
gem5 started Jun 4 2012 15:02:43
gem5 executing on zizzer
command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-timing
Couldn't unlink build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-timing/smred.sav
Couldn't unlink build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-timing/smred.sv2
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
Standard Cell Placement and Global Routing Program
Authors: Carl Sechen, Bill Swartz
Yale University
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
61 62 63 64 65 66 67 68 69 70 71 72 73 74 75
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
info: Increasing stack size by one page.
122 123 124 Exiting @ tick 270576960000 because target called exit()

276
simulators/gem5/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/smred.out Normal file
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@ -0,0 +1,276 @@
TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
Standard Cell Placement and Global Routing Program
Authors: Carl Sechen, Bill Swartz
Yale University
NOTE: Restart file .rs2 not used
TimberWolf will perform a global route step
rowSep: 1.000000
feedThruWidth: 4
******************
BLOCK DATA
block:1 desire:85
block:2 desire:85
Total Desired Length: 170
total cell length: 168
total block length: 168
block x-span:84 block y-span:78
implicit feed thru range: -84
Using default value of bin.penalty.control:1.000000
numBins automatically set to:5
binWidth = average_cell_width + 0 sigma= 17
average_cell_width is:16
standard deviation of cell length is:23.6305
TimberWolfSC starting from the beginning
THIS IS THE ROUTE COST OF THE ORIGINAL PLACEMENT: 645
The number of nets with 1 pin is 4
The number of nets with 2 pin is 9
The number of nets with 3 pin is 0
The number of nets with 4 pin is 2
The number of nets with 5 pin is 0
The number of nets with 6 pin is 0
The number of nets with 7 pin is 0
The number of nets with 8 pin is 0
The number of nets with 9 pin is 0
The number of nets with 10 pin or more is 0
New Cost Function: Initial Horizontal Cost:242
New Cost Function: FEEDS:0 MISSING_ROWS:-46
bdxlen:86 bdylen:78
l:0 t:78 r:86 b:0
THIS IS THE ROUTE COST OF THE CURRENT PLACEMENT: 645
THIS IS THE PENALTY OF THE CURRENT PLACEMENT: 44
The rand generator seed was at utemp() : 1
tempfile[0][0] = 0.982500 tempfile[0][1] = 90.000000
tempfile[1][0] = 0.915000 tempfile[1][1] = 20.000000
tempfile[2][0] = 0.700000 tempfile[2][1] = 10.000000
tempfile[3][0] = 0.100000 tempfile[3][1] = 0.000000
I T fds Wire Penalty P_lim Epct binC rowC acc s/p early FDs MRs
1 500 0 929 592 160 30.0 1.0 3.0 84.2 34.7 0.0 0 40
2 491 0 876 106 726 0.0 0.8 2.5 80.0 18.5 0.0 0 46
3 482 0 822 273 372 0.0 0.5 1.5 80.8 21.2 0.0 0 46
4 474 0 826 53 247 0.0 0.5 0.9 65.0 21.9 0.0 0 48
5 465 8 987 73 190 0.0 0.5 0.5 50.0 38.3 0.0 0 46
6 457 8 851 67 226 0.0 0.5 0.5 53.8 42.9 0.0 0 52
7 449 8 1067 108 190 0.0 0.5 0.5 46.2 53.8 0.0 0 50
8 441 8 918 106 171 0.0 0.5 0.5 47.1 40.4 0.0 0 48
9 434 8 812 101 197 0.0 0.5 0.5 53.6 21.0 0.0 0 48
10 426 8 1038 121 181 0.0 0.5 0.5 43.6 27.1 0.0 0 48
11 419 8 898 93 187 0.0 0.5 0.5 45.3 47.8 0.0 0 50
12 411 4 857 94 240 0.0 0.5 0.5 62.7 51.6 0.0 0 44
13 404 8 1043 88 185 0.0 0.5 0.5 54.0 52.8 0.0 0 50
14 397 8 767 94 154 0.0 0.5 0.5 33.8 35.0 0.0 0 50
15 390 8 862 89 183 0.0 0.5 0.5 55.6 29.0 0.0 0 46
16 383 4 798 79 173 0.0 0.5 0.5 57.5 35.3 0.0 0 52
17 376 8 827 100 152 0.0 0.5 0.5 35.3 81.8 0.0 0 50
18 370 8 878 101 208 0.0 0.5 0.5 44.7 46.2 0.0 0 48
19 363 4 921 67 167 0.0 0.5 0.5 57.1 34.7 0.0 0 48
20 357 8 933 93 154 0.0 0.5 0.5 46.5 43.6 0.0 0 52
21 351 8 930 89 147 0.0 0.5 0.5 39.4 36.5 0.0 0 52
22 345 8 951 79 142 0.0 0.5 0.5 32.8 51.3 0.0 0 50
23 339 8 1046 87 207 0.0 0.5 0.5 52.8 61.0 0.0 0 48
24 333 4 989 96 185 0.0 0.5 0.5 45.3 43.3 0.0 0 42
25 327 4 577 86 157 0.0 0.5 0.5 31.1 55.3 0.0 0 52
26 321 8 776 97 174 0.0 0.5 0.5 47.9 62.5 0.0 0 52
27 315 8 850 81 188 0.0 0.5 0.5 45.0 55.2 0.0 0 50
28 310 8 898 97 148 0.0 0.5 0.5 43.0 45.8 0.0 0 48
29 304 8 889 65 173 0.0 0.5 0.5 32.5 41.3 0.0 0 50
30 299 8 858 81 153 0.0 0.5 0.5 44.3 29.2 0.0 0 46
31 294 8 871 82 187 0.0 0.5 0.5 45.7 47.7 0.0 0 48
32 289 8 782 109 173 0.0 0.5 0.5 35.2 57.4 0.0 0 48
33 284 8 743 98 189 0.0 0.6 0.5 41.8 64.3 0.0 0 52
34 279 8 943 90 147 0.0 0.5 0.5 38.6 32.8 0.0 0 48
35 274 8 907 57 166 0.0 0.5 0.5 33.6 51.0 0.0 0 48
36 269 8 900 70 148 0.0 0.5 0.5 45.0 41.4 0.0 0 50
37 264 4 875 106 133 0.0 0.5 0.5 31.7 55.3 0.0 0 52
38 260 8 1023 145 149 0.0 0.6 0.5 28.7 65.0 0.0 0 52
39 255 8 801 151 173 0.0 0.9 0.5 41.7 41.2 0.0 0 48
40 251 8 741 104 159 0.0 0.8 0.5 36.2 47.5 0.0 0 48
41 246 8 828 108 149 0.0 0.5 0.5 34.6 50.9 0.0 0 50
42 242 8 947 128 132 0.0 0.7 0.5 34.2 39.0 0.0 0 50
43 238 8 917 101 142 0.0 0.8 0.5 34.4 50.9 0.0 0 48
44 234 8 761 86 129 0.0 0.5 0.5 42.0 36.4 0.0 0 52
45 229 8 979 106 137 0.0 0.5 0.5 29.2 55.3 0.0 0 50
46 225 8 806 74 130 0.0 0.7 0.5 33.1 65.4 0.0 0 52
47 221 8 971 125 114 0.0 0.5 0.5 31.9 45.6 0.0 0 52
48 218 8 869 125 104 0.0 0.9 0.5 30.0 56.0 0.0 0 48
49 214 8 999 153 140 0.0 0.8 0.5 30.4 46.4 0.0 0 52
50 210 8 798 192 139 0.0 1.0 0.5 28.9 50.0 0.0 0 52
51 206 8 860 125 157 0.0 1.2 0.5 31.5 26.9 0.0 0 52
52 203 8 893 186 127 5.9 0.9 0.5 26.4 42.3 0.0 0 46
53 199 8 863 126 141 0.0 1.2 0.5 32.5 44.4 0.0 0 44
54 196 8 788 97 133 0.0 0.9 0.5 37.5 40.0 0.0 0 50
55 192 8 926 119 116 0.0 0.6 0.5 26.1 55.3 0.0 0 52
56 189 8 789 162 107 0.0 0.8 0.5 25.2 40.4 0.0 0 48
57 186 8 878 107 128 0.0 1.1 0.5 23.1 34.0 0.0 0 52
58 182 8 775 105 122 0.0 0.8 0.5 25.5 57.4 0.0 0 50
59 179 8 747 94 129 0.0 0.7 0.5 34.3 37.3 0.0 0 50
60 176 8 845 96 138 0.0 0.6 0.5 28.3 41.7 0.0 0 52
61 173 8 961 121 110 0.0 0.6 0.5 29.0 52.6 0.0 0 48
62 170 4 911 110 109 0.0 0.9 0.5 33.5 33.3 0.0 0 48
63 167 8 656 109 109 0.0 0.8 0.5 21.9 44.7 0.0 0 52
64 164 8 934 117 105 0.0 0.8 0.5 15.5 50.0 0.0 0 52
65 161 8 972 125 95 0.0 0.8 0.5 24.4 50.0 0.0 0 50
66 158 8 894 125 101 0.0 0.9 0.5 27.2 35.9 0.0 0 52
67 155 8 798 146 129 0.0 1.0 0.5 22.8 58.7 0.0 0 52
68 153 8 901 183 92 0.0 1.1 0.5 23.6 34.5 0.0 0 52
69 150 8 977 197 103 0.0 1.4 0.5 23.6 36.8 0.0 0 52
70 147 8 905 262 93 0.0 1.5 0.5 20.3 63.4 0.0 0 52
71 145 8 995 148 122 0.0 1.9 0.5 20.9 35.3 0.0 0 52
72 142 8 934 230 99 0.0 1.6 0.5 20.0 65.9 0.0 0 52
73 140 8 862 173 100 0.0 1.8 0.5 26.8 46.8 0.0 0 52
74 137 8 924 139 90 0.0 1.7 0.5 16.8 42.5 0.0 0 52
75 135 8 888 168 113 0.0 1.6 0.5 22.9 40.4 0.0 0 52
76 133 8 712 212 84 0.0 1.6 0.5 13.4 46.9 0.0 0 52
77 130 8 868 210 91 0.0 1.7 0.5 17.7 51.2 0.0 0 52
78 128 8 952 307 92 0.0 1.9 0.5 19.7 44.9 0.0 0 50
79 126 8 801 157 107 0.0 2.2 0.5 15.8 39.0 0.0 0 52
80 123 8 849 147 93 0.0 2.1 0.5 15.6 51.4 0.0 0 52
81 121 8 799 154 86 0.0 1.9 0.5 12.2 50.0 0.0 0 52
82 119 8 941 213 82 0.0 1.8 0.5 19.5 41.2 0.0 0 50
83 117 8 751 268 94 0.0 2.0 0.5 20.8 42.6 0.0 0 50
84 115 8 828 198 102 0.0 2.2 0.5 15.5 59.5 0.0 0 52
85 113 8 898 266 123 0.0 2.2 0.5 13.2 85.2 0.0 0 52
86 111 8 943 190 93 0.0 2.4 0.5 19.5 45.1 0.0 0 52
87 109 8 864 183 65 0.0 2.4 0.5 14.9 31.8 0.0 0 52
88 107 8 793 203 93 0.0 2.4 0.5 11.8 35.3 0.0 0 52
89 105 8 752 162 74 1.2 2.4 0.5 13.1 21.4 0.0 0 52
90 103 8 801 149 77 0.0 2.3 0.5 9.7 58.3 0.0 0 52
91 102 8 901 230 99 0.0 2.2 0.5 16.0 25.5 0.0 0 52
92 100 8 826 201 87 0.0 2.4 0.5 12.8 45.7 0.0 0 52
93 98 8 810 196 83 0.0 2.5 0.5 14.0 24.4 0.0 0 52
94 96 8 857 209 68 1.0 2.5 0.5 11.5 27.0 5.1 0 52
95 95 8 771 174 91 0.0 2.6 0.5 10.5 26.5 0.0 0 52
96 93 8 955 210 59 0.0 2.6 0.5 10.0 36.7 0.7 0 52
97 91 8 833 206 53 0.0 2.7 0.5 10.2 19.4 1.4 0 52
98 90 8 888 229 86 0.0 2.8 0.5 8.1 36.0 0.0 0 52
99 88 8 794 186 91 1.0 2.9 0.5 8.3 25.0 0.5 0 52
100 81 8 756 170 72 1.0 2.9 0.5 6.0 23.8 7.0 0 52
101 74 8 791 176 67 0.0 2.9 0.5 4.4 58.3 4.0 0 52
102 67 8 813 213 43 0.0 3.0 0.5 7.0 150.0 4.2 0 52
103 62 8 779 245 39 0.0 3.1 0.5 3.2 16.7 13.0 0 52
104 56 8 767 303 63 0.0 3.2 0.5 4.1 20.0 0.7 0 52
105 52 8 757 270 57 0.0 3.5 0.5 6.4 3.7 0.5 0 52
106 47 8 763 283 41 0.0 3.7 0.5 4.5 0.0 0.0 0 52
107 43 8 768 283 36 0.0 3.7 0.5 2.9 18.2 3.6 0 52
108 39 8 804 283 25 0.0 3.7 0.5 3.1 0.0 6.2 0 52
109 36 8 781 283 24 0.0 3.7 0.5 3.6 6.7 6.7 0 52
110 33 8 738 298 42 0.0 3.7 0.5 3.3 15.4 3.5 0 52
111 30 8 761 298 36 0.0 3.7 0.5 2.2 0.0 4.3 0 52
112 27 8 769 298 37 0.0 3.7 0.5 0.9 0.0 2.2 0 52
113 25 8 745 298 31 0.0 3.7 0.5 1.5 0.0 6.6 0 52
114 23 8 753 298 16 0.0 3.7 0.5 1.3 0.0 2.8 0 52
115 21 8 745 298 11 0.0 3.7 0.5 1.5 0.0 14.0 0 52
116 19 8 747 298 21 0.0 3.7 0.5 2.1 0.0 5.8 0 52
117 13 8 737 298 12 0.0 3.7 0.5 1.0 0.0 10.0 0 52
118 9 8 736 298 4 0.0 3.7 0.5 1.5 0.0 18.5 0 52
119 0 8 739 298 0 0.0 3.7 0.5 1.8 0.0 18.0 0 52
120 0 8 732 298 0 0.0 3.7 0.5 1.2 0.0 21.8 0 52
121 0 8 732 19 -1 0.0 0.0 0.5 0.0 100.0 54.8
Initial Wiring Cost: 645 Final Wiring Cost: 732
############## Percent Wire Cost Reduction: -13
Initial Wire Length: 645 Final Wire Length: 732
************** Percent Wire Length Reduction: -13
Initial Horiz. Wire: 216 Final Horiz. Wire: 147
$$$$$$$$$$$ Percent H-Wire Length Reduction: 32
Initial Vert. Wire: 429 Final Vert. Wire: 585
@@@@@@@@@@@ Percent V-Wire Length Reduction: -36
Before Feeds are Added:
BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET
1 82 -20
2 86 -16
LONGEST Block is:2 Its length is:86
BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET
1 86 -16
2 86 -16
LONGEST Block is:1 Its length is:86
Added: 1 feed-through cells
Removed the cell overlaps --- Will do neighbor interchanges only now
TOTAL INTERCONNECT LENGTH: 994
OVERLAP PENALTY: 0
initialRowControl: 1.650
finalRowControl: 0.300
iter T Wire accept
122 0.001 976 16%
123 0.001 971 0%
124 0.001 971 0%
Total Feed-Alignment Movement (Pass 1): 0
Total Feed-Alignment Movement (Pass 2): 0
Total Feed-Alignment Movement (Pass 3): 0
Total Feed-Alignment Movement (Pass 4): 0
Total Feed-Alignment Movement (Pass 5): 0
Total Feed-Alignment Movement (Pass 6): 0
Total Feed-Alignment Movement (Pass 7): 0
Total Feed-Alignment Movement (Pass 8): 0
The rand generator seed was at globroute() : 987654321
Total Number of Net Segments: 9
Number of Switchable Net Segments: 0
Number of channels: 3
THIS IS THE ORIGINAL NUMBER OF TRACKS: 5
no. of accepted flips: 0
no. of attempted flips: 0
THIS IS THE NUMBER OF TRACKS: 5
FINAL NUMBER OF ROUTING TRACKS: 5
MAX OF CHANNEL: 1 is: 0
MAX OF CHANNEL: 2 is: 4
MAX OF CHANNEL: 3 is: 1
FINAL TOTAL INTERCONNECT LENGTH: 978
FINAL OVERLAP PENALTY: 0 FINAL VALUE OF TOTAL COST IS: 978
MAX NUMBER OF ATTEMPTED FLIPS PER T: 55
cost_scale_factor:3.90616
Number of Feed Thrus: 0
Number of Implicit Feed Thrus: 0
Statistics:
Number of Standard Cells: 10
Number of Pads: 0
Number of Nets: 15
Number of Pins: 46
Usage statistics not available

17
simulators/gem5/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/smred.pin Normal file
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$COUNT_1/$AND2_1/$ND2_1$Z 1 $COUNT_1/$AND2_1/$ND2_1 00#Z 17 52 2 1 0
$COUNT_1/$AND2_1/$ND2_1$Z 1 ACOUNT_1 00#A 15 26 2 -1 0
B7 2 $COUNT_1/$FJK3_2 00#K 25 78 3 -1 0
B7 2 $COUNT_1/$FJK3_2 00#J 23 78 3 -1 0
B7 3 $COUNT_1/$AND2_2/$ND2_1 00#A 9 26 2 -1 0
B7 3 ACOUNT_1 01#Z 17 26 2 -1 0
B6 5 $COUNT_1/$FJK3_1 00#K 25 26 2 -1 0
B6 5 $COUNT_1/$FJK3_1 00#J 23 26 2 -1 0
B6 5 $COUNT_1/$AND2_3/$IV_1 01#Z 7 26 2 -1 0
$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$FJK3_1 01#Q 81 26 2 -1 0
$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$AND2_1/$ND2_1 00#B 19 52 2 1 0
$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$FJK3_2 00#Q 81 52 2 1 0
$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$AND2_2/$ND2_1 01#B 11 26 2 -1 0
$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$ND2_1 00#Z 5 52 2 1 0
$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$IV_1 00#A 5 26 2 -1 0
$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$ND2_1 00#Z 7 52 2 1 0
$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$IV_1 00#A 3 26 2 -1 0

11
simulators/gem5/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/smred.pl1 Normal file
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$COUNT_1/$AND2_4/$IV_1 0 0 4 26 0 1
$COUNT_1/$AND2_3/$IV_1 4 0 8 26 2 1
$COUNT_1/$AND2_2/$ND2_1 8 0 14 26 0 1
ACOUNT_1 14 0 18 26 2 1
twfeed1 18 0 22 26 0 1
$COUNT_1/$FJK3_1 22 0 86 26 0 1
$COUNT_1/$AND2_3/$ND2_1 0 52 6 78 0 2
$COUNT_1/$AND2_4/$ND2_1 6 52 12 78 2 2
$COUNT_1/$AND2_2/$IV_1 12 52 16 78 2 2
$COUNT_1/$AND2_1/$ND2_1 16 52 22 78 2 2
$COUNT_1/$FJK3_2 22 52 86 78 0 2

2
simulators/gem5/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/smred.pl2 Normal file
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@ -0,0 +1,2 @@
1 0 0 86 26 0 0
2 0 52 86 78 0 0

18
simulators/gem5/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/smred.sav Normal file
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@ -0,0 +1,18 @@
0.009592
121
0
1
0.000000
0.500000
3.906156
1
1 1 2 37 13
2 2 0 34 65
3 2 2 63 65
4 1 0 59 13
5 1 2 32 13
6 2 0 23 65
7 1 2 12 13
8 2 0 6 65
9 1 0 70 13
10 2 0 70 65

19
simulators/gem5/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/smred.sv2 Normal file
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@ -0,0 +1,19 @@
0.001000
123
0
2
0.000000
0.500000
3.906156
1
1 1 2 16 13
2 2 2 19 65
3 2 2 14 65
4 1 0 11 13
5 1 2 6 13
6 2 0 3 65
7 1 0 2 13
8 2 2 9 65
9 1 0 50 13
10 2 0 54 65
11 1 0 84 13

29
simulators/gem5/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/smred.twf Normal file
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net 1
segment channel 2
pin1 1 pin2 7 0 0
net 2
segment channel 3
pin1 41 pin2 42 0 0
segment channel 2
pin1 12 pin2 3 0 0
net 3
segment channel 2
pin1 35 pin2 36 0 0
segment channel 2
pin1 19 pin2 35 0 0
net 4
segment channel 2
pin1 5 pin2 38 0 0
net 5
net 7
segment channel 2
pin1 14 pin2 43 0 0
net 8
segment channel 2
pin1 23 pin2 17 0 0
net 9
net 11
segment channel 2
pin1 25 pin2 31 0 0
net 14
net 15

383
simulators/gem5/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt Normal file
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---------- Begin Simulation Statistics ----------
sim_seconds 0.270577 # Number of seconds simulated
sim_ticks 270576960000 # Number of ticks simulated
final_tick 270576960000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1394951 # Simulator instruction rate (inst/s)
host_op_rate 1394952 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1951161352 # Simulator tick rate (ticks/s)
host_mem_usage 227304 # Number of bytes of host memory used
host_seconds 138.67 # Real time elapsed on the host
sim_insts 193444531 # Number of instructions simulated
sim_ops 193444769 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 230208 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 100864 # Number of bytes read from this memory
system.physmem.bytes_read::total 331072 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 230208 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 230208 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 3597 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 1576 # Number of read requests responded to by this memory
system.physmem.num_reads::total 5173 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 850804 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 372774 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 1223578 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 850804 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 850804 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 850804 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 372774 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 1223578 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 401 # Number of system calls
system.cpu.numCycles 541153920 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 193444531 # Number of instructions committed
system.cpu.committedOps 193444769 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 167974818 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 1970372 # Number of float alu accesses
system.cpu.num_func_calls 1957920 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 8665107 # number of instructions that are conditional controls
system.cpu.num_int_insts 167974818 # number of integer instructions
system.cpu.num_fp_insts 1970372 # number of float instructions
system.cpu.num_int_register_reads 352617963 # number of times the integer registers were read
system.cpu.num_int_register_writes 163060136 # number of times the integer registers were written
system.cpu.num_fp_register_reads 3181089 # number of times the floating registers were read
system.cpu.num_fp_register_writes 2974850 # number of times the floating registers were written
system.cpu.num_mem_refs 76733959 # number of memory refs
system.cpu.num_load_insts 57735092 # Number of load instructions
system.cpu.num_store_insts 18998867 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 541153920 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.icache.replacements 10362 # number of replacements
system.cpu.icache.tagsinuse 1591.571713 # Cycle average of tags in use
system.cpu.icache.total_refs 193433261 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 12288 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 15741.639079 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 1591.571713 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.777135 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.777135 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 193433261 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 193433261 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 193433261 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 193433261 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 193433261 # number of overall hits
system.cpu.icache.overall_hits::total 193433261 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 12288 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 12288 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 12288 # number of demand (read+write) misses
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system.cpu.l2cache.ReadExReq_mshr_misses::total 1078 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 3597 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 1576 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 5173 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3597 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 1576 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 5173 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 143880000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 19920000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 163800000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 43120000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 43120000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 143880000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 63040000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 206920000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 143880000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 63040000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 206920000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.292725 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.320272 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.292725 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.373125 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.292725 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.373125 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

550
simulators/gem5/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini Normal file
View File

@ -0,0 +1,550 @@
[root]
type=Root
children=system
full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
boot_osflags=a
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
readfile=
symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.cpu]
type=DerivO3CPU
children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
LSQDepCheckShift=4
RASSize=16
SQEntries=32
SSITSize=1024
activity=0
backComSize=5
cachePorts=200
checker=Null
choiceCtrBits=2
choicePredictorSize=8192
clock=500
commitToDecodeDelay=1
commitToFetchDelay=1
commitToIEWDelay=1
commitToRenameDelay=1
commitWidth=8
cpu_id=0
decodeToFetchDelay=1
decodeToRenameDelay=1
decodeWidth=8
defer_registration=false
dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
fetchToDecodeDelay=1
fetchTrapLatency=1
fetchWidth=8
forwardComSize=5
fuPool=system.cpu.fuPool
function_trace=false
function_trace_start=0
globalCtrBits=2
globalHistoryBits=13
globalPredictorSize=8192
iewToCommitDelay=1
iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
instShiftAmt=2
interrupts=system.cpu.interrupts
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
localCtrBits=2
localHistoryBits=11
localHistoryTableSize=2048
localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
needsTSO=true
numIQEntries=64
numPhysFloatRegs=256
numPhysIntRegs=256
numROBEntries=192
numRobs=1
numThreads=1
phase=0
predType=tournament
profile=0
progress_interval=0
renameToDecodeDelay=1
renameToFetchDelay=1
renameToIEWDelay=2
renameToROBDelay=1
renameWidth=8
smtCommitPolicy=RoundRobin
smtFetchPolicy=SingleThread
smtIQPolicy=Partitioned
smtIQThreshold=100
smtLSQPolicy=Partitioned
smtLSQThreshold=100
smtNumFetchingThreads=1
smtROBPolicy=Partitioned
smtROBThreshold=100
squashWidth=8
store_set_clear_period=250000
system=system
tracer=system.cpu.tracer
trapLatency=13
wbDepth=1
wbWidth=8
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=262144
subblock_size=0
system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
[system.cpu.dtb]
type=X86TLB
children=walker
size=64
walker=system.cpu.dtb.walker
[system.cpu.dtb.walker]
type=X86PagetableWalker
system=system
port=system.cpu.toL2Bus.slave[3]
[system.cpu.fuPool]
type=FUPool
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
[system.cpu.fuPool.FUList0]
type=FUDesc
children=opList
count=6
opList=system.cpu.fuPool.FUList0.opList
[system.cpu.fuPool.FUList0.opList]
type=OpDesc
issueLat=1
opClass=IntAlu
opLat=1
[system.cpu.fuPool.FUList1]
type=FUDesc
children=opList0 opList1
count=2
opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
[system.cpu.fuPool.FUList1.opList0]
type=OpDesc
issueLat=1
opClass=IntMult
opLat=3
[system.cpu.fuPool.FUList1.opList1]
type=OpDesc
issueLat=19
opClass=IntDiv
opLat=20
[system.cpu.fuPool.FUList2]
type=FUDesc
children=opList0 opList1 opList2
count=4
opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
[system.cpu.fuPool.FUList2.opList0]
type=OpDesc
issueLat=1
opClass=FloatAdd
opLat=2
[system.cpu.fuPool.FUList2.opList1]
type=OpDesc
issueLat=1
opClass=FloatCmp
opLat=2
[system.cpu.fuPool.FUList2.opList2]
type=OpDesc
issueLat=1
opClass=FloatCvt
opLat=2
[system.cpu.fuPool.FUList3]
type=FUDesc
children=opList0 opList1 opList2
count=2
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
[system.cpu.fuPool.FUList3.opList0]
type=OpDesc
issueLat=1
opClass=FloatMult
opLat=4
[system.cpu.fuPool.FUList3.opList1]
type=OpDesc
issueLat=12
opClass=FloatDiv
opLat=12
[system.cpu.fuPool.FUList3.opList2]
type=OpDesc
issueLat=24
opClass=FloatSqrt
opLat=24
[system.cpu.fuPool.FUList4]
type=FUDesc
children=opList
count=0
opList=system.cpu.fuPool.FUList4.opList
[system.cpu.fuPool.FUList4.opList]
type=OpDesc
issueLat=1
opClass=MemRead
opLat=1
[system.cpu.fuPool.FUList5]
type=FUDesc
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
count=4
opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
[system.cpu.fuPool.FUList5.opList00]
type=OpDesc
issueLat=1
opClass=SimdAdd
opLat=1
[system.cpu.fuPool.FUList5.opList01]
type=OpDesc
issueLat=1
opClass=SimdAddAcc
opLat=1
[system.cpu.fuPool.FUList5.opList02]
type=OpDesc
issueLat=1
opClass=SimdAlu
opLat=1
[system.cpu.fuPool.FUList5.opList03]
type=OpDesc
issueLat=1
opClass=SimdCmp
opLat=1
[system.cpu.fuPool.FUList5.opList04]
type=OpDesc
issueLat=1
opClass=SimdCvt
opLat=1
[system.cpu.fuPool.FUList5.opList05]
type=OpDesc
issueLat=1
opClass=SimdMisc
opLat=1
[system.cpu.fuPool.FUList5.opList06]
type=OpDesc
issueLat=1
opClass=SimdMult
opLat=1
[system.cpu.fuPool.FUList5.opList07]
type=OpDesc
issueLat=1
opClass=SimdMultAcc
opLat=1
[system.cpu.fuPool.FUList5.opList08]
type=OpDesc
issueLat=1
opClass=SimdShift
opLat=1
[system.cpu.fuPool.FUList5.opList09]
type=OpDesc
issueLat=1
opClass=SimdShiftAcc
opLat=1
[system.cpu.fuPool.FUList5.opList10]
type=OpDesc
issueLat=1
opClass=SimdSqrt
opLat=1
[system.cpu.fuPool.FUList5.opList11]
type=OpDesc
issueLat=1
opClass=SimdFloatAdd
opLat=1
[system.cpu.fuPool.FUList5.opList12]
type=OpDesc
issueLat=1
opClass=SimdFloatAlu
opLat=1
[system.cpu.fuPool.FUList5.opList13]
type=OpDesc
issueLat=1
opClass=SimdFloatCmp
opLat=1
[system.cpu.fuPool.FUList5.opList14]
type=OpDesc
issueLat=1
opClass=SimdFloatCvt
opLat=1
[system.cpu.fuPool.FUList5.opList15]
type=OpDesc
issueLat=1
opClass=SimdFloatDiv
opLat=1
[system.cpu.fuPool.FUList5.opList16]
type=OpDesc
issueLat=1
opClass=SimdFloatMisc
opLat=1
[system.cpu.fuPool.FUList5.opList17]
type=OpDesc
issueLat=1
opClass=SimdFloatMult
opLat=1
[system.cpu.fuPool.FUList5.opList18]
type=OpDesc
issueLat=1
opClass=SimdFloatMultAcc
opLat=1
[system.cpu.fuPool.FUList5.opList19]
type=OpDesc
issueLat=1
opClass=SimdFloatSqrt
opLat=1
[system.cpu.fuPool.FUList6]
type=FUDesc
children=opList
count=0
opList=system.cpu.fuPool.FUList6.opList
[system.cpu.fuPool.FUList6.opList]
type=OpDesc
issueLat=1
opClass=MemWrite
opLat=1
[system.cpu.fuPool.FUList7]
type=FUDesc
children=opList0 opList1
count=4
opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
[system.cpu.fuPool.FUList7.opList0]
type=OpDesc
issueLat=1
opClass=MemRead
opLat=1
[system.cpu.fuPool.FUList7.opList1]
type=OpDesc
issueLat=1
opClass=MemWrite
opLat=1
[system.cpu.fuPool.FUList8]
type=FUDesc
children=opList
count=1
opList=system.cpu.fuPool.FUList8.opList
[system.cpu.fuPool.FUList8.opList]
type=OpDesc
issueLat=3
opClass=IprAccess
opLat=3
[system.cpu.icache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=131072
subblock_size=0
system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.interrupts]
type=X86LocalApic
int_latency=1000
pio_addr=2305843009213693952
pio_latency=1000
system=system
int_master=system.membus.slave[2]
int_slave=system.membus.master[2]
pio=system.membus.master[1]
[system.cpu.itb]
type=X86TLB
children=walker
size=64
walker=system.cpu.itb.walker
[system.cpu.itb.walker]
type=X86PagetableWalker
system=system
port=system.cpu.toL2Bus.slave[2]
[system.cpu.l2cache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=false
latency=1000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=2097152
subblock_size=0
system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
[system.cpu.toL2Bus]
type=CoherentBus
block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=twolf smred
cwd=build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing
egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/cpu2000/binaries/x86/linux/twolf
gid=100
input=cin
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=0
system=system
uid=100
[system.membus]
type=CoherentBus
block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave
slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master
[system.physmem]
type=SimpleMemory
conf_table_reported=false
file=
in_addr_map=true
latency=30000
latency_var=0
null=false
range=0:134217727
zero=false
port=system.membus.master[0]

4
simulators/gem5/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simerr Executable file
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@ -0,0 +1,4 @@
warn: Sockets disabled, not accepting gdb connections
warn: instruction 'fnstcw_Mw' unimplemented
warn: instruction 'fldcw_Mw' unimplemented
hack: be nice to actually delete the event here

27
simulators/gem5/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout Executable file
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@ -0,0 +1,27 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 4 2012 13:44:28
gem5 started Jun 4 2012 16:25:20
gem5 executing on zizzer
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing
Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/smred.sav
Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/smred.sv2
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
Standard Cell Placement and Global Routing Program
Authors: Carl Sechen, Bill Swartz
Yale University
info: Increasing stack size by one page.
info: Increasing stack size by one page.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
61 62 63 64 65 66 67 68 69 70 71 72 73 74 75
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
122 123 124 Exiting @ tick 87751730000 because target called exit()

276
simulators/gem5/tests/long/se/70.twolf/ref/x86/linux/o3-timing/smred.out Normal file
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@ -0,0 +1,276 @@
TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
Standard Cell Placement and Global Routing Program
Authors: Carl Sechen, Bill Swartz
Yale University
NOTE: Restart file .rs2 not used
TimberWolf will perform a global route step
rowSep: 1.000000
feedThruWidth: 4
******************
BLOCK DATA
block:1 desire:85
block:2 desire:85
Total Desired Length: 170
total cell length: 168
total block length: 168
block x-span:84 block y-span:78
implicit feed thru range: -84
Using default value of bin.penalty.control:1.000000
numBins automatically set to:5
binWidth = average_cell_width + 0 sigma= 17
average_cell_width is:16
standard deviation of cell length is:23.6305
TimberWolfSC starting from the beginning
THIS IS THE ROUTE COST OF THE ORIGINAL PLACEMENT: 645
The number of nets with 1 pin is 4
The number of nets with 2 pin is 9
The number of nets with 3 pin is 0
The number of nets with 4 pin is 2
The number of nets with 5 pin is 0
The number of nets with 6 pin is 0
The number of nets with 7 pin is 0
The number of nets with 8 pin is 0
The number of nets with 9 pin is 0
The number of nets with 10 pin or more is 0
New Cost Function: Initial Horizontal Cost:242
New Cost Function: FEEDS:0 MISSING_ROWS:-46
bdxlen:86 bdylen:78
l:0 t:78 r:86 b:0
THIS IS THE ROUTE COST OF THE CURRENT PLACEMENT: 645
THIS IS THE PENALTY OF THE CURRENT PLACEMENT: 44
The rand generator seed was at utemp() : 1
tempfile[0][0] = 0.982500 tempfile[0][1] = 90.000000
tempfile[1][0] = 0.915000 tempfile[1][1] = 20.000000
tempfile[2][0] = 0.700000 tempfile[2][1] = 10.000000
tempfile[3][0] = 0.100000 tempfile[3][1] = 0.000000
I T fds Wire Penalty P_lim Epct binC rowC acc s/p early FDs MRs
1 500 0 929 592 160 30.0 1.0 3.0 84.2 34.7 0.0 0 40
2 491 0 876 106 726 0.0 0.8 2.5 80.0 18.5 0.0 0 46
3 482 0 822 273 372 0.0 0.5 1.5 80.8 21.2 0.0 0 46
4 474 0 826 53 247 0.0 0.5 0.9 65.0 21.9 0.0 0 48
5 465 8 987 73 190 0.0 0.5 0.5 50.0 38.3 0.0 0 46
6 457 8 851 67 226 0.0 0.5 0.5 53.8 42.9 0.0 0 52
7 449 8 1067 108 190 0.0 0.5 0.5 46.2 53.8 0.0 0 50
8 441 8 918 106 171 0.0 0.5 0.5 47.1 40.4 0.0 0 48
9 434 8 812 101 197 0.0 0.5 0.5 53.6 21.0 0.0 0 48
10 426 8 1038 121 181 0.0 0.5 0.5 43.6 27.1 0.0 0 48
11 419 8 898 93 187 0.0 0.5 0.5 45.3 47.8 0.0 0 50
12 411 4 857 94 240 0.0 0.5 0.5 62.7 51.6 0.0 0 44
13 404 8 1043 88 185 0.0 0.5 0.5 54.0 52.8 0.0 0 50
14 397 8 767 94 154 0.0 0.5 0.5 33.8 35.0 0.0 0 50
15 390 8 862 89 183 0.0 0.5 0.5 55.6 29.0 0.0 0 46
16 383 4 798 79 173 0.0 0.5 0.5 57.5 35.3 0.0 0 52
17 376 8 827 100 152 0.0 0.5 0.5 35.3 81.8 0.0 0 50
18 370 8 878 101 208 0.0 0.5 0.5 44.7 46.2 0.0 0 48
19 363 4 921 67 167 0.0 0.5 0.5 57.1 34.7 0.0 0 48
20 357 8 933 93 154 0.0 0.5 0.5 46.5 43.6 0.0 0 52
21 351 8 930 89 147 0.0 0.5 0.5 39.4 36.5 0.0 0 52
22 345 8 951 79 142 0.0 0.5 0.5 32.8 51.3 0.0 0 50
23 339 8 1046 87 207 0.0 0.5 0.5 52.8 61.0 0.0 0 48
24 333 4 989 96 185 0.0 0.5 0.5 45.3 43.3 0.0 0 42
25 327 4 577 86 157 0.0 0.5 0.5 31.1 55.3 0.0 0 52
26 321 8 776 97 174 0.0 0.5 0.5 47.9 62.5 0.0 0 52
27 315 8 850 81 188 0.0 0.5 0.5 45.0 55.2 0.0 0 50
28 310 8 898 97 148 0.0 0.5 0.5 43.0 45.8 0.0 0 48
29 304 8 889 65 173 0.0 0.5 0.5 32.5 41.3 0.0 0 50
30 299 8 858 81 153 0.0 0.5 0.5 44.3 29.2 0.0 0 46
31 294 8 871 82 187 0.0 0.5 0.5 45.7 47.7 0.0 0 48
32 289 8 782 109 173 0.0 0.5 0.5 35.2 57.4 0.0 0 48
33 284 8 743 98 189 0.0 0.6 0.5 41.8 64.3 0.0 0 52
34 279 8 943 90 147 0.0 0.5 0.5 38.6 32.8 0.0 0 48
35 274 8 907 57 166 0.0 0.5 0.5 33.6 51.0 0.0 0 48
36 269 8 900 70 148 0.0 0.5 0.5 45.0 41.4 0.0 0 50
37 264 4 875 106 133 0.0 0.5 0.5 31.7 55.3 0.0 0 52
38 260 8 1023 145 149 0.0 0.6 0.5 28.7 65.0 0.0 0 52
39 255 8 801 151 173 0.0 0.9 0.5 41.7 41.2 0.0 0 48
40 251 8 741 104 159 0.0 0.8 0.5 36.2 47.5 0.0 0 48
41 246 8 828 108 149 0.0 0.5 0.5 34.6 50.9 0.0 0 50
42 242 8 947 128 132 0.0 0.7 0.5 34.2 39.0 0.0 0 50
43 238 8 917 101 142 0.0 0.8 0.5 34.4 50.9 0.0 0 48
44 234 8 761 86 129 0.0 0.5 0.5 42.0 36.4 0.0 0 52
45 229 8 979 106 137 0.0 0.5 0.5 29.2 55.3 0.0 0 50
46 225 8 806 74 130 0.0 0.7 0.5 33.1 65.4 0.0 0 52
47 221 8 971 125 114 0.0 0.5 0.5 31.9 45.6 0.0 0 52
48 218 8 869 125 104 0.0 0.9 0.5 30.0 56.0 0.0 0 48
49 214 8 999 153 140 0.0 0.8 0.5 30.4 46.4 0.0 0 52
50 210 8 798 192 139 0.0 1.0 0.5 28.9 50.0 0.0 0 52
51 206 8 860 125 157 0.0 1.2 0.5 31.5 26.9 0.0 0 52
52 203 8 893 186 127 5.9 0.9 0.5 26.4 42.3 0.0 0 46
53 199 8 863 126 141 0.0 1.2 0.5 32.5 44.4 0.0 0 44
54 196 8 788 97 133 0.0 0.9 0.5 37.5 40.0 0.0 0 50
55 192 8 926 119 116 0.0 0.6 0.5 26.1 55.3 0.0 0 52
56 189 8 789 162 107 0.0 0.8 0.5 25.2 40.4 0.0 0 48
57 186 8 878 107 128 0.0 1.1 0.5 23.1 34.0 0.0 0 52
58 182 8 775 105 122 0.0 0.8 0.5 25.5 57.4 0.0 0 50
59 179 8 747 94 129 0.0 0.7 0.5 34.3 37.3 0.0 0 50
60 176 8 845 96 138 0.0 0.6 0.5 28.3 41.7 0.0 0 52
61 173 8 961 121 110 0.0 0.6 0.5 29.0 52.6 0.0 0 48
62 170 4 911 110 109 0.0 0.9 0.5 33.5 33.3 0.0 0 48
63 167 8 656 109 109 0.0 0.8 0.5 21.9 44.7 0.0 0 52
64 164 8 934 117 105 0.0 0.8 0.5 15.5 50.0 0.0 0 52
65 161 8 972 125 95 0.0 0.8 0.5 24.4 50.0 0.0 0 50
66 158 8 894 125 101 0.0 0.9 0.5 27.2 35.9 0.0 0 52
67 155 8 798 146 129 0.0 1.0 0.5 22.8 58.7 0.0 0 52
68 153 8 901 183 92 0.0 1.1 0.5 23.6 34.5 0.0 0 52
69 150 8 977 197 103 0.0 1.4 0.5 23.6 36.8 0.0 0 52
70 147 8 905 262 93 0.0 1.5 0.5 20.3 63.4 0.0 0 52
71 145 8 995 148 122 0.0 1.9 0.5 20.9 35.3 0.0 0 52
72 142 8 934 230 99 0.0 1.6 0.5 20.0 65.9 0.0 0 52
73 140 8 862 173 100 0.0 1.8 0.5 26.8 46.8 0.0 0 52
74 137 8 924 139 90 0.0 1.7 0.5 16.8 42.5 0.0 0 52
75 135 8 888 168 113 0.0 1.6 0.5 22.9 40.4 0.0 0 52
76 133 8 712 212 84 0.0 1.6 0.5 13.4 46.9 0.0 0 52
77 130 8 868 210 91 0.0 1.7 0.5 17.7 51.2 0.0 0 52
78 128 8 952 307 92 0.0 1.9 0.5 19.7 44.9 0.0 0 50
79 126 8 801 157 107 0.0 2.2 0.5 15.8 39.0 0.0 0 52
80 123 8 849 147 93 0.0 2.1 0.5 15.6 51.4 0.0 0 52
81 121 8 799 154 86 0.0 1.9 0.5 12.2 50.0 0.0 0 52
82 119 8 941 213 82 0.0 1.8 0.5 19.5 41.2 0.0 0 50
83 117 8 751 268 94 0.0 2.0 0.5 20.8 42.6 0.0 0 50
84 115 8 828 198 102 0.0 2.2 0.5 15.5 59.5 0.0 0 52
85 113 8 898 266 123 0.0 2.2 0.5 13.2 85.2 0.0 0 52
86 111 8 943 190 93 0.0 2.4 0.5 19.5 45.1 0.0 0 52
87 109 8 864 183 65 0.0 2.4 0.5 14.9 31.8 0.0 0 52
88 107 8 793 203 93 0.0 2.4 0.5 11.8 35.3 0.0 0 52
89 105 8 752 162 74 1.2 2.4 0.5 13.1 21.4 0.0 0 52
90 103 8 801 149 77 0.0 2.3 0.5 9.7 58.3 0.0 0 52
91 102 8 901 230 99 0.0 2.2 0.5 16.0 25.5 0.0 0 52
92 100 8 826 201 87 0.0 2.4 0.5 12.8 45.7 0.0 0 52
93 98 8 810 196 83 0.0 2.5 0.5 14.0 24.4 0.0 0 52
94 96 8 857 209 68 1.0 2.5 0.5 11.5 27.0 5.1 0 52
95 95 8 771 174 91 0.0 2.6 0.5 10.5 26.5 0.0 0 52
96 93 8 955 210 59 0.0 2.6 0.5 10.0 36.7 0.7 0 52
97 91 8 833 206 53 0.0 2.7 0.5 10.2 19.4 1.4 0 52
98 90 8 888 229 86 0.0 2.8 0.5 8.1 36.0 0.0 0 52
99 88 8 794 186 91 1.0 2.9 0.5 8.3 25.0 0.5 0 52
100 81 8 756 170 72 1.0 2.9 0.5 6.0 23.8 7.0 0 52
101 74 8 791 176 67 0.0 2.9 0.5 4.4 58.3 4.0 0 52
102 67 8 813 213 43 0.0 3.0 0.5 7.0 150.0 4.2 0 52
103 62 8 779 245 39 0.0 3.1 0.5 3.2 16.7 13.0 0 52
104 56 8 767 303 63 0.0 3.2 0.5 4.1 20.0 0.7 0 52
105 52 8 757 270 57 0.0 3.5 0.5 6.4 3.7 0.5 0 52
106 47 8 763 283 41 0.0 3.7 0.5 4.5 0.0 0.0 0 52
107 43 8 768 283 36 0.0 3.7 0.5 2.9 18.2 3.6 0 52
108 39 8 804 283 25 0.0 3.7 0.5 3.1 0.0 6.2 0 52
109 36 8 781 283 24 0.0 3.7 0.5 3.6 6.7 6.7 0 52
110 33 8 738 298 42 0.0 3.7 0.5 3.3 15.4 3.5 0 52
111 30 8 761 298 36 0.0 3.7 0.5 2.2 0.0 4.3 0 52
112 27 8 769 298 37 0.0 3.7 0.5 0.9 0.0 2.2 0 52
113 25 8 745 298 31 0.0 3.7 0.5 1.5 0.0 6.6 0 52
114 23 8 753 298 16 0.0 3.7 0.5 1.3 0.0 2.8 0 52
115 21 8 745 298 11 0.0 3.7 0.5 1.5 0.0 14.0 0 52
116 19 8 747 298 21 0.0 3.7 0.5 2.1 0.0 5.8 0 52
117 13 8 737 298 12 0.0 3.7 0.5 1.0 0.0 10.0 0 52
118 9 8 736 298 4 0.0 3.7 0.5 1.5 0.0 18.5 0 52
119 0 8 739 298 0 0.0 3.7 0.5 1.8 0.0 18.0 0 52
120 0 8 732 298 0 0.0 3.7 0.5 1.2 0.0 21.8 0 52
121 0 8 732 19 -1 0.0 0.0 0.5 0.0 100.0 54.8
Initial Wiring Cost: 645 Final Wiring Cost: 732
############## Percent Wire Cost Reduction: -13
Initial Wire Length: 645 Final Wire Length: 732
************** Percent Wire Length Reduction: -13
Initial Horiz. Wire: 216 Final Horiz. Wire: 147
$$$$$$$$$$$ Percent H-Wire Length Reduction: 32
Initial Vert. Wire: 429 Final Vert. Wire: 585
@@@@@@@@@@@ Percent V-Wire Length Reduction: -36
Before Feeds are Added:
BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET
1 82 -20
2 86 -16
LONGEST Block is:2 Its length is:86
BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET
1 86 -16
2 86 -16
LONGEST Block is:1 Its length is:86
Added: 1 feed-through cells
Removed the cell overlaps --- Will do neighbor interchanges only now
TOTAL INTERCONNECT LENGTH: 994
OVERLAP PENALTY: 0
initialRowControl: 1.650
finalRowControl: 0.300
iter T Wire accept
122 0.001 976 16%
123 0.001 971 0%
124 0.001 971 0%
Total Feed-Alignment Movement (Pass 1): 0
Total Feed-Alignment Movement (Pass 2): 0
Total Feed-Alignment Movement (Pass 3): 0
Total Feed-Alignment Movement (Pass 4): 0
Total Feed-Alignment Movement (Pass 5): 0
Total Feed-Alignment Movement (Pass 6): 0
Total Feed-Alignment Movement (Pass 7): 0
Total Feed-Alignment Movement (Pass 8): 0
The rand generator seed was at globroute() : 987654321
Total Number of Net Segments: 9
Number of Switchable Net Segments: 0
Number of channels: 3
THIS IS THE ORIGINAL NUMBER OF TRACKS: 5
no. of accepted flips: 0
no. of attempted flips: 0
THIS IS THE NUMBER OF TRACKS: 5
FINAL NUMBER OF ROUTING TRACKS: 5
MAX OF CHANNEL: 1 is: 0
MAX OF CHANNEL: 2 is: 4
MAX OF CHANNEL: 3 is: 1
FINAL TOTAL INTERCONNECT LENGTH: 978
FINAL OVERLAP PENALTY: 0 FINAL VALUE OF TOTAL COST IS: 978
MAX NUMBER OF ATTEMPTED FLIPS PER T: 55
cost_scale_factor:3.90616
Number of Feed Thrus: 0
Number of Implicit Feed Thrus: 0
Statistics:
Number of Standard Cells: 10
Number of Pads: 0
Number of Nets: 15
Number of Pins: 46
Usage statistics not available

17
simulators/gem5/tests/long/se/70.twolf/ref/x86/linux/o3-timing/smred.pin Normal file
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@ -0,0 +1,17 @@
$COUNT_1/$AND2_1/$ND2_1$Z 1 $COUNT_1/$AND2_1/$ND2_1 00#Z 17 52 2 1 0
$COUNT_1/$AND2_1/$ND2_1$Z 1 ACOUNT_1 00#A 15 26 2 -1 0
B7 2 $COUNT_1/$FJK3_2 00#K 25 78 3 -1 0
B7 2 $COUNT_1/$FJK3_2 00#J 23 78 3 -1 0
B7 3 $COUNT_1/$AND2_2/$ND2_1 00#A 9 26 2 -1 0
B7 3 ACOUNT_1 01#Z 17 26 2 -1 0
B6 5 $COUNT_1/$FJK3_1 00#K 25 26 2 -1 0
B6 5 $COUNT_1/$FJK3_1 00#J 23 26 2 -1 0
B6 5 $COUNT_1/$AND2_3/$IV_1 01#Z 7 26 2 -1 0
$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$FJK3_1 01#Q 81 26 2 -1 0
$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$AND2_1/$ND2_1 00#B 19 52 2 1 0
$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$FJK3_2 00#Q 81 52 2 1 0
$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$AND2_2/$ND2_1 01#B 11 26 2 -1 0
$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$ND2_1 00#Z 5 52 2 1 0
$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$IV_1 00#A 5 26 2 -1 0
$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$ND2_1 00#Z 7 52 2 1 0
$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$IV_1 00#A 3 26 2 -1 0

11
simulators/gem5/tests/long/se/70.twolf/ref/x86/linux/o3-timing/smred.pl1 Normal file
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@ -0,0 +1,11 @@
$COUNT_1/$AND2_4/$IV_1 0 0 4 26 0 1
$COUNT_1/$AND2_3/$IV_1 4 0 8 26 2 1
$COUNT_1/$AND2_2/$ND2_1 8 0 14 26 0 1
ACOUNT_1 14 0 18 26 2 1
twfeed1 18 0 22 26 0 1
$COUNT_1/$FJK3_1 22 0 86 26 0 1
$COUNT_1/$AND2_3/$ND2_1 0 52 6 78 0 2
$COUNT_1/$AND2_4/$ND2_1 6 52 12 78 2 2
$COUNT_1/$AND2_2/$IV_1 12 52 16 78 2 2
$COUNT_1/$AND2_1/$ND2_1 16 52 22 78 2 2
$COUNT_1/$FJK3_2 22 52 86 78 0 2

2
simulators/gem5/tests/long/se/70.twolf/ref/x86/linux/o3-timing/smred.pl2 Normal file
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@ -0,0 +1,2 @@
1 0 0 86 26 0 0
2 0 52 86 78 0 0

18
simulators/gem5/tests/long/se/70.twolf/ref/x86/linux/o3-timing/smred.sav Normal file
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@ -0,0 +1,18 @@
0.009592
121
0
1
0.000000
0.500000
3.906156
1
1 1 2 37 13
2 2 0 34 65
3 2 2 63 65
4 1 0 59 13
5 1 2 32 13
6 2 0 23 65
7 1 2 12 13
8 2 0 6 65
9 1 0 70 13
10 2 0 70 65

19
simulators/gem5/tests/long/se/70.twolf/ref/x86/linux/o3-timing/smred.sv2 Normal file
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@ -0,0 +1,19 @@
0.001000
123
0
2
0.000000
0.500000
3.906156
1
1 1 2 16 13
2 2 2 19 65
3 2 2 14 65
4 1 0 11 13
5 1 2 6 13
6 2 0 3 65
7 1 0 2 13
8 2 2 9 65
9 1 0 50 13
10 2 0 54 65
11 1 0 84 13

29
simulators/gem5/tests/long/se/70.twolf/ref/x86/linux/o3-timing/smred.twf Normal file
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@ -0,0 +1,29 @@
net 1
segment channel 2
pin1 1 pin2 7 0 0
net 2
segment channel 3
pin1 41 pin2 42 0 0
segment channel 2
pin1 12 pin2 3 0 0
net 3
segment channel 2
pin1 35 pin2 36 0 0
segment channel 2
pin1 19 pin2 35 0 0
net 4
segment channel 2
pin1 5 pin2 38 0 0
net 5
net 7
segment channel 2
pin1 14 pin2 43 0 0
net 8
segment channel 2
pin1 23 pin2 17 0 0
net 9
net 11
segment channel 2
pin1 25 pin2 31 0 0
net 14
net 15

642
simulators/gem5/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt Normal file
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@ -0,0 +1,642 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.087752 # Number of seconds simulated
sim_ticks 87751730000 # Number of ticks simulated
final_tick 87751730000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 66952 # Simulator instruction rate (inst/s)
host_op_rate 112217 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 44484510 # Simulator tick rate (ticks/s)
host_mem_usage 236376 # Number of bytes of host memory used
host_seconds 1972.64 # Real time elapsed on the host
sim_insts 132071227 # Number of instructions simulated
sim_ops 221363017 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 219584 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 125440 # Number of bytes read from this memory
system.physmem.bytes_read::total 345024 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 219584 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 219584 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 3431 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 1960 # Number of read requests responded to by this memory
system.physmem.num_reads::total 5391 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 2502332 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 1429487 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 3931820 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 2502332 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 2502332 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 2502332 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 1429487 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 3931820 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 400 # Number of system calls
system.cpu.numCycles 175503461 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.BPredUnit.lookups 20929970 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 20929970 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 2208761 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 15515509 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 13857635 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 27320294 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 226942709 # Number of instructions fetch has processed
system.cpu.fetch.Branches 20929970 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 13857635 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 59854483 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 19459786 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 71271521 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 647 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 5211 # Number of stall cycles due to pending traps
system.cpu.fetch.CacheLines 25822554 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 471165 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 175426420 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.136612 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.300359 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 117249103 66.84% 66.84% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 3234615 1.84% 68.68% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 2477718 1.41% 70.09% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 3147881 1.79% 71.89% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 3542128 2.02% 73.91% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 3766355 2.15% 76.05% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 4530628 2.58% 78.64% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 2823565 1.61% 80.25% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 34654427 19.75% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 175426420 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.119257 # Number of branch fetches per cycle
system.cpu.fetch.rate 1.293095 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 40654970 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 61059749 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 46547974 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 10189463 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 16974264 # Number of cycles decode is squashing
system.cpu.decode.DecodedInsts 365977737 # Number of instructions handled by decode
system.cpu.rename.SquashCycles 16974264 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 48548849 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 16319097 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 23046 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 48140036 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 45421128 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 356799059 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 33 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 20636040 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 22537767 # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents 2198 # Number of times there has been no free registers
system.cpu.rename.RenamedOperands 506554560 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 1130537584 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 1120266837 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 10270747 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 320143989 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 186410571 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 1911 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 1906 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 95097015 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 89808446 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 33130186 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 59201466 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 19519303 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 344515408 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 7842 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 270869041 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 254270 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 122674827 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 297005948 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 6596 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 175426420 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 1.544061 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.467197 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 49131919 28.01% 28.01% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 52597597 29.98% 57.99% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 34344440 19.58% 77.57% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 18981960 10.82% 88.39% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 12711399 7.25% 95.63% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 4926918 2.81% 98.44% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 2079867 1.19% 99.63% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 541264 0.31% 99.94% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 111056 0.06% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 175426420 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 91065 3.49% 3.49% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 3.49% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 3.49% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.49% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.49% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.49% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 3.49% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.49% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.49% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.49% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.49% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.49% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.49% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.49% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.49% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 3.49% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.49% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 3.49% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.49% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.49% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.49% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.49% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.49% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.49% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.49% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.49% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.49% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.49% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.49% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 2241508 85.86% 89.35% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 277930 10.65% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 1212815 0.45% 0.45% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 176257528 65.07% 65.52% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 0 0.00% 65.52% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.52% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 1592327 0.59% 66.11% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.11% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.11% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.11% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.11% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.11% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.11% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.11% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.11% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.11% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.11% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.11% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.11% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.11% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.11% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.11% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.11% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.11% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.11% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.11% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.11% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.11% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.11% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.11% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.11% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.11% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 68300084 25.22% 91.32% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 23506287 8.68% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 270869041 # Type of FU issued
system.cpu.iq.rate 1.543383 # Inst issue rate
system.cpu.iq.fu_busy_cnt 2610503 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.009638 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 714724682 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 462639790 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 263265519 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 5304593 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 4857798 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 2549095 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 269608691 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 2658038 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 18925158 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 33158856 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 30567 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 304625 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 12614470 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 47486 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 16974264 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 523635 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 253200 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 344523250 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 297274 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 89808446 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 33130186 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 1859 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 168556 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 31575 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 304625 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 1298513 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 1028751 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 2327264 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 267763849 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 67223329 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 3105192 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
system.cpu.iew.exec_refs 90337843 # number of memory reference insts executed
system.cpu.iew.exec_branches 14773998 # Number of branches executed
system.cpu.iew.exec_stores 23114514 # Number of stores executed
system.cpu.iew.exec_rate 1.525690 # Inst execution rate
system.cpu.iew.wb_sent 266689649 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 265814614 # cumulative count of insts written-back
system.cpu.iew.wb_producers 214459238 # num instructions producing a value
system.cpu.iew.wb_consumers 504388652 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 1.514583 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.425186 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitCommittedInsts 132071227 # The number of committed instructions
system.cpu.commit.commitCommittedOps 221363017 # The number of committed instructions
system.cpu.commit.commitSquashedInsts 123271968 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 1246 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 2209353 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 158452156 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.397034 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.794480 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 54225216 34.22% 34.22% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 60443910 38.15% 72.37% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 15544008 9.81% 82.18% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 12710691 8.02% 90.20% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 4546278 2.87% 93.07% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 2974927 1.88% 94.95% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 2086566 1.32% 96.26% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 1244605 0.79% 97.05% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 4675955 2.95% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 158452156 # Number of insts commited each cycle
system.cpu.commit.committedInsts 132071227 # Number of instructions committed
system.cpu.commit.committedOps 221363017 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 77165306 # Number of memory references committed
system.cpu.commit.loads 56649590 # Number of loads committed
system.cpu.commit.membars 0 # Number of memory barriers committed
system.cpu.commit.branches 12326943 # Number of branches committed
system.cpu.commit.fp_insts 2162459 # Number of committed floating point instructions.
system.cpu.commit.int_insts 220339606 # Number of committed integer instructions.
system.cpu.commit.function_calls 0 # Number of function calls committed.
system.cpu.commit.bw_lim_events 4675955 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 498411186 # The number of ROB reads
system.cpu.rob.rob_writes 706281673 # The number of ROB writes
system.cpu.timesIdled 1684 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 77041 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 132071227 # Number of Instructions Simulated
system.cpu.committedOps 221363017 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 132071227 # Number of Instructions Simulated
system.cpu.cpi 1.328855 # CPI: Cycles Per Instruction
system.cpu.cpi_total 1.328855 # CPI: Total CPI of All Threads
system.cpu.ipc 0.752528 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.752528 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 657510098 # number of integer regfile reads
system.cpu.int_regfile_writes 365370199 # number of integer regfile writes
system.cpu.fp_regfile_reads 3509073 # number of floating regfile reads
system.cpu.fp_regfile_writes 2221147 # number of floating regfile writes
system.cpu.misc_regfile_reads 139423581 # number of misc regfile reads
system.cpu.misc_regfile_writes 844 # number of misc regfile writes
system.cpu.icache.replacements 5601 # number of replacements
system.cpu.icache.tagsinuse 1627.936468 # Cycle average of tags in use
system.cpu.icache.total_refs 25813461 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 7571 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 3409.518029 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 1627.936468 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.794891 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.794891 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 25813461 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 25813461 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 25813461 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 25813461 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 25813461 # number of overall hits
system.cpu.icache.overall_hits::total 25813461 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 9093 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 9093 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 9093 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 9093 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 9093 # number of overall misses
system.cpu.icache.overall_misses::total 9093 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 187306000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 187306000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 187306000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 187306000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 187306000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 187306000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 25822554 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 25822554 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 25822554 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 25822554 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 25822554 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 25822554 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000352 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000352 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000352 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000352 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000352 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000352 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20598.922248 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 20598.922248 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 20598.922248 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 20598.922248 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 20598.922248 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 20598.922248 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1367 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 1367 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 1367 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 1367 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 1367 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 1367 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 7726 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 7726 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 7726 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 7726 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 7726 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 7726 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 130634500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 130634500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 130634500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 130634500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 130634500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 130634500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000299 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000299 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000299 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000299 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000299 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000299 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16908.426094 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16908.426094 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16908.426094 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 16908.426094 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16908.426094 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 16908.426094 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 56 # number of replacements
system.cpu.dcache.tagsinuse 1426.584624 # Cycle average of tags in use
system.cpu.dcache.total_refs 68642098 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 1997 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 34372.607912 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 1426.584624 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.348287 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.348287 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 48127880 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 48127880 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 20514014 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 20514014 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 68641894 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 68641894 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 68641894 # number of overall hits
system.cpu.dcache.overall_hits::total 68641894 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 772 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 772 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 1716 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 1716 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 2488 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 2488 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 2488 # number of overall misses
system.cpu.dcache.overall_misses::total 2488 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 24823500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 24823500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 65115000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 65115000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 89938500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 89938500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 89938500 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 89938500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 48128652 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 48128652 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 20515730 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 20515730 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 68644382 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 68644382 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 68644382 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 68644382 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000016 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.000016 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000084 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.000084 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.000036 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.000036 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.000036 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.000036 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32154.792746 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 32154.792746 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37945.804196 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 37945.804196 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 36148.914791 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 36148.914791 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 36148.914791 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 36148.914791 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 13 # number of writebacks
system.cpu.dcache.writebacks::total 13 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 331 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 331 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 3 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 334 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 334 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 334 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 334 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 441 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 441 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1713 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 1713 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 2154 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 2154 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 2154 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 2154 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 14546500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 14546500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 59868000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 59868000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 74414500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 74414500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 74414500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 74414500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000009 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000083 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000083 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000031 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.000031 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000031 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.000031 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 32985.260771 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 32985.260771 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34949.211909 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34949.211909 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34547.121634 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 34547.121634 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34547.121634 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 34547.121634 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 2579.336511 # Cycle average of tags in use
system.cpu.l2cache.total_refs 4173 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 3841 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 1.086436 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 1.713269 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 2279.819240 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 297.804001 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.000052 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.069575 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.009088 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.078715 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 4140 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 31 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 4171 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 13 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 13 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 8 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 8 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst 4140 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 39 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 4179 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 4140 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 39 # number of overall hits
system.cpu.l2cache.overall_hits::total 4179 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 3431 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 409 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 3840 # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data 155 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total 155 # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 1551 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 1551 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 3431 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 1960 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 5391 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 3431 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 1960 # number of overall misses
system.cpu.l2cache.overall_misses::total 5391 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 117518500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 13976500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 131495000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 52996000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 52996000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 117518500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 66972500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 184491000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 117518500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 66972500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 184491000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 7571 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 440 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 8011 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 13 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 13 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 155 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total 155 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1559 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 1559 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 7571 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 1999 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 9570 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 7571 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 1999 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 9570 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.453177 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.929545 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.479341 # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.994869 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.994869 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.453177 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.980490 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.563323 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.453177 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.980490 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.563323 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34251.967356 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34172.371638 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 34243.489583 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34168.923275 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34168.923275 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34251.967356 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34169.642857 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 34222.036728 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34251.967356 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34169.642857 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 34222.036728 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3431 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 409 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 3840 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 155 # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total 155 # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1551 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 1551 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 3431 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 1960 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 5391 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3431 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 1960 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 5391 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 106440500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 12676500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 119117000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 4805000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 4805000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 48110500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 48110500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 106440500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 60787000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 167227500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 106440500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 60787000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 167227500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.453177 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.929545 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.479341 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994869 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994869 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.453177 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.980490 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.563323 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.453177 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.980490 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.563323 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31023.171087 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 30993.887531 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31020.052083 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31000 # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31019.019987 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31019.019987 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31023.171087 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31013.775510 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31019.755147 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31023.171087 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31013.775510 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31019.755147 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

138
simulators/gem5/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/config.ini Normal file
View File

@ -0,0 +1,138 @@
[root]
type=Root
children=system
full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
boot_osflags=a
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
readfile=
symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.cpu]
type=AtomicSimpleCPU
children=dtb interrupts itb tracer workload
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
fastmem=false
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
phase=0
profile=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
system=system
tracer=system.cpu.tracer
width=1
workload=system.cpu.workload
dcache_port=system.membus.slave[2]
icache_port=system.membus.slave[1]
[system.cpu.dtb]
type=X86TLB
children=walker
size=64
walker=system.cpu.dtb.walker
[system.cpu.dtb.walker]
type=X86PagetableWalker
system=system
port=system.membus.slave[4]
[system.cpu.interrupts]
type=X86LocalApic
int_latency=1000
pio_addr=2305843009213693952
pio_latency=1000
system=system
int_master=system.membus.slave[5]
int_slave=system.membus.master[2]
pio=system.membus.master[1]
[system.cpu.itb]
type=X86TLB
children=walker
size=64
walker=system.cpu.itb.walker
[system.cpu.itb.walker]
type=X86PagetableWalker
system=system
port=system.membus.slave[3]
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=twolf smred
cwd=build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-atomic
egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/cpu2000/binaries/x86/linux/twolf
gid=100
input=cin
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=0
system=system
uid=100
[system.membus]
type=CoherentBus
block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.interrupts.int_master
[system.physmem]
type=SimpleMemory
conf_table_reported=false
file=
in_addr_map=true
latency=30000
latency_var=0
null=false
range=0:134217727
zero=false
port=system.membus.master[0]

4
simulators/gem5/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simerr Executable file
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@ -0,0 +1,4 @@
warn: Sockets disabled, not accepting gdb connections
warn: instruction 'fnstcw_Mw' unimplemented
warn: instruction 'fldcw_Mw' unimplemented
hack: be nice to actually delete the event here

27
simulators/gem5/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simout Executable file
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@ -0,0 +1,27 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 4 2012 13:44:28
gem5 started Jun 4 2012 16:58:23
gem5 executing on zizzer
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-atomic
Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-atomic/smred.sav
Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-atomic/smred.sv2
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
Standard Cell Placement and Global Routing Program
Authors: Carl Sechen, Bill Swartz
Yale University
info: Increasing stack size by one page.
info: Increasing stack size by one page.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
61 62 63 64 65 66 67 68 69 70 71 72 73 74 75
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
122 123 124 Exiting @ tick 131393100000 because target called exit()

276
simulators/gem5/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/smred.out Normal file
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@ -0,0 +1,276 @@
TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
Standard Cell Placement and Global Routing Program
Authors: Carl Sechen, Bill Swartz
Yale University
NOTE: Restart file .rs2 not used
TimberWolf will perform a global route step
rowSep: 1.000000
feedThruWidth: 4
******************
BLOCK DATA
block:1 desire:85
block:2 desire:85
Total Desired Length: 170
total cell length: 168
total block length: 168
block x-span:84 block y-span:78
implicit feed thru range: -84
Using default value of bin.penalty.control:1.000000
numBins automatically set to:5
binWidth = average_cell_width + 0 sigma= 17
average_cell_width is:16
standard deviation of cell length is:23.6305
TimberWolfSC starting from the beginning
THIS IS THE ROUTE COST OF THE ORIGINAL PLACEMENT: 645
The number of nets with 1 pin is 4
The number of nets with 2 pin is 9
The number of nets with 3 pin is 0
The number of nets with 4 pin is 2
The number of nets with 5 pin is 0
The number of nets with 6 pin is 0
The number of nets with 7 pin is 0
The number of nets with 8 pin is 0
The number of nets with 9 pin is 0
The number of nets with 10 pin or more is 0
New Cost Function: Initial Horizontal Cost:242
New Cost Function: FEEDS:0 MISSING_ROWS:-46
bdxlen:86 bdylen:78
l:0 t:78 r:86 b:0
THIS IS THE ROUTE COST OF THE CURRENT PLACEMENT: 645
THIS IS THE PENALTY OF THE CURRENT PLACEMENT: 44
The rand generator seed was at utemp() : 1
tempfile[0][0] = 0.982500 tempfile[0][1] = 90.000000
tempfile[1][0] = 0.915000 tempfile[1][1] = 20.000000
tempfile[2][0] = 0.700000 tempfile[2][1] = 10.000000
tempfile[3][0] = 0.100000 tempfile[3][1] = 0.000000
I T fds Wire Penalty P_lim Epct binC rowC acc s/p early FDs MRs
1 500 0 929 592 160 30.0 1.0 3.0 84.2 34.7 0.0 0 40
2 491 0 876 106 726 0.0 0.8 2.5 80.0 18.5 0.0 0 46
3 482 0 822 273 372 0.0 0.5 1.5 80.8 21.2 0.0 0 46
4 474 0 826 53 247 0.0 0.5 0.9 65.0 21.9 0.0 0 48
5 465 8 987 73 190 0.0 0.5 0.5 50.0 38.3 0.0 0 46
6 457 8 851 67 226 0.0 0.5 0.5 53.8 42.9 0.0 0 52
7 449 8 1067 108 190 0.0 0.5 0.5 46.2 53.8 0.0 0 50
8 441 8 918 106 171 0.0 0.5 0.5 47.1 40.4 0.0 0 48
9 434 8 812 101 197 0.0 0.5 0.5 53.6 21.0 0.0 0 48
10 426 8 1038 121 181 0.0 0.5 0.5 43.6 27.1 0.0 0 48
11 419 8 898 93 187 0.0 0.5 0.5 45.3 47.8 0.0 0 50
12 411 4 857 94 240 0.0 0.5 0.5 62.7 51.6 0.0 0 44
13 404 8 1043 88 185 0.0 0.5 0.5 54.0 52.8 0.0 0 50
14 397 8 767 94 154 0.0 0.5 0.5 33.8 35.0 0.0 0 50
15 390 8 862 89 183 0.0 0.5 0.5 55.6 29.0 0.0 0 46
16 383 4 798 79 173 0.0 0.5 0.5 57.5 35.3 0.0 0 52
17 376 8 827 100 152 0.0 0.5 0.5 35.3 81.8 0.0 0 50
18 370 8 878 101 208 0.0 0.5 0.5 44.7 46.2 0.0 0 48
19 363 4 921 67 167 0.0 0.5 0.5 57.1 34.7 0.0 0 48
20 357 8 933 93 154 0.0 0.5 0.5 46.5 43.6 0.0 0 52
21 351 8 930 89 147 0.0 0.5 0.5 39.4 36.5 0.0 0 52
22 345 8 951 79 142 0.0 0.5 0.5 32.8 51.3 0.0 0 50
23 339 8 1046 87 207 0.0 0.5 0.5 52.8 61.0 0.0 0 48
24 333 4 989 96 185 0.0 0.5 0.5 45.3 43.3 0.0 0 42
25 327 4 577 86 157 0.0 0.5 0.5 31.1 55.3 0.0 0 52
26 321 8 776 97 174 0.0 0.5 0.5 47.9 62.5 0.0 0 52
27 315 8 850 81 188 0.0 0.5 0.5 45.0 55.2 0.0 0 50
28 310 8 898 97 148 0.0 0.5 0.5 43.0 45.8 0.0 0 48
29 304 8 889 65 173 0.0 0.5 0.5 32.5 41.3 0.0 0 50
30 299 8 858 81 153 0.0 0.5 0.5 44.3 29.2 0.0 0 46
31 294 8 871 82 187 0.0 0.5 0.5 45.7 47.7 0.0 0 48
32 289 8 782 109 173 0.0 0.5 0.5 35.2 57.4 0.0 0 48
33 284 8 743 98 189 0.0 0.6 0.5 41.8 64.3 0.0 0 52
34 279 8 943 90 147 0.0 0.5 0.5 38.6 32.8 0.0 0 48
35 274 8 907 57 166 0.0 0.5 0.5 33.6 51.0 0.0 0 48
36 269 8 900 70 148 0.0 0.5 0.5 45.0 41.4 0.0 0 50
37 264 4 875 106 133 0.0 0.5 0.5 31.7 55.3 0.0 0 52
38 260 8 1023 145 149 0.0 0.6 0.5 28.7 65.0 0.0 0 52
39 255 8 801 151 173 0.0 0.9 0.5 41.7 41.2 0.0 0 48
40 251 8 741 104 159 0.0 0.8 0.5 36.2 47.5 0.0 0 48
41 246 8 828 108 149 0.0 0.5 0.5 34.6 50.9 0.0 0 50
42 242 8 947 128 132 0.0 0.7 0.5 34.2 39.0 0.0 0 50
43 238 8 917 101 142 0.0 0.8 0.5 34.4 50.9 0.0 0 48
44 234 8 761 86 129 0.0 0.5 0.5 42.0 36.4 0.0 0 52
45 229 8 979 106 137 0.0 0.5 0.5 29.2 55.3 0.0 0 50
46 225 8 806 74 130 0.0 0.7 0.5 33.1 65.4 0.0 0 52
47 221 8 971 125 114 0.0 0.5 0.5 31.9 45.6 0.0 0 52
48 218 8 869 125 104 0.0 0.9 0.5 30.0 56.0 0.0 0 48
49 214 8 999 153 140 0.0 0.8 0.5 30.4 46.4 0.0 0 52
50 210 8 798 192 139 0.0 1.0 0.5 28.9 50.0 0.0 0 52
51 206 8 860 125 157 0.0 1.2 0.5 31.5 26.9 0.0 0 52
52 203 8 893 186 127 5.9 0.9 0.5 26.4 42.3 0.0 0 46
53 199 8 863 126 141 0.0 1.2 0.5 32.5 44.4 0.0 0 44
54 196 8 788 97 133 0.0 0.9 0.5 37.5 40.0 0.0 0 50
55 192 8 926 119 116 0.0 0.6 0.5 26.1 55.3 0.0 0 52
56 189 8 789 162 107 0.0 0.8 0.5 25.2 40.4 0.0 0 48
57 186 8 878 107 128 0.0 1.1 0.5 23.1 34.0 0.0 0 52
58 182 8 775 105 122 0.0 0.8 0.5 25.5 57.4 0.0 0 50
59 179 8 747 94 129 0.0 0.7 0.5 34.3 37.3 0.0 0 50
60 176 8 845 96 138 0.0 0.6 0.5 28.3 41.7 0.0 0 52
61 173 8 961 121 110 0.0 0.6 0.5 29.0 52.6 0.0 0 48
62 170 4 911 110 109 0.0 0.9 0.5 33.5 33.3 0.0 0 48
63 167 8 656 109 109 0.0 0.8 0.5 21.9 44.7 0.0 0 52
64 164 8 934 117 105 0.0 0.8 0.5 15.5 50.0 0.0 0 52
65 161 8 972 125 95 0.0 0.8 0.5 24.4 50.0 0.0 0 50
66 158 8 894 125 101 0.0 0.9 0.5 27.2 35.9 0.0 0 52
67 155 8 798 146 129 0.0 1.0 0.5 22.8 58.7 0.0 0 52
68 153 8 901 183 92 0.0 1.1 0.5 23.6 34.5 0.0 0 52
69 150 8 977 197 103 0.0 1.4 0.5 23.6 36.8 0.0 0 52
70 147 8 905 262 93 0.0 1.5 0.5 20.3 63.4 0.0 0 52
71 145 8 995 148 122 0.0 1.9 0.5 20.9 35.3 0.0 0 52
72 142 8 934 230 99 0.0 1.6 0.5 20.0 65.9 0.0 0 52
73 140 8 862 173 100 0.0 1.8 0.5 26.8 46.8 0.0 0 52
74 137 8 924 139 90 0.0 1.7 0.5 16.8 42.5 0.0 0 52
75 135 8 888 168 113 0.0 1.6 0.5 22.9 40.4 0.0 0 52
76 133 8 712 212 84 0.0 1.6 0.5 13.4 46.9 0.0 0 52
77 130 8 868 210 91 0.0 1.7 0.5 17.7 51.2 0.0 0 52
78 128 8 952 307 92 0.0 1.9 0.5 19.7 44.9 0.0 0 50
79 126 8 801 157 107 0.0 2.2 0.5 15.8 39.0 0.0 0 52
80 123 8 849 147 93 0.0 2.1 0.5 15.6 51.4 0.0 0 52
81 121 8 799 154 86 0.0 1.9 0.5 12.2 50.0 0.0 0 52
82 119 8 941 213 82 0.0 1.8 0.5 19.5 41.2 0.0 0 50
83 117 8 751 268 94 0.0 2.0 0.5 20.8 42.6 0.0 0 50
84 115 8 828 198 102 0.0 2.2 0.5 15.5 59.5 0.0 0 52
85 113 8 898 266 123 0.0 2.2 0.5 13.2 85.2 0.0 0 52
86 111 8 943 190 93 0.0 2.4 0.5 19.5 45.1 0.0 0 52
87 109 8 864 183 65 0.0 2.4 0.5 14.9 31.8 0.0 0 52
88 107 8 793 203 93 0.0 2.4 0.5 11.8 35.3 0.0 0 52
89 105 8 752 162 74 1.2 2.4 0.5 13.1 21.4 0.0 0 52
90 103 8 801 149 77 0.0 2.3 0.5 9.7 58.3 0.0 0 52
91 102 8 901 230 99 0.0 2.2 0.5 16.0 25.5 0.0 0 52
92 100 8 826 201 87 0.0 2.4 0.5 12.8 45.7 0.0 0 52
93 98 8 810 196 83 0.0 2.5 0.5 14.0 24.4 0.0 0 52
94 96 8 857 209 68 1.0 2.5 0.5 11.5 27.0 5.1 0 52
95 95 8 771 174 91 0.0 2.6 0.5 10.5 26.5 0.0 0 52
96 93 8 955 210 59 0.0 2.6 0.5 10.0 36.7 0.7 0 52
97 91 8 833 206 53 0.0 2.7 0.5 10.2 19.4 1.4 0 52
98 90 8 888 229 86 0.0 2.8 0.5 8.1 36.0 0.0 0 52
99 88 8 794 186 91 1.0 2.9 0.5 8.3 25.0 0.5 0 52
100 81 8 756 170 72 1.0 2.9 0.5 6.0 23.8 7.0 0 52
101 74 8 791 176 67 0.0 2.9 0.5 4.4 58.3 4.0 0 52
102 67 8 813 213 43 0.0 3.0 0.5 7.0 150.0 4.2 0 52
103 62 8 779 245 39 0.0 3.1 0.5 3.2 16.7 13.0 0 52
104 56 8 767 303 63 0.0 3.2 0.5 4.1 20.0 0.7 0 52
105 52 8 757 270 57 0.0 3.5 0.5 6.4 3.7 0.5 0 52
106 47 8 763 283 41 0.0 3.7 0.5 4.5 0.0 0.0 0 52
107 43 8 768 283 36 0.0 3.7 0.5 2.9 18.2 3.6 0 52
108 39 8 804 283 25 0.0 3.7 0.5 3.1 0.0 6.2 0 52
109 36 8 781 283 24 0.0 3.7 0.5 3.6 6.7 6.7 0 52
110 33 8 738 298 42 0.0 3.7 0.5 3.3 15.4 3.5 0 52
111 30 8 761 298 36 0.0 3.7 0.5 2.2 0.0 4.3 0 52
112 27 8 769 298 37 0.0 3.7 0.5 0.9 0.0 2.2 0 52
113 25 8 745 298 31 0.0 3.7 0.5 1.5 0.0 6.6 0 52
114 23 8 753 298 16 0.0 3.7 0.5 1.3 0.0 2.8 0 52
115 21 8 745 298 11 0.0 3.7 0.5 1.5 0.0 14.0 0 52
116 19 8 747 298 21 0.0 3.7 0.5 2.1 0.0 5.8 0 52
117 13 8 737 298 12 0.0 3.7 0.5 1.0 0.0 10.0 0 52
118 9 8 736 298 4 0.0 3.7 0.5 1.5 0.0 18.5 0 52
119 0 8 739 298 0 0.0 3.7 0.5 1.8 0.0 18.0 0 52
120 0 8 732 298 0 0.0 3.7 0.5 1.2 0.0 21.8 0 52
121 0 8 732 19 -1 0.0 0.0 0.5 0.0 100.0 54.8
Initial Wiring Cost: 645 Final Wiring Cost: 732
############## Percent Wire Cost Reduction: -13
Initial Wire Length: 645 Final Wire Length: 732
************** Percent Wire Length Reduction: -13
Initial Horiz. Wire: 216 Final Horiz. Wire: 147
$$$$$$$$$$$ Percent H-Wire Length Reduction: 32
Initial Vert. Wire: 429 Final Vert. Wire: 585
@@@@@@@@@@@ Percent V-Wire Length Reduction: -36
Before Feeds are Added:
BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET
1 82 -20
2 86 -16
LONGEST Block is:2 Its length is:86
BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET
1 86 -16
2 86 -16
LONGEST Block is:1 Its length is:86
Added: 1 feed-through cells
Removed the cell overlaps --- Will do neighbor interchanges only now
TOTAL INTERCONNECT LENGTH: 994
OVERLAP PENALTY: 0
initialRowControl: 1.650
finalRowControl: 0.300
iter T Wire accept
122 0.001 976 16%
123 0.001 971 0%
124 0.001 971 0%
Total Feed-Alignment Movement (Pass 1): 0
Total Feed-Alignment Movement (Pass 2): 0
Total Feed-Alignment Movement (Pass 3): 0
Total Feed-Alignment Movement (Pass 4): 0
Total Feed-Alignment Movement (Pass 5): 0
Total Feed-Alignment Movement (Pass 6): 0
Total Feed-Alignment Movement (Pass 7): 0
Total Feed-Alignment Movement (Pass 8): 0
The rand generator seed was at globroute() : 987654321
Total Number of Net Segments: 9
Number of Switchable Net Segments: 0
Number of channels: 3
THIS IS THE ORIGINAL NUMBER OF TRACKS: 5
no. of accepted flips: 0
no. of attempted flips: 0
THIS IS THE NUMBER OF TRACKS: 5
FINAL NUMBER OF ROUTING TRACKS: 5
MAX OF CHANNEL: 1 is: 0
MAX OF CHANNEL: 2 is: 4
MAX OF CHANNEL: 3 is: 1
FINAL TOTAL INTERCONNECT LENGTH: 978
FINAL OVERLAP PENALTY: 0 FINAL VALUE OF TOTAL COST IS: 978
MAX NUMBER OF ATTEMPTED FLIPS PER T: 55
cost_scale_factor:3.90616
Number of Feed Thrus: 0
Number of Implicit Feed Thrus: 0
Statistics:
Number of Standard Cells: 10
Number of Pads: 0
Number of Nets: 15
Number of Pins: 46
Usage statistics not available

17
simulators/gem5/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/smred.pin Normal file
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@ -0,0 +1,17 @@
$COUNT_1/$AND2_1/$ND2_1$Z 1 $COUNT_1/$AND2_1/$ND2_1 00#Z 17 52 2 1 0
$COUNT_1/$AND2_1/$ND2_1$Z 1 ACOUNT_1 00#A 15 26 2 -1 0
B7 2 $COUNT_1/$FJK3_2 00#K 25 78 3 -1 0
B7 2 $COUNT_1/$FJK3_2 00#J 23 78 3 -1 0
B7 3 $COUNT_1/$AND2_2/$ND2_1 00#A 9 26 2 -1 0
B7 3 ACOUNT_1 01#Z 17 26 2 -1 0
B6 5 $COUNT_1/$FJK3_1 00#K 25 26 2 -1 0
B6 5 $COUNT_1/$FJK3_1 00#J 23 26 2 -1 0
B6 5 $COUNT_1/$AND2_3/$IV_1 01#Z 7 26 2 -1 0
$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$FJK3_1 01#Q 81 26 2 -1 0
$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$AND2_1/$ND2_1 00#B 19 52 2 1 0
$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$FJK3_2 00#Q 81 52 2 1 0
$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$AND2_2/$ND2_1 01#B 11 26 2 -1 0
$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$ND2_1 00#Z 5 52 2 1 0
$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$IV_1 00#A 5 26 2 -1 0
$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$ND2_1 00#Z 7 52 2 1 0
$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$IV_1 00#A 3 26 2 -1 0

11
simulators/gem5/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/smred.pl1 Normal file
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@ -0,0 +1,11 @@
$COUNT_1/$AND2_4/$IV_1 0 0 4 26 0 1
$COUNT_1/$AND2_3/$IV_1 4 0 8 26 2 1
$COUNT_1/$AND2_2/$ND2_1 8 0 14 26 0 1
ACOUNT_1 14 0 18 26 2 1
twfeed1 18 0 22 26 0 1
$COUNT_1/$FJK3_1 22 0 86 26 0 1
$COUNT_1/$AND2_3/$ND2_1 0 52 6 78 0 2
$COUNT_1/$AND2_4/$ND2_1 6 52 12 78 2 2
$COUNT_1/$AND2_2/$IV_1 12 52 16 78 2 2
$COUNT_1/$AND2_1/$ND2_1 16 52 22 78 2 2
$COUNT_1/$FJK3_2 22 52 86 78 0 2

2
simulators/gem5/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/smred.pl2 Normal file
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@ -0,0 +1,2 @@
1 0 0 86 26 0 0
2 0 52 86 78 0 0

18
simulators/gem5/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/smred.sav Normal file
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@ -0,0 +1,18 @@
0.009592
121
0
1
0.000000
0.500000
3.906156
1
1 1 2 37 13
2 2 0 34 65
3 2 2 63 65
4 1 0 59 13
5 1 2 32 13
6 2 0 23 65
7 1 2 12 13
8 2 0 6 65
9 1 0 70 13
10 2 0 70 65

Some files were not shown because too many files have changed in this diff Show More