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Adding gem5 source to svn.

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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1819 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
This commit is contained in:
friemel
2012-10-24 19:18:57 +00:00
parent f7ff71bd46
commit b41eec3f65
3222 changed files with 658579 additions and 1 deletions
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231
simulators/gem5/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini Normal file
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[root]
type=Root
children=system
full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
boot_osflags=a
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
readfile=
symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.cpu]
type=InOrderCPU
children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
BTBEntries=4096
BTBTagSize=16
RASSize=16
activity=0
cachePorts=2
checker=Null
choiceCtrBits=2
choicePredictorSize=8192
clock=500
cpu_id=0
defer_registration=false
div16Latency=1
div16RepeatRate=1
div24Latency=1
div24RepeatRate=1
div32Latency=1
div32RepeatRate=1
div8Latency=1
div8RepeatRate=1
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
fetchBuffSize=4
functionTrace=false
functionTraceStart=0
function_trace=false
function_trace_start=0
globalCtrBits=2
globalHistoryBits=13
globalPredictorSize=8192
instShiftAmt=2
interrupts=system.cpu.interrupts
itb=system.cpu.itb
localCtrBits=2
localHistoryBits=11
localHistoryTableSize=2048
localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
memBlockSize=64
multLatency=1
multRepeatRate=1
numThreads=1
phase=0
predType=tournament
profile=0
progress_interval=0
stageTracing=false
stageWidth=4
system=system
threadModel=SMT
tracer=system.cpu.tracer
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=262144
subblock_size=0
system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
[system.cpu.dtb]
type=AlphaTLB
size=64
[system.cpu.icache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=131072
subblock_size=0
system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.interrupts]
type=AlphaInterrupts
[system.cpu.itb]
type=AlphaTLB
size=48
[system.cpu.l2cache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=false
latency=10000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=2097152
subblock_size=0
system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
[system.cpu.toL2Bus]
type=CoherentBus
block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=bzip2 input.source 1
cwd=build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/inorder-timing
egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2
gid=100
input=cin
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=0
system=system
uid=100
[system.membus]
type=CoherentBus
block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
master=system.physmem.port[0]
slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=SimpleMemory
conf_table_reported=false
file=
in_addr_map=true
latency=30000
latency_var=0
null=false
range=0:134217727
zero=false
port=system.membus.master[0]

6
simulators/gem5/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simerr Executable file
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warn: Sockets disabled, not accepting gdb connections
warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
hack: be nice to actually delete the event here

26
simulators/gem5/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simout Executable file
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gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 4 2012 11:50:11
gem5 started Jun 4 2012 13:44:37
gem5 executing on zizzer
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/inorder-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
info: Increasing stack size by one page.
spec_init
Loading Input Data
Input data 1048576 bytes in length
Compressing Input Data, level 7
Compressed data 198546 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Compressing Input Data, level 9
Compressed data 198677 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
Exiting @ tick 1009998808500 because target called exit()

466
simulators/gem5/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt Normal file
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---------- Begin Simulation Statistics ----------
sim_seconds 1.009999 # Number of seconds simulated
sim_ticks 1009998808500 # Number of ticks simulated
final_tick 1009998808500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 98665 # Simulator instruction rate (inst/s)
host_op_rate 98665 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 54760444 # Simulator tick rate (ticks/s)
host_mem_usage 215204 # Number of bytes of host memory used
host_seconds 18443.95 # Real time elapsed on the host
sim_insts 1819780127 # Number of instructions simulated
sim_ops 1819780127 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 54976 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 172563072 # Number of bytes read from this memory
system.physmem.bytes_read::total 172618048 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 54976 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 54976 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 74938304 # Number of bytes written to this memory
system.physmem.bytes_written::total 74938304 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 859 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 2696298 # Number of read requests responded to by this memory
system.physmem.num_reads::total 2697157 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 1170911 # Number of write requests responded to by this memory
system.physmem.num_writes::total 1170911 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 54432 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 170854728 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 170909160 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 54432 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 54432 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 74196428 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 74196428 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 74196428 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 54432 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 170854728 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 245105588 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 444614444 # DTB read hits
system.cpu.dtb.read_misses 4897078 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 449511522 # DTB read accesses
system.cpu.dtb.write_hits 160920906 # DTB write hits
system.cpu.dtb.write_misses 1701304 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 162622210 # DTB write accesses
system.cpu.dtb.data_hits 605535350 # DTB hits
system.cpu.dtb.data_misses 6598382 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 612133732 # DTB accesses
system.cpu.itb.fetch_hits 231980230 # ITB hits
system.cpu.itb.fetch_misses 22 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 231980252 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 29 # Number of system calls
system.cpu.numCycles 2019997618 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.branch_predictor.lookups 328891112 # Number of BP lookups
system.cpu.branch_predictor.condPredicted 253883187 # Number of conditional branches predicted
system.cpu.branch_predictor.condIncorrect 140042357 # Number of conditional branches incorrect
system.cpu.branch_predictor.BTBLookups 232477361 # Number of BTB lookups
system.cpu.branch_predictor.BTBHits 138151285 # Number of BTB hits
system.cpu.branch_predictor.usedRAS 16767439 # Number of times the RAS was used to get a target.
system.cpu.branch_predictor.RASInCorrect 6 # Number of incorrect RAS predictions.
system.cpu.branch_predictor.BTBHitPct 59.425694 # BTB Hit Percentage
system.cpu.branch_predictor.predictedTaken 175108073 # Number of Branches Predicted As Taken (True).
system.cpu.branch_predictor.predictedNotTaken 153783039 # Number of Branches Predicted As Not Taken (False).
system.cpu.regfile_manager.intRegFileReads 1669728742 # Number of Reads from Int. Register File
system.cpu.regfile_manager.intRegFileWrites 1376202617 # Number of Writes to Int. Register File
system.cpu.regfile_manager.intRegFileAccesses 3045931359 # Total Accesses (Read+Write) to the Int. Register File
system.cpu.regfile_manager.floatRegFileReads 235 # Number of Reads from FP Register File
system.cpu.regfile_manager.floatRegFileWrites 345 # Number of Writes to FP Register File
system.cpu.regfile_manager.floatRegFileAccesses 580 # Total Accesses (Read+Write) to the FP Register File
system.cpu.regfile_manager.regForwards 651109695 # Number of Registers Read Through Forwarding Logic
system.cpu.agen_unit.agens 617989652 # Number of Address Generations
system.cpu.execution_unit.predictedTakenIncorrect 121368305 # Number of Branches Incorrectly Predicted As Taken.
system.cpu.execution_unit.predictedNotTakenIncorrect 12075594 # Number of Branches Incorrectly Predicted As Not Taken).
system.cpu.execution_unit.mispredicted 133443899 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.predicted 81756170 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.mispredictPct 62.009227 # Percentage of Incorrect Branches Predicts
system.cpu.execution_unit.executions 1139611303 # Number of Instructions Executed.
system.cpu.mult_div_unit.multiplies 75 # Number of Multipy Operations Executed
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
system.cpu.contextSwitches 1 # Number of context switches
system.cpu.threadCycles 1746428176 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
system.cpu.timesIdled 7533729 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 443112454 # Number of cycles cpu's stages were not processed
system.cpu.runCycles 1576885164 # Number of cycles cpu stages are processed.
system.cpu.activity 78.063714 # Percentage of cycles cpu is active
system.cpu.comLoads 444595663 # Number of Load instructions committed
system.cpu.comStores 160728502 # Number of Store instructions committed
system.cpu.comBranches 214632552 # Number of Branches instructions committed
system.cpu.comNops 83736345 # Number of Nop instructions committed
system.cpu.comNonSpec 29 # Number of Non-Speculative instructions committed
system.cpu.comInts 916086844 # Number of Integer instructions committed
system.cpu.comFloats 190 # Number of Floating Point instructions committed
system.cpu.committedInsts 1819780127 # Number of Instructions committed (Per-Thread)
system.cpu.committedOps 1819780127 # Number of Ops committed (Per-Thread)
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
system.cpu.committedInsts_total 1819780127 # Number of Instructions committed (Total)
system.cpu.cpi 1.110023 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.smt_cpi nan # CPI: Total SMT-CPI
system.cpu.cpi_total 1.110023 # CPI: Total CPI of All Threads
system.cpu.ipc 0.900882 # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.smt_ipc nan # IPC: Total SMT-IPC
system.cpu.ipc_total 0.900882 # IPC: Total IPC of All Threads
system.cpu.stage0.idleCycles 829317091 # Number of cycles 0 instructions are processed.
system.cpu.stage0.runCycles 1190680527 # Number of cycles 1+ instructions are processed.
system.cpu.stage0.utilization 58.944650 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage1.idleCycles 1087591326 # Number of cycles 0 instructions are processed.
system.cpu.stage1.runCycles 932406292 # Number of cycles 1+ instructions are processed.
system.cpu.stage1.utilization 46.158782 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage2.idleCycles 1046003601 # Number of cycles 0 instructions are processed.
system.cpu.stage2.runCycles 973994017 # Number of cycles 1+ instructions are processed.
system.cpu.stage2.utilization 48.217582 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage3.idleCycles 1610294122 # Number of cycles 0 instructions are processed.
system.cpu.stage3.runCycles 409703496 # Number of cycles 1+ instructions are processed.
system.cpu.stage3.utilization 20.282375 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage4.idleCycles 997062989 # Number of cycles 0 instructions are processed.
system.cpu.stage4.runCycles 1022934629 # Number of cycles 1+ instructions are processed.
system.cpu.stage4.utilization 50.640388 # Percentage of cycles stage was utilized (processing insts).
system.cpu.icache.replacements 1 # number of replacements
system.cpu.icache.tagsinuse 666.311000 # Cycle average of tags in use
system.cpu.icache.total_refs 231979155 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 859 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 270057.223516 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 666.311000 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.325347 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.325347 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 231979155 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 231979155 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 231979155 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 231979155 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 231979155 # number of overall hits
system.cpu.icache.overall_hits::total 231979155 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 1072 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 1072 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 1072 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 1072 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 1072 # number of overall misses
system.cpu.icache.overall_misses::total 1072 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 58539000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 58539000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 58539000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 58539000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 58539000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 58539000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 231980227 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 231980227 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 231980227 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 231980227 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 231980227 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 231980227 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000005 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000005 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000005 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000005 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000005 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000005 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54607.276119 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 54607.276119 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 54607.276119 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 54607.276119 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 54607.276119 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 54607.276119 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 125500 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 4 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets 31375 # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 213 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 213 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 213 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 213 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 213 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 213 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 859 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 859 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 859 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 859 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 859 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 859 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 45929000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 45929000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 45929000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 45929000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 45929000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 45929000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53467.986030 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53467.986030 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53467.986030 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 53467.986030 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53467.986030 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 53467.986030 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 9107352 # number of replacements
system.cpu.dcache.tagsinuse 4082.536815 # Cycle average of tags in use
system.cpu.dcache.total_refs 595069970 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 9111448 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 65.310143 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 12672189000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 4082.536815 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.996713 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.996713 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 437271423 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 437271423 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 157798547 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 157798547 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 595069970 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 595069970 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 595069970 # number of overall hits
system.cpu.dcache.overall_hits::total 595069970 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 7324240 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 7324240 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 2929955 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 2929955 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 10254195 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 10254195 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 10254195 # number of overall misses
system.cpu.dcache.overall_misses::total 10254195 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 180897499500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 180897499500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 110294932000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 110294932000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 291192431500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 291192431500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 291192431500 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 291192431500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 444595663 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 444595663 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 605324165 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 605324165 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 605324165 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 605324165 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.016474 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.016474 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.018229 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.018229 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.016940 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.016940 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.016940 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.016940 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24698.466940 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 24698.466940 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37643.899650 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 37643.899650 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 28397.395554 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 28397.395554 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 28397.395554 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 28397.395554 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 11000000 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 8092150500 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 2762 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 209020 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 3982.621289 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 38714.718687 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 3058572 # number of writebacks
system.cpu.dcache.writebacks::total 3058572 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 101958 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 101958 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1040789 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 1040789 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 1142747 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 1142747 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 1142747 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 1142747 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222282 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 7222282 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889166 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 1889166 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 9111448 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 9111448 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 9111448 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 9111448 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 156091594000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 156091594000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 59191446500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 59191446500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 215283040500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 215283040500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 215283040500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 215283040500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016245 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016245 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011754 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011754 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.015052 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.015052 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.015052 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.015052 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21612.503361 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 21612.503361 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31332.051551 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31332.051551 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23627.752746 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 23627.752746 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23627.752746 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 23627.752746 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 2686301 # number of replacements
system.cpu.l2cache.tagsinuse 26348.804807 # Cycle average of tags in use
system.cpu.l2cache.total_refs 7564571 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 2710944 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 2.790383 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 224336260000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 10843.214494 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 26.756246 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 15478.834067 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.330909 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.000817 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.472377 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.804102 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.data 5414817 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 5414817 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 3058572 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 3058572 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 1000333 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 1000333 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.data 6415150 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 6415150 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.data 6415150 # number of overall hits
system.cpu.l2cache.overall_hits::total 6415150 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 859 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 1807023 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 1807882 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 889275 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 889275 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 859 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 2696298 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 2697157 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 859 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 2696298 # number of overall misses
system.cpu.l2cache.overall_misses::total 2697157 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 44955000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 94411778000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 94456733000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 46506892000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 46506892000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 44955000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 140918670000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 140963625000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 44955000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 140918670000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 140963625000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 859 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 7221840 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 7222699 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 3058572 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 3058572 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1889608 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 1889608 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 859 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 9111448 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 9112307 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 859 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 9111448 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 9112307 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.250216 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.250306 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.470613 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.470613 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.295924 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.295991 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.295924 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.295991 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52334.109430 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52247.136865 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52247.178190 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52297.536757 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52297.536757 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52334.109430 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52263.759421 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 52263.781827 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52334.109430 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52263.759421 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 52263.781827 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 580500 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 70 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 8292.857143 # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks 1170911 # number of writebacks
system.cpu.l2cache.writebacks::total 1170911 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 859 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1807023 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 1807882 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 889275 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 889275 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 859 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 2696298 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 2697157 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 859 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 2696298 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 2697157 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 34480500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 72319844500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 72354325000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 35671150000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 35671150000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 34480500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 107990994500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 108025475000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 34480500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 107990994500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 108025475000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250216 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.250306 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.470613 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.470613 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.295924 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.295991 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.295924 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.295991 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40140.279395 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40021.540678 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40021.597095 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40112.619831 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40112.619831 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40140.279395 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40051.579796 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40051.608045 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40140.279395 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40051.579796 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40051.608045 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

529
simulators/gem5/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini Normal file
View File

@ -0,0 +1,529 @@
[root]
type=Root
children=system
full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
boot_osflags=a
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
readfile=
symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.cpu]
type=DerivO3CPU
children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
LSQDepCheckShift=4
RASSize=16
SQEntries=32
SSITSize=1024
activity=0
backComSize=5
cachePorts=200
checker=Null
choiceCtrBits=2
choicePredictorSize=8192
clock=500
commitToDecodeDelay=1
commitToFetchDelay=1
commitToIEWDelay=1
commitToRenameDelay=1
commitWidth=8
cpu_id=0
decodeToFetchDelay=1
decodeToRenameDelay=1
decodeWidth=8
defer_registration=false
dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
fetchToDecodeDelay=1
fetchTrapLatency=1
fetchWidth=8
forwardComSize=5
fuPool=system.cpu.fuPool
function_trace=false
function_trace_start=0
globalCtrBits=2
globalHistoryBits=13
globalPredictorSize=8192
iewToCommitDelay=1
iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
instShiftAmt=2
interrupts=system.cpu.interrupts
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
localCtrBits=2
localHistoryBits=11
localHistoryTableSize=2048
localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
needsTSO=false
numIQEntries=64
numPhysFloatRegs=256
numPhysIntRegs=256
numROBEntries=192
numRobs=1
numThreads=1
phase=0
predType=tournament
profile=0
progress_interval=0
renameToDecodeDelay=1
renameToFetchDelay=1
renameToIEWDelay=2
renameToROBDelay=1
renameWidth=8
smtCommitPolicy=RoundRobin
smtFetchPolicy=SingleThread
smtIQPolicy=Partitioned
smtIQThreshold=100
smtLSQPolicy=Partitioned
smtLSQThreshold=100
smtNumFetchingThreads=1
smtROBPolicy=Partitioned
smtROBThreshold=100
squashWidth=8
store_set_clear_period=250000
system=system
tracer=system.cpu.tracer
trapLatency=13
wbDepth=1
wbWidth=8
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=262144
subblock_size=0
system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
[system.cpu.dtb]
type=AlphaTLB
size=64
[system.cpu.fuPool]
type=FUPool
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
[system.cpu.fuPool.FUList0]
type=FUDesc
children=opList
count=6
opList=system.cpu.fuPool.FUList0.opList
[system.cpu.fuPool.FUList0.opList]
type=OpDesc
issueLat=1
opClass=IntAlu
opLat=1
[system.cpu.fuPool.FUList1]
type=FUDesc
children=opList0 opList1
count=2
opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
[system.cpu.fuPool.FUList1.opList0]
type=OpDesc
issueLat=1
opClass=IntMult
opLat=3
[system.cpu.fuPool.FUList1.opList1]
type=OpDesc
issueLat=19
opClass=IntDiv
opLat=20
[system.cpu.fuPool.FUList2]
type=FUDesc
children=opList0 opList1 opList2
count=4
opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
[system.cpu.fuPool.FUList2.opList0]
type=OpDesc
issueLat=1
opClass=FloatAdd
opLat=2
[system.cpu.fuPool.FUList2.opList1]
type=OpDesc
issueLat=1
opClass=FloatCmp
opLat=2
[system.cpu.fuPool.FUList2.opList2]
type=OpDesc
issueLat=1
opClass=FloatCvt
opLat=2
[system.cpu.fuPool.FUList3]
type=FUDesc
children=opList0 opList1 opList2
count=2
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
[system.cpu.fuPool.FUList3.opList0]
type=OpDesc
issueLat=1
opClass=FloatMult
opLat=4
[system.cpu.fuPool.FUList3.opList1]
type=OpDesc
issueLat=12
opClass=FloatDiv
opLat=12
[system.cpu.fuPool.FUList3.opList2]
type=OpDesc
issueLat=24
opClass=FloatSqrt
opLat=24
[system.cpu.fuPool.FUList4]
type=FUDesc
children=opList
count=0
opList=system.cpu.fuPool.FUList4.opList
[system.cpu.fuPool.FUList4.opList]
type=OpDesc
issueLat=1
opClass=MemRead
opLat=1
[system.cpu.fuPool.FUList5]
type=FUDesc
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
count=4
opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
[system.cpu.fuPool.FUList5.opList00]
type=OpDesc
issueLat=1
opClass=SimdAdd
opLat=1
[system.cpu.fuPool.FUList5.opList01]
type=OpDesc
issueLat=1
opClass=SimdAddAcc
opLat=1
[system.cpu.fuPool.FUList5.opList02]
type=OpDesc
issueLat=1
opClass=SimdAlu
opLat=1
[system.cpu.fuPool.FUList5.opList03]
type=OpDesc
issueLat=1
opClass=SimdCmp
opLat=1
[system.cpu.fuPool.FUList5.opList04]
type=OpDesc
issueLat=1
opClass=SimdCvt
opLat=1
[system.cpu.fuPool.FUList5.opList05]
type=OpDesc
issueLat=1
opClass=SimdMisc
opLat=1
[system.cpu.fuPool.FUList5.opList06]
type=OpDesc
issueLat=1
opClass=SimdMult
opLat=1
[system.cpu.fuPool.FUList5.opList07]
type=OpDesc
issueLat=1
opClass=SimdMultAcc
opLat=1
[system.cpu.fuPool.FUList5.opList08]
type=OpDesc
issueLat=1
opClass=SimdShift
opLat=1
[system.cpu.fuPool.FUList5.opList09]
type=OpDesc
issueLat=1
opClass=SimdShiftAcc
opLat=1
[system.cpu.fuPool.FUList5.opList10]
type=OpDesc
issueLat=1
opClass=SimdSqrt
opLat=1
[system.cpu.fuPool.FUList5.opList11]
type=OpDesc
issueLat=1
opClass=SimdFloatAdd
opLat=1
[system.cpu.fuPool.FUList5.opList12]
type=OpDesc
issueLat=1
opClass=SimdFloatAlu
opLat=1
[system.cpu.fuPool.FUList5.opList13]
type=OpDesc
issueLat=1
opClass=SimdFloatCmp
opLat=1
[system.cpu.fuPool.FUList5.opList14]
type=OpDesc
issueLat=1
opClass=SimdFloatCvt
opLat=1
[system.cpu.fuPool.FUList5.opList15]
type=OpDesc
issueLat=1
opClass=SimdFloatDiv
opLat=1
[system.cpu.fuPool.FUList5.opList16]
type=OpDesc
issueLat=1
opClass=SimdFloatMisc
opLat=1
[system.cpu.fuPool.FUList5.opList17]
type=OpDesc
issueLat=1
opClass=SimdFloatMult
opLat=1
[system.cpu.fuPool.FUList5.opList18]
type=OpDesc
issueLat=1
opClass=SimdFloatMultAcc
opLat=1
[system.cpu.fuPool.FUList5.opList19]
type=OpDesc
issueLat=1
opClass=SimdFloatSqrt
opLat=1
[system.cpu.fuPool.FUList6]
type=FUDesc
children=opList
count=0
opList=system.cpu.fuPool.FUList6.opList
[system.cpu.fuPool.FUList6.opList]
type=OpDesc
issueLat=1
opClass=MemWrite
opLat=1
[system.cpu.fuPool.FUList7]
type=FUDesc
children=opList0 opList1
count=4
opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
[system.cpu.fuPool.FUList7.opList0]
type=OpDesc
issueLat=1
opClass=MemRead
opLat=1
[system.cpu.fuPool.FUList7.opList1]
type=OpDesc
issueLat=1
opClass=MemWrite
opLat=1
[system.cpu.fuPool.FUList8]
type=FUDesc
children=opList
count=1
opList=system.cpu.fuPool.FUList8.opList
[system.cpu.fuPool.FUList8.opList]
type=OpDesc
issueLat=3
opClass=IprAccess
opLat=3
[system.cpu.icache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=131072
subblock_size=0
system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.interrupts]
type=AlphaInterrupts
[system.cpu.itb]
type=AlphaTLB
size=48
[system.cpu.l2cache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=false
latency=1000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=2097152
subblock_size=0
system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
[system.cpu.toL2Bus]
type=CoherentBus
block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=bzip2 input.source 1
cwd=build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing
egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2
gid=100
input=cin
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=0
system=system
uid=100
[system.membus]
type=CoherentBus
block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
master=system.physmem.port[0]
slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=SimpleMemory
conf_table_reported=false
file=
in_addr_map=true
latency=30000
latency_var=0
null=false
range=0:134217727
zero=false
port=system.membus.master[0]

6
simulators/gem5/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simerr Executable file
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@ -0,0 +1,6 @@
warn: Sockets disabled, not accepting gdb connections
warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
hack: be nice to actually delete the event here

26
simulators/gem5/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout Executable file
View File

@ -0,0 +1,26 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 4 2012 11:50:11
gem5 started Jun 4 2012 13:48:46
gem5 executing on zizzer
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
info: Increasing stack size by one page.
spec_init
Loading Input Data
Input data 1048576 bytes in length
Compressing Input Data, level 7
Compressed data 198546 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Compressing Input Data, level 9
Compressed data 198677 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
Exiting @ tick 614317285000 because target called exit()

690
simulators/gem5/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt Normal file
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@ -0,0 +1,690 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.614317 # Number of seconds simulated
sim_ticks 614317285000 # Number of ticks simulated
final_tick 614317285000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 134863 # Simulator instruction rate (inst/s)
host_op_rate 134863 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 47722573 # Simulator tick rate (ticks/s)
host_mem_usage 216172 # Number of bytes of host memory used
host_seconds 12872.68 # Real time elapsed on the host
sim_insts 1736043781 # Number of instructions simulated
sim_ops 1736043781 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 62784 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 173186944 # Number of bytes read from this memory
system.physmem.bytes_read::total 173249728 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 62784 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 62784 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 75020608 # Number of bytes written to this memory
system.physmem.bytes_written::total 75020608 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 981 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 2706046 # Number of read requests responded to by this memory
system.physmem.num_reads::total 2707027 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 1172197 # Number of write requests responded to by this memory
system.physmem.num_writes::total 1172197 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 102201 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 281917745 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 282019947 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 102201 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 102201 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 122120295 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 122120295 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 122120295 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 102201 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 281917745 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 404140242 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 613430411 # DTB read hits
system.cpu.dtb.read_misses 10984160 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 624414571 # DTB read accesses
system.cpu.dtb.write_hits 208466528 # DTB write hits
system.cpu.dtb.write_misses 6835381 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 215301909 # DTB write accesses
system.cpu.dtb.data_hits 821896939 # DTB hits
system.cpu.dtb.data_misses 17819541 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 839716480 # DTB accesses
system.cpu.itb.fetch_hits 401793450 # ITB hits
system.cpu.itb.fetch_misses 51 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 401793501 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 29 # Number of system calls
system.cpu.numCycles 1228634571 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.BPredUnit.lookups 381761173 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 293769294 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 18987814 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 267293652 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 262906896 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 25187123 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 6338 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 413237757 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 3162516337 # Number of instructions fetch has processed
system.cpu.fetch.Branches 381761173 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 288094019 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 577364277 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 136217023 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 121997880 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 29 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 1099 # Number of stall cycles due to pending traps
system.cpu.fetch.CacheLines 401793450 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 10461001 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 1223060627 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.585740 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.163188 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 645696350 52.79% 52.79% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 43491890 3.56% 56.35% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 22343235 1.83% 58.18% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 40947227 3.35% 61.52% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 127434510 10.42% 71.94% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 63845944 5.22% 77.16% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 40777509 3.33% 80.50% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 30328214 2.48% 82.98% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 208195748 17.02% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 1223060627 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.310720 # Number of branch fetches per cycle
system.cpu.fetch.rate 2.574009 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 442798352 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 107558051 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 546235232 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 16010373 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 110458619 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 60401844 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 1104 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 3083471433 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 2212 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 110458619 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 464144259 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 59142722 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 6290 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 539650759 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 49657978 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 3001214428 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 543640 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 1796675 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 45123611 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenamedOperands 2245055787 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 3876991628 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 3875592361 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 1399267 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 1376202963 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 868852824 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 246 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 246 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 105587598 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 677972013 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 251679590 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 61268278 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 33927488 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 2695905085 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 208 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 2494910980 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 3371495 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 947658243 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 400911726 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 179 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 1223060627 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 2.039892 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.968690 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 388423198 31.76% 31.76% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 198296660 16.21% 47.97% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 183821950 15.03% 63.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 153332369 12.54% 75.54% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 135876340 11.11% 86.65% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 79653803 6.51% 93.16% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 63718799 5.21% 98.37% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 14613920 1.19% 99.56% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 5323588 0.44% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 1223060627 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 2019639 10.76% 10.76% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 10.76% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 10.76% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 10.76% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 10.76% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 10.76% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 10.76% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 10.76% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 10.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 10.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 10.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 10.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 10.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 10.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 10.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 10.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 10.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 10.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 10.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 10.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 10.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 10.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 10.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 10.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 10.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 10.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 10.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 10.76% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 12227310 65.14% 75.90% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 4524424 24.10% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 1630534588 65.35% 65.35% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 93 0.00% 65.35% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.35% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 292 0.00% 65.35% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 16 0.00% 65.35% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 176 0.00% 65.35% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 34 0.00% 65.35% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 24 0.00% 65.35% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.35% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 642000765 25.73% 91.09% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 222374992 8.91% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 2494910980 # Type of FU issued
system.cpu.iq.rate 2.030637 # Inst issue rate
system.cpu.iq.fu_busy_cnt 18771373 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.007524 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 6233033546 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 3642313752 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 2391820907 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 1991909 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 1355027 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 871735 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 2512703438 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 978915 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 57347014 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 233376350 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 247116 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 107150 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 90951088 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 227 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 162717 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 110458619 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 22362549 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 1121439 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 2838563958 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 17898504 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 677972013 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 251679590 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 208 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 216005 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 15651 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 107150 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 13325619 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 8884381 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 22210000 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 2442758638 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 624415478 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 52152342 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 142658665 # number of nop insts executed
system.cpu.iew.exec_refs 839717432 # number of memory reference insts executed
system.cpu.iew.exec_branches 299305457 # Number of branches executed
system.cpu.iew.exec_stores 215301954 # Number of stores executed
system.cpu.iew.exec_rate 1.988190 # Inst execution rate
system.cpu.iew.wb_sent 2421432535 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 2392692642 # cumulative count of insts written-back
system.cpu.iew.wb_producers 1370537618 # num instructions producing a value
system.cpu.iew.wb_consumers 1736169101 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 1.947440 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.789403 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitCommittedInsts 1819780126 # The number of committed instructions
system.cpu.commit.commitCommittedOps 1819780126 # The number of committed instructions
system.cpu.commit.commitSquashedInsts 782630603 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 18986848 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 1112602008 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.635607 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.507788 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 589258835 52.96% 52.96% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 179628091 16.14% 69.11% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 90469983 8.13% 77.24% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 53793341 4.83% 82.07% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 36407733 3.27% 85.35% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 27937238 2.51% 87.86% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 22627047 2.03% 89.89% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 23085278 2.07% 91.97% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 89394462 8.03% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 1112602008 # Number of insts commited each cycle
system.cpu.commit.committedInsts 1819780126 # Number of instructions committed
system.cpu.commit.committedOps 1819780126 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 605324165 # Number of memory references committed
system.cpu.commit.loads 444595663 # Number of loads committed
system.cpu.commit.membars 0 # Number of memory barriers committed
system.cpu.commit.branches 214632552 # Number of branches committed
system.cpu.commit.fp_insts 805525 # Number of committed floating point instructions.
system.cpu.commit.int_insts 1718967519 # Number of committed integer instructions.
system.cpu.commit.function_calls 16767440 # Number of function calls committed.
system.cpu.commit.bw_lim_events 89394462 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 3539839075 # The number of ROB reads
system.cpu.rob.rob_writes 5315403238 # The number of ROB writes
system.cpu.timesIdled 405378 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 5573944 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 1736043781 # Number of Instructions Simulated
system.cpu.committedOps 1736043781 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 1736043781 # Number of Instructions Simulated
system.cpu.cpi 0.707721 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.707721 # CPI: Total CPI of All Threads
system.cpu.ipc 1.412986 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.412986 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 3284485483 # number of integer regfile reads
system.cpu.int_regfile_writes 1919152187 # number of integer regfile writes
system.cpu.fp_regfile_reads 52475 # number of floating regfile reads
system.cpu.fp_regfile_writes 577 # number of floating regfile writes
system.cpu.misc_regfile_reads 25 # number of misc regfile reads
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
system.cpu.icache.replacements 1 # number of replacements
system.cpu.icache.tagsinuse 800.240430 # Cycle average of tags in use
system.cpu.icache.total_refs 401791975 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 981 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 409573.878695 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 800.240430 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.390742 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.390742 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 401791975 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 401791975 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 401791975 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 401791975 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 401791975 # number of overall hits
system.cpu.icache.overall_hits::total 401791975 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 1475 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 1475 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 1475 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 1475 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 1475 # number of overall misses
system.cpu.icache.overall_misses::total 1475 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 50482500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 50482500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 50482500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 50482500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 50482500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 50482500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 401793450 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 401793450 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 401793450 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 401793450 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 401793450 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 401793450 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34225.423729 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 34225.423729 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 34225.423729 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 34225.423729 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 34225.423729 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 34225.423729 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 494 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 494 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 494 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 494 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 494 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 494 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 981 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 981 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 981 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 981 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 981 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 981 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 34897000 # number of ReadReq MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_latency::total 34897000 # number of overall MSHR miss cycles
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system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35572.884811 # average overall mshr miss latency
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 20476.218184 # average WriteReq mshr miss latency
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system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 35500 # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 35500 # average LoadLockedReq mshr miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13062.121566 # average overall mshr miss latency
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system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 84423852000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 84454420000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 30568000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 84423852000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 84454420000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250005 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.250106 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.468092 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.468092 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.294753 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.294828 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.294753 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.294828 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31160.040775 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31161.925712 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31161.924699 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31273.347207 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31273.347207 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31160.040775 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31198.232403 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31198.218562 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31160.040775 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31198.232403 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31198.218562 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

117
simulators/gem5/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini Normal file
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[root]
type=Root
children=system
full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
boot_osflags=a
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
readfile=
symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.cpu]
type=AtomicSimpleCPU
children=dtb interrupts itb tracer workload
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
fastmem=false
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
phase=0
profile=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
system=system
tracer=system.cpu.tracer
width=1
workload=system.cpu.workload
dcache_port=system.membus.slave[2]
icache_port=system.membus.slave[1]
[system.cpu.dtb]
type=AlphaTLB
size=64
[system.cpu.interrupts]
type=AlphaInterrupts
[system.cpu.itb]
type=AlphaTLB
size=48
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=bzip2 input.source 1
cwd=build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/simple-atomic
egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2
gid=100
input=cin
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=0
system=system
uid=100
[system.membus]
type=CoherentBus
block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
master=system.physmem.port[0]
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
[system.physmem]
type=SimpleMemory
conf_table_reported=false
file=
in_addr_map=true
latency=30000
latency_var=0
null=false
range=0:134217727
zero=false
port=system.membus.master[0]

7
simulators/gem5/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/simerr Executable file
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@ -0,0 +1,7 @@
warn: CoherentBus system.membus has no snooping ports attached!
warn: Sockets disabled, not accepting gdb connections
warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
hack: be nice to actually delete the event here

26
simulators/gem5/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/simout Executable file
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@ -0,0 +1,26 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 4 2012 11:50:11
gem5 started Jun 4 2012 14:21:33
gem5 executing on zizzer
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
info: Increasing stack size by one page.
spec_init
Loading Input Data
Input data 1048576 bytes in length
Compressing Input Data, level 7
Compressed data 198546 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Compressing Input Data, level 9
Compressed data 198677 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
Exiting @ tick 913189263000 because target called exit()

92
simulators/gem5/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt Normal file
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@ -0,0 +1,92 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.913189 # Number of seconds simulated
sim_ticks 913189263000 # Number of ticks simulated
final_tick 913189263000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 3414010 # Simulator instruction rate (inst/s)
host_op_rate 3414010 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1713194291 # Simulator tick rate (ticks/s)
host_mem_usage 206032 # Number of bytes of host memory used
host_seconds 533.03 # Real time elapsed on the host
sim_insts 1819780127 # Number of instructions simulated
sim_ops 1819780127 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 7305514036 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 1974795935 # Number of bytes read from this memory
system.physmem.bytes_read::total 9280309971 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 7305514036 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 7305514036 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 827777307 # Number of bytes written to this memory
system.physmem.bytes_written::total 827777307 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 1826378509 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 444595663 # Number of read requests responded to by this memory
system.physmem.num_reads::total 2270974172 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 160728502 # Number of write requests responded to by this memory
system.physmem.num_writes::total 160728502 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 7999999926 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 2162526450 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 10162526375 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 7999999926 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 7999999926 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 906468506 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 906468506 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 7999999926 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 3068994956 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 11068994882 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 444595663 # DTB read hits
system.cpu.dtb.read_misses 4897078 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 449492741 # DTB read accesses
system.cpu.dtb.write_hits 160728502 # DTB write hits
system.cpu.dtb.write_misses 1701304 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 162429806 # DTB write accesses
system.cpu.dtb.data_hits 605324165 # DTB hits
system.cpu.dtb.data_misses 6598382 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 611922547 # DTB accesses
system.cpu.itb.fetch_hits 1826378509 # ITB hits
system.cpu.itb.fetch_misses 18 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 1826378527 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 29 # Number of system calls
system.cpu.numCycles 1826378527 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 1819780127 # Number of instructions committed
system.cpu.committedOps 1819780127 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 1725565901 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 805526 # Number of float alu accesses
system.cpu.num_func_calls 33534877 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 164021647 # number of instructions that are conditional controls
system.cpu.num_int_insts 1725565901 # number of integer instructions
system.cpu.num_fp_insts 805526 # number of float instructions
system.cpu.num_int_register_reads 2347934659 # number of times the integer registers were read
system.cpu.num_int_register_writes 1376202618 # number of times the integer registers were written
system.cpu.num_fp_register_reads 357 # number of times the floating registers were read
system.cpu.num_fp_register_writes 345 # number of times the floating registers were written
system.cpu.num_mem_refs 611922547 # number of memory refs
system.cpu.num_load_insts 449492741 # Number of load instructions
system.cpu.num_store_insts 162429806 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 1826378527 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
---------- End Simulation Statistics ----------

198
simulators/gem5/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/config.ini Normal file
View File

@ -0,0 +1,198 @@
[root]
type=Root
children=system
full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
boot_osflags=a
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
readfile=
symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.cpu]
type=TimingSimpleCPU
children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
phase=0
profile=0
progress_interval=0
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=262144
subblock_size=0
system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
[system.cpu.dtb]
type=AlphaTLB
size=64
[system.cpu.icache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=131072
subblock_size=0
system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.interrupts]
type=AlphaInterrupts
[system.cpu.itb]
type=AlphaTLB
size=48
[system.cpu.l2cache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=false
latency=10000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=2097152
subblock_size=0
system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
[system.cpu.toL2Bus]
type=CoherentBus
block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=bzip2 input.source 1
cwd=build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/simple-timing
egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2
gid=100
input=cin
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=0
system=system
uid=100
[system.membus]
type=CoherentBus
block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
master=system.physmem.port[0]
slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=SimpleMemory
conf_table_reported=false
file=
in_addr_map=true
latency=30000
latency_var=0
null=false
range=0:134217727
zero=false
port=system.membus.master[0]

6
simulators/gem5/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simerr Executable file
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@ -0,0 +1,6 @@
warn: Sockets disabled, not accepting gdb connections
warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
hack: be nice to actually delete the event here

26
simulators/gem5/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simout Executable file
View File

@ -0,0 +1,26 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 4 2012 11:50:11
gem5 started Jun 4 2012 13:42:46
gem5 executing on zizzer
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
info: Increasing stack size by one page.
spec_init
Loading Input Data
Input data 1048576 bytes in length
Compressing Input Data, level 7
Compressed data 198546 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Compressing Input Data, level 9
Compressed data 198677 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
Exiting @ tick 2663443716000 because target called exit()

406
simulators/gem5/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt Normal file
View File

@ -0,0 +1,406 @@
---------- Begin Simulation Statistics ----------
sim_seconds 2.663444 # Number of seconds simulated
sim_ticks 2663443716000 # Number of ticks simulated
final_tick 2663443716000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1479188 # Simulator instruction rate (inst/s)
host_op_rate 1479188 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 2164950496 # Simulator tick rate (ticks/s)
host_mem_usage 214896 # Number of bytes of host memory used
host_seconds 1230.26 # Real time elapsed on the host
sim_insts 1819780127 # Number of instructions simulated
sim_ops 1819780127 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 51328 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 172562880 # Number of bytes read from this memory
system.physmem.bytes_read::total 172614208 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 51328 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 51328 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 74939072 # Number of bytes written to this memory
system.physmem.bytes_written::total 74939072 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 802 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 2696295 # Number of read requests responded to by this memory
system.physmem.num_reads::total 2697097 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 1170923 # Number of write requests responded to by this memory
system.physmem.num_writes::total 1170923 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 19271 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 64789385 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 64808656 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 19271 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 19271 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 28136158 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 28136158 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 28136158 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 19271 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 64789385 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 92944814 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 444595663 # DTB read hits
system.cpu.dtb.read_misses 4897078 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 449492741 # DTB read accesses
system.cpu.dtb.write_hits 160728502 # DTB write hits
system.cpu.dtb.write_misses 1701304 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 162429806 # DTB write accesses
system.cpu.dtb.data_hits 605324165 # DTB hits
system.cpu.dtb.data_misses 6598382 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 611922547 # DTB accesses
system.cpu.itb.fetch_hits 1826378510 # ITB hits
system.cpu.itb.fetch_misses 18 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 1826378528 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
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system.cpu.numCycles 5326887432 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 1819780127 # Number of instructions committed
system.cpu.committedOps 1819780127 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 1725565901 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 805526 # Number of float alu accesses
system.cpu.num_func_calls 33534877 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 164021647 # number of instructions that are conditional controls
system.cpu.num_int_insts 1725565901 # number of integer instructions
system.cpu.num_fp_insts 805526 # number of float instructions
system.cpu.num_int_register_reads 2347934659 # number of times the integer registers were read
system.cpu.num_int_register_writes 1376202618 # number of times the integer registers were written
system.cpu.num_fp_register_reads 357 # number of times the floating registers were read
system.cpu.num_fp_register_writes 345 # number of times the floating registers were written
system.cpu.num_mem_refs 611922547 # number of memory refs
system.cpu.num_load_insts 449492741 # Number of load instructions
system.cpu.num_store_insts 162429806 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 5326887432 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.icache.replacements 1 # number of replacements
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system.cpu.icache.occ_blocks::cpu.inst 612.356766 # Average occupied blocks per requestor
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system.cpu.icache.overall_miss_latency::total 44912000 # number of overall miss cycles
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system.cpu.icache.overall_avg_miss_latency::cpu.inst 56000 # average overall miss latency
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system.cpu.icache.overall_mshr_miss_latency::total 42506000 # number of overall MSHR miss cycles
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system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53000 # average ReadReq mshr miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
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system.cpu.dcache.tagsinuse 4079.504248 # Cycle average of tags in use
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system.cpu.dcache.sampled_refs 9111734 # Sample count of references to valid blocks.
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system.cpu.dcache.warmup_cycle 40989969000 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.overall_mshr_miss_latency::total 213473464000 # number of overall MSHR miss cycles
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21508.481513 # average ReadReq mshr miss latency
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30767.845574 # average WriteReq mshr miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23428.412638 # average overall mshr miss latency
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system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks 1170923 # number of writebacks
system.cpu.l2cache.writebacks::total 1170923 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 802 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1807062 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 1807864 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 889233 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 889233 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 802 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 2696295 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 2697097 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 802 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 2696295 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 2697097 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 32080000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 72282480000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 72314560000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 35569320000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 35569320000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 32080000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 107851800000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 107883880000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 32080000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 107851800000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 107883880000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250202 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.250285 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.470663 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.470663 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.295915 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.295977 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.295915 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.295977 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

547
simulators/gem5/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini Normal file
View File

@ -0,0 +1,547 @@
[root]
type=Root
children=system
full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
boot_osflags=a
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
readfile=
symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.cpu]
type=DerivO3CPU
children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
LSQDepCheckShift=4
RASSize=16
SQEntries=32
SSITSize=1024
activity=0
backComSize=5
cachePorts=200
checker=Null
choiceCtrBits=2
choicePredictorSize=8192
clock=500
commitToDecodeDelay=1
commitToFetchDelay=1
commitToIEWDelay=1
commitToRenameDelay=1
commitWidth=8
cpu_id=0
decodeToFetchDelay=1
decodeToRenameDelay=1
decodeWidth=8
defer_registration=false
dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
fetchToDecodeDelay=1
fetchTrapLatency=1
fetchWidth=8
forwardComSize=5
fuPool=system.cpu.fuPool
function_trace=false
function_trace_start=0
globalCtrBits=2
globalHistoryBits=13
globalPredictorSize=8192
iewToCommitDelay=1
iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
instShiftAmt=2
interrupts=system.cpu.interrupts
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
localCtrBits=2
localHistoryBits=11
localHistoryTableSize=2048
localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
needsTSO=false
numIQEntries=64
numPhysFloatRegs=256
numPhysIntRegs=256
numROBEntries=192
numRobs=1
numThreads=1
phase=0
predType=tournament
profile=0
progress_interval=0
renameToDecodeDelay=1
renameToFetchDelay=1
renameToIEWDelay=2
renameToROBDelay=1
renameWidth=8
smtCommitPolicy=RoundRobin
smtFetchPolicy=SingleThread
smtIQPolicy=Partitioned
smtIQThreshold=100
smtLSQPolicy=Partitioned
smtLSQThreshold=100
smtNumFetchingThreads=1
smtROBPolicy=Partitioned
smtROBThreshold=100
squashWidth=8
store_set_clear_period=250000
system=system
tracer=system.cpu.tracer
trapLatency=13
wbDepth=1
wbWidth=8
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=262144
subblock_size=0
system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
[system.cpu.dtb]
type=ArmTLB
children=walker
size=64
walker=system.cpu.dtb.walker
[system.cpu.dtb.walker]
type=ArmTableWalker
max_backoff=100000
min_backoff=0
sys=system
port=system.cpu.toL2Bus.slave[3]
[system.cpu.fuPool]
type=FUPool
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
[system.cpu.fuPool.FUList0]
type=FUDesc
children=opList
count=6
opList=system.cpu.fuPool.FUList0.opList
[system.cpu.fuPool.FUList0.opList]
type=OpDesc
issueLat=1
opClass=IntAlu
opLat=1
[system.cpu.fuPool.FUList1]
type=FUDesc
children=opList0 opList1
count=2
opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
[system.cpu.fuPool.FUList1.opList0]
type=OpDesc
issueLat=1
opClass=IntMult
opLat=3
[system.cpu.fuPool.FUList1.opList1]
type=OpDesc
issueLat=19
opClass=IntDiv
opLat=20
[system.cpu.fuPool.FUList2]
type=FUDesc
children=opList0 opList1 opList2
count=4
opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
[system.cpu.fuPool.FUList2.opList0]
type=OpDesc
issueLat=1
opClass=FloatAdd
opLat=2
[system.cpu.fuPool.FUList2.opList1]
type=OpDesc
issueLat=1
opClass=FloatCmp
opLat=2
[system.cpu.fuPool.FUList2.opList2]
type=OpDesc
issueLat=1
opClass=FloatCvt
opLat=2
[system.cpu.fuPool.FUList3]
type=FUDesc
children=opList0 opList1 opList2
count=2
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
[system.cpu.fuPool.FUList3.opList0]
type=OpDesc
issueLat=1
opClass=FloatMult
opLat=4
[system.cpu.fuPool.FUList3.opList1]
type=OpDesc
issueLat=12
opClass=FloatDiv
opLat=12
[system.cpu.fuPool.FUList3.opList2]
type=OpDesc
issueLat=24
opClass=FloatSqrt
opLat=24
[system.cpu.fuPool.FUList4]
type=FUDesc
children=opList
count=0
opList=system.cpu.fuPool.FUList4.opList
[system.cpu.fuPool.FUList4.opList]
type=OpDesc
issueLat=1
opClass=MemRead
opLat=1
[system.cpu.fuPool.FUList5]
type=FUDesc
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
count=4
opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
[system.cpu.fuPool.FUList5.opList00]
type=OpDesc
issueLat=1
opClass=SimdAdd
opLat=1
[system.cpu.fuPool.FUList5.opList01]
type=OpDesc
issueLat=1
opClass=SimdAddAcc
opLat=1
[system.cpu.fuPool.FUList5.opList02]
type=OpDesc
issueLat=1
opClass=SimdAlu
opLat=1
[system.cpu.fuPool.FUList5.opList03]
type=OpDesc
issueLat=1
opClass=SimdCmp
opLat=1
[system.cpu.fuPool.FUList5.opList04]
type=OpDesc
issueLat=1
opClass=SimdCvt
opLat=1
[system.cpu.fuPool.FUList5.opList05]
type=OpDesc
issueLat=1
opClass=SimdMisc
opLat=1
[system.cpu.fuPool.FUList5.opList06]
type=OpDesc
issueLat=1
opClass=SimdMult
opLat=1
[system.cpu.fuPool.FUList5.opList07]
type=OpDesc
issueLat=1
opClass=SimdMultAcc
opLat=1
[system.cpu.fuPool.FUList5.opList08]
type=OpDesc
issueLat=1
opClass=SimdShift
opLat=1
[system.cpu.fuPool.FUList5.opList09]
type=OpDesc
issueLat=1
opClass=SimdShiftAcc
opLat=1
[system.cpu.fuPool.FUList5.opList10]
type=OpDesc
issueLat=1
opClass=SimdSqrt
opLat=1
[system.cpu.fuPool.FUList5.opList11]
type=OpDesc
issueLat=1
opClass=SimdFloatAdd
opLat=1
[system.cpu.fuPool.FUList5.opList12]
type=OpDesc
issueLat=1
opClass=SimdFloatAlu
opLat=1
[system.cpu.fuPool.FUList5.opList13]
type=OpDesc
issueLat=1
opClass=SimdFloatCmp
opLat=1
[system.cpu.fuPool.FUList5.opList14]
type=OpDesc
issueLat=1
opClass=SimdFloatCvt
opLat=1
[system.cpu.fuPool.FUList5.opList15]
type=OpDesc
issueLat=1
opClass=SimdFloatDiv
opLat=1
[system.cpu.fuPool.FUList5.opList16]
type=OpDesc
issueLat=1
opClass=SimdFloatMisc
opLat=1
[system.cpu.fuPool.FUList5.opList17]
type=OpDesc
issueLat=1
opClass=SimdFloatMult
opLat=1
[system.cpu.fuPool.FUList5.opList18]
type=OpDesc
issueLat=1
opClass=SimdFloatMultAcc
opLat=1
[system.cpu.fuPool.FUList5.opList19]
type=OpDesc
issueLat=1
opClass=SimdFloatSqrt
opLat=1
[system.cpu.fuPool.FUList6]
type=FUDesc
children=opList
count=0
opList=system.cpu.fuPool.FUList6.opList
[system.cpu.fuPool.FUList6.opList]
type=OpDesc
issueLat=1
opClass=MemWrite
opLat=1
[system.cpu.fuPool.FUList7]
type=FUDesc
children=opList0 opList1
count=4
opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
[system.cpu.fuPool.FUList7.opList0]
type=OpDesc
issueLat=1
opClass=MemRead
opLat=1
[system.cpu.fuPool.FUList7.opList1]
type=OpDesc
issueLat=1
opClass=MemWrite
opLat=1
[system.cpu.fuPool.FUList8]
type=FUDesc
children=opList
count=1
opList=system.cpu.fuPool.FUList8.opList
[system.cpu.fuPool.FUList8.opList]
type=OpDesc
issueLat=3
opClass=IprAccess
opLat=3
[system.cpu.icache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=131072
subblock_size=0
system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.interrupts]
type=ArmInterrupts
[system.cpu.itb]
type=ArmTLB
children=walker
size=64
walker=system.cpu.itb.walker
[system.cpu.itb.walker]
type=ArmTableWalker
max_backoff=100000
min_backoff=0
sys=system
port=system.cpu.toL2Bus.slave[2]
[system.cpu.l2cache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=false
latency=1000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=2097152
subblock_size=0
system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
[system.cpu.toL2Bus]
type=CoherentBus
block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=bzip2 input.source 1
cwd=build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing
egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/cpu2000/binaries/arm/linux/bzip2
gid=100
input=cin
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=0
system=system
uid=100
[system.membus]
type=CoherentBus
block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
master=system.physmem.port[0]
slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=SimpleMemory
conf_table_reported=false
file=
in_addr_map=true
latency=30000
latency_var=0
null=false
range=0:134217727
zero=false
port=system.membus.master[0]

3
simulators/gem5/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simerr Executable file
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@ -0,0 +1,3 @@
warn: Sockets disabled, not accepting gdb connections
warn: CP14 unimplemented crn[8], opc1[2], crm[9], opc2[4]
hack: be nice to actually delete the event here

27
simulators/gem5/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout Executable file
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@ -0,0 +1,27 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 4 2012 12:14:06
gem5 started Jun 4 2012 18:36:31
gem5 executing on zizzer
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
spec_init
Loading Input Data
Input data 1048576 bytes in length
Compressing Input Data, level 7
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
Compressed data 198546 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Compressing Input Data, level 9
Compressed data 198677 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
Exiting @ tick 463993693500 because target called exit()

709
simulators/gem5/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt Normal file
View File

@ -0,0 +1,709 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.463994 # Number of seconds simulated
sim_ticks 463993693500 # Number of ticks simulated
final_tick 463993693500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 128371 # Simulator instruction rate (inst/s)
host_op_rate 143208 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 38563333 # Simulator tick rate (ticks/s)
host_mem_usage 232076 # Number of bytes of host memory used
host_seconds 12031.99 # Real time elapsed on the host
sim_insts 1544563066 # Number of instructions simulated
sim_ops 1723073879 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 49344 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 189746304 # Number of bytes read from this memory
system.physmem.bytes_read::total 189795648 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 49344 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 49344 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 78222144 # Number of bytes written to this memory
system.physmem.bytes_written::total 78222144 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 771 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 2964786 # Number of read requests responded to by this memory
system.physmem.num_reads::total 2965557 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 1222221 # Number of write requests responded to by this memory
system.physmem.num_writes::total 1222221 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 106346 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 408941558 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 409047904 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 106346 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 106346 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 168584498 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 168584498 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 168584498 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 106346 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 408941558 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 577632403 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 46 # Number of system calls
system.cpu.numCycles 927987388 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.BPredUnit.lookups 300553850 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 246366147 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 16098585 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 170916236 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 156311774 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 18335288 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 425 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 292740519 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 2158326699 # Number of instructions fetch has processed
system.cpu.fetch.Branches 300553850 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 174647062 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 429206926 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 83759589 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 129259054 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 6 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 200 # Number of stall cycles due to pending traps
system.cpu.fetch.CacheLines 283730265 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 5372560 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 918446800 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.613763 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.238744 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 489239924 53.27% 53.27% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 23020148 2.51% 55.77% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 38764254 4.22% 60.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 47809734 5.21% 65.20% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 40766066 4.44% 69.64% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 46976906 5.11% 74.75% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 39072572 4.25% 79.01% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 18137057 1.97% 80.98% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 174660139 19.02% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 918446800 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.323877 # Number of branch fetches per cycle
system.cpu.fetch.rate 2.325815 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 322039794 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 109288431 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 403236235 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 16643003 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 67239337 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 46165390 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 810 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 2346870217 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 2646 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 67239337 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 343676895 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 50827249 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 9551 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 397069716 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 59624052 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 2289998307 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 23088 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 4666333 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 46320806 # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents 5 # Number of times there has been no free registers
system.cpu.rename.RenamedOperands 2264655243 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 10570139009 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 10570134861 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 4148 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 1706319999 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 558335244 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 4462 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 4454 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 136929133 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 624839821 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 218742392 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 85961960 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 66558298 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 2190567677 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 692 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 2016055896 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 4892741 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 462785080 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 1074735939 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 515 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 918446800 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 2.195071 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.923309 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 251194344 27.35% 27.35% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 138877340 15.12% 42.47% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 158309179 17.24% 59.71% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 116273452 12.66% 72.37% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 125754756 13.69% 86.06% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 75525220 8.22% 94.28% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 39163504 4.26% 98.55% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 10678346 1.16% 99.71% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 2670659 0.29% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 918446800 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 824240 3.28% 3.28% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 4827 0.02% 3.30% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 3.30% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.30% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.30% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.30% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 3.30% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.30% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 3.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 3.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.30% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 19025079 75.82% 79.12% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 5238831 20.88% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 1234276939 61.22% 61.22% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 932607 0.05% 61.27% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.27% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.27% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.27% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.27% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.27% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.27% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.27% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.27% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.27% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.27% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.27% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.27% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.27% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.27% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.27% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.27% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.27% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.27% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.27% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.27% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.27% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 77 0.00% 61.27% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 3 0.00% 61.27% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 29 0.00% 61.27% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 14 0.00% 61.27% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.27% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.27% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 587048024 29.12% 90.39% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 193798201 9.61% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 2016055896 # Type of FU issued
system.cpu.iq.rate 2.172504 # Inst issue rate
system.cpu.iq.fu_busy_cnt 25092977 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.012447 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 4980543862 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 2653539100 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 1958126109 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 448 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 790 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 172 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 2041148646 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 227 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 63700277 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 138913044 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 284373 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 189336 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 43895340 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 451092 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 67239337 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 23164250 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 1316440 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 2190576494 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 5585867 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 624839821 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 218742392 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 626 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 207277 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 49894 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 189336 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 8626288 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 10208500 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 18834788 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 1986583692 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 572477440 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 29472204 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 8125 # number of nop insts executed
system.cpu.iew.exec_refs 763312359 # number of memory reference insts executed
system.cpu.iew.exec_branches 238194699 # Number of branches executed
system.cpu.iew.exec_stores 190834919 # Number of stores executed
system.cpu.iew.exec_rate 2.140744 # Inst execution rate
system.cpu.iew.wb_sent 1967109112 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 1958126281 # cumulative count of insts written-back
system.cpu.iew.wb_producers 1296093484 # num instructions producing a value
system.cpu.iew.wb_consumers 2068479796 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 2.110079 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.626592 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitCommittedInsts 1544563084 # The number of committed instructions
system.cpu.commit.commitCommittedOps 1723073897 # The number of committed instructions
system.cpu.commit.commitSquashedInsts 467569115 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 177 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 16098007 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 851207464 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 2.024270 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.756192 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 362905349 42.63% 42.63% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 192760849 22.65% 65.28% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 73571189 8.64% 73.92% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 35131293 4.13% 78.05% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 18689200 2.20% 80.25% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 30622248 3.60% 83.84% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 19666355 2.31% 86.15% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 10977227 1.29% 87.44% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 106883754 12.56% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 851207464 # Number of insts commited each cycle
system.cpu.commit.committedInsts 1544563084 # Number of instructions committed
system.cpu.commit.committedOps 1723073897 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 660773829 # Number of memory references committed
system.cpu.commit.loads 485926777 # Number of loads committed
system.cpu.commit.membars 62 # Number of memory barriers committed
system.cpu.commit.branches 213462371 # Number of branches committed
system.cpu.commit.fp_insts 36 # Number of committed floating point instructions.
system.cpu.commit.int_insts 1536941877 # Number of committed integer instructions.
system.cpu.commit.function_calls 13665177 # Number of function calls committed.
system.cpu.commit.bw_lim_events 106883754 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 2934966123 # The number of ROB reads
system.cpu.rob.rob_writes 4448699546 # The number of ROB writes
system.cpu.timesIdled 899596 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 9540588 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 1544563066 # Number of Instructions Simulated
system.cpu.committedOps 1723073879 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 1544563066 # Number of Instructions Simulated
system.cpu.cpi 0.600809 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.600809 # CPI: Total CPI of All Threads
system.cpu.ipc 1.664422 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.664422 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 9951953141 # number of integer regfile reads
system.cpu.int_regfile_writes 1938266429 # number of integer regfile writes
system.cpu.fp_regfile_reads 186 # number of floating regfile reads
system.cpu.fp_regfile_writes 205 # number of floating regfile writes
system.cpu.misc_regfile_reads 2897977277 # number of misc regfile reads
system.cpu.misc_regfile_writes 138 # number of misc regfile writes
system.cpu.icache.replacements 28 # number of replacements
system.cpu.icache.tagsinuse 641.389873 # Cycle average of tags in use
system.cpu.icache.total_refs 283729068 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 801 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 354218.561798 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 641.389873 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.313179 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.313179 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 283729068 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 283729068 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 283729068 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 283729068 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 283729068 # number of overall hits
system.cpu.icache.overall_hits::total 283729068 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 1197 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 1197 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 1197 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 1197 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 1197 # number of overall misses
system.cpu.icache.overall_misses::total 1197 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 39840000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 39840000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 39840000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 39840000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 39840000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 39840000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 283730265 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 283730265 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 283730265 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 283730265 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 283730265 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 283730265 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 33283.208020 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 33283.208020 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 33283.208020 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 33283.208020 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 33283.208020 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 33283.208020 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 396 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 396 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 396 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 396 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 396 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 396 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 801 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 801 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 801 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 801 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 801 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 801 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27579500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 27579500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 27579500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 27579500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27579500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 27579500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000003 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000003 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000003 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34431.335830 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 34431.335830 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34431.335830 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 34431.335830 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34431.335830 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 34431.335830 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 9619302 # number of replacements
system.cpu.dcache.tagsinuse 4087.756066 # Cycle average of tags in use
system.cpu.dcache.total_refs 660726669 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 9623398 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 68.658354 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 3346373000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 4087.756066 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.997987 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.997987 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 493348220 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 493348220 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 167378287 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 167378287 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 94 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 94 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 68 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 68 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 660726507 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 660726507 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 660726507 # number of overall hits
system.cpu.dcache.overall_hits::total 660726507 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 10693817 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 10693817 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 5207760 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 5207760 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data 15901577 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 15901577 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 15901577 # number of overall misses
system.cpu.dcache.overall_misses::total 15901577 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 189065481500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 189065481500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 129319032251 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 129319032251 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 113500 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 113500 # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 318384513751 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 318384513751 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 318384513751 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 318384513751 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 504042037 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 504042037 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 97 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 97 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 68 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 68 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 676628084 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 676628084 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 676628084 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 676628084 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.021216 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.021216 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.030175 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.030175 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.030928 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.030928 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.023501 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.023501 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.023501 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.023501 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17679.887499 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 17679.887499 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24831.987697 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 24831.987697 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 37833.333333 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 37833.333333 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 20022.197405 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 20022.197405 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 20022.197405 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 20022.197405 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 271440605 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 164500 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 91957 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 10 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 2951.821014 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 16450 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 3133684 # number of writebacks
system.cpu.dcache.writebacks::total 3133684 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2964371 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 2964371 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3313808 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 3313808 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 6278179 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 6278179 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 6278179 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 6278179 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7729446 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 7729446 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1893952 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 1893952 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 9623398 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 9623398 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 9623398 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 9623398 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 93061119500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 93061119500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 45369971960 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 45369971960 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 138431091460 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 138431091460 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 138431091460 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 138431091460 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015335 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015335 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010974 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010974 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014223 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.014223 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014223 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.014223 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12039.817537 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12039.817537 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 23955.185749 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 23955.185749 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14384.845297 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 14384.845297 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14384.845297 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 14384.845297 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 2953110 # number of replacements
system.cpu.l2cache.tagsinuse 26875.343151 # Cycle average of tags in use
system.cpu.l2cache.total_refs 7878336 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 2980430 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 2.643355 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 100989511500 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 10758.137226 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 11.396468 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 16105.809458 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.328312 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.000348 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.491510 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.820170 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 29 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 5680299 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 5680328 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 3133684 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 3133684 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 978305 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 978305 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst 29 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 6658604 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 6658633 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 29 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 6658604 # number of overall hits
system.cpu.l2cache.overall_hits::total 6658633 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 772 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 2049145 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 2049917 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 915649 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 915649 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 772 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 2964794 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 2965566 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 772 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 2964794 # number of overall misses
system.cpu.l2cache.overall_misses::total 2965566 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 26523500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 70343968500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 70370492000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 31764549000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 31764549000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 26523500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 102108517500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 102135041000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 26523500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 102108517500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 102135041000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 801 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 7729444 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 7730245 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 3133684 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 3133684 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1893954 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 1893954 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 801 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 9623398 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 9624199 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 801 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 9623398 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 9624199 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.963795 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.265109 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.265181 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.483459 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.483459 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.963795 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.308082 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.308136 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.963795 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.308082 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.308136 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34356.865285 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34328.448450 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 34328.459152 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34690.748311 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34690.748311 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34356.865285 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34440.341386 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 34440.319656 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34356.865285 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34440.341386 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 34440.319656 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 57329500 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 6735 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 8512.175204 # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks 1222221 # number of writebacks
system.cpu.l2cache.writebacks::total 1222221 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 8 # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total 9 # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data 8 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total 9 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data 8 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total 9 # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 771 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 2049137 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 2049908 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 915649 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 915649 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 771 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 2964786 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 2965557 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 771 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 2964786 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 2965557 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 24050500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 63906561000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 63930611500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 28918183500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 28918183500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24050500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 92824744500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 92848795000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24050500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 92824744500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 92848795000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.962547 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.265108 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.265180 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.483459 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.483459 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.962547 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.308081 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.308135 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.962547 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.308081 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.308135 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31193.904021 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31187.061187 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31187.063761 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31582.171225 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31582.171225 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31193.904021 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31309.087570 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31309.057624 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31193.904021 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31309.087570 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31309.057624 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

135
simulators/gem5/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini Normal file
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[root]
type=Root
children=system
full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
boot_osflags=a
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
readfile=
symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.cpu]
type=AtomicSimpleCPU
children=dtb interrupts itb tracer workload
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
fastmem=false
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
phase=0
profile=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
system=system
tracer=system.cpu.tracer
width=1
workload=system.cpu.workload
dcache_port=system.membus.slave[2]
icache_port=system.membus.slave[1]
[system.cpu.dtb]
type=ArmTLB
children=walker
size=64
walker=system.cpu.dtb.walker
[system.cpu.dtb.walker]
type=ArmTableWalker
max_backoff=100000
min_backoff=0
sys=system
port=system.membus.slave[4]
[system.cpu.interrupts]
type=ArmInterrupts
[system.cpu.itb]
type=ArmTLB
children=walker
size=64
walker=system.cpu.itb.walker
[system.cpu.itb.walker]
type=ArmTableWalker
max_backoff=100000
min_backoff=0
sys=system
port=system.membus.slave[3]
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=bzip2 input.source 1
cwd=build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-atomic
egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/cpu2000/binaries/arm/linux/bzip2
gid=100
input=cin
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=0
system=system
uid=100
[system.membus]
type=CoherentBus
block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
master=system.physmem.port[0]
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port
[system.physmem]
type=SimpleMemory
conf_table_reported=false
file=
in_addr_map=true
latency=30000
latency_var=0
null=false
range=0:134217727
zero=false
port=system.membus.master[0]

2
simulators/gem5/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simerr Executable file
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@ -0,0 +1,2 @@
warn: Sockets disabled, not accepting gdb connections
hack: be nice to actually delete the event here

27
simulators/gem5/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simout Executable file
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@ -0,0 +1,27 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 4 2012 12:14:06
gem5 started Jun 4 2012 18:41:45
gem5 executing on zizzer
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
spec_init
Loading Input Data
Input data 1048576 bytes in length
Compressing Input Data, level 7
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
Compressed data 198546 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Compressing Input Data, level 9
Compressed data 198677 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
Exiting @ tick 861538205000 because target called exit()

102
simulators/gem5/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt Normal file
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@ -0,0 +1,102 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.861538 # Number of seconds simulated
sim_ticks 861538205000 # Number of ticks simulated
final_tick 861538205000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 2187855 # Simulator instruction rate (inst/s)
host_op_rate 2440714 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1220358665 # Simulator tick rate (ticks/s)
host_mem_usage 221416 # Number of bytes of host memory used
host_seconds 705.97 # Real time elapsed on the host
sim_insts 1544563049 # Number of instructions simulated
sim_ops 1723073862 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 6178262392 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 1581387672 # Number of bytes read from this memory
system.physmem.bytes_read::total 7759650064 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 6178262392 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 6178262392 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 624158392 # Number of bytes written to this memory
system.physmem.bytes_written::total 624158392 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 1544565598 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 482384188 # Number of read requests responded to by this memory
system.physmem.num_reads::total 2026949786 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 172586108 # Number of write requests responded to by this memory
system.physmem.num_writes::total 172586108 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 7171199555 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 1835539809 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 9006739363 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 7171199555 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 7171199555 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 724469778 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 724469778 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 7171199555 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2560009587 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 9731209141 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 46 # Number of system calls
system.cpu.numCycles 1723076411 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 1544563049 # Number of instructions committed
system.cpu.committedOps 1723073862 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 1536941850 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 36 # Number of float alu accesses
system.cpu.num_func_calls 27330134 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 177498328 # number of instructions that are conditional controls
system.cpu.num_int_insts 1536941850 # number of integer instructions
system.cpu.num_fp_insts 36 # number of float instructions
system.cpu.num_int_register_reads 7861284536 # number of times the integer registers were read
system.cpu.num_int_register_writes 1675132418 # number of times the integer registers were written
system.cpu.num_fp_register_reads 24 # number of times the floating registers were read
system.cpu.num_fp_register_writes 16 # number of times the floating registers were written
system.cpu.num_mem_refs 660773816 # number of memory refs
system.cpu.num_load_insts 485926770 # Number of load instructions
system.cpu.num_store_insts 174847046 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 1723076411 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
---------- End Simulation Statistics ----------

216
simulators/gem5/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini Normal file
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@ -0,0 +1,216 @@
[root]
type=Root
children=system
full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
boot_osflags=a
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
readfile=
symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.cpu]
type=TimingSimpleCPU
children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
phase=0
profile=0
progress_interval=0
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=262144
subblock_size=0
system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
[system.cpu.dtb]
type=ArmTLB
children=walker
size=64
walker=system.cpu.dtb.walker
[system.cpu.dtb.walker]
type=ArmTableWalker
max_backoff=100000
min_backoff=0
sys=system
port=system.cpu.toL2Bus.slave[3]
[system.cpu.icache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=131072
subblock_size=0
system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.interrupts]
type=ArmInterrupts
[system.cpu.itb]
type=ArmTLB
children=walker
size=64
walker=system.cpu.itb.walker
[system.cpu.itb.walker]
type=ArmTableWalker
max_backoff=100000
min_backoff=0
sys=system
port=system.cpu.toL2Bus.slave[2]
[system.cpu.l2cache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=false
latency=10000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=2097152
subblock_size=0
system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
[system.cpu.toL2Bus]
type=CoherentBus
block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=bzip2 input.source 1
cwd=build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-timing
egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/cpu2000/binaries/arm/linux/bzip2
gid=100
input=cin
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=0
system=system
uid=100
[system.membus]
type=CoherentBus
block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
master=system.physmem.port[0]
slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=SimpleMemory
conf_table_reported=false
file=
in_addr_map=true
latency=30000
latency_var=0
null=false
range=0:134217727
zero=false
port=system.membus.master[0]

2
simulators/gem5/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simerr Executable file
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@ -0,0 +1,2 @@
warn: Sockets disabled, not accepting gdb connections
hack: be nice to actually delete the event here

27
simulators/gem5/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simout Executable file
View File

@ -0,0 +1,27 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 4 2012 12:14:06
gem5 started Jun 4 2012 18:44:07
gem5 executing on zizzer
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
spec_init
Loading Input Data
Input data 1048576 bytes in length
Compressing Input Data, level 7
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
Compressed data 198546 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Compressing Input Data, level 9
Compressed data 198677 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
Exiting @ tick 2431419954000 because target called exit()

427
simulators/gem5/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt Normal file
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@ -0,0 +1,427 @@
---------- Begin Simulation Statistics ----------
sim_seconds 2.431420 # Number of seconds simulated
sim_ticks 2431419954000 # Number of ticks simulated
final_tick 2431419954000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1031283 # Simulator instruction rate (inst/s)
host_op_rate 1150922 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1629547552 # Simulator tick rate (ticks/s)
host_mem_usage 230584 # Number of bytes of host memory used
host_seconds 1492.08 # Real time elapsed on the host
sim_insts 1538759609 # Number of instructions simulated
sim_ops 1717270343 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 39424 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 172726592 # Number of bytes read from this memory
system.physmem.bytes_read::total 172766016 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 39424 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 39424 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 75006720 # Number of bytes written to this memory
system.physmem.bytes_written::total 75006720 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 616 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 2698853 # Number of read requests responded to by this memory
system.physmem.num_reads::total 2699469 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 1171980 # Number of write requests responded to by this memory
system.physmem.num_writes::total 1171980 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 16214 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 71039391 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 71055605 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 16214 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 16214 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 30848937 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 30848937 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 30848937 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 16214 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 71039391 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 101904542 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 46 # Number of system calls
system.cpu.numCycles 4862839908 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 1538759609 # Number of instructions committed
system.cpu.committedOps 1717270343 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 1536941850 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 36 # Number of float alu accesses
system.cpu.num_func_calls 27330134 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 177498328 # number of instructions that are conditional controls
system.cpu.num_int_insts 1536941850 # number of integer instructions
system.cpu.num_fp_insts 36 # number of float instructions
system.cpu.num_int_register_reads 9304894713 # number of times the integer registers were read
system.cpu.num_int_register_writes 1675132418 # number of times the integer registers were written
system.cpu.num_fp_register_reads 24 # number of times the floating registers were read
system.cpu.num_fp_register_writes 16 # number of times the floating registers were written
system.cpu.num_mem_refs 660773816 # number of memory refs
system.cpu.num_load_insts 485926770 # Number of load instructions
system.cpu.num_store_insts 174847046 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 4862839908 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.icache.replacements 7 # number of replacements
system.cpu.icache.tagsinuse 514.872896 # Cycle average of tags in use
system.cpu.icache.total_refs 1544564961 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 638 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 2420948.214734 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 514.872896 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.251403 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.251403 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 1544564961 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 1544564961 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 1544564961 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 1544564961 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 1544564961 # number of overall hits
system.cpu.icache.overall_hits::total 1544564961 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 638 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 638 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 638 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 638 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 638 # number of overall misses
system.cpu.icache.overall_misses::total 638 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 34804000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 34804000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 34804000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 34804000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 34804000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 34804000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 1544565599 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 1544565599 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 1544565599 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 1544565599 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 1544565599 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 1544565599 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000000 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000000 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000000 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000000 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000000 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54551.724138 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 54551.724138 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 54551.724138 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 54551.724138 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 54551.724138 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 54551.724138 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 638 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 638 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 638 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 638 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 638 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 638 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 32890000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 32890000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 32890000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 32890000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 32890000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 32890000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000000 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000000 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000000 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51551.724138 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51551.724138 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51551.724138 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 51551.724138 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51551.724138 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 51551.724138 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 9111140 # number of replacements
system.cpu.dcache.tagsinuse 4083.719979 # Cycle average of tags in use
system.cpu.dcache.total_refs 645855060 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 9115236 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 70.854453 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 25923025000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 4083.719979 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.997002 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.997002 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 475158040 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 475158040 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 170696898 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 170696898 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 61 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 645854938 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 645854938 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 645854938 # number of overall hits
system.cpu.dcache.overall_hits::total 645854938 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 7226087 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 7226087 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 1889149 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 1889149 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 9115236 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 9115236 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 9115236 # number of overall misses
system.cpu.dcache.overall_misses::total 9115236 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 177140908000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 177140908000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 63824222000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 63824222000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 240965130000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 240965130000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 240965130000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 240965130000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 482384127 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 482384127 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 654970174 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 654970174 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 654970174 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 654970174 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.014980 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.014980 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010946 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.010946 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.013917 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.013917 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.013917 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.013917 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24514.084594 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 24514.084594 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33784.641656 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 33784.641656 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 26435.424162 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 26435.424162 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 26435.424162 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 26435.424162 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 3061985 # number of writebacks
system.cpu.dcache.writebacks::total 3061985 # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7226087 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 7226087 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889149 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 1889149 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 9115236 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 9115236 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 9115236 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 9115236 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 155462647000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 155462647000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 58156775000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 58156775000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 213619422000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 213619422000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 213619422000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 213619422000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.014980 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.014980 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010946 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010946 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.013917 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.013917 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.013917 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.013917 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21514.084594 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 21514.084594 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30784.641656 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30784.641656 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23435.424162 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 23435.424162 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23435.424162 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 23435.424162 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 2687066 # number of replacements
system.cpu.l2cache.tagsinuse 26134.517233 # Cycle average of tags in use
system.cpu.l2cache.total_refs 7569171 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 2714383 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 2.788542 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 538044123000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 11106.896016 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 11.181020 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 15016.440197 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.338956 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.000341 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.458265 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.797562 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 22 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 5417142 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 5417164 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 3061985 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 3061985 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 999241 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 999241 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst 22 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 6416383 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 6416405 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 22 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 6416383 # number of overall hits
system.cpu.l2cache.overall_hits::total 6416405 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 616 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 1808945 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 1809561 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 889908 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 889908 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 616 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 2698853 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 2699469 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 616 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 2698853 # number of overall misses
system.cpu.l2cache.overall_misses::total 2699469 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 32032000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 94065140000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 94097172000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 46275216000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 46275216000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 32032000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 140340356000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 140372388000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 32032000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 140340356000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 140372388000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 638 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 7226087 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 7226725 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 3061985 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 3061985 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1889149 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 1889149 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 638 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 9115236 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 9115874 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 638 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 9115236 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 9115874 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.965517 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.250335 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.250398 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.471063 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.471063 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.965517 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.296082 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.296128 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.965517 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.296082 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.296128 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks 1171980 # number of writebacks
system.cpu.l2cache.writebacks::total 1171980 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 616 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1808945 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 1809561 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 889908 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 889908 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 616 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 2698853 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 2699469 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 616 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 2698853 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 2699469 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 24640000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 72357800000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 72382440000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 35596320000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 35596320000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24640000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 107954120000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 107978760000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24640000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 107954120000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 107978760000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250335 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.250398 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.471063 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.471063 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.296082 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.296128 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.296082 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.296128 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

138
simulators/gem5/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini Normal file
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@ -0,0 +1,138 @@
[root]
type=Root
children=system
full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
boot_osflags=a
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
readfile=
symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.cpu]
type=AtomicSimpleCPU
children=dtb interrupts itb tracer workload
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
fastmem=false
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
phase=0
profile=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
system=system
tracer=system.cpu.tracer
width=1
workload=system.cpu.workload
dcache_port=system.membus.slave[2]
icache_port=system.membus.slave[1]
[system.cpu.dtb]
type=X86TLB
children=walker
size=64
walker=system.cpu.dtb.walker
[system.cpu.dtb.walker]
type=X86PagetableWalker
system=system
port=system.membus.slave[4]
[system.cpu.interrupts]
type=X86LocalApic
int_latency=1000
pio_addr=2305843009213693952
pio_latency=1000
system=system
int_master=system.membus.slave[5]
int_slave=system.membus.master[2]
pio=system.membus.master[1]
[system.cpu.itb]
type=X86TLB
children=walker
size=64
walker=system.cpu.itb.walker
[system.cpu.itb.walker]
type=X86PagetableWalker
system=system
port=system.membus.slave[3]
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=bzip2 input.source 1
cwd=build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-atomic
egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/cpu2000/binaries/x86/linux/bzip2
gid=100
input=cin
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=0
system=system
uid=100
[system.membus]
type=CoherentBus
block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.interrupts.int_master
[system.physmem]
type=SimpleMemory
conf_table_reported=false
file=
in_addr_map=true
latency=30000
latency_var=0
null=false
range=0:134217727
zero=false
port=system.membus.master[0]

4
simulators/gem5/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simerr Executable file
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@ -0,0 +1,4 @@
warn: Sockets disabled, not accepting gdb connections
warn: instruction 'fnstcw_Mw' unimplemented
warn: instruction 'fldcw_Mw' unimplemented
hack: be nice to actually delete the event here

27
simulators/gem5/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simout Executable file
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@ -0,0 +1,27 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 4 2012 13:44:28
gem5 started Jun 4 2012 15:49:05
gem5 executing on zizzer
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
spec_init
Loading Input Data
Input data 1048576 bytes in length
Compressing Input Data, level 7
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
Compressed data 198546 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Compressing Input Data, level 9
Compressed data 198677 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
Exiting @ tick 2846007259500 because target called exit()

60
simulators/gem5/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt Normal file
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@ -0,0 +1,60 @@
---------- Begin Simulation Statistics ----------
sim_seconds 2.846007 # Number of seconds simulated
sim_ticks 2846007259500 # Number of ticks simulated
final_tick 2846007259500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1390065 # Simulator instruction rate (inst/s)
host_op_rate 2165848 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1315169413 # Simulator tick rate (ticks/s)
host_mem_usage 216596 # Number of bytes of host memory used
host_seconds 2163.99 # Real time elapsed on the host
sim_insts 3008081057 # Number of instructions simulated
sim_ops 4686862651 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 32105863408 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 5023868347 # Number of bytes read from this memory
system.physmem.bytes_read::total 37129731755 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 32105863408 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 32105863408 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 1544656790 # Number of bytes written to this memory
system.physmem.bytes_written::total 1544656790 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 4013232926 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 1239184749 # Number of read requests responded to by this memory
system.physmem.num_reads::total 5252417675 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 438528337 # Number of write requests responded to by this memory
system.physmem.num_writes::total 438528337 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 11281019506 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 1765233848 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 13046253354 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 11281019506 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 11281019506 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 542745204 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 542745204 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 11281019506 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2307979052 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 13588998558 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 46 # Number of system calls
system.cpu.numCycles 5692014520 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 3008081057 # Number of instructions committed
system.cpu.committedOps 4686862651 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 4686862580 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu.num_func_calls 0 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 182173305 # number of instructions that are conditional controls
system.cpu.num_int_insts 4686862580 # number of integer instructions
system.cpu.num_fp_insts 0 # number of float instructions
system.cpu.num_int_register_reads 14165752766 # number of times the integer registers were read
system.cpu.num_int_register_writes 6716691823 # number of times the integer registers were written
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_mem_refs 1677713086 # number of memory refs
system.cpu.num_load_insts 1239184749 # Number of load instructions
system.cpu.num_store_insts 438528337 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 5692014520 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
---------- End Simulation Statistics ----------

219
simulators/gem5/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini Normal file
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[root]
type=Root
children=system
full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
boot_osflags=a
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
readfile=
symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.cpu]
type=TimingSimpleCPU
children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
phase=0
profile=0
progress_interval=0
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=262144
subblock_size=0
system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
[system.cpu.dtb]
type=X86TLB
children=walker
size=64
walker=system.cpu.dtb.walker
[system.cpu.dtb.walker]
type=X86PagetableWalker
system=system
port=system.cpu.toL2Bus.slave[3]
[system.cpu.icache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=131072
subblock_size=0
system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.interrupts]
type=X86LocalApic
int_latency=1000
pio_addr=2305843009213693952
pio_latency=1000
system=system
int_master=system.membus.slave[2]
int_slave=system.membus.master[2]
pio=system.membus.master[1]
[system.cpu.itb]
type=X86TLB
children=walker
size=64
walker=system.cpu.itb.walker
[system.cpu.itb.walker]
type=X86PagetableWalker
system=system
port=system.cpu.toL2Bus.slave[2]
[system.cpu.l2cache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=false
latency=10000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=2097152
subblock_size=0
system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
[system.cpu.toL2Bus]
type=CoherentBus
block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=bzip2 input.source 1
cwd=build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-timing
egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/cpu2000/binaries/x86/linux/bzip2
gid=100
input=cin
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=0
system=system
uid=100
[system.membus]
type=CoherentBus
block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave
slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master
[system.physmem]
type=SimpleMemory
conf_table_reported=false
file=
in_addr_map=true
latency=30000
latency_var=0
null=false
range=0:134217727
zero=false
port=system.membus.master[0]

4
simulators/gem5/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simerr Executable file
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@ -0,0 +1,4 @@
warn: Sockets disabled, not accepting gdb connections
warn: instruction 'fnstcw_Mw' unimplemented
warn: instruction 'fldcw_Mw' unimplemented
hack: be nice to actually delete the event here

27
simulators/gem5/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout Executable file
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@ -0,0 +1,27 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 4 2012 13:44:28
gem5 started Jun 4 2012 16:08:32
gem5 executing on zizzer
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
spec_init
Loading Input Data
Input data 1048576 bytes in length
Compressing Input Data, level 7
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
Compressed data 198546 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Compressing Input Data, level 9
Compressed data 198677 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
Exiting @ tick 5923548078000 because target called exit()

374
simulators/gem5/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt Normal file
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@ -0,0 +1,374 @@
---------- Begin Simulation Statistics ----------
sim_seconds 5.923548 # Number of seconds simulated
sim_ticks 5923548078000 # Number of ticks simulated
final_tick 5923548078000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 633731 # Simulator instruction rate (inst/s)
host_op_rate 987410 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1247949692 # Simulator tick rate (ticks/s)
host_mem_usage 225520 # Number of bytes of host memory used
host_seconds 4746.62 # Real time elapsed on the host
sim_insts 3008081057 # Number of instructions simulated
sim_ops 4686862651 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 43200 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 173866880 # Number of bytes read from this memory
system.physmem.bytes_read::total 173910080 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 43200 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 43200 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 75176384 # Number of bytes written to this memory
system.physmem.bytes_written::total 75176384 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 675 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 2716670 # Number of read requests responded to by this memory
system.physmem.num_reads::total 2717345 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 1174631 # Number of write requests responded to by this memory
system.physmem.num_writes::total 1174631 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 7293 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 29351814 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 29359107 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 7293 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 7293 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 12691107 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 12691107 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 12691107 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 7293 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 29351814 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 42050214 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 46 # Number of system calls
system.cpu.numCycles 11847096156 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 3008081057 # Number of instructions committed
system.cpu.committedOps 4686862651 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 4686862580 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu.num_func_calls 0 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 182173305 # number of instructions that are conditional controls
system.cpu.num_int_insts 4686862580 # number of integer instructions
system.cpu.num_fp_insts 0 # number of float instructions
system.cpu.num_int_register_reads 14165752766 # number of times the integer registers were read
system.cpu.num_int_register_writes 6716691823 # number of times the integer registers were written
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_mem_refs 1677713086 # number of memory refs
system.cpu.num_load_insts 1239184749 # Number of load instructions
system.cpu.num_store_insts 438528337 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 11847096156 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.icache.replacements 10 # number of replacements
system.cpu.icache.tagsinuse 555.713137 # Cycle average of tags in use
system.cpu.icache.total_refs 4013232252 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 675 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 5945529.262222 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 555.713137 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.271344 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.271344 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 4013232252 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 4013232252 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 4013232252 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 4013232252 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 4013232252 # number of overall hits
system.cpu.icache.overall_hits::total 4013232252 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 675 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 675 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 675 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 675 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 675 # number of overall misses
system.cpu.icache.overall_misses::total 675 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 37800000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 37800000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 37800000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 37800000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 37800000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 37800000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 4013232927 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 4013232927 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 4013232927 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 4013232927 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 4013232927 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 4013232927 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000000 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000000 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000000 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000000 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000000 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56000 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 56000 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 56000 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 56000 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 56000 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 56000 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 675 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 675 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 675 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 675 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 675 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 675 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 35775000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 35775000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 35775000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 35775000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 35775000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 35775000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000000 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000000 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000000 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53000 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 9108581 # number of replacements
system.cpu.dcache.tagsinuse 4084.662246 # Cycle average of tags in use
system.cpu.dcache.total_refs 1668600409 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 9112677 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 183.107599 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 58862779000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 4084.662246 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.997232 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.997232 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 1231961899 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 1231961899 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 436638510 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 436638510 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 1668600409 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 1668600409 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 1668600409 # number of overall hits
system.cpu.dcache.overall_hits::total 1668600409 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 7222850 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 7222850 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 1889827 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 1889827 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 9112677 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 9112677 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 9112677 # number of overall misses
system.cpu.dcache.overall_misses::total 9112677 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 177808540000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 177808540000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 63869078000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 63869078000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 241677618000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 241677618000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 241677618000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 241677618000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 1239184749 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 1239184749 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 438528337 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 438528337 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 1677713086 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 1677713086 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 1677713086 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 1677713086 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.005829 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.005829 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.004309 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.004309 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.005432 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.005432 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.005432 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.005432 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24617.504171 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 24617.504171 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33796.256483 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 33796.256483 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 26521.034159 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 26521.034159 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 26521.034159 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 26521.034159 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 3053391 # number of writebacks
system.cpu.dcache.writebacks::total 3053391 # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222850 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 7222850 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889827 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 1889827 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 9112677 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 9112677 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 9112677 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 9112677 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 156139990000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 156139990000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 58199597000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 58199597000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 214339587000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 214339587000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 214339587000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 214339587000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.005829 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.005829 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.004309 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.004309 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005432 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.005432 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005432 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.005432 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21617.504171 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 21617.504171 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30796.256483 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30796.256483 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23521.034159 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 23521.034159 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23521.034159 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 23521.034159 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 2706631 # number of replacements
system.cpu.l2cache.tagsinuse 26507.350069 # Cycle average of tags in use
system.cpu.l2cache.total_refs 7537629 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 2732923 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 2.758083 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 1324806325000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 11028.544571 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 19.163936 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 15459.641562 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.336564 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.000585 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.471791 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.808940 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.data 5396930 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 5396930 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 3053391 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 3053391 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 999077 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 999077 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.data 6396007 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 6396007 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.data 6396007 # number of overall hits
system.cpu.l2cache.overall_hits::total 6396007 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 675 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 1825920 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 1826595 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 890750 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 890750 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 675 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 2716670 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 2717345 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 675 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 2716670 # number of overall misses
system.cpu.l2cache.overall_misses::total 2717345 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 35100000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 94947840000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 94982940000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 46319000000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 46319000000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 35100000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 141266840000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 141301940000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 35100000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 141266840000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 141301940000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 675 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 7222850 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 7223525 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 3053391 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 3053391 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1889827 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 1889827 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 675 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 9112677 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 9113352 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 675 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 9112677 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 9113352 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.252798 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.252868 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.471339 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.471339 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.298120 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.298172 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.298120 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.298172 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks 1174631 # number of writebacks
system.cpu.l2cache.writebacks::total 1174631 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 675 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1825920 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 1826595 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 890750 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 890750 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 675 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 2716670 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 2717345 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 675 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 2716670 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 2717345 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 27000000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 73036800000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 73063800000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 35630000000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 35630000000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 27000000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 108666800000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 108693800000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 27000000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 108666800000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 108693800000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.252798 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.252868 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.471339 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.471339 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.298120 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.298172 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.298120 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.298172 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------