Adding gem5 source to svn.
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1819 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
This commit is contained in:
friemel
@ -0,0 +1,231 @@
|
||||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
full_system=false
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
||||
[system]
|
||||
type=System
|
||||
children=cpu membus physmem
|
||||
boot_osflags=a
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
mem_mode=atomic
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
readfile=
|
||||
symbolfile=
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.membus.slave[0]
|
||||
|
||||
[system.cpu]
|
||||
type=InOrderCPU
|
||||
children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
|
||||
BTBEntries=4096
|
||||
BTBTagSize=16
|
||||
RASSize=16
|
||||
activity=0
|
||||
cachePorts=2
|
||||
checker=Null
|
||||
choiceCtrBits=2
|
||||
choicePredictorSize=8192
|
||||
clock=500
|
||||
cpu_id=0
|
||||
defer_registration=false
|
||||
div16Latency=1
|
||||
div16RepeatRate=1
|
||||
div24Latency=1
|
||||
div24RepeatRate=1
|
||||
div32Latency=1
|
||||
div32RepeatRate=1
|
||||
div8Latency=1
|
||||
div8RepeatRate=1
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
fetchBuffSize=4
|
||||
functionTrace=false
|
||||
functionTraceStart=0
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
globalCtrBits=2
|
||||
globalHistoryBits=13
|
||||
globalPredictorSize=8192
|
||||
instShiftAmt=2
|
||||
interrupts=system.cpu.interrupts
|
||||
itb=system.cpu.itb
|
||||
localCtrBits=2
|
||||
localHistoryBits=11
|
||||
localHistoryTableSize=2048
|
||||
localPredictorSize=2048
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
memBlockSize=64
|
||||
multLatency=1
|
||||
multRepeatRate=1
|
||||
numThreads=1
|
||||
phase=0
|
||||
predType=tournament
|
||||
profile=0
|
||||
progress_interval=0
|
||||
stageTracing=false
|
||||
stageWidth=4
|
||||
system=system
|
||||
threadModel=SMT
|
||||
tracer=system.cpu.tracer
|
||||
workload=system.cpu.workload
|
||||
dcache_port=system.cpu.dcache.cpu_side
|
||||
icache_port=system.cpu.icache.cpu_side
|
||||
|
||||
[system.cpu.dcache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=262144
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.dcache_port
|
||||
mem_side=system.cpu.toL2Bus.slave[1]
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=AlphaTLB
|
||||
size=64
|
||||
|
||||
[system.cpu.icache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=131072
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.icache_port
|
||||
mem_side=system.cpu.toL2Bus.slave[0]
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=AlphaInterrupts
|
||||
|
||||
[system.cpu.itb]
|
||||
type=AlphaTLB
|
||||
size=48
|
||||
|
||||
[system.cpu.l2cache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=false
|
||||
latency=10000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=2097152
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.toL2Bus.master[0]
|
||||
mem_side=system.membus.slave[1]
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
master=system.cpu.l2cache.cpu_side
|
||||
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
|
||||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
|
||||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=vortex lendian.raw
|
||||
cwd=build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/inorder-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
ppid=99
|
||||
simpoint=0
|
||||
system=system
|
||||
uid=100
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
master=system.physmem.port[0]
|
||||
slave=system.system_port system.cpu.l2cache.mem_side
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.membus.master[0]
|
||||
|
||||
@ -0,0 +1,6 @@
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: Prefetch instructions in Alpha do not do anything
|
||||
warn: Prefetch instructions in Alpha do not do anything
|
||||
warn: Prefetch instructions in Alpha do not do anything
|
||||
warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
|
||||
hack: be nice to actually delete the event here
|
||||
@ -0,0 +1,11 @@
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jun 4 2012 11:50:11
|
||||
gem5 started Jun 4 2012 14:25:13
|
||||
gem5 executing on zizzer
|
||||
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/inorder-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
Exiting @ tick 47232621500 because target called exit()
|
||||
@ -0,0 +1,158 @@
|
||||
|
||||
SYSTEM TYPE...
|
||||
__ZTC__ := False
|
||||
__UNIX__ := True
|
||||
__RISC__ := True
|
||||
SPEC_CPU2000_LP64 := True
|
||||
__MAC__ := False
|
||||
__BCC__ := False
|
||||
__BORLANDC__ := False
|
||||
__GUI__ := False
|
||||
__WTC__ := False
|
||||
__HP__ := False
|
||||
|
||||
CODE OPTIONS...
|
||||
__MACROIZE_HM__ := True
|
||||
__MACROIZE_MEM__ := True
|
||||
ENV01 := True
|
||||
USE_HPP_STYPE_HDRS := False
|
||||
USE_H_STYPE_HDRS := False
|
||||
|
||||
CODE INCLUSION PARAMETERS...
|
||||
INCLUDE_ALL_CODE := False
|
||||
INCLUDE_DELETE_CODE := True
|
||||
__SWAP_GRP_POS__ := True
|
||||
__INCLUDE_MTRX__ := False
|
||||
__BAD_CODE__ := False
|
||||
API_INCLUDE := False
|
||||
BE_CAREFUL := False
|
||||
OLDWAY := False
|
||||
NOTUSED := False
|
||||
|
||||
SYSTEM PARAMETERS...
|
||||
EXT_ENUM := 999999999L
|
||||
CHUNK_CONSTANT := 55555555
|
||||
CORE_CONSTANT := 55555555
|
||||
CORE_LIMIT := 20971520
|
||||
CorePage_Size := 384000
|
||||
ALIGN_BYTES := True
|
||||
CORE_BLOCK_ALIGN := 8
|
||||
FAR_MEM := False
|
||||
|
||||
MEMORY MANAGEMENT PARAMETERS...
|
||||
SYSTEM_ALLOC := True
|
||||
SYSTEM_FREESTORE := True
|
||||
__NO_DISKCACHE__ := False
|
||||
__FREEZE_VCHUNKS__ := True
|
||||
__FREEZE_GRP_PACKETS__ := True
|
||||
__MINIMIZE_TREE_CACHE__:= True
|
||||
|
||||
SYSTEM STD PARAMETERS...
|
||||
__STDOUT__ := False
|
||||
NULL := 0
|
||||
LPTR := False
|
||||
False_Status := 1
|
||||
True_Status := 0
|
||||
LARGE := True
|
||||
TWOBYTE_BOOL := False
|
||||
__NOSTR__ := False
|
||||
|
||||
MEMORY VALIDATION PARAMETERS...
|
||||
CORE_CRC_CHECK := False
|
||||
VALIDATE_MEM_CHUNKS := False
|
||||
|
||||
SYSTEM DEBUG OPTIONS...
|
||||
DEBUG := False
|
||||
MCSTAT := False
|
||||
TRACKBACK := False
|
||||
FLUSH_FILES := False
|
||||
DEBUG_CORE0 := False
|
||||
DEBUG_RISC := False
|
||||
__TREE_BUG__ := False
|
||||
__TRACK_FILE_READS__ := False
|
||||
PAGE_SPACE := False
|
||||
LEAVE_NO_TRACE := True
|
||||
NULL_TRACE_STRS := False
|
||||
|
||||
TIME PARAMETERS...
|
||||
CLOCK_IS_LONG := False
|
||||
__DISPLAY_TIME__ := False
|
||||
__TREE_TIME__ := False
|
||||
__DISPLAY_ERRORS__ := False
|
||||
|
||||
API MACROS...
|
||||
__BMT01__ := True
|
||||
OPTIMIZE := True
|
||||
|
||||
END OF DEFINES.
|
||||
|
||||
|
||||
|
||||
... IMPLODE MEMORY ...
|
||||
|
||||
SWAP to DiskCache := False
|
||||
|
||||
FREEZE_GRP_PACKETS:= True
|
||||
|
||||
QueBug := 1000
|
||||
|
||||
sizeof(boolean) = 4
|
||||
sizeof(sizetype) = 4
|
||||
sizeof(chunkstruc) = 32
|
||||
|
||||
sizeof(shorttype ) = 2
|
||||
sizeof(idtype ) = 2
|
||||
sizeof(sizetype ) = 4
|
||||
sizeof(indextype ) = 4
|
||||
sizeof(numtype ) = 4
|
||||
sizeof(handletype) = 4
|
||||
sizeof(tokentype ) = 8
|
||||
|
||||
sizeof(short ) = 2
|
||||
sizeof(int ) = 4
|
||||
|
||||
sizeof(lt64 ) = 4
|
||||
sizeof(farlongtype) = 4
|
||||
sizeof(long ) = 8
|
||||
sizeof(longaddr ) = 8
|
||||
|
||||
sizeof(float ) = 4
|
||||
sizeof(double ) = 8
|
||||
|
||||
sizeof(addrtype ) = 8
|
||||
sizeof(char * ) = 8
|
||||
ALLOC CORE_1 :: 16
|
||||
BHOOLE NATH
|
||||
|
||||
OPEN File ./input/lendian.rnv
|
||||
*Status = 0
|
||||
DB HDR restored from FileVbn[ 0]
|
||||
DB BlkDirOffset : @ 2030c0
|
||||
DB BlkDirChunk : Chunk[ 10] AT Vbn[3146]
|
||||
DB BlkTknChunk : Chunk[ 11] AT Vbn[3147]
|
||||
DB BlkSizeChunk : Chunk[ 12] AT Vbn[3148]
|
||||
DB Handle Chunk's StackPtr = 20797
|
||||
|
||||
DB[ 1] LOADED; Handles= 20797
|
||||
KERNEL in CORE[ 1] Restored @ 4005c800
|
||||
|
||||
OPEN File ./input/lendian.wnv
|
||||
*Status = 0
|
||||
DB HDR restored from FileVbn[ 0]
|
||||
DB BlkDirOffset : @ 21c40
|
||||
DB BlkDirChunk : Chunk[ 31] AT Vbn[ 81]
|
||||
DB BlkTknChunk : Chunk[ 32] AT Vbn[ 82]
|
||||
DB BlkSizeChunk : Chunk[ 33] AT Vbn[ 83]
|
||||
DB Handle Chunk's StackPtr = 17
|
||||
|
||||
DB[ 2] LOADED; Handles= 17
|
||||
VORTEx_Status == -8 || fffffff8
|
||||
|
||||
BE HERE NOW !!!
|
||||
|
||||
|
||||
|
||||
... VORTEx ON LINE ...
|
||||
|
||||
|
||||
... END OF SESSION ...
|
||||
@ -0,0 +1,258 @@
|
||||
CREATE Db Header and Db Primal ...
|
||||
NEW DB [ 3] Created.
|
||||
|
||||
VORTEX INPUT PARAMETERS::
|
||||
MESSAGE FileName: smred.msg
|
||||
OUTPUT FileName: smred.out
|
||||
DISK CACHE FileName: NULL
|
||||
PART DB FileName: parts.db
|
||||
DRAW DB FileName: draw.db
|
||||
PERSON DB FileName: emp.db
|
||||
PERSONS Data FileName: ./input/persons.250
|
||||
PARTS Count : 100
|
||||
OUTER Loops : 1
|
||||
INNER Loops : 1
|
||||
LOOKUP Parts : 25
|
||||
DELETE Parts : 10
|
||||
STUFF Parts : 10
|
||||
DEPTH Traverse: 5
|
||||
% DECREASE Parts : 0
|
||||
% INCREASE LookUps : 0
|
||||
% INCREASE Deletes : 0
|
||||
% INCREASE Stuffs : 0
|
||||
FREEZE_PACKETS : 1
|
||||
ALLOC_CHUNKS : 10000
|
||||
EXTEND_CHUNKS : 5000
|
||||
DELETE Draw objects : True
|
||||
DELETE Part objects : False
|
||||
QUE_BUG : 1000
|
||||
VOID_BOUNDARY : 67108864
|
||||
VOID_RESERVE : 1048576
|
||||
|
||||
COMMIT_DBS : False
|
||||
|
||||
|
||||
|
||||
BMT TEST :: files...
|
||||
EdbName := PartLib
|
||||
EdbFileName := parts.db
|
||||
DrwName := DrawLib
|
||||
DrwFileName := draw.db
|
||||
EmpName := PersonLib
|
||||
EmpFileName := emp.db
|
||||
|
||||
Swap to DiskCache := False
|
||||
Freeze the cache := True
|
||||
|
||||
|
||||
BMT TEST :: parms...
|
||||
DeBug modulo := 1000
|
||||
Create Parts count:= 100
|
||||
Outer Loops := 1
|
||||
Inner Loops := 1
|
||||
Look Ups := 25
|
||||
Delete Parts := 10
|
||||
Stuff Parts := 10
|
||||
Traverse Limit := 5
|
||||
Delete Draws := True
|
||||
Delete Parts := False
|
||||
Delete ALL Parts := after every <mod 0>Outer Loop
|
||||
|
||||
INITIALIZE LIBRARY ::
|
||||
|
||||
INITIALIZE SCHEMA ::
|
||||
Primal_CreateDb Accessed !!!
|
||||
CREATE Db Header and Db Primal ...
|
||||
NEW DB [ 4] Created.
|
||||
PartLibCreate:: Db[ 4]; VpartsDir= 1
|
||||
|
||||
Part Count= 1
|
||||
|
||||
Initialize the Class maps
|
||||
LIST HEADS loaded ... DbListHead_Class = 207
|
||||
DbListNode_Class = 206
|
||||
|
||||
...NOTE... ShellLoadCode:: Class[ 228] will NOT be Activated.
|
||||
|
||||
|
||||
...NOTE... ShellLoadCode:: Class[ 229] will NOT be Activated.
|
||||
|
||||
Primal_CreateDb Accessed !!!
|
||||
CREATE Db Header and Db Primal ...
|
||||
NEW DB [ 5] Created.
|
||||
DrawLibCreate:: Db[ 5]; VpartsDir= 1
|
||||
|
||||
Initialize the Class maps of this schema.
|
||||
Primal_CreateDb Accessed !!!
|
||||
CREATE Db Header and Db Primal ...
|
||||
NEW DB [ 6] Created.
|
||||
|
||||
***NOTE*** Persons Library Extended!
|
||||
|
||||
Create <131072> Persons.
|
||||
ItNum 0. Person[ 6: 5]. Name= Riddell , Robert V. ;
|
||||
|
||||
LAST Person Read::
|
||||
ItNum 250. Person[ 6: 503]. Name= Gonzales , Warren X. ;
|
||||
|
||||
BUILD <Query0> for <Part2> class::
|
||||
|
||||
if (link[1].length >= 5) ::
|
||||
|
||||
Build Query2 for <Address> class::
|
||||
|
||||
if (State == CA || State == T*)
|
||||
|
||||
Build Query1 for <Person> class::
|
||||
|
||||
if (LastName >= H* && LastName <= P* && Query0(Residence)) ::
|
||||
|
||||
BUILD <Query3> for <DrawObj> class::
|
||||
|
||||
if (Id >= 3000
|
||||
&& (Id >= 3000 && Id <= 3001)
|
||||
&& Id >= 3002)
|
||||
|
||||
BUILD <Query4> for <NamedDrawObj> class::
|
||||
|
||||
if (Nam == Pre*
|
||||
|| (Nam == ??Mid??? || == Pre??Mid?? || == ??Post
|
||||
|| == Pre??Post || == ??Mid???Post || == Pre??Mid???Post)
|
||||
&& Id <= 7)
|
||||
SEED := 1008; Swap = False; RgnEntries = 135
|
||||
|
||||
OUTER LOOP [ 1] : NewParts = 100 LookUps = 25 StuffParts = 10.
|
||||
|
||||
Create 100 New Parts
|
||||
Create Part 1. Token[ 4: 2].
|
||||
|
||||
< 100> Parts Created. CurrentId= 100
|
||||
|
||||
Connect each instantiated Part TO 3 unique Parts
|
||||
Connect Part 1. Token[ 4: 2]
|
||||
Connect Part 25. Token[ 4: 26] FromList= 26.
|
||||
Connect Part 12. Token[ 4: 13] FromList= 13.
|
||||
Connect Part 59. Token[ 4: 60] FromList= 60.
|
||||
|
||||
SET <DrawObjs> entries::
|
||||
1. [ 5: 5] := <1 >; @[: 6]
|
||||
Iteration count = 100
|
||||
|
||||
SET <NamedDrawObjs> entries::
|
||||
1. [ 5: 39] := <14 >;
|
||||
Iteration count = 12
|
||||
|
||||
SET <LibRectangles> entries::
|
||||
1. [ 5: 23] := <8 >; @[: 24]
|
||||
Iteration count = 12
|
||||
|
||||
LIST <DbRectangles> entries::
|
||||
1. [ 5: 23]
|
||||
Iteration count = 12
|
||||
|
||||
SET <PersonNames > entries::
|
||||
Iteration count = 250
|
||||
|
||||
COMMIT All Image copies:: Release=<True>; Max Parts= 100
|
||||
< 100> Part images' Committed.
|
||||
< 0> are Named.
|
||||
< 50> Point images' Committed.
|
||||
< 81> Person images' Committed.
|
||||
|
||||
COMMIT Parts(* 100)
|
||||
|
||||
Commit TestObj_Class in <Primal> DB.
|
||||
ItNum 0. Token[ 0: 0]. TestObj Committed.
|
||||
< 0> TestObj images' Committed.
|
||||
|
||||
Commit CartesianPoint_Class in <Primal> DB.
|
||||
ItNum 0. Token[ 0: 0]. CartesianPoint Committed.
|
||||
< 0> CartesianPoint images' Committed.
|
||||
|
||||
BEGIN Inner Loop Sequence::.
|
||||
|
||||
INNER LOOP [ 1: 1] :
|
||||
|
||||
LOOK UP 25 Random Parts and Export each Part.
|
||||
|
||||
LookUp for 26 parts; Asserts = 8
|
||||
<Part2 > Asserts = 2; NULL Asserts = 3.
|
||||
<DrawObj > Asserts = 0; NULL Asserts = 5.
|
||||
<NamedObj > Asserts = 0; NULL Asserts = 0.
|
||||
<Person > Asserts = 0; NULL Asserts = 5.
|
||||
<TestObj > Asserts = 60; NULL Asserts = 0.
|
||||
|
||||
DELETE 10 Random Parts.
|
||||
|
||||
PartDelete :: Token[ 4: 91].
|
||||
PartDisconnect:: Token[ 4: 91] id:= 90 for each link.
|
||||
DisConnect link [ 0]:= 50; PartToken[ 51: 51].
|
||||
DisConnect link [ 1]:= 17; PartToken[ 18: 18].
|
||||
DisConnect link [ 2]:= 72; PartToken[ 73: 73].
|
||||
DeleteFromList:: Vchunk[ 4: 91]. (* 1)
|
||||
DisConnect FromList[ 0]:= 56; Token[ 57: 57].
|
||||
Vlists[ 89] := 100;
|
||||
|
||||
Delete for 11 parts;
|
||||
|
||||
Traverse Count= 0
|
||||
|
||||
TRAVERSE PartId[ 6] and all Connections to 5 Levels
|
||||
SEED In Traverse Part [ 4: 65] @ Level = 4.
|
||||
|
||||
Traverse Count= 357
|
||||
Traverse Asserts = 5. True Tests = 1
|
||||
< 5> DrawObj objects DELETED.
|
||||
< 2> are Named.
|
||||
< 2> Point objects DELETED.
|
||||
|
||||
CREATE 10 Additional Parts
|
||||
|
||||
Create 10 New Parts
|
||||
Create Part 101. Token[ 4: 102].
|
||||
|
||||
< 10> Parts Created. CurrentId= 110
|
||||
|
||||
Connect each instantiated Part TO 3 unique Parts
|
||||
|
||||
COMMIT All Image copies:: Release=<True>; Max Parts= 110
|
||||
< 81> Part images' Committed.
|
||||
< 0> are Named.
|
||||
< 38> Point images' Committed.
|
||||
< 31> Person images' Committed.
|
||||
|
||||
COMMIT Parts(* 100)
|
||||
|
||||
Commit TestObj_Class in <Primal> DB.
|
||||
ItNum 0. Token[ 3: 4]. TestObj Committed.
|
||||
< 15> TestObj images' Committed.
|
||||
|
||||
Commit CartesianPoint_Class in <Primal> DB.
|
||||
ItNum 0. Token[ 3: 3]. CartesianPoint Committed.
|
||||
< 16> CartesianPoint images' Committed.
|
||||
|
||||
DELETE All TestObj objects;
|
||||
|
||||
Delete TestObj_Class in <Primal> DB.
|
||||
ItNum 0. Token[ 3: 4]. TestObj Deleted.
|
||||
< 15> TestObj objects Deleted.
|
||||
|
||||
Commit CartesianPoint_Class in <Primal> DB.
|
||||
ItNum 0. Token[ 3: 3]. CartesianPoint Deleted.
|
||||
< 16> CartesianPoint objects Deleted.
|
||||
|
||||
DELETE TestObj and Point objects...
|
||||
|
||||
END INNER LOOP [ 1: 1].
|
||||
|
||||
DELETE All TestObj objects;
|
||||
|
||||
Delete TestObj_Class in <Primal> DB.
|
||||
< 0> TestObj objects Deleted.
|
||||
|
||||
Commit CartesianPoint_Class in <Primal> DB.
|
||||
< 0> CartesianPoint objects Deleted.
|
||||
|
||||
DELETE TestObj and Point objects...
|
||||
STATUS= -201
|
||||
V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!
|
||||
@ -0,0 +1,469 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.047233 # Number of seconds simulated
|
||||
sim_ticks 47232621500 # Number of ticks simulated
|
||||
final_tick 47232621500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 102058 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 102058 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 54566702 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 223484 # Number of bytes of host memory used
|
||||
host_seconds 865.59 # Real time elapsed on the host
|
||||
sim_insts 88340673 # Number of instructions simulated
|
||||
sim_ops 88340673 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 602240 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 10564992 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 11167232 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 602240 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 602240 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 7713024 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 7713024 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 9410 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 165078 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 174488 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 120516 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 120516 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 12750510 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 223679984 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 236430493 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 12750510 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 12750510 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 163298664 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 163298664 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 163298664 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 12750510 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 223679984 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 399729158 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
||||
system.cpu.dtb.read_hits 20277221 # DTB read hits
|
||||
system.cpu.dtb.read_misses 90148 # DTB read misses
|
||||
system.cpu.dtb.read_acv 0 # DTB read access violations
|
||||
system.cpu.dtb.read_accesses 20367369 # DTB read accesses
|
||||
system.cpu.dtb.write_hits 14736811 # DTB write hits
|
||||
system.cpu.dtb.write_misses 7252 # DTB write misses
|
||||
system.cpu.dtb.write_acv 0 # DTB write access violations
|
||||
system.cpu.dtb.write_accesses 14744063 # DTB write accesses
|
||||
system.cpu.dtb.data_hits 35014032 # DTB hits
|
||||
system.cpu.dtb.data_misses 97400 # DTB misses
|
||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
||||
system.cpu.dtb.data_accesses 35111432 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 12477897 # ITB hits
|
||||
system.cpu.itb.fetch_misses 13095 # ITB misses
|
||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
||||
system.cpu.itb.fetch_accesses 12490992 # ITB accesses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.itb.write_hits 0 # DTB write hits
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.itb.write_acv 0 # DTB write access violations
|
||||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.itb.data_hits 0 # DTB hits
|
||||
system.cpu.itb.data_misses 0 # DTB misses
|
||||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 4583 # Number of system calls
|
||||
system.cpu.numCycles 94465244 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.branch_predictor.lookups 18828991 # Number of BP lookups
|
||||
system.cpu.branch_predictor.condPredicted 12440560 # Number of conditional branches predicted
|
||||
system.cpu.branch_predictor.condIncorrect 5024685 # Number of conditional branches incorrect
|
||||
system.cpu.branch_predictor.BTBLookups 16222590 # Number of BTB lookups
|
||||
system.cpu.branch_predictor.BTBHits 5048183 # Number of BTB hits
|
||||
system.cpu.branch_predictor.usedRAS 1660950 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branch_predictor.RASInCorrect 1029 # Number of incorrect RAS predictions.
|
||||
system.cpu.branch_predictor.BTBHitPct 31.118231 # BTB Hit Percentage
|
||||
system.cpu.branch_predictor.predictedTaken 8476014 # Number of Branches Predicted As Taken (True).
|
||||
system.cpu.branch_predictor.predictedNotTaken 10352977 # Number of Branches Predicted As Not Taken (False).
|
||||
system.cpu.regfile_manager.intRegFileReads 74323677 # Number of Reads from Int. Register File
|
||||
system.cpu.regfile_manager.intRegFileWrites 52319250 # Number of Writes to Int. Register File
|
||||
system.cpu.regfile_manager.intRegFileAccesses 126642927 # Total Accesses (Read+Write) to the Int. Register File
|
||||
system.cpu.regfile_manager.floatRegFileReads 65289 # Number of Reads from FP Register File
|
||||
system.cpu.regfile_manager.floatRegFileWrites 227630 # Number of Writes to FP Register File
|
||||
system.cpu.regfile_manager.floatRegFileAccesses 292919 # Total Accesses (Read+Write) to the FP Register File
|
||||
system.cpu.regfile_manager.regForwards 14127497 # Number of Registers Read Through Forwarding Logic
|
||||
system.cpu.agen_unit.agens 35064147 # Number of Address Generations
|
||||
system.cpu.execution_unit.predictedTakenIncorrect 4680877 # Number of Branches Incorrectly Predicted As Taken.
|
||||
system.cpu.execution_unit.predictedNotTakenIncorrect 233308 # Number of Branches Incorrectly Predicted As Not Taken).
|
||||
system.cpu.execution_unit.mispredicted 4914185 # Number of Branches Incorrectly Predicted
|
||||
system.cpu.execution_unit.predicted 8858001 # Number of Branches Incorrectly Predicted
|
||||
system.cpu.execution_unit.mispredictPct 35.681953 # Percentage of Incorrect Branches Predicts
|
||||
system.cpu.execution_unit.executions 44775654 # Number of Instructions Executed.
|
||||
system.cpu.mult_div_unit.multiplies 41107 # Number of Multipy Operations Executed
|
||||
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
|
||||
system.cpu.contextSwitches 1 # Number of context switches
|
||||
system.cpu.threadCycles 78066794 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
|
||||
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
|
||||
system.cpu.timesIdled 305627 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 24182755 # Number of cycles cpu's stages were not processed
|
||||
system.cpu.runCycles 70282489 # Number of cycles cpu stages are processed.
|
||||
system.cpu.activity 74.400368 # Percentage of cycles cpu is active
|
||||
system.cpu.comLoads 20276638 # Number of Load instructions committed
|
||||
system.cpu.comStores 14613377 # Number of Store instructions committed
|
||||
system.cpu.comBranches 13754477 # Number of Branches instructions committed
|
||||
system.cpu.comNops 8748916 # Number of Nop instructions committed
|
||||
system.cpu.comNonSpec 4583 # Number of Non-Speculative instructions committed
|
||||
system.cpu.comInts 30791227 # Number of Integer instructions committed
|
||||
system.cpu.comFloats 151453 # Number of Floating Point instructions committed
|
||||
system.cpu.committedInsts 88340673 # Number of Instructions committed (Per-Thread)
|
||||
system.cpu.committedOps 88340673 # Number of Ops committed (Per-Thread)
|
||||
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
|
||||
system.cpu.committedInsts_total 88340673 # Number of Instructions committed (Total)
|
||||
system.cpu.cpi 1.069329 # CPI: Cycles Per Instruction (Per-Thread)
|
||||
system.cpu.smt_cpi nan # CPI: Total SMT-CPI
|
||||
system.cpu.cpi_total 1.069329 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 0.935166 # IPC: Instructions Per Cycle (Per-Thread)
|
||||
system.cpu.smt_ipc nan # IPC: Total SMT-IPC
|
||||
system.cpu.ipc_total 0.935166 # IPC: Total IPC of All Threads
|
||||
system.cpu.stage0.idleCycles 41039233 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage0.runCycles 53426011 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage0.utilization 56.556262 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage1.idleCycles 51809989 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage1.runCycles 42655255 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage1.utilization 45.154443 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage2.idleCycles 51339314 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage2.runCycles 43125930 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage2.utilization 45.652695 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage3.idleCycles 72336276 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage3.runCycles 22128968 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage3.utilization 23.425513 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage4.idleCycles 48368266 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage4.runCycles 46096978 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage4.utilization 48.797818 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.icache.replacements 85310 # number of replacements
|
||||
system.cpu.icache.tagsinuse 1887.040544 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 12359577 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 87356 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 141.485153 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 1887.040544 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.921407 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.921407 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 12359577 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 12359577 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 12359577 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 12359577 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 12359577 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 12359577 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 118263 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 118263 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 118263 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 118263 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 118263 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 118263 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 2089534000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 2089534000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 2089534000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 2089534000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 2089534000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 2089534000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 12477840 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 12477840 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 12477840 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 12477840 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 12477840 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 12477840 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.009478 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.009478 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.009478 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.009478 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.009478 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.009478 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17668.535383 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 17668.535383 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 17668.535383 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 17668.535383 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 17668.535383 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 17668.535383 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 1485500 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 122 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets 12176.229508 # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 30907 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::total 30907 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::cpu.inst 30907 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::total 30907 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::cpu.inst 30907 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::total 30907 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 87356 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 87356 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 87356 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 87356 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 87356 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 87356 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1366128500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 1366128500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1366128500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 1366128500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1366128500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 1366128500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.007001 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.007001 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.007001 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.007001 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.007001 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.007001 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15638.633866 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15638.633866 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15638.633866 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 15638.633866 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15638.633866 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 15638.633866 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 200251 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 4073.126583 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 34125996 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 204347 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 167.000230 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 487962000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 4073.126583 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.994416 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.994416 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 20180455 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 20180455 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 13945541 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 13945541 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 34125996 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 34125996 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 34125996 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 34125996 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 96183 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 96183 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 667836 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 667836 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 764019 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 764019 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 764019 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 764019 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 4158611000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 4158611000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 35328865500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 35328865500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 39487476500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 39487476500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 39487476500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 39487476500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 20276638 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 20276638 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 34890015 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 34890015 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 34890015 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 34890015 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004744 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.004744 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.045700 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.045700 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.021898 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.021898 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.021898 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.021898 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 43236.445110 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 43236.445110 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52900.510754 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 52900.510754 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 51683.893332 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 51683.893332 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 51683.893332 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 51683.893332 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 6329431500 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 124110 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets 50998.561760 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 161215 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 161215 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 35416 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 35416 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 524256 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 524256 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 559672 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 559672 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 559672 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 559672 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 60767 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 60767 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143580 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 143580 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 204347 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 204347 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 204347 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 204347 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2088876000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2088876000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7254482000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 7254482000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9343358000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 9343358000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9343358000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 9343358000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002997 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002997 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009825 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009825 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.005857 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.005857 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34375.170734 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34375.170734 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 50525.713888 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 50525.713888 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45723.000582 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 45723.000582 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45723.000582 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 45723.000582 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 148111 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 18671.690365 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 132979 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 173456 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 0.766644 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::writebacks 15657.217235 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 1374.269041 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 1640.204088 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.477820 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.041939 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.050055 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.569815 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 77946 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 26999 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 104945 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 161215 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 161215 # number of Writeback hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 12270 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 12270 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 77946 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 39269 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 117215 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 77946 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 39269 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 117215 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 9410 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.data 33578 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 42988 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 131500 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 131500 # number of ReadExReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 9410 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 165078 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 174488 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 9410 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 165078 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 174488 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 492013000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1752923000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 2244936000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6854378000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 6854378000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 492013000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 8607301000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 9099314000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 492013000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 8607301000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 9099314000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 87356 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 60577 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 147933 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 161215 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 161215 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 143770 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 143770 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 87356 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 204347 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 291703 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 87356 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 204347 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 291703 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.107720 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.554303 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.290591 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.914655 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.914655 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.107720 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.807832 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.598170 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.107720 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.807832 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.598170 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52286.184910 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52204.508905 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52222.387643 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52124.547529 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52124.547529 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52286.184910 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52140.812222 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52148.652056 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52286.184910 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52140.812222 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52148.652056 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks::writebacks 120516 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 120516 # number of writebacks
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 9410 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 33578 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::total 42988 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 131500 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 131500 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 9410 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 165078 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 174488 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 9410 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 165078 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 174488 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 377128500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1343464000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1720592500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5262752500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5262752500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 377128500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6606216500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 6983345000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 377128500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6606216500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 6983345000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.107720 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.554303 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.290591 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.914655 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.914655 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.107720 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.807832 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.598170 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.107720 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.807832 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.598170 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40077.417641 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40010.244803 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40024.948823 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40020.931559 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40020.931559 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40077.417641 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40018.757799 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40021.921278 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40077.417641 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40018.757799 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40021.921278 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
@ -0,0 +1,529 @@
|
||||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
full_system=false
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
||||
[system]
|
||||
type=System
|
||||
children=cpu membus physmem
|
||||
boot_osflags=a
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
mem_mode=atomic
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
readfile=
|
||||
symbolfile=
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.membus.slave[0]
|
||||
|
||||
[system.cpu]
|
||||
type=DerivO3CPU
|
||||
children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
|
||||
BTBEntries=4096
|
||||
BTBTagSize=16
|
||||
LFSTSize=1024
|
||||
LQEntries=32
|
||||
LSQCheckLoads=true
|
||||
LSQDepCheckShift=4
|
||||
RASSize=16
|
||||
SQEntries=32
|
||||
SSITSize=1024
|
||||
activity=0
|
||||
backComSize=5
|
||||
cachePorts=200
|
||||
checker=Null
|
||||
choiceCtrBits=2
|
||||
choicePredictorSize=8192
|
||||
clock=500
|
||||
commitToDecodeDelay=1
|
||||
commitToFetchDelay=1
|
||||
commitToIEWDelay=1
|
||||
commitToRenameDelay=1
|
||||
commitWidth=8
|
||||
cpu_id=0
|
||||
decodeToFetchDelay=1
|
||||
decodeToRenameDelay=1
|
||||
decodeWidth=8
|
||||
defer_registration=false
|
||||
dispatchWidth=8
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
fetchToDecodeDelay=1
|
||||
fetchTrapLatency=1
|
||||
fetchWidth=8
|
||||
forwardComSize=5
|
||||
fuPool=system.cpu.fuPool
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
globalCtrBits=2
|
||||
globalHistoryBits=13
|
||||
globalPredictorSize=8192
|
||||
iewToCommitDelay=1
|
||||
iewToDecodeDelay=1
|
||||
iewToFetchDelay=1
|
||||
iewToRenameDelay=1
|
||||
instShiftAmt=2
|
||||
interrupts=system.cpu.interrupts
|
||||
issueToExecuteDelay=1
|
||||
issueWidth=8
|
||||
itb=system.cpu.itb
|
||||
localCtrBits=2
|
||||
localHistoryBits=11
|
||||
localHistoryTableSize=2048
|
||||
localPredictorSize=2048
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
needsTSO=false
|
||||
numIQEntries=64
|
||||
numPhysFloatRegs=256
|
||||
numPhysIntRegs=256
|
||||
numROBEntries=192
|
||||
numRobs=1
|
||||
numThreads=1
|
||||
phase=0
|
||||
predType=tournament
|
||||
profile=0
|
||||
progress_interval=0
|
||||
renameToDecodeDelay=1
|
||||
renameToFetchDelay=1
|
||||
renameToIEWDelay=2
|
||||
renameToROBDelay=1
|
||||
renameWidth=8
|
||||
smtCommitPolicy=RoundRobin
|
||||
smtFetchPolicy=SingleThread
|
||||
smtIQPolicy=Partitioned
|
||||
smtIQThreshold=100
|
||||
smtLSQPolicy=Partitioned
|
||||
smtLSQThreshold=100
|
||||
smtNumFetchingThreads=1
|
||||
smtROBPolicy=Partitioned
|
||||
smtROBThreshold=100
|
||||
squashWidth=8
|
||||
store_set_clear_period=250000
|
||||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
trapLatency=13
|
||||
wbDepth=1
|
||||
wbWidth=8
|
||||
workload=system.cpu.workload
|
||||
dcache_port=system.cpu.dcache.cpu_side
|
||||
icache_port=system.cpu.icache.cpu_side
|
||||
|
||||
[system.cpu.dcache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=262144
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=20
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.dcache_port
|
||||
mem_side=system.cpu.toL2Bus.slave[1]
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=AlphaTLB
|
||||
size=64
|
||||
|
||||
[system.cpu.fuPool]
|
||||
type=FUPool
|
||||
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
|
||||
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
|
||||
|
||||
[system.cpu.fuPool.FUList0]
|
||||
type=FUDesc
|
||||
children=opList
|
||||
count=6
|
||||
opList=system.cpu.fuPool.FUList0.opList
|
||||
|
||||
[system.cpu.fuPool.FUList0.opList]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=IntAlu
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList1]
|
||||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=2
|
||||
opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=IntMult
|
||||
opLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList1]
|
||||
type=OpDesc
|
||||
issueLat=19
|
||||
opClass=IntDiv
|
||||
opLat=20
|
||||
|
||||
[system.cpu.fuPool.FUList2]
|
||||
type=FUDesc
|
||||
children=opList0 opList1 opList2
|
||||
count=4
|
||||
opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=FloatAdd
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList1]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=FloatCmp
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList2]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=FloatCvt
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList3]
|
||||
type=FUDesc
|
||||
children=opList0 opList1 opList2
|
||||
count=2
|
||||
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=FloatMult
|
||||
opLat=4
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList1]
|
||||
type=OpDesc
|
||||
issueLat=12
|
||||
opClass=FloatDiv
|
||||
opLat=12
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList2]
|
||||
type=OpDesc
|
||||
issueLat=24
|
||||
opClass=FloatSqrt
|
||||
opLat=24
|
||||
|
||||
[system.cpu.fuPool.FUList4]
|
||||
type=FUDesc
|
||||
children=opList
|
||||
count=0
|
||||
opList=system.cpu.fuPool.FUList4.opList
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5]
|
||||
type=FUDesc
|
||||
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
|
||||
count=4
|
||||
opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList00]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdAdd
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList01]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdAddAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList02]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdAlu
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList03]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdCmp
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList04]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdCvt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList05]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdMisc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList06]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdMult
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList07]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdMultAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList08]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdShift
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList09]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdShiftAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList10]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdSqrt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList11]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatAdd
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList12]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatAlu
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList13]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatCmp
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList14]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatCvt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList15]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatDiv
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList16]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatMisc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList17]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatMult
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList18]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatMultAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList19]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatSqrt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList6]
|
||||
type=FUDesc
|
||||
children=opList
|
||||
count=0
|
||||
opList=system.cpu.fuPool.FUList6.opList
|
||||
|
||||
[system.cpu.fuPool.FUList6.opList]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList7]
|
||||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=4
|
||||
opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList1]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList8]
|
||||
type=FUDesc
|
||||
children=opList
|
||||
count=1
|
||||
opList=system.cpu.fuPool.FUList8.opList
|
||||
|
||||
[system.cpu.fuPool.FUList8.opList]
|
||||
type=OpDesc
|
||||
issueLat=3
|
||||
opClass=IprAccess
|
||||
opLat=3
|
||||
|
||||
[system.cpu.icache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=131072
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=20
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.icache_port
|
||||
mem_side=system.cpu.toL2Bus.slave[0]
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=AlphaInterrupts
|
||||
|
||||
[system.cpu.itb]
|
||||
type=AlphaTLB
|
||||
size=48
|
||||
|
||||
[system.cpu.l2cache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=false
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=2097152
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.toL2Bus.master[0]
|
||||
mem_side=system.membus.slave[1]
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
master=system.cpu.l2cache.cpu_side
|
||||
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
|
||||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
|
||||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=vortex lendian.raw
|
||||
cwd=build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/o3-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
ppid=99
|
||||
simpoint=0
|
||||
system=system
|
||||
uid=100
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
master=system.physmem.port[0]
|
||||
slave=system.system_port system.cpu.l2cache.mem_side
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.membus.master[0]
|
||||
|
||||
6
simulators/gem5/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simerr
Executable file
6
simulators/gem5/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simerr
Executable file
@ -0,0 +1,6 @@
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: Prefetch instructions in Alpha do not do anything
|
||||
warn: Prefetch instructions in Alpha do not do anything
|
||||
warn: Prefetch instructions in Alpha do not do anything
|
||||
warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
|
||||
hack: be nice to actually delete the event here
|
||||
11
simulators/gem5/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout
Executable file
11
simulators/gem5/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout
Executable file
@ -0,0 +1,11 @@
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jun 4 2012 11:50:11
|
||||
gem5 started Jun 4 2012 14:07:55
|
||||
gem5 executing on zizzer
|
||||
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
Exiting @ tick 21302882000 because target called exit()
|
||||
@ -0,0 +1,158 @@
|
||||
|
||||
SYSTEM TYPE...
|
||||
__ZTC__ := False
|
||||
__UNIX__ := True
|
||||
__RISC__ := True
|
||||
SPEC_CPU2000_LP64 := True
|
||||
__MAC__ := False
|
||||
__BCC__ := False
|
||||
__BORLANDC__ := False
|
||||
__GUI__ := False
|
||||
__WTC__ := False
|
||||
__HP__ := False
|
||||
|
||||
CODE OPTIONS...
|
||||
__MACROIZE_HM__ := True
|
||||
__MACROIZE_MEM__ := True
|
||||
ENV01 := True
|
||||
USE_HPP_STYPE_HDRS := False
|
||||
USE_H_STYPE_HDRS := False
|
||||
|
||||
CODE INCLUSION PARAMETERS...
|
||||
INCLUDE_ALL_CODE := False
|
||||
INCLUDE_DELETE_CODE := True
|
||||
__SWAP_GRP_POS__ := True
|
||||
__INCLUDE_MTRX__ := False
|
||||
__BAD_CODE__ := False
|
||||
API_INCLUDE := False
|
||||
BE_CAREFUL := False
|
||||
OLDWAY := False
|
||||
NOTUSED := False
|
||||
|
||||
SYSTEM PARAMETERS...
|
||||
EXT_ENUM := 999999999L
|
||||
CHUNK_CONSTANT := 55555555
|
||||
CORE_CONSTANT := 55555555
|
||||
CORE_LIMIT := 20971520
|
||||
CorePage_Size := 384000
|
||||
ALIGN_BYTES := True
|
||||
CORE_BLOCK_ALIGN := 8
|
||||
FAR_MEM := False
|
||||
|
||||
MEMORY MANAGEMENT PARAMETERS...
|
||||
SYSTEM_ALLOC := True
|
||||
SYSTEM_FREESTORE := True
|
||||
__NO_DISKCACHE__ := False
|
||||
__FREEZE_VCHUNKS__ := True
|
||||
__FREEZE_GRP_PACKETS__ := True
|
||||
__MINIMIZE_TREE_CACHE__:= True
|
||||
|
||||
SYSTEM STD PARAMETERS...
|
||||
__STDOUT__ := False
|
||||
NULL := 0
|
||||
LPTR := False
|
||||
False_Status := 1
|
||||
True_Status := 0
|
||||
LARGE := True
|
||||
TWOBYTE_BOOL := False
|
||||
__NOSTR__ := False
|
||||
|
||||
MEMORY VALIDATION PARAMETERS...
|
||||
CORE_CRC_CHECK := False
|
||||
VALIDATE_MEM_CHUNKS := False
|
||||
|
||||
SYSTEM DEBUG OPTIONS...
|
||||
DEBUG := False
|
||||
MCSTAT := False
|
||||
TRACKBACK := False
|
||||
FLUSH_FILES := False
|
||||
DEBUG_CORE0 := False
|
||||
DEBUG_RISC := False
|
||||
__TREE_BUG__ := False
|
||||
__TRACK_FILE_READS__ := False
|
||||
PAGE_SPACE := False
|
||||
LEAVE_NO_TRACE := True
|
||||
NULL_TRACE_STRS := False
|
||||
|
||||
TIME PARAMETERS...
|
||||
CLOCK_IS_LONG := False
|
||||
__DISPLAY_TIME__ := False
|
||||
__TREE_TIME__ := False
|
||||
__DISPLAY_ERRORS__ := False
|
||||
|
||||
API MACROS...
|
||||
__BMT01__ := True
|
||||
OPTIMIZE := True
|
||||
|
||||
END OF DEFINES.
|
||||
|
||||
|
||||
|
||||
... IMPLODE MEMORY ...
|
||||
|
||||
SWAP to DiskCache := False
|
||||
|
||||
FREEZE_GRP_PACKETS:= True
|
||||
|
||||
QueBug := 1000
|
||||
|
||||
sizeof(boolean) = 4
|
||||
sizeof(sizetype) = 4
|
||||
sizeof(chunkstruc) = 32
|
||||
|
||||
sizeof(shorttype ) = 2
|
||||
sizeof(idtype ) = 2
|
||||
sizeof(sizetype ) = 4
|
||||
sizeof(indextype ) = 4
|
||||
sizeof(numtype ) = 4
|
||||
sizeof(handletype) = 4
|
||||
sizeof(tokentype ) = 8
|
||||
|
||||
sizeof(short ) = 2
|
||||
sizeof(int ) = 4
|
||||
|
||||
sizeof(lt64 ) = 4
|
||||
sizeof(farlongtype) = 4
|
||||
sizeof(long ) = 8
|
||||
sizeof(longaddr ) = 8
|
||||
|
||||
sizeof(float ) = 4
|
||||
sizeof(double ) = 8
|
||||
|
||||
sizeof(addrtype ) = 8
|
||||
sizeof(char * ) = 8
|
||||
ALLOC CORE_1 :: 16
|
||||
BHOOLE NATH
|
||||
|
||||
OPEN File ./input/lendian.rnv
|
||||
*Status = 0
|
||||
DB HDR restored from FileVbn[ 0]
|
||||
DB BlkDirOffset : @ 2030c0
|
||||
DB BlkDirChunk : Chunk[ 10] AT Vbn[3146]
|
||||
DB BlkTknChunk : Chunk[ 11] AT Vbn[3147]
|
||||
DB BlkSizeChunk : Chunk[ 12] AT Vbn[3148]
|
||||
DB Handle Chunk's StackPtr = 20797
|
||||
|
||||
DB[ 1] LOADED; Handles= 20797
|
||||
KERNEL in CORE[ 1] Restored @ 4005c800
|
||||
|
||||
OPEN File ./input/lendian.wnv
|
||||
*Status = 0
|
||||
DB HDR restored from FileVbn[ 0]
|
||||
DB BlkDirOffset : @ 21c40
|
||||
DB BlkDirChunk : Chunk[ 31] AT Vbn[ 81]
|
||||
DB BlkTknChunk : Chunk[ 32] AT Vbn[ 82]
|
||||
DB BlkSizeChunk : Chunk[ 33] AT Vbn[ 83]
|
||||
DB Handle Chunk's StackPtr = 17
|
||||
|
||||
DB[ 2] LOADED; Handles= 17
|
||||
VORTEx_Status == -8 || fffffff8
|
||||
|
||||
BE HERE NOW !!!
|
||||
|
||||
|
||||
|
||||
... VORTEx ON LINE ...
|
||||
|
||||
|
||||
... END OF SESSION ...
|
||||
@ -0,0 +1,258 @@
|
||||
CREATE Db Header and Db Primal ...
|
||||
NEW DB [ 3] Created.
|
||||
|
||||
VORTEX INPUT PARAMETERS::
|
||||
MESSAGE FileName: smred.msg
|
||||
OUTPUT FileName: smred.out
|
||||
DISK CACHE FileName: NULL
|
||||
PART DB FileName: parts.db
|
||||
DRAW DB FileName: draw.db
|
||||
PERSON DB FileName: emp.db
|
||||
PERSONS Data FileName: ./input/persons.250
|
||||
PARTS Count : 100
|
||||
OUTER Loops : 1
|
||||
INNER Loops : 1
|
||||
LOOKUP Parts : 25
|
||||
DELETE Parts : 10
|
||||
STUFF Parts : 10
|
||||
DEPTH Traverse: 5
|
||||
% DECREASE Parts : 0
|
||||
% INCREASE LookUps : 0
|
||||
% INCREASE Deletes : 0
|
||||
% INCREASE Stuffs : 0
|
||||
FREEZE_PACKETS : 1
|
||||
ALLOC_CHUNKS : 10000
|
||||
EXTEND_CHUNKS : 5000
|
||||
DELETE Draw objects : True
|
||||
DELETE Part objects : False
|
||||
QUE_BUG : 1000
|
||||
VOID_BOUNDARY : 67108864
|
||||
VOID_RESERVE : 1048576
|
||||
|
||||
COMMIT_DBS : False
|
||||
|
||||
|
||||
|
||||
BMT TEST :: files...
|
||||
EdbName := PartLib
|
||||
EdbFileName := parts.db
|
||||
DrwName := DrawLib
|
||||
DrwFileName := draw.db
|
||||
EmpName := PersonLib
|
||||
EmpFileName := emp.db
|
||||
|
||||
Swap to DiskCache := False
|
||||
Freeze the cache := True
|
||||
|
||||
|
||||
BMT TEST :: parms...
|
||||
DeBug modulo := 1000
|
||||
Create Parts count:= 100
|
||||
Outer Loops := 1
|
||||
Inner Loops := 1
|
||||
Look Ups := 25
|
||||
Delete Parts := 10
|
||||
Stuff Parts := 10
|
||||
Traverse Limit := 5
|
||||
Delete Draws := True
|
||||
Delete Parts := False
|
||||
Delete ALL Parts := after every <mod 0>Outer Loop
|
||||
|
||||
INITIALIZE LIBRARY ::
|
||||
|
||||
INITIALIZE SCHEMA ::
|
||||
Primal_CreateDb Accessed !!!
|
||||
CREATE Db Header and Db Primal ...
|
||||
NEW DB [ 4] Created.
|
||||
PartLibCreate:: Db[ 4]; VpartsDir= 1
|
||||
|
||||
Part Count= 1
|
||||
|
||||
Initialize the Class maps
|
||||
LIST HEADS loaded ... DbListHead_Class = 207
|
||||
DbListNode_Class = 206
|
||||
|
||||
...NOTE... ShellLoadCode:: Class[ 228] will NOT be Activated.
|
||||
|
||||
|
||||
...NOTE... ShellLoadCode:: Class[ 229] will NOT be Activated.
|
||||
|
||||
Primal_CreateDb Accessed !!!
|
||||
CREATE Db Header and Db Primal ...
|
||||
NEW DB [ 5] Created.
|
||||
DrawLibCreate:: Db[ 5]; VpartsDir= 1
|
||||
|
||||
Initialize the Class maps of this schema.
|
||||
Primal_CreateDb Accessed !!!
|
||||
CREATE Db Header and Db Primal ...
|
||||
NEW DB [ 6] Created.
|
||||
|
||||
***NOTE*** Persons Library Extended!
|
||||
|
||||
Create <131072> Persons.
|
||||
ItNum 0. Person[ 6: 5]. Name= Riddell , Robert V. ;
|
||||
|
||||
LAST Person Read::
|
||||
ItNum 250. Person[ 6: 503]. Name= Gonzales , Warren X. ;
|
||||
|
||||
BUILD <Query0> for <Part2> class::
|
||||
|
||||
if (link[1].length >= 5) ::
|
||||
|
||||
Build Query2 for <Address> class::
|
||||
|
||||
if (State == CA || State == T*)
|
||||
|
||||
Build Query1 for <Person> class::
|
||||
|
||||
if (LastName >= H* && LastName <= P* && Query0(Residence)) ::
|
||||
|
||||
BUILD <Query3> for <DrawObj> class::
|
||||
|
||||
if (Id >= 3000
|
||||
&& (Id >= 3000 && Id <= 3001)
|
||||
&& Id >= 3002)
|
||||
|
||||
BUILD <Query4> for <NamedDrawObj> class::
|
||||
|
||||
if (Nam == Pre*
|
||||
|| (Nam == ??Mid??? || == Pre??Mid?? || == ??Post
|
||||
|| == Pre??Post || == ??Mid???Post || == Pre??Mid???Post)
|
||||
&& Id <= 7)
|
||||
SEED := 1008; Swap = False; RgnEntries = 135
|
||||
|
||||
OUTER LOOP [ 1] : NewParts = 100 LookUps = 25 StuffParts = 10.
|
||||
|
||||
Create 100 New Parts
|
||||
Create Part 1. Token[ 4: 2].
|
||||
|
||||
< 100> Parts Created. CurrentId= 100
|
||||
|
||||
Connect each instantiated Part TO 3 unique Parts
|
||||
Connect Part 1. Token[ 4: 2]
|
||||
Connect Part 25. Token[ 4: 26] FromList= 26.
|
||||
Connect Part 12. Token[ 4: 13] FromList= 13.
|
||||
Connect Part 59. Token[ 4: 60] FromList= 60.
|
||||
|
||||
SET <DrawObjs> entries::
|
||||
1. [ 5: 5] := <1 >; @[: 6]
|
||||
Iteration count = 100
|
||||
|
||||
SET <NamedDrawObjs> entries::
|
||||
1. [ 5: 39] := <14 >;
|
||||
Iteration count = 12
|
||||
|
||||
SET <LibRectangles> entries::
|
||||
1. [ 5: 23] := <8 >; @[: 24]
|
||||
Iteration count = 12
|
||||
|
||||
LIST <DbRectangles> entries::
|
||||
1. [ 5: 23]
|
||||
Iteration count = 12
|
||||
|
||||
SET <PersonNames > entries::
|
||||
Iteration count = 250
|
||||
|
||||
COMMIT All Image copies:: Release=<True>; Max Parts= 100
|
||||
< 100> Part images' Committed.
|
||||
< 0> are Named.
|
||||
< 50> Point images' Committed.
|
||||
< 81> Person images' Committed.
|
||||
|
||||
COMMIT Parts(* 100)
|
||||
|
||||
Commit TestObj_Class in <Primal> DB.
|
||||
ItNum 0. Token[ 0: 0]. TestObj Committed.
|
||||
< 0> TestObj images' Committed.
|
||||
|
||||
Commit CartesianPoint_Class in <Primal> DB.
|
||||
ItNum 0. Token[ 0: 0]. CartesianPoint Committed.
|
||||
< 0> CartesianPoint images' Committed.
|
||||
|
||||
BEGIN Inner Loop Sequence::.
|
||||
|
||||
INNER LOOP [ 1: 1] :
|
||||
|
||||
LOOK UP 25 Random Parts and Export each Part.
|
||||
|
||||
LookUp for 26 parts; Asserts = 8
|
||||
<Part2 > Asserts = 2; NULL Asserts = 3.
|
||||
<DrawObj > Asserts = 0; NULL Asserts = 5.
|
||||
<NamedObj > Asserts = 0; NULL Asserts = 0.
|
||||
<Person > Asserts = 0; NULL Asserts = 5.
|
||||
<TestObj > Asserts = 60; NULL Asserts = 0.
|
||||
|
||||
DELETE 10 Random Parts.
|
||||
|
||||
PartDelete :: Token[ 4: 91].
|
||||
PartDisconnect:: Token[ 4: 91] id:= 90 for each link.
|
||||
DisConnect link [ 0]:= 50; PartToken[ 51: 51].
|
||||
DisConnect link [ 1]:= 17; PartToken[ 18: 18].
|
||||
DisConnect link [ 2]:= 72; PartToken[ 73: 73].
|
||||
DeleteFromList:: Vchunk[ 4: 91]. (* 1)
|
||||
DisConnect FromList[ 0]:= 56; Token[ 57: 57].
|
||||
Vlists[ 89] := 100;
|
||||
|
||||
Delete for 11 parts;
|
||||
|
||||
Traverse Count= 0
|
||||
|
||||
TRAVERSE PartId[ 6] and all Connections to 5 Levels
|
||||
SEED In Traverse Part [ 4: 65] @ Level = 4.
|
||||
|
||||
Traverse Count= 357
|
||||
Traverse Asserts = 5. True Tests = 1
|
||||
< 5> DrawObj objects DELETED.
|
||||
< 2> are Named.
|
||||
< 2> Point objects DELETED.
|
||||
|
||||
CREATE 10 Additional Parts
|
||||
|
||||
Create 10 New Parts
|
||||
Create Part 101. Token[ 4: 102].
|
||||
|
||||
< 10> Parts Created. CurrentId= 110
|
||||
|
||||
Connect each instantiated Part TO 3 unique Parts
|
||||
|
||||
COMMIT All Image copies:: Release=<True>; Max Parts= 110
|
||||
< 81> Part images' Committed.
|
||||
< 0> are Named.
|
||||
< 38> Point images' Committed.
|
||||
< 31> Person images' Committed.
|
||||
|
||||
COMMIT Parts(* 100)
|
||||
|
||||
Commit TestObj_Class in <Primal> DB.
|
||||
ItNum 0. Token[ 3: 4]. TestObj Committed.
|
||||
< 15> TestObj images' Committed.
|
||||
|
||||
Commit CartesianPoint_Class in <Primal> DB.
|
||||
ItNum 0. Token[ 3: 3]. CartesianPoint Committed.
|
||||
< 16> CartesianPoint images' Committed.
|
||||
|
||||
DELETE All TestObj objects;
|
||||
|
||||
Delete TestObj_Class in <Primal> DB.
|
||||
ItNum 0. Token[ 3: 4]. TestObj Deleted.
|
||||
< 15> TestObj objects Deleted.
|
||||
|
||||
Commit CartesianPoint_Class in <Primal> DB.
|
||||
ItNum 0. Token[ 3: 3]. CartesianPoint Deleted.
|
||||
< 16> CartesianPoint objects Deleted.
|
||||
|
||||
DELETE TestObj and Point objects...
|
||||
|
||||
END INNER LOOP [ 1: 1].
|
||||
|
||||
DELETE All TestObj objects;
|
||||
|
||||
Delete TestObj_Class in <Primal> DB.
|
||||
< 0> TestObj objects Deleted.
|
||||
|
||||
Commit CartesianPoint_Class in <Primal> DB.
|
||||
< 0> CartesianPoint objects Deleted.
|
||||
|
||||
DELETE TestObj and Point objects...
|
||||
STATUS= -201
|
||||
V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!
|
||||
@ -0,0 +1,675 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.021303 # Number of seconds simulated
|
||||
sim_ticks 21302882000 # Number of ticks simulated
|
||||
final_tick 21302882000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 166406 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 166406 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 44538843 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 224724 # Number of bytes of host memory used
|
||||
host_seconds 478.30 # Real time elapsed on the host
|
||||
sim_insts 79591756 # Number of instructions simulated
|
||||
sim_ops 79591756 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 658624 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 10591744 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 11250368 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 658624 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 658624 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 7713792 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 7713792 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 10291 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 165496 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 175787 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 120528 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 120528 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 30917131 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 497197703 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 528114834 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 30917131 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 30917131 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 362100865 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 362100865 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 362100865 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 30917131 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 497197703 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 890215699 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
||||
system.cpu.dtb.read_hits 22551743 # DTB read hits
|
||||
system.cpu.dtb.read_misses 221888 # DTB read misses
|
||||
system.cpu.dtb.read_acv 31 # DTB read access violations
|
||||
system.cpu.dtb.read_accesses 22773631 # DTB read accesses
|
||||
system.cpu.dtb.write_hits 15815895 # DTB write hits
|
||||
system.cpu.dtb.write_misses 41880 # DTB write misses
|
||||
system.cpu.dtb.write_acv 3 # DTB write access violations
|
||||
system.cpu.dtb.write_accesses 15857775 # DTB write accesses
|
||||
system.cpu.dtb.data_hits 38367638 # DTB hits
|
||||
system.cpu.dtb.data_misses 263768 # DTB misses
|
||||
system.cpu.dtb.data_acv 34 # DTB access violations
|
||||
system.cpu.dtb.data_accesses 38631406 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 14242802 # ITB hits
|
||||
system.cpu.itb.fetch_misses 40881 # ITB misses
|
||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
||||
system.cpu.itb.fetch_accesses 14283683 # ITB accesses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.itb.write_hits 0 # DTB write hits
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.itb.write_acv 0 # DTB write access violations
|
||||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.itb.data_hits 0 # DTB hits
|
||||
system.cpu.itb.data_misses 0 # DTB misses
|
||||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 4583 # Number of system calls
|
||||
system.cpu.numCycles 42605767 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.BPredUnit.lookups 16836861 # Number of BP lookups
|
||||
system.cpu.BPredUnit.condPredicted 10841966 # Number of conditional branches predicted
|
||||
system.cpu.BPredUnit.condIncorrect 504890 # Number of conditional branches incorrect
|
||||
system.cpu.BPredUnit.BTBLookups 12277416 # Number of BTB lookups
|
||||
system.cpu.BPredUnit.BTBHits 7519870 # Number of BTB hits
|
||||
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu.BPredUnit.usedRAS 2023035 # Number of times the RAS was used to get a target.
|
||||
system.cpu.BPredUnit.RASInCorrect 69381 # Number of incorrect RAS predictions.
|
||||
system.cpu.fetch.icacheStallCycles 15349105 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.Insts 107382964 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.Branches 16836861 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.predictedBranches 9542905 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.Cycles 19934365 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.SquashCycles 2235712 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.BlockedCycles 4959568 # Number of cycles fetch has spent blocked
|
||||
system.cpu.fetch.MiscStallCycles 8744 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
||||
system.cpu.fetch.PendingTrapStallCycles 326008 # Number of stall cycles due to pending traps
|
||||
system.cpu.fetch.CacheLines 14242802 # Number of cache lines fetched
|
||||
system.cpu.fetch.IcacheSquashes 231176 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.rateDist::samples 42192824 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 2.545053 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 3.166401 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 22258459 52.75% 52.75% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 1558399 3.69% 56.45% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 1415455 3.35% 59.80% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 1535754 3.64% 63.44% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 4212607 9.98% 73.43% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 1888173 4.48% 77.90% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 696328 1.65% 79.55% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 1104060 2.62% 82.17% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 7523589 17.83% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::total 42192824 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.branchRate 0.395178 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.rate 2.520386 # Number of inst fetches per cycle
|
||||
system.cpu.decode.IdleCycles 16468277 # Number of cycles decode is idle
|
||||
system.cpu.decode.BlockedCycles 4517812 # Number of cycles decode is blocked
|
||||
system.cpu.decode.RunCycles 18984446 # Number of cycles decode is running
|
||||
system.cpu.decode.UnblockCycles 716137 # Number of cycles decode is unblocking
|
||||
system.cpu.decode.SquashCycles 1506152 # Number of cycles decode is squashing
|
||||
system.cpu.decode.BranchResolved 3833098 # Number of times decode resolved a branch
|
||||
system.cpu.decode.BranchMispred 111400 # Number of times decode detected a branch misprediction
|
||||
system.cpu.decode.DecodedInsts 105432186 # Number of instructions handled by decode
|
||||
system.cpu.decode.SquashedInsts 305241 # Number of squashed instructions handled by decode
|
||||
system.cpu.rename.SquashCycles 1506152 # Number of cycles rename is squashing
|
||||
system.cpu.rename.IdleCycles 16967340 # Number of cycles rename is idle
|
||||
system.cpu.rename.BlockCycles 2377848 # Number of cycles rename is blocking
|
||||
system.cpu.rename.serializeStallCycles 83482 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RunCycles 19155996 # Number of cycles rename is running
|
||||
system.cpu.rename.UnblockCycles 2102006 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RenamedInsts 103893842 # Number of instructions processed by rename
|
||||
system.cpu.rename.ROBFullEvents 209 # Number of times rename has blocked due to ROB full
|
||||
system.cpu.rename.IQFullEvents 2243 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.LSQFullEvents 1985062 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RenamedOperands 62645887 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RenameLookups 125253216 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.int_rename_lookups 124792086 # Number of integer rename lookups
|
||||
system.cpu.rename.fp_rename_lookups 461130 # Number of floating rename lookups
|
||||
system.cpu.rename.CommittedMaps 52546881 # Number of HB maps that are committed
|
||||
system.cpu.rename.UndoneMaps 10099006 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.serializingInsts 6339 # count of serializing insts renamed
|
||||
system.cpu.rename.tempSerializingInsts 6334 # count of temporary serializing insts renamed
|
||||
system.cpu.rename.skidInsts 4415607 # count of insts added to the skid buffer
|
||||
system.cpu.memDep0.insertedLoads 23483376 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 16437713 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.conflictingLoads 1109953 # Number of conflicting loads.
|
||||
system.cpu.memDep0.conflictingStores 422268 # Number of conflicting stores.
|
||||
system.cpu.iq.iqInstsAdded 91768592 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqNonSpecInstsAdded 5634 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqInstsIssued 89301611 # Number of instructions issued
|
||||
system.cpu.iq.iqSquashedInstsIssued 133191 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedInstsExamined 11574502 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedOperandsExamined 5080166 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 1051 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.issued_per_cycle::samples 42192824 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::mean 2.116512 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::stdev 2.120688 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::0 13823160 32.76% 32.76% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::1 6872678 16.29% 49.05% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::2 5530993 13.11% 62.16% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::3 4799446 11.38% 73.53% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::4 4794506 11.36% 84.90% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::5 2657744 6.30% 91.20% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::6 1943834 4.61% 95.80% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::7 1324843 3.14% 98.94% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::8 445620 1.06% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::total 42192824 # Number of insts issued each cycle
|
||||
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntAlu 129735 6.85% 6.85% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntMult 1 0.00% 6.85% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntDiv 0 0.00% 6.85% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.85% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.85% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.85% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatMult 0 0.00% 6.85% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.85% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.85% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.85% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.85% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.85% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.85% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.85% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.85% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdMult 0 0.00% 6.85% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.85% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdShift 0 0.00% 6.85% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.85% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.85% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.85% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.85% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.85% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.85% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.85% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.85% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.85% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.85% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.85% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::MemRead 797111 42.11% 48.97% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::MemWrite 966009 51.03% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntAlu 49865595 55.84% 55.84% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntMult 43886 0.05% 55.89% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 55.89% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatAdd 121283 0.14% 56.02% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatCmp 87 0.00% 56.02% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatCvt 121847 0.14% 56.16% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatMult 55 0.00% 56.16% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatDiv 38973 0.04% 56.20% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.20% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.20% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.20% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.20% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.20% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.20% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.20% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.20% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.20% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.20% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.20% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.20% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.20% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.20% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.20% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.20% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.20% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.20% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.20% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.20% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.20% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::MemRead 23075616 25.84% 82.04% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::MemWrite 16034269 17.96% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::total 89301611 # Type of FU issued
|
||||
system.cpu.iq.rate 2.095998 # Inst issue rate
|
||||
system.cpu.iq.fu_busy_cnt 1892856 # FU busy when requested
|
||||
system.cpu.iq.fu_busy_rate 0.021196 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.int_inst_queue_reads 222206616 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_writes 102943544 # Number of integer instruction queue writes
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 87154270 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.fp_inst_queue_reads 615477 # Number of floating instruction queue reads
|
||||
system.cpu.iq.fp_inst_queue_writes 421862 # Number of floating instruction queue writes
|
||||
system.cpu.iq.fp_inst_queue_wakeup_accesses 299078 # Number of floating instruction queue wakeup accesses
|
||||
system.cpu.iq.int_alu_accesses 90886504 # Number of integer alu accesses
|
||||
system.cpu.iq.fp_alu_accesses 307963 # Number of floating point alu accesses
|
||||
system.cpu.iew.lsq.thread0.forwLoads 1459837 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread0.squashedLoads 3206738 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread0.ignoredResponses 5121 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread0.memOrderViolation 17710 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread0.squashedStores 1824336 # Number of stores squashed
|
||||
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
||||
system.cpu.iew.lsq.thread0.rescheduledLoads 2474 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread0.cacheBlocked 56 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||||
system.cpu.iew.iewSquashCycles 1506152 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewBlockCycles 1422947 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewUnblockCycles 61908 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.iewDispatchedInsts 101335985 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewDispSquashedInsts 260919 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispLoadInsts 23483376 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispStoreInsts 16437713 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 5634 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewIQFullEvents 42556 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.iewLSQFullEvents 655 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.memOrderViolationEvents 17710 # Number of memory order violations
|
||||
system.cpu.iew.predictedTakenIncorrect 285901 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.iew.predictedNotTakenIncorrect 175983 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.branchMispredicts 461884 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewExecutedInsts 88268407 # Number of executed instructions
|
||||
system.cpu.iew.iewExecLoadInsts 22778571 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 1033204 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
||||
system.cpu.iew.exec_nop 9561759 # number of nop insts executed
|
||||
system.cpu.iew.exec_refs 38636897 # number of memory reference insts executed
|
||||
system.cpu.iew.exec_branches 15172966 # Number of branches executed
|
||||
system.cpu.iew.exec_stores 15858326 # Number of stores executed
|
||||
system.cpu.iew.exec_rate 2.071748 # Inst execution rate
|
||||
system.cpu.iew.wb_sent 87882567 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.wb_count 87453348 # cumulative count of insts written-back
|
||||
system.cpu.iew.wb_producers 33493281 # num instructions producing a value
|
||||
system.cpu.iew.wb_consumers 43663372 # num instructions consuming a value
|
||||
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
||||
system.cpu.iew.wb_rate 2.052618 # insts written-back per cycle
|
||||
system.cpu.iew.wb_fanout 0.767080 # average fanout of values written-back
|
||||
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||
system.cpu.commit.commitCommittedInsts 88340672 # The number of committed instructions
|
||||
system.cpu.commit.commitCommittedOps 88340672 # The number of committed instructions
|
||||
system.cpu.commit.commitSquashedInsts 9892654 # The number of squashed insts skipped by commit
|
||||
system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu.commit.branchMispredicts 396008 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.committed_per_cycle::samples 40686672 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::mean 2.171243 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::stdev 2.822339 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::0 17747243 43.62% 43.62% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::1 7065292 17.37% 60.98% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::2 3424426 8.42% 69.40% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::3 2111790 5.19% 74.59% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::4 2029147 4.99% 79.58% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::5 1183341 2.91% 82.49% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::6 1120057 2.75% 85.24% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::7 705485 1.73% 86.97% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::8 5299891 13.03% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::total 40686672 # Number of insts commited each cycle
|
||||
system.cpu.commit.committedInsts 88340672 # Number of instructions committed
|
||||
system.cpu.commit.committedOps 88340672 # Number of ops (including micro ops) committed
|
||||
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
||||
system.cpu.commit.refs 34890015 # Number of memory references committed
|
||||
system.cpu.commit.loads 20276638 # Number of loads committed
|
||||
system.cpu.commit.membars 0 # Number of memory barriers committed
|
||||
system.cpu.commit.branches 13754477 # Number of branches committed
|
||||
system.cpu.commit.fp_insts 267754 # Number of committed floating point instructions.
|
||||
system.cpu.commit.int_insts 77942044 # Number of committed integer instructions.
|
||||
system.cpu.commit.function_calls 1661057 # Number of function calls committed.
|
||||
system.cpu.commit.bw_lim_events 5299891 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
||||
system.cpu.rob.rob_reads 132302765 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 197976180 # The number of ROB writes
|
||||
system.cpu.timesIdled 17931 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 412943 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.committedInsts 79591756 # Number of Instructions Simulated
|
||||
system.cpu.committedOps 79591756 # Number of Ops (including micro ops) Simulated
|
||||
system.cpu.committedInsts_total 79591756 # Number of Instructions Simulated
|
||||
system.cpu.cpi 0.535304 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 0.535304 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 1.868098 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 1.868098 # IPC: Total IPC of All Threads
|
||||
system.cpu.int_regfile_reads 116852046 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 57987678 # number of integer regfile writes
|
||||
system.cpu.fp_regfile_reads 254259 # number of floating regfile reads
|
||||
system.cpu.fp_regfile_writes 241396 # number of floating regfile writes
|
||||
system.cpu.misc_regfile_reads 38319 # number of misc regfile reads
|
||||
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
|
||||
system.cpu.icache.replacements 94879 # number of replacements
|
||||
system.cpu.icache.tagsinuse 1931.404224 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 14141018 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 96927 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 145.893487 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 17852736000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 1931.404224 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.943068 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.943068 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 14141018 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 14141018 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 14141018 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 14141018 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 14141018 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 14141018 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 101784 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 101784 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 101784 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 101784 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 101784 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 101784 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 964559500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 964559500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 964559500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 964559500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 964559500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 964559500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 14242802 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 14242802 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 14242802 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 14242802 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 14242802 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 14242802 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.007146 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.007146 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.007146 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.007146 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.007146 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.007146 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 9476.533640 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 9476.533640 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 9476.533640 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 9476.533640 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 9476.533640 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 9476.533640 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4856 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::total 4856 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::cpu.inst 4856 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::total 4856 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::cpu.inst 4856 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::total 4856 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 96928 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 96928 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 96928 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 96928 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 96928 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 96928 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 566036000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 566036000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 566036000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 566036000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 566036000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 566036000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006805 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006805 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006805 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.006805 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006805 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.006805 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 5839.757346 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 5839.757346 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 5839.757346 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 5839.757346 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 5839.757346 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 5839.757346 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 201683 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 4076.258401 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 34409774 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 205779 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 167.217131 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 158059000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 4076.258401 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.995180 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.995180 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 20831540 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 20831540 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 13578164 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 13578164 # number of WriteReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::cpu.data 70 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::total 70 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 34409704 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 34409704 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 34409704 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 34409704 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 257782 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 257782 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 1035213 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 1035213 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 1292995 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 1292995 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 1292995 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 1292995 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 8279025500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 8279025500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 34022399498 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 34022399498 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 42301424998 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 42301424998 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 42301424998 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 42301424998 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 21089322 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 21089322 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 70 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::total 70 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 35702699 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 35702699 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 35702699 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 35702699 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012223 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.012223 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.070840 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.070840 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.036216 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.036216 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.036216 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.036216 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32116.383223 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 32116.383223 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 32865.120027 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 32865.120027 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 32715.845767 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 32715.845767 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 32715.845767 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 32715.845767 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 96500 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 15 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 6433.333333 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 161705 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 161705 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 195431 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 195431 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 891785 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 891785 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 1087216 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 1087216 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 1087216 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 1087216 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62351 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 62351 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143428 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 143428 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 205779 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 205779 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 205779 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 205779 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1281958000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 1281958000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4735775500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 4735775500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6017733500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 6017733500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6017733500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 6017733500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002957 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002957 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009815 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009815 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005764 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.005764 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005764 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.005764 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 20560.343860 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 20560.343860 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33018.486627 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33018.486627 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29243.671609 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 29243.671609 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29243.671609 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 29243.671609 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 149461 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 18973.137542 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 143447 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 174828 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 0.820504 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::writebacks 15709.127164 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 1544.894785 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 1719.115593 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.479405 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.047146 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.052463 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.579014 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 86637 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 28247 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 114884 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 161705 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 161705 # number of Writeback hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 12036 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 12036 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 86637 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 40283 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 126920 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 86637 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 40283 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 126920 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 10291 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.data 34099 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 44390 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 131397 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 131397 # number of ReadExReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 10291 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 165496 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 175787 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 10291 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 165496 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 175787 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 353191500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1174547500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 1527739000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4525137500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 4525137500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 353191500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 5699685000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 6052876500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 353191500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 5699685000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 6052876500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 96928 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 62346 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 159274 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 161705 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 161705 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 143433 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 143433 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 96928 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 205779 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 302707 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 96928 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 205779 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 302707 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.106172 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.546932 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.278702 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.916086 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.916086 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.106172 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.804241 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.580717 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.106172 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.804241 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.580717 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34320.425615 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34445.218335 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 34416.287452 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34438.666788 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34438.666788 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34320.425615 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34440.016677 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 34433.015524 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34320.425615 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34440.016677 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 34433.015524 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 29000 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 11 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 2636.363636 # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks::writebacks 120528 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 120528 # number of writebacks
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 10291 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 34099 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::total 44390 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 131397 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 131397 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 10291 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 165496 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 175787 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 10291 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 165496 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 175787 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 319907000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1058267500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1378174500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4118158500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4118158500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 319907000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5176426000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 5496333000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 319907000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5176426000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 5496333000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.106172 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.546932 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.278702 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.916086 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.916086 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.106172 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.804241 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.580717 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.106172 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.804241 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.580717 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31086.094646 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31035.147658 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31046.958774 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31341.343410 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31341.343410 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31086.094646 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31278.254459 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31267.004955 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31086.094646 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31278.254459 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31267.004955 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
@ -0,0 +1,117 @@
|
||||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
full_system=false
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
||||
[system]
|
||||
type=System
|
||||
children=cpu membus physmem
|
||||
boot_osflags=a
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
mem_mode=atomic
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
readfile=
|
||||
symbolfile=
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.membus.slave[0]
|
||||
|
||||
[system.cpu]
|
||||
type=AtomicSimpleCPU
|
||||
children=dtb interrupts itb tracer workload
|
||||
checker=Null
|
||||
clock=500
|
||||
cpu_id=0
|
||||
defer_registration=false
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
fastmem=false
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
interrupts=system.cpu.interrupts
|
||||
itb=system.cpu.itb
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
phase=0
|
||||
profile=0
|
||||
progress_interval=0
|
||||
simulate_data_stalls=false
|
||||
simulate_inst_stalls=false
|
||||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
width=1
|
||||
workload=system.cpu.workload
|
||||
dcache_port=system.membus.slave[2]
|
||||
icache_port=system.membus.slave[1]
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=AlphaTLB
|
||||
size=64
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=AlphaInterrupts
|
||||
|
||||
[system.cpu.itb]
|
||||
type=AlphaTLB
|
||||
size=48
|
||||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
|
||||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=vortex lendian.raw
|
||||
cwd=build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/simple-atomic
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
ppid=99
|
||||
simpoint=0
|
||||
system=system
|
||||
uid=100
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
master=system.physmem.port[0]
|
||||
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.membus.master[0]
|
||||
|
||||
@ -0,0 +1,7 @@
|
||||
warn: CoherentBus system.membus has no snooping ports attached!
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: Prefetch instructions in Alpha do not do anything
|
||||
warn: Prefetch instructions in Alpha do not do anything
|
||||
warn: Prefetch instructions in Alpha do not do anything
|
||||
warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
|
||||
hack: be nice to actually delete the event here
|
||||
11
simulators/gem5/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/simout
Executable file
11
simulators/gem5/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/simout
Executable file
@ -0,0 +1,11 @@
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jun 4 2012 11:50:11
|
||||
gem5 started Jun 4 2012 14:30:37
|
||||
gem5 executing on zizzer
|
||||
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/simple-atomic
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
Exiting @ tick 44221003000 because target called exit()
|
||||
@ -0,0 +1,158 @@
|
||||
|
||||
SYSTEM TYPE...
|
||||
__ZTC__ := False
|
||||
__UNIX__ := True
|
||||
__RISC__ := True
|
||||
SPEC_CPU2000_LP64 := True
|
||||
__MAC__ := False
|
||||
__BCC__ := False
|
||||
__BORLANDC__ := False
|
||||
__GUI__ := False
|
||||
__WTC__ := False
|
||||
__HP__ := False
|
||||
|
||||
CODE OPTIONS...
|
||||
__MACROIZE_HM__ := True
|
||||
__MACROIZE_MEM__ := True
|
||||
ENV01 := True
|
||||
USE_HPP_STYPE_HDRS := False
|
||||
USE_H_STYPE_HDRS := False
|
||||
|
||||
CODE INCLUSION PARAMETERS...
|
||||
INCLUDE_ALL_CODE := False
|
||||
INCLUDE_DELETE_CODE := True
|
||||
__SWAP_GRP_POS__ := True
|
||||
__INCLUDE_MTRX__ := False
|
||||
__BAD_CODE__ := False
|
||||
API_INCLUDE := False
|
||||
BE_CAREFUL := False
|
||||
OLDWAY := False
|
||||
NOTUSED := False
|
||||
|
||||
SYSTEM PARAMETERS...
|
||||
EXT_ENUM := 999999999L
|
||||
CHUNK_CONSTANT := 55555555
|
||||
CORE_CONSTANT := 55555555
|
||||
CORE_LIMIT := 20971520
|
||||
CorePage_Size := 384000
|
||||
ALIGN_BYTES := True
|
||||
CORE_BLOCK_ALIGN := 8
|
||||
FAR_MEM := False
|
||||
|
||||
MEMORY MANAGEMENT PARAMETERS...
|
||||
SYSTEM_ALLOC := True
|
||||
SYSTEM_FREESTORE := True
|
||||
__NO_DISKCACHE__ := False
|
||||
__FREEZE_VCHUNKS__ := True
|
||||
__FREEZE_GRP_PACKETS__ := True
|
||||
__MINIMIZE_TREE_CACHE__:= True
|
||||
|
||||
SYSTEM STD PARAMETERS...
|
||||
__STDOUT__ := False
|
||||
NULL := 0
|
||||
LPTR := False
|
||||
False_Status := 1
|
||||
True_Status := 0
|
||||
LARGE := True
|
||||
TWOBYTE_BOOL := False
|
||||
__NOSTR__ := False
|
||||
|
||||
MEMORY VALIDATION PARAMETERS...
|
||||
CORE_CRC_CHECK := False
|
||||
VALIDATE_MEM_CHUNKS := False
|
||||
|
||||
SYSTEM DEBUG OPTIONS...
|
||||
DEBUG := False
|
||||
MCSTAT := False
|
||||
TRACKBACK := False
|
||||
FLUSH_FILES := False
|
||||
DEBUG_CORE0 := False
|
||||
DEBUG_RISC := False
|
||||
__TREE_BUG__ := False
|
||||
__TRACK_FILE_READS__ := False
|
||||
PAGE_SPACE := False
|
||||
LEAVE_NO_TRACE := True
|
||||
NULL_TRACE_STRS := False
|
||||
|
||||
TIME PARAMETERS...
|
||||
CLOCK_IS_LONG := False
|
||||
__DISPLAY_TIME__ := False
|
||||
__TREE_TIME__ := False
|
||||
__DISPLAY_ERRORS__ := False
|
||||
|
||||
API MACROS...
|
||||
__BMT01__ := True
|
||||
OPTIMIZE := True
|
||||
|
||||
END OF DEFINES.
|
||||
|
||||
|
||||
|
||||
... IMPLODE MEMORY ...
|
||||
|
||||
SWAP to DiskCache := False
|
||||
|
||||
FREEZE_GRP_PACKETS:= True
|
||||
|
||||
QueBug := 1000
|
||||
|
||||
sizeof(boolean) = 4
|
||||
sizeof(sizetype) = 4
|
||||
sizeof(chunkstruc) = 32
|
||||
|
||||
sizeof(shorttype ) = 2
|
||||
sizeof(idtype ) = 2
|
||||
sizeof(sizetype ) = 4
|
||||
sizeof(indextype ) = 4
|
||||
sizeof(numtype ) = 4
|
||||
sizeof(handletype) = 4
|
||||
sizeof(tokentype ) = 8
|
||||
|
||||
sizeof(short ) = 2
|
||||
sizeof(int ) = 4
|
||||
|
||||
sizeof(lt64 ) = 4
|
||||
sizeof(farlongtype) = 4
|
||||
sizeof(long ) = 8
|
||||
sizeof(longaddr ) = 8
|
||||
|
||||
sizeof(float ) = 4
|
||||
sizeof(double ) = 8
|
||||
|
||||
sizeof(addrtype ) = 8
|
||||
sizeof(char * ) = 8
|
||||
ALLOC CORE_1 :: 16
|
||||
BHOOLE NATH
|
||||
|
||||
OPEN File ./input/lendian.rnv
|
||||
*Status = 0
|
||||
DB HDR restored from FileVbn[ 0]
|
||||
DB BlkDirOffset : @ 2030c0
|
||||
DB BlkDirChunk : Chunk[ 10] AT Vbn[3146]
|
||||
DB BlkTknChunk : Chunk[ 11] AT Vbn[3147]
|
||||
DB BlkSizeChunk : Chunk[ 12] AT Vbn[3148]
|
||||
DB Handle Chunk's StackPtr = 20797
|
||||
|
||||
DB[ 1] LOADED; Handles= 20797
|
||||
KERNEL in CORE[ 1] Restored @ 4005c800
|
||||
|
||||
OPEN File ./input/lendian.wnv
|
||||
*Status = 0
|
||||
DB HDR restored from FileVbn[ 0]
|
||||
DB BlkDirOffset : @ 21c40
|
||||
DB BlkDirChunk : Chunk[ 31] AT Vbn[ 81]
|
||||
DB BlkTknChunk : Chunk[ 32] AT Vbn[ 82]
|
||||
DB BlkSizeChunk : Chunk[ 33] AT Vbn[ 83]
|
||||
DB Handle Chunk's StackPtr = 17
|
||||
|
||||
DB[ 2] LOADED; Handles= 17
|
||||
VORTEx_Status == -8 || fffffff8
|
||||
|
||||
BE HERE NOW !!!
|
||||
|
||||
|
||||
|
||||
... VORTEx ON LINE ...
|
||||
|
||||
|
||||
... END OF SESSION ...
|
||||
@ -0,0 +1,258 @@
|
||||
CREATE Db Header and Db Primal ...
|
||||
NEW DB [ 3] Created.
|
||||
|
||||
VORTEX INPUT PARAMETERS::
|
||||
MESSAGE FileName: smred.msg
|
||||
OUTPUT FileName: smred.out
|
||||
DISK CACHE FileName: NULL
|
||||
PART DB FileName: parts.db
|
||||
DRAW DB FileName: draw.db
|
||||
PERSON DB FileName: emp.db
|
||||
PERSONS Data FileName: ./input/persons.250
|
||||
PARTS Count : 100
|
||||
OUTER Loops : 1
|
||||
INNER Loops : 1
|
||||
LOOKUP Parts : 25
|
||||
DELETE Parts : 10
|
||||
STUFF Parts : 10
|
||||
DEPTH Traverse: 5
|
||||
% DECREASE Parts : 0
|
||||
% INCREASE LookUps : 0
|
||||
% INCREASE Deletes : 0
|
||||
% INCREASE Stuffs : 0
|
||||
FREEZE_PACKETS : 1
|
||||
ALLOC_CHUNKS : 10000
|
||||
EXTEND_CHUNKS : 5000
|
||||
DELETE Draw objects : True
|
||||
DELETE Part objects : False
|
||||
QUE_BUG : 1000
|
||||
VOID_BOUNDARY : 67108864
|
||||
VOID_RESERVE : 1048576
|
||||
|
||||
COMMIT_DBS : False
|
||||
|
||||
|
||||
|
||||
BMT TEST :: files...
|
||||
EdbName := PartLib
|
||||
EdbFileName := parts.db
|
||||
DrwName := DrawLib
|
||||
DrwFileName := draw.db
|
||||
EmpName := PersonLib
|
||||
EmpFileName := emp.db
|
||||
|
||||
Swap to DiskCache := False
|
||||
Freeze the cache := True
|
||||
|
||||
|
||||
BMT TEST :: parms...
|
||||
DeBug modulo := 1000
|
||||
Create Parts count:= 100
|
||||
Outer Loops := 1
|
||||
Inner Loops := 1
|
||||
Look Ups := 25
|
||||
Delete Parts := 10
|
||||
Stuff Parts := 10
|
||||
Traverse Limit := 5
|
||||
Delete Draws := True
|
||||
Delete Parts := False
|
||||
Delete ALL Parts := after every <mod 0>Outer Loop
|
||||
|
||||
INITIALIZE LIBRARY ::
|
||||
|
||||
INITIALIZE SCHEMA ::
|
||||
Primal_CreateDb Accessed !!!
|
||||
CREATE Db Header and Db Primal ...
|
||||
NEW DB [ 4] Created.
|
||||
PartLibCreate:: Db[ 4]; VpartsDir= 1
|
||||
|
||||
Part Count= 1
|
||||
|
||||
Initialize the Class maps
|
||||
LIST HEADS loaded ... DbListHead_Class = 207
|
||||
DbListNode_Class = 206
|
||||
|
||||
...NOTE... ShellLoadCode:: Class[ 228] will NOT be Activated.
|
||||
|
||||
|
||||
...NOTE... ShellLoadCode:: Class[ 229] will NOT be Activated.
|
||||
|
||||
Primal_CreateDb Accessed !!!
|
||||
CREATE Db Header and Db Primal ...
|
||||
NEW DB [ 5] Created.
|
||||
DrawLibCreate:: Db[ 5]; VpartsDir= 1
|
||||
|
||||
Initialize the Class maps of this schema.
|
||||
Primal_CreateDb Accessed !!!
|
||||
CREATE Db Header and Db Primal ...
|
||||
NEW DB [ 6] Created.
|
||||
|
||||
***NOTE*** Persons Library Extended!
|
||||
|
||||
Create <131072> Persons.
|
||||
ItNum 0. Person[ 6: 5]. Name= Riddell , Robert V. ;
|
||||
|
||||
LAST Person Read::
|
||||
ItNum 250. Person[ 6: 503]. Name= Gonzales , Warren X. ;
|
||||
|
||||
BUILD <Query0> for <Part2> class::
|
||||
|
||||
if (link[1].length >= 5) ::
|
||||
|
||||
Build Query2 for <Address> class::
|
||||
|
||||
if (State == CA || State == T*)
|
||||
|
||||
Build Query1 for <Person> class::
|
||||
|
||||
if (LastName >= H* && LastName <= P* && Query0(Residence)) ::
|
||||
|
||||
BUILD <Query3> for <DrawObj> class::
|
||||
|
||||
if (Id >= 3000
|
||||
&& (Id >= 3000 && Id <= 3001)
|
||||
&& Id >= 3002)
|
||||
|
||||
BUILD <Query4> for <NamedDrawObj> class::
|
||||
|
||||
if (Nam == Pre*
|
||||
|| (Nam == ??Mid??? || == Pre??Mid?? || == ??Post
|
||||
|| == Pre??Post || == ??Mid???Post || == Pre??Mid???Post)
|
||||
&& Id <= 7)
|
||||
SEED := 1008; Swap = False; RgnEntries = 135
|
||||
|
||||
OUTER LOOP [ 1] : NewParts = 100 LookUps = 25 StuffParts = 10.
|
||||
|
||||
Create 100 New Parts
|
||||
Create Part 1. Token[ 4: 2].
|
||||
|
||||
< 100> Parts Created. CurrentId= 100
|
||||
|
||||
Connect each instantiated Part TO 3 unique Parts
|
||||
Connect Part 1. Token[ 4: 2]
|
||||
Connect Part 25. Token[ 4: 26] FromList= 26.
|
||||
Connect Part 12. Token[ 4: 13] FromList= 13.
|
||||
Connect Part 59. Token[ 4: 60] FromList= 60.
|
||||
|
||||
SET <DrawObjs> entries::
|
||||
1. [ 5: 5] := <1 >; @[: 6]
|
||||
Iteration count = 100
|
||||
|
||||
SET <NamedDrawObjs> entries::
|
||||
1. [ 5: 39] := <14 >;
|
||||
Iteration count = 12
|
||||
|
||||
SET <LibRectangles> entries::
|
||||
1. [ 5: 23] := <8 >; @[: 24]
|
||||
Iteration count = 12
|
||||
|
||||
LIST <DbRectangles> entries::
|
||||
1. [ 5: 23]
|
||||
Iteration count = 12
|
||||
|
||||
SET <PersonNames > entries::
|
||||
Iteration count = 250
|
||||
|
||||
COMMIT All Image copies:: Release=<True>; Max Parts= 100
|
||||
< 100> Part images' Committed.
|
||||
< 0> are Named.
|
||||
< 50> Point images' Committed.
|
||||
< 81> Person images' Committed.
|
||||
|
||||
COMMIT Parts(* 100)
|
||||
|
||||
Commit TestObj_Class in <Primal> DB.
|
||||
ItNum 0. Token[ 0: 0]. TestObj Committed.
|
||||
< 0> TestObj images' Committed.
|
||||
|
||||
Commit CartesianPoint_Class in <Primal> DB.
|
||||
ItNum 0. Token[ 0: 0]. CartesianPoint Committed.
|
||||
< 0> CartesianPoint images' Committed.
|
||||
|
||||
BEGIN Inner Loop Sequence::.
|
||||
|
||||
INNER LOOP [ 1: 1] :
|
||||
|
||||
LOOK UP 25 Random Parts and Export each Part.
|
||||
|
||||
LookUp for 26 parts; Asserts = 8
|
||||
<Part2 > Asserts = 2; NULL Asserts = 3.
|
||||
<DrawObj > Asserts = 0; NULL Asserts = 5.
|
||||
<NamedObj > Asserts = 0; NULL Asserts = 0.
|
||||
<Person > Asserts = 0; NULL Asserts = 5.
|
||||
<TestObj > Asserts = 60; NULL Asserts = 0.
|
||||
|
||||
DELETE 10 Random Parts.
|
||||
|
||||
PartDelete :: Token[ 4: 91].
|
||||
PartDisconnect:: Token[ 4: 91] id:= 90 for each link.
|
||||
DisConnect link [ 0]:= 50; PartToken[ 51: 51].
|
||||
DisConnect link [ 1]:= 17; PartToken[ 18: 18].
|
||||
DisConnect link [ 2]:= 72; PartToken[ 73: 73].
|
||||
DeleteFromList:: Vchunk[ 4: 91]. (* 1)
|
||||
DisConnect FromList[ 0]:= 56; Token[ 57: 57].
|
||||
Vlists[ 89] := 100;
|
||||
|
||||
Delete for 11 parts;
|
||||
|
||||
Traverse Count= 0
|
||||
|
||||
TRAVERSE PartId[ 6] and all Connections to 5 Levels
|
||||
SEED In Traverse Part [ 4: 65] @ Level = 4.
|
||||
|
||||
Traverse Count= 357
|
||||
Traverse Asserts = 5. True Tests = 1
|
||||
< 5> DrawObj objects DELETED.
|
||||
< 2> are Named.
|
||||
< 2> Point objects DELETED.
|
||||
|
||||
CREATE 10 Additional Parts
|
||||
|
||||
Create 10 New Parts
|
||||
Create Part 101. Token[ 4: 102].
|
||||
|
||||
< 10> Parts Created. CurrentId= 110
|
||||
|
||||
Connect each instantiated Part TO 3 unique Parts
|
||||
|
||||
COMMIT All Image copies:: Release=<True>; Max Parts= 110
|
||||
< 81> Part images' Committed.
|
||||
< 0> are Named.
|
||||
< 38> Point images' Committed.
|
||||
< 31> Person images' Committed.
|
||||
|
||||
COMMIT Parts(* 100)
|
||||
|
||||
Commit TestObj_Class in <Primal> DB.
|
||||
ItNum 0. Token[ 3: 4]. TestObj Committed.
|
||||
< 15> TestObj images' Committed.
|
||||
|
||||
Commit CartesianPoint_Class in <Primal> DB.
|
||||
ItNum 0. Token[ 3: 3]. CartesianPoint Committed.
|
||||
< 16> CartesianPoint images' Committed.
|
||||
|
||||
DELETE All TestObj objects;
|
||||
|
||||
Delete TestObj_Class in <Primal> DB.
|
||||
ItNum 0. Token[ 3: 4]. TestObj Deleted.
|
||||
< 15> TestObj objects Deleted.
|
||||
|
||||
Commit CartesianPoint_Class in <Primal> DB.
|
||||
ItNum 0. Token[ 3: 3]. CartesianPoint Deleted.
|
||||
< 16> CartesianPoint objects Deleted.
|
||||
|
||||
DELETE TestObj and Point objects...
|
||||
|
||||
END INNER LOOP [ 1: 1].
|
||||
|
||||
DELETE All TestObj objects;
|
||||
|
||||
Delete TestObj_Class in <Primal> DB.
|
||||
< 0> TestObj objects Deleted.
|
||||
|
||||
Commit CartesianPoint_Class in <Primal> DB.
|
||||
< 0> CartesianPoint objects Deleted.
|
||||
|
||||
DELETE TestObj and Point objects...
|
||||
STATUS= -201
|
||||
V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!
|
||||
@ -0,0 +1,92 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.044221 # Number of seconds simulated
|
||||
sim_ticks 44221003000 # Number of ticks simulated
|
||||
final_tick 44221003000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 3187268 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 3187266 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1595460185 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 214012 # Number of bytes of host memory used
|
||||
host_seconds 27.72 # Real time elapsed on the host
|
||||
sim_insts 88340673 # Number of instructions simulated
|
||||
sim_ops 88340673 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 353752292 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 126702647 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 480454939 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 353752292 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 353752292 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::cpu.data 91652896 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 91652896 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 88438073 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 20276638 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 108714711 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::cpu.data 14613377 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 14613377 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 7999644241 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 2865214229 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 10864858470 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 7999644241 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 7999644241 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::cpu.data 2072610067 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 2072610067 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 7999644241 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 4937824296 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 12937468537 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
||||
system.cpu.dtb.read_hits 20276638 # DTB read hits
|
||||
system.cpu.dtb.read_misses 90148 # DTB read misses
|
||||
system.cpu.dtb.read_acv 0 # DTB read access violations
|
||||
system.cpu.dtb.read_accesses 20366786 # DTB read accesses
|
||||
system.cpu.dtb.write_hits 14613377 # DTB write hits
|
||||
system.cpu.dtb.write_misses 7252 # DTB write misses
|
||||
system.cpu.dtb.write_acv 0 # DTB write access violations
|
||||
system.cpu.dtb.write_accesses 14620629 # DTB write accesses
|
||||
system.cpu.dtb.data_hits 34890015 # DTB hits
|
||||
system.cpu.dtb.data_misses 97400 # DTB misses
|
||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
||||
system.cpu.dtb.data_accesses 34987415 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 88438073 # ITB hits
|
||||
system.cpu.itb.fetch_misses 3934 # ITB misses
|
||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
||||
system.cpu.itb.fetch_accesses 88442007 # ITB accesses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.itb.write_hits 0 # DTB write hits
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.itb.write_acv 0 # DTB write access violations
|
||||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.itb.data_hits 0 # DTB hits
|
||||
system.cpu.itb.data_misses 0 # DTB misses
|
||||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 4583 # Number of system calls
|
||||
system.cpu.numCycles 88442007 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 88340673 # Number of instructions committed
|
||||
system.cpu.committedOps 88340673 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 78039444 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 267757 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 3321606 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 8920848 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 78039444 # number of integer instructions
|
||||
system.cpu.num_fp_insts 267757 # number of float instructions
|
||||
system.cpu.num_int_register_reads 105931758 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 52319251 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 229023 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 227630 # number of times the floating registers were written
|
||||
system.cpu.num_mem_refs 34987415 # number of memory refs
|
||||
system.cpu.num_load_insts 20366786 # Number of load instructions
|
||||
system.cpu.num_store_insts 14620629 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 88442007 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
@ -0,0 +1,198 @@
|
||||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
full_system=false
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
||||
[system]
|
||||
type=System
|
||||
children=cpu membus physmem
|
||||
boot_osflags=a
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
mem_mode=atomic
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
readfile=
|
||||
symbolfile=
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.membus.slave[0]
|
||||
|
||||
[system.cpu]
|
||||
type=TimingSimpleCPU
|
||||
children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
|
||||
checker=Null
|
||||
clock=500
|
||||
cpu_id=0
|
||||
defer_registration=false
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
interrupts=system.cpu.interrupts
|
||||
itb=system.cpu.itb
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
phase=0
|
||||
profile=0
|
||||
progress_interval=0
|
||||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
workload=system.cpu.workload
|
||||
dcache_port=system.cpu.dcache.cpu_side
|
||||
icache_port=system.cpu.icache.cpu_side
|
||||
|
||||
[system.cpu.dcache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=262144
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.dcache_port
|
||||
mem_side=system.cpu.toL2Bus.slave[1]
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=AlphaTLB
|
||||
size=64
|
||||
|
||||
[system.cpu.icache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=131072
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.icache_port
|
||||
mem_side=system.cpu.toL2Bus.slave[0]
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=AlphaInterrupts
|
||||
|
||||
[system.cpu.itb]
|
||||
type=AlphaTLB
|
||||
size=48
|
||||
|
||||
[system.cpu.l2cache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=false
|
||||
latency=10000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=2097152
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.toL2Bus.master[0]
|
||||
mem_side=system.membus.slave[1]
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
master=system.cpu.l2cache.cpu_side
|
||||
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
|
||||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
|
||||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=vortex lendian.raw
|
||||
cwd=build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/simple-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
ppid=99
|
||||
simpoint=0
|
||||
system=system
|
||||
uid=100
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
master=system.physmem.port[0]
|
||||
slave=system.system_port system.cpu.l2cache.mem_side
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.membus.master[0]
|
||||
|
||||
@ -0,0 +1,6 @@
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: Prefetch instructions in Alpha do not do anything
|
||||
warn: Prefetch instructions in Alpha do not do anything
|
||||
warn: Prefetch instructions in Alpha do not do anything
|
||||
warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
|
||||
hack: be nice to actually delete the event here
|
||||
11
simulators/gem5/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/simout
Executable file
11
simulators/gem5/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/simout
Executable file
@ -0,0 +1,11 @@
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jun 4 2012 11:50:11
|
||||
gem5 started Jun 4 2012 14:21:00
|
||||
gem5 executing on zizzer
|
||||
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/simple-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
Exiting @ tick 134276988000 because target called exit()
|
||||
@ -0,0 +1,158 @@
|
||||
|
||||
SYSTEM TYPE...
|
||||
__ZTC__ := False
|
||||
__UNIX__ := True
|
||||
__RISC__ := True
|
||||
SPEC_CPU2000_LP64 := True
|
||||
__MAC__ := False
|
||||
__BCC__ := False
|
||||
__BORLANDC__ := False
|
||||
__GUI__ := False
|
||||
__WTC__ := False
|
||||
__HP__ := False
|
||||
|
||||
CODE OPTIONS...
|
||||
__MACROIZE_HM__ := True
|
||||
__MACROIZE_MEM__ := True
|
||||
ENV01 := True
|
||||
USE_HPP_STYPE_HDRS := False
|
||||
USE_H_STYPE_HDRS := False
|
||||
|
||||
CODE INCLUSION PARAMETERS...
|
||||
INCLUDE_ALL_CODE := False
|
||||
INCLUDE_DELETE_CODE := True
|
||||
__SWAP_GRP_POS__ := True
|
||||
__INCLUDE_MTRX__ := False
|
||||
__BAD_CODE__ := False
|
||||
API_INCLUDE := False
|
||||
BE_CAREFUL := False
|
||||
OLDWAY := False
|
||||
NOTUSED := False
|
||||
|
||||
SYSTEM PARAMETERS...
|
||||
EXT_ENUM := 999999999L
|
||||
CHUNK_CONSTANT := 55555555
|
||||
CORE_CONSTANT := 55555555
|
||||
CORE_LIMIT := 20971520
|
||||
CorePage_Size := 384000
|
||||
ALIGN_BYTES := True
|
||||
CORE_BLOCK_ALIGN := 8
|
||||
FAR_MEM := False
|
||||
|
||||
MEMORY MANAGEMENT PARAMETERS...
|
||||
SYSTEM_ALLOC := True
|
||||
SYSTEM_FREESTORE := True
|
||||
__NO_DISKCACHE__ := False
|
||||
__FREEZE_VCHUNKS__ := True
|
||||
__FREEZE_GRP_PACKETS__ := True
|
||||
__MINIMIZE_TREE_CACHE__:= True
|
||||
|
||||
SYSTEM STD PARAMETERS...
|
||||
__STDOUT__ := False
|
||||
NULL := 0
|
||||
LPTR := False
|
||||
False_Status := 1
|
||||
True_Status := 0
|
||||
LARGE := True
|
||||
TWOBYTE_BOOL := False
|
||||
__NOSTR__ := False
|
||||
|
||||
MEMORY VALIDATION PARAMETERS...
|
||||
CORE_CRC_CHECK := False
|
||||
VALIDATE_MEM_CHUNKS := False
|
||||
|
||||
SYSTEM DEBUG OPTIONS...
|
||||
DEBUG := False
|
||||
MCSTAT := False
|
||||
TRACKBACK := False
|
||||
FLUSH_FILES := False
|
||||
DEBUG_CORE0 := False
|
||||
DEBUG_RISC := False
|
||||
__TREE_BUG__ := False
|
||||
__TRACK_FILE_READS__ := False
|
||||
PAGE_SPACE := False
|
||||
LEAVE_NO_TRACE := True
|
||||
NULL_TRACE_STRS := False
|
||||
|
||||
TIME PARAMETERS...
|
||||
CLOCK_IS_LONG := False
|
||||
__DISPLAY_TIME__ := False
|
||||
__TREE_TIME__ := False
|
||||
__DISPLAY_ERRORS__ := False
|
||||
|
||||
API MACROS...
|
||||
__BMT01__ := True
|
||||
OPTIMIZE := True
|
||||
|
||||
END OF DEFINES.
|
||||
|
||||
|
||||
|
||||
... IMPLODE MEMORY ...
|
||||
|
||||
SWAP to DiskCache := False
|
||||
|
||||
FREEZE_GRP_PACKETS:= True
|
||||
|
||||
QueBug := 1000
|
||||
|
||||
sizeof(boolean) = 4
|
||||
sizeof(sizetype) = 4
|
||||
sizeof(chunkstruc) = 32
|
||||
|
||||
sizeof(shorttype ) = 2
|
||||
sizeof(idtype ) = 2
|
||||
sizeof(sizetype ) = 4
|
||||
sizeof(indextype ) = 4
|
||||
sizeof(numtype ) = 4
|
||||
sizeof(handletype) = 4
|
||||
sizeof(tokentype ) = 8
|
||||
|
||||
sizeof(short ) = 2
|
||||
sizeof(int ) = 4
|
||||
|
||||
sizeof(lt64 ) = 4
|
||||
sizeof(farlongtype) = 4
|
||||
sizeof(long ) = 8
|
||||
sizeof(longaddr ) = 8
|
||||
|
||||
sizeof(float ) = 4
|
||||
sizeof(double ) = 8
|
||||
|
||||
sizeof(addrtype ) = 8
|
||||
sizeof(char * ) = 8
|
||||
ALLOC CORE_1 :: 16
|
||||
BHOOLE NATH
|
||||
|
||||
OPEN File ./input/lendian.rnv
|
||||
*Status = 0
|
||||
DB HDR restored from FileVbn[ 0]
|
||||
DB BlkDirOffset : @ 2030c0
|
||||
DB BlkDirChunk : Chunk[ 10] AT Vbn[3146]
|
||||
DB BlkTknChunk : Chunk[ 11] AT Vbn[3147]
|
||||
DB BlkSizeChunk : Chunk[ 12] AT Vbn[3148]
|
||||
DB Handle Chunk's StackPtr = 20797
|
||||
|
||||
DB[ 1] LOADED; Handles= 20797
|
||||
KERNEL in CORE[ 1] Restored @ 4005c800
|
||||
|
||||
OPEN File ./input/lendian.wnv
|
||||
*Status = 0
|
||||
DB HDR restored from FileVbn[ 0]
|
||||
DB BlkDirOffset : @ 21c40
|
||||
DB BlkDirChunk : Chunk[ 31] AT Vbn[ 81]
|
||||
DB BlkTknChunk : Chunk[ 32] AT Vbn[ 82]
|
||||
DB BlkSizeChunk : Chunk[ 33] AT Vbn[ 83]
|
||||
DB Handle Chunk's StackPtr = 17
|
||||
|
||||
DB[ 2] LOADED; Handles= 17
|
||||
VORTEx_Status == -8 || fffffff8
|
||||
|
||||
BE HERE NOW !!!
|
||||
|
||||
|
||||
|
||||
... VORTEx ON LINE ...
|
||||
|
||||
|
||||
... END OF SESSION ...
|
||||
@ -0,0 +1,258 @@
|
||||
CREATE Db Header and Db Primal ...
|
||||
NEW DB [ 3] Created.
|
||||
|
||||
VORTEX INPUT PARAMETERS::
|
||||
MESSAGE FileName: smred.msg
|
||||
OUTPUT FileName: smred.out
|
||||
DISK CACHE FileName: NULL
|
||||
PART DB FileName: parts.db
|
||||
DRAW DB FileName: draw.db
|
||||
PERSON DB FileName: emp.db
|
||||
PERSONS Data FileName: ./input/persons.250
|
||||
PARTS Count : 100
|
||||
OUTER Loops : 1
|
||||
INNER Loops : 1
|
||||
LOOKUP Parts : 25
|
||||
DELETE Parts : 10
|
||||
STUFF Parts : 10
|
||||
DEPTH Traverse: 5
|
||||
% DECREASE Parts : 0
|
||||
% INCREASE LookUps : 0
|
||||
% INCREASE Deletes : 0
|
||||
% INCREASE Stuffs : 0
|
||||
FREEZE_PACKETS : 1
|
||||
ALLOC_CHUNKS : 10000
|
||||
EXTEND_CHUNKS : 5000
|
||||
DELETE Draw objects : True
|
||||
DELETE Part objects : False
|
||||
QUE_BUG : 1000
|
||||
VOID_BOUNDARY : 67108864
|
||||
VOID_RESERVE : 1048576
|
||||
|
||||
COMMIT_DBS : False
|
||||
|
||||
|
||||
|
||||
BMT TEST :: files...
|
||||
EdbName := PartLib
|
||||
EdbFileName := parts.db
|
||||
DrwName := DrawLib
|
||||
DrwFileName := draw.db
|
||||
EmpName := PersonLib
|
||||
EmpFileName := emp.db
|
||||
|
||||
Swap to DiskCache := False
|
||||
Freeze the cache := True
|
||||
|
||||
|
||||
BMT TEST :: parms...
|
||||
DeBug modulo := 1000
|
||||
Create Parts count:= 100
|
||||
Outer Loops := 1
|
||||
Inner Loops := 1
|
||||
Look Ups := 25
|
||||
Delete Parts := 10
|
||||
Stuff Parts := 10
|
||||
Traverse Limit := 5
|
||||
Delete Draws := True
|
||||
Delete Parts := False
|
||||
Delete ALL Parts := after every <mod 0>Outer Loop
|
||||
|
||||
INITIALIZE LIBRARY ::
|
||||
|
||||
INITIALIZE SCHEMA ::
|
||||
Primal_CreateDb Accessed !!!
|
||||
CREATE Db Header and Db Primal ...
|
||||
NEW DB [ 4] Created.
|
||||
PartLibCreate:: Db[ 4]; VpartsDir= 1
|
||||
|
||||
Part Count= 1
|
||||
|
||||
Initialize the Class maps
|
||||
LIST HEADS loaded ... DbListHead_Class = 207
|
||||
DbListNode_Class = 206
|
||||
|
||||
...NOTE... ShellLoadCode:: Class[ 228] will NOT be Activated.
|
||||
|
||||
|
||||
...NOTE... ShellLoadCode:: Class[ 229] will NOT be Activated.
|
||||
|
||||
Primal_CreateDb Accessed !!!
|
||||
CREATE Db Header and Db Primal ...
|
||||
NEW DB [ 5] Created.
|
||||
DrawLibCreate:: Db[ 5]; VpartsDir= 1
|
||||
|
||||
Initialize the Class maps of this schema.
|
||||
Primal_CreateDb Accessed !!!
|
||||
CREATE Db Header and Db Primal ...
|
||||
NEW DB [ 6] Created.
|
||||
|
||||
***NOTE*** Persons Library Extended!
|
||||
|
||||
Create <131072> Persons.
|
||||
ItNum 0. Person[ 6: 5]. Name= Riddell , Robert V. ;
|
||||
|
||||
LAST Person Read::
|
||||
ItNum 250. Person[ 6: 503]. Name= Gonzales , Warren X. ;
|
||||
|
||||
BUILD <Query0> for <Part2> class::
|
||||
|
||||
if (link[1].length >= 5) ::
|
||||
|
||||
Build Query2 for <Address> class::
|
||||
|
||||
if (State == CA || State == T*)
|
||||
|
||||
Build Query1 for <Person> class::
|
||||
|
||||
if (LastName >= H* && LastName <= P* && Query0(Residence)) ::
|
||||
|
||||
BUILD <Query3> for <DrawObj> class::
|
||||
|
||||
if (Id >= 3000
|
||||
&& (Id >= 3000 && Id <= 3001)
|
||||
&& Id >= 3002)
|
||||
|
||||
BUILD <Query4> for <NamedDrawObj> class::
|
||||
|
||||
if (Nam == Pre*
|
||||
|| (Nam == ??Mid??? || == Pre??Mid?? || == ??Post
|
||||
|| == Pre??Post || == ??Mid???Post || == Pre??Mid???Post)
|
||||
&& Id <= 7)
|
||||
SEED := 1008; Swap = False; RgnEntries = 135
|
||||
|
||||
OUTER LOOP [ 1] : NewParts = 100 LookUps = 25 StuffParts = 10.
|
||||
|
||||
Create 100 New Parts
|
||||
Create Part 1. Token[ 4: 2].
|
||||
|
||||
< 100> Parts Created. CurrentId= 100
|
||||
|
||||
Connect each instantiated Part TO 3 unique Parts
|
||||
Connect Part 1. Token[ 4: 2]
|
||||
Connect Part 25. Token[ 4: 26] FromList= 26.
|
||||
Connect Part 12. Token[ 4: 13] FromList= 13.
|
||||
Connect Part 59. Token[ 4: 60] FromList= 60.
|
||||
|
||||
SET <DrawObjs> entries::
|
||||
1. [ 5: 5] := <1 >; @[: 6]
|
||||
Iteration count = 100
|
||||
|
||||
SET <NamedDrawObjs> entries::
|
||||
1. [ 5: 39] := <14 >;
|
||||
Iteration count = 12
|
||||
|
||||
SET <LibRectangles> entries::
|
||||
1. [ 5: 23] := <8 >; @[: 24]
|
||||
Iteration count = 12
|
||||
|
||||
LIST <DbRectangles> entries::
|
||||
1. [ 5: 23]
|
||||
Iteration count = 12
|
||||
|
||||
SET <PersonNames > entries::
|
||||
Iteration count = 250
|
||||
|
||||
COMMIT All Image copies:: Release=<True>; Max Parts= 100
|
||||
< 100> Part images' Committed.
|
||||
< 0> are Named.
|
||||
< 50> Point images' Committed.
|
||||
< 81> Person images' Committed.
|
||||
|
||||
COMMIT Parts(* 100)
|
||||
|
||||
Commit TestObj_Class in <Primal> DB.
|
||||
ItNum 0. Token[ 0: 0]. TestObj Committed.
|
||||
< 0> TestObj images' Committed.
|
||||
|
||||
Commit CartesianPoint_Class in <Primal> DB.
|
||||
ItNum 0. Token[ 0: 0]. CartesianPoint Committed.
|
||||
< 0> CartesianPoint images' Committed.
|
||||
|
||||
BEGIN Inner Loop Sequence::.
|
||||
|
||||
INNER LOOP [ 1: 1] :
|
||||
|
||||
LOOK UP 25 Random Parts and Export each Part.
|
||||
|
||||
LookUp for 26 parts; Asserts = 8
|
||||
<Part2 > Asserts = 2; NULL Asserts = 3.
|
||||
<DrawObj > Asserts = 0; NULL Asserts = 5.
|
||||
<NamedObj > Asserts = 0; NULL Asserts = 0.
|
||||
<Person > Asserts = 0; NULL Asserts = 5.
|
||||
<TestObj > Asserts = 60; NULL Asserts = 0.
|
||||
|
||||
DELETE 10 Random Parts.
|
||||
|
||||
PartDelete :: Token[ 4: 91].
|
||||
PartDisconnect:: Token[ 4: 91] id:= 90 for each link.
|
||||
DisConnect link [ 0]:= 50; PartToken[ 51: 51].
|
||||
DisConnect link [ 1]:= 17; PartToken[ 18: 18].
|
||||
DisConnect link [ 2]:= 72; PartToken[ 73: 73].
|
||||
DeleteFromList:: Vchunk[ 4: 91]. (* 1)
|
||||
DisConnect FromList[ 0]:= 56; Token[ 57: 57].
|
||||
Vlists[ 89] := 100;
|
||||
|
||||
Delete for 11 parts;
|
||||
|
||||
Traverse Count= 0
|
||||
|
||||
TRAVERSE PartId[ 6] and all Connections to 5 Levels
|
||||
SEED In Traverse Part [ 4: 65] @ Level = 4.
|
||||
|
||||
Traverse Count= 357
|
||||
Traverse Asserts = 5. True Tests = 1
|
||||
< 5> DrawObj objects DELETED.
|
||||
< 2> are Named.
|
||||
< 2> Point objects DELETED.
|
||||
|
||||
CREATE 10 Additional Parts
|
||||
|
||||
Create 10 New Parts
|
||||
Create Part 101. Token[ 4: 102].
|
||||
|
||||
< 10> Parts Created. CurrentId= 110
|
||||
|
||||
Connect each instantiated Part TO 3 unique Parts
|
||||
|
||||
COMMIT All Image copies:: Release=<True>; Max Parts= 110
|
||||
< 81> Part images' Committed.
|
||||
< 0> are Named.
|
||||
< 38> Point images' Committed.
|
||||
< 31> Person images' Committed.
|
||||
|
||||
COMMIT Parts(* 100)
|
||||
|
||||
Commit TestObj_Class in <Primal> DB.
|
||||
ItNum 0. Token[ 3: 4]. TestObj Committed.
|
||||
< 15> TestObj images' Committed.
|
||||
|
||||
Commit CartesianPoint_Class in <Primal> DB.
|
||||
ItNum 0. Token[ 3: 3]. CartesianPoint Committed.
|
||||
< 16> CartesianPoint images' Committed.
|
||||
|
||||
DELETE All TestObj objects;
|
||||
|
||||
Delete TestObj_Class in <Primal> DB.
|
||||
ItNum 0. Token[ 3: 4]. TestObj Deleted.
|
||||
< 15> TestObj objects Deleted.
|
||||
|
||||
Commit CartesianPoint_Class in <Primal> DB.
|
||||
ItNum 0. Token[ 3: 3]. CartesianPoint Deleted.
|
||||
< 16> CartesianPoint objects Deleted.
|
||||
|
||||
DELETE TestObj and Point objects...
|
||||
|
||||
END INNER LOOP [ 1: 1].
|
||||
|
||||
DELETE All TestObj objects;
|
||||
|
||||
Delete TestObj_Class in <Primal> DB.
|
||||
< 0> TestObj objects Deleted.
|
||||
|
||||
Commit CartesianPoint_Class in <Primal> DB.
|
||||
< 0> CartesianPoint objects Deleted.
|
||||
|
||||
DELETE TestObj and Point objects...
|
||||
STATUS= -201
|
||||
V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!
|
||||
@ -0,0 +1,409 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.134277 # Number of seconds simulated
|
||||
sim_ticks 134276988000 # Number of ticks simulated
|
||||
final_tick 134276988000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1431789 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1431788 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2176303972 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 222880 # Number of bytes of host memory used
|
||||
host_seconds 61.70 # Real time elapsed on the host
|
||||
sim_insts 88340673 # Number of instructions simulated
|
||||
sim_ops 88340673 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 558272 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 10563648 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 11121920 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 558272 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 558272 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 7712384 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 7712384 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 8723 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 165057 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 173780 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 120506 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 120506 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 4157615 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 78670576 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 82828191 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 4157615 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 4157615 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 57436379 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 57436379 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 57436379 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 4157615 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 78670576 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 140264570 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
||||
system.cpu.dtb.read_hits 20276638 # DTB read hits
|
||||
system.cpu.dtb.read_misses 90148 # DTB read misses
|
||||
system.cpu.dtb.read_acv 0 # DTB read access violations
|
||||
system.cpu.dtb.read_accesses 20366786 # DTB read accesses
|
||||
system.cpu.dtb.write_hits 14613377 # DTB write hits
|
||||
system.cpu.dtb.write_misses 7252 # DTB write misses
|
||||
system.cpu.dtb.write_acv 0 # DTB write access violations
|
||||
system.cpu.dtb.write_accesses 14620629 # DTB write accesses
|
||||
system.cpu.dtb.data_hits 34890015 # DTB hits
|
||||
system.cpu.dtb.data_misses 97400 # DTB misses
|
||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
||||
system.cpu.dtb.data_accesses 34987415 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 88438074 # ITB hits
|
||||
system.cpu.itb.fetch_misses 3934 # ITB misses
|
||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
||||
system.cpu.itb.fetch_accesses 88442008 # ITB accesses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.itb.write_hits 0 # DTB write hits
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.itb.write_acv 0 # DTB write access violations
|
||||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.itb.data_hits 0 # DTB hits
|
||||
system.cpu.itb.data_misses 0 # DTB misses
|
||||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 4583 # Number of system calls
|
||||
system.cpu.numCycles 268553976 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 88340673 # Number of instructions committed
|
||||
system.cpu.committedOps 88340673 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 78039444 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 267757 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 3321606 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 8920848 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 78039444 # number of integer instructions
|
||||
system.cpu.num_fp_insts 267757 # number of float instructions
|
||||
system.cpu.num_int_register_reads 105931758 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 52319251 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 229023 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 227630 # number of times the floating registers were written
|
||||
system.cpu.num_mem_refs 34987415 # number of memory refs
|
||||
system.cpu.num_load_insts 20366786 # Number of load instructions
|
||||
system.cpu.num_store_insts 14620629 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 268553976 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.icache.replacements 74391 # number of replacements
|
||||
system.cpu.icache.tagsinuse 1871.404551 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 88361638 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 76436 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 1156.021220 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 1871.404551 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.913772 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.913772 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 88361638 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 88361638 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 88361638 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 88361638 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 88361638 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 88361638 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 76436 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 76436 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 76436 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 76436 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 76436 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 76436 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 1436470000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 1436470000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 1436470000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 1436470000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 1436470000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 1436470000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 88438074 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 88438074 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 88438074 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 88438074 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 88438074 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 88438074 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000864 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.000864 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000864 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.000864 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000864 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000864 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18793.107960 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 18793.107960 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 18793.107960 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 18793.107960 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 18793.107960 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 18793.107960 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 76436 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 76436 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 76436 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 76436 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 76436 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 76436 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1207162000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 1207162000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1207162000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 1207162000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1207162000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 1207162000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000864 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000864 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000864 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000864 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000864 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000864 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15793.107960 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15793.107960 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15793.107960 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 15793.107960 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15793.107960 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 15793.107960 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 200248 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 4078.858373 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 34685671 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 204344 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 169.741568 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 943232000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 4078.858373 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.995815 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.995815 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 20215872 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 20215872 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 14469799 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 14469799 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 34685671 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 34685671 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 34685671 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 34685671 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 60766 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 60766 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 143578 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 143578 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 204344 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 204344 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 204344 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 204344 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 2261000000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 2261000000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 7532210000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 7532210000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 9793210000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 9793210000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 9793210000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 9793210000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 20276638 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 20276638 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 34890015 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 34890015 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 34890015 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 34890015 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002997 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.002997 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.009825 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.009825 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.005857 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.005857 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.005857 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.005857 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 37208.307277 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 37208.307277 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52460.753040 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 52460.753040 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 47925.116470 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 47925.116470 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 47925.116470 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 47925.116470 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 161222 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 161222 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 60766 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 60766 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143578 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 143578 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 204344 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 204344 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 204344 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 204344 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2078702000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2078702000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7101476000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 7101476000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9180178000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 9180178000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9180178000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 9180178000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002997 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002997 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009825 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009825 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.005857 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.005857 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34208.307277 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34208.307277 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49460.753040 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49460.753040 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44925.116470 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 44925.116470 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44925.116470 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 44925.116470 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 147405 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 18614.813333 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 122958 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 172748 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 0.711777 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::writebacks 15808.263557 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 1305.254425 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 1501.295351 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.482430 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.039833 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.045816 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.568079 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 67713 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 27188 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 94901 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 161222 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 161222 # number of Writeback hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 12099 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 12099 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 67713 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 39287 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 107000 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 67713 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 39287 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 107000 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 8723 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.data 33578 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 42301 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 131479 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 131479 # number of ReadExReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 8723 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 165057 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 173780 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 8723 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 165057 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 173780 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 453596000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1746056000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 2199652000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6836908000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 6836908000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 453596000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 8582964000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 9036560000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 453596000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 8582964000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 9036560000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 76436 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 60766 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 137202 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 161222 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 161222 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 143578 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 143578 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 76436 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 204344 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 280780 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 76436 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 204344 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 280780 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.114122 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.552579 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.308312 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.915732 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.915732 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.114122 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.807741 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.618919 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.114122 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.807741 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.618919 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks::writebacks 120506 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 120506 # number of writebacks
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 8723 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 33578 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::total 42301 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 131479 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 131479 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 8723 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 165057 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 173780 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 8723 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 165057 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 173780 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 348920000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1343120000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1692040000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5259160000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5259160000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 348920000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6602280000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 6951200000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 348920000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6602280000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 6951200000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.114122 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.552579 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.308312 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.915732 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.915732 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.114122 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.807741 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.618919 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.114122 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.807741 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.618919 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
@ -0,0 +1,547 @@
|
||||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
full_system=false
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
||||
[system]
|
||||
type=System
|
||||
children=cpu membus physmem
|
||||
boot_osflags=a
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
mem_mode=atomic
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
readfile=
|
||||
symbolfile=
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.membus.slave[0]
|
||||
|
||||
[system.cpu]
|
||||
type=DerivO3CPU
|
||||
children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
|
||||
BTBEntries=4096
|
||||
BTBTagSize=16
|
||||
LFSTSize=1024
|
||||
LQEntries=32
|
||||
LSQCheckLoads=true
|
||||
LSQDepCheckShift=4
|
||||
RASSize=16
|
||||
SQEntries=32
|
||||
SSITSize=1024
|
||||
activity=0
|
||||
backComSize=5
|
||||
cachePorts=200
|
||||
checker=Null
|
||||
choiceCtrBits=2
|
||||
choicePredictorSize=8192
|
||||
clock=500
|
||||
commitToDecodeDelay=1
|
||||
commitToFetchDelay=1
|
||||
commitToIEWDelay=1
|
||||
commitToRenameDelay=1
|
||||
commitWidth=8
|
||||
cpu_id=0
|
||||
decodeToFetchDelay=1
|
||||
decodeToRenameDelay=1
|
||||
decodeWidth=8
|
||||
defer_registration=false
|
||||
dispatchWidth=8
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
fetchToDecodeDelay=1
|
||||
fetchTrapLatency=1
|
||||
fetchWidth=8
|
||||
forwardComSize=5
|
||||
fuPool=system.cpu.fuPool
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
globalCtrBits=2
|
||||
globalHistoryBits=13
|
||||
globalPredictorSize=8192
|
||||
iewToCommitDelay=1
|
||||
iewToDecodeDelay=1
|
||||
iewToFetchDelay=1
|
||||
iewToRenameDelay=1
|
||||
instShiftAmt=2
|
||||
interrupts=system.cpu.interrupts
|
||||
issueToExecuteDelay=1
|
||||
issueWidth=8
|
||||
itb=system.cpu.itb
|
||||
localCtrBits=2
|
||||
localHistoryBits=11
|
||||
localHistoryTableSize=2048
|
||||
localPredictorSize=2048
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
needsTSO=false
|
||||
numIQEntries=64
|
||||
numPhysFloatRegs=256
|
||||
numPhysIntRegs=256
|
||||
numROBEntries=192
|
||||
numRobs=1
|
||||
numThreads=1
|
||||
phase=0
|
||||
predType=tournament
|
||||
profile=0
|
||||
progress_interval=0
|
||||
renameToDecodeDelay=1
|
||||
renameToFetchDelay=1
|
||||
renameToIEWDelay=2
|
||||
renameToROBDelay=1
|
||||
renameWidth=8
|
||||
smtCommitPolicy=RoundRobin
|
||||
smtFetchPolicy=SingleThread
|
||||
smtIQPolicy=Partitioned
|
||||
smtIQThreshold=100
|
||||
smtLSQPolicy=Partitioned
|
||||
smtLSQThreshold=100
|
||||
smtNumFetchingThreads=1
|
||||
smtROBPolicy=Partitioned
|
||||
smtROBThreshold=100
|
||||
squashWidth=8
|
||||
store_set_clear_period=250000
|
||||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
trapLatency=13
|
||||
wbDepth=1
|
||||
wbWidth=8
|
||||
workload=system.cpu.workload
|
||||
dcache_port=system.cpu.dcache.cpu_side
|
||||
icache_port=system.cpu.icache.cpu_side
|
||||
|
||||
[system.cpu.dcache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=262144
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=20
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.dcache_port
|
||||
mem_side=system.cpu.toL2Bus.slave[1]
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
size=64
|
||||
walker=system.cpu.dtb.walker
|
||||
|
||||
[system.cpu.dtb.walker]
|
||||
type=ArmTableWalker
|
||||
max_backoff=100000
|
||||
min_backoff=0
|
||||
sys=system
|
||||
port=system.cpu.toL2Bus.slave[3]
|
||||
|
||||
[system.cpu.fuPool]
|
||||
type=FUPool
|
||||
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
|
||||
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
|
||||
|
||||
[system.cpu.fuPool.FUList0]
|
||||
type=FUDesc
|
||||
children=opList
|
||||
count=6
|
||||
opList=system.cpu.fuPool.FUList0.opList
|
||||
|
||||
[system.cpu.fuPool.FUList0.opList]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=IntAlu
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList1]
|
||||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=2
|
||||
opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=IntMult
|
||||
opLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList1]
|
||||
type=OpDesc
|
||||
issueLat=19
|
||||
opClass=IntDiv
|
||||
opLat=20
|
||||
|
||||
[system.cpu.fuPool.FUList2]
|
||||
type=FUDesc
|
||||
children=opList0 opList1 opList2
|
||||
count=4
|
||||
opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=FloatAdd
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList1]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=FloatCmp
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList2]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=FloatCvt
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList3]
|
||||
type=FUDesc
|
||||
children=opList0 opList1 opList2
|
||||
count=2
|
||||
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=FloatMult
|
||||
opLat=4
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList1]
|
||||
type=OpDesc
|
||||
issueLat=12
|
||||
opClass=FloatDiv
|
||||
opLat=12
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList2]
|
||||
type=OpDesc
|
||||
issueLat=24
|
||||
opClass=FloatSqrt
|
||||
opLat=24
|
||||
|
||||
[system.cpu.fuPool.FUList4]
|
||||
type=FUDesc
|
||||
children=opList
|
||||
count=0
|
||||
opList=system.cpu.fuPool.FUList4.opList
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5]
|
||||
type=FUDesc
|
||||
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
|
||||
count=4
|
||||
opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList00]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdAdd
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList01]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdAddAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList02]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdAlu
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList03]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdCmp
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList04]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdCvt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList05]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdMisc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList06]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdMult
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList07]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdMultAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList08]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdShift
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList09]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdShiftAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList10]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdSqrt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList11]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatAdd
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList12]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatAlu
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList13]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatCmp
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList14]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatCvt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList15]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatDiv
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList16]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatMisc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList17]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatMult
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList18]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatMultAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList19]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatSqrt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList6]
|
||||
type=FUDesc
|
||||
children=opList
|
||||
count=0
|
||||
opList=system.cpu.fuPool.FUList6.opList
|
||||
|
||||
[system.cpu.fuPool.FUList6.opList]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList7]
|
||||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=4
|
||||
opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList1]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList8]
|
||||
type=FUDesc
|
||||
children=opList
|
||||
count=1
|
||||
opList=system.cpu.fuPool.FUList8.opList
|
||||
|
||||
[system.cpu.fuPool.FUList8.opList]
|
||||
type=OpDesc
|
||||
issueLat=3
|
||||
opClass=IprAccess
|
||||
opLat=3
|
||||
|
||||
[system.cpu.icache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=131072
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=20
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.icache_port
|
||||
mem_side=system.cpu.toL2Bus.slave[0]
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=ArmInterrupts
|
||||
|
||||
[system.cpu.itb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
size=64
|
||||
walker=system.cpu.itb.walker
|
||||
|
||||
[system.cpu.itb.walker]
|
||||
type=ArmTableWalker
|
||||
max_backoff=100000
|
||||
min_backoff=0
|
||||
sys=system
|
||||
port=system.cpu.toL2Bus.slave[2]
|
||||
|
||||
[system.cpu.l2cache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=false
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=2097152
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.toL2Bus.master[0]
|
||||
mem_side=system.membus.slave[1]
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
master=system.cpu.l2cache.cpu_side
|
||||
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
|
||||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
|
||||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=vortex lendian.raw
|
||||
cwd=build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/cpu2000/binaries/arm/linux/vortex
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
ppid=99
|
||||
simpoint=0
|
||||
system=system
|
||||
uid=100
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
master=system.physmem.port[0]
|
||||
slave=system.system_port system.cpu.l2cache.mem_side
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.membus.master[0]
|
||||
|
||||
2
simulators/gem5/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simerr
Executable file
2
simulators/gem5/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simerr
Executable file
@ -0,0 +1,2 @@
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
hack: be nice to actually delete the event here
|
||||
11
simulators/gem5/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout
Executable file
11
simulators/gem5/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout
Executable file
@ -0,0 +1,11 @@
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jun 4 2012 12:14:06
|
||||
gem5 started Jun 4 2012 18:32:39
|
||||
gem5 executing on zizzer
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
Exiting @ tick 24560764000 because target called exit()
|
||||
@ -0,0 +1,258 @@
|
||||
CREATE Db Header and Db Primal ...
|
||||
NEW DB [ 3] Created.
|
||||
|
||||
VORTEX INPUT PARAMETERS::
|
||||
MESSAGE FileName: smred.msg
|
||||
OUTPUT FileName: smred.out
|
||||
DISK CACHE FileName: NULL
|
||||
PART DB FileName: parts.db
|
||||
DRAW DB FileName: draw.db
|
||||
PERSON DB FileName: emp.db
|
||||
PERSONS Data FileName: ./input/persons.250
|
||||
PARTS Count : 100
|
||||
OUTER Loops : 1
|
||||
INNER Loops : 1
|
||||
LOOKUP Parts : 25
|
||||
DELETE Parts : 10
|
||||
STUFF Parts : 10
|
||||
DEPTH Traverse: 5
|
||||
% DECREASE Parts : 0
|
||||
% INCREASE LookUps : 0
|
||||
% INCREASE Deletes : 0
|
||||
% INCREASE Stuffs : 0
|
||||
FREEZE_PACKETS : 1
|
||||
ALLOC_CHUNKS : 10000
|
||||
EXTEND_CHUNKS : 5000
|
||||
DELETE Draw objects : True
|
||||
DELETE Part objects : False
|
||||
QUE_BUG : 1000
|
||||
VOID_BOUNDARY : 67108864
|
||||
VOID_RESERVE : 1048576
|
||||
|
||||
COMMIT_DBS : False
|
||||
|
||||
|
||||
|
||||
BMT TEST :: files...
|
||||
EdbName := PartLib
|
||||
EdbFileName := parts.db
|
||||
DrwName := DrawLib
|
||||
DrwFileName := draw.db
|
||||
EmpName := PersonLib
|
||||
EmpFileName := emp.db
|
||||
|
||||
Swap to DiskCache := False
|
||||
Freeze the cache := True
|
||||
|
||||
|
||||
BMT TEST :: parms...
|
||||
DeBug modulo := 1000
|
||||
Create Parts count:= 100
|
||||
Outer Loops := 1
|
||||
Inner Loops := 1
|
||||
Look Ups := 25
|
||||
Delete Parts := 10
|
||||
Stuff Parts := 10
|
||||
Traverse Limit := 5
|
||||
Delete Draws := True
|
||||
Delete Parts := False
|
||||
Delete ALL Parts := after every <mod 0>Outer Loop
|
||||
|
||||
INITIALIZE LIBRARY ::
|
||||
|
||||
INITIALIZE SCHEMA ::
|
||||
Primal_CreateDb Accessed !!!
|
||||
CREATE Db Header and Db Primal ...
|
||||
NEW DB [ 4] Created.
|
||||
PartLibCreate:: Db[ 4]; VpartsDir= 1
|
||||
|
||||
Part Count= 1
|
||||
|
||||
Initialize the Class maps
|
||||
LIST HEADS loaded ... DbListHead_Class = 207
|
||||
DbListNode_Class = 206
|
||||
|
||||
...NOTE... ShellLoadCode:: Class[ 228] will NOT be Activated.
|
||||
|
||||
|
||||
...NOTE... ShellLoadCode:: Class[ 229] will NOT be Activated.
|
||||
|
||||
Primal_CreateDb Accessed !!!
|
||||
CREATE Db Header and Db Primal ...
|
||||
NEW DB [ 5] Created.
|
||||
DrawLibCreate:: Db[ 5]; VpartsDir= 1
|
||||
|
||||
Initialize the Class maps of this schema.
|
||||
Primal_CreateDb Accessed !!!
|
||||
CREATE Db Header and Db Primal ...
|
||||
NEW DB [ 6] Created.
|
||||
|
||||
***NOTE*** Persons Library Extended!
|
||||
|
||||
Create <131072> Persons.
|
||||
ItNum 0. Person[ 6: 5]. Name= Riddell , Robert V. ;
|
||||
|
||||
LAST Person Read::
|
||||
ItNum 250. Person[ 6: 503]. Name= Gonzales , Warren X. ;
|
||||
|
||||
BUILD <Query0> for <Part2> class::
|
||||
|
||||
if (link[1].length >= 5) ::
|
||||
|
||||
Build Query2 for <Address> class::
|
||||
|
||||
if (State == CA || State == T*)
|
||||
|
||||
Build Query1 for <Person> class::
|
||||
|
||||
if (LastName >= H* && LastName <= P* && Query0(Residence)) ::
|
||||
|
||||
BUILD <Query3> for <DrawObj> class::
|
||||
|
||||
if (Id >= 3000
|
||||
&& (Id >= 3000 && Id <= 3001)
|
||||
&& Id >= 3002)
|
||||
|
||||
BUILD <Query4> for <NamedDrawObj> class::
|
||||
|
||||
if (Nam == Pre*
|
||||
|| (Nam == ??Mid??? || == Pre??Mid?? || == ??Post
|
||||
|| == Pre??Post || == ??Mid???Post || == Pre??Mid???Post)
|
||||
&& Id <= 7)
|
||||
SEED := 1008; Swap = False; RgnEntries = 135
|
||||
|
||||
OUTER LOOP [ 1] : NewParts = 100 LookUps = 25 StuffParts = 10.
|
||||
|
||||
Create 100 New Parts
|
||||
Create Part 1. Token[ 4: 2].
|
||||
|
||||
< 100> Parts Created. CurrentId= 100
|
||||
|
||||
Connect each instantiated Part TO 3 unique Parts
|
||||
Connect Part 1. Token[ 4: 2]
|
||||
Connect Part 25. Token[ 4: 26] FromList= 26.
|
||||
Connect Part 12. Token[ 4: 13] FromList= 13.
|
||||
Connect Part 59. Token[ 4: 60] FromList= 60.
|
||||
|
||||
SET <DrawObjs> entries::
|
||||
1. [ 5: 5] := <1 >; @[: 6]
|
||||
Iteration count = 100
|
||||
|
||||
SET <NamedDrawObjs> entries::
|
||||
1. [ 5: 39] := <14 >;
|
||||
Iteration count = 12
|
||||
|
||||
SET <LibRectangles> entries::
|
||||
1. [ 5: 23] := <8 >; @[: 24]
|
||||
Iteration count = 12
|
||||
|
||||
LIST <DbRectangles> entries::
|
||||
1. [ 5: 23]
|
||||
Iteration count = 12
|
||||
|
||||
SET <PersonNames > entries::
|
||||
Iteration count = 250
|
||||
|
||||
COMMIT All Image copies:: Release=<True>; Max Parts= 100
|
||||
< 100> Part images' Committed.
|
||||
< 0> are Named.
|
||||
< 50> Point images' Committed.
|
||||
< 81> Person images' Committed.
|
||||
|
||||
COMMIT Parts(* 100)
|
||||
|
||||
Commit TestObj_Class in <Primal> DB.
|
||||
ItNum 0. Token[ 0: 0]. TestObj Committed.
|
||||
< 0> TestObj images' Committed.
|
||||
|
||||
Commit CartesianPoint_Class in <Primal> DB.
|
||||
ItNum 0. Token[ 0: 0]. CartesianPoint Committed.
|
||||
< 0> CartesianPoint images' Committed.
|
||||
|
||||
BEGIN Inner Loop Sequence::.
|
||||
|
||||
INNER LOOP [ 1: 1] :
|
||||
|
||||
LOOK UP 25 Random Parts and Export each Part.
|
||||
|
||||
LookUp for 26 parts; Asserts = 8
|
||||
<Part2 > Asserts = 2; NULL Asserts = 3.
|
||||
<DrawObj > Asserts = 0; NULL Asserts = 5.
|
||||
<NamedObj > Asserts = 0; NULL Asserts = 0.
|
||||
<Person > Asserts = 0; NULL Asserts = 5.
|
||||
<TestObj > Asserts = 60; NULL Asserts = 0.
|
||||
|
||||
DELETE 10 Random Parts.
|
||||
|
||||
PartDelete :: Token[ 4: 91].
|
||||
PartDisconnect:: Token[ 4: 91] id:= 90 for each link.
|
||||
DisConnect link [ 0]:= 50; PartToken[ 51: 51].
|
||||
DisConnect link [ 1]:= 17; PartToken[ 18: 18].
|
||||
DisConnect link [ 2]:= 72; PartToken[ 73: 73].
|
||||
DeleteFromList:: Vchunk[ 4: 91]. (* 1)
|
||||
DisConnect FromList[ 0]:= 56; Token[ 57: 57].
|
||||
Vlists[ 89] := 100;
|
||||
|
||||
Delete for 11 parts;
|
||||
|
||||
Traverse Count= 0
|
||||
|
||||
TRAVERSE PartId[ 6] and all Connections to 5 Levels
|
||||
SEED In Traverse Part [ 4: 65] @ Level = 4.
|
||||
|
||||
Traverse Count= 357
|
||||
Traverse Asserts = 5. True Tests = 1
|
||||
< 5> DrawObj objects DELETED.
|
||||
< 2> are Named.
|
||||
< 2> Point objects DELETED.
|
||||
|
||||
CREATE 10 Additional Parts
|
||||
|
||||
Create 10 New Parts
|
||||
Create Part 101. Token[ 4: 102].
|
||||
|
||||
< 10> Parts Created. CurrentId= 110
|
||||
|
||||
Connect each instantiated Part TO 3 unique Parts
|
||||
|
||||
COMMIT All Image copies:: Release=<True>; Max Parts= 110
|
||||
< 81> Part images' Committed.
|
||||
< 0> are Named.
|
||||
< 38> Point images' Committed.
|
||||
< 31> Person images' Committed.
|
||||
|
||||
COMMIT Parts(* 100)
|
||||
|
||||
Commit TestObj_Class in <Primal> DB.
|
||||
ItNum 0. Token[ 3: 4]. TestObj Committed.
|
||||
< 15> TestObj images' Committed.
|
||||
|
||||
Commit CartesianPoint_Class in <Primal> DB.
|
||||
ItNum 0. Token[ 3: 3]. CartesianPoint Committed.
|
||||
< 16> CartesianPoint images' Committed.
|
||||
|
||||
DELETE All TestObj objects;
|
||||
|
||||
Delete TestObj_Class in <Primal> DB.
|
||||
ItNum 0. Token[ 3: 4]. TestObj Deleted.
|
||||
< 15> TestObj objects Deleted.
|
||||
|
||||
Commit CartesianPoint_Class in <Primal> DB.
|
||||
ItNum 0. Token[ 3: 3]. CartesianPoint Deleted.
|
||||
< 16> CartesianPoint objects Deleted.
|
||||
|
||||
DELETE TestObj and Point objects...
|
||||
|
||||
END INNER LOOP [ 1: 1].
|
||||
|
||||
DELETE All TestObj objects;
|
||||
|
||||
Delete TestObj_Class in <Primal> DB.
|
||||
< 0> TestObj objects Deleted.
|
||||
|
||||
Commit CartesianPoint_Class in <Primal> DB.
|
||||
< 0> CartesianPoint objects Deleted.
|
||||
|
||||
DELETE TestObj and Point objects...
|
||||
STATUS= -201
|
||||
V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!
|
||||
@ -0,0 +1,729 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.024561 # Number of seconds simulated
|
||||
sim_ticks 24560764000 # Number of ticks simulated
|
||||
final_tick 24560764000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 104807 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 148726 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 36296181 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 240672 # Number of bytes of host memory used
|
||||
host_seconds 676.68 # Real time elapsed on the host
|
||||
sim_insts 70920072 # Number of instructions simulated
|
||||
sim_ops 100639320 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 367552 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 8319680 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 8687232 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 367552 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 367552 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 5661632 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 5661632 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 5743 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 129995 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 135738 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 88463 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 88463 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 14965007 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 338738648 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 353703655 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 14965007 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 14965007 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 230515305 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 230515305 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 230515305 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 14965007 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 338738648 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 584218960 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.dtb.read_hits 0 # DTB read hits
|
||||
system.cpu.dtb.read_misses 0 # DTB read misses
|
||||
system.cpu.dtb.write_hits 0 # DTB write hits
|
||||
system.cpu.dtb.write_misses 0 # DTB write misses
|
||||
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
|
||||
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||||
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
|
||||
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.dtb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.dtb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
|
||||
system.cpu.dtb.hits 0 # DTB hits
|
||||
system.cpu.dtb.misses 0 # DTB misses
|
||||
system.cpu.dtb.accesses 0 # DTB accesses
|
||||
system.cpu.itb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.itb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.write_hits 0 # DTB write hits
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
|
||||
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||||
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
|
||||
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.itb.inst_accesses 0 # ITB inst accesses
|
||||
system.cpu.itb.hits 0 # DTB hits
|
||||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 1946 # Number of system calls
|
||||
system.cpu.numCycles 49121529 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.BPredUnit.lookups 17484643 # Number of BP lookups
|
||||
system.cpu.BPredUnit.condPredicted 13346532 # Number of conditional branches predicted
|
||||
system.cpu.BPredUnit.condIncorrect 763895 # Number of conditional branches incorrect
|
||||
system.cpu.BPredUnit.BTBLookups 12042742 # Number of BTB lookups
|
||||
system.cpu.BPredUnit.BTBHits 8272877 # Number of BTB hits
|
||||
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu.BPredUnit.usedRAS 1873235 # Number of times the RAS was used to get a target.
|
||||
system.cpu.BPredUnit.RASInCorrect 186435 # Number of incorrect RAS predictions.
|
||||
system.cpu.fetch.icacheStallCycles 13233353 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.Insts 89314081 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.Branches 17484643 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.predictedBranches 10146112 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.Cycles 22235900 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.SquashCycles 3054378 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.BlockedCycles 9993886 # Number of cycles fetch has spent blocked
|
||||
system.cpu.fetch.MiscStallCycles 34 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
||||
system.cpu.fetch.PendingTrapStallCycles 494 # Number of stall cycles due to pending traps
|
||||
system.cpu.fetch.CacheLines 12432222 # Number of cache lines fetched
|
||||
system.cpu.fetch.IcacheSquashes 242141 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.rateDist::samples 47666513 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 2.625620 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 3.342151 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 25452916 53.40% 53.40% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 2276272 4.78% 58.17% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 2010669 4.22% 62.39% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 2082167 4.37% 66.76% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 1606372 3.37% 70.13% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 1473384 3.09% 73.22% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 1003270 2.10% 75.33% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 1293693 2.71% 78.04% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 10467770 21.96% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::total 47666513 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.branchRate 0.355947 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.rate 1.818227 # Number of inst fetches per cycle
|
||||
system.cpu.decode.IdleCycles 15402794 # Number of cycles decode is idle
|
||||
system.cpu.decode.BlockedCycles 8395926 # Number of cycles decode is blocked
|
||||
system.cpu.decode.RunCycles 20419082 # Number of cycles decode is running
|
||||
system.cpu.decode.UnblockCycles 1357324 # Number of cycles decode is unblocking
|
||||
system.cpu.decode.SquashCycles 2091387 # Number of cycles decode is squashing
|
||||
system.cpu.decode.BranchResolved 3552582 # Number of times decode resolved a branch
|
||||
system.cpu.decode.BranchMispred 114889 # Number of times decode detected a branch misprediction
|
||||
system.cpu.decode.DecodedInsts 122010152 # Number of instructions handled by decode
|
||||
system.cpu.decode.SquashedInsts 381349 # Number of squashed instructions handled by decode
|
||||
system.cpu.rename.SquashCycles 2091387 # Number of cycles rename is squashing
|
||||
system.cpu.rename.IdleCycles 17235553 # Number of cycles rename is idle
|
||||
system.cpu.rename.BlockCycles 2381046 # Number of cycles rename is blocking
|
||||
system.cpu.rename.serializeStallCycles 774700 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RunCycles 19895179 # Number of cycles rename is running
|
||||
system.cpu.rename.UnblockCycles 5288648 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RenamedInsts 118965286 # Number of instructions processed by rename
|
||||
system.cpu.rename.ROBFullEvents 65 # Number of times rename has blocked due to ROB full
|
||||
system.cpu.rename.IQFullEvents 10051 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.LSQFullEvents 4471697 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.FullRegisterEvents 173 # Number of times there has been no free registers
|
||||
system.cpu.rename.RenamedOperands 119289544 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RenameLookups 547314245 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.int_rename_lookups 547305502 # Number of integer rename lookups
|
||||
system.cpu.rename.fp_rename_lookups 8743 # Number of floating rename lookups
|
||||
system.cpu.rename.CommittedMaps 99152581 # Number of HB maps that are committed
|
||||
system.cpu.rename.UndoneMaps 20136963 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.serializingInsts 50089 # count of serializing insts renamed
|
||||
system.cpu.rename.tempSerializingInsts 50062 # count of temporary serializing insts renamed
|
||||
system.cpu.rename.skidInsts 12897670 # count of insts added to the skid buffer
|
||||
system.cpu.memDep0.insertedLoads 30342934 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 22764283 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.conflictingLoads 3373932 # Number of conflicting loads.
|
||||
system.cpu.memDep0.conflictingStores 4070444 # Number of conflicting stores.
|
||||
system.cpu.iq.iqInstsAdded 114201865 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqNonSpecInstsAdded 59946 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqInstsIssued 108885427 # Number of instructions issued
|
||||
system.cpu.iq.iqSquashedInstsIssued 355885 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedInstsExamined 13447173 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedOperandsExamined 32642565 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 23673 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.issued_per_cycle::samples 47666513 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::mean 2.284317 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::stdev 2.003120 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::0 11902735 24.97% 24.97% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::1 8314690 17.44% 42.41% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::2 7496951 15.73% 58.14% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::3 7072171 14.84% 72.98% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::4 5553695 11.65% 84.63% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::5 3902484 8.19% 92.82% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::6 1926147 4.04% 96.86% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::7 904880 1.90% 98.76% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::8 592760 1.24% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::total 47666513 # Number of insts issued each cycle
|
||||
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntAlu 112261 4.35% 4.35% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntMult 0 0.00% 4.35% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntDiv 0 0.00% 4.35% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatAdd 2 0.00% 4.35% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.35% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.35% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatMult 0 0.00% 4.35% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.35% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.35% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.35% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.35% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.35% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.35% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.35% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.35% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdMult 0 0.00% 4.35% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.35% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdShift 0 0.00% 4.35% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.35% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.35% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.35% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.35% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.35% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.35% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.35% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.35% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.35% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.35% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.35% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::MemRead 1423319 55.12% 59.47% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::MemWrite 1046695 40.53% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntAlu 57627292 52.92% 52.92% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntMult 88925 0.08% 53.01% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 53.01% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatAdd 277 0.00% 53.01% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 53.01% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 53.01% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 53.01% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 53.01% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 53.01% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 53.01% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 53.01% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 53.01% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 53.01% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 53.01% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 53.01% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 53.01% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 53.01% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 53.01% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 53.01% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 53.01% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 53.01% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 53.01% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 53.01% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 53.01% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 53.01% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 53.01% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 53.01% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 53.01% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 53.01% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::MemRead 29380371 26.98% 79.99% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::MemWrite 21788555 20.01% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::total 108885427 # Type of FU issued
|
||||
system.cpu.iq.rate 2.216654 # Inst issue rate
|
||||
system.cpu.iq.fu_busy_cnt 2582277 # FU busy when requested
|
||||
system.cpu.iq.fu_busy_rate 0.023716 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.int_inst_queue_reads 268374678 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_writes 127734912 # Number of integer instruction queue writes
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 106613834 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.fp_inst_queue_reads 851 # Number of floating instruction queue reads
|
||||
system.cpu.iq.fp_inst_queue_writes 1416 # Number of floating instruction queue writes
|
||||
system.cpu.iq.fp_inst_queue_wakeup_accesses 211 # Number of floating instruction queue wakeup accesses
|
||||
system.cpu.iq.int_alu_accesses 111467277 # Number of integer alu accesses
|
||||
system.cpu.iq.fp_alu_accesses 427 # Number of floating point alu accesses
|
||||
system.cpu.iew.lsq.thread0.forwLoads 2219770 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread0.squashedLoads 3033338 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread0.ignoredResponses 8348 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread0.memOrderViolation 28761 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread0.squashedStores 2206058 # Number of stores squashed
|
||||
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
||||
system.cpu.iew.lsq.thread0.rescheduledLoads 47 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread0.cacheBlocked 51 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||||
system.cpu.iew.iewSquashCycles 2091387 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewBlockCycles 991755 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewUnblockCycles 31052 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.iewDispatchedInsts 114342127 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewDispSquashedInsts 442332 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispLoadInsts 30342934 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispStoreInsts 22764283 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 43712 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewIQFullEvents 1891 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.iewLSQFullEvents 1967 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.memOrderViolationEvents 28761 # Number of memory order violations
|
||||
system.cpu.iew.predictedTakenIncorrect 532244 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.iew.predictedNotTakenIncorrect 266639 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.branchMispredicts 798883 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewExecutedInsts 107583415 # Number of executed instructions
|
||||
system.cpu.iew.iewExecLoadInsts 28980389 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 1302012 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
||||
system.cpu.iew.exec_nop 80316 # number of nop insts executed
|
||||
system.cpu.iew.exec_refs 50461236 # number of memory reference insts executed
|
||||
system.cpu.iew.exec_branches 14752818 # Number of branches executed
|
||||
system.cpu.iew.exec_stores 21480847 # Number of stores executed
|
||||
system.cpu.iew.exec_rate 2.190148 # Inst execution rate
|
||||
system.cpu.iew.wb_sent 106971474 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.wb_count 106614045 # cumulative count of insts written-back
|
||||
system.cpu.iew.wb_producers 53628736 # num instructions producing a value
|
||||
system.cpu.iew.wb_consumers 104822222 # num instructions consuming a value
|
||||
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
||||
system.cpu.iew.wb_rate 2.170414 # insts written-back per cycle
|
||||
system.cpu.iew.wb_fanout 0.511616 # average fanout of values written-back
|
||||
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||
system.cpu.commit.commitCommittedInsts 70925624 # The number of committed instructions
|
||||
system.cpu.commit.commitCommittedOps 100644872 # The number of committed instructions
|
||||
system.cpu.commit.commitSquashedInsts 13697900 # The number of squashed insts skipped by commit
|
||||
system.cpu.commit.commitNonSpecStalls 36273 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu.commit.branchMispredicts 715054 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.committed_per_cycle::samples 45575127 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::mean 2.208329 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::stdev 2.734720 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::0 16228357 35.61% 35.61% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::1 11797211 25.89% 61.49% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::2 3508330 7.70% 69.19% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::3 2972714 6.52% 75.71% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::4 1972056 4.33% 80.04% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::5 1932722 4.24% 84.28% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::6 698627 1.53% 85.81% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::7 551617 1.21% 87.02% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::8 5913493 12.98% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::total 45575127 # Number of insts commited each cycle
|
||||
system.cpu.commit.committedInsts 70925624 # Number of instructions committed
|
||||
system.cpu.commit.committedOps 100644872 # Number of ops (including micro ops) committed
|
||||
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
||||
system.cpu.commit.refs 47867821 # Number of memory references committed
|
||||
system.cpu.commit.loads 27309596 # Number of loads committed
|
||||
system.cpu.commit.membars 15920 # Number of memory barriers committed
|
||||
system.cpu.commit.branches 13671115 # Number of branches committed
|
||||
system.cpu.commit.fp_insts 56 # Number of committed floating point instructions.
|
||||
system.cpu.commit.int_insts 91482735 # Number of committed integer instructions.
|
||||
system.cpu.commit.function_calls 1679850 # Number of function calls committed.
|
||||
system.cpu.commit.bw_lim_events 5913493 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
||||
system.cpu.rob.rob_reads 153979107 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 230788170 # The number of ROB writes
|
||||
system.cpu.timesIdled 64143 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 1455016 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.committedInsts 70920072 # Number of Instructions Simulated
|
||||
system.cpu.committedOps 100639320 # Number of Ops (including micro ops) Simulated
|
||||
system.cpu.committedInsts_total 70920072 # Number of Instructions Simulated
|
||||
system.cpu.cpi 0.692632 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 0.692632 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 1.443768 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 1.443768 # IPC: Total IPC of All Threads
|
||||
system.cpu.int_regfile_reads 517371049 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 104514948 # number of integer regfile writes
|
||||
system.cpu.fp_regfile_reads 1051 # number of floating regfile reads
|
||||
system.cpu.fp_regfile_writes 886 # number of floating regfile writes
|
||||
system.cpu.misc_regfile_reads 147913903 # number of misc regfile reads
|
||||
system.cpu.misc_regfile_writes 36814 # number of misc regfile writes
|
||||
system.cpu.icache.replacements 31518 # number of replacements
|
||||
system.cpu.icache.tagsinuse 1822.469235 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 12397113 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 33561 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 369.390453 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 1822.469235 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.889878 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.889878 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 12397114 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 12397114 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 12397114 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 12397114 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 12397114 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 12397114 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 35108 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 35108 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 35108 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 35108 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 35108 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 35108 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 406151000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 406151000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 406151000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 406151000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 406151000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 406151000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 12432222 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 12432222 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 12432222 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 12432222 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 12432222 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 12432222 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.002824 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.002824 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.002824 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.002824 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.002824 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.002824 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 11568.616839 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 11568.616839 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 11568.616839 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 11568.616839 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 11568.616839 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 11568.616839 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1474 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::total 1474 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::cpu.inst 1474 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::total 1474 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::cpu.inst 1474 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::total 1474 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 33634 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 33634 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 33634 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 33634 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 33634 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 33634 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 268782500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 268782500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 268782500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 268782500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 268782500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 268782500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.002705 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.002705 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.002705 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.002705 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.002705 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.002705 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 7991.392638 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 7991.392638 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 7991.392638 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 7991.392638 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 7991.392638 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 7991.392638 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 158907 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 4070.754102 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 44741379 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 163003 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 274.481936 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 274553000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 4070.754102 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.993836 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.993836 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 26393302 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 26393302 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 18309799 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 18309799 # number of WriteReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::cpu.data 19644 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::total 19644 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::cpu.data 18406 # number of StoreCondReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::total 18406 # number of StoreCondReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 44703101 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 44703101 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 44703101 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 44703101 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 110193 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 110193 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 1540102 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 1540102 # number of WriteReq misses
|
||||
system.cpu.dcache.LoadLockedReq_misses::cpu.data 35 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.LoadLockedReq_misses::total 35 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 1650295 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 1650295 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 1650295 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 1650295 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 2434975500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 2434975500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 52525381000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 52525381000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 425000 # number of LoadLockedReq miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_miss_latency::total 425000 # number of LoadLockedReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 54960356500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 54960356500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 54960356500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 54960356500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 26503495 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 26503495 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 19679 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::total 19679 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::cpu.data 18406 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::total 18406 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 46353396 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 46353396 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 46353396 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 46353396 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004158 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.004158 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.077587 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.077587 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001779 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001779 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.035602 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.035602 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.035602 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.035602 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22097.370069 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 22097.370069 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34105.131348 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 34105.131348 # average WriteReq miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12142.857143 # average LoadLockedReq miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12142.857143 # average LoadLockedReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 33303.352734 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 33303.352734 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 33303.352734 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 33303.352734 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 203500 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 11 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets 18500 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 123795 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 123795 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 54073 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 54073 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1433145 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 1433145 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 35 # number of LoadLockedReq MSHR hits
|
||||
system.cpu.dcache.LoadLockedReq_mshr_hits::total 35 # number of LoadLockedReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 1487218 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 1487218 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 1487218 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 1487218 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 56120 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 56120 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 106957 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 106957 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 163077 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 163077 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 163077 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 163077 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1049489500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 1049489500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3666942000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3666942000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4716431500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 4716431500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4716431500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 4716431500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002117 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002117 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005388 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005388 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003518 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.003518 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003518 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.003518 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18700.810763 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18700.810763 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34284.263770 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34284.263770 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28921.500273 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 28921.500273 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28921.500273 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 28921.500273 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 115487 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 18346.494934 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 78611 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 134352 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 0.585112 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::writebacks 15851.533035 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 880.199051 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 1614.762848 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.483750 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.026862 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.049279 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.559891 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 27786 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 28611 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 56397 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 123795 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 123795 # number of Writeback hits
|
||||
system.cpu.l2cache.UpgradeReq_hits::cpu.data 11 # number of UpgradeReq hits
|
||||
system.cpu.l2cache.UpgradeReq_hits::total 11 # number of UpgradeReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 4332 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 4332 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 27786 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 32943 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 60729 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 27786 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 32943 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 60729 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 5769 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.data 27473 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 33242 # number of ReadReq misses
|
||||
system.cpu.l2cache.UpgradeReq_misses::cpu.data 63 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_misses::total 63 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 102587 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 102587 # number of ReadExReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 5769 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 130060 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 135829 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 5769 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 130060 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 135829 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 197487500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 940646500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 1138134000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 34500 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency::total 34500 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3520234000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 3520234000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 197487500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 4460880500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 4658368000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 197487500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 4460880500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 4658368000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 33555 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 56084 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 89639 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 123795 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 123795 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 74 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_accesses::total 74 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 106919 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 106919 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 33555 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 163003 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 196558 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 33555 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 163003 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 196558 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.171927 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.489855 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.370843 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.851351 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.851351 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.959483 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.959483 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.171927 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.797899 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.691038 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.171927 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.797899 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.691038 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34232.535968 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34238.943690 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 34237.831659 # average ReadReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 547.619048 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 547.619048 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34314.620761 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34314.620761 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34232.535968 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34298.635245 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 34295.827842 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34232.535968 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34298.635245 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 34295.827842 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks::writebacks 88463 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 88463 # number of writebacks
|
||||
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 26 # number of ReadReq MSHR hits
|
||||
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 65 # number of ReadReq MSHR hits
|
||||
system.cpu.l2cache.ReadReq_mshr_hits::total 91 # number of ReadReq MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_hits::cpu.inst 26 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_hits::cpu.data 65 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_hits::total 91 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_hits::cpu.inst 26 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_hits::cpu.data 65 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_hits::total 91 # number of overall MSHR hits
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 5743 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 27408 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::total 33151 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 63 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses::total 63 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102587 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 102587 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 5743 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 129995 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 135738 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 5743 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 129995 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 135738 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 178439000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 852007500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1030446500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1955000 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1955000 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3195019500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3195019500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 178439000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4047027000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 4225466000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 178439000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4047027000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 4225466000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.171152 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.488696 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.369828 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.851351 # mshr miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.851351 # mshr miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.959483 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.959483 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.171152 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.797501 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.690575 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.171152 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.797501 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.690575 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31070.694759 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31086.088004 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31083.421315 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31031.746032 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31031.746032 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31144.487118 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31144.487118 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31070.694759 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31132.174314 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31129.573148 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31070.694759 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31132.174314 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31129.573148 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
@ -0,0 +1,135 @@
|
||||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
full_system=false
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
||||
[system]
|
||||
type=System
|
||||
children=cpu membus physmem
|
||||
boot_osflags=a
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
mem_mode=atomic
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
readfile=
|
||||
symbolfile=
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.membus.slave[0]
|
||||
|
||||
[system.cpu]
|
||||
type=AtomicSimpleCPU
|
||||
children=dtb interrupts itb tracer workload
|
||||
checker=Null
|
||||
clock=500
|
||||
cpu_id=0
|
||||
defer_registration=false
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
fastmem=false
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
interrupts=system.cpu.interrupts
|
||||
itb=system.cpu.itb
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
phase=0
|
||||
profile=0
|
||||
progress_interval=0
|
||||
simulate_data_stalls=false
|
||||
simulate_inst_stalls=false
|
||||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
width=1
|
||||
workload=system.cpu.workload
|
||||
dcache_port=system.membus.slave[2]
|
||||
icache_port=system.membus.slave[1]
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
size=64
|
||||
walker=system.cpu.dtb.walker
|
||||
|
||||
[system.cpu.dtb.walker]
|
||||
type=ArmTableWalker
|
||||
max_backoff=100000
|
||||
min_backoff=0
|
||||
sys=system
|
||||
port=system.membus.slave[4]
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=ArmInterrupts
|
||||
|
||||
[system.cpu.itb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
size=64
|
||||
walker=system.cpu.itb.walker
|
||||
|
||||
[system.cpu.itb.walker]
|
||||
type=ArmTableWalker
|
||||
max_backoff=100000
|
||||
min_backoff=0
|
||||
sys=system
|
||||
port=system.membus.slave[3]
|
||||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
|
||||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=vortex lendian.raw
|
||||
cwd=build/ARM/tests/opt/long/se/50.vortex/arm/linux/simple-atomic
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/cpu2000/binaries/arm/linux/vortex
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
ppid=99
|
||||
simpoint=0
|
||||
system=system
|
||||
uid=100
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
master=system.physmem.port[0]
|
||||
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.membus.master[0]
|
||||
|
||||
@ -0,0 +1,2 @@
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
hack: be nice to actually delete the event here
|
||||
11
simulators/gem5/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/simout
Executable file
11
simulators/gem5/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/simout
Executable file
@ -0,0 +1,11 @@
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jun 4 2012 12:14:06
|
||||
gem5 started Jun 4 2012 18:34:04
|
||||
gem5 executing on zizzer
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/50.vortex/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/50.vortex/arm/linux/simple-atomic
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
Exiting @ tick 53932162000 because target called exit()
|
||||
@ -0,0 +1,258 @@
|
||||
CREATE Db Header and Db Primal ...
|
||||
NEW DB [ 3] Created.
|
||||
|
||||
VORTEX INPUT PARAMETERS::
|
||||
MESSAGE FileName: smred.msg
|
||||
OUTPUT FileName: smred.out
|
||||
DISK CACHE FileName: NULL
|
||||
PART DB FileName: parts.db
|
||||
DRAW DB FileName: draw.db
|
||||
PERSON DB FileName: emp.db
|
||||
PERSONS Data FileName: ./input/persons.250
|
||||
PARTS Count : 100
|
||||
OUTER Loops : 1
|
||||
INNER Loops : 1
|
||||
LOOKUP Parts : 25
|
||||
DELETE Parts : 10
|
||||
STUFF Parts : 10
|
||||
DEPTH Traverse: 5
|
||||
% DECREASE Parts : 0
|
||||
% INCREASE LookUps : 0
|
||||
% INCREASE Deletes : 0
|
||||
% INCREASE Stuffs : 0
|
||||
FREEZE_PACKETS : 1
|
||||
ALLOC_CHUNKS : 10000
|
||||
EXTEND_CHUNKS : 5000
|
||||
DELETE Draw objects : True
|
||||
DELETE Part objects : False
|
||||
QUE_BUG : 1000
|
||||
VOID_BOUNDARY : 67108864
|
||||
VOID_RESERVE : 1048576
|
||||
|
||||
COMMIT_DBS : False
|
||||
|
||||
|
||||
|
||||
BMT TEST :: files...
|
||||
EdbName := PartLib
|
||||
EdbFileName := parts.db
|
||||
DrwName := DrawLib
|
||||
DrwFileName := draw.db
|
||||
EmpName := PersonLib
|
||||
EmpFileName := emp.db
|
||||
|
||||
Swap to DiskCache := False
|
||||
Freeze the cache := True
|
||||
|
||||
|
||||
BMT TEST :: parms...
|
||||
DeBug modulo := 1000
|
||||
Create Parts count:= 100
|
||||
Outer Loops := 1
|
||||
Inner Loops := 1
|
||||
Look Ups := 25
|
||||
Delete Parts := 10
|
||||
Stuff Parts := 10
|
||||
Traverse Limit := 5
|
||||
Delete Draws := True
|
||||
Delete Parts := False
|
||||
Delete ALL Parts := after every <mod 0>Outer Loop
|
||||
|
||||
INITIALIZE LIBRARY ::
|
||||
|
||||
INITIALIZE SCHEMA ::
|
||||
Primal_CreateDb Accessed !!!
|
||||
CREATE Db Header and Db Primal ...
|
||||
NEW DB [ 4] Created.
|
||||
PartLibCreate:: Db[ 4]; VpartsDir= 1
|
||||
|
||||
Part Count= 1
|
||||
|
||||
Initialize the Class maps
|
||||
LIST HEADS loaded ... DbListHead_Class = 207
|
||||
DbListNode_Class = 206
|
||||
|
||||
...NOTE... ShellLoadCode:: Class[ 228] will NOT be Activated.
|
||||
|
||||
|
||||
...NOTE... ShellLoadCode:: Class[ 229] will NOT be Activated.
|
||||
|
||||
Primal_CreateDb Accessed !!!
|
||||
CREATE Db Header and Db Primal ...
|
||||
NEW DB [ 5] Created.
|
||||
DrawLibCreate:: Db[ 5]; VpartsDir= 1
|
||||
|
||||
Initialize the Class maps of this schema.
|
||||
Primal_CreateDb Accessed !!!
|
||||
CREATE Db Header and Db Primal ...
|
||||
NEW DB [ 6] Created.
|
||||
|
||||
***NOTE*** Persons Library Extended!
|
||||
|
||||
Create <131072> Persons.
|
||||
ItNum 0. Person[ 6: 5]. Name= Riddell , Robert V. ;
|
||||
|
||||
LAST Person Read::
|
||||
ItNum 250. Person[ 6: 503]. Name= Gonzales , Warren X. ;
|
||||
|
||||
BUILD <Query0> for <Part2> class::
|
||||
|
||||
if (link[1].length >= 5) ::
|
||||
|
||||
Build Query2 for <Address> class::
|
||||
|
||||
if (State == CA || State == T*)
|
||||
|
||||
Build Query1 for <Person> class::
|
||||
|
||||
if (LastName >= H* && LastName <= P* && Query0(Residence)) ::
|
||||
|
||||
BUILD <Query3> for <DrawObj> class::
|
||||
|
||||
if (Id >= 3000
|
||||
&& (Id >= 3000 && Id <= 3001)
|
||||
&& Id >= 3002)
|
||||
|
||||
BUILD <Query4> for <NamedDrawObj> class::
|
||||
|
||||
if (Nam == Pre*
|
||||
|| (Nam == ??Mid??? || == Pre??Mid?? || == ??Post
|
||||
|| == Pre??Post || == ??Mid???Post || == Pre??Mid???Post)
|
||||
&& Id <= 7)
|
||||
SEED := 1008; Swap = False; RgnEntries = 135
|
||||
|
||||
OUTER LOOP [ 1] : NewParts = 100 LookUps = 25 StuffParts = 10.
|
||||
|
||||
Create 100 New Parts
|
||||
Create Part 1. Token[ 4: 2].
|
||||
|
||||
< 100> Parts Created. CurrentId= 100
|
||||
|
||||
Connect each instantiated Part TO 3 unique Parts
|
||||
Connect Part 1. Token[ 4: 2]
|
||||
Connect Part 25. Token[ 4: 26] FromList= 26.
|
||||
Connect Part 12. Token[ 4: 13] FromList= 13.
|
||||
Connect Part 59. Token[ 4: 60] FromList= 60.
|
||||
|
||||
SET <DrawObjs> entries::
|
||||
1. [ 5: 5] := <1 >; @[: 6]
|
||||
Iteration count = 100
|
||||
|
||||
SET <NamedDrawObjs> entries::
|
||||
1. [ 5: 39] := <14 >;
|
||||
Iteration count = 12
|
||||
|
||||
SET <LibRectangles> entries::
|
||||
1. [ 5: 23] := <8 >; @[: 24]
|
||||
Iteration count = 12
|
||||
|
||||
LIST <DbRectangles> entries::
|
||||
1. [ 5: 23]
|
||||
Iteration count = 12
|
||||
|
||||
SET <PersonNames > entries::
|
||||
Iteration count = 250
|
||||
|
||||
COMMIT All Image copies:: Release=<True>; Max Parts= 100
|
||||
< 100> Part images' Committed.
|
||||
< 0> are Named.
|
||||
< 50> Point images' Committed.
|
||||
< 81> Person images' Committed.
|
||||
|
||||
COMMIT Parts(* 100)
|
||||
|
||||
Commit TestObj_Class in <Primal> DB.
|
||||
ItNum 0. Token[ 0: 0]. TestObj Committed.
|
||||
< 0> TestObj images' Committed.
|
||||
|
||||
Commit CartesianPoint_Class in <Primal> DB.
|
||||
ItNum 0. Token[ 0: 0]. CartesianPoint Committed.
|
||||
< 0> CartesianPoint images' Committed.
|
||||
|
||||
BEGIN Inner Loop Sequence::.
|
||||
|
||||
INNER LOOP [ 1: 1] :
|
||||
|
||||
LOOK UP 25 Random Parts and Export each Part.
|
||||
|
||||
LookUp for 26 parts; Asserts = 8
|
||||
<Part2 > Asserts = 2; NULL Asserts = 3.
|
||||
<DrawObj > Asserts = 0; NULL Asserts = 5.
|
||||
<NamedObj > Asserts = 0; NULL Asserts = 0.
|
||||
<Person > Asserts = 0; NULL Asserts = 5.
|
||||
<TestObj > Asserts = 60; NULL Asserts = 0.
|
||||
|
||||
DELETE 10 Random Parts.
|
||||
|
||||
PartDelete :: Token[ 4: 91].
|
||||
PartDisconnect:: Token[ 4: 91] id:= 90 for each link.
|
||||
DisConnect link [ 0]:= 50; PartToken[ 51: 51].
|
||||
DisConnect link [ 1]:= 17; PartToken[ 18: 18].
|
||||
DisConnect link [ 2]:= 72; PartToken[ 73: 73].
|
||||
DeleteFromList:: Vchunk[ 4: 91]. (* 1)
|
||||
DisConnect FromList[ 0]:= 56; Token[ 57: 57].
|
||||
Vlists[ 89] := 100;
|
||||
|
||||
Delete for 11 parts;
|
||||
|
||||
Traverse Count= 0
|
||||
|
||||
TRAVERSE PartId[ 6] and all Connections to 5 Levels
|
||||
SEED In Traverse Part [ 4: 65] @ Level = 4.
|
||||
|
||||
Traverse Count= 357
|
||||
Traverse Asserts = 5. True Tests = 1
|
||||
< 5> DrawObj objects DELETED.
|
||||
< 2> are Named.
|
||||
< 2> Point objects DELETED.
|
||||
|
||||
CREATE 10 Additional Parts
|
||||
|
||||
Create 10 New Parts
|
||||
Create Part 101. Token[ 4: 102].
|
||||
|
||||
< 10> Parts Created. CurrentId= 110
|
||||
|
||||
Connect each instantiated Part TO 3 unique Parts
|
||||
|
||||
COMMIT All Image copies:: Release=<True>; Max Parts= 110
|
||||
< 81> Part images' Committed.
|
||||
< 0> are Named.
|
||||
< 38> Point images' Committed.
|
||||
< 31> Person images' Committed.
|
||||
|
||||
COMMIT Parts(* 100)
|
||||
|
||||
Commit TestObj_Class in <Primal> DB.
|
||||
ItNum 0. Token[ 3: 4]. TestObj Committed.
|
||||
< 15> TestObj images' Committed.
|
||||
|
||||
Commit CartesianPoint_Class in <Primal> DB.
|
||||
ItNum 0. Token[ 3: 3]. CartesianPoint Committed.
|
||||
< 16> CartesianPoint images' Committed.
|
||||
|
||||
DELETE All TestObj objects;
|
||||
|
||||
Delete TestObj_Class in <Primal> DB.
|
||||
ItNum 0. Token[ 3: 4]. TestObj Deleted.
|
||||
< 15> TestObj objects Deleted.
|
||||
|
||||
Commit CartesianPoint_Class in <Primal> DB.
|
||||
ItNum 0. Token[ 3: 3]. CartesianPoint Deleted.
|
||||
< 16> CartesianPoint objects Deleted.
|
||||
|
||||
DELETE TestObj and Point objects...
|
||||
|
||||
END INNER LOOP [ 1: 1].
|
||||
|
||||
DELETE All TestObj objects;
|
||||
|
||||
Delete TestObj_Class in <Primal> DB.
|
||||
< 0> TestObj objects Deleted.
|
||||
|
||||
Commit CartesianPoint_Class in <Primal> DB.
|
||||
< 0> CartesianPoint objects Deleted.
|
||||
|
||||
DELETE TestObj and Point objects...
|
||||
STATUS= -201
|
||||
V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!
|
||||
@ -0,0 +1,102 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.053932 # Number of seconds simulated
|
||||
sim_ticks 53932162000 # Number of ticks simulated
|
||||
final_tick 53932162000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1760373 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2498132 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1338828629 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 228700 # Number of bytes of host memory used
|
||||
host_seconds 40.28 # Real time elapsed on the host
|
||||
sim_insts 70913189 # Number of instructions simulated
|
||||
sim_ops 100632437 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 312580308 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 106573346 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 419153654 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 312580308 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 312580308 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::cpu.data 78660211 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 78660211 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 78145077 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 27156253 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 105301330 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::cpu.data 19865820 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 19865820 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 5795805256 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 1976062929 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 7771868185 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 5795805256 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 5795805256 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::cpu.data 1458502832 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 1458502832 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 5795805256 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 3434565761 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 9230371017 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.dtb.read_hits 0 # DTB read hits
|
||||
system.cpu.dtb.read_misses 0 # DTB read misses
|
||||
system.cpu.dtb.write_hits 0 # DTB write hits
|
||||
system.cpu.dtb.write_misses 0 # DTB write misses
|
||||
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
|
||||
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||||
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
|
||||
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.dtb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.dtb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
|
||||
system.cpu.dtb.hits 0 # DTB hits
|
||||
system.cpu.dtb.misses 0 # DTB misses
|
||||
system.cpu.dtb.accesses 0 # DTB accesses
|
||||
system.cpu.itb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.itb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.write_hits 0 # DTB write hits
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
|
||||
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||||
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
|
||||
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.itb.inst_accesses 0 # ITB inst accesses
|
||||
system.cpu.itb.hits 0 # DTB hits
|
||||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 1946 # Number of system calls
|
||||
system.cpu.numCycles 107864325 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 70913189 # Number of instructions committed
|
||||
system.cpu.committedOps 100632437 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 91472788 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 56 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 3287514 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 10711743 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 91472788 # number of integer instructions
|
||||
system.cpu.num_fp_insts 56 # number of float instructions
|
||||
system.cpu.num_int_register_reads 452177233 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 96252298 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 36 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 20 # number of times the floating registers were written
|
||||
system.cpu.num_mem_refs 47862848 # number of memory refs
|
||||
system.cpu.num_load_insts 27307109 # Number of load instructions
|
||||
system.cpu.num_store_insts 20555739 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 107864325 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
@ -0,0 +1,216 @@
|
||||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
full_system=false
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
||||
[system]
|
||||
type=System
|
||||
children=cpu membus physmem
|
||||
boot_osflags=a
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
mem_mode=atomic
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
readfile=
|
||||
symbolfile=
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.membus.slave[0]
|
||||
|
||||
[system.cpu]
|
||||
type=TimingSimpleCPU
|
||||
children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
|
||||
checker=Null
|
||||
clock=500
|
||||
cpu_id=0
|
||||
defer_registration=false
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
interrupts=system.cpu.interrupts
|
||||
itb=system.cpu.itb
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
phase=0
|
||||
profile=0
|
||||
progress_interval=0
|
||||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
workload=system.cpu.workload
|
||||
dcache_port=system.cpu.dcache.cpu_side
|
||||
icache_port=system.cpu.icache.cpu_side
|
||||
|
||||
[system.cpu.dcache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=262144
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.dcache_port
|
||||
mem_side=system.cpu.toL2Bus.slave[1]
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
size=64
|
||||
walker=system.cpu.dtb.walker
|
||||
|
||||
[system.cpu.dtb.walker]
|
||||
type=ArmTableWalker
|
||||
max_backoff=100000
|
||||
min_backoff=0
|
||||
sys=system
|
||||
port=system.cpu.toL2Bus.slave[3]
|
||||
|
||||
[system.cpu.icache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=131072
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.icache_port
|
||||
mem_side=system.cpu.toL2Bus.slave[0]
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=ArmInterrupts
|
||||
|
||||
[system.cpu.itb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
size=64
|
||||
walker=system.cpu.itb.walker
|
||||
|
||||
[system.cpu.itb.walker]
|
||||
type=ArmTableWalker
|
||||
max_backoff=100000
|
||||
min_backoff=0
|
||||
sys=system
|
||||
port=system.cpu.toL2Bus.slave[2]
|
||||
|
||||
[system.cpu.l2cache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=false
|
||||
latency=10000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=2097152
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.toL2Bus.master[0]
|
||||
mem_side=system.membus.slave[1]
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
master=system.cpu.l2cache.cpu_side
|
||||
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
|
||||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
|
||||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=vortex lendian.raw
|
||||
cwd=build/ARM/tests/opt/long/se/50.vortex/arm/linux/simple-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/cpu2000/binaries/arm/linux/vortex
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
ppid=99
|
||||
simpoint=0
|
||||
system=system
|
||||
uid=100
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
master=system.physmem.port[0]
|
||||
slave=system.system_port system.cpu.l2cache.mem_side
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.membus.master[0]
|
||||
|
||||
@ -0,0 +1,2 @@
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
hack: be nice to actually delete the event here
|
||||
11
simulators/gem5/tests/long/se/50.vortex/ref/arm/linux/simple-timing/simout
Executable file
11
simulators/gem5/tests/long/se/50.vortex/ref/arm/linux/simple-timing/simout
Executable file
@ -0,0 +1,11 @@
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jun 4 2012 12:14:06
|
||||
gem5 started Jun 4 2012 18:34:55
|
||||
gem5 executing on zizzer
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/50.vortex/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/50.vortex/arm/linux/simple-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
Exiting @ tick 133117442000 because target called exit()
|
||||
@ -0,0 +1,258 @@
|
||||
CREATE Db Header and Db Primal ...
|
||||
NEW DB [ 3] Created.
|
||||
|
||||
VORTEX INPUT PARAMETERS::
|
||||
MESSAGE FileName: smred.msg
|
||||
OUTPUT FileName: smred.out
|
||||
DISK CACHE FileName: NULL
|
||||
PART DB FileName: parts.db
|
||||
DRAW DB FileName: draw.db
|
||||
PERSON DB FileName: emp.db
|
||||
PERSONS Data FileName: ./input/persons.250
|
||||
PARTS Count : 100
|
||||
OUTER Loops : 1
|
||||
INNER Loops : 1
|
||||
LOOKUP Parts : 25
|
||||
DELETE Parts : 10
|
||||
STUFF Parts : 10
|
||||
DEPTH Traverse: 5
|
||||
% DECREASE Parts : 0
|
||||
% INCREASE LookUps : 0
|
||||
% INCREASE Deletes : 0
|
||||
% INCREASE Stuffs : 0
|
||||
FREEZE_PACKETS : 1
|
||||
ALLOC_CHUNKS : 10000
|
||||
EXTEND_CHUNKS : 5000
|
||||
DELETE Draw objects : True
|
||||
DELETE Part objects : False
|
||||
QUE_BUG : 1000
|
||||
VOID_BOUNDARY : 67108864
|
||||
VOID_RESERVE : 1048576
|
||||
|
||||
COMMIT_DBS : False
|
||||
|
||||
|
||||
|
||||
BMT TEST :: files...
|
||||
EdbName := PartLib
|
||||
EdbFileName := parts.db
|
||||
DrwName := DrawLib
|
||||
DrwFileName := draw.db
|
||||
EmpName := PersonLib
|
||||
EmpFileName := emp.db
|
||||
|
||||
Swap to DiskCache := False
|
||||
Freeze the cache := True
|
||||
|
||||
|
||||
BMT TEST :: parms...
|
||||
DeBug modulo := 1000
|
||||
Create Parts count:= 100
|
||||
Outer Loops := 1
|
||||
Inner Loops := 1
|
||||
Look Ups := 25
|
||||
Delete Parts := 10
|
||||
Stuff Parts := 10
|
||||
Traverse Limit := 5
|
||||
Delete Draws := True
|
||||
Delete Parts := False
|
||||
Delete ALL Parts := after every <mod 0>Outer Loop
|
||||
|
||||
INITIALIZE LIBRARY ::
|
||||
|
||||
INITIALIZE SCHEMA ::
|
||||
Primal_CreateDb Accessed !!!
|
||||
CREATE Db Header and Db Primal ...
|
||||
NEW DB [ 4] Created.
|
||||
PartLibCreate:: Db[ 4]; VpartsDir= 1
|
||||
|
||||
Part Count= 1
|
||||
|
||||
Initialize the Class maps
|
||||
LIST HEADS loaded ... DbListHead_Class = 207
|
||||
DbListNode_Class = 206
|
||||
|
||||
...NOTE... ShellLoadCode:: Class[ 228] will NOT be Activated.
|
||||
|
||||
|
||||
...NOTE... ShellLoadCode:: Class[ 229] will NOT be Activated.
|
||||
|
||||
Primal_CreateDb Accessed !!!
|
||||
CREATE Db Header and Db Primal ...
|
||||
NEW DB [ 5] Created.
|
||||
DrawLibCreate:: Db[ 5]; VpartsDir= 1
|
||||
|
||||
Initialize the Class maps of this schema.
|
||||
Primal_CreateDb Accessed !!!
|
||||
CREATE Db Header and Db Primal ...
|
||||
NEW DB [ 6] Created.
|
||||
|
||||
***NOTE*** Persons Library Extended!
|
||||
|
||||
Create <131072> Persons.
|
||||
ItNum 0. Person[ 6: 5]. Name= Riddell , Robert V. ;
|
||||
|
||||
LAST Person Read::
|
||||
ItNum 250. Person[ 6: 503]. Name= Gonzales , Warren X. ;
|
||||
|
||||
BUILD <Query0> for <Part2> class::
|
||||
|
||||
if (link[1].length >= 5) ::
|
||||
|
||||
Build Query2 for <Address> class::
|
||||
|
||||
if (State == CA || State == T*)
|
||||
|
||||
Build Query1 for <Person> class::
|
||||
|
||||
if (LastName >= H* && LastName <= P* && Query0(Residence)) ::
|
||||
|
||||
BUILD <Query3> for <DrawObj> class::
|
||||
|
||||
if (Id >= 3000
|
||||
&& (Id >= 3000 && Id <= 3001)
|
||||
&& Id >= 3002)
|
||||
|
||||
BUILD <Query4> for <NamedDrawObj> class::
|
||||
|
||||
if (Nam == Pre*
|
||||
|| (Nam == ??Mid??? || == Pre??Mid?? || == ??Post
|
||||
|| == Pre??Post || == ??Mid???Post || == Pre??Mid???Post)
|
||||
&& Id <= 7)
|
||||
SEED := 1008; Swap = False; RgnEntries = 135
|
||||
|
||||
OUTER LOOP [ 1] : NewParts = 100 LookUps = 25 StuffParts = 10.
|
||||
|
||||
Create 100 New Parts
|
||||
Create Part 1. Token[ 4: 2].
|
||||
|
||||
< 100> Parts Created. CurrentId= 100
|
||||
|
||||
Connect each instantiated Part TO 3 unique Parts
|
||||
Connect Part 1. Token[ 4: 2]
|
||||
Connect Part 25. Token[ 4: 26] FromList= 26.
|
||||
Connect Part 12. Token[ 4: 13] FromList= 13.
|
||||
Connect Part 59. Token[ 4: 60] FromList= 60.
|
||||
|
||||
SET <DrawObjs> entries::
|
||||
1. [ 5: 5] := <1 >; @[: 6]
|
||||
Iteration count = 100
|
||||
|
||||
SET <NamedDrawObjs> entries::
|
||||
1. [ 5: 39] := <14 >;
|
||||
Iteration count = 12
|
||||
|
||||
SET <LibRectangles> entries::
|
||||
1. [ 5: 23] := <8 >; @[: 24]
|
||||
Iteration count = 12
|
||||
|
||||
LIST <DbRectangles> entries::
|
||||
1. [ 5: 23]
|
||||
Iteration count = 12
|
||||
|
||||
SET <PersonNames > entries::
|
||||
Iteration count = 250
|
||||
|
||||
COMMIT All Image copies:: Release=<True>; Max Parts= 100
|
||||
< 100> Part images' Committed.
|
||||
< 0> are Named.
|
||||
< 50> Point images' Committed.
|
||||
< 81> Person images' Committed.
|
||||
|
||||
COMMIT Parts(* 100)
|
||||
|
||||
Commit TestObj_Class in <Primal> DB.
|
||||
ItNum 0. Token[ 0: 0]. TestObj Committed.
|
||||
< 0> TestObj images' Committed.
|
||||
|
||||
Commit CartesianPoint_Class in <Primal> DB.
|
||||
ItNum 0. Token[ 0: 0]. CartesianPoint Committed.
|
||||
< 0> CartesianPoint images' Committed.
|
||||
|
||||
BEGIN Inner Loop Sequence::.
|
||||
|
||||
INNER LOOP [ 1: 1] :
|
||||
|
||||
LOOK UP 25 Random Parts and Export each Part.
|
||||
|
||||
LookUp for 26 parts; Asserts = 8
|
||||
<Part2 > Asserts = 2; NULL Asserts = 3.
|
||||
<DrawObj > Asserts = 0; NULL Asserts = 5.
|
||||
<NamedObj > Asserts = 0; NULL Asserts = 0.
|
||||
<Person > Asserts = 0; NULL Asserts = 5.
|
||||
<TestObj > Asserts = 60; NULL Asserts = 0.
|
||||
|
||||
DELETE 10 Random Parts.
|
||||
|
||||
PartDelete :: Token[ 4: 91].
|
||||
PartDisconnect:: Token[ 4: 91] id:= 90 for each link.
|
||||
DisConnect link [ 0]:= 50; PartToken[ 51: 51].
|
||||
DisConnect link [ 1]:= 17; PartToken[ 18: 18].
|
||||
DisConnect link [ 2]:= 72; PartToken[ 73: 73].
|
||||
DeleteFromList:: Vchunk[ 4: 91]. (* 1)
|
||||
DisConnect FromList[ 0]:= 56; Token[ 57: 57].
|
||||
Vlists[ 89] := 100;
|
||||
|
||||
Delete for 11 parts;
|
||||
|
||||
Traverse Count= 0
|
||||
|
||||
TRAVERSE PartId[ 6] and all Connections to 5 Levels
|
||||
SEED In Traverse Part [ 4: 65] @ Level = 4.
|
||||
|
||||
Traverse Count= 357
|
||||
Traverse Asserts = 5. True Tests = 1
|
||||
< 5> DrawObj objects DELETED.
|
||||
< 2> are Named.
|
||||
< 2> Point objects DELETED.
|
||||
|
||||
CREATE 10 Additional Parts
|
||||
|
||||
Create 10 New Parts
|
||||
Create Part 101. Token[ 4: 102].
|
||||
|
||||
< 10> Parts Created. CurrentId= 110
|
||||
|
||||
Connect each instantiated Part TO 3 unique Parts
|
||||
|
||||
COMMIT All Image copies:: Release=<True>; Max Parts= 110
|
||||
< 81> Part images' Committed.
|
||||
< 0> are Named.
|
||||
< 38> Point images' Committed.
|
||||
< 31> Person images' Committed.
|
||||
|
||||
COMMIT Parts(* 100)
|
||||
|
||||
Commit TestObj_Class in <Primal> DB.
|
||||
ItNum 0. Token[ 3: 4]. TestObj Committed.
|
||||
< 15> TestObj images' Committed.
|
||||
|
||||
Commit CartesianPoint_Class in <Primal> DB.
|
||||
ItNum 0. Token[ 3: 3]. CartesianPoint Committed.
|
||||
< 16> CartesianPoint images' Committed.
|
||||
|
||||
DELETE All TestObj objects;
|
||||
|
||||
Delete TestObj_Class in <Primal> DB.
|
||||
ItNum 0. Token[ 3: 4]. TestObj Deleted.
|
||||
< 15> TestObj objects Deleted.
|
||||
|
||||
Commit CartesianPoint_Class in <Primal> DB.
|
||||
ItNum 0. Token[ 3: 3]. CartesianPoint Deleted.
|
||||
< 16> CartesianPoint objects Deleted.
|
||||
|
||||
DELETE TestObj and Point objects...
|
||||
|
||||
END INNER LOOP [ 1: 1].
|
||||
|
||||
DELETE All TestObj objects;
|
||||
|
||||
Delete TestObj_Class in <Primal> DB.
|
||||
< 0> TestObj objects Deleted.
|
||||
|
||||
Commit CartesianPoint_Class in <Primal> DB.
|
||||
< 0> CartesianPoint objects Deleted.
|
||||
|
||||
DELETE TestObj and Point objects...
|
||||
STATUS= -201
|
||||
V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!
|
||||
@ -0,0 +1,427 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.133117 # Number of seconds simulated
|
||||
sim_ticks 133117442000 # Number of ticks simulated
|
||||
final_tick 133117442000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 828989 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1175527 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1568098699 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 237868 # Number of bytes of host memory used
|
||||
host_seconds 84.89 # Real time elapsed on the host
|
||||
sim_insts 70373636 # Number of instructions simulated
|
||||
sim_ops 99791663 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 294208 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 8276480 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 8570688 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 294208 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 294208 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 5660736 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 5660736 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 4597 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 129320 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 133917 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 88449 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 88449 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 2210139 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 62174272 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 64384410 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 2210139 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 2210139 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 42524375 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 42524375 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 42524375 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 2210139 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 62174272 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 106908785 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.dtb.read_hits 0 # DTB read hits
|
||||
system.cpu.dtb.read_misses 0 # DTB read misses
|
||||
system.cpu.dtb.write_hits 0 # DTB write hits
|
||||
system.cpu.dtb.write_misses 0 # DTB write misses
|
||||
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
|
||||
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||||
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
|
||||
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.dtb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.dtb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
|
||||
system.cpu.dtb.hits 0 # DTB hits
|
||||
system.cpu.dtb.misses 0 # DTB misses
|
||||
system.cpu.dtb.accesses 0 # DTB accesses
|
||||
system.cpu.itb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.itb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.write_hits 0 # DTB write hits
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
|
||||
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||||
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
|
||||
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.itb.inst_accesses 0 # ITB inst accesses
|
||||
system.cpu.itb.hits 0 # DTB hits
|
||||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 1946 # Number of system calls
|
||||
system.cpu.numCycles 266234884 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 70373636 # Number of instructions committed
|
||||
system.cpu.committedOps 99791663 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 91472788 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 56 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 3287514 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 10711743 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 91472788 # number of integer instructions
|
||||
system.cpu.num_fp_insts 56 # number of float instructions
|
||||
system.cpu.num_int_register_reads 533542913 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 96252298 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 36 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 20 # number of times the floating registers were written
|
||||
system.cpu.num_mem_refs 47862848 # number of memory refs
|
||||
system.cpu.num_load_insts 27307109 # Number of load instructions
|
||||
system.cpu.num_store_insts 20555739 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 266234884 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.icache.replacements 16890 # number of replacements
|
||||
system.cpu.icache.tagsinuse 1736.182852 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 78126170 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 18908 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 4131.910831 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 1736.182852 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.847746 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.847746 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 78126170 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 78126170 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 78126170 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 78126170 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 78126170 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 78126170 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 18908 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 18908 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 18908 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 18908 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 18908 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 18908 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 457786000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 457786000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 457786000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 457786000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 457786000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 457786000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 78145078 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 78145078 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 78145078 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 78145078 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 78145078 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 78145078 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000242 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.000242 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000242 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.000242 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000242 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000242 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 24211.233340 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 24211.233340 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 24211.233340 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 24211.233340 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 24211.233340 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 24211.233340 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 18908 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 18908 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 18908 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 18908 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 18908 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 18908 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 401062000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 401062000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 401062000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 401062000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 401062000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 401062000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000242 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000242 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000242 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21211.233340 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21211.233340 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21211.233340 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 21211.233340 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21211.233340 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 21211.233340 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 155902 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 4076.934010 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 46862075 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 159998 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 292.891630 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 1079641000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 4076.934010 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.995345 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.995345 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 27087368 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 27087368 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 19742869 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 19742869 # number of WriteReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::cpu.data 15919 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 46830237 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 46830237 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 46830237 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 46830237 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 52966 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 52966 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 107032 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 107032 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 159998 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 159998 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 159998 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 159998 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 1862630000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 1862630000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 5808782000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 5808782000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 7671412000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 7671412000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 7671412000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 7671412000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 27140334 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 27140334 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15919 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::total 15919 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 46990235 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 46990235 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 46990235 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 46990235 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001952 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.001952 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005392 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.005392 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.003405 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.003405 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.003405 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.003405 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 35166.521920 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 35166.521920 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54271.451529 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 54271.451529 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 47946.924337 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 47946.924337 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 47946.924337 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 47946.924337 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 122808 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 122808 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 52966 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 52966 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107032 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 107032 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 159998 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 159998 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 159998 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 159998 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1703732000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 1703732000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5487686000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 5487686000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7191418000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 7191418000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7191418000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 7191418000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001952 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001952 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005392 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005392 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003405 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.003405 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003405 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.003405 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 32166.521920 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 32166.521920 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51271.451529 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51271.451529 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44946.924337 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 44946.924337 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44946.924337 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 44946.924337 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 113660 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 18191.621028 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 61800 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 132489 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 0.466454 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::writebacks 16025.699940 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 701.722418 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 1464.198671 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.489066 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.021415 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.044684 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.555164 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 14311 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 26273 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 40584 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 122808 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 122808 # number of Writeback hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 4405 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 4405 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 14311 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 30678 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 44989 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 14311 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 30678 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 44989 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 4597 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.data 26693 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 31290 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 102627 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 102627 # number of ReadExReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 4597 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 129320 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 133917 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 4597 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 129320 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 133917 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 239044000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1388036000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 1627080000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5336604000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 5336604000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 239044000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 6724640000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 6963684000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 239044000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 6724640000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 6963684000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 18908 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 52966 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 71874 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 122808 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 122808 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 107032 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 107032 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 18908 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 159998 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 178906 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 18908 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 159998 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 178906 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.243125 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.503965 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.435345 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.958844 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.958844 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.243125 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.808260 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.748533 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.243125 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.808260 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.748533 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks::writebacks 88449 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 88449 # number of writebacks
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 4597 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 26693 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::total 31290 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102627 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 102627 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 4597 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 129320 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 133917 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 4597 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 129320 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 133917 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 183880000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1067720000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1251600000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4105080000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4105080000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 183880000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5172800000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 5356680000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 183880000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5172800000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 5356680000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.243125 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.503965 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.435345 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.958844 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.958844 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.243125 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.808260 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.748533 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.243125 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.808260 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.748533 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
@ -0,0 +1,117 @@
|
||||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
full_system=false
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
||||
[system]
|
||||
type=System
|
||||
children=cpu membus physmem
|
||||
boot_osflags=a
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
mem_mode=atomic
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
readfile=
|
||||
symbolfile=
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.membus.slave[0]
|
||||
|
||||
[system.cpu]
|
||||
type=AtomicSimpleCPU
|
||||
children=dtb interrupts itb tracer workload
|
||||
checker=Null
|
||||
clock=500
|
||||
cpu_id=0
|
||||
defer_registration=false
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
fastmem=false
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
interrupts=system.cpu.interrupts
|
||||
itb=system.cpu.itb
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
phase=0
|
||||
profile=0
|
||||
progress_interval=0
|
||||
simulate_data_stalls=false
|
||||
simulate_inst_stalls=false
|
||||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
width=1
|
||||
workload=system.cpu.workload
|
||||
dcache_port=system.membus.slave[2]
|
||||
icache_port=system.membus.slave[1]
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=SparcTLB
|
||||
size=64
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=SparcInterrupts
|
||||
|
||||
[system.cpu.itb]
|
||||
type=SparcTLB
|
||||
size=64
|
||||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
|
||||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=vortex bendian.raw
|
||||
cwd=build/SPARC/tests/opt/long/se/50.vortex/sparc/linux/simple-atomic
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/cpu2000/binaries/sparc/linux/vortex
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
ppid=99
|
||||
simpoint=0
|
||||
system=system
|
||||
uid=100
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
master=system.physmem.port[0]
|
||||
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.membus.master[0]
|
||||
|
||||
564
simulators/gem5/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/simerr
Executable file
564
simulators/gem5/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/simerr
Executable file
@ -0,0 +1,564 @@
|
||||
warn: CoherentBus system.membus has no snooping ports attached!
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: ignoring syscall time(4026528248, 4026527848, ...)
|
||||
warn: ignoring syscall time(1375098, 4026527400, ...)
|
||||
warn: ignoring syscall time(1, 4026527312, ...)
|
||||
warn: ignoring syscall time(413, 4026527048, ...)
|
||||
warn: ignoring syscall time(414, 4026527048, ...)
|
||||
warn: ignoring syscall time(4026527688, 4026527288, ...)
|
||||
warn: ignoring syscall time(1375098, 4026526840, ...)
|
||||
warn: ignoring syscall time(409, 4026527048, ...)
|
||||
warn: ignoring syscall time(409, 4026527048, ...)
|
||||
warn: ignoring syscall time(409, 4026526960, ...)
|
||||
warn: ignoring syscall time(409, 4026527040, ...)
|
||||
warn: ignoring syscall time(409, 4026527000, ...)
|
||||
warn: ignoring syscall time(409, 4026526984, ...)
|
||||
warn: ignoring syscall time(409, 4026526984, ...)
|
||||
warn: ignoring syscall time(409, 4026526872, ...)
|
||||
warn: ignoring syscall time(19045, 4026526312, ...)
|
||||
warn: ignoring syscall time(409, 4026526832, ...)
|
||||
warn: ignoring syscall time(409, 4026526872, ...)
|
||||
warn: ignoring syscall time(409, 4026526872, ...)
|
||||
warn: ignoring syscall time(409, 4026526848, ...)
|
||||
warn: ignoring syscall time(409, 4026526840, ...)
|
||||
warn: ignoring syscall time(409, 4026526872, ...)
|
||||
warn: ignoring syscall time(409, 4026526856, ...)
|
||||
warn: ignoring syscall time(409, 4026526848, ...)
|
||||
warn: ignoring syscall time(409, 4026526936, ...)
|
||||
warn: ignoring syscall time(4026527408, 4026527008, ...)
|
||||
warn: ignoring syscall time(1375098, 4026526560, ...)
|
||||
warn: ignoring syscall time(18732, 4026527184, ...)
|
||||
warn: ignoring syscall time(409, 4026526632, ...)
|
||||
warn: ignoring syscall time(0, 4026526736, ...)
|
||||
warn: ignoring syscall time(0, 4026527320, ...)
|
||||
warn: ignoring syscall time(225, 4026527744, ...)
|
||||
warn: ignoring syscall time(409, 4026527048, ...)
|
||||
warn: ignoring syscall time(409, 4026526856, ...)
|
||||
warn: ignoring syscall time(409, 4026526872, ...)
|
||||
warn: ignoring syscall time(4026527496, 4026527096, ...)
|
||||
warn: ignoring syscall time(1375098, 4026526648, ...)
|
||||
warn: ignoring syscall time(0, 4026526824, ...)
|
||||
warn: ignoring syscall time(0, 4026527320, ...)
|
||||
warn: ignoring syscall time(1879089152, 4026527184, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall time(1595768, 4026527472, ...)
|
||||
warn: ignoring syscall time(17300, 4026526912, ...)
|
||||
warn: ignoring syscall time(0, 4026527472, ...)
|
||||
warn: ignoring syscall time(0, 4026527472, ...)
|
||||
warn: ignoring syscall time(19045, 4026526912, ...)
|
||||
warn: ignoring syscall time(0, 4026527472, ...)
|
||||
warn: ignoring syscall time(0, 4026527472, ...)
|
||||
warn: ignoring syscall time(0, 4026527472, ...)
|
||||
warn: ignoring syscall time(0, 4026527472, ...)
|
||||
warn: ignoring syscall time(0, 4026527472, ...)
|
||||
warn: ignoring syscall time(0, 4026527472, ...)
|
||||
warn: ignoring syscall time(0, 4026527472, ...)
|
||||
warn: ignoring syscall time(0, 4026527472, ...)
|
||||
warn: ignoring syscall time(0, 4026527472, ...)
|
||||
warn: ignoring syscall time(19045, 4026526912, ...)
|
||||
warn: ignoring syscall time(17300, 4026526912, ...)
|
||||
warn: ignoring syscall time(20500, 4026525968, ...)
|
||||
warn: ignoring syscall time(4026526436, 4026525968, ...)
|
||||
warn: ignoring syscall time(7004192, 4026526056, ...)
|
||||
warn: ignoring syscall time(4, 4026527512, ...)
|
||||
warn: ignoring syscall time(0, 4026525760, ...)
|
||||
hack: be nice to actually delete the event here
|
||||
11
simulators/gem5/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/simout
Executable file
11
simulators/gem5/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/simout
Executable file
@ -0,0 +1,11 @@
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jun 4 2012 12:01:47
|
||||
gem5 started Jun 4 2012 14:58:33
|
||||
gem5 executing on zizzer
|
||||
command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/50.vortex/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/opt/long/se/50.vortex/sparc/linux/simple-atomic
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
Exiting @ tick 68148678500 because target called exit()
|
||||
@ -0,0 +1,158 @@
|
||||
|
||||
SYSTEM TYPE...
|
||||
__ZTC__ := False
|
||||
__UNIX__ := True
|
||||
__RISC__ := True
|
||||
SPEC_CPU2000_LP64 := False
|
||||
__MAC__ := False
|
||||
__BCC__ := False
|
||||
__BORLANDC__ := False
|
||||
__GUI__ := False
|
||||
__WTC__ := False
|
||||
__HP__ := False
|
||||
|
||||
CODE OPTIONS...
|
||||
__MACROIZE_HM__ := True
|
||||
__MACROIZE_MEM__ := True
|
||||
ENV01 := True
|
||||
USE_HPP_STYPE_HDRS := False
|
||||
USE_H_STYPE_HDRS := False
|
||||
|
||||
CODE INCLUSION PARAMETERS...
|
||||
INCLUDE_ALL_CODE := False
|
||||
INCLUDE_DELETE_CODE := True
|
||||
__SWAP_GRP_POS__ := True
|
||||
__INCLUDE_MTRX__ := False
|
||||
__BAD_CODE__ := False
|
||||
API_INCLUDE := False
|
||||
BE_CAREFUL := False
|
||||
OLDWAY := False
|
||||
NOTUSED := False
|
||||
|
||||
SYSTEM PARAMETERS...
|
||||
EXT_ENUM := 999999999L
|
||||
CHUNK_CONSTANT := 55555555
|
||||
CORE_CONSTANT := 55555555
|
||||
CORE_LIMIT := 20971520
|
||||
CorePage_Size := 384000
|
||||
ALIGN_BYTES := True
|
||||
CORE_BLOCK_ALIGN := 8
|
||||
FAR_MEM := False
|
||||
|
||||
MEMORY MANAGEMENT PARAMETERS...
|
||||
SYSTEM_ALLOC := True
|
||||
SYSTEM_FREESTORE := True
|
||||
__NO_DISKCACHE__ := False
|
||||
__FREEZE_VCHUNKS__ := True
|
||||
__FREEZE_GRP_PACKETS__ := True
|
||||
__MINIMIZE_TREE_CACHE__:= True
|
||||
|
||||
SYSTEM STD PARAMETERS...
|
||||
__STDOUT__ := False
|
||||
NULL := 0
|
||||
LPTR := False
|
||||
False_Status := 1
|
||||
True_Status := 0
|
||||
LARGE := True
|
||||
TWOBYTE_BOOL := False
|
||||
__NOSTR__ := False
|
||||
|
||||
MEMORY VALIDATION PARAMETERS...
|
||||
CORE_CRC_CHECK := False
|
||||
VALIDATE_MEM_CHUNKS := False
|
||||
|
||||
SYSTEM DEBUG OPTIONS...
|
||||
DEBUG := False
|
||||
MCSTAT := False
|
||||
TRACKBACK := False
|
||||
FLUSH_FILES := False
|
||||
DEBUG_CORE0 := False
|
||||
DEBUG_RISC := False
|
||||
__TREE_BUG__ := False
|
||||
__TRACK_FILE_READS__ := False
|
||||
PAGE_SPACE := False
|
||||
LEAVE_NO_TRACE := True
|
||||
NULL_TRACE_STRS := False
|
||||
|
||||
TIME PARAMETERS...
|
||||
CLOCK_IS_LONG := False
|
||||
__DISPLAY_TIME__ := False
|
||||
__TREE_TIME__ := False
|
||||
__DISPLAY_ERRORS__ := False
|
||||
|
||||
API MACROS...
|
||||
__BMT01__ := True
|
||||
OPTIMIZE := True
|
||||
|
||||
END OF DEFINES.
|
||||
|
||||
|
||||
|
||||
... IMPLODE MEMORY ...
|
||||
|
||||
SWAP to DiskCache := False
|
||||
|
||||
FREEZE_GRP_PACKETS:= True
|
||||
|
||||
QueBug := 1000
|
||||
|
||||
sizeof(boolean) = 4
|
||||
sizeof(sizetype) = 4
|
||||
sizeof(chunkstruc) = 32
|
||||
|
||||
sizeof(shorttype ) = 2
|
||||
sizeof(idtype ) = 2
|
||||
sizeof(sizetype ) = 4
|
||||
sizeof(indextype ) = 4
|
||||
sizeof(numtype ) = 4
|
||||
sizeof(handletype) = 4
|
||||
sizeof(tokentype ) = 8
|
||||
|
||||
sizeof(short ) = 2
|
||||
sizeof(int ) = 4
|
||||
|
||||
sizeof(lt64 ) = 4
|
||||
sizeof(farlongtype) = 4
|
||||
sizeof(long ) = 4
|
||||
sizeof(longaddr ) = 4
|
||||
|
||||
sizeof(float ) = 4
|
||||
sizeof(double ) = 8
|
||||
|
||||
sizeof(addrtype ) = 4
|
||||
sizeof(char * ) = 4
|
||||
ALLOC CORE_1 :: 8
|
||||
BHOOLE NATH
|
||||
|
||||
OPEN File ./input/bendian.rnv
|
||||
*Status = 0
|
||||
DB HDR restored from FileVbn[ 0]
|
||||
DB BlkDirOffset : @ 2030c0
|
||||
DB BlkDirChunk : Chunk[ 10] AT Vbn[3146]
|
||||
DB BlkTknChunk : Chunk[ 11] AT Vbn[3147]
|
||||
DB BlkSizeChunk : Chunk[ 12] AT Vbn[3148]
|
||||
DB Handle Chunk's StackPtr = 20797
|
||||
|
||||
DB[ 1] LOADED; Handles= 20797
|
||||
KERNEL in CORE[ 1] Restored @ 1b4750
|
||||
|
||||
OPEN File ./input/bendian.wnv
|
||||
*Status = 0
|
||||
DB HDR restored from FileVbn[ 0]
|
||||
DB BlkDirOffset : @ 21c40
|
||||
DB BlkDirChunk : Chunk[ 31] AT Vbn[ 81]
|
||||
DB BlkTknChunk : Chunk[ 32] AT Vbn[ 82]
|
||||
DB BlkSizeChunk : Chunk[ 33] AT Vbn[ 83]
|
||||
DB Handle Chunk's StackPtr = 17
|
||||
|
||||
DB[ 2] LOADED; Handles= 17
|
||||
VORTEx_Status == -8 || fffffff8
|
||||
|
||||
BE HERE NOW !!!
|
||||
|
||||
|
||||
|
||||
... VORTEx ON LINE ...
|
||||
|
||||
|
||||
... END OF SESSION ...
|
||||
@ -0,0 +1,258 @@
|
||||
CREATE Db Header and Db Primal ...
|
||||
NEW DB [ 3] Created.
|
||||
|
||||
VORTEX INPUT PARAMETERS::
|
||||
MESSAGE FileName: smred.msg
|
||||
OUTPUT FileName: smred.out
|
||||
DISK CACHE FileName: NULL
|
||||
PART DB FileName: parts.db
|
||||
DRAW DB FileName: draw.db
|
||||
PERSON DB FileName: emp.db
|
||||
PERSONS Data FileName: ./input/persons.250
|
||||
PARTS Count : 100
|
||||
OUTER Loops : 1
|
||||
INNER Loops : 1
|
||||
LOOKUP Parts : 25
|
||||
DELETE Parts : 10
|
||||
STUFF Parts : 10
|
||||
DEPTH Traverse: 5
|
||||
% DECREASE Parts : 0
|
||||
% INCREASE LookUps : 0
|
||||
% INCREASE Deletes : 0
|
||||
% INCREASE Stuffs : 0
|
||||
FREEZE_PACKETS : 1
|
||||
ALLOC_CHUNKS : 10000
|
||||
EXTEND_CHUNKS : 5000
|
||||
DELETE Draw objects : True
|
||||
DELETE Part objects : False
|
||||
QUE_BUG : 1000
|
||||
VOID_BOUNDARY : 67108864
|
||||
VOID_RESERVE : 1048576
|
||||
|
||||
COMMIT_DBS : False
|
||||
|
||||
|
||||
|
||||
BMT TEST :: files...
|
||||
EdbName := PartLib
|
||||
EdbFileName := parts.db
|
||||
DrwName := DrawLib
|
||||
DrwFileName := draw.db
|
||||
EmpName := PersonLib
|
||||
EmpFileName := emp.db
|
||||
|
||||
Swap to DiskCache := False
|
||||
Freeze the cache := True
|
||||
|
||||
|
||||
BMT TEST :: parms...
|
||||
DeBug modulo := 1000
|
||||
Create Parts count:= 100
|
||||
Outer Loops := 1
|
||||
Inner Loops := 1
|
||||
Look Ups := 25
|
||||
Delete Parts := 10
|
||||
Stuff Parts := 10
|
||||
Traverse Limit := 5
|
||||
Delete Draws := True
|
||||
Delete Parts := False
|
||||
Delete ALL Parts := after every <mod 0>Outer Loop
|
||||
|
||||
INITIALIZE LIBRARY ::
|
||||
|
||||
INITIALIZE SCHEMA ::
|
||||
Primal_CreateDb Accessed !!!
|
||||
CREATE Db Header and Db Primal ...
|
||||
NEW DB [ 4] Created.
|
||||
PartLibCreate:: Db[ 4]; VpartsDir= 1
|
||||
|
||||
Part Count= 1
|
||||
|
||||
Initialize the Class maps
|
||||
LIST HEADS loaded ... DbListHead_Class = 207
|
||||
DbListNode_Class = 206
|
||||
|
||||
...NOTE... ShellLoadCode:: Class[ 228] will NOT be Activated.
|
||||
|
||||
|
||||
...NOTE... ShellLoadCode:: Class[ 229] will NOT be Activated.
|
||||
|
||||
Primal_CreateDb Accessed !!!
|
||||
CREATE Db Header and Db Primal ...
|
||||
NEW DB [ 5] Created.
|
||||
DrawLibCreate:: Db[ 5]; VpartsDir= 1
|
||||
|
||||
Initialize the Class maps of this schema.
|
||||
Primal_CreateDb Accessed !!!
|
||||
CREATE Db Header and Db Primal ...
|
||||
NEW DB [ 6] Created.
|
||||
|
||||
***NOTE*** Persons Library Extended!
|
||||
|
||||
Create <131072> Persons.
|
||||
ItNum 0. Person[ 6: 5]. Name= Riddell , Robert V. ;
|
||||
|
||||
LAST Person Read::
|
||||
ItNum 250. Person[ 6: 503]. Name= Gonzales , Warren X. ;
|
||||
|
||||
BUILD <Query0> for <Part2> class::
|
||||
|
||||
if (link[1].length >= 5) ::
|
||||
|
||||
Build Query2 for <Address> class::
|
||||
|
||||
if (State == CA || State == T*)
|
||||
|
||||
Build Query1 for <Person> class::
|
||||
|
||||
if (LastName >= H* && LastName <= P* && Query0(Residence)) ::
|
||||
|
||||
BUILD <Query3> for <DrawObj> class::
|
||||
|
||||
if (Id >= 3000
|
||||
&& (Id >= 3000 && Id <= 3001)
|
||||
&& Id >= 3002)
|
||||
|
||||
BUILD <Query4> for <NamedDrawObj> class::
|
||||
|
||||
if (Nam == Pre*
|
||||
|| (Nam == ??Mid??? || == Pre??Mid?? || == ??Post
|
||||
|| == Pre??Post || == ??Mid???Post || == Pre??Mid???Post)
|
||||
&& Id <= 7)
|
||||
SEED := 1008; Swap = False; RgnEntries = 135
|
||||
|
||||
OUTER LOOP [ 1] : NewParts = 100 LookUps = 25 StuffParts = 10.
|
||||
|
||||
Create 100 New Parts
|
||||
Create Part 1. Token[ 4: 2].
|
||||
|
||||
< 100> Parts Created. CurrentId= 100
|
||||
|
||||
Connect each instantiated Part TO 3 unique Parts
|
||||
Connect Part 1. Token[ 4: 2]
|
||||
Connect Part 25. Token[ 4: 26] FromList= 26.
|
||||
Connect Part 12. Token[ 4: 13] FromList= 13.
|
||||
Connect Part 59. Token[ 4: 60] FromList= 60.
|
||||
|
||||
SET <DrawObjs> entries::
|
||||
1. [ 5: 5] := <1 >; @[: 6]
|
||||
Iteration count = 100
|
||||
|
||||
SET <NamedDrawObjs> entries::
|
||||
1. [ 5: 39] := <14 >;
|
||||
Iteration count = 12
|
||||
|
||||
SET <LibRectangles> entries::
|
||||
1. [ 5: 23] := <8 >; @[: 24]
|
||||
Iteration count = 12
|
||||
|
||||
LIST <DbRectangles> entries::
|
||||
1. [ 5: 23]
|
||||
Iteration count = 12
|
||||
|
||||
SET <PersonNames > entries::
|
||||
Iteration count = 250
|
||||
|
||||
COMMIT All Image copies:: Release=<True>; Max Parts= 100
|
||||
< 100> Part images' Committed.
|
||||
< 0> are Named.
|
||||
< 50> Point images' Committed.
|
||||
< 81> Person images' Committed.
|
||||
|
||||
COMMIT Parts(* 100)
|
||||
|
||||
Commit TestObj_Class in <Primal> DB.
|
||||
ItNum 0. Token[ 0: 0]. TestObj Committed.
|
||||
< 0> TestObj images' Committed.
|
||||
|
||||
Commit CartesianPoint_Class in <Primal> DB.
|
||||
ItNum 0. Token[ 0: 0]. CartesianPoint Committed.
|
||||
< 0> CartesianPoint images' Committed.
|
||||
|
||||
BEGIN Inner Loop Sequence::.
|
||||
|
||||
INNER LOOP [ 1: 1] :
|
||||
|
||||
LOOK UP 25 Random Parts and Export each Part.
|
||||
|
||||
LookUp for 26 parts; Asserts = 8
|
||||
<Part2 > Asserts = 2; NULL Asserts = 3.
|
||||
<DrawObj > Asserts = 0; NULL Asserts = 5.
|
||||
<NamedObj > Asserts = 0; NULL Asserts = 0.
|
||||
<Person > Asserts = 0; NULL Asserts = 5.
|
||||
<TestObj > Asserts = 60; NULL Asserts = 0.
|
||||
|
||||
DELETE 10 Random Parts.
|
||||
|
||||
PartDelete :: Token[ 4: 91].
|
||||
PartDisconnect:: Token[ 4: 91] id:= 90 for each link.
|
||||
DisConnect link [ 0]:= 50; PartToken[ 51: 51].
|
||||
DisConnect link [ 1]:= 17; PartToken[ 18: 18].
|
||||
DisConnect link [ 2]:= 72; PartToken[ 73: 73].
|
||||
DeleteFromList:: Vchunk[ 4: 91]. (* 1)
|
||||
DisConnect FromList[ 0]:= 56; Token[ 57: 57].
|
||||
Vlists[ 89] := 100;
|
||||
|
||||
Delete for 11 parts;
|
||||
|
||||
Traverse Count= 0
|
||||
|
||||
TRAVERSE PartId[ 6] and all Connections to 5 Levels
|
||||
SEED In Traverse Part [ 4: 65] @ Level = 4.
|
||||
|
||||
Traverse Count= 357
|
||||
Traverse Asserts = 5. True Tests = 1
|
||||
< 5> DrawObj objects DELETED.
|
||||
< 2> are Named.
|
||||
< 2> Point objects DELETED.
|
||||
|
||||
CREATE 10 Additional Parts
|
||||
|
||||
Create 10 New Parts
|
||||
Create Part 101. Token[ 4: 102].
|
||||
|
||||
< 10> Parts Created. CurrentId= 110
|
||||
|
||||
Connect each instantiated Part TO 3 unique Parts
|
||||
|
||||
COMMIT All Image copies:: Release=<True>; Max Parts= 110
|
||||
< 81> Part images' Committed.
|
||||
< 0> are Named.
|
||||
< 38> Point images' Committed.
|
||||
< 31> Person images' Committed.
|
||||
|
||||
COMMIT Parts(* 100)
|
||||
|
||||
Commit TestObj_Class in <Primal> DB.
|
||||
ItNum 0. Token[ 3: 4]. TestObj Committed.
|
||||
< 15> TestObj images' Committed.
|
||||
|
||||
Commit CartesianPoint_Class in <Primal> DB.
|
||||
ItNum 0. Token[ 3: 3]. CartesianPoint Committed.
|
||||
< 16> CartesianPoint images' Committed.
|
||||
|
||||
DELETE All TestObj objects;
|
||||
|
||||
Delete TestObj_Class in <Primal> DB.
|
||||
ItNum 0. Token[ 3: 4]. TestObj Deleted.
|
||||
< 15> TestObj objects Deleted.
|
||||
|
||||
Commit CartesianPoint_Class in <Primal> DB.
|
||||
ItNum 0. Token[ 3: 3]. CartesianPoint Deleted.
|
||||
< 16> CartesianPoint objects Deleted.
|
||||
|
||||
DELETE TestObj and Point objects...
|
||||
|
||||
END INNER LOOP [ 1: 1].
|
||||
|
||||
DELETE All TestObj objects;
|
||||
|
||||
Delete TestObj_Class in <Primal> DB.
|
||||
< 0> TestObj objects Deleted.
|
||||
|
||||
Commit CartesianPoint_Class in <Primal> DB.
|
||||
< 0> CartesianPoint objects Deleted.
|
||||
|
||||
DELETE TestObj and Point objects...
|
||||
STATUS= -201
|
||||
V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!
|
||||
@ -0,0 +1,62 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.068149 # Number of seconds simulated
|
||||
sim_ticks 68148678500 # Number of ticks simulated
|
||||
final_tick 68148678500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 2876458 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2913702 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1458542737 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 222372 # Number of bytes of host memory used
|
||||
host_seconds 46.72 # Real time elapsed on the host
|
||||
sim_insts 134398975 # Number of instructions simulated
|
||||
sim_ops 136139203 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 538214332 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 147559361 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 685773693 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 538214332 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 538214332 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::cpu.data 89882950 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 89882950 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 134553583 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 37231301 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 171784884 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::cpu.data 20864304 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 20864304 # Number of write requests responded to by this memory
|
||||
system.physmem.num_other::cpu.data 15916 # Number of other requests responded to by this memory
|
||||
system.physmem.num_other::total 15916 # Number of other requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 7897648844 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 2165256381 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 10062905226 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 7897648844 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 7897648844 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::cpu.data 1318924328 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 1318924328 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 7897648844 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 3484180709 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 11381829554 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu.workload.num_syscalls 1946 # Number of system calls
|
||||
system.cpu.numCycles 136297358 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 134398975 # Number of instructions committed
|
||||
system.cpu.committedOps 136139203 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 115187758 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 2326977 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 1709332 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 8898970 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 115187758 # number of integer instructions
|
||||
system.cpu.num_fp_insts 2326977 # number of float instructions
|
||||
system.cpu.num_int_register_reads 263032383 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 113147747 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 4725607 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 1150968 # number of times the floating registers were written
|
||||
system.cpu.num_mem_refs 58160249 # number of memory refs
|
||||
system.cpu.num_load_insts 37275868 # Number of load instructions
|
||||
system.cpu.num_store_insts 20884381 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 136297358 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
@ -0,0 +1,198 @@
|
||||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
full_system=false
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
||||
[system]
|
||||
type=System
|
||||
children=cpu membus physmem
|
||||
boot_osflags=a
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
mem_mode=atomic
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
readfile=
|
||||
symbolfile=
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.membus.slave[0]
|
||||
|
||||
[system.cpu]
|
||||
type=TimingSimpleCPU
|
||||
children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
|
||||
checker=Null
|
||||
clock=500
|
||||
cpu_id=0
|
||||
defer_registration=false
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
interrupts=system.cpu.interrupts
|
||||
itb=system.cpu.itb
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
phase=0
|
||||
profile=0
|
||||
progress_interval=0
|
||||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
workload=system.cpu.workload
|
||||
dcache_port=system.cpu.dcache.cpu_side
|
||||
icache_port=system.cpu.icache.cpu_side
|
||||
|
||||
[system.cpu.dcache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=262144
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.dcache_port
|
||||
mem_side=system.cpu.toL2Bus.slave[1]
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=SparcTLB
|
||||
size=64
|
||||
|
||||
[system.cpu.icache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=131072
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.icache_port
|
||||
mem_side=system.cpu.toL2Bus.slave[0]
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=SparcInterrupts
|
||||
|
||||
[system.cpu.itb]
|
||||
type=SparcTLB
|
||||
size=64
|
||||
|
||||
[system.cpu.l2cache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=false
|
||||
latency=10000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=2097152
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.toL2Bus.master[0]
|
||||
mem_side=system.membus.slave[1]
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
master=system.cpu.l2cache.cpu_side
|
||||
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
|
||||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
|
||||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=vortex bendian.raw
|
||||
cwd=build/SPARC/tests/opt/long/se/50.vortex/sparc/linux/simple-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/cpu2000/binaries/sparc/linux/vortex
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
ppid=99
|
||||
simpoint=0
|
||||
system=system
|
||||
uid=100
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
master=system.physmem.port[0]
|
||||
slave=system.system_port system.cpu.l2cache.mem_side
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.membus.master[0]
|
||||
|
||||
563
simulators/gem5/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/simerr
Executable file
563
simulators/gem5/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/simerr
Executable file
@ -0,0 +1,563 @@
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: ignoring syscall time(4026528248, 4026527848, ...)
|
||||
warn: ignoring syscall time(1375098, 4026527400, ...)
|
||||
warn: ignoring syscall time(1, 4026527312, ...)
|
||||
warn: ignoring syscall time(413, 4026527048, ...)
|
||||
warn: ignoring syscall time(414, 4026527048, ...)
|
||||
warn: ignoring syscall time(4026527688, 4026527288, ...)
|
||||
warn: ignoring syscall time(1375098, 4026526840, ...)
|
||||
warn: ignoring syscall time(409, 4026527048, ...)
|
||||
warn: ignoring syscall time(409, 4026527048, ...)
|
||||
warn: ignoring syscall time(409, 4026526960, ...)
|
||||
warn: ignoring syscall time(409, 4026527040, ...)
|
||||
warn: ignoring syscall time(409, 4026527000, ...)
|
||||
warn: ignoring syscall time(409, 4026526984, ...)
|
||||
warn: ignoring syscall time(409, 4026526984, ...)
|
||||
warn: ignoring syscall time(409, 4026526872, ...)
|
||||
warn: ignoring syscall time(19045, 4026526312, ...)
|
||||
warn: ignoring syscall time(409, 4026526832, ...)
|
||||
warn: ignoring syscall time(409, 4026526872, ...)
|
||||
warn: ignoring syscall time(409, 4026526872, ...)
|
||||
warn: ignoring syscall time(409, 4026526848, ...)
|
||||
warn: ignoring syscall time(409, 4026526840, ...)
|
||||
warn: ignoring syscall time(409, 4026526872, ...)
|
||||
warn: ignoring syscall time(409, 4026526856, ...)
|
||||
warn: ignoring syscall time(409, 4026526848, ...)
|
||||
warn: ignoring syscall time(409, 4026526936, ...)
|
||||
warn: ignoring syscall time(4026527408, 4026527008, ...)
|
||||
warn: ignoring syscall time(1375098, 4026526560, ...)
|
||||
warn: ignoring syscall time(18732, 4026527184, ...)
|
||||
warn: ignoring syscall time(409, 4026526632, ...)
|
||||
warn: ignoring syscall time(0, 4026526736, ...)
|
||||
warn: ignoring syscall time(0, 4026527320, ...)
|
||||
warn: ignoring syscall time(225, 4026527744, ...)
|
||||
warn: ignoring syscall time(409, 4026527048, ...)
|
||||
warn: ignoring syscall time(409, 4026526856, ...)
|
||||
warn: ignoring syscall time(409, 4026526872, ...)
|
||||
warn: ignoring syscall time(4026527496, 4026527096, ...)
|
||||
warn: ignoring syscall time(1375098, 4026526648, ...)
|
||||
warn: ignoring syscall time(0, 4026526824, ...)
|
||||
warn: ignoring syscall time(0, 4026527320, ...)
|
||||
warn: ignoring syscall time(1879089152, 4026527184, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall times(246, 4026527728, ...)
|
||||
warn: ignoring syscall time(1595768, 4026527472, ...)
|
||||
warn: ignoring syscall time(17300, 4026526912, ...)
|
||||
warn: ignoring syscall time(0, 4026527472, ...)
|
||||
warn: ignoring syscall time(0, 4026527472, ...)
|
||||
warn: ignoring syscall time(19045, 4026526912, ...)
|
||||
warn: ignoring syscall time(0, 4026527472, ...)
|
||||
warn: ignoring syscall time(0, 4026527472, ...)
|
||||
warn: ignoring syscall time(0, 4026527472, ...)
|
||||
warn: ignoring syscall time(0, 4026527472, ...)
|
||||
warn: ignoring syscall time(0, 4026527472, ...)
|
||||
warn: ignoring syscall time(0, 4026527472, ...)
|
||||
warn: ignoring syscall time(0, 4026527472, ...)
|
||||
warn: ignoring syscall time(0, 4026527472, ...)
|
||||
warn: ignoring syscall time(0, 4026527472, ...)
|
||||
warn: ignoring syscall time(19045, 4026526912, ...)
|
||||
warn: ignoring syscall time(17300, 4026526912, ...)
|
||||
warn: ignoring syscall time(20500, 4026525968, ...)
|
||||
warn: ignoring syscall time(4026526436, 4026525968, ...)
|
||||
warn: ignoring syscall time(7004192, 4026526056, ...)
|
||||
warn: ignoring syscall time(4, 4026527512, ...)
|
||||
warn: ignoring syscall time(0, 4026525760, ...)
|
||||
hack: be nice to actually delete the event here
|
||||
11
simulators/gem5/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/simout
Executable file
11
simulators/gem5/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/simout
Executable file
@ -0,0 +1,11 @@
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jun 4 2012 12:01:47
|
||||
gem5 started Jun 4 2012 14:59:31
|
||||
gem5 executing on zizzer
|
||||
command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/50.vortex/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/long/se/50.vortex/sparc/linux/simple-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
Exiting @ tick 202941992000 because target called exit()
|
||||
@ -0,0 +1,158 @@
|
||||
|
||||
SYSTEM TYPE...
|
||||
__ZTC__ := False
|
||||
__UNIX__ := True
|
||||
__RISC__ := True
|
||||
SPEC_CPU2000_LP64 := False
|
||||
__MAC__ := False
|
||||
__BCC__ := False
|
||||
__BORLANDC__ := False
|
||||
__GUI__ := False
|
||||
__WTC__ := False
|
||||
__HP__ := False
|
||||
|
||||
CODE OPTIONS...
|
||||
__MACROIZE_HM__ := True
|
||||
__MACROIZE_MEM__ := True
|
||||
ENV01 := True
|
||||
USE_HPP_STYPE_HDRS := False
|
||||
USE_H_STYPE_HDRS := False
|
||||
|
||||
CODE INCLUSION PARAMETERS...
|
||||
INCLUDE_ALL_CODE := False
|
||||
INCLUDE_DELETE_CODE := True
|
||||
__SWAP_GRP_POS__ := True
|
||||
__INCLUDE_MTRX__ := False
|
||||
__BAD_CODE__ := False
|
||||
API_INCLUDE := False
|
||||
BE_CAREFUL := False
|
||||
OLDWAY := False
|
||||
NOTUSED := False
|
||||
|
||||
SYSTEM PARAMETERS...
|
||||
EXT_ENUM := 999999999L
|
||||
CHUNK_CONSTANT := 55555555
|
||||
CORE_CONSTANT := 55555555
|
||||
CORE_LIMIT := 20971520
|
||||
CorePage_Size := 384000
|
||||
ALIGN_BYTES := True
|
||||
CORE_BLOCK_ALIGN := 8
|
||||
FAR_MEM := False
|
||||
|
||||
MEMORY MANAGEMENT PARAMETERS...
|
||||
SYSTEM_ALLOC := True
|
||||
SYSTEM_FREESTORE := True
|
||||
__NO_DISKCACHE__ := False
|
||||
__FREEZE_VCHUNKS__ := True
|
||||
__FREEZE_GRP_PACKETS__ := True
|
||||
__MINIMIZE_TREE_CACHE__:= True
|
||||
|
||||
SYSTEM STD PARAMETERS...
|
||||
__STDOUT__ := False
|
||||
NULL := 0
|
||||
LPTR := False
|
||||
False_Status := 1
|
||||
True_Status := 0
|
||||
LARGE := True
|
||||
TWOBYTE_BOOL := False
|
||||
__NOSTR__ := False
|
||||
|
||||
MEMORY VALIDATION PARAMETERS...
|
||||
CORE_CRC_CHECK := False
|
||||
VALIDATE_MEM_CHUNKS := False
|
||||
|
||||
SYSTEM DEBUG OPTIONS...
|
||||
DEBUG := False
|
||||
MCSTAT := False
|
||||
TRACKBACK := False
|
||||
FLUSH_FILES := False
|
||||
DEBUG_CORE0 := False
|
||||
DEBUG_RISC := False
|
||||
__TREE_BUG__ := False
|
||||
__TRACK_FILE_READS__ := False
|
||||
PAGE_SPACE := False
|
||||
LEAVE_NO_TRACE := True
|
||||
NULL_TRACE_STRS := False
|
||||
|
||||
TIME PARAMETERS...
|
||||
CLOCK_IS_LONG := False
|
||||
__DISPLAY_TIME__ := False
|
||||
__TREE_TIME__ := False
|
||||
__DISPLAY_ERRORS__ := False
|
||||
|
||||
API MACROS...
|
||||
__BMT01__ := True
|
||||
OPTIMIZE := True
|
||||
|
||||
END OF DEFINES.
|
||||
|
||||
|
||||
|
||||
... IMPLODE MEMORY ...
|
||||
|
||||
SWAP to DiskCache := False
|
||||
|
||||
FREEZE_GRP_PACKETS:= True
|
||||
|
||||
QueBug := 1000
|
||||
|
||||
sizeof(boolean) = 4
|
||||
sizeof(sizetype) = 4
|
||||
sizeof(chunkstruc) = 32
|
||||
|
||||
sizeof(shorttype ) = 2
|
||||
sizeof(idtype ) = 2
|
||||
sizeof(sizetype ) = 4
|
||||
sizeof(indextype ) = 4
|
||||
sizeof(numtype ) = 4
|
||||
sizeof(handletype) = 4
|
||||
sizeof(tokentype ) = 8
|
||||
|
||||
sizeof(short ) = 2
|
||||
sizeof(int ) = 4
|
||||
|
||||
sizeof(lt64 ) = 4
|
||||
sizeof(farlongtype) = 4
|
||||
sizeof(long ) = 4
|
||||
sizeof(longaddr ) = 4
|
||||
|
||||
sizeof(float ) = 4
|
||||
sizeof(double ) = 8
|
||||
|
||||
sizeof(addrtype ) = 4
|
||||
sizeof(char * ) = 4
|
||||
ALLOC CORE_1 :: 8
|
||||
BHOOLE NATH
|
||||
|
||||
OPEN File ./input/bendian.rnv
|
||||
*Status = 0
|
||||
DB HDR restored from FileVbn[ 0]
|
||||
DB BlkDirOffset : @ 2030c0
|
||||
DB BlkDirChunk : Chunk[ 10] AT Vbn[3146]
|
||||
DB BlkTknChunk : Chunk[ 11] AT Vbn[3147]
|
||||
DB BlkSizeChunk : Chunk[ 12] AT Vbn[3148]
|
||||
DB Handle Chunk's StackPtr = 20797
|
||||
|
||||
DB[ 1] LOADED; Handles= 20797
|
||||
KERNEL in CORE[ 1] Restored @ 1b4750
|
||||
|
||||
OPEN File ./input/bendian.wnv
|
||||
*Status = 0
|
||||
DB HDR restored from FileVbn[ 0]
|
||||
DB BlkDirOffset : @ 21c40
|
||||
DB BlkDirChunk : Chunk[ 31] AT Vbn[ 81]
|
||||
DB BlkTknChunk : Chunk[ 32] AT Vbn[ 82]
|
||||
DB BlkSizeChunk : Chunk[ 33] AT Vbn[ 83]
|
||||
DB Handle Chunk's StackPtr = 17
|
||||
|
||||
DB[ 2] LOADED; Handles= 17
|
||||
VORTEx_Status == -8 || fffffff8
|
||||
|
||||
BE HERE NOW !!!
|
||||
|
||||
|
||||
|
||||
... VORTEx ON LINE ...
|
||||
|
||||
|
||||
... END OF SESSION ...
|
||||
@ -0,0 +1,258 @@
|
||||
CREATE Db Header and Db Primal ...
|
||||
NEW DB [ 3] Created.
|
||||
|
||||
VORTEX INPUT PARAMETERS::
|
||||
MESSAGE FileName: smred.msg
|
||||
OUTPUT FileName: smred.out
|
||||
DISK CACHE FileName: NULL
|
||||
PART DB FileName: parts.db
|
||||
DRAW DB FileName: draw.db
|
||||
PERSON DB FileName: emp.db
|
||||
PERSONS Data FileName: ./input/persons.250
|
||||
PARTS Count : 100
|
||||
OUTER Loops : 1
|
||||
INNER Loops : 1
|
||||
LOOKUP Parts : 25
|
||||
DELETE Parts : 10
|
||||
STUFF Parts : 10
|
||||
DEPTH Traverse: 5
|
||||
% DECREASE Parts : 0
|
||||
% INCREASE LookUps : 0
|
||||
% INCREASE Deletes : 0
|
||||
% INCREASE Stuffs : 0
|
||||
FREEZE_PACKETS : 1
|
||||
ALLOC_CHUNKS : 10000
|
||||
EXTEND_CHUNKS : 5000
|
||||
DELETE Draw objects : True
|
||||
DELETE Part objects : False
|
||||
QUE_BUG : 1000
|
||||
VOID_BOUNDARY : 67108864
|
||||
VOID_RESERVE : 1048576
|
||||
|
||||
COMMIT_DBS : False
|
||||
|
||||
|
||||
|
||||
BMT TEST :: files...
|
||||
EdbName := PartLib
|
||||
EdbFileName := parts.db
|
||||
DrwName := DrawLib
|
||||
DrwFileName := draw.db
|
||||
EmpName := PersonLib
|
||||
EmpFileName := emp.db
|
||||
|
||||
Swap to DiskCache := False
|
||||
Freeze the cache := True
|
||||
|
||||
|
||||
BMT TEST :: parms...
|
||||
DeBug modulo := 1000
|
||||
Create Parts count:= 100
|
||||
Outer Loops := 1
|
||||
Inner Loops := 1
|
||||
Look Ups := 25
|
||||
Delete Parts := 10
|
||||
Stuff Parts := 10
|
||||
Traverse Limit := 5
|
||||
Delete Draws := True
|
||||
Delete Parts := False
|
||||
Delete ALL Parts := after every <mod 0>Outer Loop
|
||||
|
||||
INITIALIZE LIBRARY ::
|
||||
|
||||
INITIALIZE SCHEMA ::
|
||||
Primal_CreateDb Accessed !!!
|
||||
CREATE Db Header and Db Primal ...
|
||||
NEW DB [ 4] Created.
|
||||
PartLibCreate:: Db[ 4]; VpartsDir= 1
|
||||
|
||||
Part Count= 1
|
||||
|
||||
Initialize the Class maps
|
||||
LIST HEADS loaded ... DbListHead_Class = 207
|
||||
DbListNode_Class = 206
|
||||
|
||||
...NOTE... ShellLoadCode:: Class[ 228] will NOT be Activated.
|
||||
|
||||
|
||||
...NOTE... ShellLoadCode:: Class[ 229] will NOT be Activated.
|
||||
|
||||
Primal_CreateDb Accessed !!!
|
||||
CREATE Db Header and Db Primal ...
|
||||
NEW DB [ 5] Created.
|
||||
DrawLibCreate:: Db[ 5]; VpartsDir= 1
|
||||
|
||||
Initialize the Class maps of this schema.
|
||||
Primal_CreateDb Accessed !!!
|
||||
CREATE Db Header and Db Primal ...
|
||||
NEW DB [ 6] Created.
|
||||
|
||||
***NOTE*** Persons Library Extended!
|
||||
|
||||
Create <131072> Persons.
|
||||
ItNum 0. Person[ 6: 5]. Name= Riddell , Robert V. ;
|
||||
|
||||
LAST Person Read::
|
||||
ItNum 250. Person[ 6: 503]. Name= Gonzales , Warren X. ;
|
||||
|
||||
BUILD <Query0> for <Part2> class::
|
||||
|
||||
if (link[1].length >= 5) ::
|
||||
|
||||
Build Query2 for <Address> class::
|
||||
|
||||
if (State == CA || State == T*)
|
||||
|
||||
Build Query1 for <Person> class::
|
||||
|
||||
if (LastName >= H* && LastName <= P* && Query0(Residence)) ::
|
||||
|
||||
BUILD <Query3> for <DrawObj> class::
|
||||
|
||||
if (Id >= 3000
|
||||
&& (Id >= 3000 && Id <= 3001)
|
||||
&& Id >= 3002)
|
||||
|
||||
BUILD <Query4> for <NamedDrawObj> class::
|
||||
|
||||
if (Nam == Pre*
|
||||
|| (Nam == ??Mid??? || == Pre??Mid?? || == ??Post
|
||||
|| == Pre??Post || == ??Mid???Post || == Pre??Mid???Post)
|
||||
&& Id <= 7)
|
||||
SEED := 1008; Swap = False; RgnEntries = 135
|
||||
|
||||
OUTER LOOP [ 1] : NewParts = 100 LookUps = 25 StuffParts = 10.
|
||||
|
||||
Create 100 New Parts
|
||||
Create Part 1. Token[ 4: 2].
|
||||
|
||||
< 100> Parts Created. CurrentId= 100
|
||||
|
||||
Connect each instantiated Part TO 3 unique Parts
|
||||
Connect Part 1. Token[ 4: 2]
|
||||
Connect Part 25. Token[ 4: 26] FromList= 26.
|
||||
Connect Part 12. Token[ 4: 13] FromList= 13.
|
||||
Connect Part 59. Token[ 4: 60] FromList= 60.
|
||||
|
||||
SET <DrawObjs> entries::
|
||||
1. [ 5: 5] := <1 >; @[: 6]
|
||||
Iteration count = 100
|
||||
|
||||
SET <NamedDrawObjs> entries::
|
||||
1. [ 5: 39] := <14 >;
|
||||
Iteration count = 12
|
||||
|
||||
SET <LibRectangles> entries::
|
||||
1. [ 5: 23] := <8 >; @[: 24]
|
||||
Iteration count = 12
|
||||
|
||||
LIST <DbRectangles> entries::
|
||||
1. [ 5: 23]
|
||||
Iteration count = 12
|
||||
|
||||
SET <PersonNames > entries::
|
||||
Iteration count = 250
|
||||
|
||||
COMMIT All Image copies:: Release=<True>; Max Parts= 100
|
||||
< 100> Part images' Committed.
|
||||
< 0> are Named.
|
||||
< 50> Point images' Committed.
|
||||
< 81> Person images' Committed.
|
||||
|
||||
COMMIT Parts(* 100)
|
||||
|
||||
Commit TestObj_Class in <Primal> DB.
|
||||
ItNum 0. Token[ 0: 0]. TestObj Committed.
|
||||
< 0> TestObj images' Committed.
|
||||
|
||||
Commit CartesianPoint_Class in <Primal> DB.
|
||||
ItNum 0. Token[ 0: 0]. CartesianPoint Committed.
|
||||
< 0> CartesianPoint images' Committed.
|
||||
|
||||
BEGIN Inner Loop Sequence::.
|
||||
|
||||
INNER LOOP [ 1: 1] :
|
||||
|
||||
LOOK UP 25 Random Parts and Export each Part.
|
||||
|
||||
LookUp for 26 parts; Asserts = 8
|
||||
<Part2 > Asserts = 2; NULL Asserts = 3.
|
||||
<DrawObj > Asserts = 0; NULL Asserts = 5.
|
||||
<NamedObj > Asserts = 0; NULL Asserts = 0.
|
||||
<Person > Asserts = 0; NULL Asserts = 5.
|
||||
<TestObj > Asserts = 60; NULL Asserts = 0.
|
||||
|
||||
DELETE 10 Random Parts.
|
||||
|
||||
PartDelete :: Token[ 4: 91].
|
||||
PartDisconnect:: Token[ 4: 91] id:= 90 for each link.
|
||||
DisConnect link [ 0]:= 50; PartToken[ 51: 51].
|
||||
DisConnect link [ 1]:= 17; PartToken[ 18: 18].
|
||||
DisConnect link [ 2]:= 72; PartToken[ 73: 73].
|
||||
DeleteFromList:: Vchunk[ 4: 91]. (* 1)
|
||||
DisConnect FromList[ 0]:= 56; Token[ 57: 57].
|
||||
Vlists[ 89] := 100;
|
||||
|
||||
Delete for 11 parts;
|
||||
|
||||
Traverse Count= 0
|
||||
|
||||
TRAVERSE PartId[ 6] and all Connections to 5 Levels
|
||||
SEED In Traverse Part [ 4: 65] @ Level = 4.
|
||||
|
||||
Traverse Count= 357
|
||||
Traverse Asserts = 5. True Tests = 1
|
||||
< 5> DrawObj objects DELETED.
|
||||
< 2> are Named.
|
||||
< 2> Point objects DELETED.
|
||||
|
||||
CREATE 10 Additional Parts
|
||||
|
||||
Create 10 New Parts
|
||||
Create Part 101. Token[ 4: 102].
|
||||
|
||||
< 10> Parts Created. CurrentId= 110
|
||||
|
||||
Connect each instantiated Part TO 3 unique Parts
|
||||
|
||||
COMMIT All Image copies:: Release=<True>; Max Parts= 110
|
||||
< 81> Part images' Committed.
|
||||
< 0> are Named.
|
||||
< 38> Point images' Committed.
|
||||
< 31> Person images' Committed.
|
||||
|
||||
COMMIT Parts(* 100)
|
||||
|
||||
Commit TestObj_Class in <Primal> DB.
|
||||
ItNum 0. Token[ 3: 4]. TestObj Committed.
|
||||
< 15> TestObj images' Committed.
|
||||
|
||||
Commit CartesianPoint_Class in <Primal> DB.
|
||||
ItNum 0. Token[ 3: 3]. CartesianPoint Committed.
|
||||
< 16> CartesianPoint images' Committed.
|
||||
|
||||
DELETE All TestObj objects;
|
||||
|
||||
Delete TestObj_Class in <Primal> DB.
|
||||
ItNum 0. Token[ 3: 4]. TestObj Deleted.
|
||||
< 15> TestObj objects Deleted.
|
||||
|
||||
Commit CartesianPoint_Class in <Primal> DB.
|
||||
ItNum 0. Token[ 3: 3]. CartesianPoint Deleted.
|
||||
< 16> CartesianPoint objects Deleted.
|
||||
|
||||
DELETE TestObj and Point objects...
|
||||
|
||||
END INNER LOOP [ 1: 1].
|
||||
|
||||
DELETE All TestObj objects;
|
||||
|
||||
Delete TestObj_Class in <Primal> DB.
|
||||
< 0> TestObj objects Deleted.
|
||||
|
||||
Commit CartesianPoint_Class in <Primal> DB.
|
||||
< 0> CartesianPoint objects Deleted.
|
||||
|
||||
DELETE TestObj and Point objects...
|
||||
STATUS= -201
|
||||
V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!
|
||||
@ -0,0 +1,397 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.202942 # Number of seconds simulated
|
||||
sim_ticks 202941992000 # Number of ticks simulated
|
||||
final_tick 202941992000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1325068 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1342225 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2000847198 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 231252 # Number of bytes of host memory used
|
||||
host_seconds 101.43 # Real time elapsed on the host
|
||||
sim_insts 134398975 # Number of instructions simulated
|
||||
sim_ops 136139203 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 835264 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 8135040 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 8970304 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 835264 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 835264 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 5584960 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 5584960 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 13051 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 127110 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 140161 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 87265 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 87265 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 4115777 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 40085543 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 44201320 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 4115777 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 4115777 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 27519982 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 27519982 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 27519982 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 4115777 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 40085543 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 71721303 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu.workload.num_syscalls 1946 # Number of system calls
|
||||
system.cpu.numCycles 405883984 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 134398975 # Number of instructions committed
|
||||
system.cpu.committedOps 136139203 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 115187758 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 2326977 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 1709332 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 8898970 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 115187758 # number of integer instructions
|
||||
system.cpu.num_fp_insts 2326977 # number of float instructions
|
||||
system.cpu.num_int_register_reads 263032383 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 113147746 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 4725607 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 1150968 # number of times the floating registers were written
|
||||
system.cpu.num_mem_refs 58160249 # number of memory refs
|
||||
system.cpu.num_load_insts 37275868 # Number of load instructions
|
||||
system.cpu.num_store_insts 20884381 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 405883984 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.icache.replacements 184976 # number of replacements
|
||||
system.cpu.icache.tagsinuse 2004.721102 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 134366560 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 187024 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 718.445547 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 144544557000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 2004.721102 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.978868 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.978868 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 134366560 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 134366560 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 134366560 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 134366560 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 134366560 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 134366560 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 187024 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 187024 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 187024 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 187024 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 187024 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 187024 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 3166478000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 3166478000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 3166478000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 3166478000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 3166478000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 3166478000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 134553584 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 134553584 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 134553584 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 134553584 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 134553584 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 134553584 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001390 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.001390 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.001390 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.001390 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.001390 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.001390 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16930.864488 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 16930.864488 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 16930.864488 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 16930.864488 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 16930.864488 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 16930.864488 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 187024 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 187024 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 187024 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 187024 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 187024 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 187024 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2605406000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 2605406000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2605406000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 2605406000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2605406000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 2605406000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001390 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001390 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001390 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.001390 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001390 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.001390 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13930.864488 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13930.864488 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13930.864488 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 13930.864488 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13930.864488 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 13930.864488 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 146582 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 4087.617150 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 57960843 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 150678 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 384.666925 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 776708000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 4087.617150 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.997953 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.997953 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 37185802 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 37185802 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 20759140 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 20759140 # number of WriteReq hits
|
||||
system.cpu.dcache.SwapReq_hits::cpu.data 15901 # number of SwapReq hits
|
||||
system.cpu.dcache.SwapReq_hits::total 15901 # number of SwapReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 57944942 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 57944942 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 57944942 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 57944942 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 45499 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 45499 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 105164 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 105164 # number of WriteReq misses
|
||||
system.cpu.dcache.SwapReq_misses::cpu.data 15 # number of SwapReq misses
|
||||
system.cpu.dcache.SwapReq_misses::total 15 # number of SwapReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 150663 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 150663 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 150663 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 150663 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 1709246000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 1709246000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 5738404000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 5738404000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.SwapReq_miss_latency::cpu.data 462000 # number of SwapReq miss cycles
|
||||
system.cpu.dcache.SwapReq_miss_latency::total 462000 # number of SwapReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 7447650000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 7447650000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 7447650000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 7447650000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 37231301 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 37231301 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 20864304 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 20864304 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.SwapReq_accesses::cpu.data 15916 # number of SwapReq accesses(hits+misses)
|
||||
system.cpu.dcache.SwapReq_accesses::total 15916 # number of SwapReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 58095605 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 58095605 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 58095605 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 58095605 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001222 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.001222 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005040 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.005040 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.000942 # miss rate for SwapReq accesses
|
||||
system.cpu.dcache.SwapReq_miss_rate::total 0.000942 # miss rate for SwapReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.002593 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.002593 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.002593 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.002593 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 37566.671795 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 37566.671795 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54566.239398 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 54566.239398 # average WriteReq miss latency
|
||||
system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 30800 # average SwapReq miss latency
|
||||
system.cpu.dcache.SwapReq_avg_miss_latency::total 30800 # average SwapReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 49432.508313 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 49432.508313 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 49432.508313 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 49432.508313 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 118818 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 118818 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 45499 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 45499 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 105164 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 105164 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.SwapReq_mshr_misses::cpu.data 15 # number of SwapReq MSHR misses
|
||||
system.cpu.dcache.SwapReq_mshr_misses::total 15 # number of SwapReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 150663 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 150663 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 150663 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 150663 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1572749000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 1572749000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5422912000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 5422912000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 417000 # number of SwapReq MSHR miss cycles
|
||||
system.cpu.dcache.SwapReq_mshr_miss_latency::total 417000 # number of SwapReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6995661000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 6995661000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6995661000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 6995661000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001222 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001222 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005040 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005040 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.000942 # mshr miss rate for SwapReq accesses
|
||||
system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.000942 # mshr miss rate for SwapReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002593 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.002593 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002593 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.002593 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34566.671795 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34566.671795 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51566.239398 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51566.239398 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 27800 # average SwapReq mshr miss latency
|
||||
system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 27800 # average SwapReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 46432.508313 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 46432.508313 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 46432.508313 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 46432.508313 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 120138 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 19734.031622 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 212003 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 139002 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 1.525179 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::writebacks 15768.107062 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 2612.732810 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 1353.191750 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.481204 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.079734 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.041296 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.602235 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 173973 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 19969 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 193942 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 118818 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 118818 # number of Writeback hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 3599 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 3599 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 173973 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 23568 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 197541 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 173973 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 23568 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 197541 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 13051 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.data 25530 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 38581 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 101580 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 101580 # number of ReadExReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 13051 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 127110 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 140161 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 13051 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 127110 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 140161 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 678652000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1327560000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 2006212000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5282160000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 5282160000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 678652000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 6609720000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 7288372000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 678652000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 6609720000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 7288372000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 187024 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 45499 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 232523 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 118818 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 118818 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 105179 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 105179 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 187024 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 150678 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 337702 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 187024 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 150678 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 337702 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.069782 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.561111 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.165923 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.965782 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.965782 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.069782 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.843587 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.415043 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.069782 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.843587 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.415043 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks::writebacks 87265 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 87265 # number of writebacks
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 13051 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 25530 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::total 38581 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 101580 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 101580 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 13051 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 127110 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 140161 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 13051 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 127110 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 140161 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 522040000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1021200000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1543240000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4063200000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4063200000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 522040000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5084400000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 5606440000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 522040000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5084400000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 5606440000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.069782 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.561111 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.165923 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.965782 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.965782 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.069782 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.843587 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.415043 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.069782 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.843587 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.415043 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
Reference in New Issue
Block a user