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Adding gem5 source to svn.

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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1819 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
This commit is contained in:
friemel
2012-10-24 19:18:57 +00:00
parent f7ff71bd46
commit b41eec3f65
3222 changed files with 658579 additions and 1 deletions
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529
simulators/gem5/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini Normal file
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[root]
type=Root
children=system
full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
boot_osflags=a
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
readfile=
symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.cpu]
type=DerivO3CPU
children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
LSQDepCheckShift=4
RASSize=16
SQEntries=32
SSITSize=1024
activity=0
backComSize=5
cachePorts=200
checker=Null
choiceCtrBits=2
choicePredictorSize=8192
clock=500
commitToDecodeDelay=1
commitToFetchDelay=1
commitToIEWDelay=1
commitToRenameDelay=1
commitWidth=8
cpu_id=0
decodeToFetchDelay=1
decodeToRenameDelay=1
decodeWidth=8
defer_registration=false
dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
fetchToDecodeDelay=1
fetchTrapLatency=1
fetchWidth=8
forwardComSize=5
fuPool=system.cpu.fuPool
function_trace=false
function_trace_start=0
globalCtrBits=2
globalHistoryBits=13
globalPredictorSize=8192
iewToCommitDelay=1
iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
instShiftAmt=2
interrupts=system.cpu.interrupts
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
localCtrBits=2
localHistoryBits=11
localHistoryTableSize=2048
localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
needsTSO=false
numIQEntries=64
numPhysFloatRegs=256
numPhysIntRegs=256
numROBEntries=192
numRobs=1
numThreads=1
phase=0
predType=tournament
profile=0
progress_interval=0
renameToDecodeDelay=1
renameToFetchDelay=1
renameToIEWDelay=2
renameToROBDelay=1
renameWidth=8
smtCommitPolicy=RoundRobin
smtFetchPolicy=SingleThread
smtIQPolicy=Partitioned
smtIQThreshold=100
smtLSQPolicy=Partitioned
smtLSQThreshold=100
smtNumFetchingThreads=1
smtROBPolicy=Partitioned
smtROBThreshold=100
squashWidth=8
store_set_clear_period=250000
system=system
tracer=system.cpu.tracer
trapLatency=13
wbDepth=1
wbWidth=8
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=262144
subblock_size=0
system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
[system.cpu.dtb]
type=AlphaTLB
size=64
[system.cpu.fuPool]
type=FUPool
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
[system.cpu.fuPool.FUList0]
type=FUDesc
children=opList
count=6
opList=system.cpu.fuPool.FUList0.opList
[system.cpu.fuPool.FUList0.opList]
type=OpDesc
issueLat=1
opClass=IntAlu
opLat=1
[system.cpu.fuPool.FUList1]
type=FUDesc
children=opList0 opList1
count=2
opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
[system.cpu.fuPool.FUList1.opList0]
type=OpDesc
issueLat=1
opClass=IntMult
opLat=3
[system.cpu.fuPool.FUList1.opList1]
type=OpDesc
issueLat=19
opClass=IntDiv
opLat=20
[system.cpu.fuPool.FUList2]
type=FUDesc
children=opList0 opList1 opList2
count=4
opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
[system.cpu.fuPool.FUList2.opList0]
type=OpDesc
issueLat=1
opClass=FloatAdd
opLat=2
[system.cpu.fuPool.FUList2.opList1]
type=OpDesc
issueLat=1
opClass=FloatCmp
opLat=2
[system.cpu.fuPool.FUList2.opList2]
type=OpDesc
issueLat=1
opClass=FloatCvt
opLat=2
[system.cpu.fuPool.FUList3]
type=FUDesc
children=opList0 opList1 opList2
count=2
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
[system.cpu.fuPool.FUList3.opList0]
type=OpDesc
issueLat=1
opClass=FloatMult
opLat=4
[system.cpu.fuPool.FUList3.opList1]
type=OpDesc
issueLat=12
opClass=FloatDiv
opLat=12
[system.cpu.fuPool.FUList3.opList2]
type=OpDesc
issueLat=24
opClass=FloatSqrt
opLat=24
[system.cpu.fuPool.FUList4]
type=FUDesc
children=opList
count=0
opList=system.cpu.fuPool.FUList4.opList
[system.cpu.fuPool.FUList4.opList]
type=OpDesc
issueLat=1
opClass=MemRead
opLat=1
[system.cpu.fuPool.FUList5]
type=FUDesc
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
count=4
opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
[system.cpu.fuPool.FUList5.opList00]
type=OpDesc
issueLat=1
opClass=SimdAdd
opLat=1
[system.cpu.fuPool.FUList5.opList01]
type=OpDesc
issueLat=1
opClass=SimdAddAcc
opLat=1
[system.cpu.fuPool.FUList5.opList02]
type=OpDesc
issueLat=1
opClass=SimdAlu
opLat=1
[system.cpu.fuPool.FUList5.opList03]
type=OpDesc
issueLat=1
opClass=SimdCmp
opLat=1
[system.cpu.fuPool.FUList5.opList04]
type=OpDesc
issueLat=1
opClass=SimdCvt
opLat=1
[system.cpu.fuPool.FUList5.opList05]
type=OpDesc
issueLat=1
opClass=SimdMisc
opLat=1
[system.cpu.fuPool.FUList5.opList06]
type=OpDesc
issueLat=1
opClass=SimdMult
opLat=1
[system.cpu.fuPool.FUList5.opList07]
type=OpDesc
issueLat=1
opClass=SimdMultAcc
opLat=1
[system.cpu.fuPool.FUList5.opList08]
type=OpDesc
issueLat=1
opClass=SimdShift
opLat=1
[system.cpu.fuPool.FUList5.opList09]
type=OpDesc
issueLat=1
opClass=SimdShiftAcc
opLat=1
[system.cpu.fuPool.FUList5.opList10]
type=OpDesc
issueLat=1
opClass=SimdSqrt
opLat=1
[system.cpu.fuPool.FUList5.opList11]
type=OpDesc
issueLat=1
opClass=SimdFloatAdd
opLat=1
[system.cpu.fuPool.FUList5.opList12]
type=OpDesc
issueLat=1
opClass=SimdFloatAlu
opLat=1
[system.cpu.fuPool.FUList5.opList13]
type=OpDesc
issueLat=1
opClass=SimdFloatCmp
opLat=1
[system.cpu.fuPool.FUList5.opList14]
type=OpDesc
issueLat=1
opClass=SimdFloatCvt
opLat=1
[system.cpu.fuPool.FUList5.opList15]
type=OpDesc
issueLat=1
opClass=SimdFloatDiv
opLat=1
[system.cpu.fuPool.FUList5.opList16]
type=OpDesc
issueLat=1
opClass=SimdFloatMisc
opLat=1
[system.cpu.fuPool.FUList5.opList17]
type=OpDesc
issueLat=1
opClass=SimdFloatMult
opLat=1
[system.cpu.fuPool.FUList5.opList18]
type=OpDesc
issueLat=1
opClass=SimdFloatMultAcc
opLat=1
[system.cpu.fuPool.FUList5.opList19]
type=OpDesc
issueLat=1
opClass=SimdFloatSqrt
opLat=1
[system.cpu.fuPool.FUList6]
type=FUDesc
children=opList
count=0
opList=system.cpu.fuPool.FUList6.opList
[system.cpu.fuPool.FUList6.opList]
type=OpDesc
issueLat=1
opClass=MemWrite
opLat=1
[system.cpu.fuPool.FUList7]
type=FUDesc
children=opList0 opList1
count=4
opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
[system.cpu.fuPool.FUList7.opList0]
type=OpDesc
issueLat=1
opClass=MemRead
opLat=1
[system.cpu.fuPool.FUList7.opList1]
type=OpDesc
issueLat=1
opClass=MemWrite
opLat=1
[system.cpu.fuPool.FUList8]
type=FUDesc
children=opList
count=1
opList=system.cpu.fuPool.FUList8.opList
[system.cpu.fuPool.FUList8.opList]
type=OpDesc
issueLat=3
opClass=IprAccess
opLat=3
[system.cpu.icache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=131072
subblock_size=0
system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.interrupts]
type=AlphaInterrupts
[system.cpu.itb]
type=AlphaTLB
size=48
[system.cpu.l2cache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=false
latency=1000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=2097152
subblock_size=0
system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
[system.cpu.toL2Bus]
type=CoherentBus
block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=perlbmk -I. -I lib lgred.makerand.pl
cwd=build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/o3-timing
egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk
gid=100
input=cin
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=0
system=system
uid=100
[system.membus]
type=CoherentBus
block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
master=system.physmem.port[0]
slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=SimpleMemory
conf_table_reported=false
file=
in_addr_map=true
latency=30000
latency_var=0
null=false
range=0:134217727
zero=false
port=system.membus.master[0]

7
simulators/gem5/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simerr Executable file
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warn: Sockets disabled, not accepting gdb connections
warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
warn: ignoring syscall sigprocmask(0, 1, ...)
warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
hack: be nice to actually delete the event here

1388
simulators/gem5/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout Executable file
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File diff suppressed because it is too large Load Diff

693
simulators/gem5/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt Normal file
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---------- Begin Simulation Statistics ----------
sim_seconds 0.645508 # Number of seconds simulated
sim_ticks 645508416000 # Number of ticks simulated
final_tick 645508416000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 137005 # Simulator instruction rate (inst/s)
host_op_rate 137005 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 48511232 # Simulator tick rate (ticks/s)
host_mem_usage 222596 # Number of bytes of host memory used
host_seconds 13306.37 # Real time elapsed on the host
sim_insts 1823043370 # Number of instructions simulated
sim_ops 1823043370 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 192384 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 94602752 # Number of bytes read from this memory
system.physmem.bytes_read::total 94795136 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 192384 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 192384 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 4281472 # Number of bytes written to this memory
system.physmem.bytes_written::total 4281472 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 3006 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 1478168 # Number of read requests responded to by this memory
system.physmem.num_reads::total 1481174 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 66898 # Number of write requests responded to by this memory
system.physmem.num_writes::total 66898 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 298035 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 146555412 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 146853447 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 298035 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 298035 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 6632713 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 6632713 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 6632713 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 298035 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 146555412 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 153486160 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 526109598 # DTB read hits
system.cpu.dtb.read_misses 625347 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 526734945 # DTB read accesses
system.cpu.dtb.write_hits 292167921 # DTB write hits
system.cpu.dtb.write_misses 53946 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 292221867 # DTB write accesses
system.cpu.dtb.data_hits 818277519 # DTB hits
system.cpu.dtb.data_misses 679293 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 818956812 # DTB accesses
system.cpu.itb.fetch_hits 402604817 # ITB hits
system.cpu.itb.fetch_misses 847 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 402605664 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 39 # Number of system calls
system.cpu.numCycles 1291016833 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.BPredUnit.lookups 393573728 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 256530657 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 27586844 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 324820294 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 261991971 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 57786471 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 8197 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 421176645 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 3321335108 # Number of instructions fetch has processed
system.cpu.fetch.Branches 393573728 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 319778442 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 638257970 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 162812665 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 96711303 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 158 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 8593 # Number of stall cycles due to pending traps
system.cpu.fetch.CacheLines 402604817 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 9565592 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 1290891849 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.572900 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.136734 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 652633879 50.56% 50.56% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 59721794 4.63% 55.18% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 43804545 3.39% 58.58% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 72624877 5.63% 64.20% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 127484332 9.88% 74.08% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 46855386 3.63% 77.71% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 41599950 3.22% 80.93% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 7021053 0.54% 81.47% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 239146033 18.53% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 1290891849 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.304856 # Number of branch fetches per cycle
system.cpu.fetch.rate 2.572651 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 453921580 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 79454568 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 612779431 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 10011349 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 134724921 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 33550717 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 12520 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 3227083732 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 46784 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 134724921 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 483920973 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 32457268 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 25980 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 591448832 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 48313875 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 3136668879 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 405 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 8064 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 42516144 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenamedOperands 2086288186 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 3648925200 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 3531562512 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 117362688 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 1384969070 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 701319116 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 4353 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 267 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 142890931 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 736649308 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 360329563 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 68950696 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 9282518 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 2642275746 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 205 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 2193056773 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 17946555 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 819111732 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 708893207 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 166 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 1290891849 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 1.698869 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.804017 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 470876253 36.48% 36.48% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 218068463 16.89% 53.37% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 252707156 19.58% 72.95% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 121463164 9.41% 82.36% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 106308054 8.24% 90.59% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 77452334 6.00% 96.59% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 21076392 1.63% 98.22% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 17287996 1.34% 99.56% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 5652037 0.44% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 1290891849 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 1141130 3.16% 3.16% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 3.16% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 3.16% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.16% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.16% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.16% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 3.16% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.16% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.16% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.16% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.16% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.16% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.16% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.16% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.16% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 3.16% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.16% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 3.16% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.16% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.16% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.16% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.16% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.16% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.16% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.16% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.16% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.16% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.16% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.16% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 24070571 66.71% 69.88% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 10868345 30.12% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 2752 0.00% 0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 1255545244 57.25% 57.25% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 16688 0.00% 57.25% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.25% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 29218260 1.33% 58.58% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 8254696 0.38% 58.96% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 7204651 0.33% 59.29% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 4 0.00% 59.29% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.29% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.29% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.29% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.29% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.29% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.29% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.29% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.29% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.29% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.29% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.29% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.29% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.29% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.29% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.29% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.29% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.29% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.29% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.29% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.29% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.29% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.29% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 589185884 26.87% 86.16% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 303628594 13.84% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 2193056773 # Type of FU issued
system.cpu.iq.rate 1.698705 # Inst issue rate
system.cpu.iq.fu_busy_cnt 36080046 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.016452 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 5576578817 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 3377639693 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 2021595592 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 154453179 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 83821528 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 75359015 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 2150081181 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 79052886 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 67169273 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 225579282 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 22953 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 76359 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 149534667 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 4418 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 31 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 134724921 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 3817892 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 203271 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 3000868514 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 2715875 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 736649308 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 360329563 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 205 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 131040 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 4909 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 76359 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 27588382 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 31906 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 27620288 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 2101232365 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 526735105 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 91824408 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 358592563 # number of nop insts executed
system.cpu.iew.exec_refs 818957488 # number of memory reference insts executed
system.cpu.iew.exec_branches 281208298 # Number of branches executed
system.cpu.iew.exec_stores 292222383 # Number of stores executed
system.cpu.iew.exec_rate 1.627579 # Inst execution rate
system.cpu.iew.wb_sent 2099740429 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 2096954607 # cumulative count of insts written-back
system.cpu.iew.wb_producers 1185148628 # num instructions producing a value
system.cpu.iew.wb_consumers 1754528061 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 1.624266 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.675480 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitCommittedInsts 2008987604 # The number of committed instructions
system.cpu.commit.commitCommittedOps 2008987604 # The number of committed instructions
system.cpu.commit.commitSquashedInsts 975184756 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 39 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 27574586 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 1156166928 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.737628 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.495396 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 540094894 46.71% 46.71% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 227413285 19.67% 66.38% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 119190896 10.31% 76.69% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 56737431 4.91% 81.60% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 50997203 4.41% 86.01% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 24159454 2.09% 88.10% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 18394192 1.59% 89.69% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 15607584 1.35% 91.04% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 103571989 8.96% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 1156166928 # Number of insts commited each cycle
system.cpu.commit.committedInsts 2008987604 # Number of instructions committed
system.cpu.commit.committedOps 2008987604 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 721864922 # Number of memory references committed
system.cpu.commit.loads 511070026 # Number of loads committed
system.cpu.commit.membars 0 # Number of memory barriers committed
system.cpu.commit.branches 266706457 # Number of branches committed
system.cpu.commit.fp_insts 71824891 # Number of committed floating point instructions.
system.cpu.commit.int_insts 1778941351 # Number of committed integer instructions.
system.cpu.commit.function_calls 39955347 # Number of function calls committed.
system.cpu.commit.bw_lim_events 103571989 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 4031130889 # The number of ROB reads
system.cpu.rob.rob_writes 6103072592 # The number of ROB writes
system.cpu.timesIdled 3457 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 124984 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 1823043370 # Number of Instructions Simulated
system.cpu.committedOps 1823043370 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 1823043370 # Number of Instructions Simulated
system.cpu.cpi 0.708166 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.708166 # CPI: Total CPI of All Threads
system.cpu.ipc 1.412099 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.412099 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 2678294251 # number of integer regfile reads
system.cpu.int_regfile_writes 1517633044 # number of integer regfile writes
system.cpu.fp_regfile_reads 81926245 # number of floating regfile reads
system.cpu.fp_regfile_writes 54028832 # number of floating regfile writes
system.cpu.misc_regfile_reads 1 # number of misc regfile reads
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
system.cpu.icache.replacements 8444 # number of replacements
system.cpu.icache.tagsinuse 1673.037469 # Cycle average of tags in use
system.cpu.icache.total_refs 402593289 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 10171 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 39582.468685 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 1673.037469 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.816913 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.816913 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 402593289 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 402593289 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 402593289 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 402593289 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 402593289 # number of overall hits
system.cpu.icache.overall_hits::total 402593289 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 11528 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 11528 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 11528 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 11528 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 11528 # number of overall misses
system.cpu.icache.overall_misses::total 11528 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 191663000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 191663000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 191663000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 191663000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 191663000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 191663000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 402604817 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 402604817 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 402604817 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 402604817 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 402604817 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 402604817 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000029 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000029 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000029 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000029 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000029 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000029 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16625.867453 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 16625.867453 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 16625.867453 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 16625.867453 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 16625.867453 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 16625.867453 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1356 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 1356 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 1356 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 1356 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 1356 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 1356 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 10172 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 10172 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 10172 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 10172 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 10172 # number of overall MSHR misses
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system.cpu.icache.overall_mshr_miss_latency::total 123488000 # number of overall MSHR miss cycles
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system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12139.992135 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12139.992135 # average ReadReq mshr miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12139.992135 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 12139.992135 # average overall mshr miss latency
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34227.205505 # average ReadReq mshr miss latency
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34815.073180 # average WriteReq mshr miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34254.679034 # average overall mshr miss latency
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system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2147444000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 93472000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 45899201500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 45992673500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 93472000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 45899201500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 45992673500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.295517 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.966291 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.961652 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.933607 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.933607 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.295517 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964764 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.960350 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.295517 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964764 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.960350 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31095.143047 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31000.637348 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31000.838210 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 32123.320868 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 32123.320868 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31095.143047 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31051.410597 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31051.499351 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31095.143047 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31051.410597 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31051.499351 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

117
simulators/gem5/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini Normal file
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[root]
type=Root
children=system
full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
boot_osflags=a
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
readfile=
symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.cpu]
type=AtomicSimpleCPU
children=dtb interrupts itb tracer workload
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
fastmem=false
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
phase=0
profile=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
system=system
tracer=system.cpu.tracer
width=1
workload=system.cpu.workload
dcache_port=system.membus.slave[2]
icache_port=system.membus.slave[1]
[system.cpu.dtb]
type=AlphaTLB
size=64
[system.cpu.interrupts]
type=AlphaInterrupts
[system.cpu.itb]
type=AlphaTLB
size=48
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=perlbmk -I. -I lib lgred.makerand.pl
cwd=build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-atomic
egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk
gid=100
input=cin
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=0
system=system
uid=100
[system.membus]
type=CoherentBus
block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
master=system.physmem.port[0]
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
[system.physmem]
type=SimpleMemory
conf_table_reported=false
file=
in_addr_map=true
latency=30000
latency_var=0
null=false
range=0:134217727
zero=false
port=system.membus.master[0]

8
simulators/gem5/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/simerr Executable file
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@ -0,0 +1,8 @@
warn: CoherentBus system.membus has no snooping ports attached!
warn: Sockets disabled, not accepting gdb connections
warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
warn: ignoring syscall sigprocmask(0, 1, ...)
warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
hack: be nice to actually delete the event here

1388
simulators/gem5/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/simout Executable file
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File diff suppressed because it is too large Load Diff

92
simulators/gem5/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt Normal file
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@ -0,0 +1,92 @@
---------- Begin Simulation Statistics ----------
sim_seconds 1.004711 # Number of seconds simulated
sim_ticks 1004710587000 # Number of ticks simulated
final_tick 1004710587000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 3539563 # Simulator instruction rate (inst/s)
host_op_rate 3539563 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1770163280 # Simulator tick rate (ticks/s)
host_mem_usage 211940 # Number of bytes of host memory used
host_seconds 567.58 # Real time elapsed on the host
sim_insts 2008987605 # Number of instructions simulated
sim_ops 2008987605 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 8037684280 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 3569416716 # Number of bytes read from this memory
system.physmem.bytes_read::total 11607100996 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 8037684280 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 8037684280 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 1586125963 # Number of bytes written to this memory
system.physmem.bytes_written::total 1586125963 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 2009421070 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 511070026 # Number of read requests responded to by this memory
system.physmem.num_reads::total 2520491096 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 210794896 # Number of write requests responded to by this memory
system.physmem.num_writes::total 210794896 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 7999999586 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 3552681501 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 11552681087 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 7999999586 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 7999999586 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 1578689409 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 1578689409 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 7999999586 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 5131370910 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 13131370496 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 511070026 # DTB read hits
system.cpu.dtb.read_misses 418884 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 511488910 # DTB read accesses
system.cpu.dtb.write_hits 210794896 # DTB write hits
system.cpu.dtb.write_misses 14581 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 210809477 # DTB write accesses
system.cpu.dtb.data_hits 721864922 # DTB hits
system.cpu.dtb.data_misses 433465 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 722298387 # DTB accesses
system.cpu.itb.fetch_hits 2009421070 # ITB hits
system.cpu.itb.fetch_misses 105 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 2009421175 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 39 # Number of system calls
system.cpu.numCycles 2009421175 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 2008987605 # Number of instructions committed
system.cpu.committedOps 2008987605 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 1779374816 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 71831671 # Number of float alu accesses
system.cpu.num_func_calls 79910682 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 172959296 # number of instructions that are conditional controls
system.cpu.num_int_insts 1779374816 # number of integer instructions
system.cpu.num_fp_insts 71831671 # number of float instructions
system.cpu.num_int_register_reads 2314712013 # number of times the integer registers were read
system.cpu.num_int_register_writes 1332688300 # number of times the integer registers were written
system.cpu.num_fp_register_reads 77066699 # number of times the floating registers were read
system.cpu.num_fp_register_writes 52280770 # number of times the floating registers were written
system.cpu.num_mem_refs 722298387 # number of memory refs
system.cpu.num_load_insts 511488910 # Number of load instructions
system.cpu.num_store_insts 210809477 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 2009421175 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
---------- End Simulation Statistics ----------

198
simulators/gem5/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini Normal file
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[root]
type=Root
children=system
full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
boot_osflags=a
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
readfile=
symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.cpu]
type=TimingSimpleCPU
children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
phase=0
profile=0
progress_interval=0
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=262144
subblock_size=0
system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
[system.cpu.dtb]
type=AlphaTLB
size=64
[system.cpu.icache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=131072
subblock_size=0
system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.interrupts]
type=AlphaInterrupts
[system.cpu.itb]
type=AlphaTLB
size=48
[system.cpu.l2cache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=false
latency=10000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=2097152
subblock_size=0
system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
[system.cpu.toL2Bus]
type=CoherentBus
block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=perlbmk -I. -I lib lgred.makerand.pl
cwd=build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-timing
egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk
gid=100
input=cin
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=0
system=system
uid=100
[system.membus]
type=CoherentBus
block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
master=system.physmem.port[0]
slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=SimpleMemory
conf_table_reported=false
file=
in_addr_map=true
latency=30000
latency_var=0
null=false
range=0:134217727
zero=false
port=system.membus.master[0]

7
simulators/gem5/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/simerr Executable file
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@ -0,0 +1,7 @@
warn: Sockets disabled, not accepting gdb connections
warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
warn: ignoring syscall sigprocmask(0, 1, ...)
warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
hack: be nice to actually delete the event here

1388
simulators/gem5/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/simout Executable file
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File diff suppressed because it is too large Load Diff

409
simulators/gem5/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt Normal file
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@ -0,0 +1,409 @@
---------- Begin Simulation Statistics ----------
sim_seconds 2.813468 # Number of seconds simulated
sim_ticks 2813467842000 # Number of ticks simulated
final_tick 2813467842000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1483350 # Simulator instruction rate (inst/s)
host_op_rate 1483350 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 2077343480 # Simulator tick rate (ticks/s)
host_mem_usage 220820 # Number of bytes of host memory used
host_seconds 1354.36 # Real time elapsed on the host
sim_insts 2008987605 # Number of instructions simulated
sim_ops 2008987605 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 152128 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 94556032 # Number of bytes read from this memory
system.physmem.bytes_read::total 94708160 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 152128 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 152128 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 4281472 # Number of bytes written to this memory
system.physmem.bytes_written::total 4281472 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 2377 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 1477438 # Number of read requests responded to by this memory
system.physmem.num_reads::total 1479815 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 66898 # Number of write requests responded to by this memory
system.physmem.num_writes::total 66898 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 54071 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 33608357 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 33662428 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 54071 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 54071 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 1521777 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 1521777 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 1521777 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 54071 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 33608357 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 35184206 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 511070026 # DTB read hits
system.cpu.dtb.read_misses 418884 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 511488910 # DTB read accesses
system.cpu.dtb.write_hits 210794896 # DTB write hits
system.cpu.dtb.write_misses 14581 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 210809477 # DTB write accesses
system.cpu.dtb.data_hits 721864922 # DTB hits
system.cpu.dtb.data_misses 433465 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 722298387 # DTB accesses
system.cpu.itb.fetch_hits 2009421071 # ITB hits
system.cpu.itb.fetch_misses 105 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 2009421176 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 39 # Number of system calls
system.cpu.numCycles 5626935684 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 2008987605 # Number of instructions committed
system.cpu.committedOps 2008987605 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 1779374816 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 71831671 # Number of float alu accesses
system.cpu.num_func_calls 79910682 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 172959296 # number of instructions that are conditional controls
system.cpu.num_int_insts 1779374816 # number of integer instructions
system.cpu.num_fp_insts 71831671 # number of float instructions
system.cpu.num_int_register_reads 2314712013 # number of times the integer registers were read
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system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks 66898 # number of writebacks
system.cpu.l2cache.writebacks::total 66898 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2377 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1410565 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 1412942 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66873 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 66873 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 2377 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 1477438 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 1479815 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2377 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 1477438 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 1479815 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 95080000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 56422600000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 56517680000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2674920000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2674920000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 95080000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 59097520000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 59192600000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 95080000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 59097520000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 59192600000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.224330 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.967338 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.961978 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.929411 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.929411 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.224330 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.965555 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.960457 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.224330 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.965555 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.960457 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

547
simulators/gem5/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini Normal file
View File

@ -0,0 +1,547 @@
[root]
type=Root
children=system
full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
boot_osflags=a
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
readfile=
symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.cpu]
type=DerivO3CPU
children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
LSQDepCheckShift=4
RASSize=16
SQEntries=32
SSITSize=1024
activity=0
backComSize=5
cachePorts=200
checker=Null
choiceCtrBits=2
choicePredictorSize=8192
clock=500
commitToDecodeDelay=1
commitToFetchDelay=1
commitToIEWDelay=1
commitToRenameDelay=1
commitWidth=8
cpu_id=0
decodeToFetchDelay=1
decodeToRenameDelay=1
decodeWidth=8
defer_registration=false
dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
fetchToDecodeDelay=1
fetchTrapLatency=1
fetchWidth=8
forwardComSize=5
fuPool=system.cpu.fuPool
function_trace=false
function_trace_start=0
globalCtrBits=2
globalHistoryBits=13
globalPredictorSize=8192
iewToCommitDelay=1
iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
instShiftAmt=2
interrupts=system.cpu.interrupts
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
localCtrBits=2
localHistoryBits=11
localHistoryTableSize=2048
localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
needsTSO=false
numIQEntries=64
numPhysFloatRegs=256
numPhysIntRegs=256
numROBEntries=192
numRobs=1
numThreads=1
phase=0
predType=tournament
profile=0
progress_interval=0
renameToDecodeDelay=1
renameToFetchDelay=1
renameToIEWDelay=2
renameToROBDelay=1
renameWidth=8
smtCommitPolicy=RoundRobin
smtFetchPolicy=SingleThread
smtIQPolicy=Partitioned
smtIQThreshold=100
smtLSQPolicy=Partitioned
smtLSQThreshold=100
smtNumFetchingThreads=1
smtROBPolicy=Partitioned
smtROBThreshold=100
squashWidth=8
store_set_clear_period=250000
system=system
tracer=system.cpu.tracer
trapLatency=13
wbDepth=1
wbWidth=8
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=262144
subblock_size=0
system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
[system.cpu.dtb]
type=ArmTLB
children=walker
size=64
walker=system.cpu.dtb.walker
[system.cpu.dtb.walker]
type=ArmTableWalker
max_backoff=100000
min_backoff=0
sys=system
port=system.cpu.toL2Bus.slave[3]
[system.cpu.fuPool]
type=FUPool
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
[system.cpu.fuPool.FUList0]
type=FUDesc
children=opList
count=6
opList=system.cpu.fuPool.FUList0.opList
[system.cpu.fuPool.FUList0.opList]
type=OpDesc
issueLat=1
opClass=IntAlu
opLat=1
[system.cpu.fuPool.FUList1]
type=FUDesc
children=opList0 opList1
count=2
opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
[system.cpu.fuPool.FUList1.opList0]
type=OpDesc
issueLat=1
opClass=IntMult
opLat=3
[system.cpu.fuPool.FUList1.opList1]
type=OpDesc
issueLat=19
opClass=IntDiv
opLat=20
[system.cpu.fuPool.FUList2]
type=FUDesc
children=opList0 opList1 opList2
count=4
opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
[system.cpu.fuPool.FUList2.opList0]
type=OpDesc
issueLat=1
opClass=FloatAdd
opLat=2
[system.cpu.fuPool.FUList2.opList1]
type=OpDesc
issueLat=1
opClass=FloatCmp
opLat=2
[system.cpu.fuPool.FUList2.opList2]
type=OpDesc
issueLat=1
opClass=FloatCvt
opLat=2
[system.cpu.fuPool.FUList3]
type=FUDesc
children=opList0 opList1 opList2
count=2
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
[system.cpu.fuPool.FUList3.opList0]
type=OpDesc
issueLat=1
opClass=FloatMult
opLat=4
[system.cpu.fuPool.FUList3.opList1]
type=OpDesc
issueLat=12
opClass=FloatDiv
opLat=12
[system.cpu.fuPool.FUList3.opList2]
type=OpDesc
issueLat=24
opClass=FloatSqrt
opLat=24
[system.cpu.fuPool.FUList4]
type=FUDesc
children=opList
count=0
opList=system.cpu.fuPool.FUList4.opList
[system.cpu.fuPool.FUList4.opList]
type=OpDesc
issueLat=1
opClass=MemRead
opLat=1
[system.cpu.fuPool.FUList5]
type=FUDesc
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
count=4
opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
[system.cpu.fuPool.FUList5.opList00]
type=OpDesc
issueLat=1
opClass=SimdAdd
opLat=1
[system.cpu.fuPool.FUList5.opList01]
type=OpDesc
issueLat=1
opClass=SimdAddAcc
opLat=1
[system.cpu.fuPool.FUList5.opList02]
type=OpDesc
issueLat=1
opClass=SimdAlu
opLat=1
[system.cpu.fuPool.FUList5.opList03]
type=OpDesc
issueLat=1
opClass=SimdCmp
opLat=1
[system.cpu.fuPool.FUList5.opList04]
type=OpDesc
issueLat=1
opClass=SimdCvt
opLat=1
[system.cpu.fuPool.FUList5.opList05]
type=OpDesc
issueLat=1
opClass=SimdMisc
opLat=1
[system.cpu.fuPool.FUList5.opList06]
type=OpDesc
issueLat=1
opClass=SimdMult
opLat=1
[system.cpu.fuPool.FUList5.opList07]
type=OpDesc
issueLat=1
opClass=SimdMultAcc
opLat=1
[system.cpu.fuPool.FUList5.opList08]
type=OpDesc
issueLat=1
opClass=SimdShift
opLat=1
[system.cpu.fuPool.FUList5.opList09]
type=OpDesc
issueLat=1
opClass=SimdShiftAcc
opLat=1
[system.cpu.fuPool.FUList5.opList10]
type=OpDesc
issueLat=1
opClass=SimdSqrt
opLat=1
[system.cpu.fuPool.FUList5.opList11]
type=OpDesc
issueLat=1
opClass=SimdFloatAdd
opLat=1
[system.cpu.fuPool.FUList5.opList12]
type=OpDesc
issueLat=1
opClass=SimdFloatAlu
opLat=1
[system.cpu.fuPool.FUList5.opList13]
type=OpDesc
issueLat=1
opClass=SimdFloatCmp
opLat=1
[system.cpu.fuPool.FUList5.opList14]
type=OpDesc
issueLat=1
opClass=SimdFloatCvt
opLat=1
[system.cpu.fuPool.FUList5.opList15]
type=OpDesc
issueLat=1
opClass=SimdFloatDiv
opLat=1
[system.cpu.fuPool.FUList5.opList16]
type=OpDesc
issueLat=1
opClass=SimdFloatMisc
opLat=1
[system.cpu.fuPool.FUList5.opList17]
type=OpDesc
issueLat=1
opClass=SimdFloatMult
opLat=1
[system.cpu.fuPool.FUList5.opList18]
type=OpDesc
issueLat=1
opClass=SimdFloatMultAcc
opLat=1
[system.cpu.fuPool.FUList5.opList19]
type=OpDesc
issueLat=1
opClass=SimdFloatSqrt
opLat=1
[system.cpu.fuPool.FUList6]
type=FUDesc
children=opList
count=0
opList=system.cpu.fuPool.FUList6.opList
[system.cpu.fuPool.FUList6.opList]
type=OpDesc
issueLat=1
opClass=MemWrite
opLat=1
[system.cpu.fuPool.FUList7]
type=FUDesc
children=opList0 opList1
count=4
opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
[system.cpu.fuPool.FUList7.opList0]
type=OpDesc
issueLat=1
opClass=MemRead
opLat=1
[system.cpu.fuPool.FUList7.opList1]
type=OpDesc
issueLat=1
opClass=MemWrite
opLat=1
[system.cpu.fuPool.FUList8]
type=FUDesc
children=opList
count=1
opList=system.cpu.fuPool.FUList8.opList
[system.cpu.fuPool.FUList8.opList]
type=OpDesc
issueLat=3
opClass=IprAccess
opLat=3
[system.cpu.icache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=131072
subblock_size=0
system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.interrupts]
type=ArmInterrupts
[system.cpu.itb]
type=ArmTLB
children=walker
size=64
walker=system.cpu.itb.walker
[system.cpu.itb.walker]
type=ArmTableWalker
max_backoff=100000
min_backoff=0
sys=system
port=system.cpu.toL2Bus.slave[2]
[system.cpu.l2cache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=false
latency=1000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=2097152
subblock_size=0
system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
[system.cpu.toL2Bus]
type=CoherentBus
block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=perlbmk -I. -I lib lgred.makerand.pl
cwd=build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing
egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/cpu2000/binaries/arm/linux/perlbmk
gid=100
input=cin
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=0
system=system
uid=100
[system.membus]
type=CoherentBus
block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
master=system.physmem.port[0]
slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=SimpleMemory
conf_table_reported=false
file=
in_addr_map=true
latency=30000
latency_var=0
null=false
range=0:134217727
zero=false
port=system.membus.master[0]

3
simulators/gem5/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simerr Executable file
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@ -0,0 +1,3 @@
warn: Sockets disabled, not accepting gdb connections
warn: fcntl64(3, 2) passed through to host
hack: be nice to actually delete the event here

1388
simulators/gem5/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout Executable file
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File diff suppressed because it is too large Load Diff

725
simulators/gem5/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt Normal file
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@ -0,0 +1,725 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.735495 # Number of seconds simulated
sim_ticks 735495062500 # Number of ticks simulated
final_tick 735495062500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 76677 # Simulator instruction rate (inst/s)
host_op_rate 104424 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 40737062 # Simulator tick rate (ticks/s)
host_mem_usage 237976 # Number of bytes of host memory used
host_seconds 18054.69 # Real time elapsed on the host
sim_insts 1384379503 # Number of instructions simulated
sim_ops 1885334256 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 213952 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 94625728 # Number of bytes read from this memory
system.physmem.bytes_read::total 94839680 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 213952 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 213952 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 4230336 # Number of bytes written to this memory
system.physmem.bytes_written::total 4230336 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 3343 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 1478527 # Number of read requests responded to by this memory
system.physmem.num_reads::total 1481870 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 66099 # Number of write requests responded to by this memory
system.physmem.num_writes::total 66099 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 290895 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 128655830 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 128946726 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 290895 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 290895 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 5751685 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 5751685 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 5751685 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 290895 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 128655830 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 134698411 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 1411 # Number of system calls
system.cpu.numCycles 1470990126 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.BPredUnit.lookups 524657246 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 401089358 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 35661760 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 339540356 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 278948773 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 59722038 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 2842670 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 444619593 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 2613573524 # Number of instructions fetch has processed
system.cpu.fetch.Branches 524657246 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 338670811 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 712273911 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 223851331 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 98512911 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 2271 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 29657 # Number of stall cycles due to pending traps
system.cpu.fetch.CacheLines 414743940 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 11577936 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 1438039773 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.556437 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.167543 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 725823899 50.47% 50.47% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 56807029 3.95% 54.42% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 112550044 7.83% 62.25% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 69779758 4.85% 67.10% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 84813159 5.90% 73.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 53785792 3.74% 76.74% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 34099274 2.37% 79.11% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 30811930 2.14% 81.25% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 269568888 18.75% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 1438039773 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.356669 # Number of branch fetches per cycle
system.cpu.fetch.rate 1.776744 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 492128614 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 78582078 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 673411779 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 11338206 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 182579096 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 79653725 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 23825 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 3539524175 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 54394 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 182579096 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 529782652 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 30198632 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 660985 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 645094382 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 49724026 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 3431194053 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 133 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 4188042 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 40587721 # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents 1707 # Number of times there has been no free registers
system.cpu.rename.RenamedOperands 3342681891 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 16249059655 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 15604311677 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 644747978 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 1993154351 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 1349527540 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 64268 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 59597 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 138053548 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 1061160981 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 575711799 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 34121400 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 39206197 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 3192585936 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 69047 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 2718019401 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 27726721 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 1306902480 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 3048220381 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 45882 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 1438039773 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 1.890086 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.916332 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 521512118 36.27% 36.27% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 198246164 13.79% 50.05% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 216916723 15.08% 65.14% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 178677193 12.43% 77.56% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 155355732 10.80% 88.36% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 100852221 7.01% 95.38% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 48369591 3.36% 98.74% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 10873615 0.76% 99.50% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 7236416 0.50% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 1438039773 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 1743579 1.83% 1.83% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 23896 0.03% 1.85% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 1.85% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.85% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.85% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.85% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 1.85% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.85% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.85% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.85% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.85% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.85% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.85% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.85% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.85% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 1.85% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.85% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 1.85% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.85% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.85% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.85% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.85% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.85% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.85% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.85% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.85% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.85% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.85% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.85% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 56969230 59.63% 61.48% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 36797024 38.52% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 1258053988 46.29% 46.29% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 11231448 0.41% 46.70% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 46.70% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 1 0.00% 46.70% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 46.70% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 46.70% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 46.70% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 46.70% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 46.70% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 46.70% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 46.70% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 46.70% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 46.70% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 46.70% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 46.70% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 46.70% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 46.70% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 46.70% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 46.70% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 46.70% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.05% 46.75% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 46.75% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 6876560 0.25% 47.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 5503486 0.20% 47.20% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 73 0.00% 47.20% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 23204970 0.85% 48.06% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 48.06% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.06% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.06% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 902246151 33.19% 81.25% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 509527435 18.75% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 2718019401 # Type of FU issued
system.cpu.iq.rate 1.847748 # Inst issue rate
system.cpu.iq.fu_busy_cnt 95533729 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.035148 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 6864166409 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 4398397135 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 2490268759 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 133172616 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 101224152 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 59789124 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 2745104459 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 68448671 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 72240187 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 429772018 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 278201 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 1347099 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 298714721 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 14 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 26 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 182579096 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 16373982 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 1591067 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 3192732241 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 7809183 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 1061160981 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 575711799 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 58058 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 1589162 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 317 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 1347099 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 36984086 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 8972300 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 45956386 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 2617990910 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 846641153 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 100028491 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 77258 # number of nop insts executed
system.cpu.iew.exec_refs 1326395495 # number of memory reference insts executed
system.cpu.iew.exec_branches 359930496 # Number of branches executed
system.cpu.iew.exec_stores 479754342 # Number of stores executed
system.cpu.iew.exec_rate 1.779747 # Inst execution rate
system.cpu.iew.wb_sent 2578580051 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 2550057883 # cumulative count of insts written-back
system.cpu.iew.wb_producers 1472840060 # num instructions producing a value
system.cpu.iew.wb_consumers 2760220207 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 1.733566 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.533595 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitCommittedInsts 1384390519 # The number of committed instructions
system.cpu.commit.commitCommittedOps 1885345272 # The number of committed instructions
system.cpu.commit.commitSquashedInsts 1307387427 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 23165 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 41179561 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 1255460679 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.501716 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.213055 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 576199063 45.90% 45.90% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 316668907 25.22% 71.12% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 101245126 8.06% 79.18% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 79298067 6.32% 85.50% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 52885974 4.21% 89.71% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 24348674 1.94% 91.65% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 17176683 1.37% 93.02% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 9160932 0.73% 93.75% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 78477253 6.25% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 1255460679 # Number of insts commited each cycle
system.cpu.commit.committedInsts 1384390519 # Number of instructions committed
system.cpu.commit.committedOps 1885345272 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 908386041 # Number of memory references committed
system.cpu.commit.loads 631388963 # Number of loads committed
system.cpu.commit.membars 9986 # Number of memory barriers committed
system.cpu.commit.branches 291350326 # Number of branches committed
system.cpu.commit.fp_insts 52289415 # Number of committed floating point instructions.
system.cpu.commit.int_insts 1653705999 # Number of committed integer instructions.
system.cpu.commit.function_calls 41577833 # Number of function calls committed.
system.cpu.commit.bw_lim_events 78477253 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 4369697780 # The number of ROB reads
system.cpu.rob.rob_writes 6568059146 # The number of ROB writes
system.cpu.timesIdled 1341236 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 32950353 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 1384379503 # Number of Instructions Simulated
system.cpu.committedOps 1885334256 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 1384379503 # Number of Instructions Simulated
system.cpu.cpi 1.062563 # CPI: Cycles Per Instruction
system.cpu.cpi_total 1.062563 # CPI: Total CPI of All Threads
system.cpu.ipc 0.941121 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.941121 # IPC: Total IPC of All Threads
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system.cpu.int_regfile_writes 2421503464 # number of integer regfile writes
system.cpu.fp_regfile_reads 71102089 # number of floating regfile reads
system.cpu.fp_regfile_writes 50855882 # number of floating regfile writes
system.cpu.misc_regfile_reads 4088825153 # number of misc regfile reads
system.cpu.misc_regfile_writes 13776464 # number of misc regfile writes
system.cpu.icache.replacements 29072 # number of replacements
system.cpu.icache.tagsinuse 1666.420003 # Cycle average of tags in use
system.cpu.icache.total_refs 414707358 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 30775 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 13475.462486 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 1666.420003 # Average occupied blocks per requestor
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system.cpu.icache.ReadReq_hits::total 414707364 # number of ReadReq hits
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system.cpu.icache.demand_hits::total 414707364 # number of demand (read+write) hits
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system.cpu.icache.overall_hits::total 414707364 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 36576 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 36576 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 36576 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 36576 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 36576 # number of overall misses
system.cpu.icache.overall_misses::total 36576 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 322136500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 322136500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 322136500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 322136500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 322136500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 322136500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 414743940 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 414743940 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 414743940 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 414743940 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 414743940 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 414743940 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000088 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000088 # miss rate for ReadReq accesses
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system.cpu.icache.overall_miss_rate::cpu.inst 0.000088 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000088 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8807.319007 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 8807.319007 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 8807.319007 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 8807.319007 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 8807.319007 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 8807.319007 # average overall miss latency
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system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.cpu.icache.overall_mshr_hits::cpu.inst 853 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 853 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 35723 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 35723 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 35723 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 35723 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 35723 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 35723 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 192601000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 192601000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 192601000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 192601000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 192601000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 192601000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000086 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000086 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000086 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000086 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000086 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000086 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 5391.512471 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 5391.512471 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 5391.512471 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 5391.512471 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 5391.512471 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 5391.512471 # average overall mshr miss latency
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system.cpu.dcache.total_refs 1032974400 # Total number of references to valid blocks.
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system.cpu.dcache.warmup_cycle 290267000 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.LoadLockedReq_hits::cpu.data 13150 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 13150 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 11766 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 11766 # number of StoreCondReq hits
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system.cpu.dcache.overall_hits::total 1032932504 # number of overall hits
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system.cpu.dcache.WriteReq_misses::cpu.data 821102 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 821102 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses
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system.cpu.dcache.demand_misses::total 3189668 # number of demand (read+write) misses
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system.cpu.dcache.overall_misses::total 3189668 # number of overall misses
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system.cpu.dcache.ReadReq_miss_latency::total 80139479500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 28569168500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 28569168500 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 114500 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 114500 # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 108708648000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 108708648000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 108708648000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 108708648000 # number of overall miss cycles
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system.cpu.dcache.ReadReq_accesses::total 759186494 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_accesses::total 276935678 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13153 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 13153 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 11766 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 11766 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 1036122172 # number of demand (read+write) accesses
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system.cpu.dcache.overall_accesses::total 1036122172 # number of overall (read+write) accesses
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system.cpu.dcache.ReadReq_miss_rate::total 0.003120 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002965 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.002965 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000228 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000228 # miss rate for LoadLockedReq accesses
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system.cpu.dcache.overall_miss_rate::cpu.data 0.003078 # miss rate for overall accesses
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system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33834.598445 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 33834.598445 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34793.690065 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 34793.690065 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 38166.666667 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 38166.666667 # average LoadLockedReq miss latency
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system.cpu.dcache.demand_avg_miss_latency::total 34081.493121 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 34081.493121 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 34081.493121 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 81500 # number of cycles access was blocked
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system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 20375 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
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system.cpu.dcache.writebacks::total 106560 # number of writebacks
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system.cpu.dcache.ReadReq_mshr_hits::total 904767 # number of ReadReq MSHR hits
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system.cpu.dcache.WriteReq_mshr_hits::total 743443 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits
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system.cpu.dcache.demand_mshr_hits::total 1648210 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 1648210 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 1648210 # number of overall MSHR hits
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system.cpu.dcache.WriteReq_mshr_misses::total 77659 # number of WriteReq MSHR misses
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system.cpu.dcache.demand_mshr_misses::total 1541458 # number of demand (read+write) MSHR misses
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system.cpu.dcache.overall_mshr_misses::total 1541458 # number of overall MSHR misses
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system.cpu.dcache.ReadReq_mshr_miss_latency::total 50029877000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2502958500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 2502958500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 52532835500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 52532835500 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_latency::total 52532835500 # number of overall MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001928 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000280 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000280 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001488 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.001488 # mshr miss rate for demand accesses
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34178.105737 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34178.105737 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32230.114990 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32230.114990 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34079.965526 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 34079.965526 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34079.965526 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 34079.965526 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 1480284 # number of replacements
system.cpu.l2cache.tagsinuse 31973.508020 # Cycle average of tags in use
system.cpu.l2cache.total_refs 87070 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 1513005 # Sample count of references to valid blocks.
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system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 2965.813236 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 61.172380 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 28946.522403 # Average occupied blocks per requestor
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system.cpu.l2cache.ReadReq_hits::cpu.data 51328 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 78756 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 106560 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 106560 # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data 3 # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total 3 # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 6632 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 6632 # number of ReadExReq hits
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system.cpu.l2cache.demand_hits::total 85388 # number of demand (read+write) hits
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system.cpu.l2cache.overall_hits::total 85388 # number of overall hits
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system.cpu.l2cache.ReadReq_misses::cpu.data 1412471 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 1415819 # number of ReadReq misses
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system.cpu.l2cache.UpgradeReq_misses::total 4944 # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 66080 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 66080 # number of ReadExReq misses
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system.cpu.l2cache.demand_misses::total 1481899 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 3348 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 1478551 # number of overall misses
system.cpu.l2cache.overall_misses::total 1481899 # number of overall misses
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system.cpu.l2cache.overall_miss_latency::cpu.data 50708648500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 50823414500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 30776 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 1463799 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 1494575 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 106560 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 106560 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 4947 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total 4947 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 72712 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 72712 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 30776 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 1536511 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 1567287 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 30776 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 1536511 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 1567287 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.108786 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.964935 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.947305 # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.999394 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.999394 # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.908791 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.908791 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.108786 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.962278 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.945519 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.108786 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.962278 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.945519 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34278.972521 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34306.089470 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 34306.025346 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34084.322034 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34084.322034 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34278.972521 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34296.178150 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 34296.139278 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34278.972521 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34296.178150 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 34296.139278 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks 66099 # number of writebacks
system.cpu.l2cache.writebacks::total 66099 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 5 # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 24 # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total 29 # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst 5 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data 24 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total 29 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst 5 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data 24 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total 29 # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3343 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1412447 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 1415790 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 4944 # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total 4944 # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66080 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 66080 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 3343 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 1478527 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 1481870 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3343 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 1478527 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 1481870 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 103877000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 43883033500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 43986910500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 153264000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 153264000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2048525000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2048525000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 103877000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 45931558500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 46035435500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 103877000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 45931558500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 46035435500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.108624 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.964919 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.947286 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.999394 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.999394 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.908791 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.908791 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.108624 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.962263 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.945500 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.108624 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.962263 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.945500 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31072.988334 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31068.800104 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31068.809993 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31000 # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31000.680993 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31000.680993 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31072.988334 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31065.755647 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31065.771964 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31072.988334 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31065.755647 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31065.771964 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

135
simulators/gem5/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/config.ini Normal file
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@ -0,0 +1,135 @@
[root]
type=Root
children=system
full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
boot_osflags=a
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
readfile=
symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.cpu]
type=AtomicSimpleCPU
children=dtb interrupts itb tracer workload
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
fastmem=false
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
phase=0
profile=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
system=system
tracer=system.cpu.tracer
width=1
workload=system.cpu.workload
dcache_port=system.membus.slave[2]
icache_port=system.membus.slave[1]
[system.cpu.dtb]
type=ArmTLB
children=walker
size=64
walker=system.cpu.dtb.walker
[system.cpu.dtb.walker]
type=ArmTableWalker
max_backoff=100000
min_backoff=0
sys=system
port=system.membus.slave[4]
[system.cpu.interrupts]
type=ArmInterrupts
[system.cpu.itb]
type=ArmTLB
children=walker
size=64
walker=system.cpu.itb.walker
[system.cpu.itb.walker]
type=ArmTableWalker
max_backoff=100000
min_backoff=0
sys=system
port=system.membus.slave[3]
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=perlbmk -I. -I lib lgred.makerand.pl
cwd=build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-atomic
egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/cpu2000/binaries/arm/linux/perlbmk
gid=100
input=cin
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=0
system=system
uid=100
[system.membus]
type=CoherentBus
block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
master=system.physmem.port[0]
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port
[system.physmem]
type=SimpleMemory
conf_table_reported=false
file=
in_addr_map=true
latency=30000
latency_var=0
null=false
range=0:134217727
zero=false
port=system.membus.master[0]

3
simulators/gem5/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simerr Executable file
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@ -0,0 +1,3 @@
warn: Sockets disabled, not accepting gdb connections
warn: fcntl64(3, 2) passed through to host
hack: be nice to actually delete the event here

1388
simulators/gem5/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simout Executable file
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File diff suppressed because it is too large Load Diff

102
simulators/gem5/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt Normal file
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@ -0,0 +1,102 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.945613 # Number of seconds simulated
sim_ticks 945613131000 # Number of ticks simulated
final_tick 945613131000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1814541 # Simulator instruction rate (inst/s)
host_op_rate 2471154 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1239437075 # Simulator tick rate (ticks/s)
host_mem_usage 226248 # Number of bytes of host memory used
host_seconds 762.94 # Real time elapsed on the host
sim_insts 1384381614 # Number of instructions simulated
sim_ops 1885336367 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 5561086040 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 2464405275 # Number of bytes read from this memory
system.physmem.bytes_read::total 8025491315 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 5561086040 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 5561086040 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 1123958396 # Number of bytes written to this memory
system.physmem.bytes_written::total 1123958396 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 1390271510 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 620345399 # Number of read requests responded to by this memory
system.physmem.num_reads::total 2010616909 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 276945663 # Number of write requests responded to by this memory
system.physmem.num_writes::total 276945663 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 5880931491 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 2606145361 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 8487076852 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 5880931491 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 5880931491 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 1188602780 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 1188602780 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 5880931491 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 3794748141 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 9675679632 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 1411 # Number of system calls
system.cpu.numCycles 1891226263 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 1384381614 # Number of instructions committed
system.cpu.committedOps 1885336367 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 1653698876 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 52289415 # Number of float alu accesses
system.cpu.num_func_calls 80344203 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 223735906 # number of instructions that are conditional controls
system.cpu.num_int_insts 1653698876 # number of integer instructions
system.cpu.num_fp_insts 52289415 # number of float instructions
system.cpu.num_int_register_reads 8601515950 # number of times the integer registers were read
system.cpu.num_int_register_writes 1874331406 # number of times the integer registers were written
system.cpu.num_fp_register_reads 60540850 # number of times the floating registers were read
system.cpu.num_fp_register_writes 46777010 # number of times the floating registers were written
system.cpu.num_mem_refs 908382480 # number of memory refs
system.cpu.num_load_insts 631387182 # Number of load instructions
system.cpu.num_store_insts 276995298 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 1891226263 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
---------- End Simulation Statistics ----------

216
simulators/gem5/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini Normal file
View File

@ -0,0 +1,216 @@
[root]
type=Root
children=system
full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
boot_osflags=a
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
readfile=
symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.cpu]
type=TimingSimpleCPU
children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
phase=0
profile=0
progress_interval=0
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=262144
subblock_size=0
system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
[system.cpu.dtb]
type=ArmTLB
children=walker
size=64
walker=system.cpu.dtb.walker
[system.cpu.dtb.walker]
type=ArmTableWalker
max_backoff=100000
min_backoff=0
sys=system
port=system.cpu.toL2Bus.slave[3]
[system.cpu.icache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=131072
subblock_size=0
system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.interrupts]
type=ArmInterrupts
[system.cpu.itb]
type=ArmTLB
children=walker
size=64
walker=system.cpu.itb.walker
[system.cpu.itb.walker]
type=ArmTableWalker
max_backoff=100000
min_backoff=0
sys=system
port=system.cpu.toL2Bus.slave[2]
[system.cpu.l2cache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=false
latency=10000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=2097152
subblock_size=0
system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
[system.cpu.toL2Bus]
type=CoherentBus
block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=perlbmk -I. -I lib lgred.makerand.pl
cwd=build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-timing
egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/cpu2000/binaries/arm/linux/perlbmk
gid=100
input=cin
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=0
system=system
uid=100
[system.membus]
type=CoherentBus
block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
master=system.physmem.port[0]
slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=SimpleMemory
conf_table_reported=false
file=
in_addr_map=true
latency=30000
latency_var=0
null=false
range=0:134217727
zero=false
port=system.membus.master[0]

3
simulators/gem5/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simerr Executable file
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@ -0,0 +1,3 @@
warn: Sockets disabled, not accepting gdb connections
warn: fcntl64(3, 2) passed through to host
hack: be nice to actually delete the event here

1388
simulators/gem5/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simout Executable file
View File

File diff suppressed because it is too large Load Diff

427
simulators/gem5/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt Normal file
View File

@ -0,0 +1,427 @@
---------- Begin Simulation Statistics ----------
sim_seconds 2.369902 # Number of seconds simulated
sim_ticks 2369901960000 # Number of ticks simulated
final_tick 2369901960000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 768078 # Simulator instruction rate (inst/s)
host_op_rate 1041952 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1317503901 # Simulator tick rate (ticks/s)
host_mem_usage 235416 # Number of bytes of host memory used
host_seconds 1798.78 # Real time elapsed on the host
sim_insts 1381604347 # Number of instructions simulated
sim_ops 1874244950 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 144448 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 94551872 # Number of bytes read from this memory
system.physmem.bytes_read::total 94696320 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 144448 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 144448 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 4230336 # Number of bytes written to this memory
system.physmem.bytes_written::total 4230336 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 2257 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 1477373 # Number of read requests responded to by this memory
system.physmem.num_reads::total 1479630 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 66099 # Number of write requests responded to by this memory
system.physmem.num_writes::total 66099 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 60951 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 39896955 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 39957906 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 60951 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 60951 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 1785026 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 1785026 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 1785026 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 60951 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 39896955 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 41742932 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 1411 # Number of system calls
system.cpu.numCycles 4739803920 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 1381604347 # Number of instructions committed
system.cpu.committedOps 1874244950 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 1653698876 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 52289415 # Number of float alu accesses
system.cpu.num_func_calls 80344203 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 223735906 # number of instructions that are conditional controls
system.cpu.num_int_insts 1653698876 # number of integer instructions
system.cpu.num_fp_insts 52289415 # number of float instructions
system.cpu.num_int_register_reads 10466679954 # number of times the integer registers were read
system.cpu.num_int_register_writes 1874331406 # number of times the integer registers were written
system.cpu.num_fp_register_reads 60540850 # number of times the floating registers were read
system.cpu.num_fp_register_writes 46777010 # number of times the floating registers were written
system.cpu.num_mem_refs 908382480 # number of memory refs
system.cpu.num_load_insts 631387182 # Number of load instructions
system.cpu.num_store_insts 276995298 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 4739803920 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.icache.replacements 18364 # number of replacements
system.cpu.icache.tagsinuse 1392.324437 # Cycle average of tags in use
system.cpu.icache.total_refs 1390251708 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 19803 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 70204.095743 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 1392.324437 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.679846 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.679846 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 1390251708 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 1390251708 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 1390251708 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 1390251708 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 1390251708 # number of overall hits
system.cpu.icache.overall_hits::total 1390251708 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 19803 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 19803 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 19803 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 19803 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 19803 # number of overall misses
system.cpu.icache.overall_misses::total 19803 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 372036000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 372036000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 372036000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 372036000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 372036000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 372036000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 1390271511 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 1390271511 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 1390271511 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 1390271511 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 1390271511 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 1390271511 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000014 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000014 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000014 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000014 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000014 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000014 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18786.850477 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 18786.850477 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 18786.850477 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 18786.850477 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 18786.850477 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 18786.850477 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 19803 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 19803 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 19803 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 19803 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 19803 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 19803 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 312627000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 312627000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 312627000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 312627000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 312627000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 312627000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000014 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000014 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000014 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000014 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000014 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000014 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15786.850477 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15786.850477 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15786.850477 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 15786.850477 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15786.850477 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 15786.850477 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 1529557 # number of replacements
system.cpu.dcache.tagsinuse 4094.960333 # Cycle average of tags in use
system.cpu.dcache.total_refs 895757409 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 1533653 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 584.067849 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 997882000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 4094.960333 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.999746 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.999746 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 618874541 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 618874541 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 276862898 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 276862898 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 9985 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 9985 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 9985 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 9985 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 895737439 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 895737439 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 895737439 # number of overall hits
system.cpu.dcache.overall_hits::total 895737439 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 1460873 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 1460873 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 72780 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 72780 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 1533653 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 1533653 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 1533653 # number of overall misses
system.cpu.dcache.overall_misses::total 1533653 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 79725982000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 79725982000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 3794826000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 3794826000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 83520808000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 83520808000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 83520808000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 83520808000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 620335414 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 620335414 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 276935678 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 276935678 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 9985 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 9985 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 9985 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 9985 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 897271092 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 897271092 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 897271092 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 897271092 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002355 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.002355 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000263 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.000263 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.001709 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.001709 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.001709 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.001709 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54574.204602 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 54574.204602 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52141.055235 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 52141.055235 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 54458.738711 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 54458.738711 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 54458.738711 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 54458.738711 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 107259 # number of writebacks
system.cpu.dcache.writebacks::total 107259 # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1460873 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 1460873 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 72780 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 72780 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 1533653 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 1533653 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 1533653 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 1533653 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75343363000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 75343363000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3576486000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3576486000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 78919849000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 78919849000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 78919849000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 78919849000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002355 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002355 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000263 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000263 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001709 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.001709 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001709 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.001709 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51574.204602 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 51574.204602 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49141.055235 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49141.055235 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51458.738711 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 51458.738711 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51458.738711 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 51458.738711 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 1478755 # number of replacements
system.cpu.l2cache.tagsinuse 31934.844118 # Cycle average of tags in use
system.cpu.l2cache.total_refs 75453 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 1511475 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.049920 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 3041.423322 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 32.598415 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 28860.822381 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.092817 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.000995 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.880762 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.974574 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 17546 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 49593 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 67139 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 107259 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 107259 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 6687 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 6687 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst 17546 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 56280 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 73826 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 17546 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 56280 # number of overall hits
system.cpu.l2cache.overall_hits::total 73826 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 2257 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 1411280 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 1413537 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 66093 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 66093 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 2257 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 1477373 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 1479630 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 2257 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 1477373 # number of overall misses
system.cpu.l2cache.overall_misses::total 1479630 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 117364000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 73386560000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 73503924000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3436836000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 3436836000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 117364000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 76823396000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 76940760000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 117364000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 76823396000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 76940760000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 19803 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 1460873 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 1480676 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 107259 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 107259 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 72780 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 72780 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 19803 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 1533653 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 1553456 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 19803 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 1533653 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 1553456 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.113973 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.966052 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.954657 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.908120 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.908120 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.113973 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.963303 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.952476 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.113973 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.963303 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.952476 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks 66099 # number of writebacks
system.cpu.l2cache.writebacks::total 66099 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2257 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1411280 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 1413537 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66093 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 66093 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 2257 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 1477373 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 1479630 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2257 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 1477373 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 1479630 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 90280000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 56451200000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 56541480000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2643720000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2643720000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 90280000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 59094920000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 59185200000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 90280000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 59094920000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 59185200000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.113973 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.966052 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.954657 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.908120 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.908120 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.113973 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.963303 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.952476 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.113973 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.963303 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.952476 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------