christoph/fail
1
Fork 0
Code Actions Packages Releases Activity

Adding gem5 source to svn.

Browse Source 
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1819 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
This commit is contained in:
friemel
2012-10-24 19:18:57 +00:00
parent f7ff71bd46
commit b41eec3f65
3222 changed files with 658579 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

231
simulators/gem5/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/config.ini Normal file
View File

@ -0,0 +1,231 @@
[root]
type=Root
children=system
full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
boot_osflags=a
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
readfile=
symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.cpu]
type=InOrderCPU
children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
BTBEntries=4096
BTBTagSize=16
RASSize=16
activity=0
cachePorts=2
checker=Null
choiceCtrBits=2
choicePredictorSize=8192
clock=500
cpu_id=0
defer_registration=false
div16Latency=1
div16RepeatRate=1
div24Latency=1
div24RepeatRate=1
div32Latency=1
div32RepeatRate=1
div8Latency=1
div8RepeatRate=1
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
fetchBuffSize=4
functionTrace=false
functionTraceStart=0
function_trace=false
function_trace_start=0
globalCtrBits=2
globalHistoryBits=13
globalPredictorSize=8192
instShiftAmt=2
interrupts=system.cpu.interrupts
itb=system.cpu.itb
localCtrBits=2
localHistoryBits=11
localHistoryTableSize=2048
localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
memBlockSize=64
multLatency=1
multRepeatRate=1
numThreads=1
phase=0
predType=tournament
profile=0
progress_interval=0
stageTracing=false
stageWidth=4
system=system
threadModel=SMT
tracer=system.cpu.tracer
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=262144
subblock_size=0
system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
[system.cpu.dtb]
type=AlphaTLB
size=64
[system.cpu.icache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=131072
subblock_size=0
system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.interrupts]
type=AlphaInterrupts
[system.cpu.itb]
type=AlphaTLB
size=48
[system.cpu.l2cache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=false
latency=10000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=2097152
subblock_size=0
system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
[system.cpu.toL2Bus]
type=CoherentBus
block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
cwd=build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/inorder-timing
egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon
gid=100
input=cin
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=0
system=system
uid=100
[system.membus]
type=CoherentBus
block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
master=system.physmem.port[0]
slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=SimpleMemory
conf_table_reported=false
file=
in_addr_map=true
latency=30000
latency_var=0
null=false
range=0:134217727
zero=false
port=system.membus.master[0]

52
simulators/gem5/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/simerr Executable file
View File

@ -0,0 +1,52 @@
warn: Sockets disabled, not accepting gdb connections
warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
getting pixel output filename pixels_out.cook
opening control file chair.control.cook
opening camera file chair.camera
opening surfaces file chair.surfaces
reading data
processing 8parts
Grid measure is 6 by 3.0001 by 6
cell dimension is 0.863065
Creating grid for list of length 21
Grid size = 7 by 4 by 7
Total occupancy = 236
reading control stream
reading camera stream
Writing to chair.cook.ppm
calculating 15 by 15 image with 196 samples
col 0. . .
col 1. . .
col 2. . .
col 3. . .
col 4. . .
col 5. . .
col 6. . .
col 7. . .
col 8. . .
col 9. . .
col 10. . .
col 11. . .
col 12. . .
col 13. . .
col 14. . .
Writing to chair.cook.ppm
0 8 14
1 8 14
2 8 14
3 8 14
4 8 14
5 8 14
6 8 14
7 8 14
8 8 14
9 8 14
10 8 14
11 8 14
12 8 14
13 8 14
14 8 14
warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
hack: be nice to actually delete the event here

14
simulators/gem5/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/simout Executable file
View File

@ -0,0 +1,14 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 4 2012 11:50:11
gem5 started Jun 4 2012 13:42:58
gem5 executing on zizzer
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/inorder-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Eon, Version 1.1
info: Increasing stack size by one page.
OO-style eon Time= 0.133333
Exiting @ tick 141175129500 because target called exit()

460
simulators/gem5/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt Normal file
View File

@ -0,0 +1,460 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.141175 # Number of seconds simulated
sim_ticks 141175129500 # Number of ticks simulated
final_tick 141175129500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 110841 # Simulator instruction rate (inst/s)
host_op_rate 110841 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 39251086 # Simulator tick rate (ticks/s)
host_mem_usage 221340 # Number of bytes of host memory used
host_seconds 3596.72 # Real time elapsed on the host
sim_insts 398664595 # Number of instructions simulated
sim_ops 398664595 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 214592 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 254400 # Number of bytes read from this memory
system.physmem.bytes_read::total 468992 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 214592 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 214592 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 3353 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 3975 # Number of read requests responded to by this memory
system.physmem.num_reads::total 7328 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 1520041 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 1802017 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 3322058 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 1520041 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 1520041 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 1520041 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 1802017 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 3322058 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 94755013 # DTB read hits
system.cpu.dtb.read_misses 21 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 94755034 # DTB read accesses
system.cpu.dtb.write_hits 73522045 # DTB write hits
system.cpu.dtb.write_misses 35 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 73522080 # DTB write accesses
system.cpu.dtb.data_hits 168277058 # DTB hits
system.cpu.dtb.data_misses 56 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 168277114 # DTB accesses
system.cpu.itb.fetch_hits 49111850 # ITB hits
system.cpu.itb.fetch_misses 88782 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 49200632 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 215 # Number of system calls
system.cpu.numCycles 282350260 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.branch_predictor.lookups 53870351 # Number of BP lookups
system.cpu.branch_predictor.condPredicted 30921654 # Number of conditional branches predicted
system.cpu.branch_predictor.condIncorrect 16037209 # Number of conditional branches incorrect
system.cpu.branch_predictor.BTBLookups 33426940 # Number of BTB lookups
system.cpu.branch_predictor.BTBHits 15653987 # Number of BTB hits
system.cpu.branch_predictor.usedRAS 8007516 # Number of times the RAS was used to get a target.
system.cpu.branch_predictor.RASInCorrect 18 # Number of incorrect RAS predictions.
system.cpu.branch_predictor.BTBHitPct 46.830452 # BTB Hit Percentage
system.cpu.branch_predictor.predictedTaken 29683846 # Number of Branches Predicted As Taken (True).
system.cpu.branch_predictor.predictedNotTaken 24186505 # Number of Branches Predicted As Not Taken (False).
system.cpu.regfile_manager.intRegFileReads 280818442 # Number of Reads from Int. Register File
system.cpu.regfile_manager.intRegFileWrites 159335859 # Number of Writes to Int. Register File
system.cpu.regfile_manager.intRegFileAccesses 440154301 # Total Accesses (Read+Write) to the Int. Register File
system.cpu.regfile_manager.floatRegFileReads 119907697 # Number of Reads from FP Register File
system.cpu.regfile_manager.floatRegFileWrites 100196481 # Number of Writes to FP Register File
system.cpu.regfile_manager.floatRegFileAccesses 220104178 # Total Accesses (Read+Write) to the FP Register File
system.cpu.regfile_manager.regForwards 100457644 # Number of Registers Read Through Forwarding Logic
system.cpu.agen_unit.agens 168700458 # Number of Address Generations
system.cpu.execution_unit.predictedTakenIncorrect 14475221 # Number of Branches Incorrectly Predicted As Taken.
system.cpu.execution_unit.predictedNotTakenIncorrect 1561329 # Number of Branches Incorrectly Predicted As Not Taken).
system.cpu.execution_unit.mispredicted 16036550 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.predicted 28551001 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.mispredictPct 35.966429 # Percentage of Incorrect Branches Predicts
system.cpu.execution_unit.executions 205750873 # Number of Instructions Executed.
system.cpu.mult_div_unit.multiplies 2124330 # Number of Multipy Operations Executed
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
system.cpu.contextSwitches 1 # Number of context switches
system.cpu.threadCycles 281921224 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
system.cpu.timesIdled 6799 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 13475974 # Number of cycles cpu's stages were not processed
system.cpu.runCycles 268874286 # Number of cycles cpu stages are processed.
system.cpu.activity 95.227214 # Percentage of cycles cpu is active
system.cpu.comLoads 94754489 # Number of Load instructions committed
system.cpu.comStores 73520729 # Number of Store instructions committed
system.cpu.comBranches 44587532 # Number of Branches instructions committed
system.cpu.comNops 23089775 # Number of Nop instructions committed
system.cpu.comNonSpec 215 # Number of Non-Speculative instructions committed
system.cpu.comInts 112239074 # Number of Integer instructions committed
system.cpu.comFloats 50439198 # Number of Floating Point instructions committed
system.cpu.committedInsts 398664595 # Number of Instructions committed (Per-Thread)
system.cpu.committedOps 398664595 # Number of Ops committed (Per-Thread)
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
system.cpu.committedInsts_total 398664595 # Number of Instructions committed (Total)
system.cpu.cpi 0.708240 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.smt_cpi nan # CPI: Total SMT-CPI
system.cpu.cpi_total 0.708240 # CPI: Total CPI of All Threads
system.cpu.ipc 1.411951 # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.smt_ipc nan # IPC: Total SMT-IPC
system.cpu.ipc_total 1.411951 # IPC: Total IPC of All Threads
system.cpu.stage0.idleCycles 78536322 # Number of cycles 0 instructions are processed.
system.cpu.stage0.runCycles 203813938 # Number of cycles 1+ instructions are processed.
system.cpu.stage0.utilization 72.184788 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage1.idleCycles 108863639 # Number of cycles 0 instructions are processed.
system.cpu.stage1.runCycles 173486621 # Number of cycles 1+ instructions are processed.
system.cpu.stage1.utilization 61.443762 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage2.idleCycles 104640873 # Number of cycles 0 instructions are processed.
system.cpu.stage2.runCycles 177709387 # Number of cycles 1+ instructions are processed.
system.cpu.stage2.utilization 62.939339 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage3.idleCycles 183568799 # Number of cycles 0 instructions are processed.
system.cpu.stage3.runCycles 98781461 # Number of cycles 1+ instructions are processed.
system.cpu.stage3.utilization 34.985433 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage4.idleCycles 92657665 # Number of cycles 0 instructions are processed.
system.cpu.stage4.runCycles 189692595 # Number of cycles 1+ instructions are processed.
system.cpu.stage4.utilization 67.183432 # Percentage of cycles stage was utilized (processing insts).
system.cpu.icache.replacements 1974 # number of replacements
system.cpu.icache.tagsinuse 1829.918694 # Cycle average of tags in use
system.cpu.icache.total_refs 49107469 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 3901 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 12588.430915 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 1829.918694 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.893515 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.893515 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 49107469 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 49107469 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 49107469 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 49107469 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 49107469 # number of overall hits
system.cpu.icache.overall_hits::total 49107469 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 4380 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 4380 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 4380 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 4380 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 4380 # number of overall misses
system.cpu.icache.overall_misses::total 4380 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 214309000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 214309000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 214309000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 214309000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 214309000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 214309000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 49111849 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 49111849 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 49111849 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 49111849 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 49111849 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 49111849 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000089 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000089 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000089 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000089 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000089 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000089 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48928.995434 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 48928.995434 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 48928.995434 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 48928.995434 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 48928.995434 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 48928.995434 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 45000 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets 45000 # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 479 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 479 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 479 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 479 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 479 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 479 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 3901 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 3901 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 3901 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 3901 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 3901 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 3901 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 185222000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 185222000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 185222000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 185222000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 185222000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 185222000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000079 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000079 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000079 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000079 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000079 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000079 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 47480.645988 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 47480.645988 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 47480.645988 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 47480.645988 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 47480.645988 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 47480.645988 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 764 # number of replacements
system.cpu.dcache.tagsinuse 3284.843893 # Cycle average of tags in use
system.cpu.dcache.total_refs 168261959 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 4152 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 40525.519990 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 3284.843893 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.801964 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.801964 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 94753265 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 94753265 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 73508694 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 73508694 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 168261959 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 168261959 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 168261959 # number of overall hits
system.cpu.dcache.overall_hits::total 168261959 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 1224 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 1224 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 12035 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 12035 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 13259 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 13259 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 13259 # number of overall misses
system.cpu.dcache.overall_misses::total 13259 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 63819000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 63819000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 626556000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 626556000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 690375000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 690375000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 690375000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 690375000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 94754489 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 94754489 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 73520729 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 73520729 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 168275218 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 168275218 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 168275218 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 168275218 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000013 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.000013 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000164 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.000164 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.000079 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.000079 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.000079 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.000079 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 52139.705882 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 52139.705882 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52061.154965 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 52061.154965 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 52068.406365 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 52068.406365 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 52068.406365 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 52068.406365 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 82410500 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 1848 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 44594.426407 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 649 # number of writebacks
system.cpu.dcache.writebacks::total 649 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 274 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 274 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 8833 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 8833 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 9107 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 9107 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 9107 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 9107 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 950 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 950 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3202 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 3202 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 4152 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 4152 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 4152 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 4152 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 46180000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 46180000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 169537000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 169537000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 215717000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 215717000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 215717000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 215717000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000044 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 48610.526316 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 48610.526316 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52947.220487 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52947.220487 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51954.961464 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 51954.961464 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51954.961464 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 51954.961464 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 13 # number of replacements
system.cpu.l2cache.tagsinuse 3896.685167 # Cycle average of tags in use
system.cpu.l2cache.total_refs 736 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 4717 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.156031 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 370.518693 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 2902.345937 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 623.820537 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.011307 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.088573 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.019037 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.118917 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 548 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 117 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 665 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 649 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 649 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 60 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 60 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst 548 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 177 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 725 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 548 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 177 # number of overall hits
system.cpu.l2cache.overall_hits::total 725 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 3353 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 830 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 4183 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 3145 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 3145 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 3353 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 3975 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 7328 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 3353 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 3975 # number of overall misses
system.cpu.l2cache.overall_misses::total 7328 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 175438000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 43622500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 219060500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 164970500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 164970500 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 175438000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 208593000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 384031000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 175438000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 208593000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 384031000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 3901 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 947 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 4848 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 649 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 649 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 3205 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 3205 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 3901 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 4152 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 8053 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 3901 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 4152 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 8053 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.859523 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.876452 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.862830 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.981279 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.981279 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.859523 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.957370 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.909971 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.859523 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.957370 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.909971 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52322.696093 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52557.228916 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52369.232608 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52454.848967 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52454.848967 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52322.696093 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52476.226415 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 52405.977074 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52322.696093 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52476.226415 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 52405.977074 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3353 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 830 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 4183 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3145 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 3145 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 3353 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 3975 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 7328 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3353 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 3975 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 7328 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 134591000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 33517500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 168108500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 126757500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 126757500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 134591000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 160275000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 294866000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 134591000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 160275000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 294866000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.859523 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.876452 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.862830 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.981279 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.981279 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.859523 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.957370 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.909971 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.859523 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.957370 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.909971 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40140.471220 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40382.530120 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40188.501076 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40304.451510 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40304.451510 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40140.471220 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40320.754717 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40238.264192 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40140.471220 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40320.754717 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40238.264192 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

529
simulators/gem5/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini Normal file
View File

@ -0,0 +1,529 @@
[root]
type=Root
children=system
full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
boot_osflags=a
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
readfile=
symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.cpu]
type=DerivO3CPU
children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
LSQDepCheckShift=4
RASSize=16
SQEntries=32
SSITSize=1024
activity=0
backComSize=5
cachePorts=200
checker=Null
choiceCtrBits=2
choicePredictorSize=8192
clock=500
commitToDecodeDelay=1
commitToFetchDelay=1
commitToIEWDelay=1
commitToRenameDelay=1
commitWidth=8
cpu_id=0
decodeToFetchDelay=1
decodeToRenameDelay=1
decodeWidth=8
defer_registration=false
dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
fetchToDecodeDelay=1
fetchTrapLatency=1
fetchWidth=8
forwardComSize=5
fuPool=system.cpu.fuPool
function_trace=false
function_trace_start=0
globalCtrBits=2
globalHistoryBits=13
globalPredictorSize=8192
iewToCommitDelay=1
iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
instShiftAmt=2
interrupts=system.cpu.interrupts
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
localCtrBits=2
localHistoryBits=11
localHistoryTableSize=2048
localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
needsTSO=false
numIQEntries=64
numPhysFloatRegs=256
numPhysIntRegs=256
numROBEntries=192
numRobs=1
numThreads=1
phase=0
predType=tournament
profile=0
progress_interval=0
renameToDecodeDelay=1
renameToFetchDelay=1
renameToIEWDelay=2
renameToROBDelay=1
renameWidth=8
smtCommitPolicy=RoundRobin
smtFetchPolicy=SingleThread
smtIQPolicy=Partitioned
smtIQThreshold=100
smtLSQPolicy=Partitioned
smtLSQThreshold=100
smtNumFetchingThreads=1
smtROBPolicy=Partitioned
smtROBThreshold=100
squashWidth=8
store_set_clear_period=250000
system=system
tracer=system.cpu.tracer
trapLatency=13
wbDepth=1
wbWidth=8
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=262144
subblock_size=0
system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
[system.cpu.dtb]
type=AlphaTLB
size=64
[system.cpu.fuPool]
type=FUPool
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
[system.cpu.fuPool.FUList0]
type=FUDesc
children=opList
count=6
opList=system.cpu.fuPool.FUList0.opList
[system.cpu.fuPool.FUList0.opList]
type=OpDesc
issueLat=1
opClass=IntAlu
opLat=1
[system.cpu.fuPool.FUList1]
type=FUDesc
children=opList0 opList1
count=2
opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
[system.cpu.fuPool.FUList1.opList0]
type=OpDesc
issueLat=1
opClass=IntMult
opLat=3
[system.cpu.fuPool.FUList1.opList1]
type=OpDesc
issueLat=19
opClass=IntDiv
opLat=20
[system.cpu.fuPool.FUList2]
type=FUDesc
children=opList0 opList1 opList2
count=4
opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
[system.cpu.fuPool.FUList2.opList0]
type=OpDesc
issueLat=1
opClass=FloatAdd
opLat=2
[system.cpu.fuPool.FUList2.opList1]
type=OpDesc
issueLat=1
opClass=FloatCmp
opLat=2
[system.cpu.fuPool.FUList2.opList2]
type=OpDesc
issueLat=1
opClass=FloatCvt
opLat=2
[system.cpu.fuPool.FUList3]
type=FUDesc
children=opList0 opList1 opList2
count=2
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
[system.cpu.fuPool.FUList3.opList0]
type=OpDesc
issueLat=1
opClass=FloatMult
opLat=4
[system.cpu.fuPool.FUList3.opList1]
type=OpDesc
issueLat=12
opClass=FloatDiv
opLat=12
[system.cpu.fuPool.FUList3.opList2]
type=OpDesc
issueLat=24
opClass=FloatSqrt
opLat=24
[system.cpu.fuPool.FUList4]
type=FUDesc
children=opList
count=0
opList=system.cpu.fuPool.FUList4.opList
[system.cpu.fuPool.FUList4.opList]
type=OpDesc
issueLat=1
opClass=MemRead
opLat=1
[system.cpu.fuPool.FUList5]
type=FUDesc
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
count=4
opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
[system.cpu.fuPool.FUList5.opList00]
type=OpDesc
issueLat=1
opClass=SimdAdd
opLat=1
[system.cpu.fuPool.FUList5.opList01]
type=OpDesc
issueLat=1
opClass=SimdAddAcc
opLat=1
[system.cpu.fuPool.FUList5.opList02]
type=OpDesc
issueLat=1
opClass=SimdAlu
opLat=1
[system.cpu.fuPool.FUList5.opList03]
type=OpDesc
issueLat=1
opClass=SimdCmp
opLat=1
[system.cpu.fuPool.FUList5.opList04]
type=OpDesc
issueLat=1
opClass=SimdCvt
opLat=1
[system.cpu.fuPool.FUList5.opList05]
type=OpDesc
issueLat=1
opClass=SimdMisc
opLat=1
[system.cpu.fuPool.FUList5.opList06]
type=OpDesc
issueLat=1
opClass=SimdMult
opLat=1
[system.cpu.fuPool.FUList5.opList07]
type=OpDesc
issueLat=1
opClass=SimdMultAcc
opLat=1
[system.cpu.fuPool.FUList5.opList08]
type=OpDesc
issueLat=1
opClass=SimdShift
opLat=1
[system.cpu.fuPool.FUList5.opList09]
type=OpDesc
issueLat=1
opClass=SimdShiftAcc
opLat=1
[system.cpu.fuPool.FUList5.opList10]
type=OpDesc
issueLat=1
opClass=SimdSqrt
opLat=1
[system.cpu.fuPool.FUList5.opList11]
type=OpDesc
issueLat=1
opClass=SimdFloatAdd
opLat=1
[system.cpu.fuPool.FUList5.opList12]
type=OpDesc
issueLat=1
opClass=SimdFloatAlu
opLat=1
[system.cpu.fuPool.FUList5.opList13]
type=OpDesc
issueLat=1
opClass=SimdFloatCmp
opLat=1
[system.cpu.fuPool.FUList5.opList14]
type=OpDesc
issueLat=1
opClass=SimdFloatCvt
opLat=1
[system.cpu.fuPool.FUList5.opList15]
type=OpDesc
issueLat=1
opClass=SimdFloatDiv
opLat=1
[system.cpu.fuPool.FUList5.opList16]
type=OpDesc
issueLat=1
opClass=SimdFloatMisc
opLat=1
[system.cpu.fuPool.FUList5.opList17]
type=OpDesc
issueLat=1
opClass=SimdFloatMult
opLat=1
[system.cpu.fuPool.FUList5.opList18]
type=OpDesc
issueLat=1
opClass=SimdFloatMultAcc
opLat=1
[system.cpu.fuPool.FUList5.opList19]
type=OpDesc
issueLat=1
opClass=SimdFloatSqrt
opLat=1
[system.cpu.fuPool.FUList6]
type=FUDesc
children=opList
count=0
opList=system.cpu.fuPool.FUList6.opList
[system.cpu.fuPool.FUList6.opList]
type=OpDesc
issueLat=1
opClass=MemWrite
opLat=1
[system.cpu.fuPool.FUList7]
type=FUDesc
children=opList0 opList1
count=4
opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
[system.cpu.fuPool.FUList7.opList0]
type=OpDesc
issueLat=1
opClass=MemRead
opLat=1
[system.cpu.fuPool.FUList7.opList1]
type=OpDesc
issueLat=1
opClass=MemWrite
opLat=1
[system.cpu.fuPool.FUList8]
type=FUDesc
children=opList
count=1
opList=system.cpu.fuPool.FUList8.opList
[system.cpu.fuPool.FUList8.opList]
type=OpDesc
issueLat=3
opClass=IprAccess
opLat=3
[system.cpu.icache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=131072
subblock_size=0
system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.interrupts]
type=AlphaInterrupts
[system.cpu.itb]
type=AlphaTLB
size=48
[system.cpu.l2cache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=false
latency=1000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=2097152
subblock_size=0
system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
[system.cpu.toL2Bus]
type=CoherentBus
block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
cwd=build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing
egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon
gid=100
input=cin
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=0
system=system
uid=100
[system.membus]
type=CoherentBus
block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
master=system.physmem.port[0]
slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=SimpleMemory
conf_table_reported=false
file=
in_addr_map=true
latency=30000
latency_var=0
null=false
range=0:134217727
zero=false
port=system.membus.master[0]

52
simulators/gem5/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simerr Executable file
View File

@ -0,0 +1,52 @@
warn: Sockets disabled, not accepting gdb connections
warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
getting pixel output filename pixels_out.cook
opening control file chair.control.cook
opening camera file chair.camera
opening surfaces file chair.surfaces
reading data
processing 8parts
Grid measure is 6 by 3.0001 by 6
cell dimension is 0.863065
Creating grid for list of length 21
Grid size = 7 by 4 by 7
Total occupancy = 236
reading control stream
reading camera stream
Writing to chair.cook.ppm
calculating 15 by 15 image with 196 samples
col 0. . .
col 1. . .
col 2. . .
col 3. . .
col 4. . .
col 5. . .
col 6. . .
col 7. . .
col 8. . .
col 9. . .
col 10. . .
col 11. . .
col 12. . .
col 13. . .
col 14. . .
Writing to chair.cook.ppm
0 8 14
1 8 14
2 8 14
3 8 14
4 8 14
5 8 14
6 8 14
7 8 14
8 8 14
9 8 14
10 8 14
11 8 14
12 8 14
13 8 14
14 8 14
warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
hack: be nice to actually delete the event here

14
simulators/gem5/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout Executable file
View File

@ -0,0 +1,14 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 4 2012 11:50:11
gem5 started Jun 4 2012 13:46:44
gem5 executing on zizzer
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Eon, Version 1.1
info: Increasing stack size by one page.
OO-style eon Time= 0.066667
Exiting @ tick 80257421500 because target called exit()

666
simulators/gem5/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt Normal file
View File

@ -0,0 +1,666 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.080257 # Number of seconds simulated
sim_ticks 80257421500 # Number of ticks simulated
final_tick 80257421500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 183656 # Simulator instruction rate (inst/s)
host_op_rate 183656 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 39245952 # Simulator tick rate (ticks/s)
host_mem_usage 222148 # Number of bytes of host memory used
host_seconds 2044.99 # Real time elapsed on the host
sim_insts 375574808 # Number of instructions simulated
sim_ops 375574808 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 222720 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 255808 # Number of bytes read from this memory
system.physmem.bytes_read::total 478528 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 222720 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 222720 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 3480 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 3997 # Number of read requests responded to by this memory
system.physmem.num_reads::total 7477 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 2775070 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 3187344 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 5962414 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 2775070 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 2775070 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 2775070 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 3187344 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 5962414 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 103368572 # DTB read hits
system.cpu.dtb.read_misses 88956 # DTB read misses
system.cpu.dtb.read_acv 48603 # DTB read access violations
system.cpu.dtb.read_accesses 103457528 # DTB read accesses
system.cpu.dtb.write_hits 78975243 # DTB write hits
system.cpu.dtb.write_misses 1664 # DTB write misses
system.cpu.dtb.write_acv 3 # DTB write access violations
system.cpu.dtb.write_accesses 78976907 # DTB write accesses
system.cpu.dtb.data_hits 182343815 # DTB hits
system.cpu.dtb.data_misses 90620 # DTB misses
system.cpu.dtb.data_acv 48606 # DTB access violations
system.cpu.dtb.data_accesses 182434435 # DTB accesses
system.cpu.itb.fetch_hits 52487109 # ITB hits
system.cpu.itb.fetch_misses 461 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 52487570 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 215 # Number of system calls
system.cpu.numCycles 160514845 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.BPredUnit.lookups 52017212 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 30261257 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 1593315 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 28494887 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 24272738 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 9355488 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 4145 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 53524792 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 462212886 # Number of instructions fetch has processed
system.cpu.fetch.Branches 52017212 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 33628226 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 81457148 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 7754706 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 19283001 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 185 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 7777 # Number of stall cycles due to pending traps
system.cpu.fetch.CacheLines 52487109 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 628108 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 160395311 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.881711 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.314748 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 78938163 49.21% 49.21% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 4375676 2.73% 51.94% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 7263628 4.53% 56.47% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 5613511 3.50% 59.97% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 12408314 7.74% 67.71% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 8080182 5.04% 72.74% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 5692573 3.55% 76.29% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 1906295 1.19% 77.48% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 36116969 22.52% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 160395311 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.324065 # Number of branch fetches per cycle
system.cpu.fetch.rate 2.879565 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 59060129 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 14738019 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 76660368 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 3818816 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 6117979 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 9735972 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 4512 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 456714619 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 12671 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 6117979 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 62341788 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 4786215 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 392111 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 77312738 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 9444480 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 451064099 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 10 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 26210 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 7820126 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenamedOperands 294805500 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 593185508 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 313931497 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 279254011 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 259532329 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 35273171 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 38670 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 424 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 27284397 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 106956708 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 81779793 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 8927292 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 6395845 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 416292628 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 359 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 407676624 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 1078526 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 40464590 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 19834312 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 144 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 160395311 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 2.541699 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 2.006909 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 31984575 19.94% 19.94% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 26488225 16.51% 36.46% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 26058764 16.25% 52.70% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 24758572 15.44% 68.14% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 21531957 13.42% 81.56% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 15472386 9.65% 91.21% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 8703569 5.43% 96.64% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 4094121 2.55% 99.19% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 1303142 0.81% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 160395311 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 35479 0.30% 0.30% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 0.30% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 0.30% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 74583 0.63% 0.93% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 5020 0.04% 0.97% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 3238 0.03% 1.00% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 1852472 15.62% 16.62% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 1780365 15.01% 31.63% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 31.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 31.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 31.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 31.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 31.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 31.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 31.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 31.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 31.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 31.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 31.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 31.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 31.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 31.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 31.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 31.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 31.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 31.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 31.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 31.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 31.63% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 5090382 42.92% 74.55% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 3018331 25.45% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 33581 0.01% 0.01% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 157965890 38.75% 38.76% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 2126519 0.52% 39.28% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 39.28% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 33457651 8.21% 47.48% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 7841942 1.92% 49.41% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 2840834 0.70% 50.11% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 16563363 4.06% 54.17% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 1591033 0.39% 54.56% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 54.56% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 54.56% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 54.56% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 54.56% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 54.56% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 54.56% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 54.56% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 54.56% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 54.56% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 54.56% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 54.56% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 54.56% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 54.56% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 54.56% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 54.56% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 54.56% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 54.56% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 54.56% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.56% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 54.56% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.56% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 105252822 25.82% 80.38% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 80002989 19.62% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 407676624 # Type of FU issued
system.cpu.iq.rate 2.539806 # Inst issue rate
system.cpu.iq.fu_busy_cnt 11859870 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.029091 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 647408174 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 269506276 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 237627844 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 341278781 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 187302066 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 162920489 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 245219921 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 174282992 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 14797631 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 12202221 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 124163 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 50788 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 8259064 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 260903 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 1 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 6117979 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 2500869 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 370633 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 441236152 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 174981 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 106956708 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 81779793 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 359 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 125 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 18 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 50788 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 1245732 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 559417 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 1805149 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 403162552 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 103506235 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 4514072 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 24943165 # number of nop insts executed
system.cpu.iew.exec_refs 182483180 # number of memory reference insts executed
system.cpu.iew.exec_branches 47188511 # Number of branches executed
system.cpu.iew.exec_stores 78976945 # Number of stores executed
system.cpu.iew.exec_rate 2.511684 # Inst execution rate
system.cpu.iew.wb_sent 401387937 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 400548333 # cumulative count of insts written-back
system.cpu.iew.wb_producers 195210305 # num instructions producing a value
system.cpu.iew.wb_consumers 273275997 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 2.495397 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.714334 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitCommittedInsts 398664583 # The number of committed instructions
system.cpu.commit.commitCommittedOps 398664583 # The number of committed instructions
system.cpu.commit.commitSquashedInsts 42606114 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 215 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 1588886 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 154277332 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 2.584078 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.967872 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 58795294 38.11% 38.11% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 23338616 15.13% 53.24% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 13263185 8.60% 61.83% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 11678899 7.57% 69.40% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 8438473 5.47% 74.87% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 5481478 3.55% 78.43% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 5137622 3.33% 81.76% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 3374234 2.19% 83.94% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 24769531 16.06% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 154277332 # Number of insts commited each cycle
system.cpu.commit.committedInsts 398664583 # Number of instructions committed
system.cpu.commit.committedOps 398664583 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 168275216 # Number of memory references committed
system.cpu.commit.loads 94754487 # Number of loads committed
system.cpu.commit.membars 0 # Number of memory barriers committed
system.cpu.commit.branches 44587533 # Number of branches committed
system.cpu.commit.fp_insts 155295106 # Number of committed floating point instructions.
system.cpu.commit.int_insts 316365839 # Number of committed integer instructions.
system.cpu.commit.function_calls 8007752 # Number of function calls committed.
system.cpu.commit.bw_lim_events 24769531 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 570775521 # The number of ROB reads
system.cpu.rob.rob_writes 888672842 # The number of ROB writes
system.cpu.timesIdled 2679 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 119534 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 375574808 # Number of Instructions Simulated
system.cpu.committedOps 375574808 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 375574808 # Number of Instructions Simulated
system.cpu.cpi 0.427384 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.427384 # CPI: Total CPI of All Threads
system.cpu.ipc 2.339814 # IPC: Instructions Per Cycle
system.cpu.ipc_total 2.339814 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 402674037 # number of integer regfile reads
system.cpu.int_regfile_writes 172514061 # number of integer regfile writes
system.cpu.fp_regfile_reads 158318736 # number of floating regfile reads
system.cpu.fp_regfile_writes 105208261 # number of floating regfile writes
system.cpu.misc_regfile_reads 350572 # number of misc regfile reads
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
system.cpu.icache.replacements 2234 # number of replacements
system.cpu.icache.tagsinuse 1837.389415 # Cycle average of tags in use
system.cpu.icache.total_refs 52481453 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 4164 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 12603.615034 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 1837.389415 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.897163 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.897163 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 52481453 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 52481453 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 52481453 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 52481453 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 52481453 # number of overall hits
system.cpu.icache.overall_hits::total 52481453 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 5656 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 5656 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 5656 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 5656 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 5656 # number of overall misses
system.cpu.icache.overall_misses::total 5656 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 175405000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 175405000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 175405000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 175405000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 175405000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 175405000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 52487109 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 52487109 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 52487109 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 52487109 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 52487109 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 52487109 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000108 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000108 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000108 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000108 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000108 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000108 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 31012.199434 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 31012.199434 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 31012.199434 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 31012.199434 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 31012.199434 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 31012.199434 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1492 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 1492 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 1492 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 1492 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 1492 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 1492 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4164 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 4164 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 4164 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 4164 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 4164 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 4164 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 125153000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 125153000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 125153000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 125153000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 125153000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 125153000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000079 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000079 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000079 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000079 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000079 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000079 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 30055.955812 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 30055.955812 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 30055.955812 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 30055.955812 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 30055.955812 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 30055.955812 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 804 # number of replacements
system.cpu.dcache.tagsinuse 3297.800145 # Cycle average of tags in use
system.cpu.dcache.total_refs 161809566 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 4205 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 38480.277289 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 3297.800145 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.805127 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.805127 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 88308332 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 88308332 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 73501218 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 73501218 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 16 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 16 # number of LoadLockedReq hits
system.cpu.dcache.demand_hits::cpu.data 161809550 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 161809550 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 161809550 # number of overall hits
system.cpu.dcache.overall_hits::total 161809550 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 1689 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 1689 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 19511 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 19511 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 21200 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 21200 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 21200 # number of overall misses
system.cpu.dcache.overall_misses::total 21200 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 56020500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 56020500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 567228500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 567228500 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 623249000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 623249000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 623249000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 623249000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 88310021 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 88310021 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 73520729 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 73520729 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 16 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 16 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 161830750 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 161830750 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 161830750 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 161830750 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000019 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.000019 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000265 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.000265 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.000131 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.000131 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.000131 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.000131 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33167.850799 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 33167.850799 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29072.241300 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 29072.241300 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 29398.537736 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 29398.537736 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 29398.537736 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 29398.537736 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 2500 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 2500 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 682 # number of writebacks
system.cpu.dcache.writebacks::total 682 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 686 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 686 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16309 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 16309 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 16995 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 16995 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 16995 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 16995 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1003 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 1003 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3202 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 3202 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 4205 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 4205 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 4205 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 4205 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 31754500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 31754500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 113124000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 113124000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 144878500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 144878500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 144878500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 144878500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000011 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000011 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000044 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000026 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.000026 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000026 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.000026 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31659.521436 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31659.521436 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35329.169269 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35329.169269 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34453.864447 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 34453.864447 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34453.864447 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 34453.864447 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 11 # number of replacements
system.cpu.l2cache.tagsinuse 4039.301940 # Cycle average of tags in use
system.cpu.l2cache.total_refs 903 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 4887 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.184776 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 374.716771 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 3001.811767 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 662.773402 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.011435 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.091608 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.020226 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.123270 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 684 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 133 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 817 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 682 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 682 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 75 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 75 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst 684 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 208 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 892 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 684 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 208 # number of overall hits
system.cpu.l2cache.overall_hits::total 892 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 3480 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 870 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 4350 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 3127 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 3127 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 3480 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 3997 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 7477 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 3480 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 3997 # number of overall misses
system.cpu.l2cache.overall_misses::total 7477 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 119653000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 30088500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 149741500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 108341500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 108341500 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 119653000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 138430000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 258083000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 119653000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 138430000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 258083000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 4164 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 1003 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 5167 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 682 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 682 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 3202 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 3202 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 4164 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 4205 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 8369 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 4164 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 4205 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 8369 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.835735 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.867398 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.841881 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.976577 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.976577 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.835735 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.950535 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.893416 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.835735 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.950535 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.893416 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34383.045977 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34584.482759 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 34423.333333 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34647.105852 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34647.105852 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34383.045977 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34633.475106 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 34516.918550 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34383.045977 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34633.475106 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 34516.918550 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3480 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 870 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 4350 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3127 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 3127 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 3480 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 3997 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 7477 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3480 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 3997 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 7477 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 108421000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 27340000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 135761000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 98470000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 98470000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 108421000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 125810000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 234231000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 108421000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 125810000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 234231000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.835735 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.867398 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.841881 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.976577 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.976577 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.835735 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.950535 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.893416 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.835735 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.950535 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.893416 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31155.459770 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31425.287356 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31209.425287 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31490.246242 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31490.246242 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31155.459770 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31476.107080 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31326.869065 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31155.459770 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31476.107080 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31326.869065 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

117
simulators/gem5/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/config.ini Normal file
View File

@ -0,0 +1,117 @@
[root]
type=Root
children=system
full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
boot_osflags=a
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
readfile=
symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.cpu]
type=AtomicSimpleCPU
children=dtb interrupts itb tracer workload
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
fastmem=false
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
phase=0
profile=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
system=system
tracer=system.cpu.tracer
width=1
workload=system.cpu.workload
dcache_port=system.membus.slave[2]
icache_port=system.membus.slave[1]
[system.cpu.dtb]
type=AlphaTLB
size=64
[system.cpu.interrupts]
type=AlphaInterrupts
[system.cpu.itb]
type=AlphaTLB
size=48
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
cwd=build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/simple-atomic
egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon
gid=100
input=cin
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=0
system=system
uid=100
[system.membus]
type=CoherentBus
block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
master=system.physmem.port[0]
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
[system.physmem]
type=SimpleMemory
conf_table_reported=false
file=
in_addr_map=true
latency=30000
latency_var=0
null=false
range=0:134217727
zero=false
port=system.membus.master[0]

53
simulators/gem5/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/simerr Executable file
View File

@ -0,0 +1,53 @@
warn: CoherentBus system.membus has no snooping ports attached!
warn: Sockets disabled, not accepting gdb connections
warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
getting pixel output filename pixels_out.cook
opening control file chair.control.cook
opening camera file chair.camera
opening surfaces file chair.surfaces
reading data
processing 8parts
Grid measure is 6 by 3.0001 by 6
cell dimension is 0.863065
Creating grid for list of length 21
Grid size = 7 by 4 by 7
Total occupancy = 236
reading control stream
reading camera stream
Writing to chair.cook.ppm
calculating 15 by 15 image with 196 samples
col 0. . .
col 1. . .
col 2. . .
col 3. . .
col 4. . .
col 5. . .
col 6. . .
col 7. . .
col 8. . .
col 9. . .
col 10. . .
col 11. . .
col 12. . .
col 13. . .
col 14. . .
Writing to chair.cook.ppm
0 8 14
1 8 14
2 8 14
3 8 14
4 8 14
5 8 14
6 8 14
7 8 14
8 8 14
9 8 14
10 8 14
11 8 14
12 8 14
13 8 14
14 8 14
warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
hack: be nice to actually delete the event here

14
simulators/gem5/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/simout Executable file
View File

@ -0,0 +1,14 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 4 2012 11:50:11
gem5 started Jun 4 2012 14:23:04
gem5 executing on zizzer
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Eon, Version 1.1
info: Increasing stack size by one page.
OO-style eon Time= 0.183333
Exiting @ tick 199332411500 because target called exit()

92
simulators/gem5/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt Normal file
View File

@ -0,0 +1,92 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.199332 # Number of seconds simulated
sim_ticks 199332411500 # Number of ticks simulated
final_tick 199332411500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 3372014 # Simulator instruction rate (inst/s)
host_op_rate 3372014 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1686007461 # Simulator tick rate (ticks/s)
host_mem_usage 211928 # Number of bytes of host memory used
host_seconds 118.23 # Real time elapsed on the host
sim_insts 398664595 # Number of instructions simulated
sim_ops 398664595 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 1594658604 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 662449271 # Number of bytes read from this memory
system.physmem.bytes_read::total 2257107875 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 1594658604 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 1594658604 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 492356798 # Number of bytes written to this memory
system.physmem.bytes_written::total 492356798 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 398664651 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 94754489 # Number of read requests responded to by this memory
system.physmem.num_reads::total 493419140 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 73520729 # Number of write requests responded to by this memory
system.physmem.num_writes::total 73520729 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 7999996548 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 3323339471 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 11323336020 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 7999996548 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 7999996548 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 2470028804 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 2470028804 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 7999996548 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 5793368275 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 13793364824 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 94754489 # DTB read hits
system.cpu.dtb.read_misses 21 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 94754510 # DTB read accesses
system.cpu.dtb.write_hits 73520729 # DTB write hits
system.cpu.dtb.write_misses 35 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 73520764 # DTB write accesses
system.cpu.dtb.data_hits 168275218 # DTB hits
system.cpu.dtb.data_misses 56 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 168275274 # DTB accesses
system.cpu.itb.fetch_hits 398664651 # ITB hits
system.cpu.itb.fetch_misses 173 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 398664824 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 215 # Number of system calls
system.cpu.numCycles 398664824 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 398664595 # Number of instructions committed
system.cpu.committedOps 398664595 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 316365907 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 155295119 # Number of float alu accesses
system.cpu.num_func_calls 16015498 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 25997787 # number of instructions that are conditional controls
system.cpu.num_int_insts 316365907 # number of integer instructions
system.cpu.num_fp_insts 155295119 # number of float instructions
system.cpu.num_int_register_reads 372938760 # number of times the integer registers were read
system.cpu.num_int_register_writes 159335860 # number of times the integer registers were written
system.cpu.num_fp_register_reads 151776196 # number of times the floating registers were read
system.cpu.num_fp_register_writes 100196481 # number of times the floating registers were written
system.cpu.num_mem_refs 168275274 # number of memory refs
system.cpu.num_load_insts 94754510 # Number of load instructions
system.cpu.num_store_insts 73520764 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 398664824 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
---------- End Simulation Statistics ----------

198
simulators/gem5/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/config.ini Normal file
View File

@ -0,0 +1,198 @@
[root]
type=Root
children=system
full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
boot_osflags=a
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
readfile=
symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.cpu]
type=TimingSimpleCPU
children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
phase=0
profile=0
progress_interval=0
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=262144
subblock_size=0
system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
[system.cpu.dtb]
type=AlphaTLB
size=64
[system.cpu.icache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=131072
subblock_size=0
system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.interrupts]
type=AlphaInterrupts
[system.cpu.itb]
type=AlphaTLB
size=48
[system.cpu.l2cache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=false
latency=10000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=2097152
subblock_size=0
system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
[system.cpu.toL2Bus]
type=CoherentBus
block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
cwd=build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/simple-timing
egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon
gid=100
input=cin
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=0
system=system
uid=100
[system.membus]
type=CoherentBus
block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
master=system.physmem.port[0]
slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=SimpleMemory
conf_table_reported=false
file=
in_addr_map=true
latency=30000
latency_var=0
null=false
range=0:134217727
zero=false
port=system.membus.master[0]

52
simulators/gem5/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simerr Executable file
View File

@ -0,0 +1,52 @@
warn: Sockets disabled, not accepting gdb connections
warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
getting pixel output filename pixels_out.cook
opening control file chair.control.cook
opening camera file chair.camera
opening surfaces file chair.surfaces
reading data
processing 8parts
Grid measure is 6 by 3.0001 by 6
cell dimension is 0.863065
Creating grid for list of length 21
Grid size = 7 by 4 by 7
Total occupancy = 236
reading control stream
reading camera stream
Writing to chair.cook.ppm
calculating 15 by 15 image with 196 samples
col 0. . .
col 1. . .
col 2. . .
col 3. . .
col 4. . .
col 5. . .
col 6. . .
col 7. . .
col 8. . .
col 9. . .
col 10. . .
col 11. . .
col 12. . .
col 13. . .
col 14. . .
Writing to chair.cook.ppm
0 8 14
1 8 14
2 8 14
3 8 14
4 8 14
5 8 14
6 8 14
7 8 14
8 8 14
9 8 14
10 8 14
11 8 14
12 8 14
13 8 14
14 8 14
warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
hack: be nice to actually delete the event here

14
simulators/gem5/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simout Executable file
View File

@ -0,0 +1,14 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 4 2012 11:50:11
gem5 started Jun 4 2012 13:47:31
gem5 executing on zizzer
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Eon, Version 1.1
info: Increasing stack size by one page.
OO-style eon Time= 0.566667
Exiting @ tick 567343170000 because target called exit()

400
simulators/gem5/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt Normal file
View File

@ -0,0 +1,400 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.567343 # Number of seconds simulated
sim_ticks 567343170000 # Number of ticks simulated
final_tick 567343170000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1377504 # Simulator instruction rate (inst/s)
host_op_rate 1377504 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1960338494 # Simulator tick rate (ticks/s)
host_mem_usage 220796 # Number of bytes of host memory used
host_seconds 289.41 # Real time elapsed on the host
sim_insts 398664609 # Number of instructions simulated
sim_ops 398664609 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 205120 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 254400 # Number of bytes read from this memory
system.physmem.bytes_read::total 459520 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 205120 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 205120 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 3205 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 3975 # Number of read requests responded to by this memory
system.physmem.num_reads::total 7180 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 361545 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 448406 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 809951 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 361545 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 361545 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 361545 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 448406 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 809951 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 94754490 # DTB read hits
system.cpu.dtb.read_misses 21 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 94754511 # DTB read accesses
system.cpu.dtb.write_hits 73520730 # DTB write hits
system.cpu.dtb.write_misses 35 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 73520765 # DTB write accesses
system.cpu.dtb.data_hits 168275220 # DTB hits
system.cpu.dtb.data_misses 56 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 168275276 # DTB accesses
system.cpu.itb.fetch_hits 398664666 # ITB hits
system.cpu.itb.fetch_misses 173 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 398664839 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 215 # Number of system calls
system.cpu.numCycles 1134686340 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 398664609 # Number of instructions committed
system.cpu.committedOps 398664609 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 316365921 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 155295119 # Number of float alu accesses
system.cpu.num_func_calls 16015498 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 25997790 # number of instructions that are conditional controls
system.cpu.num_int_insts 316365921 # number of integer instructions
system.cpu.num_fp_insts 155295119 # number of float instructions
system.cpu.num_int_register_reads 372938779 # number of times the integer registers were read
system.cpu.num_int_register_writes 159335870 # number of times the integer registers were written
system.cpu.num_fp_register_reads 151776196 # number of times the floating registers were read
system.cpu.num_fp_register_writes 100196481 # number of times the floating registers were written
system.cpu.num_mem_refs 168275276 # number of memory refs
system.cpu.num_load_insts 94754511 # Number of load instructions
system.cpu.num_store_insts 73520765 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 1134686340 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.icache.replacements 1769 # number of replacements
system.cpu.icache.tagsinuse 1795.131074 # Cycle average of tags in use
system.cpu.icache.total_refs 398660993 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 3673 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 108538.250204 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 1795.131074 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.876529 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.876529 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 398660993 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 398660993 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 398660993 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 398660993 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 398660993 # number of overall hits
system.cpu.icache.overall_hits::total 398660993 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 3673 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 3673 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 3673 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 3673 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 3673 # number of overall misses
system.cpu.icache.overall_misses::total 3673 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 186032000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 186032000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 186032000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 186032000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 186032000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 186032000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 398664666 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 398664666 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 398664666 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 398664666 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 398664666 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 398664666 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000009 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000009 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000009 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000009 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000009 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000009 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 50648.516199 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 50648.516199 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 50648.516199 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 50648.516199 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 50648.516199 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 50648.516199 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 3673 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 3673 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 3673 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 3673 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 3673 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 3673 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 175013000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 175013000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 175013000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 175013000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 175013000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 175013000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000009 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000009 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000009 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000009 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000009 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000009 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 47648.516199 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 47648.516199 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 47648.516199 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 47648.516199 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 47648.516199 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 47648.516199 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 764 # number of replacements
system.cpu.dcache.tagsinuse 3288.912598 # Cycle average of tags in use
system.cpu.dcache.total_refs 168271068 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 4152 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 40527.713873 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 3288.912598 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.802957 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.802957 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 94753540 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 94753540 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 73517528 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 73517528 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 168271068 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 168271068 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 168271068 # number of overall hits
system.cpu.dcache.overall_hits::total 168271068 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 950 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 950 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 3202 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 3202 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 4152 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 4152 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 4152 # number of overall misses
system.cpu.dcache.overall_misses::total 4152 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 48286000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 48286000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 176792000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 176792000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 225078000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 225078000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 225078000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 225078000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 94754490 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 94754490 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 73520730 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 73520730 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 168275220 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 168275220 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 168275220 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 168275220 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000010 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.000010 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000044 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.000044 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.000025 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.000025 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.000025 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.000025 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50827.368421 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 50827.368421 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55212.991880 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 55212.991880 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 54209.537572 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 54209.537572 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 54209.537572 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 54209.537572 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 649 # number of writebacks
system.cpu.dcache.writebacks::total 649 # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 950 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 950 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3202 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 3202 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 4152 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 4152 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 4152 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 4152 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 45436000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 45436000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 167186000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 167186000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 212622000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 212622000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 212622000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 212622000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000044 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47827.368421 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47827.368421 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52212.991880 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52212.991880 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51209.537572 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 51209.537572 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51209.537572 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 51209.537572 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 13 # number of replacements
system.cpu.l2cache.tagsinuse 3768.712262 # Cycle average of tags in use
system.cpu.l2cache.total_refs 656 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 4572 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.143482 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 371.536808 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 2770.454482 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 626.720973 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.011338 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.084548 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.019126 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.115012 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 468 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 117 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 585 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 649 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 649 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 60 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 60 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst 468 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 177 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 645 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 468 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 177 # number of overall hits
system.cpu.l2cache.overall_hits::total 645 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 3205 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 833 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 4038 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 3142 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 3142 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 3205 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 3975 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 7180 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 3205 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 3975 # number of overall misses
system.cpu.l2cache.overall_misses::total 7180 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 166660000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 43316000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 209976000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 163384000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 163384000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 166660000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 206700000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 373360000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 166660000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 206700000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 373360000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 3673 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 950 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 4623 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 649 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 649 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 3202 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 3202 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 3673 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 4152 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 7825 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 3673 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 4152 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 7825 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.872584 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.876842 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.873459 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.981262 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.981262 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.872584 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.957370 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.917572 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.872584 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.957370 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.917572 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3205 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 833 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 4038 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3142 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 3142 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 3205 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 3975 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 7180 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3205 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 3975 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 7180 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 128200000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 33320000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 161520000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 125680000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 125680000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 128200000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 159000000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 287200000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 128200000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 159000000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 287200000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.872584 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.876842 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.873459 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.981262 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.981262 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.872584 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.957370 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.917572 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.872584 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.957370 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.917572 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

547
simulators/gem5/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini Normal file
View File

@ -0,0 +1,547 @@
[root]
type=Root
children=system
full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
boot_osflags=a
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
readfile=
symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.cpu]
type=DerivO3CPU
children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
LSQDepCheckShift=4
RASSize=16
SQEntries=32
SSITSize=1024
activity=0
backComSize=5
cachePorts=200
checker=Null
choiceCtrBits=2
choicePredictorSize=8192
clock=500
commitToDecodeDelay=1
commitToFetchDelay=1
commitToIEWDelay=1
commitToRenameDelay=1
commitWidth=8
cpu_id=0
decodeToFetchDelay=1
decodeToRenameDelay=1
decodeWidth=8
defer_registration=false
dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
fetchToDecodeDelay=1
fetchTrapLatency=1
fetchWidth=8
forwardComSize=5
fuPool=system.cpu.fuPool
function_trace=false
function_trace_start=0
globalCtrBits=2
globalHistoryBits=13
globalPredictorSize=8192
iewToCommitDelay=1
iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
instShiftAmt=2
interrupts=system.cpu.interrupts
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
localCtrBits=2
localHistoryBits=11
localHistoryTableSize=2048
localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
needsTSO=false
numIQEntries=64
numPhysFloatRegs=256
numPhysIntRegs=256
numROBEntries=192
numRobs=1
numThreads=1
phase=0
predType=tournament
profile=0
progress_interval=0
renameToDecodeDelay=1
renameToFetchDelay=1
renameToIEWDelay=2
renameToROBDelay=1
renameWidth=8
smtCommitPolicy=RoundRobin
smtFetchPolicy=SingleThread
smtIQPolicy=Partitioned
smtIQThreshold=100
smtLSQPolicy=Partitioned
smtLSQThreshold=100
smtNumFetchingThreads=1
smtROBPolicy=Partitioned
smtROBThreshold=100
squashWidth=8
store_set_clear_period=250000
system=system
tracer=system.cpu.tracer
trapLatency=13
wbDepth=1
wbWidth=8
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=262144
subblock_size=0
system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
[system.cpu.dtb]
type=ArmTLB
children=walker
size=64
walker=system.cpu.dtb.walker
[system.cpu.dtb.walker]
type=ArmTableWalker
max_backoff=100000
min_backoff=0
sys=system
port=system.cpu.toL2Bus.slave[3]
[system.cpu.fuPool]
type=FUPool
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
[system.cpu.fuPool.FUList0]
type=FUDesc
children=opList
count=6
opList=system.cpu.fuPool.FUList0.opList
[system.cpu.fuPool.FUList0.opList]
type=OpDesc
issueLat=1
opClass=IntAlu
opLat=1
[system.cpu.fuPool.FUList1]
type=FUDesc
children=opList0 opList1
count=2
opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
[system.cpu.fuPool.FUList1.opList0]
type=OpDesc
issueLat=1
opClass=IntMult
opLat=3
[system.cpu.fuPool.FUList1.opList1]
type=OpDesc
issueLat=19
opClass=IntDiv
opLat=20
[system.cpu.fuPool.FUList2]
type=FUDesc
children=opList0 opList1 opList2
count=4
opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
[system.cpu.fuPool.FUList2.opList0]
type=OpDesc
issueLat=1
opClass=FloatAdd
opLat=2
[system.cpu.fuPool.FUList2.opList1]
type=OpDesc
issueLat=1
opClass=FloatCmp
opLat=2
[system.cpu.fuPool.FUList2.opList2]
type=OpDesc
issueLat=1
opClass=FloatCvt
opLat=2
[system.cpu.fuPool.FUList3]
type=FUDesc
children=opList0 opList1 opList2
count=2
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
[system.cpu.fuPool.FUList3.opList0]
type=OpDesc
issueLat=1
opClass=FloatMult
opLat=4
[system.cpu.fuPool.FUList3.opList1]
type=OpDesc
issueLat=12
opClass=FloatDiv
opLat=12
[system.cpu.fuPool.FUList3.opList2]
type=OpDesc
issueLat=24
opClass=FloatSqrt
opLat=24
[system.cpu.fuPool.FUList4]
type=FUDesc
children=opList
count=0
opList=system.cpu.fuPool.FUList4.opList
[system.cpu.fuPool.FUList4.opList]
type=OpDesc
issueLat=1
opClass=MemRead
opLat=1
[system.cpu.fuPool.FUList5]
type=FUDesc
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
count=4
opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
[system.cpu.fuPool.FUList5.opList00]
type=OpDesc
issueLat=1
opClass=SimdAdd
opLat=1
[system.cpu.fuPool.FUList5.opList01]
type=OpDesc
issueLat=1
opClass=SimdAddAcc
opLat=1
[system.cpu.fuPool.FUList5.opList02]
type=OpDesc
issueLat=1
opClass=SimdAlu
opLat=1
[system.cpu.fuPool.FUList5.opList03]
type=OpDesc
issueLat=1
opClass=SimdCmp
opLat=1
[system.cpu.fuPool.FUList5.opList04]
type=OpDesc
issueLat=1
opClass=SimdCvt
opLat=1
[system.cpu.fuPool.FUList5.opList05]
type=OpDesc
issueLat=1
opClass=SimdMisc
opLat=1
[system.cpu.fuPool.FUList5.opList06]
type=OpDesc
issueLat=1
opClass=SimdMult
opLat=1
[system.cpu.fuPool.FUList5.opList07]
type=OpDesc
issueLat=1
opClass=SimdMultAcc
opLat=1
[system.cpu.fuPool.FUList5.opList08]
type=OpDesc
issueLat=1
opClass=SimdShift
opLat=1
[system.cpu.fuPool.FUList5.opList09]
type=OpDesc
issueLat=1
opClass=SimdShiftAcc
opLat=1
[system.cpu.fuPool.FUList5.opList10]
type=OpDesc
issueLat=1
opClass=SimdSqrt
opLat=1
[system.cpu.fuPool.FUList5.opList11]
type=OpDesc
issueLat=1
opClass=SimdFloatAdd
opLat=1
[system.cpu.fuPool.FUList5.opList12]
type=OpDesc
issueLat=1
opClass=SimdFloatAlu
opLat=1
[system.cpu.fuPool.FUList5.opList13]
type=OpDesc
issueLat=1
opClass=SimdFloatCmp
opLat=1
[system.cpu.fuPool.FUList5.opList14]
type=OpDesc
issueLat=1
opClass=SimdFloatCvt
opLat=1
[system.cpu.fuPool.FUList5.opList15]
type=OpDesc
issueLat=1
opClass=SimdFloatDiv
opLat=1
[system.cpu.fuPool.FUList5.opList16]
type=OpDesc
issueLat=1
opClass=SimdFloatMisc
opLat=1
[system.cpu.fuPool.FUList5.opList17]
type=OpDesc
issueLat=1
opClass=SimdFloatMult
opLat=1
[system.cpu.fuPool.FUList5.opList18]
type=OpDesc
issueLat=1
opClass=SimdFloatMultAcc
opLat=1
[system.cpu.fuPool.FUList5.opList19]
type=OpDesc
issueLat=1
opClass=SimdFloatSqrt
opLat=1
[system.cpu.fuPool.FUList6]
type=FUDesc
children=opList
count=0
opList=system.cpu.fuPool.FUList6.opList
[system.cpu.fuPool.FUList6.opList]
type=OpDesc
issueLat=1
opClass=MemWrite
opLat=1
[system.cpu.fuPool.FUList7]
type=FUDesc
children=opList0 opList1
count=4
opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
[system.cpu.fuPool.FUList7.opList0]
type=OpDesc
issueLat=1
opClass=MemRead
opLat=1
[system.cpu.fuPool.FUList7.opList1]
type=OpDesc
issueLat=1
opClass=MemWrite
opLat=1
[system.cpu.fuPool.FUList8]
type=FUDesc
children=opList
count=1
opList=system.cpu.fuPool.FUList8.opList
[system.cpu.fuPool.FUList8.opList]
type=OpDesc
issueLat=3
opClass=IprAccess
opLat=3
[system.cpu.icache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=131072
subblock_size=0
system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.interrupts]
type=ArmInterrupts
[system.cpu.itb]
type=ArmTLB
children=walker
size=64
walker=system.cpu.itb.walker
[system.cpu.itb.walker]
type=ArmTableWalker
max_backoff=100000
min_backoff=0
sys=system
port=system.cpu.toL2Bus.slave[2]
[system.cpu.l2cache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=false
latency=1000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=2097152
subblock_size=0
system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
[system.cpu.toL2Bus]
type=CoherentBus
block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
cwd=build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing
egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/cpu2000/binaries/arm/linux/eon
gid=100
input=cin
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=0
system=system
uid=100
[system.membus]
type=CoherentBus
block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
master=system.physmem.port[0]
slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=SimpleMemory
conf_table_reported=false
file=
in_addr_map=true
latency=30000
latency_var=0
null=false
range=0:134217727
zero=false
port=system.membus.master[0]

48
simulators/gem5/tests/long/se/30.eon/ref/arm/linux/o3-timing/simerr Executable file
View File

@ -0,0 +1,48 @@
warn: Sockets disabled, not accepting gdb connections
getting pixel output filename pixels_out.cook
opening control file chair.control.cook
opening camera file chair.camera
opening surfaces file chair.surfaces
reading data
processing 8parts
Grid measure is 6 by 3.0001 by 6
cell dimension is 0.863065
Creating grid for list of length 21
Grid size = 7 by 4 by 7
Total occupancy = 236
reading control stream
reading camera stream
Writing to chair.cook.ppm
calculating 15 by 15 image with 196 samples
col 0. . .
col 1. . .
col 2. . .
col 3. . .
col 4. . .
col 5. . .
col 6. . .
col 7. . .
col 8. . .
col 9. . .
col 10. . .
col 11. . .
col 12. . .
col 13. . .
col 14. . .
Writing to chair.cook.ppm
0 8 14
1 8 14
2 8 14
3 8 14
4 8 14
5 8 14
6 8 14
7 8 14
8 8 14
9 8 14
10 8 14
11 8 14
12 8 14
13 8 14
14 8 14
hack: be nice to actually delete the event here

16
simulators/gem5/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout Executable file
View File

@ -0,0 +1,16 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 4 2012 12:14:06
gem5 started Jun 4 2012 17:54:41
gem5 executing on zizzer
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Eon, Version 1.1
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
OO-style eon Time= 0.070000
Exiting @ tick 71774859500 because target called exit()

714
simulators/gem5/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt Normal file
View File

@ -0,0 +1,714 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.071775 # Number of seconds simulated
sim_ticks 71774859500 # Number of ticks simulated
final_tick 71774859500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 120484 # Simulator instruction rate (inst/s)
host_op_rate 154032 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 31671128 # Simulator tick rate (ticks/s)
host_mem_usage 240520 # Number of bytes of host memory used
host_seconds 2266.26 # Real time elapsed on the host
sim_insts 273048474 # Number of instructions simulated
sim_ops 349076199 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 199168 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 273728 # Number of bytes read from this memory
system.physmem.bytes_read::total 472896 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 199168 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 199168 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 3112 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 4277 # Number of read requests responded to by this memory
system.physmem.num_reads::total 7389 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 2774899 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 3813703 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 6588602 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 2774899 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 2774899 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 2774899 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 3813703 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 6588602 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 191 # Number of system calls
system.cpu.numCycles 143549720 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.BPredUnit.lookups 37175542 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 22262323 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 2214096 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 22505770 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 18082192 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 7072101 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 52600 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 41561697 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 332366381 # Number of instructions fetch has processed
system.cpu.fetch.Branches 37175542 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 25154293 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 74569841 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 8920940 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 20643175 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 124 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 4492 # Number of stall cycles due to pending traps
system.cpu.fetch.CacheLines 39951299 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 710527 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 143433675 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.978110 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.454958 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 69560380 48.50% 48.50% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 7529870 5.25% 53.75% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 5927266 4.13% 57.88% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 6353418 4.43% 62.31% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 5053258 3.52% 65.83% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 4245115 2.96% 68.79% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 3249040 2.27% 71.06% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 4338891 3.03% 74.08% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 37176437 25.92% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 143433675 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.258973 # Number of branch fetches per cycle
system.cpu.fetch.rate 2.315340 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 48398038 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 15922899 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 70106313 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 2422163 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 6584262 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 7647961 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 70686 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 419107715 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 208401 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 6584262 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 54237445 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 1551128 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 362766 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 66624532 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 14073542 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 408263314 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 21 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 1648402 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 10108765 # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents 752 # Number of times there has been no free registers
system.cpu.rename.RenamedOperands 447190592 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 2407780645 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 1318183800 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 1089596845 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 384584999 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 62605593 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 23936 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 23899 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 35817763 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 106133186 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 93562284 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 4587440 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 5646194 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 394242574 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 33887 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 379407553 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 1341475 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 44167400 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 116755410 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 9405 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 143433675 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 2.645178 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 2.047092 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 29947758 20.88% 20.88% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 20633542 14.39% 35.26% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 21077069 14.69% 49.96% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 18246072 12.72% 62.68% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 24216587 16.88% 79.56% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 16050569 11.19% 90.75% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 9012327 6.28% 97.04% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 3309506 2.31% 99.34% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 940245 0.66% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 143433675 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 9527 0.05% 0.05% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 4696 0.03% 0.08% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 0.08% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.08% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.08% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.08% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 0.08% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.08% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.08% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.08% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.08% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.08% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.08% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.08% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.08% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 0.08% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.08% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 0.08% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.08% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.08% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 47773 0.27% 0.34% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.34% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 7824 0.04% 0.39% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 381 0.00% 0.39% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 3 0.00% 0.39% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 194196 1.08% 1.47% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 4065 0.02% 1.49% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 241389 1.34% 2.83% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.83% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 9461548 52.57% 55.40% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 8027461 44.60% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 129140993 34.04% 34.04% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 2178888 0.57% 34.61% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 34.61% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 34.61% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 34.61% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 34.61% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 34.61% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 34.61% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 34.61% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 34.61% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 34.61% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 34.61% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 3 0.00% 34.61% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 34.61% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 34.61% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 34.61% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 34.61% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 34.61% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 34.61% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 34.61% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 6841737 1.80% 36.42% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 36.42% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 8706483 2.29% 38.71% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 3462240 0.91% 39.62% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 1609824 0.42% 40.05% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 21270001 5.61% 45.65% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 7182346 1.89% 47.55% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 7142588 1.88% 49.43% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 175287 0.05% 49.47% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 102963295 27.14% 76.61% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 88733868 23.39% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 379407553 # Type of FU issued
system.cpu.iq.rate 2.643039 # Inst issue rate
system.cpu.iq.fu_busy_cnt 17998863 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.047439 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 670841771 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 305961612 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 253223434 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 250747348 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 132496015 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 118776381 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 268120952 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 129285464 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 10792483 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 11482088 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 116027 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 13932 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 11184344 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 9709 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 181 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 6584262 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 34186 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 1479 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 394326849 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 1347232 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 106133186 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 93562284 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 22722 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 192 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 169 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 13932 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 1780753 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 562062 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 2342815 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 374477920 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 101438803 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 4929633 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 50388 # number of nop insts executed
system.cpu.iew.exec_refs 188856020 # number of memory reference insts executed
system.cpu.iew.exec_branches 32491949 # Number of branches executed
system.cpu.iew.exec_stores 87417217 # Number of stores executed
system.cpu.iew.exec_rate 2.608698 # Inst execution rate
system.cpu.iew.wb_sent 372876985 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 371999815 # cumulative count of insts written-back
system.cpu.iew.wb_producers 185166823 # num instructions producing a value
system.cpu.iew.wb_consumers 368327153 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 2.591435 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.502724 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitCommittedInsts 273049086 # The number of committed instructions
system.cpu.commit.commitCommittedOps 349076811 # The number of committed instructions
system.cpu.commit.commitSquashedInsts 45250302 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 24482 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 2186131 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 136849414 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 2.550810 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.650371 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 39364225 28.76% 28.76% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 29162916 21.31% 50.07% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 13605145 9.94% 60.02% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 11228015 8.20% 68.22% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 13810148 10.09% 78.31% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 7236976 5.29% 83.60% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 4020101 2.94% 86.54% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 3901622 2.85% 89.39% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 14520266 10.61% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 136849414 # Number of insts commited each cycle
system.cpu.commit.committedInsts 273049086 # Number of instructions committed
system.cpu.commit.committedOps 349076811 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 177029038 # Number of memory references committed
system.cpu.commit.loads 94651098 # Number of loads committed
system.cpu.commit.membars 11033 # Number of memory barriers committed
system.cpu.commit.branches 30523993 # Number of branches committed
system.cpu.commit.fp_insts 114216705 # Number of committed floating point instructions.
system.cpu.commit.int_insts 279594011 # Number of committed integer instructions.
system.cpu.commit.function_calls 6225112 # Number of function calls committed.
system.cpu.commit.bw_lim_events 14520266 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 516653738 # The number of ROB reads
system.cpu.rob.rob_writes 795243409 # The number of ROB writes
system.cpu.timesIdled 2720 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 116045 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 273048474 # Number of Instructions Simulated
system.cpu.committedOps 349076199 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 273048474 # Number of Instructions Simulated
system.cpu.cpi 0.525730 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.525730 # CPI: Total CPI of All Threads
system.cpu.ipc 1.902118 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.902118 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 1788157543 # number of integer regfile reads
system.cpu.int_regfile_writes 236964047 # number of integer regfile writes
system.cpu.fp_regfile_reads 189767378 # number of floating regfile reads
system.cpu.fp_regfile_writes 133494852 # number of floating regfile writes
system.cpu.misc_regfile_reads 995239791 # number of misc regfile reads
system.cpu.misc_regfile_writes 34426479 # number of misc regfile writes
system.cpu.icache.replacements 14190 # number of replacements
system.cpu.icache.tagsinuse 1864.933817 # Cycle average of tags in use
system.cpu.icache.total_refs 39934285 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 16092 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 2481.623478 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 1864.933817 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.910612 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.910612 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 39934285 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 39934285 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 39934285 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 39934285 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 39934285 # number of overall hits
system.cpu.icache.overall_hits::total 39934285 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 17014 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 17014 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 17014 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 17014 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 17014 # number of overall misses
system.cpu.icache.overall_misses::total 17014 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 211050500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 211050500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 211050500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 211050500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 211050500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 211050500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 39951299 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 39951299 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 39951299 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 39951299 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 39951299 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 39951299 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000426 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000426 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000426 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000426 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000426 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000426 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 12404.519807 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 12404.519807 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 12404.519807 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 12404.519807 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 12404.519807 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 12404.519807 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 900 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 900 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 900 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 900 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 900 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 900 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 16114 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 16114 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 16114 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 16114 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 16114 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 16114 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 139714000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 139714000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 139714000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 139714000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 139714000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 139714000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000403 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000403 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000403 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000403 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000403 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000403 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 8670.348765 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 8670.348765 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 8670.348765 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 8670.348765 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 8670.348765 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 8670.348765 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 1427 # number of replacements
system.cpu.dcache.tagsinuse 3127.647604 # Cycle average of tags in use
system.cpu.dcache.total_refs 172501472 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 4641 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 37169.030812 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 3127.647604 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.763586 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.763586 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 90441052 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 90441052 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 82033132 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 82033132 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 14008 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 14008 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 13257 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 13257 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 172474184 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 172474184 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 172474184 # number of overall hits
system.cpu.dcache.overall_hits::total 172474184 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 3598 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 3598 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 19528 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 19528 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data 23126 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 23126 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 23126 # number of overall misses
system.cpu.dcache.overall_misses::total 23126 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 115634000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 115634000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 650274000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 650274000 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 76000 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 76000 # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 765908000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 765908000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 765908000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 765908000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 90444650 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 90444650 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 82052660 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 82052660 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 14010 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 14010 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 13257 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 13257 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 172497310 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 172497310 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 172497310 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 172497310 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000040 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.000040 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000238 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.000238 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000143 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000143 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.000134 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.000134 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.000134 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.000134 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32138.410228 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 32138.410228 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33299.569848 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 33299.569848 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 38000 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 38000 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 33118.913777 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 33118.913777 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 33118.913777 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 33118.913777 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 315000 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 13 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 24230.769231 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 1038 # number of writebacks
system.cpu.dcache.writebacks::total 1038 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1792 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 1792 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16671 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 16671 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 18463 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 18463 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 18463 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 18463 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1806 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 1806 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2857 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 2857 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 4663 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 4663 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 4663 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 4663 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 54896500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 54896500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 101557000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 101557000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 156453500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 156453500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 156453500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 156453500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000020 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000020 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000035 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 30396.733112 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30396.733112 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35546.727336 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35546.727336 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 33552.112374 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 33552.112374 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 33552.112374 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 33552.112374 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 69 # number of replacements
system.cpu.l2cache.tagsinuse 4034.301662 # Cycle average of tags in use
system.cpu.l2cache.total_refs 13357 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 5499 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 2.428987 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 380.580872 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 2851.587465 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 802.133324 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.011614 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.087024 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.024479 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.123117 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 12970 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 298 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 13268 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 1038 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 1038 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 17 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 17 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst 12970 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 315 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 13285 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 12970 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 315 # number of overall hits
system.cpu.l2cache.overall_hits::total 13285 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 3122 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 1507 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 4629 # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data 22 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total 22 # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 2819 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 2819 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 3122 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 4326 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 7448 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 3122 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 4326 # number of overall misses
system.cpu.l2cache.overall_misses::total 7448 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 106982000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 51758500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 158740500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 97188000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 97188000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 106982000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 148946500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 255928500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 106982000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 148946500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 255928500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 16092 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 1805 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 17897 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 1038 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 1038 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 22 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total 22 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 2836 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 2836 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 16092 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 4641 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 20733 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 16092 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 4641 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 20733 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.194009 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.834903 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.258647 # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.994006 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.994006 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.194009 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.932127 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.359234 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.194009 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.932127 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.359234 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34267.136451 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34345.388188 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 34292.611795 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34476.055339 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34476.055339 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34267.136451 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34430.536292 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 34362.043502 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34267.136451 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34430.536292 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 34362.043502 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 10 # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 49 # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total 59 # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst 10 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data 49 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total 59 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst 10 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data 49 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total 59 # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3112 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1458 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 4570 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 22 # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total 22 # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 2819 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 2819 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 3112 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 4277 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 7389 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3112 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 4277 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 7389 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 96743500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 45668000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 142411500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 682000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 682000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 88208000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 88208000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 96743500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 133876000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 230619500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 96743500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 133876000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 230619500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.193388 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.807756 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.255350 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994006 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994006 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.193388 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.921569 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.356388 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.193388 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.921569 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.356388 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31087.242931 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31322.359396 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31162.253829 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31000 # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31290.528556 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31290.528556 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31087.242931 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31301.379472 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31211.192313 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31087.242931 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31301.379472 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31211.192313 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

135
simulators/gem5/tests/long/se/30.eon/ref/arm/linux/simple-atomic/config.ini Normal file
View File

@ -0,0 +1,135 @@
[root]
type=Root
children=system
full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
boot_osflags=a
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
readfile=
symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.cpu]
type=AtomicSimpleCPU
children=dtb interrupts itb tracer workload
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
fastmem=false
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
phase=0
profile=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
system=system
tracer=system.cpu.tracer
width=1
workload=system.cpu.workload
dcache_port=system.membus.slave[2]
icache_port=system.membus.slave[1]
[system.cpu.dtb]
type=ArmTLB
children=walker
size=64
walker=system.cpu.dtb.walker
[system.cpu.dtb.walker]
type=ArmTableWalker
max_backoff=100000
min_backoff=0
sys=system
port=system.membus.slave[4]
[system.cpu.interrupts]
type=ArmInterrupts
[system.cpu.itb]
type=ArmTLB
children=walker
size=64
walker=system.cpu.itb.walker
[system.cpu.itb.walker]
type=ArmTableWalker
max_backoff=100000
min_backoff=0
sys=system
port=system.membus.slave[3]
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
cwd=build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-atomic
egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/cpu2000/binaries/arm/linux/eon
gid=100
input=cin
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=0
system=system
uid=100
[system.membus]
type=CoherentBus
block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
master=system.physmem.port[0]
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port
[system.physmem]
type=SimpleMemory
conf_table_reported=false
file=
in_addr_map=true
latency=30000
latency_var=0
null=false
range=0:134217727
zero=false
port=system.membus.master[0]

48
simulators/gem5/tests/long/se/30.eon/ref/arm/linux/simple-atomic/simerr Executable file
View File

@ -0,0 +1,48 @@
warn: Sockets disabled, not accepting gdb connections
getting pixel output filename pixels_out.cook
opening control file chair.control.cook
opening camera file chair.camera
opening surfaces file chair.surfaces
reading data
processing 8parts
Grid measure is 6 by 3.0001 by 6
cell dimension is 0.863065
Creating grid for list of length 21
Grid size = 7 by 4 by 7
Total occupancy = 236
reading control stream
reading camera stream
Writing to chair.cook.ppm
calculating 15 by 15 image with 196 samples
col 0. . .
col 1. . .
col 2. . .
col 3. . .
col 4. . .
col 5. . .
col 6. . .
col 7. . .
col 8. . .
col 9. . .
col 10. . .
col 11. . .
col 12. . .
col 13. . .
col 14. . .
Writing to chair.cook.ppm
0 8 14
1 8 14
2 8 14
3 8 14
4 8 14
5 8 14
6 8 14
7 8 14
8 8 14
9 8 14
10 8 14
11 8 14
12 8 14
13 8 14
14 8 14
hack: be nice to actually delete the event here

16
simulators/gem5/tests/long/se/30.eon/ref/arm/linux/simple-atomic/simout Executable file
View File

@ -0,0 +1,16 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 4 2012 12:14:06
gem5 started Jun 4 2012 18:01:26
gem5 executing on zizzer
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Eon, Version 1.1
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
OO-style eon Time= 0.210000
Exiting @ tick 212344048000 because target called exit()

102
simulators/gem5/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt Normal file
View File

@ -0,0 +1,102 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.212344 # Number of seconds simulated
sim_ticks 212344048000 # Number of ticks simulated
final_tick 212344048000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1586428 # Simulator instruction rate (inst/s)
host_op_rate 2028172 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1233780581 # Simulator tick rate (ticks/s)
host_mem_usage 229108 # Number of bytes of host memory used
host_seconds 172.11 # Real time elapsed on the host
sim_insts 273037671 # Number of instructions simulated
sim_ops 349065408 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 1394641440 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 480709269 # Number of bytes read from this memory
system.physmem.bytes_read::total 1875350709 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 1394641440 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 1394641440 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 400047783 # Number of bytes written to this memory
system.physmem.bytes_written::total 400047783 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 348660360 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 94582506 # Number of read requests responded to by this memory
system.physmem.num_reads::total 443242866 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 82063572 # Number of write requests responded to by this memory
system.physmem.num_writes::total 82063572 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 6567838624 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 2263822667 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 8831661291 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 6567838624 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 6567838624 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 1883960425 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 1883960425 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 6567838624 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 4147783092 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 10715621716 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 191 # Number of system calls
system.cpu.numCycles 424688097 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 273037671 # Number of instructions committed
system.cpu.committedOps 349065408 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 279584926 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 114216705 # Number of float alu accesses
system.cpu.num_func_calls 12433363 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 18087062 # number of instructions that are conditional controls
system.cpu.num_int_insts 279584926 # number of integer instructions
system.cpu.num_fp_insts 114216705 # number of float instructions
system.cpu.num_int_register_reads 1887652191 # number of times the integer registers were read
system.cpu.num_int_register_writes 251197918 # number of times the integer registers were written
system.cpu.num_fp_register_reads 180262959 # number of times the floating registers were read
system.cpu.num_fp_register_writes 126152315 # number of times the floating registers were written
system.cpu.num_mem_refs 177024357 # number of memory refs
system.cpu.num_load_insts 94648758 # Number of load instructions
system.cpu.num_store_insts 82375599 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 424688097 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
---------- End Simulation Statistics ----------

216
simulators/gem5/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini Normal file
View File

@ -0,0 +1,216 @@
[root]
type=Root
children=system
full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
boot_osflags=a
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
readfile=
symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.cpu]
type=TimingSimpleCPU
children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
phase=0
profile=0
progress_interval=0
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=262144
subblock_size=0
system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
[system.cpu.dtb]
type=ArmTLB
children=walker
size=64
walker=system.cpu.dtb.walker
[system.cpu.dtb.walker]
type=ArmTableWalker
max_backoff=100000
min_backoff=0
sys=system
port=system.cpu.toL2Bus.slave[3]
[system.cpu.icache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=131072
subblock_size=0
system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.interrupts]
type=ArmInterrupts
[system.cpu.itb]
type=ArmTLB
children=walker
size=64
walker=system.cpu.itb.walker
[system.cpu.itb.walker]
type=ArmTableWalker
max_backoff=100000
min_backoff=0
sys=system
port=system.cpu.toL2Bus.slave[2]
[system.cpu.l2cache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=false
latency=10000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=2097152
subblock_size=0
system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
[system.cpu.toL2Bus]
type=CoherentBus
block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
cwd=build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-timing
egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/cpu2000/binaries/arm/linux/eon
gid=100
input=cin
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=0
system=system
uid=100
[system.membus]
type=CoherentBus
block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
master=system.physmem.port[0]
slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=SimpleMemory
conf_table_reported=false
file=
in_addr_map=true
latency=30000
latency_var=0
null=false
range=0:134217727
zero=false
port=system.membus.master[0]

48
simulators/gem5/tests/long/se/30.eon/ref/arm/linux/simple-timing/simerr Executable file
View File

@ -0,0 +1,48 @@
warn: Sockets disabled, not accepting gdb connections
getting pixel output filename pixels_out.cook
opening control file chair.control.cook
opening camera file chair.camera
opening surfaces file chair.surfaces
reading data
processing 8parts
Grid measure is 6 by 3.0001 by 6
cell dimension is 0.863065
Creating grid for list of length 21
Grid size = 7 by 4 by 7
Total occupancy = 236
reading control stream
reading camera stream
Writing to chair.cook.ppm
calculating 15 by 15 image with 196 samples
col 0. . .
col 1. . .
col 2. . .
col 3. . .
col 4. . .
col 5. . .
col 6. . .
col 7. . .
col 8. . .
col 9. . .
col 10. . .
col 11. . .
col 12. . .
col 13. . .
col 14. . .
Writing to chair.cook.ppm
0 8 14
1 8 14
2 8 14
3 8 14
4 8 14
5 8 14
6 8 14
7 8 14
8 8 14
9 8 14
10 8 14
11 8 14
12 8 14
13 8 14
14 8 14
hack: be nice to actually delete the event here

16
simulators/gem5/tests/long/se/30.eon/ref/arm/linux/simple-timing/simout Executable file
View File

@ -0,0 +1,16 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 4 2012 12:14:06
gem5 started Jun 4 2012 18:04:29
gem5 executing on zizzer
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Eon, Version 1.1
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
OO-style eon Time= 0.520000
Exiting @ tick 525854475000 because target called exit()

418
simulators/gem5/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt Normal file
View File

@ -0,0 +1,418 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.525854 # Number of seconds simulated
sim_ticks 525854475000 # Number of ticks simulated
final_tick 525854475000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 697015 # Simulator instruction rate (inst/s)
host_op_rate 891108 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1343878935 # Simulator tick rate (ticks/s)
host_mem_usage 238268 # Number of bytes of host memory used
host_seconds 391.30 # Real time elapsed on the host
sim_insts 272739291 # Number of instructions simulated
sim_ops 348687131 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 167040 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 270272 # Number of bytes read from this memory
system.physmem.bytes_read::total 437312 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 167040 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 167040 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 2610 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 4223 # Number of read requests responded to by this memory
system.physmem.num_reads::total 6833 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 317654 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 513967 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 831622 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 317654 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 317654 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 317654 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 513967 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 831622 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 191 # Number of system calls
system.cpu.numCycles 1051708950 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 272739291 # Number of instructions committed
system.cpu.committedOps 348687131 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 279584925 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 114216705 # Number of float alu accesses
system.cpu.num_func_calls 12433363 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 18087061 # number of instructions that are conditional controls
system.cpu.num_int_insts 279584925 # number of integer instructions
system.cpu.num_fp_insts 114216705 # number of float instructions
system.cpu.num_int_register_reads 2212913209 # number of times the integer registers were read
system.cpu.num_int_register_writes 251197915 # number of times the integer registers were written
system.cpu.num_fp_register_reads 180262959 # number of times the floating registers were read
system.cpu.num_fp_register_writes 126152315 # number of times the floating registers were written
system.cpu.num_mem_refs 177024357 # number of memory refs
system.cpu.num_load_insts 94648758 # Number of load instructions
system.cpu.num_store_insts 82375599 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 1051708950 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.icache.replacements 13796 # number of replacements
system.cpu.icache.tagsinuse 1765.984158 # Cycle average of tags in use
system.cpu.icache.total_refs 348644756 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 15603 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 22344.725758 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 1765.984158 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.862297 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.862297 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 348644756 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 348644756 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 348644756 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 348644756 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 348644756 # number of overall hits
system.cpu.icache.overall_hits::total 348644756 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 15603 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 15603 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 15603 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 15603 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 15603 # number of overall misses
system.cpu.icache.overall_misses::total 15603 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 328062000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 328062000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 328062000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 328062000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 328062000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 328062000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 348660359 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 348660359 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 348660359 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 348660359 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 348660359 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 348660359 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000045 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000045 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000045 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000045 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000045 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000045 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21025.572005 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 21025.572005 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 21025.572005 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 21025.572005 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 21025.572005 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 21025.572005 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15603 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 15603 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 15603 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 15603 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 15603 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 15603 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 281253000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 281253000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 281253000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 281253000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 281253000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 281253000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000045 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000045 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000045 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18025.572005 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18025.572005 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18025.572005 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 18025.572005 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18025.572005 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 18025.572005 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 1332 # number of replacements
system.cpu.dcache.tagsinuse 3078.396238 # Cycle average of tags in use
system.cpu.dcache.total_refs 176641600 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 4478 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 39446.538633 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 3078.396238 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.751562 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.751562 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 94570005 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 94570005 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 82049805 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 82049805 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 10895 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 10895 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 176619810 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 176619810 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 176619810 # number of overall hits
system.cpu.dcache.overall_hits::total 176619810 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 1606 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 1606 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 2872 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 2872 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 4478 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 4478 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 4478 # number of overall misses
system.cpu.dcache.overall_misses::total 4478 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 79898000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 79898000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 160160000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 160160000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 240058000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 240058000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 240058000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 240058000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 94571611 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 94571611 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 82052677 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 82052677 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10895 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 10895 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 176624288 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 176624288 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 176624288 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 176624288 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000017 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.000017 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000035 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.000035 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.000025 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.000025 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.000025 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.000025 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 49749.688667 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 49749.688667 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55766.016713 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 55766.016713 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 53608.307280 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 53608.307280 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 53608.307280 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 53608.307280 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 998 # number of writebacks
system.cpu.dcache.writebacks::total 998 # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1606 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 1606 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2872 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 2872 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 4478 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 4478 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 4478 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 4478 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75080000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 75080000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 151544000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 151544000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 226624000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 226624000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 226624000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 226624000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000017 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000017 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000035 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46749.688667 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46749.688667 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52766.016713 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52766.016713 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 50608.307280 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 50608.307280 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 50608.307280 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 50608.307280 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 48 # number of replacements
system.cpu.l2cache.tagsinuse 3475.672922 # Cycle average of tags in use
system.cpu.l2cache.total_refs 13308 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 4883 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 2.725374 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 341.613272 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 2402.300580 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 731.759070 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.010425 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.073312 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.022332 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.106069 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 12993 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 239 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 13232 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 998 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 998 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 16 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 16 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst 12993 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 255 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 13248 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 12993 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 255 # number of overall hits
system.cpu.l2cache.overall_hits::total 13248 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 2610 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 1367 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 3977 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 2856 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 2856 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 2610 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 4223 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 6833 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 2610 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 4223 # number of overall misses
system.cpu.l2cache.overall_misses::total 6833 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 135720000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 71084000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 206804000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 148512000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 148512000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 135720000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 219596000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 355316000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 135720000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 219596000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 355316000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 15603 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 1606 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 17209 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 998 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 998 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 2872 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 2872 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 15603 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 4478 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 20081 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 15603 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 4478 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 20081 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.167276 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.851183 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.231100 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.994429 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.994429 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.167276 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.943055 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.340272 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.167276 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.943055 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.340272 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2610 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1367 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 3977 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 2856 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 2856 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 2610 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 4223 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 6833 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2610 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 4223 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 6833 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 104400000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 54680000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 159080000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 114240000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 114240000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 104400000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 168920000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 273320000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 104400000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 168920000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 273320000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.167276 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.851183 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.231100 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994429 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994429 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.167276 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.943055 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.340272 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.167276 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.943055 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.340272 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------