Adding gem5 source to svn.
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1819 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
This commit is contained in:
friemel
@ -0,0 +1,6 @@
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I removed the reference outputs for this program because it's taking
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way too long... over an hour for simple-atomic and over 19 hrs for
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o3-timing. We need to find a shorter input if we want to keep this
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||||
in the regressions.
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||||
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||||
Steve
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||||
@ -0,0 +1,547 @@
|
||||
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|
||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
|
||||
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|
||||
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||||
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||||
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|
||||
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||||
|
||||
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|
||||
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||||
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|
||||
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|
||||
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||||
|
||||
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|
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||||
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|
||||
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|
||||
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
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|
||||
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|
||||
|
||||
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|
||||
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|
||||
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
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|
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|
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|
||||
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|
||||
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|
||||
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|
||||
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|
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|
||||
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|
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|
||||
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|
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|
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|
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|
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|
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|
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|
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|
||||
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|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
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|
||||
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|
||||
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|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
master=system.cpu.l2cache.cpu_side
|
||||
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
|
||||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
|
||||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=parser 2.1.dict -batch
|
||||
cwd=build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/cpu2000/binaries/arm/linux/parser
|
||||
gid=100
|
||||
input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
ppid=99
|
||||
simpoint=114600000000
|
||||
system=system
|
||||
uid=100
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
master=system.physmem.port[0]
|
||||
slave=system.system_port system.cpu.l2cache.mem_side
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.membus.master[0]
|
||||
|
||||
3
simulators/gem5/tests/long/se/20.parser/ref/arm/linux/o3-timing/simerr
Executable file
3
simulators/gem5/tests/long/se/20.parser/ref/arm/linux/o3-timing/simerr
Executable file
@ -0,0 +1,3 @@
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: CP14 unimplemented crn[8], opc1[2], crm[9], opc2[4]
|
||||
hack: be nice to actually delete the event here
|
||||
70
simulators/gem5/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout
Executable file
70
simulators/gem5/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout
Executable file
@ -0,0 +1,70 @@
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jun 4 2012 12:14:06
|
||||
gem5 started Jun 4 2012 17:38:42
|
||||
gem5 executing on zizzer
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
||||
Reading the dictionary files: *************************************************
|
||||
|
||||
|
||||
Welcome to the Link Parser -- Version 2.1
|
||||
|
||||
Copyright (C) 1991-1995 Daniel Sleator and Davy Temperley
|
||||
|
||||
Processing sentences in batch mode
|
||||
|
||||
info: Increasing stack size by one page.
|
||||
Echoing of input sentence turned on.
|
||||
* as had expected the party to be a success , it was a success
|
||||
* do you know where John 's
|
||||
* he said that , finding that it was impossible to get work as a waiter , he would work as a janitor
|
||||
info: Increasing stack size by one page.
|
||||
* how fast the program is it
|
||||
* I am wondering whether to invite to the party
|
||||
* I gave him for his birthday it
|
||||
* I thought terrible after our discussion
|
||||
* I wonder how much money have you earned
|
||||
* Janet who is an expert on dogs helped me choose one
|
||||
* she interviewed more programmers than was hired
|
||||
* such flowers are found chiefly particularly in Europe
|
||||
* the dogs some of which were very large ran after the man
|
||||
* the man whom I play tennis is here
|
||||
* there is going to be an important meeting January
|
||||
* to pretend that our program is usable in its current form would be happy
|
||||
* we're thinking about going to a movie this theater
|
||||
* which dog you said you chased
|
||||
- also invited to the meeting were several prominent scientists
|
||||
- he ran home so quickly that his mother could hardly believe he had called from school
|
||||
- so many people attended that they spilled over into several neighboring fields
|
||||
- voting in favor of the bill were 36 Republicans and 4 moderate Democrats
|
||||
: Grace may not be possible to fix the problem
|
||||
any program as good as ours should be useful
|
||||
biochemically , I think the experiment has a lot of problems
|
||||
Fred has had five years of experience as a programmer
|
||||
he is looking for another job
|
||||
how did John do it
|
||||
how many more people do you think will come
|
||||
how much more spilled
|
||||
I have more money than John has time
|
||||
I made it clear that I was angry
|
||||
I wonder how John did it
|
||||
I wonder how much more quickly he ran
|
||||
invite John and whoever else you want to invite
|
||||
it is easier to ignore the problem than it is to solve it
|
||||
many who initially supported Thomas later changed their minds
|
||||
neither Mary nor Louise are coming to the party
|
||||
she interviewed more programmers than were hired
|
||||
telling Joe that Sue was coming to the party would create a real problem
|
||||
the man with whom I play tennis is here
|
||||
there is a dog in the park
|
||||
this is not the man we know and love
|
||||
we like to eat at restaurants , usually on weekends
|
||||
what did John say he thought you should do
|
||||
about 2 million people attended
|
||||
the five best costumes got prizes
|
||||
No errors!
|
||||
Exiting @ tick 233057542500 because target called exit()
|
||||
@ -0,0 +1,730 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.233058 # Number of seconds simulated
|
||||
sim_ticks 233057542500 # Number of ticks simulated
|
||||
final_tick 233057542500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 102553 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 115527 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 46960535 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 237172 # Number of bytes of host memory used
|
||||
host_seconds 4962.84 # Real time elapsed on the host
|
||||
sim_insts 508954936 # Number of instructions simulated
|
||||
sim_ops 573341497 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 246208 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 14967936 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 15214144 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 246208 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 246208 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 10947904 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 10947904 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 3847 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 233874 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 237721 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 171061 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 171061 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 1056426 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 64224208 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 65280633 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 1056426 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 1056426 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 46975111 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 46975111 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 46975111 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 1056426 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 64224208 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 112255745 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.dtb.read_hits 0 # DTB read hits
|
||||
system.cpu.dtb.read_misses 0 # DTB read misses
|
||||
system.cpu.dtb.write_hits 0 # DTB write hits
|
||||
system.cpu.dtb.write_misses 0 # DTB write misses
|
||||
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
|
||||
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||||
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
|
||||
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.dtb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.dtb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
|
||||
system.cpu.dtb.hits 0 # DTB hits
|
||||
system.cpu.dtb.misses 0 # DTB misses
|
||||
system.cpu.dtb.accesses 0 # DTB accesses
|
||||
system.cpu.itb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.itb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.write_hits 0 # DTB write hits
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
|
||||
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||||
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
|
||||
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.itb.inst_accesses 0 # ITB inst accesses
|
||||
system.cpu.itb.hits 0 # DTB hits
|
||||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 548 # Number of system calls
|
||||
system.cpu.numCycles 466115086 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.BPredUnit.lookups 200399400 # Number of BP lookups
|
||||
system.cpu.BPredUnit.condPredicted 157559949 # Number of conditional branches predicted
|
||||
system.cpu.BPredUnit.condIncorrect 13227368 # Number of conditional branches incorrect
|
||||
system.cpu.BPredUnit.BTBLookups 107557824 # Number of BTB lookups
|
||||
system.cpu.BPredUnit.BTBHits 98829929 # Number of BTB hits
|
||||
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu.BPredUnit.usedRAS 10084316 # Number of times the RAS was used to get a target.
|
||||
system.cpu.BPredUnit.RASInCorrect 2451057 # Number of incorrect RAS predictions.
|
||||
system.cpu.fetch.icacheStallCycles 137234241 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.Insts 896616118 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.Branches 200399400 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.predictedBranches 108914245 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.Cycles 197636410 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.SquashCycles 54052361 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.BlockedCycles 88992455 # Number of cycles fetch has spent blocked
|
||||
system.cpu.fetch.MiscStallCycles 124 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
||||
system.cpu.fetch.PendingTrapStallCycles 1657 # Number of stall cycles due to pending traps
|
||||
system.cpu.fetch.CacheLines 126860220 # Number of cache lines fetched
|
||||
system.cpu.fetch.IcacheSquashes 3882835 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.rateDist::samples 462293499 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 2.263975 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 3.101557 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 264670388 57.25% 57.25% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 16165090 3.50% 60.75% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 21531844 4.66% 65.41% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 22983454 4.97% 70.38% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 24508471 5.30% 75.68% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 13134616 2.84% 78.52% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 13371052 2.89% 81.41% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 12920313 2.79% 84.21% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 73008271 15.79% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::total 462293499 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.branchRate 0.429935 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.rate 1.923594 # Number of inst fetches per cycle
|
||||
system.cpu.decode.IdleCycles 152295850 # Number of cycles decode is idle
|
||||
system.cpu.decode.BlockedCycles 84600682 # Number of cycles decode is blocked
|
||||
system.cpu.decode.RunCycles 182545472 # Number of cycles decode is running
|
||||
system.cpu.decode.UnblockCycles 4580461 # Number of cycles decode is unblocking
|
||||
system.cpu.decode.SquashCycles 38271034 # Number of cycles decode is squashing
|
||||
system.cpu.decode.BranchResolved 32275508 # Number of times decode resolved a branch
|
||||
system.cpu.decode.BranchMispred 160463 # Number of times decode detected a branch misprediction
|
||||
system.cpu.decode.DecodedInsts 977106792 # Number of instructions handled by decode
|
||||
system.cpu.decode.SquashedInsts 311018 # Number of squashed instructions handled by decode
|
||||
system.cpu.rename.SquashCycles 38271034 # Number of cycles rename is squashing
|
||||
system.cpu.rename.IdleCycles 165689191 # Number of cycles rename is idle
|
||||
system.cpu.rename.BlockCycles 6700759 # Number of cycles rename is blocking
|
||||
system.cpu.rename.serializeStallCycles 64642468 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RunCycles 173582675 # Number of cycles rename is running
|
||||
system.cpu.rename.UnblockCycles 13407372 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RenamedInsts 899108485 # Number of instructions processed by rename
|
||||
system.cpu.rename.ROBFullEvents 1442 # Number of times rename has blocked due to ROB full
|
||||
system.cpu.rename.IQFullEvents 2810546 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.LSQFullEvents 7739563 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.FullRegisterEvents 106 # Number of times there has been no free registers
|
||||
system.cpu.rename.RenamedOperands 1049429059 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RenameLookups 3915911188 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.int_rename_lookups 3915906253 # Number of integer rename lookups
|
||||
system.cpu.rename.fp_rename_lookups 4935 # Number of floating rename lookups
|
||||
system.cpu.rename.CommittedMaps 672199832 # Number of HB maps that are committed
|
||||
system.cpu.rename.UndoneMaps 377229227 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.serializingInsts 5987863 # count of serializing insts renamed
|
||||
system.cpu.rename.tempSerializingInsts 5982547 # count of temporary serializing insts renamed
|
||||
system.cpu.rename.skidInsts 72814411 # count of insts added to the skid buffer
|
||||
system.cpu.memDep0.insertedLoads 187298810 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 75062120 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.conflictingLoads 17028922 # Number of conflicting loads.
|
||||
system.cpu.memDep0.conflictingStores 10874751 # Number of conflicting stores.
|
||||
system.cpu.iq.iqInstsAdded 806565254 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqNonSpecInstsAdded 6815793 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqInstsIssued 700720615 # Number of instructions issued
|
||||
system.cpu.iq.iqSquashedInstsIssued 1613210 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedInstsExamined 237113606 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedOperandsExamined 598814504 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 3094720 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.issued_per_cycle::samples 462293499 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::mean 1.515748 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::stdev 1.710183 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::0 192936549 41.73% 41.73% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::1 75135766 16.25% 57.99% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::2 69228865 14.98% 72.96% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::3 61089071 13.21% 86.18% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::4 35380643 7.65% 93.83% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::5 15554118 3.36% 97.19% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::6 7568076 1.64% 98.83% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::7 4045000 0.87% 99.71% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::8 1355411 0.29% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::total 462293499 # Number of insts issued each cycle
|
||||
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntAlu 467117 4.69% 4.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntMult 0 0.00% 4.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntDiv 0 0.00% 4.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatMult 0 0.00% 4.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdMult 0 0.00% 4.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdShift 0 0.00% 4.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::MemRead 6749256 67.80% 72.49% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::MemWrite 2738977 27.51% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntAlu 472287152 67.40% 67.40% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntMult 386091 0.06% 67.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatAdd 198 0.00% 67.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::MemRead 162565842 23.20% 90.66% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::MemWrite 65481329 9.34% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::total 700720615 # Type of FU issued
|
||||
system.cpu.iq.rate 1.503321 # Inst issue rate
|
||||
system.cpu.iq.fu_busy_cnt 9955350 # FU busy when requested
|
||||
system.cpu.iq.fu_busy_rate 0.014207 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.int_inst_queue_reads 1875302857 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_writes 1050553482 # Number of integer instruction queue writes
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 668216510 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.fp_inst_queue_reads 432 # Number of floating instruction queue reads
|
||||
system.cpu.iq.fp_inst_queue_writes 858 # Number of floating instruction queue writes
|
||||
system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses
|
||||
system.cpu.iq.int_alu_accesses 710675747 # Number of integer alu accesses
|
||||
system.cpu.iq.fp_alu_accesses 218 # Number of floating point alu accesses
|
||||
system.cpu.iew.lsq.thread0.forwLoads 9109880 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread0.squashedLoads 60525813 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread0.ignoredResponses 50692 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread0.memOrderViolation 63405 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread0.squashedStores 17458202 # Number of stores squashed
|
||||
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
||||
system.cpu.iew.lsq.thread0.rescheduledLoads 20818 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread0.cacheBlocked 376 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||||
system.cpu.iew.iewSquashCycles 38271034 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewBlockCycles 2890868 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewUnblockCycles 175492 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.iewDispatchedInsts 822161545 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewDispSquashedInsts 8144996 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispLoadInsts 187298810 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispStoreInsts 75062120 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 5327019 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewIQFullEvents 85808 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.iewLSQFullEvents 8514 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.memOrderViolationEvents 63405 # Number of memory order violations
|
||||
system.cpu.iew.predictedTakenIncorrect 10568276 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.iew.predictedNotTakenIncorrect 7702731 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.branchMispredicts 18271007 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewExecutedInsts 681861282 # Number of executed instructions
|
||||
system.cpu.iew.iewExecLoadInsts 155223597 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 18859333 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
||||
system.cpu.iew.exec_nop 8780498 # number of nop insts executed
|
||||
system.cpu.iew.exec_refs 219185272 # number of memory reference insts executed
|
||||
system.cpu.iew.exec_branches 141958281 # Number of branches executed
|
||||
system.cpu.iew.exec_stores 63961675 # Number of stores executed
|
||||
system.cpu.iew.exec_rate 1.462860 # Inst execution rate
|
||||
system.cpu.iew.wb_sent 673014173 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.wb_count 668216526 # cumulative count of insts written-back
|
||||
system.cpu.iew.wb_producers 381765084 # num instructions producing a value
|
||||
system.cpu.iew.wb_consumers 656387982 # num instructions consuming a value
|
||||
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
||||
system.cpu.iew.wb_rate 1.433587 # insts written-back per cycle
|
||||
system.cpu.iew.wb_fanout 0.581615 # average fanout of values written-back
|
||||
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||
system.cpu.commit.commitCommittedInsts 510298820 # The number of committed instructions
|
||||
system.cpu.commit.commitCommittedOps 574685381 # The number of committed instructions
|
||||
system.cpu.commit.commitSquashedInsts 247493136 # The number of squashed insts skipped by commit
|
||||
system.cpu.commit.commitNonSpecStalls 3721073 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu.commit.branchMispredicts 15415046 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.committed_per_cycle::samples 424022466 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::mean 1.355318 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::stdev 2.071268 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::0 206316988 48.66% 48.66% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::1 102533575 24.18% 72.84% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::2 40145036 9.47% 82.31% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::3 19513900 4.60% 86.91% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::4 17437160 4.11% 91.02% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::5 7239208 1.71% 92.73% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::6 7753458 1.83% 94.56% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::7 3810522 0.90% 95.45% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::8 19272619 4.55% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::total 424022466 # Number of insts commited each cycle
|
||||
system.cpu.commit.committedInsts 510298820 # Number of instructions committed
|
||||
system.cpu.commit.committedOps 574685381 # Number of ops (including micro ops) committed
|
||||
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
||||
system.cpu.commit.refs 184376915 # Number of memory references committed
|
||||
system.cpu.commit.loads 126772997 # Number of loads committed
|
||||
system.cpu.commit.membars 1488542 # Number of memory barriers committed
|
||||
system.cpu.commit.branches 120192182 # Number of branches committed
|
||||
system.cpu.commit.fp_insts 16 # Number of committed floating point instructions.
|
||||
system.cpu.commit.int_insts 473701465 # Number of committed integer instructions.
|
||||
system.cpu.commit.function_calls 9757362 # Number of function calls committed.
|
||||
system.cpu.commit.bw_lim_events 19272619 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
||||
system.cpu.rob.rob_reads 1226921226 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 1682775882 # The number of ROB writes
|
||||
system.cpu.timesIdled 98525 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 3821587 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.committedInsts 508954936 # Number of Instructions Simulated
|
||||
system.cpu.committedOps 573341497 # Number of Ops (including micro ops) Simulated
|
||||
system.cpu.committedInsts_total 508954936 # Number of Instructions Simulated
|
||||
system.cpu.cpi 0.915828 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 0.915828 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 1.091908 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 1.091908 # IPC: Total IPC of All Threads
|
||||
system.cpu.int_regfile_reads 3163594515 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 777373809 # number of integer regfile writes
|
||||
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
|
||||
system.cpu.misc_regfile_reads 1130092901 # number of misc regfile reads
|
||||
system.cpu.misc_regfile_writes 4463966 # number of misc regfile writes
|
||||
system.cpu.icache.replacements 16105 # number of replacements
|
||||
system.cpu.icache.tagsinuse 1117.727093 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 126840323 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 17981 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 7054.130638 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 1117.727093 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.545765 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.545765 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 126840329 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 126840329 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 126840329 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 126840329 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 126840329 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 126840329 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 19891 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 19891 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 19891 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 19891 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 19891 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 19891 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 267894500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 267894500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 267894500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 267894500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 267894500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 267894500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 126860220 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 126860220 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 126860220 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 126860220 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 126860220 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 126860220 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000157 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.000157 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000157 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.000157 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000157 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000157 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13468.126288 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 13468.126288 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13468.126288 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 13468.126288 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13468.126288 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 13468.126288 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks::writebacks 1 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 1 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1759 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::total 1759 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::cpu.inst 1759 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::total 1759 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::cpu.inst 1759 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::total 1759 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 18132 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 18132 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 18132 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 18132 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 18132 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 18132 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 171640500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 171640500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 171640500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 171640500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 171640500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 171640500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000143 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000143 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000143 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000143 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000143 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000143 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 9466.164792 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 9466.164792 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 9466.164792 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 9466.164792 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 9466.164792 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 9466.164792 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 1204809 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 4052.906677 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 197317737 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 1208905 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 163.220217 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 5518270000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 4052.906677 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.989479 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.989479 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 140063979 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 140063979 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 52782968 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 52782968 # number of WriteReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::cpu.data 2238489 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::total 2238489 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::cpu.data 2231982 # number of StoreCondReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::total 2231982 # number of StoreCondReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 192846947 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 192846947 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 192846947 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 192846947 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 1318830 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 1318830 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 1456338 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 1456338 # number of WriteReq misses
|
||||
system.cpu.dcache.LoadLockedReq_misses::cpu.data 78 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.LoadLockedReq_misses::total 78 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 2775168 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 2775168 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 2775168 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 2775168 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 15287682000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 15287682000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 25164058992 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 25164058992 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 845500 # number of LoadLockedReq miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_miss_latency::total 845500 # number of LoadLockedReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 40451740992 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 40451740992 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 40451740992 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 40451740992 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 141382809 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 141382809 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 2238567 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::total 2238567 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::cpu.data 2231982 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::total 2231982 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 195622115 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 195622115 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 195622115 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 195622115 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009328 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.009328 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.026850 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.026850 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000035 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000035 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.014186 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.014186 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.014186 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.014186 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11591.851869 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 11591.851869 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17278.996354 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 17278.996354 # average WriteReq miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 10839.743590 # average LoadLockedReq miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 10839.743590 # average LoadLockedReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 14576.321503 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 14576.321503 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 14576.321503 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 14576.321503 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 602000 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 92 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets 6543.478261 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 1073322 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 1073322 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 451055 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 451055 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1115056 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 1115056 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 78 # number of LoadLockedReq MSHR hits
|
||||
system.cpu.dcache.LoadLockedReq_mshr_hits::total 78 # number of LoadLockedReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 1566111 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 1566111 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 1566111 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 1566111 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 867775 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 867775 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 341282 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 341282 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 1209057 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 1209057 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 1209057 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 1209057 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6208585000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 6208585000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4381340497 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 4381340497 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10589925497 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 10589925497 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10589925497 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 10589925497 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006138 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006138 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006292 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006292 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006181 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.006181 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006181 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.006181 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7154.602287 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 7154.602287 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 12837.889185 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 12837.889185 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8758.830640 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 8758.830640 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8758.830640 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 8758.830640 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 218501 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 20930.395337 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 1557466 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 238907 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 6.519131 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 170551572000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::writebacks 13694.941090 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 198.526640 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 7036.927606 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.417936 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.006059 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.214750 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.638745 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 14165 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 742446 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 756611 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 1073323 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 1073323 # number of Writeback hits
|
||||
system.cpu.l2cache.UpgradeReq_hits::cpu.data 110 # number of UpgradeReq hits
|
||||
system.cpu.l2cache.UpgradeReq_hits::total 110 # number of UpgradeReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 232553 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 232553 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 14165 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 974999 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 989164 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 14165 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 974999 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 989164 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 3852 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.data 124612 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 128464 # number of ReadReq misses
|
||||
system.cpu.l2cache.UpgradeReq_misses::cpu.data 33 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_misses::total 33 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 109285 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 109285 # number of ReadExReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 3852 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 233897 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 237749 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 3852 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 233897 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 237749 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 132071500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4261496000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 4393567500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 205000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency::total 205000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3742208000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 3742208000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 132071500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 8003704000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 8135775500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 132071500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 8003704000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 8135775500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 18017 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 867058 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 885075 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 1073323 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 1073323 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 143 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_accesses::total 143 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 341838 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 341838 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 18017 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 1208896 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 1226913 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 18017 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 1208896 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 1226913 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.213798 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.143718 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.145145 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.230769 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.230769 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.319698 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.319698 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.213798 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.193480 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.193778 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.213798 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.193480 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.193778 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34286.474559 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34198.118961 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 34200.768309 # average ReadReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 6212.121212 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 6212.121212 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34242.649952 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34242.649952 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34286.474559 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34218.925424 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 34220.019853 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34286.474559 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34218.925424 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 34220.019853 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks::writebacks 171061 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 171061 # number of writebacks
|
||||
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 5 # number of ReadReq MSHR hits
|
||||
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 22 # number of ReadReq MSHR hits
|
||||
system.cpu.l2cache.ReadReq_mshr_hits::total 27 # number of ReadReq MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_hits::cpu.inst 5 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_hits::cpu.data 22 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_hits::total 27 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_hits::cpu.inst 5 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_hits::cpu.data 22 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_hits::total 27 # number of overall MSHR hits
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3847 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 124590 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::total 128437 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 33 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses::total 33 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 109285 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 109285 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 3847 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 233875 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 237722 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3847 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 233875 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 237722 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 119582500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3866885000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3986467500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1024500 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1024500 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3388776000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3388776000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 119582500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7255661000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 7375243500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 119582500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7255661000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 7375243500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.213521 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.143693 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.145114 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.230769 # mshr miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.230769 # mshr miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.319698 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.319698 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.213521 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.193462 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.193756 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.213521 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.193462 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.193756 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31084.611385 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31036.880970 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31038.310611 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31045.454545 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31045.454545 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31008.610514 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31008.610514 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31084.611385 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31023.670764 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31024.656952 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31084.611385 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31023.670764 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31024.656952 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
@ -0,0 +1,135 @@
|
||||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
full_system=false
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
||||
[system]
|
||||
type=System
|
||||
children=cpu membus physmem
|
||||
boot_osflags=a
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
mem_mode=atomic
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
readfile=
|
||||
symbolfile=
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.membus.slave[0]
|
||||
|
||||
[system.cpu]
|
||||
type=AtomicSimpleCPU
|
||||
children=dtb interrupts itb tracer workload
|
||||
checker=Null
|
||||
clock=500
|
||||
cpu_id=0
|
||||
defer_registration=false
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
fastmem=false
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
interrupts=system.cpu.interrupts
|
||||
itb=system.cpu.itb
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
phase=0
|
||||
profile=0
|
||||
progress_interval=0
|
||||
simulate_data_stalls=false
|
||||
simulate_inst_stalls=false
|
||||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
width=1
|
||||
workload=system.cpu.workload
|
||||
dcache_port=system.membus.slave[2]
|
||||
icache_port=system.membus.slave[1]
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
size=64
|
||||
walker=system.cpu.dtb.walker
|
||||
|
||||
[system.cpu.dtb.walker]
|
||||
type=ArmTableWalker
|
||||
max_backoff=100000
|
||||
min_backoff=0
|
||||
sys=system
|
||||
port=system.membus.slave[4]
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=ArmInterrupts
|
||||
|
||||
[system.cpu.itb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
size=64
|
||||
walker=system.cpu.itb.walker
|
||||
|
||||
[system.cpu.itb.walker]
|
||||
type=ArmTableWalker
|
||||
max_backoff=100000
|
||||
min_backoff=0
|
||||
sys=system
|
||||
port=system.membus.slave[3]
|
||||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
|
||||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=parser 2.1.dict -batch
|
||||
cwd=build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-atomic
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/cpu2000/binaries/arm/linux/parser
|
||||
gid=100
|
||||
input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
ppid=99
|
||||
simpoint=114600000000
|
||||
system=system
|
||||
uid=100
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
master=system.physmem.port[0]
|
||||
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.membus.master[0]
|
||||
|
||||
@ -0,0 +1,2 @@
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
hack: be nice to actually delete the event here
|
||||
70
simulators/gem5/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simout
Executable file
70
simulators/gem5/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simout
Executable file
@ -0,0 +1,70 @@
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jun 4 2012 12:14:06
|
||||
gem5 started Jun 4 2012 17:42:59
|
||||
gem5 executing on zizzer
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-atomic
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
||||
Reading the dictionary files: *************************************************
|
||||
|
||||
|
||||
Welcome to the Link Parser -- Version 2.1
|
||||
|
||||
Copyright (C) 1991-1995 Daniel Sleator and Davy Temperley
|
||||
|
||||
Processing sentences in batch mode
|
||||
|
||||
info: Increasing stack size by one page.
|
||||
Echoing of input sentence turned on.
|
||||
* as had expected the party to be a success , it was a success
|
||||
* do you know where John 's
|
||||
* he said that , finding that it was impossible to get work as a waiter , he would work as a janitor
|
||||
info: Increasing stack size by one page.
|
||||
* how fast the program is it
|
||||
* I am wondering whether to invite to the party
|
||||
* I gave him for his birthday it
|
||||
* I thought terrible after our discussion
|
||||
* I wonder how much money have you earned
|
||||
* Janet who is an expert on dogs helped me choose one
|
||||
* she interviewed more programmers than was hired
|
||||
* such flowers are found chiefly particularly in Europe
|
||||
* the dogs some of which were very large ran after the man
|
||||
* the man whom I play tennis is here
|
||||
* there is going to be an important meeting January
|
||||
* to pretend that our program is usable in its current form would be happy
|
||||
* we're thinking about going to a movie this theater
|
||||
* which dog you said you chased
|
||||
- also invited to the meeting were several prominent scientists
|
||||
- he ran home so quickly that his mother could hardly believe he had called from school
|
||||
- so many people attended that they spilled over into several neighboring fields
|
||||
- voting in favor of the bill were 36 Republicans and 4 moderate Democrats
|
||||
: Grace may not be possible to fix the problem
|
||||
any program as good as ours should be useful
|
||||
biochemically , I think the experiment has a lot of problems
|
||||
Fred has had five years of experience as a programmer
|
||||
he is looking for another job
|
||||
how did John do it
|
||||
how many more people do you think will come
|
||||
how much more spilled
|
||||
I have more money than John has time
|
||||
I made it clear that I was angry
|
||||
I wonder how John did it
|
||||
I wonder how much more quickly he ran
|
||||
invite John and whoever else you want to invite
|
||||
it is easier to ignore the problem than it is to solve it
|
||||
many who initially supported Thomas later changed their minds
|
||||
neither Mary nor Louise are coming to the party
|
||||
she interviewed more programmers than were hired
|
||||
telling Joe that Sue was coming to the party would create a real problem
|
||||
the man with whom I play tennis is here
|
||||
there is a dog in the park
|
||||
this is not the man we know and love
|
||||
we like to eat at restaurants , usually on weekends
|
||||
what did John say he thought you should do
|
||||
about 2 million people attended
|
||||
the five best costumes got prizes
|
||||
No errors!
|
||||
Exiting @ tick 290498972000 because target called exit()
|
||||
@ -0,0 +1,102 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.290499 # Number of seconds simulated
|
||||
sim_ticks 290498972000 # Number of ticks simulated
|
||||
final_tick 290498972000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 2223848 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2506499 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1275264214 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 224628 # Number of bytes of host memory used
|
||||
host_seconds 227.80 # Real time elapsed on the host
|
||||
sim_insts 506581615 # Number of instructions simulated
|
||||
sim_ops 570968176 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 2066445536 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 422852702 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 2489298238 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 2066445536 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 2066445536 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::cpu.data 216067624 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 216067624 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 516611384 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 125228858 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 641840242 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::cpu.data 55727847 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 55727847 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 7113434935 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 1455608256 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 8569043191 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 7113434935 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 7113434935 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::cpu.data 743781028 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 743781028 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 7113434935 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 2199389284 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 9312824219 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.dtb.read_hits 0 # DTB read hits
|
||||
system.cpu.dtb.read_misses 0 # DTB read misses
|
||||
system.cpu.dtb.write_hits 0 # DTB write hits
|
||||
system.cpu.dtb.write_misses 0 # DTB write misses
|
||||
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
|
||||
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||||
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
|
||||
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.dtb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.dtb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
|
||||
system.cpu.dtb.hits 0 # DTB hits
|
||||
system.cpu.dtb.misses 0 # DTB misses
|
||||
system.cpu.dtb.accesses 0 # DTB accesses
|
||||
system.cpu.itb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.itb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.write_hits 0 # DTB write hits
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
|
||||
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||||
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
|
||||
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.itb.inst_accesses 0 # ITB inst accesses
|
||||
system.cpu.itb.hits 0 # DTB hits
|
||||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 548 # Number of system calls
|
||||
system.cpu.numCycles 580997945 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 506581615 # Number of instructions committed
|
||||
system.cpu.committedOps 570968176 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 470727703 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 15725605 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 94894805 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 470727703 # number of integer instructions
|
||||
system.cpu.num_fp_insts 16 # number of float instructions
|
||||
system.cpu.num_int_register_reads 2465023721 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 646169365 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 16 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
|
||||
system.cpu.num_mem_refs 182890035 # number of memory refs
|
||||
system.cpu.num_load_insts 126029556 # Number of load instructions
|
||||
system.cpu.num_store_insts 56860479 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 580997945 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
@ -0,0 +1,216 @@
|
||||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
full_system=false
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
||||
[system]
|
||||
type=System
|
||||
children=cpu membus physmem
|
||||
boot_osflags=a
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
mem_mode=atomic
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
readfile=
|
||||
symbolfile=
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.membus.slave[0]
|
||||
|
||||
[system.cpu]
|
||||
type=TimingSimpleCPU
|
||||
children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
|
||||
checker=Null
|
||||
clock=500
|
||||
cpu_id=0
|
||||
defer_registration=false
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
interrupts=system.cpu.interrupts
|
||||
itb=system.cpu.itb
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
phase=0
|
||||
profile=0
|
||||
progress_interval=0
|
||||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
workload=system.cpu.workload
|
||||
dcache_port=system.cpu.dcache.cpu_side
|
||||
icache_port=system.cpu.icache.cpu_side
|
||||
|
||||
[system.cpu.dcache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=262144
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.dcache_port
|
||||
mem_side=system.cpu.toL2Bus.slave[1]
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
size=64
|
||||
walker=system.cpu.dtb.walker
|
||||
|
||||
[system.cpu.dtb.walker]
|
||||
type=ArmTableWalker
|
||||
max_backoff=100000
|
||||
min_backoff=0
|
||||
sys=system
|
||||
port=system.cpu.toL2Bus.slave[3]
|
||||
|
||||
[system.cpu.icache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=131072
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.icache_port
|
||||
mem_side=system.cpu.toL2Bus.slave[0]
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=ArmInterrupts
|
||||
|
||||
[system.cpu.itb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
size=64
|
||||
walker=system.cpu.itb.walker
|
||||
|
||||
[system.cpu.itb.walker]
|
||||
type=ArmTableWalker
|
||||
max_backoff=100000
|
||||
min_backoff=0
|
||||
sys=system
|
||||
port=system.cpu.toL2Bus.slave[2]
|
||||
|
||||
[system.cpu.l2cache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=false
|
||||
latency=10000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=2097152
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.toL2Bus.master[0]
|
||||
mem_side=system.membus.slave[1]
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
master=system.cpu.l2cache.cpu_side
|
||||
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
|
||||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
|
||||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=parser 2.1.dict -batch
|
||||
cwd=build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/cpu2000/binaries/arm/linux/parser
|
||||
gid=100
|
||||
input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
ppid=99
|
||||
simpoint=114600000000
|
||||
system=system
|
||||
uid=100
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
master=system.physmem.port[0]
|
||||
slave=system.system_port system.cpu.l2cache.mem_side
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.membus.master[0]
|
||||
|
||||
@ -0,0 +1,2 @@
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
hack: be nice to actually delete the event here
|
||||
70
simulators/gem5/tests/long/se/20.parser/ref/arm/linux/simple-timing/simout
Executable file
70
simulators/gem5/tests/long/se/20.parser/ref/arm/linux/simple-timing/simout
Executable file
@ -0,0 +1,70 @@
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jun 4 2012 12:14:06
|
||||
gem5 started Jun 4 2012 17:46:58
|
||||
gem5 executing on zizzer
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
||||
Reading the dictionary files: *************************************************
|
||||
|
||||
|
||||
Welcome to the Link Parser -- Version 2.1
|
||||
|
||||
Copyright (C) 1991-1995 Daniel Sleator and Davy Temperley
|
||||
|
||||
Processing sentences in batch mode
|
||||
|
||||
info: Increasing stack size by one page.
|
||||
Echoing of input sentence turned on.
|
||||
* as had expected the party to be a success , it was a success
|
||||
* do you know where John 's
|
||||
* he said that , finding that it was impossible to get work as a waiter , he would work as a janitor
|
||||
info: Increasing stack size by one page.
|
||||
* how fast the program is it
|
||||
* I am wondering whether to invite to the party
|
||||
* I gave him for his birthday it
|
||||
* I thought terrible after our discussion
|
||||
* I wonder how much money have you earned
|
||||
* Janet who is an expert on dogs helped me choose one
|
||||
* she interviewed more programmers than was hired
|
||||
* such flowers are found chiefly particularly in Europe
|
||||
* the dogs some of which were very large ran after the man
|
||||
* the man whom I play tennis is here
|
||||
* there is going to be an important meeting January
|
||||
* to pretend that our program is usable in its current form would be happy
|
||||
* we're thinking about going to a movie this theater
|
||||
* which dog you said you chased
|
||||
- also invited to the meeting were several prominent scientists
|
||||
- he ran home so quickly that his mother could hardly believe he had called from school
|
||||
- so many people attended that they spilled over into several neighboring fields
|
||||
- voting in favor of the bill were 36 Republicans and 4 moderate Democrats
|
||||
: Grace may not be possible to fix the problem
|
||||
any program as good as ours should be useful
|
||||
biochemically , I think the experiment has a lot of problems
|
||||
Fred has had five years of experience as a programmer
|
||||
he is looking for another job
|
||||
how did John do it
|
||||
how many more people do you think will come
|
||||
how much more spilled
|
||||
I have more money than John has time
|
||||
I made it clear that I was angry
|
||||
I wonder how John did it
|
||||
I wonder how much more quickly he ran
|
||||
invite John and whoever else you want to invite
|
||||
it is easier to ignore the problem than it is to solve it
|
||||
many who initially supported Thomas later changed their minds
|
||||
neither Mary nor Louise are coming to the party
|
||||
she interviewed more programmers than were hired
|
||||
telling Joe that Sue was coming to the party would create a real problem
|
||||
the man with whom I play tennis is here
|
||||
there is a dog in the park
|
||||
this is not the man we know and love
|
||||
we like to eat at restaurants , usually on weekends
|
||||
what did John say he thought you should do
|
||||
about 2 million people attended
|
||||
the five best costumes got prizes
|
||||
No errors!
|
||||
Exiting @ tick 722234364000 because target called exit()
|
||||
@ -0,0 +1,427 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.722234 # Number of seconds simulated
|
||||
sim_ticks 722234364000 # Number of ticks simulated
|
||||
final_tick 722234364000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1114772 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1256160 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1594352181 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 233804 # Number of bytes of host memory used
|
||||
host_seconds 453.00 # Real time elapsed on the host
|
||||
sim_insts 504986861 # Number of instructions simulated
|
||||
sim_ops 569034848 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 188608 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 14608448 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 14797056 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 188608 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 188608 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 11027328 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 11027328 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 2947 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 228257 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 231204 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 172302 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 172302 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 261145 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 20226742 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 20487887 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 261145 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 261145 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 15268351 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 15268351 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 15268351 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 261145 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 20226742 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 35756238 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.dtb.read_hits 0 # DTB read hits
|
||||
system.cpu.dtb.read_misses 0 # DTB read misses
|
||||
system.cpu.dtb.write_hits 0 # DTB write hits
|
||||
system.cpu.dtb.write_misses 0 # DTB write misses
|
||||
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
|
||||
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||||
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
|
||||
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.dtb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.dtb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
|
||||
system.cpu.dtb.hits 0 # DTB hits
|
||||
system.cpu.dtb.misses 0 # DTB misses
|
||||
system.cpu.dtb.accesses 0 # DTB accesses
|
||||
system.cpu.itb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.itb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.write_hits 0 # DTB write hits
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
|
||||
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||||
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
|
||||
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.itb.inst_accesses 0 # ITB inst accesses
|
||||
system.cpu.itb.hits 0 # DTB hits
|
||||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 548 # Number of system calls
|
||||
system.cpu.numCycles 1444468728 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 504986861 # Number of instructions committed
|
||||
system.cpu.committedOps 569034848 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 470727703 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 15725605 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 94894805 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 470727703 # number of integer instructions
|
||||
system.cpu.num_fp_insts 16 # number of float instructions
|
||||
system.cpu.num_int_register_reads 2844375220 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 646169365 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 16 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
|
||||
system.cpu.num_mem_refs 182890035 # number of memory refs
|
||||
system.cpu.num_load_insts 126029556 # Number of load instructions
|
||||
system.cpu.num_store_insts 56860479 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 1444468728 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.icache.replacements 9788 # number of replacements
|
||||
system.cpu.icache.tagsinuse 984.426148 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 516599864 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 11521 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 44839.845847 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 984.426148 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.480677 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.480677 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 516599864 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 516599864 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 516599864 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 516599864 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 516599864 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 516599864 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 11521 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 11521 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 11521 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 11521 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 11521 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 11521 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 285068000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 285068000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 285068000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 285068000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 285068000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 285068000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 516611385 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 516611385 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 516611385 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 516611385 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 516611385 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 516611385 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000022 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.000022 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000022 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.000022 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000022 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000022 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 24743.338252 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 24743.338252 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 24743.338252 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 24743.338252 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 24743.338252 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 24743.338252 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 11521 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 11521 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 11521 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 11521 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 11521 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 11521 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 250505000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 250505000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 250505000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 250505000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 250505000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 250505000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000022 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000022 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21743.338252 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21743.338252 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21743.338252 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 21743.338252 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21743.338252 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 21743.338252 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 1134822 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 4065.490059 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 179817787 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 1138918 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 157.884753 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 11889987000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 4065.490059 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.992551 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.992551 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 122957659 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 122957659 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 53883046 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 53883046 # number of WriteReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488541 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::total 1488541 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 176840705 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 176840705 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 176840705 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 176840705 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 782658 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 782658 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 356260 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 356260 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 1138918 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 1138918 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 1138918 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 1138918 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 15502704000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 15502704000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 10028942000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 10028942000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 25531646000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 25531646000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 25531646000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 25531646000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 123740317 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 123740317 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488541 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::total 1488541 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 177979623 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 177979623 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 177979623 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 177979623 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.006325 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.006325 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006568 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.006568 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.006399 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.006399 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.006399 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.006399 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19807.762778 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 19807.762778 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28150.625947 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 28150.625947 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 22417.457622 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 22417.457622 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 22417.457622 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 22417.457622 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 1025440 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 1025440 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 782658 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 782658 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356260 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 356260 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 1138918 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 1138918 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 1138918 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 1138918 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 13154730000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 13154730000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8960162000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 8960162000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 22114892000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 22114892000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 22114892000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 22114892000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006325 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006325 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006568 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006568 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006399 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.006399 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006399 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.006399 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16807.762778 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16807.762778 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25150.625947 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25150.625947 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19417.457622 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 19417.457622 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19417.457622 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 19417.457622 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 212089 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 20443.163614 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 1426644 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 232128 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 6.145937 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 513135223000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::writebacks 14594.006011 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 132.842413 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 5716.315189 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.445374 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.004054 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.174448 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.623876 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 8574 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 674432 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 683006 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 1025440 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 1025440 # number of Writeback hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 236229 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 236229 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 8574 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 910661 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 919235 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 8574 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 910661 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 919235 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 2947 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.data 108226 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 111173 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 120031 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 120031 # number of ReadExReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 2947 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 228257 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 231204 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 2947 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 228257 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 231204 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 153244000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5627752000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 5780996000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6241612000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 6241612000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 153244000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 11869364000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 12022608000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 153244000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 11869364000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 12022608000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 11521 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 782658 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 794179 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 1025440 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 1025440 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 356260 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 356260 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 11521 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 1138918 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 1150439 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 11521 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 1138918 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 1150439 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.255794 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.138280 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.139985 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.336920 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.336920 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.255794 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.200416 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.200970 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.255794 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.200416 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.200970 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks::writebacks 172302 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 172302 # number of writebacks
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2947 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 108226 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::total 111173 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 120031 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 120031 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 2947 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 228257 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 231204 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2947 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 228257 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 231204 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 117880000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4329040000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 4446920000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4801240000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4801240000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 117880000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9130280000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 9248160000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 117880000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9130280000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 9248160000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.255794 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.138280 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.139985 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.336920 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.336920 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.255794 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.200416 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.200970 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.255794 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.200416 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.200970 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
@ -0,0 +1,550 @@
|
||||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
full_system=false
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
||||
[system]
|
||||
type=System
|
||||
children=cpu membus physmem
|
||||
boot_osflags=a
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
mem_mode=atomic
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
readfile=
|
||||
symbolfile=
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.membus.slave[0]
|
||||
|
||||
[system.cpu]
|
||||
type=DerivO3CPU
|
||||
children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
|
||||
BTBEntries=4096
|
||||
BTBTagSize=16
|
||||
LFSTSize=1024
|
||||
LQEntries=32
|
||||
LSQCheckLoads=true
|
||||
LSQDepCheckShift=4
|
||||
RASSize=16
|
||||
SQEntries=32
|
||||
SSITSize=1024
|
||||
activity=0
|
||||
backComSize=5
|
||||
cachePorts=200
|
||||
checker=Null
|
||||
choiceCtrBits=2
|
||||
choicePredictorSize=8192
|
||||
clock=500
|
||||
commitToDecodeDelay=1
|
||||
commitToFetchDelay=1
|
||||
commitToIEWDelay=1
|
||||
commitToRenameDelay=1
|
||||
commitWidth=8
|
||||
cpu_id=0
|
||||
decodeToFetchDelay=1
|
||||
decodeToRenameDelay=1
|
||||
decodeWidth=8
|
||||
defer_registration=false
|
||||
dispatchWidth=8
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
fetchToDecodeDelay=1
|
||||
fetchTrapLatency=1
|
||||
fetchWidth=8
|
||||
forwardComSize=5
|
||||
fuPool=system.cpu.fuPool
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
globalCtrBits=2
|
||||
globalHistoryBits=13
|
||||
globalPredictorSize=8192
|
||||
iewToCommitDelay=1
|
||||
iewToDecodeDelay=1
|
||||
iewToFetchDelay=1
|
||||
iewToRenameDelay=1
|
||||
instShiftAmt=2
|
||||
interrupts=system.cpu.interrupts
|
||||
issueToExecuteDelay=1
|
||||
issueWidth=8
|
||||
itb=system.cpu.itb
|
||||
localCtrBits=2
|
||||
localHistoryBits=11
|
||||
localHistoryTableSize=2048
|
||||
localPredictorSize=2048
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
needsTSO=true
|
||||
numIQEntries=64
|
||||
numPhysFloatRegs=256
|
||||
numPhysIntRegs=256
|
||||
numROBEntries=192
|
||||
numRobs=1
|
||||
numThreads=1
|
||||
phase=0
|
||||
predType=tournament
|
||||
profile=0
|
||||
progress_interval=0
|
||||
renameToDecodeDelay=1
|
||||
renameToFetchDelay=1
|
||||
renameToIEWDelay=2
|
||||
renameToROBDelay=1
|
||||
renameWidth=8
|
||||
smtCommitPolicy=RoundRobin
|
||||
smtFetchPolicy=SingleThread
|
||||
smtIQPolicy=Partitioned
|
||||
smtIQThreshold=100
|
||||
smtLSQPolicy=Partitioned
|
||||
smtLSQThreshold=100
|
||||
smtNumFetchingThreads=1
|
||||
smtROBPolicy=Partitioned
|
||||
smtROBThreshold=100
|
||||
squashWidth=8
|
||||
store_set_clear_period=250000
|
||||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
trapLatency=13
|
||||
wbDepth=1
|
||||
wbWidth=8
|
||||
workload=system.cpu.workload
|
||||
dcache_port=system.cpu.dcache.cpu_side
|
||||
icache_port=system.cpu.icache.cpu_side
|
||||
|
||||
[system.cpu.dcache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=262144
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=20
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.dcache_port
|
||||
mem_side=system.cpu.toL2Bus.slave[1]
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=X86TLB
|
||||
children=walker
|
||||
size=64
|
||||
walker=system.cpu.dtb.walker
|
||||
|
||||
[system.cpu.dtb.walker]
|
||||
type=X86PagetableWalker
|
||||
system=system
|
||||
port=system.cpu.toL2Bus.slave[3]
|
||||
|
||||
[system.cpu.fuPool]
|
||||
type=FUPool
|
||||
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
|
||||
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
|
||||
|
||||
[system.cpu.fuPool.FUList0]
|
||||
type=FUDesc
|
||||
children=opList
|
||||
count=6
|
||||
opList=system.cpu.fuPool.FUList0.opList
|
||||
|
||||
[system.cpu.fuPool.FUList0.opList]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=IntAlu
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList1]
|
||||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=2
|
||||
opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=IntMult
|
||||
opLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList1]
|
||||
type=OpDesc
|
||||
issueLat=19
|
||||
opClass=IntDiv
|
||||
opLat=20
|
||||
|
||||
[system.cpu.fuPool.FUList2]
|
||||
type=FUDesc
|
||||
children=opList0 opList1 opList2
|
||||
count=4
|
||||
opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=FloatAdd
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList1]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=FloatCmp
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList2]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=FloatCvt
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList3]
|
||||
type=FUDesc
|
||||
children=opList0 opList1 opList2
|
||||
count=2
|
||||
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=FloatMult
|
||||
opLat=4
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList1]
|
||||
type=OpDesc
|
||||
issueLat=12
|
||||
opClass=FloatDiv
|
||||
opLat=12
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList2]
|
||||
type=OpDesc
|
||||
issueLat=24
|
||||
opClass=FloatSqrt
|
||||
opLat=24
|
||||
|
||||
[system.cpu.fuPool.FUList4]
|
||||
type=FUDesc
|
||||
children=opList
|
||||
count=0
|
||||
opList=system.cpu.fuPool.FUList4.opList
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5]
|
||||
type=FUDesc
|
||||
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
|
||||
count=4
|
||||
opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList00]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdAdd
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList01]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdAddAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList02]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdAlu
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList03]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdCmp
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList04]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdCvt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList05]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdMisc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList06]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdMult
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList07]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdMultAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList08]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdShift
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList09]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdShiftAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList10]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdSqrt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList11]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatAdd
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList12]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatAlu
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList13]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatCmp
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList14]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatCvt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList15]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatDiv
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList16]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatMisc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList17]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatMult
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList18]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatMultAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList19]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatSqrt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList6]
|
||||
type=FUDesc
|
||||
children=opList
|
||||
count=0
|
||||
opList=system.cpu.fuPool.FUList6.opList
|
||||
|
||||
[system.cpu.fuPool.FUList6.opList]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList7]
|
||||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=4
|
||||
opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList1]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList8]
|
||||
type=FUDesc
|
||||
children=opList
|
||||
count=1
|
||||
opList=system.cpu.fuPool.FUList8.opList
|
||||
|
||||
[system.cpu.fuPool.FUList8.opList]
|
||||
type=OpDesc
|
||||
issueLat=3
|
||||
opClass=IprAccess
|
||||
opLat=3
|
||||
|
||||
[system.cpu.icache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=131072
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=20
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.icache_port
|
||||
mem_side=system.cpu.toL2Bus.slave[0]
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=X86LocalApic
|
||||
int_latency=1000
|
||||
pio_addr=2305843009213693952
|
||||
pio_latency=1000
|
||||
system=system
|
||||
int_master=system.membus.slave[2]
|
||||
int_slave=system.membus.master[2]
|
||||
pio=system.membus.master[1]
|
||||
|
||||
[system.cpu.itb]
|
||||
type=X86TLB
|
||||
children=walker
|
||||
size=64
|
||||
walker=system.cpu.itb.walker
|
||||
|
||||
[system.cpu.itb.walker]
|
||||
type=X86PagetableWalker
|
||||
system=system
|
||||
port=system.cpu.toL2Bus.slave[2]
|
||||
|
||||
[system.cpu.l2cache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=false
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=2097152
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.toL2Bus.master[0]
|
||||
mem_side=system.membus.slave[1]
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
master=system.cpu.l2cache.cpu_side
|
||||
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
|
||||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
|
||||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=parser 2.1.dict -batch
|
||||
cwd=build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/cpu2000/binaries/x86/linux/parser
|
||||
gid=100
|
||||
input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
ppid=99
|
||||
simpoint=114600000000
|
||||
system=system
|
||||
uid=100
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave
|
||||
slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.membus.master[0]
|
||||
|
||||
4
simulators/gem5/tests/long/se/20.parser/ref/x86/linux/o3-timing/simerr
Executable file
4
simulators/gem5/tests/long/se/20.parser/ref/x86/linux/o3-timing/simerr
Executable file
@ -0,0 +1,4 @@
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: instruction 'fnstcw_Mw' unimplemented
|
||||
warn: instruction 'fldcw_Mw' unimplemented
|
||||
hack: be nice to actually delete the event here
|
||||
82
simulators/gem5/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout
Executable file
82
simulators/gem5/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout
Executable file
@ -0,0 +1,82 @@
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jun 4 2012 13:44:28
|
||||
gem5 started Jun 4 2012 15:27:18
|
||||
gem5 executing on zizzer
|
||||
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
||||
Reading the dictionary files: ***********************info: Increasing stack size by one page.
|
||||
**************************
|
||||
58924 words stored in 3784810 bytes
|
||||
|
||||
|
||||
Welcome to the Link Parser -- Version 2.1
|
||||
|
||||
Copyright (C) 1991-1995 Daniel Sleator and Davy Temperley
|
||||
|
||||
Processing sentences in batch mode
|
||||
|
||||
info: Increasing stack size by one page.
|
||||
info: Increasing stack size by one page.
|
||||
Echoing of input sentence turned on.
|
||||
* as had expected the party to be a success , it was a success
|
||||
* do you know where John 's
|
||||
* he said that , finding that it was impossible to get work as a waiter , he would work as a janitor
|
||||
* how fast the program is it
|
||||
* I am wondering whether to invite to the party
|
||||
* I gave him for his birthday it
|
||||
* I thought terrible after our discussion
|
||||
* I wonder how much money have you earned
|
||||
* Janet who is an expert on dogs helped me choose one
|
||||
* she interviewed more programmers than was hired
|
||||
* such flowers are found chiefly particularly in Europe
|
||||
* the dogs some of which were very large ran after the man
|
||||
* the man whom I play tennis is here
|
||||
* there is going to be an important meeting January
|
||||
* to pretend that our program is usable in its current form would be happy
|
||||
* we're thinking about going to a movie this theater
|
||||
* which dog you said you chased
|
||||
- also invited to the meeting were several prominent scientists
|
||||
- he ran home so quickly that his mother could hardly believe he had called from school
|
||||
- so many people attended that they spilled over into several neighboring fields
|
||||
- voting in favor of the bill were 36 Republicans and 4 moderate Democrats
|
||||
: Grace may not be possible to fix the problem
|
||||
any program as good as ours should be useful
|
||||
biochemically , I think the experiment has a lot of problems
|
||||
Fred has had five years of experience as a programmer
|
||||
he is looking for another job
|
||||
how did John do it
|
||||
how many more people do you think will come
|
||||
how much more spilled
|
||||
I have more money than John has time
|
||||
I made it clear that I was angry
|
||||
I wonder how John did it
|
||||
I wonder how much more quickly he ran
|
||||
invite John and whoever else you want to invite
|
||||
it is easier to ignore the problem than it is to solve it
|
||||
many who initially supported Thomas later changed their minds
|
||||
neither Mary nor Louise are coming to the party
|
||||
she interviewed more programmers than were hired
|
||||
telling Joe that Sue was coming to the party would create a real problem
|
||||
the man with whom I play tennis is here
|
||||
there is a dog in the park
|
||||
this is not the man we know and love
|
||||
info: Increasing stack size by one page.
|
||||
info: Increasing stack size by one page.
|
||||
info: Increasing stack size by one page.
|
||||
info: Increasing stack size by one page.
|
||||
info: Increasing stack size by one page.
|
||||
info: Increasing stack size by one page.
|
||||
info: Increasing stack size by one page.
|
||||
info: Increasing stack size by one page.
|
||||
info: Increasing stack size by one page.
|
||||
info: Increasing stack size by one page.
|
||||
we like to eat at restaurants , usually on weekends
|
||||
what did John say he thought you should do
|
||||
about 2 million people attended
|
||||
the five best costumes got prizes
|
||||
No errors!
|
||||
Exiting @ tick 459937575500 because target called exit()
|
||||
@ -0,0 +1,658 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.459938 # Number of seconds simulated
|
||||
sim_ticks 459937575500 # Number of ticks simulated
|
||||
final_tick 459937575500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 70939 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 131174 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 39458742 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 264492 # Number of bytes of host memory used
|
||||
host_seconds 11656.16 # Real time elapsed on the host
|
||||
sim_insts 826877144 # Number of instructions simulated
|
||||
sim_ops 1528988756 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 379264 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 37103744 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 37483008 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 379264 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 379264 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 26316864 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 26316864 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 5926 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 579746 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 585672 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 411201 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 411201 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 824599 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 80671261 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 81495859 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 824599 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 824599 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 57218339 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 57218339 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 57218339 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 824599 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 80671261 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 138714198 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu.workload.num_syscalls 551 # Number of system calls
|
||||
system.cpu.numCycles 919875152 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.BPredUnit.lookups 225607243 # Number of BP lookups
|
||||
system.cpu.BPredUnit.condPredicted 225607243 # Number of conditional branches predicted
|
||||
system.cpu.BPredUnit.condIncorrect 14288733 # Number of conditional branches incorrect
|
||||
system.cpu.BPredUnit.BTBLookups 160422197 # Number of BTB lookups
|
||||
system.cpu.BPredUnit.BTBHits 155872353 # Number of BTB hits
|
||||
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
|
||||
system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
|
||||
system.cpu.fetch.icacheStallCycles 191636234 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.Insts 1263077256 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.Branches 225607243 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.predictedBranches 155872353 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.Cycles 392059630 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.SquashCycles 98480346 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.BlockedCycles 233495655 # Number of cycles fetch has spent blocked
|
||||
system.cpu.fetch.MiscStallCycles 26883 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
||||
system.cpu.fetch.PendingTrapStallCycles 277282 # Number of stall cycles due to pending traps
|
||||
system.cpu.fetch.CacheLines 183482871 # Number of cache lines fetched
|
||||
system.cpu.fetch.IcacheSquashes 3659349 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.rateDist::samples 901432928 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 2.597231 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 3.389695 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 513839664 57.00% 57.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 25974503 2.88% 59.88% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 29108148 3.23% 63.11% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 30308604 3.36% 66.48% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 19639160 2.18% 68.65% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 25619098 2.84% 71.50% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 32630243 3.62% 75.12% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 30828862 3.42% 78.54% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 193484646 21.46% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::total 901432928 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.branchRate 0.245259 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.rate 1.373096 # Number of inst fetches per cycle
|
||||
system.cpu.decode.IdleCycles 252952155 # Number of cycles decode is idle
|
||||
system.cpu.decode.BlockedCycles 185449202 # Number of cycles decode is blocked
|
||||
system.cpu.decode.RunCycles 329948666 # Number of cycles decode is running
|
||||
system.cpu.decode.UnblockCycles 49145661 # Number of cycles decode is unblocking
|
||||
system.cpu.decode.SquashCycles 83937244 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DecodedInsts 2290194252 # Number of instructions handled by decode
|
||||
system.cpu.decode.SquashedInsts 1 # Number of squashed instructions handled by decode
|
||||
system.cpu.rename.SquashCycles 83937244 # Number of cycles rename is squashing
|
||||
system.cpu.rename.IdleCycles 289581235 # Number of cycles rename is idle
|
||||
system.cpu.rename.BlockCycles 42452690 # Number of cycles rename is blocking
|
||||
system.cpu.rename.serializeStallCycles 14732 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RunCycles 340327979 # Number of cycles rename is running
|
||||
system.cpu.rename.UnblockCycles 145119048 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RenamedInsts 2240246263 # Number of instructions processed by rename
|
||||
system.cpu.rename.ROBFullEvents 3253 # Number of times rename has blocked due to ROB full
|
||||
system.cpu.rename.IQFullEvents 23409384 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.LSQFullEvents 104435988 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.FullRegisterEvents 12914 # Number of times there has been no free registers
|
||||
system.cpu.rename.RenamedOperands 2886886923 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RenameLookups 6492696430 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.int_rename_lookups 6491823905 # Number of integer rename lookups
|
||||
system.cpu.rename.fp_rename_lookups 872525 # Number of floating rename lookups
|
||||
system.cpu.rename.CommittedMaps 1993077484 # Number of HB maps that are committed
|
||||
system.cpu.rename.UndoneMaps 893809439 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.serializingInsts 1297 # count of serializing insts renamed
|
||||
system.cpu.rename.tempSerializingInsts 1279 # count of temporary serializing insts renamed
|
||||
system.cpu.rename.skidInsts 347581498 # count of insts added to the skid buffer
|
||||
system.cpu.memDep0.insertedLoads 540130264 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 217339026 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.conflictingLoads 215698631 # Number of conflicting loads.
|
||||
system.cpu.memDep0.conflictingStores 63624557 # Number of conflicting stores.
|
||||
system.cpu.iq.iqInstsAdded 2143116411 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqNonSpecInstsAdded 61984 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqInstsIssued 1846710444 # Number of instructions issued
|
||||
system.cpu.iq.iqSquashedInstsIssued 1594990 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedInstsExamined 612455576 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedOperandsExamined 1230055220 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 61431 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.issued_per_cycle::samples 901432928 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::mean 2.048639 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::stdev 1.805034 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::0 246353790 27.33% 27.33% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::1 156616035 17.37% 44.70% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::2 150729220 16.72% 61.42% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::3 147768173 16.39% 77.82% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::4 103385508 11.47% 89.29% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::5 58828894 6.53% 95.81% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::6 27652970 3.07% 98.88% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::7 9059576 1.01% 99.88% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::8 1038762 0.12% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::total 901432928 # Number of insts issued each cycle
|
||||
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntAlu 2653442 16.77% 16.77% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntMult 0 0.00% 16.77% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntDiv 0 0.00% 16.77% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatAdd 0 0.00% 16.77% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatCmp 0 0.00% 16.77% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatCvt 0 0.00% 16.77% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatMult 0 0.00% 16.77% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatDiv 0 0.00% 16.77% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 16.77% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdAdd 0 0.00% 16.77% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 16.77% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdAlu 0 0.00% 16.77% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdCmp 0 0.00% 16.77% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdCvt 0 0.00% 16.77% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdMisc 0 0.00% 16.77% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdMult 0 0.00% 16.77% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 16.77% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdShift 0 0.00% 16.77% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 16.77% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 16.77% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 16.77% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 16.77% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 16.77% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 16.77% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 16.77% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 16.77% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 16.77% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 16.77% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 16.77% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::MemRead 9987443 63.11% 79.88% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::MemWrite 3184017 20.12% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.FU_type_0::No_OpClass 2723282 0.15% 0.15% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntAlu 1219442774 66.03% 66.18% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntMult 0 0.00% 66.18% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.18% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 66.18% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.18% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.18% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.18% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.18% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.18% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.18% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.18% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.18% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.18% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.18% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.18% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.18% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.18% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.18% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.18% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.18% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.18% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.18% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.18% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.18% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.18% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.18% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.18% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.18% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.18% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::MemRead 447111847 24.21% 90.39% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::MemWrite 177432541 9.61% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::total 1846710444 # Type of FU issued
|
||||
system.cpu.iq.rate 2.007566 # Inst issue rate
|
||||
system.cpu.iq.fu_busy_cnt 15824902 # FU busy when requested
|
||||
system.cpu.iq.fu_busy_rate 0.008569 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.int_inst_queue_reads 4612265736 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_writes 2755596507 # Number of integer instruction queue writes
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 1806213833 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.fp_inst_queue_reads 7972 # Number of floating instruction queue reads
|
||||
system.cpu.iq.fp_inst_queue_writes 299756 # Number of floating instruction queue writes
|
||||
system.cpu.iq.fp_inst_queue_wakeup_accesses 262 # Number of floating instruction queue wakeup accesses
|
||||
system.cpu.iq.int_alu_accesses 1859809264 # Number of integer alu accesses
|
||||
system.cpu.iq.fp_alu_accesses 2800 # Number of floating point alu accesses
|
||||
system.cpu.iew.lsq.thread0.forwLoads 168051220 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread0.squashedLoads 156028104 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread0.ignoredResponses 428762 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread0.memOrderViolation 273999 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread0.squashedStores 68179105 # Number of stores squashed
|
||||
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
||||
system.cpu.iew.lsq.thread0.rescheduledLoads 6544 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread0.cacheBlocked 1 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||||
system.cpu.iew.iewSquashCycles 83937244 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewBlockCycles 7052726 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewUnblockCycles 1164788 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.iewDispatchedInsts 2143178395 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewDispSquashedInsts 2770813 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispLoadInsts 540130264 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispStoreInsts 217339290 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 5780 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewIQFullEvents 918370 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.iewLSQFullEvents 16344 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.memOrderViolationEvents 273999 # Number of memory order violations
|
||||
system.cpu.iew.predictedTakenIncorrect 10084956 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.iew.predictedNotTakenIncorrect 5239444 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.branchMispredicts 15324400 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewExecutedInsts 1818728049 # Number of executed instructions
|
||||
system.cpu.iew.iewExecLoadInsts 438648218 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 27982395 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
||||
system.cpu.iew.exec_nop 0 # number of nop insts executed
|
||||
system.cpu.iew.exec_refs 610505515 # number of memory reference insts executed
|
||||
system.cpu.iew.exec_branches 170830738 # Number of branches executed
|
||||
system.cpu.iew.exec_stores 171857297 # Number of stores executed
|
||||
system.cpu.iew.exec_rate 1.977147 # Inst execution rate
|
||||
system.cpu.iew.wb_sent 1813502289 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.wb_count 1806214095 # cumulative count of insts written-back
|
||||
system.cpu.iew.wb_producers 1379770015 # num instructions producing a value
|
||||
system.cpu.iew.wb_consumers 2939115295 # num instructions consuming a value
|
||||
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
||||
system.cpu.iew.wb_rate 1.963543 # insts written-back per cycle
|
||||
system.cpu.iew.wb_fanout 0.469451 # average fanout of values written-back
|
||||
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||
system.cpu.commit.commitCommittedInsts 826877144 # The number of committed instructions
|
||||
system.cpu.commit.commitCommittedOps 1528988756 # The number of committed instructions
|
||||
system.cpu.commit.commitSquashedInsts 614215075 # The number of squashed insts skipped by commit
|
||||
system.cpu.commit.commitNonSpecStalls 553 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu.commit.branchMispredicts 14315916 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.committed_per_cycle::samples 817495684 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::mean 1.870333 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::stdev 2.327982 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::0 301315612 36.86% 36.86% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::1 204371597 25.00% 61.86% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::2 73328146 8.97% 70.83% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::3 95079836 11.63% 82.46% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::4 30908814 3.78% 86.24% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::5 28772319 3.52% 89.76% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::6 16400347 2.01% 91.77% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::7 11729678 1.43% 93.20% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::8 55589335 6.80% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::total 817495684 # Number of insts commited each cycle
|
||||
system.cpu.commit.committedInsts 826877144 # Number of instructions committed
|
||||
system.cpu.commit.committedOps 1528988756 # Number of ops (including micro ops) committed
|
||||
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
||||
system.cpu.commit.refs 533262345 # Number of memory references committed
|
||||
system.cpu.commit.loads 384102160 # Number of loads committed
|
||||
system.cpu.commit.membars 0 # Number of memory barriers committed
|
||||
system.cpu.commit.branches 149758588 # Number of branches committed
|
||||
system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
|
||||
system.cpu.commit.int_insts 1528317614 # Number of committed integer instructions.
|
||||
system.cpu.commit.function_calls 0 # Number of function calls committed.
|
||||
system.cpu.commit.bw_lim_events 55589335 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
||||
system.cpu.rob.rob_reads 2905110180 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 4370460169 # The number of ROB writes
|
||||
system.cpu.timesIdled 411218 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 18442224 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.committedInsts 826877144 # Number of Instructions Simulated
|
||||
system.cpu.committedOps 1528988756 # Number of Ops (including micro ops) Simulated
|
||||
system.cpu.committedInsts_total 826877144 # Number of Instructions Simulated
|
||||
system.cpu.cpi 1.112469 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 1.112469 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 0.898901 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.898901 # IPC: Total IPC of All Threads
|
||||
system.cpu.int_regfile_reads 4004380471 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 2286341091 # number of integer regfile writes
|
||||
system.cpu.fp_regfile_reads 262 # number of floating regfile reads
|
||||
system.cpu.misc_regfile_reads 1001920300 # number of misc regfile reads
|
||||
system.cpu.icache.replacements 10653 # number of replacements
|
||||
system.cpu.icache.tagsinuse 997.180863 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 183252097 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 12174 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 15052.743305 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 997.180863 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.486905 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.486905 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 183258482 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 183258482 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 183258482 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 183258482 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 183258482 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 183258482 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 224389 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 224389 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 224389 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 224389 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 224389 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 224389 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 1641701500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 1641701500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 1641701500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 1641701500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 1641701500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 1641701500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 183482871 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 183482871 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 183482871 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 183482871 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 183482871 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 183482871 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001223 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.001223 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.001223 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.001223 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.001223 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.001223 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 7316.318982 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 7316.318982 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 7316.318982 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 7316.318982 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 7316.318982 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 7316.318982 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks::writebacks 8 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 8 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2536 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::total 2536 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::cpu.inst 2536 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::total 2536 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::cpu.inst 2536 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::total 2536 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 221853 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 221853 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 221853 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 221853 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 221853 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 221853 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 915847000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 915847000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 915847000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 915847000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 915847000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 915847000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001209 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001209 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001209 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.001209 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001209 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.001209 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 4128.170455 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 4128.170455 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 4128.170455 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 4128.170455 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 4128.170455 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 4128.170455 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 2527239 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 4087.019700 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 415133448 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 2531335 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 163.997830 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 2117139000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 4087.019700 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.997808 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.997808 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 266287966 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 266287966 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 148171236 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 148171236 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 414459202 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 414459202 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 414459202 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 414459202 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 2669585 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 2669585 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 988965 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 988965 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 3658550 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 3658550 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 3658550 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 3658550 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 39016731000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 39016731000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 20136479000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 20136479000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 59153210000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 59153210000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 59153210000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 59153210000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 268957551 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 268957551 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 149160201 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 149160201 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 418117752 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 418117752 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 418117752 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 418117752 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009926 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.009926 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006630 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.006630 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.008750 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.008750 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.008750 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.008750 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14615.279528 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 14615.279528 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 20361.164450 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 20361.164450 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 16168.484782 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 16168.484782 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 16168.484782 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 16168.484782 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 2229248 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 2229248 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 908413 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 908413 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 9153 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 9153 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 917566 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 917566 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 917566 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 917566 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1761172 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 1761172 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 979812 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 979812 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 2740984 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 2740984 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 2740984 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 2740984 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 14912272500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 14912272500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 17125192000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 17125192000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 32037464500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 32037464500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 32037464500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 32037464500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006548 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006548 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006569 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006569 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006556 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.006556 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006556 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.006556 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8467.243688 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 8467.243688 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 17478.038644 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 17478.038644 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11688.307739 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 11688.307739 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11688.307739 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 11688.307739 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 574865 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 21613.693664 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 3194256 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 594053 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 5.377056 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 253036052000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::writebacks 13760.767426 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 63.333478 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 7789.592760 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.419945 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.001933 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.237720 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.659598 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 6154 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 1427336 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 1433490 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 2229256 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 2229256 # number of Writeback hits
|
||||
system.cpu.l2cache.UpgradeReq_hits::cpu.data 1290 # number of UpgradeReq hits
|
||||
system.cpu.l2cache.UpgradeReq_hits::total 1290 # number of UpgradeReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 524130 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 524130 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 6154 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 1951466 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 1957620 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 6154 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 1951466 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 1957620 # number of overall hits
|
||||
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|
||||
system.cpu.l2cache.ReadReq_misses::cpu.data 332758 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 338684 # number of ReadReq misses
|
||||
system.cpu.l2cache.UpgradeReq_misses::cpu.data 208352 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_misses::total 208352 # number of UpgradeReq misses
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
system.cpu.l2cache.overall_misses::cpu.inst 5926 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 579785 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 585711 # number of overall misses
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 8462790000 # number of ReadExReq miss cycles
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 19823634500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 20026640000 # number of overall miss cycles
|
||||
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|
||||
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|
||||
system.cpu.l2cache.ReadReq_accesses::total 1772174 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 2229256 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 2229256 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 209642 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_accesses::total 209642 # number of UpgradeReq accesses(hits+misses)
|
||||
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|
||||
system.cpu.l2cache.ReadExReq_accesses::total 771157 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 12080 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 2531251 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 2543331 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 12080 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 2531251 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 2543331 # number of overall (read+write) accesses
|
||||
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|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.189057 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.191112 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.993847 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.993847 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.320333 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.320333 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.490563 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.229051 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.230293 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.490563 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.229051 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.230293 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34256.749916 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34141.461663 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 34143.478877 # average ReadReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 47.078982 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 47.078982 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34258.562829 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34258.562829 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34256.749916 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34191.354554 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 34192.016199 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34256.749916 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34191.354554 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 34192.016199 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks::writebacks 411201 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 411201 # number of writebacks
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 5926 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 332758 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::total 338684 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 208352 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses::total 208352 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 247027 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 247027 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 5926 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 579785 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 585711 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 5926 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 579785 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 585711 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 183905000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 10323225500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 10507130500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 6459209000 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 6459209000 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7658508000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7658508000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 183905000 # number of demand (read+write) MSHR miss cycles
|
||||
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|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 18165638500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 183905000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 17981733500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 18165638500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.490563 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.189057 # mshr miss rate for ReadReq accesses
|
||||
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|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.993847 # mshr miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.993847 # mshr miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.320333 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.320333 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.490563 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.229051 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.230293 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.490563 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.229051 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.230293 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31033.580830 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31023.222582 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31023.403822 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31001.425472 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31001.425472 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31002.716302 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31002.716302 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31033.580830 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31014.485542 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31014.678741 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31033.580830 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31014.485542 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31014.678741 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
@ -0,0 +1,138 @@
|
||||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
full_system=false
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
||||
[system]
|
||||
type=System
|
||||
children=cpu membus physmem
|
||||
boot_osflags=a
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
mem_mode=atomic
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
readfile=
|
||||
symbolfile=
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.membus.slave[0]
|
||||
|
||||
[system.cpu]
|
||||
type=AtomicSimpleCPU
|
||||
children=dtb interrupts itb tracer workload
|
||||
checker=Null
|
||||
clock=500
|
||||
cpu_id=0
|
||||
defer_registration=false
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
fastmem=false
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
interrupts=system.cpu.interrupts
|
||||
itb=system.cpu.itb
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
phase=0
|
||||
profile=0
|
||||
progress_interval=0
|
||||
simulate_data_stalls=false
|
||||
simulate_inst_stalls=false
|
||||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
width=1
|
||||
workload=system.cpu.workload
|
||||
dcache_port=system.membus.slave[2]
|
||||
icache_port=system.membus.slave[1]
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=X86TLB
|
||||
children=walker
|
||||
size=64
|
||||
walker=system.cpu.dtb.walker
|
||||
|
||||
[system.cpu.dtb.walker]
|
||||
type=X86PagetableWalker
|
||||
system=system
|
||||
port=system.membus.slave[4]
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=X86LocalApic
|
||||
int_latency=1000
|
||||
pio_addr=2305843009213693952
|
||||
pio_latency=1000
|
||||
system=system
|
||||
int_master=system.membus.slave[5]
|
||||
int_slave=system.membus.master[2]
|
||||
pio=system.membus.master[1]
|
||||
|
||||
[system.cpu.itb]
|
||||
type=X86TLB
|
||||
children=walker
|
||||
size=64
|
||||
walker=system.cpu.itb.walker
|
||||
|
||||
[system.cpu.itb.walker]
|
||||
type=X86PagetableWalker
|
||||
system=system
|
||||
port=system.membus.slave[3]
|
||||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
|
||||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=parser 2.1.dict -batch
|
||||
cwd=build/X86/tests/opt/long/se/20.parser/x86/linux/simple-atomic
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/cpu2000/binaries/x86/linux/parser
|
||||
gid=100
|
||||
input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
ppid=99
|
||||
simpoint=114600000000
|
||||
system=system
|
||||
uid=100
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave
|
||||
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.interrupts.int_master
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.membus.master[0]
|
||||
|
||||
@ -0,0 +1,4 @@
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: instruction 'fnstcw_Mw' unimplemented
|
||||
warn: instruction 'fldcw_Mw' unimplemented
|
||||
hack: be nice to actually delete the event here
|
||||
72
simulators/gem5/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout
Executable file
72
simulators/gem5/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout
Executable file
@ -0,0 +1,72 @@
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jun 4 2012 13:44:28
|
||||
gem5 started Jun 4 2012 15:38:11
|
||||
gem5 executing on zizzer
|
||||
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/simple-atomic
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
||||
Reading the dictionary files: *****************************info: Increasing stack size by one page.
|
||||
********************
|
||||
58924 words stored in 3784810 bytes
|
||||
|
||||
|
||||
Welcome to the Link Parser -- Version 2.1
|
||||
|
||||
Copyright (C) 1991-1995 Daniel Sleator and Davy Temperley
|
||||
|
||||
Processing sentences in batch mode
|
||||
|
||||
Echoing of input sentence turned on.
|
||||
* as had expected the party to be a success , it was a success
|
||||
* do you know where John 's
|
||||
* he said that , finding that it was impossible to get work as a waiter , he would work as a janitor
|
||||
info: Increasing stack size by one page.
|
||||
info: Increasing stack size by one page.
|
||||
* how fast the program is it
|
||||
* I am wondering whether to invite to the party
|
||||
* I gave him for his birthday it
|
||||
* I thought terrible after our discussion
|
||||
* I wonder how much money have you earned
|
||||
* Janet who is an expert on dogs helped me choose one
|
||||
* she interviewed more programmers than was hired
|
||||
* such flowers are found chiefly particularly in Europe
|
||||
* the dogs some of which were very large ran after the man
|
||||
* the man whom I play tennis is here
|
||||
* there is going to be an important meeting January
|
||||
* to pretend that our program is usable in its current form would be happy
|
||||
* we're thinking about going to a movie this theater
|
||||
* which dog you said you chased
|
||||
- also invited to the meeting were several prominent scientists
|
||||
- he ran home so quickly that his mother could hardly believe he had called from school
|
||||
- so many people attended that they spilled over into several neighboring fields
|
||||
- voting in favor of the bill were 36 Republicans and 4 moderate Democrats
|
||||
: Grace may not be possible to fix the problem
|
||||
any program as good as ours should be useful
|
||||
biochemically , I think the experiment has a lot of problems
|
||||
Fred has had five years of experience as a programmer
|
||||
he is looking for another job
|
||||
how did John do it
|
||||
how many more people do you think will come
|
||||
how much more spilled
|
||||
I have more money than John has time
|
||||
I made it clear that I was angry
|
||||
I wonder how John did it
|
||||
I wonder how much more quickly he ran
|
||||
invite John and whoever else you want to invite
|
||||
it is easier to ignore the problem than it is to solve it
|
||||
many who initially supported Thomas later changed their minds
|
||||
neither Mary nor Louise are coming to the party
|
||||
she interviewed more programmers than were hired
|
||||
telling Joe that Sue was coming to the party would create a real problem
|
||||
the man with whom I play tennis is here
|
||||
there is a dog in the park
|
||||
this is not the man we know and love
|
||||
we like to eat at restaurants , usually on weekends
|
||||
what did John say he thought you should do
|
||||
about 2 million people attended
|
||||
the five best costumes got prizes
|
||||
No errors!
|
||||
Exiting @ tick 885229360000 because target called exit()
|
||||
@ -0,0 +1,60 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.885229 # Number of seconds simulated
|
||||
sim_ticks 885229360000 # Number of ticks simulated
|
||||
final_tick 885229360000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1285236 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2376545 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1375933868 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 220604 # Number of bytes of host memory used
|
||||
host_seconds 643.37 # Real time elapsed on the host
|
||||
sim_insts 826877145 # Number of instructions simulated
|
||||
sim_ops 1528988757 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 8546776872 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 2285655660 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 10832432532 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 8546776872 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 8546776872 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::cpu.data 991849460 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 991849460 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 1068347109 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 384102189 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 1452449298 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::cpu.data 149160201 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 149160201 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 9654872803 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 2581992604 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 12236865406 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 9654872803 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 9654872803 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::cpu.data 1120443475 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 1120443475 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 9654872803 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 3702436078 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 13357308881 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu.workload.num_syscalls 551 # Number of system calls
|
||||
system.cpu.numCycles 1770458721 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 826877145 # Number of instructions committed
|
||||
system.cpu.committedOps 1528988757 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 1528317615 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 0 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 92658800 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 1528317615 # number of integer instructions
|
||||
system.cpu.num_fp_insts 0 # number of float instructions
|
||||
system.cpu.num_int_register_reads 4441632810 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 1993077484 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
|
||||
system.cpu.num_mem_refs 533262345 # number of memory refs
|
||||
system.cpu.num_load_insts 384102160 # Number of load instructions
|
||||
system.cpu.num_store_insts 149160185 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 1770458721 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
@ -0,0 +1,219 @@
|
||||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
full_system=false
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
||||
[system]
|
||||
type=System
|
||||
children=cpu membus physmem
|
||||
boot_osflags=a
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
mem_mode=atomic
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
readfile=
|
||||
symbolfile=
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.membus.slave[0]
|
||||
|
||||
[system.cpu]
|
||||
type=TimingSimpleCPU
|
||||
children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
|
||||
checker=Null
|
||||
clock=500
|
||||
cpu_id=0
|
||||
defer_registration=false
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
interrupts=system.cpu.interrupts
|
||||
itb=system.cpu.itb
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
phase=0
|
||||
profile=0
|
||||
progress_interval=0
|
||||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
workload=system.cpu.workload
|
||||
dcache_port=system.cpu.dcache.cpu_side
|
||||
icache_port=system.cpu.icache.cpu_side
|
||||
|
||||
[system.cpu.dcache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=262144
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.dcache_port
|
||||
mem_side=system.cpu.toL2Bus.slave[1]
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=X86TLB
|
||||
children=walker
|
||||
size=64
|
||||
walker=system.cpu.dtb.walker
|
||||
|
||||
[system.cpu.dtb.walker]
|
||||
type=X86PagetableWalker
|
||||
system=system
|
||||
port=system.cpu.toL2Bus.slave[3]
|
||||
|
||||
[system.cpu.icache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=131072
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.icache_port
|
||||
mem_side=system.cpu.toL2Bus.slave[0]
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=X86LocalApic
|
||||
int_latency=1000
|
||||
pio_addr=2305843009213693952
|
||||
pio_latency=1000
|
||||
system=system
|
||||
int_master=system.membus.slave[2]
|
||||
int_slave=system.membus.master[2]
|
||||
pio=system.membus.master[1]
|
||||
|
||||
[system.cpu.itb]
|
||||
type=X86TLB
|
||||
children=walker
|
||||
size=64
|
||||
walker=system.cpu.itb.walker
|
||||
|
||||
[system.cpu.itb.walker]
|
||||
type=X86PagetableWalker
|
||||
system=system
|
||||
port=system.cpu.toL2Bus.slave[2]
|
||||
|
||||
[system.cpu.l2cache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=false
|
||||
latency=10000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=2097152
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.toL2Bus.master[0]
|
||||
mem_side=system.membus.slave[1]
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
master=system.cpu.l2cache.cpu_side
|
||||
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
|
||||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
|
||||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=parser 2.1.dict -batch
|
||||
cwd=build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/cpu2000/binaries/x86/linux/parser
|
||||
gid=100
|
||||
input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
ppid=99
|
||||
simpoint=114600000000
|
||||
system=system
|
||||
uid=100
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave
|
||||
slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.membus.master[0]
|
||||
|
||||
@ -0,0 +1,4 @@
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: instruction 'fnstcw_Mw' unimplemented
|
||||
warn: instruction 'fldcw_Mw' unimplemented
|
||||
hack: be nice to actually delete the event here
|
||||
72
simulators/gem5/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout
Executable file
72
simulators/gem5/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout
Executable file
@ -0,0 +1,72 @@
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jun 4 2012 13:44:28
|
||||
gem5 started Jun 4 2012 15:45:58
|
||||
gem5 executing on zizzer
|
||||
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
||||
Reading the dictionary files: *****************************info: Increasing stack size by one page.
|
||||
********************
|
||||
58924 words stored in 3784810 bytes
|
||||
|
||||
|
||||
Welcome to the Link Parser -- Version 2.1
|
||||
|
||||
Copyright (C) 1991-1995 Daniel Sleator and Davy Temperley
|
||||
|
||||
Processing sentences in batch mode
|
||||
|
||||
Echoing of input sentence turned on.
|
||||
* as had expected the party to be a success , it was a success
|
||||
* do you know where John 's
|
||||
* he said that , finding that it was impossible to get work as a waiter , he would work as a janitor
|
||||
info: Increasing stack size by one page.
|
||||
info: Increasing stack size by one page.
|
||||
* how fast the program is it
|
||||
* I am wondering whether to invite to the party
|
||||
* I gave him for his birthday it
|
||||
* I thought terrible after our discussion
|
||||
* I wonder how much money have you earned
|
||||
* Janet who is an expert on dogs helped me choose one
|
||||
* she interviewed more programmers than was hired
|
||||
* such flowers are found chiefly particularly in Europe
|
||||
* the dogs some of which were very large ran after the man
|
||||
* the man whom I play tennis is here
|
||||
* there is going to be an important meeting January
|
||||
* to pretend that our program is usable in its current form would be happy
|
||||
* we're thinking about going to a movie this theater
|
||||
* which dog you said you chased
|
||||
- also invited to the meeting were several prominent scientists
|
||||
- he ran home so quickly that his mother could hardly believe he had called from school
|
||||
- so many people attended that they spilled over into several neighboring fields
|
||||
- voting in favor of the bill were 36 Republicans and 4 moderate Democrats
|
||||
: Grace may not be possible to fix the problem
|
||||
any program as good as ours should be useful
|
||||
biochemically , I think the experiment has a lot of problems
|
||||
Fred has had five years of experience as a programmer
|
||||
he is looking for another job
|
||||
how did John do it
|
||||
how many more people do you think will come
|
||||
how much more spilled
|
||||
I have more money than John has time
|
||||
I made it clear that I was angry
|
||||
I wonder how John did it
|
||||
I wonder how much more quickly he ran
|
||||
invite John and whoever else you want to invite
|
||||
it is easier to ignore the problem than it is to solve it
|
||||
many who initially supported Thomas later changed their minds
|
||||
neither Mary nor Louise are coming to the party
|
||||
she interviewed more programmers than were hired
|
||||
telling Joe that Sue was coming to the party would create a real problem
|
||||
the man with whom I play tennis is here
|
||||
there is a dog in the park
|
||||
this is not the man we know and love
|
||||
we like to eat at restaurants , usually on weekends
|
||||
what did John say he thought you should do
|
||||
about 2 million people attended
|
||||
the five best costumes got prizes
|
||||
No errors!
|
||||
Exiting @ tick 1658729604000 because target called exit()
|
||||
@ -0,0 +1,377 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 1.658730 # Number of seconds simulated
|
||||
sim_ticks 1658729604000 # Number of ticks simulated
|
||||
final_tick 1658729604000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 615589 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1138293 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1234881669 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 229524 # Number of bytes of host memory used
|
||||
host_seconds 1343.23 # Real time elapsed on the host
|
||||
sim_insts 826877145 # Number of instructions simulated
|
||||
sim_ops 1528988757 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 148544 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 36946432 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 37094976 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 148544 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 148544 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 26349376 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 26349376 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 2321 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 577288 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 579609 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 411709 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 411709 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 89553 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 22273933 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 22363486 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 89553 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 89553 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 15885275 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 15885275 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 15885275 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 89553 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 22273933 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 38248761 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu.workload.num_syscalls 551 # Number of system calls
|
||||
system.cpu.numCycles 3317459208 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 826877145 # Number of instructions committed
|
||||
system.cpu.committedOps 1528988757 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 1528317615 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 0 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 92658800 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 1528317615 # number of integer instructions
|
||||
system.cpu.num_fp_insts 0 # number of float instructions
|
||||
system.cpu.num_int_register_reads 4441632810 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 1993077484 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
|
||||
system.cpu.num_mem_refs 533262345 # number of memory refs
|
||||
system.cpu.num_load_insts 384102160 # Number of load instructions
|
||||
system.cpu.num_store_insts 149160185 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 3317459208 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.icache.replacements 1253 # number of replacements
|
||||
system.cpu.icache.tagsinuse 882.231489 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 1068344296 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 2814 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 379653.267946 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 882.231489 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.430777 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.430777 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 1068344296 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 1068344296 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 1068344296 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 1068344296 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 1068344296 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 1068344296 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 2814 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 2814 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 2814 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 2814 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 2814 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 2814 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 136878000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 136878000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 136878000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 136878000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 136878000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 136878000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 1068347110 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 1068347110 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 1068347110 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 1068347110 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 1068347110 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 1068347110 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000003 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.000003 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000003 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.000003 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000003 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000003 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48641.791045 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 48641.791045 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 48641.791045 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 48641.791045 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 48641.791045 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 48641.791045 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 2814 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 2814 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 2814 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 2814 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 2814 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 2814 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 128436000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 128436000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 128436000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 128436000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 128436000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 128436000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000003 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000003 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000003 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 45641.791045 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 45641.791045 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 45641.791045 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 45641.791045 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 45641.791045 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 45641.791045 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 2514362 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 4086.472055 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 530743932 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 2518458 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 210.741625 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 8216675000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 4086.472055 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.997674 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.997674 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 382374775 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 382374775 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 148369157 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 148369157 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 530743932 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 530743932 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 530743932 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 530743932 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 1727414 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 1727414 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 791044 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 791044 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 2518458 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 2518458 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 2518458 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 2518458 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 38012508000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 38012508000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 21492013500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 21492013500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 59504521500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 59504521500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 59504521500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 59504521500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 384102189 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 384102189 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 149160201 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 149160201 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 533262390 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 533262390 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 533262390 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 533262390 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004497 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.004497 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005303 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.005303 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.004723 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.004723 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.004723 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.004723 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22005.441660 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 22005.441660 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27169.175798 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 27169.175798 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 23627.363053 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 23627.363053 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 23627.363053 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 23627.363053 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 2223170 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 2223170 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1727414 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 1727414 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 791044 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 791044 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 2518458 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 2518458 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 2518458 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 2518458 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 32830264000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 32830264000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 19118876000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 19118876000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 51949140000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 51949140000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 51949140000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 51949140000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.004497 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.004497 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005303 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005303 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.004723 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.004723 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.004723 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.004723 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19005.440502 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19005.440502 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24169.168845 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24169.168845 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20627.360075 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 20627.360075 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20627.360075 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 20627.360075 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 568906 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 21228.193311 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 3146531 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 587958 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 5.351625 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 896565143000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::writebacks 13679.064710 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 30.006309 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 7519.122292 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.417452 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.000916 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.229465 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.647833 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 493 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 1398159 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 1398652 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 2223170 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 2223170 # number of Writeback hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 543011 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 543011 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 493 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 1941170 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 1941663 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 493 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 1941170 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 1941663 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 2321 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.data 329255 # number of ReadReq misses
|
||||
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|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 248033 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 248033 # number of ReadExReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 2321 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 577288 # number of demand (read+write) misses
|
||||
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|
||||
system.cpu.l2cache.overall_misses::cpu.inst 2321 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 577288 # number of overall misses
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 12897722000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 12897722000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 120692000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 30018982000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 30139674000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 120692000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 30018982000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 30139674000 # number of overall miss cycles
|
||||
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|
||||
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|
||||
system.cpu.l2cache.ReadReq_accesses::total 1730228 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 2223170 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 2223170 # number of Writeback accesses(hits+misses)
|
||||
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|
||||
system.cpu.l2cache.ReadExReq_accesses::total 791044 # number of ReadExReq accesses(hits+misses)
|
||||
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|
||||
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|
||||
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|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 2814 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 2518458 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 2521272 # number of overall (read+write) accesses
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.313551 # miss rate for ReadExReq accesses
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
system.cpu.l2cache.overall_miss_rate::total 0.229888 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000.024190 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000.024190 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000.010393 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52000.010352 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000.010393 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52000.010352 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks::writebacks 411709 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 411709 # number of writebacks
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2321 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 329255 # number of ReadReq MSHR misses
|
||||
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|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 248033 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 248033 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 2321 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 577288 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 579609 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2321 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 577288 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 579609 # number of overall MSHR misses
|
||||
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|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 13170200000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13263040000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 9921320000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 9921320000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 92840000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 23091520000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 23184360000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 92840000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 23091520000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 23184360000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.824805 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.190606 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.191637 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.313551 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.313551 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.824805 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.229223 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.229888 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.824805 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.229223 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.229888 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
Reference in New Issue
Block a user