Adding gem5 source to svn.

git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1819 8c4709b5-6ec9-48aa-a5cd-a96041d1645a

simulators/gem5/tests/long/se/10.mcf/ref/arm/linux/o3-timing/chair.cook.ppm

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simulators/gem5/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini

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simulators/gem5/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simerr

@@ -0,0 +1,2 @@
+warn: Sockets disabled, not accepting gdb connections
+hack: be nice to actually delete the event here

simulators/gem5/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout

@@ -0,0 +1,26 @@
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jun  4 2012 12:14:06
+gem5 started Jun  4 2012 17:32:09
+gem5 executing on zizzer
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0.  Starting simulation...
+
+MCF SPEC version 1.6.I
+by  Andreas Loebel
+Copyright (c) 1998,1999   ZIB Berlin
+All Rights Reserved.
+
+nodes                      : 500
+active arcs                : 1905
+simplex iterations         : 1502
+flow value                 : 4990014995
+new implicit arcs          : 23867
+active arcs                : 25772
+simplex iterations         : 2663
+flow value                 : 3080014995
+checksum                   : 68389
+optimal
+Exiting @ tick 25988864000 because target called exit()

simulators/gem5/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt

@@ -0,0 +1,709 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds                                  0.025989                       # Number of seconds simulated
+sim_ticks                                 25988864000                       # Number of ticks simulated
+final_tick                                25988864000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                 141606                       # Simulator instruction rate (inst/s)
+host_op_rate                                   142623                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               40620332                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 364696                       # Number of bytes of host memory used
+host_seconds                                   639.80                       # Real time elapsed on the host
+sim_insts                                    90599356                       # Number of instructions simulated
+sim_ops                                      91249910                       # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu.inst             46144                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data            952896                       # Number of bytes read from this memory
+system.physmem.bytes_read::total               999040                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        46144                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           46144                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks         2048                       # Number of bytes written to this memory
+system.physmem.bytes_written::total              2048                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst                721                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data              14889                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                 15610                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks              32                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total                   32                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst              1775530                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             36665550                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                38441080                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         1775530                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            1775530                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks             78803                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                  78803                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks             78803                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             1775530                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            36665550                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               38519883                       # Total bandwidth to/from this memory (bytes/s)
+system.cpu.dtb.inst_hits                            0                       # ITB inst hits
+system.cpu.dtb.inst_misses                          0                       # ITB inst misses
+system.cpu.dtb.read_hits                            0                       # DTB read hits
+system.cpu.dtb.read_misses                          0                       # DTB read misses
+system.cpu.dtb.write_hits                           0                       # DTB write hits
+system.cpu.dtb.write_misses                         0                       # DTB write misses
+system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                        0                       # DTB read accesses
+system.cpu.dtb.write_accesses                       0                       # DTB write accesses
+system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.dtb.hits                                 0                       # DTB hits
+system.cpu.dtb.misses                               0                       # DTB misses
+system.cpu.dtb.accesses                             0                       # DTB accesses
+system.cpu.itb.inst_hits                            0                       # ITB inst hits
+system.cpu.itb.inst_misses                          0                       # ITB inst misses
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
+system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
+system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.itb.hits                                 0                       # DTB hits
+system.cpu.itb.misses                               0                       # DTB misses
+system.cpu.itb.accesses                             0                       # DTB accesses
+system.cpu.workload.num_syscalls                  442                       # Number of system calls
+system.cpu.numCycles                         51977729                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.BPredUnit.lookups                 27100787                       # Number of BP lookups
+system.cpu.BPredUnit.condPredicted           22324909                       # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect             913851                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups              11625204                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                 11498872                       # Number of BTB hits
+system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.BPredUnit.usedRAS                    61157                       # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect               10323                       # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles           14508615                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      130146910                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    27100787                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           11560029                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                      24493529                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 4999674                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles                8879281                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                    2                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles            50                       # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines                  14156722                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                388066                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples           51938784                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.527703                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.247354                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 27487299     52.92%     52.92% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  3456218      6.65%     59.58% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  2037280      3.92%     63.50% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                  1594827      3.07%     66.57% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  1702478      3.28%     69.85% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                  2979904      5.74%     75.59% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                  1536396      2.96%     78.54% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  1112311      2.14%     80.68% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                 10032071     19.32%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::total             51938784                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.521392                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        2.503898                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 17258666                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles               6822276                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  22930941                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles                878432                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                4048469                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved              4484484                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                  8960                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              128309268                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                 42973                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                4048469                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 19038937                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                 2026641                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles         195067                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  21988132                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles               4641538                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              124853766                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                    22                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                 286024                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents               3901771                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents              441                       # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands           145615724                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups             543819179                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        543813062                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups              6117                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps             107429479                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                 38186245                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts              20008                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts          20006                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  11296413                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             29738779                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores             5601526                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           2062082                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          1203344                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  119239629                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded               22672                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 105633795                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued             86270                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        27804178                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     69103102                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved          12544                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples      51938784                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         2.033813                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.918657                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            14084713     27.12%     27.12% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            11449450     22.04%     49.16% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2             8003608     15.41%     64.57% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3             6710442     12.92%     77.49% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4             5305637     10.22%     87.71% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5             2900837      5.59%     93.29% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             2546575      4.90%     98.19% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7              460556      0.89%     99.08% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              476966      0.92%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total        51938784                       # Number of insts issued each cycle
+system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                   33927      5.08%      5.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                     27      0.00%      5.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      5.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      5.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      5.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      5.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      5.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      5.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      5.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      5.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      5.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      5.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      5.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      5.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      5.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      5.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      5.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      5.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      5.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      5.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      5.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      5.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      5.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      5.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      5.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      5.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      5.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      5.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      5.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                 354815     53.12%     58.20% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                279170     41.80%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
+system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu              74740578     70.75%     70.75% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                10525      0.01%     70.76% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     70.76% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     70.76% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     70.76% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     70.76% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     70.76% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     70.76% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     70.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     70.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     70.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     70.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     70.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     70.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     70.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     70.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     70.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     70.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     70.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     70.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     70.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     70.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               1      0.00%     70.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt             195      0.00%     70.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     70.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc            237      0.00%     70.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     70.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            2      0.00%     70.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     70.76% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             25722669     24.35%     95.12% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite             5159588      4.88%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::total              105633795                       # Type of FU issued
+system.cpu.iq.rate                           2.032290                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                      667939                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.006323                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          263959647                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         147067415                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    102938725                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads                 936                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes               1347                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses          404                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              106301267                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                     467                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads           423068                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
+system.cpu.iew.lsq.thread0.squashedLoads      7162902                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses         8413                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation         3100                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores       854772                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
+system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
+system.cpu.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked         39235                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
+system.cpu.iew.iewSquashCycles                4048469                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                  193737                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                 33246                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           119298911                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            399459                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts              29738779                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts              5601526                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts              18769                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                  13636                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                  1014                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents           3100                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         499711                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       490212                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts               989923                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             104558374                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              25377273                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           1075421                       # Number of squashed instructions skipped in execute
+system.cpu.iew.exec_swp                             0                       # number of swp insts executed
+system.cpu.iew.exec_nop                         36610                       # number of nop insts executed
+system.cpu.iew.exec_refs                     30470186                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 21355608                       # Number of branches executed
+system.cpu.iew.exec_stores                    5092913                       # Number of stores executed
+system.cpu.iew.exec_rate                     2.011600                       # Inst execution rate
+system.cpu.iew.wb_sent                      103258351                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     102939129                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                  62202150                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 103963576                       # num instructions consuming a value
+system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
+system.cpu.iew.wb_rate                       1.980447                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.598307                       # average fanout of values written-back
+system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu.commit.commitCommittedInsts       90611965                       # The number of committed instructions
+system.cpu.commit.commitCommittedOps         91262519                       # The number of committed instructions
+system.cpu.commit.commitSquashedInsts        28037719                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls           10128                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts            916929                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples     47890316                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.905657                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.507554                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     17540600     36.63%     36.63% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     13534361     28.26%     64.89% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2      4502880      9.40%     74.29% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      3873758      8.09%     82.38% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      1516151      3.17%     85.54% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5       799389      1.67%     87.21% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6       846315      1.77%     88.98% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7       253211      0.53%     89.51% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      5023651     10.49%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total     47890316                       # Number of insts commited each cycle
+system.cpu.commit.committedInsts             90611965                       # Number of instructions committed
+system.cpu.commit.committedOps               91262519                       # Number of ops (including micro ops) committed
+system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
+system.cpu.commit.refs                       27322631                       # Number of memory references committed
+system.cpu.commit.loads                      22575877                       # Number of loads committed
+system.cpu.commit.membars                        3888                       # Number of memory barriers committed
+system.cpu.commit.branches                   18722471                       # Number of branches committed
+system.cpu.commit.fp_insts                         48                       # Number of committed floating point instructions.
+system.cpu.commit.int_insts                  72533322                       # Number of committed integer instructions.
+system.cpu.commit.function_calls                56148                       # Number of function calls committed.
+system.cpu.commit.bw_lim_events               5023651                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
+system.cpu.rob.rob_reads                    162161169                       # The number of ROB reads
+system.cpu.rob.rob_writes                   242671240                       # The number of ROB writes
+system.cpu.timesIdled                            1828                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                           38945                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.committedInsts                    90599356                       # Number of Instructions Simulated
+system.cpu.committedOps                      91249910                       # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total              90599356                       # Number of Instructions Simulated
+system.cpu.cpi                               0.573710                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.573710                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.743042                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.743042                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                497076309                       # number of integer regfile reads
+system.cpu.int_regfile_writes               120895703                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                       198                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                      527                       # number of floating regfile writes
+system.cpu.misc_regfile_reads               183813486                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                  11604                       # number of misc regfile writes
+system.cpu.icache.replacements                      3                       # number of replacements
+system.cpu.icache.tagsinuse                649.670012                       # Cycle average of tags in use
+system.cpu.icache.total_refs                 14155750                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                    749                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs               18899.532710                       # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::cpu.inst     649.670012                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.317222                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.317222                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst     14155750                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        14155750                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      14155750                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         14155750                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     14155750                       # number of overall hits
+system.cpu.icache.overall_hits::total        14155750                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst          972                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total           972                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst          972                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total            972                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst          972                       # number of overall misses
+system.cpu.icache.overall_misses::total           972                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     33892500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     33892500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     33892500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     33892500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     33892500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     33892500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     14156722                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     14156722                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     14156722                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     14156722                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     14156722                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     14156722                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000069                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.000069                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000069                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.000069                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000069                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.000069                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34868.827160                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 34868.827160                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 34868.827160                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 34868.827160                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 34868.827160                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 34868.827160                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.icache.fast_writes                       0                       # number of fast writes performed
+system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst          223                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total          223                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst          223                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total          223                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst          223                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total          223                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst          749                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total          749                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst          749                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total          749                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst          749                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total          749                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     25625000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     25625000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     25625000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     25625000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     25625000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     25625000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000053                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000053                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000053                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.000053                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000053                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.000053                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34212.283044                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 34212.283044                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34212.283044                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 34212.283044                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34212.283044                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 34212.283044                       # average overall mshr miss latency
+system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.replacements                 943602                       # number of replacements
+system.cpu.dcache.tagsinuse               3646.405021                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                 28436874                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                 947698                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                  30.006261                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle             8214901000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data    3646.405021                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.890236                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.890236                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data     23866253                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        23866253                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      4558926                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        4558926                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data         5898                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total         5898                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data         5797                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total         5797                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data      28425179                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         28425179                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     28425179                       # number of overall hits
+system.cpu.dcache.overall_hits::total        28425179                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      1004103                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       1004103                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       176055                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       176055                       # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data            8                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total            8                       # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses::cpu.data      1180158                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        1180158                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      1180158                       # number of overall misses
+system.cpu.dcache.overall_misses::total       1180158                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data   5784178500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total   5784178500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data   4612267011                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   4612267011                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       129000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total       129000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  10396445511                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  10396445511                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  10396445511                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  10396445511                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     24870356                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     24870356                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data      4734981                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total      4734981                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data         5906                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total         5906                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data         5797                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total         5797                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     29605337                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     29605337                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     29605337                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     29605337                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.040373                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.040373                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.037182                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.037182                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.001355                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.001355                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.039863                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.039863                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.039863                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.039863                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data  5760.542992                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total  5760.542992                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26197.875726                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 26197.875726                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        16125                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        16125                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data  8809.367484                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total  8809.367484                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data  8809.367484                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total  8809.367484                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs     23104055                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs              8078                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs  2860.120698                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.writebacks::writebacks       942908                       # number of writebacks
+system.cpu.dcache.writebacks::total            942908                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data        99918                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total        99918                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data       132542                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total       132542                       # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data            8                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total            8                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data       232460                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total       232460                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data       232460                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total       232460                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data       904185                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       904185                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data        43513                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total        43513                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data       947698                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       947698                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       947698                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       947698                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   2402147500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   2402147500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   1077084130                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   1077084130                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data   3479231630                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total   3479231630                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data   3479231630                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total   3479231630                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.036356                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.036356                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.009190                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.009190                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.032011                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.032011                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.032011                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.032011                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data  2656.699127                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total  2656.699127                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24753.157217                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24753.157217                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data  3671.245091                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total  3671.245091                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data  3671.245091                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total  3671.245091                       # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.l2cache.replacements                   770                       # number of replacements
+system.cpu.l2cache.tagsinuse             10017.166349                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                 1600694                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                 15595                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                102.641488                       # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::writebacks  9634.775304                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst    182.147356                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data    200.243688                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks     0.294030                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst     0.005559                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.006111                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.305700                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst           27                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data       902746                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total         902773                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks       942908                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total       942908                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data        30054                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total        30054                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst           27                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data       932800                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total          932827                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst           27                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data       932800                       # number of overall hits
+system.cpu.l2cache.overall_hits::total         932827                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst          722                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data          364                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total         1086                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data        14534                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total        14534                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst          722                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data        14898                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total         15620                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst          722                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data        14898                       # number of overall misses
+system.cpu.l2cache.overall_misses::total        15620                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     24755500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data     12471500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total     37227000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    499277500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total    499277500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     24755500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data    511749000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total    536504500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     24755500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data    511749000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total    536504500                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst          749                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data       903110                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total       903859                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks       942908                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total       942908                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data        44588                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total        44588                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst          749                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data       947698                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total       948447                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst          749                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data       947698                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total       948447                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.963952                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.000403                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.001202                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.325962                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.325962                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.963952                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.015720                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.016469                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.963952                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.015720                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.016469                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34287.396122                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34262.362637                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 34279.005525                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34352.380625                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34352.380625                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34287.396122                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34350.181232                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 34347.279129                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34287.396122                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34350.181232                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 34347.279129                       # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
+system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
+system.cpu.l2cache.writebacks::writebacks           32                       # number of writebacks
+system.cpu.l2cache.writebacks::total               32                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            1                       # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.data            9                       # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::total           10                       # number of ReadReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.inst            1                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data            9                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total           10                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.inst            1                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.data            9                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total           10                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          721                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data          355                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total         1076                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        14534                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total        14534                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst          721                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data        14889                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total        15610                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst          721                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data        14889                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total        15610                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     22414000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     11074500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total     33488500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    452032500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    452032500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     22414000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    463107000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    485521000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     22414000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    463107000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    485521000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.962617                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.000393                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.001190                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.325962                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.325962                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.962617                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.015711                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.016458                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.962617                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.015711                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.016458                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31087.378641                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31195.774648                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31123.141264                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31101.726985                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31101.726985                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31087.378641                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31103.969373                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31103.203075                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31087.378641                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31103.969373                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31103.203075                       # average overall mshr miss latency
+system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+
+---------- End Simulation Statistics   ----------

simulators/gem5/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/chair.cook.ppm

@@ -0,0 +1,4 @@
+P6
+15 15
+255
+

simulators/gem5/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini

@@ -0,0 +1,135 @@
+[root]
+type=Root
+children=system
+full_system=false
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
+mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
+readfile=
+symbolfile=
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.slave[0]
+
+[system.cpu]
+type=AtomicSimpleCPU
+children=dtb interrupts itb tracer workload
+checker=Null
+clock=500
+cpu_id=0
+defer_registration=false
+do_checkpoint_insts=true
+do_quiesce=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+fastmem=false
+function_trace=false
+function_trace_start=0
+interrupts=system.cpu.interrupts
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+phase=0
+profile=0
+progress_interval=0
+simulate_data_stalls=false
+simulate_inst_stalls=false
+system=system
+tracer=system.cpu.tracer
+width=1
+workload=system.cpu.workload
+dcache_port=system.membus.slave[2]
+icache_port=system.membus.slave[1]
+
+[system.cpu.dtb]
+type=ArmTLB
+children=walker
+size=64
+walker=system.cpu.dtb.walker
+
+[system.cpu.dtb.walker]
+type=ArmTableWalker
+max_backoff=100000
+min_backoff=0
+sys=system
+port=system.membus.slave[4]
+
+[system.cpu.interrupts]
+type=ArmInterrupts
+
+[system.cpu.itb]
+type=ArmTLB
+children=walker
+size=64
+walker=system.cpu.itb.walker
+
+[system.cpu.itb.walker]
+type=ArmTableWalker
+max_backoff=100000
+min_backoff=0
+sys=system
+port=system.membus.slave[3]
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=mcf mcf.in
+cwd=build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-atomic
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/dist/m5/cpu2000/binaries/arm/linux/mcf
+gid=100
+input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=55300000000
+system=system
+uid=100
+
+[system.membus]
+type=CoherentBus
+block_size=64
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+master=system.physmem.port[0]
+slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port
+
+[system.physmem]
+type=SimpleMemory
+conf_table_reported=false
+file=
+in_addr_map=true
+latency=30000
+latency_var=0
+null=false
+range=0:268435455
+zero=false
+port=system.membus.master[0]
+

simulators/gem5/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/mcf.out

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+95

simulators/gem5/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simerr

@@ -0,0 +1,2 @@
+warn: Sockets disabled, not accepting gdb connections
+hack: be nice to actually delete the event here

simulators/gem5/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simout

@@ -0,0 +1,26 @@
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jun  4 2012 12:14:06
+gem5 started Jun  4 2012 17:36:14
+gem5 executing on zizzer
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-atomic
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0.  Starting simulation...
+
+MCF SPEC version 1.6.I
+by  Andreas Loebel
+Copyright (c) 1998,1999   ZIB Berlin
+All Rights Reserved.
+
+nodes                      : 500
+active arcs                : 1905
+simplex iterations         : 1502
+flow value                 : 4990014995
+new implicit arcs          : 23867
+active arcs                : 25772
+simplex iterations         : 2663
+flow value                 : 3080014995
+checksum                   : 68389
+optimal
+Exiting @ tick 54240666000 because target called exit()

simulators/gem5/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt

@@ -0,0 +1,102 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds                                  0.054241                       # Number of seconds simulated
+sim_ticks                                 54240666000                       # Number of ticks simulated
+final_tick                                54240666000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                2223712                       # Simulator instruction rate (inst/s)
+host_op_rate                                  2239678                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1331261387                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 354056                       # Number of bytes of host memory used
+host_seconds                                    40.74                       # Real time elapsed on the host
+sim_insts                                    90602415                       # Number of instructions simulated
+sim_ops                                      91252969                       # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu.inst         431323116                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          90016599                       # Number of bytes read from this memory
+system.physmem.bytes_read::total            521339715                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst    431323116                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total       431323116                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::cpu.data       18908138                       # Number of bytes written to this memory
+system.physmem.bytes_written::total          18908138                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst          107830779                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data           22553295                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total             130384074                       # Number of read requests responded to by this memory
+system.physmem.num_writes::cpu.data           4738868                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total              4738868                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst           7952024704                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data           1659577687                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              9611602391                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst      7952024704                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total         7952024704                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data           348597084                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total              348597084                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst          7952024704                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data          2008174771                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total             9960199475                       # Total bandwidth to/from this memory (bytes/s)
+system.cpu.dtb.inst_hits                            0                       # ITB inst hits
+system.cpu.dtb.inst_misses                          0                       # ITB inst misses
+system.cpu.dtb.read_hits                            0                       # DTB read hits
+system.cpu.dtb.read_misses                          0                       # DTB read misses
+system.cpu.dtb.write_hits                           0                       # DTB write hits
+system.cpu.dtb.write_misses                         0                       # DTB write misses
+system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                        0                       # DTB read accesses
+system.cpu.dtb.write_accesses                       0                       # DTB write accesses
+system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.dtb.hits                                 0                       # DTB hits
+system.cpu.dtb.misses                               0                       # DTB misses
+system.cpu.dtb.accesses                             0                       # DTB accesses
+system.cpu.itb.inst_hits                            0                       # ITB inst hits
+system.cpu.itb.inst_misses                          0                       # ITB inst misses
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
+system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
+system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.itb.hits                                 0                       # DTB hits
+system.cpu.itb.misses                               0                       # DTB misses
+system.cpu.itb.accesses                             0                       # DTB accesses
+system.cpu.workload.num_syscalls                  442                       # Number of system calls
+system.cpu.numCycles                        108481333                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.committedInsts                    90602415                       # Number of instructions committed
+system.cpu.committedOps                      91252969                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses              72525682                       # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses                     48                       # Number of float alu accesses
+system.cpu.num_func_calls                       96832                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts     15548926                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                     72525682                       # number of integer instructions
+system.cpu.num_fp_insts                            48                       # number of float instructions
+system.cpu.num_int_register_reads           396912516                       # number of times the integer registers were read
+system.cpu.num_int_register_writes          106840370                       # number of times the integer registers were written
+system.cpu.num_fp_register_reads                   54                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes                  30                       # number of times the floating registers were written
+system.cpu.num_mem_refs                      27318811                       # number of memory refs
+system.cpu.num_load_insts                    22573967                       # Number of load instructions
+system.cpu.num_store_insts                    4744844                       # Number of store instructions
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
+system.cpu.num_busy_cycles                  108481333                       # Number of busy cycles
+system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                            0                       # Percentage of idle cycles
+
+---------- End Simulation Statistics   ----------

simulators/gem5/tests/long/se/10.mcf/ref/arm/linux/simple-timing/chair.cook.ppm

@@ -0,0 +1,4 @@
+P6
+15 15
+255
+

simulators/gem5/tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini

@@ -0,0 +1,216 @@
+[root]
+type=Root
+children=system
+full_system=false
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
+mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
+readfile=
+symbolfile=
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.slave[0]
+
+[system.cpu]
+type=TimingSimpleCPU
+children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
+checker=Null
+clock=500
+cpu_id=0
+defer_registration=false
+do_checkpoint_insts=true
+do_quiesce=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+function_trace=false
+function_trace_start=0
+interrupts=system.cpu.interrupts
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+phase=0
+profile=0
+progress_interval=0
+system=system
+tracer=system.cpu.tracer
+workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.dcache]
+type=BaseCache
+addr_ranges=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+prefetch_on_access=false
+prefetcher=Null
+prioritizeRequests=false
+repl=Null
+size=262144
+subblock_size=0
+system=system
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.slave[1]
+
+[system.cpu.dtb]
+type=ArmTLB
+children=walker
+size=64
+walker=system.cpu.dtb.walker
+
+[system.cpu.dtb.walker]
+type=ArmTableWalker
+max_backoff=100000
+min_backoff=0
+sys=system
+port=system.cpu.toL2Bus.slave[3]
+
+[system.cpu.icache]
+type=BaseCache
+addr_ranges=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+prefetch_on_access=false
+prefetcher=Null
+prioritizeRequests=false
+repl=Null
+size=131072
+subblock_size=0
+system=system
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.slave[0]
+
+[system.cpu.interrupts]
+type=ArmInterrupts
+
+[system.cpu.itb]
+type=ArmTLB
+children=walker
+size=64
+walker=system.cpu.itb.walker
+
+[system.cpu.itb.walker]
+type=ArmTableWalker
+max_backoff=100000
+min_backoff=0
+sys=system
+port=system.cpu.toL2Bus.slave[2]
+
+[system.cpu.l2cache]
+type=BaseCache
+addr_ranges=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=false
+latency=10000
+max_miss_count=0
+mshrs=10
+prefetch_on_access=false
+prefetcher=Null
+prioritizeRequests=false
+repl=Null
+size=2097152
+subblock_size=0
+system=system
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.master[0]
+mem_side=system.membus.slave[1]
+
+[system.cpu.toL2Bus]
+type=CoherentBus
+block_size=64
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+master=system.cpu.l2cache.cpu_side
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=mcf mcf.in
+cwd=build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-timing
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/dist/m5/cpu2000/binaries/arm/linux/mcf
+gid=100
+input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=55300000000
+system=system
+uid=100
+
+[system.membus]
+type=CoherentBus
+block_size=64
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+master=system.physmem.port[0]
+slave=system.system_port system.cpu.l2cache.mem_side
+
+[system.physmem]
+type=SimpleMemory
+conf_table_reported=false
+file=
+in_addr_map=true
+latency=30000
+latency_var=0
+null=false
+range=0:268435455
+zero=false
+port=system.membus.master[0]
+

simulators/gem5/tests/long/se/10.mcf/ref/arm/linux/simple-timing/mcf.out

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simulators/gem5/tests/long/se/10.mcf/ref/arm/linux/simple-timing/simerr

@@ -0,0 +1,2 @@
+warn: Sockets disabled, not accepting gdb connections
+hack: be nice to actually delete the event here

simulators/gem5/tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout

@@ -0,0 +1,26 @@
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jun  4 2012 12:14:06
+gem5 started Jun  4 2012 17:37:05
+gem5 executing on zizzer
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-timing
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0.  Starting simulation...
+
+MCF SPEC version 1.6.I
+by  Andreas Loebel
+Copyright (c) 1998,1999   ZIB Berlin
+All Rights Reserved.
+
+nodes                      : 500
+active arcs                : 1905
+simplex iterations         : 1502
+flow value                 : 4990014995
+new implicit arcs          : 23867
+active arcs                : 25772
+simplex iterations         : 2663
+flow value                 : 3080014995
+checksum                   : 68389
+optimal
+Exiting @ tick 148086239000 because target called exit()

simulators/gem5/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt

@@ -0,0 +1,427 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds                                  0.148086                       # Number of seconds simulated
+sim_ticks                                148086239000                       # Number of ticks simulated
+final_tick                               148086239000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                1056603                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1064179                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1727464138                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 363220                       # Number of bytes of host memory used
+host_seconds                                    85.72                       # Real time elapsed on the host
+sim_insts                                    90576869                       # Number of instructions simulated
+sim_ops                                      91226321                       # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu.inst             36992                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data            949120                       # Number of bytes read from this memory
+system.physmem.bytes_read::total               986112                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        36992                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           36992                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks         2048                       # Number of bytes written to this memory
+system.physmem.bytes_written::total              2048                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst                578                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data              14830                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                 15408                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks              32                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total                   32                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst               249800                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              6409238                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 6659039                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          249800                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             249800                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks             13830                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                  13830                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks             13830                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              249800                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             6409238                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                6672869                       # Total bandwidth to/from this memory (bytes/s)
+system.cpu.dtb.inst_hits                            0                       # ITB inst hits
+system.cpu.dtb.inst_misses                          0                       # ITB inst misses
+system.cpu.dtb.read_hits                            0                       # DTB read hits
+system.cpu.dtb.read_misses                          0                       # DTB read misses
+system.cpu.dtb.write_hits                           0                       # DTB write hits
+system.cpu.dtb.write_misses                         0                       # DTB write misses
+system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                        0                       # DTB read accesses
+system.cpu.dtb.write_accesses                       0                       # DTB write accesses
+system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.dtb.hits                                 0                       # DTB hits
+system.cpu.dtb.misses                               0                       # DTB misses
+system.cpu.dtb.accesses                             0                       # DTB accesses
+system.cpu.itb.inst_hits                            0                       # ITB inst hits
+system.cpu.itb.inst_misses                          0                       # ITB inst misses
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
+system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
+system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.itb.hits                                 0                       # DTB hits
+system.cpu.itb.misses                               0                       # DTB misses
+system.cpu.itb.accesses                             0                       # DTB accesses
+system.cpu.workload.num_syscalls                  442                       # Number of system calls
+system.cpu.numCycles                        296172478                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.committedInsts                    90576869                       # Number of instructions committed
+system.cpu.committedOps                      91226321                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses              72525682                       # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses                     48                       # Number of float alu accesses
+system.cpu.num_func_calls                       96832                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts     15548926                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                     72525682                       # number of integer instructions
+system.cpu.num_fp_insts                            48                       # number of float instructions
+system.cpu.num_int_register_reads           464563396                       # number of times the integer registers were read
+system.cpu.num_int_register_writes          106840370                       # number of times the integer registers were written
+system.cpu.num_fp_register_reads                   54                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes                  30                       # number of times the floating registers were written
+system.cpu.num_mem_refs                      27318811                       # number of memory refs
+system.cpu.num_load_insts                    22573967                       # Number of load instructions
+system.cpu.num_store_insts                    4744844                       # Number of store instructions
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
+system.cpu.num_busy_cycles                  296172478                       # Number of busy cycles
+system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                            0                       # Percentage of idle cycles
+system.cpu.icache.replacements                      2                       # number of replacements
+system.cpu.icache.tagsinuse                510.335448                       # Cycle average of tags in use
+system.cpu.icache.total_refs                107830181                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                    599                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs               180016.996661                       # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::cpu.inst     510.335448                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.249187                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.249187                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst    107830181                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       107830181                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     107830181                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        107830181                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    107830181                       # number of overall hits
+system.cpu.icache.overall_hits::total       107830181                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst          599                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total           599                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst          599                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total            599                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst          599                       # number of overall misses
+system.cpu.icache.overall_misses::total           599                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     32662000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     32662000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     32662000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     32662000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     32662000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     32662000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    107830780                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    107830780                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    107830780                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    107830780                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    107830780                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    107830780                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000006                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.000006                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000006                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.000006                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000006                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.000006                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54527.545910                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 54527.545910                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 54527.545910                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 54527.545910                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 54527.545910                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 54527.545910                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.icache.fast_writes                       0                       # number of fast writes performed
+system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst          599                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total          599                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst          599                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total          599                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst          599                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total          599                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     30865000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     30865000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     30865000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     30865000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     30865000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     30865000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000006                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000006                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000006                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.000006                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000006                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.000006                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51527.545910                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51527.545910                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51527.545910                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 51527.545910                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51527.545910                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 51527.545910                       # average overall mshr miss latency
+system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.replacements                 942702                       # number of replacements
+system.cpu.dcache.tagsinuse               3568.549501                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                 26345365                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                 946798                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                  27.825751                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle            54479156000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data    3568.549501                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.871228                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.871228                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data     21649219                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        21649219                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      4688372                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        4688372                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data         3887                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total         3887                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data         3887                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total         3887                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data      26337591                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         26337591                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     26337591                       # number of overall hits
+system.cpu.dcache.overall_hits::total        26337591                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       900189                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        900189                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data        46609                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total        46609                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data       946798                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total         946798                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data       946798                       # number of overall misses
+system.cpu.dcache.overall_misses::total        946798                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  12614490000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  12614490000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data   1263542000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   1263542000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  13878032000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  13878032000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  13878032000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  13878032000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     22549408                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     22549408                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data      4734981                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total      4734981                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data         3887                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total         3887                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data         3887                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total         3887                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     27284389                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     27284389                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     27284389                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     27284389                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.039921                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.039921                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.009844                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.009844                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.034701                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.034701                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.034701                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.034701                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14013.157237                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 14013.157237                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27109.399472                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 27109.399472                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 14657.859438                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 14657.859438                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 14657.859438                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 14657.859438                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.writebacks::writebacks       942309                       # number of writebacks
+system.cpu.dcache.writebacks::total            942309                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data       900189                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       900189                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data        46609                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total        46609                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data       946798                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       946798                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       946798                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       946798                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   9913923000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   9913923000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   1123715000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   1123715000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  11037638000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  11037638000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  11037638000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  11037638000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.039921                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.039921                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.009844                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.009844                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.034701                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.034701                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.034701                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.034701                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11013.157237                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11013.157237                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24109.399472                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24109.399472                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11657.859438                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 11657.859438                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11657.859438                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 11657.859438                       # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.l2cache.replacements                   634                       # number of replacements
+system.cpu.l2cache.tagsinuse              9235.307693                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                 1594542                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                 15392                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                103.595504                       # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::writebacks  8910.209882                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst    165.071875                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data    160.025936                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks     0.271918                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst     0.005038                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.004884                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.281839                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst           21                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data       899907                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total         899928                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks       942309                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total       942309                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data        32061                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total        32061                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst           21                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data       931968                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total          931989                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst           21                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data       931968                       # number of overall hits
+system.cpu.l2cache.overall_hits::total         931989                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst          578                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data          282                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total          860                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data        14548                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total        14548                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst          578                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data        14830                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total         15408                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst          578                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data        14830                       # number of overall misses
+system.cpu.l2cache.overall_misses::total        15408                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     30056000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data     14664000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total     44720000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    756496000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total    756496000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     30056000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data    771160000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total    801216000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     30056000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data    771160000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total    801216000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst          599                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data       900189                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total       900788                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks       942309                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total       942309                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data        46609                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total        46609                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst          599                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data       946798                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total       947397                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst          599                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data       946798                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total       947397                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.964942                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.000313                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.000955                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.312129                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.312129                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.964942                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.015663                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.016264                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.964942                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.015663                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.016264                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst        52000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data        52000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total        52000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data        52000                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total        52000                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data        52000                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total        52000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data        52000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total        52000                       # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
+system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
+system.cpu.l2cache.writebacks::writebacks           32                       # number of writebacks
+system.cpu.l2cache.writebacks::total               32                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          578                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data          282                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total          860                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        14548                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total        14548                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst          578                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data        14830                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total        15408                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst          578                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data        14830                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total        15408                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     23120000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     11280000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total     34400000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    581920000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    581920000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     23120000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    593200000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    616320000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     23120000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    593200000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    616320000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.964942                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.000313                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.000955                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.312129                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.312129                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.964942                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.015663                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.016264                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.964942                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.015663                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.016264                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst        40000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total        40000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total        40000                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total        40000                       # average overall mshr miss latency
+system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+
+---------- End Simulation Statistics   ----------

simulators/gem5/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini

@@ -0,0 +1,117 @@
+[root]
+type=Root
+children=system
+full_system=false
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
+mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
+readfile=
+symbolfile=
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.slave[0]
+
+[system.cpu]
+type=AtomicSimpleCPU
+children=dtb interrupts itb tracer workload
+checker=Null
+clock=500
+cpu_id=0
+defer_registration=false
+do_checkpoint_insts=true
+do_quiesce=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+fastmem=false
+function_trace=false
+function_trace_start=0
+interrupts=system.cpu.interrupts
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+phase=0
+profile=0
+progress_interval=0
+simulate_data_stalls=false
+simulate_inst_stalls=false
+system=system
+tracer=system.cpu.tracer
+width=1
+workload=system.cpu.workload
+dcache_port=system.membus.slave[2]
+icache_port=system.membus.slave[1]
+
+[system.cpu.dtb]
+type=SparcTLB
+size=64
+
+[system.cpu.interrupts]
+type=SparcInterrupts
+
+[system.cpu.itb]
+type=SparcTLB
+size=64
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=mcf mcf.in
+cwd=build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-atomic
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/dist/m5/cpu2000/binaries/sparc/linux/mcf
+gid=100
+input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=55300000000
+system=system
+uid=100
+
+[system.membus]
+type=CoherentBus
+block_size=64
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+master=system.physmem.port[0]
+slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
+
+[system.physmem]
+type=SimpleMemory
+conf_table_reported=false
+file=
+in_addr_map=true
+latency=30000
+latency_var=0
+null=false
+range=0:268435455
+zero=false
+port=system.membus.master[0]
+

simulators/gem5/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/mcf.out

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simulators/gem5/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simerr

@@ -0,0 +1,3 @@
+warn: CoherentBus system.membus has no snooping ports attached!
+warn: Sockets disabled, not accepting gdb connections
+hack: be nice to actually delete the event here

simulators/gem5/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simout

@@ -0,0 +1,26 @@
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jun  4 2012 12:01:47
+gem5 started Jun  4 2012 14:53:37
+gem5 executing on zizzer
+command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-atomic
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0.  Starting simulation...
+
+MCF SPEC version 1.6.I
+by  Andreas Loebel
+Copyright (c) 1998,1999   ZIB Berlin
+All Rights Reserved.
+
+nodes                      : 500
+active arcs                : 1905
+simplex iterations         : 1502
+flow value                 : 4990014995
+new implicit arcs          : 23867
+active arcs                : 25772
+simplex iterations         : 2663
+flow value                 : 3080014995
+checksum                   : 68389
+optimal
+Exiting @ tick 122215830000 because target called exit()

simulators/gem5/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt

@@ -0,0 +1,62 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds                                  0.122216                       # Number of seconds simulated
+sim_ticks                                122215830000                       # Number of ticks simulated
+final_tick                               122215830000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                2951739                       # Simulator instruction rate (inst/s)
+host_op_rate                                  2951861                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1479540198                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 346528                       # Number of bytes of host memory used
+host_seconds                                    82.60                       # Real time elapsed on the host
+sim_insts                                   243825163                       # Number of instructions simulated
+sim_ops                                     243835278                       # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu.inst         977686044                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data         328674009                       # Number of bytes read from this memory
+system.physmem.bytes_read::total           1306360053                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst    977686044                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total       977686044                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::cpu.data       91606089                       # Number of bytes written to this memory
+system.physmem.bytes_written::total          91606089                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst          244421511                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data           82220434                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total             326641945                       # Number of read requests responded to by this memory
+system.physmem.num_writes::cpu.data          22901951                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total             22901951                       # Number of write requests responded to by this memory
+system.physmem.num_other::cpu.data               3886                       # Number of other requests responded to by this memory
+system.physmem.num_other::total                  3886                       # Number of other requests responded to by this memory
+system.physmem.bw_read::cpu.inst           7999667834                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data           2689291633                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total             10688959466                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst      7999667834                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total         7999667834                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data           749543566                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total              749543566                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst          7999667834                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data          3438835198                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total            11438503032                       # Total bandwidth to/from this memory (bytes/s)
+system.cpu.workload.num_syscalls                  443                       # Number of system calls
+system.cpu.numCycles                        244431661                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.committedInsts                   243825163                       # Number of instructions committed
+system.cpu.committedOps                     243835278                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses             194726506                       # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses                  11630                       # Number of float alu accesses
+system.cpu.num_func_calls                     4252956                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts     18619960                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                    194726506                       # number of integer instructions
+system.cpu.num_fp_insts                         11630                       # number of float instructions
+system.cpu.num_int_register_reads           456819010                       # number of times the integer registers were read
+system.cpu.num_int_register_writes          215451567                       # number of times the integer registers were written
+system.cpu.num_fp_register_reads                23256                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes                  90                       # number of times the floating registers were written
+system.cpu.num_mem_refs                     105711442                       # number of memory refs
+system.cpu.num_load_insts                    82803522                       # Number of load instructions
+system.cpu.num_store_insts                   22907920                       # Number of store instructions
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
+system.cpu.num_busy_cycles                  244431661                       # Number of busy cycles
+system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                            0                       # Percentage of idle cycles
+
+---------- End Simulation Statistics   ----------

simulators/gem5/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini

@@ -0,0 +1,198 @@
+[root]
+type=Root
+children=system
+full_system=false
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
+mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
+readfile=
+symbolfile=
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.slave[0]
+
+[system.cpu]
+type=TimingSimpleCPU
+children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
+checker=Null
+clock=500
+cpu_id=0
+defer_registration=false
+do_checkpoint_insts=true
+do_quiesce=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+function_trace=false
+function_trace_start=0
+interrupts=system.cpu.interrupts
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+phase=0
+profile=0
+progress_interval=0
+system=system
+tracer=system.cpu.tracer
+workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.dcache]
+type=BaseCache
+addr_ranges=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+prefetch_on_access=false
+prefetcher=Null
+prioritizeRequests=false
+repl=Null
+size=262144
+subblock_size=0
+system=system
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.slave[1]
+
+[system.cpu.dtb]
+type=SparcTLB
+size=64
+
+[system.cpu.icache]
+type=BaseCache
+addr_ranges=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
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+prefetch_on_access=false
+prefetcher=Null
+prioritizeRequests=false
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+size=131072
+subblock_size=0
+system=system
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.slave[0]
+
+[system.cpu.interrupts]
+type=SparcInterrupts
+
+[system.cpu.itb]
+type=SparcTLB
+size=64
+
+[system.cpu.l2cache]
+type=BaseCache
+addr_ranges=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=false
+latency=10000
+max_miss_count=0
+mshrs=10
+prefetch_on_access=false
+prefetcher=Null
+prioritizeRequests=false
+repl=Null
+size=2097152
+subblock_size=0
+system=system
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.master[0]
+mem_side=system.membus.slave[1]
+
+[system.cpu.toL2Bus]
+type=CoherentBus
+block_size=64
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+master=system.cpu.l2cache.cpu_side
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=mcf mcf.in
+cwd=build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-timing
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/dist/m5/cpu2000/binaries/sparc/linux/mcf
+gid=100
+input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=55300000000
+system=system
+uid=100
+
+[system.membus]
+type=CoherentBus
+block_size=64
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+master=system.physmem.port[0]
+slave=system.system_port system.cpu.l2cache.mem_side
+
+[system.physmem]
+type=SimpleMemory
+conf_table_reported=false
+file=
+in_addr_map=true
+latency=30000
+latency_var=0
+null=false
+range=0:268435455
+zero=false
+port=system.membus.master[0]
+

simulators/gem5/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/mcf.out

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simulators/gem5/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simerr

@@ -0,0 +1,2 @@
+warn: Sockets disabled, not accepting gdb connections
+hack: be nice to actually delete the event here

simulators/gem5/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout

@@ -0,0 +1,26 @@
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jun  4 2012 12:01:47
+gem5 started Jun  4 2012 14:55:10
+gem5 executing on zizzer
+command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-timing
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0.  Starting simulation...
+
+MCF SPEC version 1.6.I
+by  Andreas Loebel
+Copyright (c) 1998,1999   ZIB Berlin
+All Rights Reserved.
+
+nodes                      : 500
+active arcs                : 1905
+simplex iterations         : 1502
+flow value                 : 4990014995
+new implicit arcs          : 23867
+active arcs                : 25772
+simplex iterations         : 2663
+flow value                 : 3080014995
+checksum                   : 68389
+optimal
+Exiting @ tick 362430887000 because target called exit()

simulators/gem5/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt

@@ -0,0 +1,397 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds                                  0.362431                       # Number of seconds simulated
+sim_ticks                                362430887000                       # Number of ticks simulated
+final_tick                               362430887000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                1267775                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1267827                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1884467398                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 355400                       # Number of bytes of host memory used
+host_seconds                                   192.33                       # Real time elapsed on the host
+sim_insts                                   243825163                       # Number of instructions simulated
+sim_ops                                     243835278                       # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu.inst             56256                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data            945216                       # Number of bytes read from this memory
+system.physmem.bytes_read::total              1001472                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        56256                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           56256                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks         2560                       # Number of bytes written to this memory
+system.physmem.bytes_written::total              2560                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst                879                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data              14769                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                 15648                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks              40                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total                   40                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst               155219                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              2607990                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 2763208                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          155219                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             155219                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks              7063                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                   7063                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks              7063                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              155219                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             2607990                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                2770272                       # Total bandwidth to/from this memory (bytes/s)
+system.cpu.workload.num_syscalls                  443                       # Number of system calls
+system.cpu.numCycles                        724861774                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.committedInsts                   243825163                       # Number of instructions committed
+system.cpu.committedOps                     243835278                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses             194726506                       # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses                  11630                       # Number of float alu accesses
+system.cpu.num_func_calls                     4252956                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts     18619960                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                    194726506                       # number of integer instructions
+system.cpu.num_fp_insts                         11630                       # number of float instructions
+system.cpu.num_int_register_reads           456819010                       # number of times the integer registers were read
+system.cpu.num_int_register_writes          215451566                       # number of times the integer registers were written
+system.cpu.num_fp_register_reads                23256                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes                  90                       # number of times the floating registers were written
+system.cpu.num_mem_refs                     105711442                       # number of memory refs
+system.cpu.num_load_insts                    82803522                       # Number of load instructions
+system.cpu.num_store_insts                   22907920                       # Number of store instructions
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
+system.cpu.num_busy_cycles                  724861774                       # Number of busy cycles
+system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                            0                       # Percentage of idle cycles
+system.cpu.icache.replacements                     25                       # number of replacements
+system.cpu.icache.tagsinuse                725.567632                       # Cycle average of tags in use
+system.cpu.icache.total_refs                244420630                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                    882                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs               277120.895692                       # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::cpu.inst     725.567632                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.354281                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.354281                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst    244420630                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       244420630                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     244420630                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        244420630                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    244420630                       # number of overall hits
+system.cpu.icache.overall_hits::total       244420630                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst          882                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total           882                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst          882                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total            882                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst          882                       # number of overall misses
+system.cpu.icache.overall_misses::total           882                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     49266000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     49266000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     49266000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     49266000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     49266000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     49266000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    244421512                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    244421512                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    244421512                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    244421512                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    244421512                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    244421512                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000004                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.000004                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000004                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.000004                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000004                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.000004                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55857.142857                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 55857.142857                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 55857.142857                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 55857.142857                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 55857.142857                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 55857.142857                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.icache.fast_writes                       0                       # number of fast writes performed
+system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst          882                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total          882                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst          882                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total          882                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst          882                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total          882                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     46620000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     46620000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     46620000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     46620000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     46620000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     46620000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000004                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000004                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000004                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.000004                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000004                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.000004                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52857.142857                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52857.142857                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52857.142857                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 52857.142857                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52857.142857                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 52857.142857                       # average overall mshr miss latency
+system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.replacements                 935475                       # number of replacements
+system.cpu.dcache.tagsinuse               3563.824259                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                104186700                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                 939571                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                 110.887522                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle           134373316000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data    3563.824259                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.870074                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.870074                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data     81327577                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        81327577                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     22855241                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       22855241                       # number of WriteReq hits
+system.cpu.dcache.SwapReq_hits::cpu.data         3882                       # number of SwapReq hits
+system.cpu.dcache.SwapReq_hits::total            3882                       # number of SwapReq hits
+system.cpu.dcache.demand_hits::cpu.data     104182818                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        104182818                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    104182818                       # number of overall hits
+system.cpu.dcache.overall_hits::total       104182818                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       892857                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        892857                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data        46710                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total        46710                       # number of WriteReq misses
+system.cpu.dcache.SwapReq_misses::cpu.data            4                       # number of SwapReq misses
+system.cpu.dcache.SwapReq_misses::total             4                       # number of SwapReq misses
+system.cpu.dcache.demand_misses::cpu.data       939567                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total         939567                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data       939567                       # number of overall misses
+system.cpu.dcache.overall_misses::total        939567                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  12508482000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  12508482000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data   1265712000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   1265712000                       # number of WriteReq miss cycles
+system.cpu.dcache.SwapReq_miss_latency::cpu.data        98000                       # number of SwapReq miss cycles
+system.cpu.dcache.SwapReq_miss_latency::total        98000                       # number of SwapReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  13774194000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  13774194000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  13774194000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  13774194000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     82220434                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     82220434                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data     22901951                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total     22901951                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.SwapReq_accesses::cpu.data         3886                       # number of SwapReq accesses(hits+misses)
+system.cpu.dcache.SwapReq_accesses::total         3886                       # number of SwapReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data    105122385                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    105122385                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    105122385                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    105122385                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.010859                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.010859                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.002040                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.002040                       # miss rate for WriteReq accesses
+system.cpu.dcache.SwapReq_miss_rate::cpu.data     0.001029                       # miss rate for SwapReq accesses
+system.cpu.dcache.SwapReq_miss_rate::total     0.001029                       # miss rate for SwapReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.008938                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.008938                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.008938                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.008938                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14009.502082                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 14009.502082                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27097.238279                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 27097.238279                       # average WriteReq miss latency
+system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data        24500                       # average SwapReq miss latency
+system.cpu.dcache.SwapReq_avg_miss_latency::total        24500                       # average SwapReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 14660.150899                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 14660.150899                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 14660.150899                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 14660.150899                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.writebacks::writebacks       935237                       # number of writebacks
+system.cpu.dcache.writebacks::total            935237                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data       892857                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       892857                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data        46710                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total        46710                       # number of WriteReq MSHR misses
+system.cpu.dcache.SwapReq_mshr_misses::cpu.data            4                       # number of SwapReq MSHR misses
+system.cpu.dcache.SwapReq_mshr_misses::total            4                       # number of SwapReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data       939567                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       939567                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       939567                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       939567                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   9829911000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   9829911000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   1125582000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   1125582000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data        86000                       # number of SwapReq MSHR miss cycles
+system.cpu.dcache.SwapReq_mshr_miss_latency::total        86000                       # number of SwapReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  10955493000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  10955493000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  10955493000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  10955493000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.010859                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.010859                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.002040                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.002040                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data     0.001029                       # mshr miss rate for SwapReq accesses
+system.cpu.dcache.SwapReq_mshr_miss_rate::total     0.001029                       # mshr miss rate for SwapReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.008938                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.008938                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.008938                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.008938                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11009.502082                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11009.502082                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24097.238279                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24097.238279                       # average WriteReq mshr miss latency
+system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data        21500                       # average SwapReq mshr miss latency
+system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total        21500                       # average SwapReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11660.150899                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 11660.150899                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11660.150899                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 11660.150899                       # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.l2cache.replacements                   865                       # number of replacements
+system.cpu.l2cache.tagsinuse              9236.752232                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                 1585884                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                 15631                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                101.457616                       # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::writebacks  8861.245791                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst    244.574580                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data    130.931861                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks     0.270424                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst     0.007464                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.003996                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.281883                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst            3                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data       892655                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total         892658                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks       935237                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total       935237                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data        32147                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total        32147                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst            3                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data       924802                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total          924805                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst            3                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data       924802                       # number of overall hits
+system.cpu.l2cache.overall_hits::total         924805                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst          879                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data          202                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total         1081                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data        14567                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total        14567                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst          879                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data        14769                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total         15648                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst          879                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data        14769                       # number of overall misses
+system.cpu.l2cache.overall_misses::total        15648                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     45708000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data     10504000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total     56212000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    757484000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total    757484000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     45708000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data    767988000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total    813696000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     45708000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data    767988000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total    813696000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst          882                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data       892857                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total       893739                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks       935237                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total       935237                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data        46714                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total        46714                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst          882                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data       939571                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total       940453                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst          882                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data       939571                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total       940453                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.996599                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.000226                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.001210                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.311834                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.311834                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.996599                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.015719                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.016639                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.996599                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.015719                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.016639                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst        52000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data        52000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total        52000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data        52000                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total        52000                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data        52000                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total        52000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data        52000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total        52000                       # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
+system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
+system.cpu.l2cache.writebacks::writebacks           40                       # number of writebacks
+system.cpu.l2cache.writebacks::total               40                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          879                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data          202                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total         1081                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        14567                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total        14567                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst          879                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data        14769                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total        15648                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst          879                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data        14769                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total        15648                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     35160000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      8080000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total     43240000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    582680000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    582680000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     35160000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    590760000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    625920000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     35160000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    590760000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    625920000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.996599                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.000226                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.001210                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.311834                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.311834                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.996599                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.015719                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.016639                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.996599                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.015719                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.016639                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst        40000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total        40000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total        40000                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total        40000                       # average overall mshr miss latency
+system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+
+---------- End Simulation Statistics   ----------

simulators/gem5/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini

@@ -0,0 +1,550 @@
+[root]
+type=Root
+children=system
+full_system=false
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
+mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
+readfile=
+symbolfile=
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.slave[0]
+
+[system.cpu]
+type=DerivO3CPU
+children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
+BTBEntries=4096
+BTBTagSize=16
+LFSTSize=1024
+LQEntries=32
+LSQCheckLoads=true
+LSQDepCheckShift=4
+RASSize=16
+SQEntries=32
+SSITSize=1024
+activity=0
+backComSize=5
+cachePorts=200
+checker=Null
+choiceCtrBits=2
+choicePredictorSize=8192
+clock=500
+commitToDecodeDelay=1
+commitToFetchDelay=1
+commitToIEWDelay=1
+commitToRenameDelay=1
+commitWidth=8
+cpu_id=0
+decodeToFetchDelay=1
+decodeToRenameDelay=1
+decodeWidth=8
+defer_registration=false
+dispatchWidth=8
+do_checkpoint_insts=true
+do_quiesce=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+fetchToDecodeDelay=1
+fetchTrapLatency=1
+fetchWidth=8
+forwardComSize=5
+fuPool=system.cpu.fuPool
+function_trace=false
+function_trace_start=0
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+iewToCommitDelay=1
+iewToDecodeDelay=1
+iewToFetchDelay=1
+iewToRenameDelay=1
+instShiftAmt=2
+interrupts=system.cpu.interrupts
+issueToExecuteDelay=1
+issueWidth=8
+itb=system.cpu.itb
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+needsTSO=true
+numIQEntries=64
+numPhysFloatRegs=256
+numPhysIntRegs=256
+numROBEntries=192
+numRobs=1
+numThreads=1
+phase=0
+predType=tournament
+profile=0
+progress_interval=0
+renameToDecodeDelay=1
+renameToFetchDelay=1
+renameToIEWDelay=2
+renameToROBDelay=1
+renameWidth=8
+smtCommitPolicy=RoundRobin
+smtFetchPolicy=SingleThread
+smtIQPolicy=Partitioned
+smtIQThreshold=100
+smtLSQPolicy=Partitioned
+smtLSQThreshold=100
+smtNumFetchingThreads=1
+smtROBPolicy=Partitioned
+smtROBThreshold=100
+squashWidth=8
+store_set_clear_period=250000
+system=system
+tracer=system.cpu.tracer
+trapLatency=13
+wbDepth=1
+wbWidth=8
+workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.dcache]
+type=BaseCache
+addr_ranges=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+prefetch_on_access=false
+prefetcher=Null
+prioritizeRequests=false
+repl=Null
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+***
+145
+***
+150
+()
+8
+***
+67
+()
+7
+***
+60
+***
+231
+()
+6
+***
+56
+***
+234
+()
+5
+***
+164
+***
+202
+()
+4
+***
+53
+()
+3
+***
+130
+***
+185
+***
+200
+()
+2
+***
+205
+()
+1
+***
+39
+***
+95

simulators/gem5/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simerr

@@ -0,0 +1,4 @@
+warn: Sockets disabled, not accepting gdb connections
+warn: instruction 'fnstcw_Mw' unimplemented
+warn: instruction 'fldcw_Mw' unimplemented
+hack: be nice to actually delete the event here

simulators/gem5/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout

@@ -0,0 +1,27 @@
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jun  4 2012 13:44:28
+gem5 started Jun  4 2012 15:14:48
+gem5 executing on zizzer
+command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0.  Starting simulation...
+
+MCF SPEC version 1.6.I
+by  Andreas Loebel
+Copyright (c) 1998,1999   ZIB Berlin
+All Rights Reserved.
+
+nodes                      : 500
+active arcs                : 1905
+simplex iterations         : 1502
+flow value                 : 4990014995
+new implicit arcs          : 23867
+active arcs                : 25772
+simplex iterations         : 2663
+flow value                 : 3080014995
+info: Increasing stack size by one page.
+checksum                   : 68389
+optimal
+Exiting @ tick 67388458000 because target called exit()

simulators/gem5/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt

@@ -0,0 +1,652 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds                                  0.067388                       # Number of seconds simulated
+sim_ticks                                 67388458000                       # Number of ticks simulated
+final_tick                                67388458000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                  84988                       # Simulator instruction rate (inst/s)
+host_op_rate                                   149650                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               36250631                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 363056                       # Number of bytes of host memory used
+host_seconds                                  1858.96                       # Real time elapsed on the host
+sim_insts                                   157988582                       # Number of instructions simulated
+sim_ops                                     278192519                       # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu.inst             69248                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data           3838272                       # Number of bytes read from this memory
+system.physmem.bytes_read::total              3907520                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        69248                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           69248                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks       897536                       # Number of bytes written to this memory
+system.physmem.bytes_written::total            897536                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst               1082                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data              59973                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                 61055                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks           14024                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total                14024                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst              1027594                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             56957410                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                57985004                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         1027594                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            1027594                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks          13318839                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               13318839                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks          13318839                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             1027594                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            56957410                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               71303843                       # Total bandwidth to/from this memory (bytes/s)
+system.cpu.workload.num_syscalls                  444                       # Number of system calls
+system.cpu.numCycles                        134776917                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.BPredUnit.lookups                 36128556                       # Number of BP lookups
+system.cpu.BPredUnit.condPredicted           36128556                       # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect            1088012                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups              25661198                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                 25550813                       # Number of BTB hits
+system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.BPredUnit.usedRAS                        0                       # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect                   0                       # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles           27997413                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      196488492                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    36128556                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           25550813                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                      59432634                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 8416233                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles               39238726                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                   25                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles           143                       # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines                  27278821                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                142192                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples          133966907                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.578141                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.358289                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 77274639     57.68%     57.68% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  2166516      1.62%     59.30% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  2997281      2.24%     61.54% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                  4102912      3.06%     64.60% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  8026102      5.99%     70.59% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                  5043006      3.76%     74.35% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                  2893464      2.16%     76.51% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  1468336      1.10%     77.61% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                 29994651     22.39%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::total            133966907                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.268062                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        1.457879                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 40465112                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              30125694                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  46506148                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               9571987                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                7297966                       # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts              341297669                       # Number of instructions handled by decode
+system.cpu.rename.SquashCycles                7297966                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 45865108                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                 5065508                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles           9277                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  50351191                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              25377857                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              337406380                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                    13                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                   3712                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents              23187560                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents            79157                       # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands           414755881                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            1009935094                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       1009932394                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups              2700                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps             341010940                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                 73744941                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts                481                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts            474                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  56192967                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            108162580                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            37173372                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads          46311356                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          7909478                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  331723465                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                2616                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 311412241                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            185399                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        53269773                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     92543278                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved           2170                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     133966907                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         2.324546                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.724461                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            27936582     20.85%     20.85% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            17254518     12.88%     33.73% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            25564521     19.08%     52.82% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            31166509     23.26%     76.08% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            17676068     13.19%     89.27% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5             9033591      6.74%     96.02% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             3761456      2.81%     98.83% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7             1501105      1.12%     99.95% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8               72557      0.05%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       133966907                       # Number of insts issued each cycle
+system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                   23354      1.11%      1.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%      1.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      1.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      1.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      1.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      1.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      1.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      1.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      1.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      1.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      1.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      1.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      1.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      1.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      1.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      1.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      1.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      1.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      1.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      1.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      1.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      1.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      1.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      1.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      1.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      1.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      1.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      1.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      1.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                1960413     92.78%     93.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                129107      6.11%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
+system.cpu.iq.FU_type_0::No_OpClass             31371      0.01%      0.01% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             177196652     56.90%     56.91% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                    0      0.00%     56.91% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     56.91% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                 116      0.00%     56.91% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     56.91% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     56.91% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     56.91% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     56.91% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     56.91% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     56.91% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     56.91% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     56.91% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     56.91% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     56.91% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     56.91% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     56.91% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     56.91% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     56.91% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     56.91% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     56.91% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     56.91% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     56.91% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     56.91% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     56.91% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     56.91% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     56.91% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     56.91% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     56.91% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     56.91% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             99714062     32.02%     88.93% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            34470040     11.07%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::total              311412241                       # Type of FU issued
+system.cpu.iq.rate                           2.310575                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     2112874                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.006785                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          759088710                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         385026224                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    308270248                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads                 952                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes               1427                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses          314                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              313493303                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                     441                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads         52569930                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
+system.cpu.iew.lsq.thread0.squashedLoads     17383192                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        98849                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        32443                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      5733621                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
+system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
+system.cpu.iew.lsq.thread0.rescheduledLoads         3316                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked          3845                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
+system.cpu.iew.iewSquashCycles                7297966                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                  891871                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                 89086                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           331726081                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts             45756                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts             108162580                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             37173372                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts                476                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                    224                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                 43423                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          32443                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         615219                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       578970                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts              1194189                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             309448819                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              99181332                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           1963422                       # Number of squashed instructions skipped in execute
+system.cpu.iew.exec_swp                             0                       # number of swp insts executed
+system.cpu.iew.exec_nop                             0                       # number of nop insts executed
+system.cpu.iew.exec_refs                    133262430                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 31528913                       # Number of branches executed
+system.cpu.iew.exec_stores                   34081098                       # Number of stores executed
+system.cpu.iew.exec_rate                     2.296008                       # Inst execution rate
+system.cpu.iew.wb_sent                      308818207                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     308270562                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 227514859                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 467066838                       # num instructions consuming a value
+system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
+system.cpu.iew.wb_rate                       2.287265                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.487114                       # average fanout of values written-back
+system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu.commit.commitCommittedInsts      157988582                       # The number of committed instructions
+system.cpu.commit.commitCommittedOps        278192519                       # The number of committed instructions
+system.cpu.commit.commitSquashedInsts        53537768                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls             446                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts           1088027                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    126668941                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     2.196217                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.674380                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     46359304     36.60%     36.60% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     24201081     19.11%     55.70% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     16849760     13.30%     69.01% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     12619079      9.96%     78.97% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      3360251      2.65%     81.62% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      3556898      2.81%     84.43% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      2707142      2.14%     86.57% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      1157073      0.91%     87.48% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     15858353     12.52%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    126668941                       # Number of insts commited each cycle
+system.cpu.commit.committedInsts            157988582                       # Number of instructions committed
+system.cpu.commit.committedOps              278192519                       # Number of ops (including micro ops) committed
+system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
+system.cpu.commit.refs                      122219139                       # Number of memory references committed
+system.cpu.commit.loads                      90779388                       # Number of loads committed
+system.cpu.commit.membars                           0                       # Number of memory barriers committed
+system.cpu.commit.branches                   29309710                       # Number of branches committed
+system.cpu.commit.fp_insts                         40                       # Number of committed floating point instructions.
+system.cpu.commit.int_insts                 278186227                       # Number of committed integer instructions.
+system.cpu.commit.function_calls                    0                       # Number of function calls committed.
+system.cpu.commit.bw_lim_events              15858353                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
+system.cpu.rob.rob_reads                    442540875                       # The number of ROB reads
+system.cpu.rob.rob_writes                   670767297                       # The number of ROB writes
+system.cpu.timesIdled                           23993                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                          810010                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.committedInsts                   157988582                       # Number of Instructions Simulated
+system.cpu.committedOps                     278192519                       # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total             157988582                       # Number of Instructions Simulated
+system.cpu.cpi                               0.853080                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.853080                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.172223                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.172223                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                705322547                       # number of integer regfile reads
+system.cpu.int_regfile_writes               373244258                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                       361                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                      193                       # number of floating regfile writes
+system.cpu.misc_regfile_reads               197929880                       # number of misc regfile reads
+system.cpu.icache.replacements                     97                       # number of replacements
+system.cpu.icache.tagsinuse                846.508998                       # Cycle average of tags in use
+system.cpu.icache.total_refs                 27277404                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                   1093                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs               24956.453797                       # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::cpu.inst     846.508998                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.413334                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.413334                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst     27277408                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        27277408                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      27277408                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         27277408                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     27277408                       # number of overall hits
+system.cpu.icache.overall_hits::total        27277408                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst         1413                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total          1413                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst         1413                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total           1413                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst         1413                       # number of overall misses
+system.cpu.icache.overall_misses::total          1413                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     50201500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     50201500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     50201500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     50201500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     50201500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     50201500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     27278821                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     27278821                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     27278821                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     27278821                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     27278821                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     27278821                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000052                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.000052                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000052                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.000052                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000052                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.000052                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35528.308563                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 35528.308563                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 35528.308563                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 35528.308563                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 35528.308563                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 35528.308563                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.icache.fast_writes                       0                       # number of fast writes performed
+system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst          315                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total          315                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst          315                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total          315                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst          315                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total          315                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst         1098                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total         1098                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst         1098                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total         1098                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst         1098                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total         1098                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     38330500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     38330500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     38330500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     38330500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     38330500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     38330500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000040                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000040                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000040                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.000040                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000040                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.000040                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34909.380692                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 34909.380692                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34909.380692                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 34909.380692                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34909.380692                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 34909.380692                       # average overall mshr miss latency
+system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.replacements                2072128                       # number of replacements
+system.cpu.dcache.tagsinuse               4072.706371                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                 75623437                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                2076224                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                  36.423544                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle            22601159000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data    4072.706371                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.994313                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.994313                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data     44269678                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        44269678                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     31353743                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       31353743                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data      75623421                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         75623421                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     75623421                       # number of overall hits
+system.cpu.dcache.overall_hits::total        75623421                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      2291019                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       2291019                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data        86008                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total        86008                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data      2377027                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        2377027                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      2377027                       # number of overall misses
+system.cpu.dcache.overall_misses::total       2377027                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  13818885500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  13818885500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data   1502429791                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   1502429791                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  15321315291                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  15321315291                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  15321315291                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  15321315291                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     46560697                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     46560697                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data     31439751                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total     31439751                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     78000448                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     78000448                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     78000448                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     78000448                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.049205                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.049205                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.002736                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.002736                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.030475                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.030475                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.030475                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.030475                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data  6031.763813                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total  6031.763813                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17468.488873                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 17468.488873                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data  6445.578990                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total  6445.578990                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data  6445.578990                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total  6445.578990                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.writebacks::writebacks      1878988                       # number of writebacks
+system.cpu.dcache.writebacks::total           1878988                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       296886                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       296886                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data         3910                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total         3910                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data       300796                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total       300796                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data       300796                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total       300796                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1994133                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      1994133                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data        82098                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total        82098                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      2076231                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      2076231                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      2076231                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      2076231                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   5596231500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   5596231500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   1158803791                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   1158803791                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data   6755035291                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total   6755035291                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data   6755035291                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total   6755035291                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.042829                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.042829                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.002611                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.002611                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.026618                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.026618                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.026618                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.026618                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data  2806.348172                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total  2806.348172                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14114.884540                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14114.884540                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data  3253.508541                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total  3253.508541                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data  3253.508541                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total  3253.508541                       # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.l2cache.replacements                 33429                       # number of replacements
+system.cpu.l2cache.tagsinuse             18994.164700                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                 3761791                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                 61439                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                 61.228064                       # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::writebacks 12943.264838                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst    249.609803                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data   5801.290058                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks     0.394997                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst     0.007617                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.177041                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.579656                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst           12                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data      1963548                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total        1963560                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks      1878988                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total      1878988                       # number of Writeback hits
+system.cpu.l2cache.UpgradeReq_hits::cpu.data            1                       # number of UpgradeReq hits
+system.cpu.l2cache.UpgradeReq_hits::total            1                       # number of UpgradeReq hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data        52705                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total        52705                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst           12                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data      2016253                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         2016265                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst           12                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data      2016253                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        2016265                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst         1082                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data        30455                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total        31537                       # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses::cpu.data            4                       # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total            4                       # number of UpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data        29518                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total        29518                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst         1082                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data        59973                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total         61055                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         1082                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data        59973                       # number of overall misses
+system.cpu.l2cache.overall_misses::total        61055                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     37085000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data   1040283500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total   1077368500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   1006135000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   1006135000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     37085000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data   2046418500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total   2083503500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     37085000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data   2046418500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total   2083503500                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst         1094                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data      1994003                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total      1995097                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks      1878988                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total      1878988                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data            5                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total            5                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data        82223                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total        82223                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst         1094                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data      2076226                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      2077320                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst         1094                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data      2076226                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      2077320                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.989031                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.015273                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.015807                       # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.800000                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total     0.800000                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.358999                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.358999                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.989031                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.028886                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.029391                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.989031                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.028886                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.029391                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34274.491682                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34158.052865                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 34162.047753                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34085.473271                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34085.473271                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34274.491682                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34122.330049                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 34125.026615                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34274.491682                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34122.330049                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 34125.026615                       # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
+system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
+system.cpu.l2cache.writebacks::writebacks        14024                       # number of writebacks
+system.cpu.l2cache.writebacks::total            14024                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         1082                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        30455                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total        31537                       # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data            4                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total            4                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        29518                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total        29518                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         1082                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data        59973                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total        61055                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         1082                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data        59973                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total        61055                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     33615000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data    944732500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total    978347500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data       124000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total       124000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    915134000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    915134000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     33615000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   1859866500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total   1893481500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     33615000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   1859866500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total   1893481500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.989031                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.015273                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.015807                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.800000                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.800000                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.358999                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.358999                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.989031                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.028886                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.029391                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.989031                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.028886                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.029391                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31067.467652                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31020.604170                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31022.212005                       # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data        31000                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total        31000                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31002.574700                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31002.574700                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31067.467652                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31011.730279                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31012.718041                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31067.467652                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31011.730279                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31012.718041                       # average overall mshr miss latency
+system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+
+---------- End Simulation Statistics   ----------

simulators/gem5/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/config.ini

@@ -0,0 +1,138 @@
+[root]
+type=Root
+children=system
+full_system=false
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
+mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
+readfile=
+symbolfile=
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.slave[0]
+
+[system.cpu]
+type=AtomicSimpleCPU
+children=dtb interrupts itb tracer workload
+checker=Null
+clock=500
+cpu_id=0
+defer_registration=false
+do_checkpoint_insts=true
+do_quiesce=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+fastmem=false
+function_trace=false
+function_trace_start=0
+interrupts=system.cpu.interrupts
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+phase=0
+profile=0
+progress_interval=0
+simulate_data_stalls=false
+simulate_inst_stalls=false
+system=system
+tracer=system.cpu.tracer
+width=1
+workload=system.cpu.workload
+dcache_port=system.membus.slave[2]
+icache_port=system.membus.slave[1]
+
+[system.cpu.dtb]
+type=X86TLB
+children=walker
+size=64
+walker=system.cpu.dtb.walker
+
+[system.cpu.dtb.walker]
+type=X86PagetableWalker
+system=system
+port=system.membus.slave[4]
+
+[system.cpu.interrupts]
+type=X86LocalApic
+int_latency=1000
+pio_addr=2305843009213693952
+pio_latency=1000
+system=system
+int_master=system.membus.slave[5]
+int_slave=system.membus.master[2]
+pio=system.membus.master[1]
+
+[system.cpu.itb]
+type=X86TLB
+children=walker
+size=64
+walker=system.cpu.itb.walker
+
+[system.cpu.itb.walker]
+type=X86PagetableWalker
+system=system
+port=system.membus.slave[3]
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=mcf mcf.in
+cwd=build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-atomic
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/dist/m5/cpu2000/binaries/x86/linux/mcf
+gid=100
+input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=55300000000
+system=system
+uid=100
+
+[system.membus]
+type=CoherentBus
+block_size=64
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave
+slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.interrupts.int_master
+
+[system.physmem]
+type=SimpleMemory
+conf_table_reported=false
+file=
+in_addr_map=true
+latency=30000
+latency_var=0
+null=false
+range=0:268435455
+zero=false
+port=system.membus.master[0]
+

simulators/gem5/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/mcf.out

@@ -0,0 +1,999 @@
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simulators/gem5/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simerr

@@ -0,0 +1,4 @@
+warn: Sockets disabled, not accepting gdb connections
+warn: instruction 'fnstcw_Mw' unimplemented
+warn: instruction 'fldcw_Mw' unimplemented
+hack: be nice to actually delete the event here

simulators/gem5/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simout

@@ -0,0 +1,26 @@
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jun  4 2012 13:44:28
+gem5 started Jun  4 2012 15:20:09
+gem5 executing on zizzer
+command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-atomic
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0.  Starting simulation...
+
+MCF SPEC version 1.6.I
+by  Andreas Loebel
+Copyright (c) 1998,1999   ZIB Berlin
+All Rights Reserved.
+
+nodes                      : 500
+active arcs                : 1905
+simplex iterations         : 1502
+flow value                 : 4990014995
+new implicit arcs          : 23867
+active arcs                : 25772
+simplex iterations         : 2663
+flow value                 : 3080014995
+checksum                   : 68389
+optimal
+Exiting @ tick 168950072000 because target called exit()

simulators/gem5/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt

@@ -0,0 +1,60 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds                                  0.168950                       # Number of seconds simulated
+sim_ticks                                168950072000                       # Number of ticks simulated
+final_tick                               168950072000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                1244063                       # Simulator instruction rate (inst/s)
+host_op_rate                                  2190595                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1330377575                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 351912                       # Number of bytes of host memory used
+host_seconds                                   126.99                       # Real time elapsed on the host
+sim_insts                                   157988583                       # Number of instructions simulated
+sim_ops                                     278192520                       # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu.inst        1741569664                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data         717246015                       # Number of bytes read from this memory
+system.physmem.bytes_read::total           2458815679                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst   1741569664                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total      1741569664                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::cpu.data      243173115                       # Number of bytes written to this memory
+system.physmem.bytes_written::total         243173115                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst          217696208                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data           90779450                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total             308475658                       # Number of read requests responded to by this memory
+system.physmem.num_writes::cpu.data          31439751                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total             31439751                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst          10308191310                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data           4245313462                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total             14553504772                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst     10308191310                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total        10308191310                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data          1439319393                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total             1439319393                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst         10308191310                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data          5684632854                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total            15992824164                       # Total bandwidth to/from this memory (bytes/s)
+system.cpu.workload.num_syscalls                  444                       # Number of system calls
+system.cpu.numCycles                        337900145                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.committedInsts                   157988583                       # Number of instructions committed
+system.cpu.committedOps                     278192520                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses             278186228                       # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses                     40                       # Number of float alu accesses
+system.cpu.num_func_calls                           0                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts     18628012                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                    278186228                       # number of integer instructions
+system.cpu.num_fp_insts                            40                       # number of float instructions
+system.cpu.num_int_register_reads           834011910                       # number of times the integer registers were read
+system.cpu.num_int_register_writes          341010914                       # number of times the integer registers were written
+system.cpu.num_fp_register_reads                   40                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes                  26                       # number of times the floating registers were written
+system.cpu.num_mem_refs                     122219139                       # number of memory refs
+system.cpu.num_load_insts                    90779388                       # Number of load instructions
+system.cpu.num_store_insts                   31439751                       # Number of store instructions
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
+system.cpu.num_busy_cycles                  337900145                       # Number of busy cycles
+system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                            0                       # Percentage of idle cycles
+
+---------- End Simulation Statistics   ----------

simulators/gem5/tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini

@@ -0,0 +1,219 @@
+[root]
+type=Root
+children=system
+full_system=false
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
+mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
+readfile=
+symbolfile=
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.slave[0]
+
+[system.cpu]
+type=TimingSimpleCPU
+children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
+checker=Null
+clock=500
+cpu_id=0
+defer_registration=false
+do_checkpoint_insts=true
+do_quiesce=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+function_trace=false
+function_trace_start=0
+interrupts=system.cpu.interrupts
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+phase=0
+profile=0
+progress_interval=0
+system=system
+tracer=system.cpu.tracer
+workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.dcache]
+type=BaseCache
+addr_ranges=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+prefetch_on_access=false
+prefetcher=Null
+prioritizeRequests=false
+repl=Null
+size=262144
+subblock_size=0
+system=system
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.slave[1]
+
+[system.cpu.dtb]
+type=X86TLB
+children=walker
+size=64
+walker=system.cpu.dtb.walker
+
+[system.cpu.dtb.walker]
+type=X86PagetableWalker
+system=system
+port=system.cpu.toL2Bus.slave[3]
+
+[system.cpu.icache]
+type=BaseCache
+addr_ranges=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+prefetch_on_access=false
+prefetcher=Null
+prioritizeRequests=false
+repl=Null
+size=131072
+subblock_size=0
+system=system
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.slave[0]
+
+[system.cpu.interrupts]
+type=X86LocalApic
+int_latency=1000
+pio_addr=2305843009213693952
+pio_latency=1000
+system=system
+int_master=system.membus.slave[2]
+int_slave=system.membus.master[2]
+pio=system.membus.master[1]
+
+[system.cpu.itb]
+type=X86TLB
+children=walker
+size=64
+walker=system.cpu.itb.walker
+
+[system.cpu.itb.walker]
+type=X86PagetableWalker
+system=system
+port=system.cpu.toL2Bus.slave[2]
+
+[system.cpu.l2cache]
+type=BaseCache
+addr_ranges=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=false
+latency=10000
+max_miss_count=0
+mshrs=10
+prefetch_on_access=false
+prefetcher=Null
+prioritizeRequests=false
+repl=Null
+size=2097152
+subblock_size=0
+system=system
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.master[0]
+mem_side=system.membus.slave[1]
+
+[system.cpu.toL2Bus]
+type=CoherentBus
+block_size=64
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+master=system.cpu.l2cache.cpu_side
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=mcf mcf.in
+cwd=build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/dist/m5/cpu2000/binaries/x86/linux/mcf
+gid=100
+input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=55300000000
+system=system
+uid=100
+
+[system.membus]
+type=CoherentBus
+block_size=64
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave
+slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master
+
+[system.physmem]
+type=SimpleMemory
+conf_table_reported=false
+file=
+in_addr_map=true
+latency=30000
+latency_var=0
+null=false
+range=0:268435455
+zero=false
+port=system.membus.master[0]
+

simulators/gem5/tests/long/se/10.mcf/ref/x86/linux/simple-timing/mcf.out

@@ -0,0 +1,999 @@
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simulators/gem5/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simerr

@@ -0,0 +1,4 @@
+warn: Sockets disabled, not accepting gdb connections
+warn: instruction 'fnstcw_Mw' unimplemented
+warn: instruction 'fldcw_Mw' unimplemented
+hack: be nice to actually delete the event here

simulators/gem5/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout

@@ -0,0 +1,26 @@
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jun  4 2012 13:44:28
+gem5 started Jun  4 2012 15:22:27
+gem5 executing on zizzer
+command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0.  Starting simulation...
+
+MCF SPEC version 1.6.I
+by  Andreas Loebel
+Copyright (c) 1998,1999   ZIB Berlin
+All Rights Reserved.
+
+nodes                      : 500
+active arcs                : 1905
+simplex iterations         : 1502
+flow value                 : 4990014995
+new implicit arcs          : 23867
+active arcs                : 25772
+simplex iterations         : 2663
+flow value                 : 3080014995
+checksum                   : 68389
+optimal
+Exiting @ tick 370010840000 because target called exit()

simulators/gem5/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt

@@ -0,0 +1,374 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds                                  0.370011                       # Number of seconds simulated
+sim_ticks                                370010840000                       # Number of ticks simulated
+final_tick                               370010840000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                 564351                       # Simulator instruction rate (inst/s)
+host_op_rate                                   993732                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1321716509                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 360832                       # Number of bytes of host memory used
+host_seconds                                   279.95                       # Real time elapsed on the host
+sim_insts                                   157988583                       # Number of instructions simulated
+sim_ops                                     278192520                       # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu.inst             51712                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data           4849088                       # Number of bytes read from this memory
+system.physmem.bytes_read::total              4900800                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        51712                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           51712                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      1885440                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           1885440                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst                808                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data              75767                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                 76575                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks           29460                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total                29460                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst               139758                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             13105259                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                13245017                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          139758                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             139758                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           5095634                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                5095634                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           5095634                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              139758                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            13105259                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               18340652                       # Total bandwidth to/from this memory (bytes/s)
+system.cpu.workload.num_syscalls                  444                       # Number of system calls
+system.cpu.numCycles                        740021680                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.committedInsts                   157988583                       # Number of instructions committed
+system.cpu.committedOps                     278192520                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses             278186228                       # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses                     40                       # Number of float alu accesses
+system.cpu.num_func_calls                           0                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts     18628012                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                    278186228                       # number of integer instructions
+system.cpu.num_fp_insts                            40                       # number of float instructions
+system.cpu.num_int_register_reads           834011910                       # number of times the integer registers were read
+system.cpu.num_int_register_writes          341010914                       # number of times the integer registers were written
+system.cpu.num_fp_register_reads                   40                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes                  26                       # number of times the floating registers were written
+system.cpu.num_mem_refs                     122219139                       # number of memory refs
+system.cpu.num_load_insts                    90779388                       # Number of load instructions
+system.cpu.num_store_insts                   31439751                       # Number of store instructions
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
+system.cpu.num_busy_cycles                  740021680                       # Number of busy cycles
+system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                            0                       # Percentage of idle cycles
+system.cpu.icache.replacements                     24                       # number of replacements
+system.cpu.icache.tagsinuse                666.191948                       # Cycle average of tags in use
+system.cpu.icache.total_refs                217695401                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                    808                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs               269425.001238                       # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::cpu.inst     666.191948                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.325289                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.325289                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst    217695401                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       217695401                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     217695401                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        217695401                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    217695401                       # number of overall hits
+system.cpu.icache.overall_hits::total       217695401                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst          808                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total           808                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst          808                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total            808                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst          808                       # number of overall misses
+system.cpu.icache.overall_misses::total           808                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     45248000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     45248000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     45248000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     45248000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     45248000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     45248000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    217696209                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    217696209                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    217696209                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    217696209                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    217696209                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    217696209                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000004                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.000004                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000004                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.000004                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000004                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.000004                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst        56000                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total        56000                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst        56000                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total        56000                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst        56000                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total        56000                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.icache.fast_writes                       0                       # number of fast writes performed
+system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst          808                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total          808                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst          808                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total          808                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst          808                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total          808                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     42824000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     42824000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     42824000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     42824000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     42824000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     42824000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000004                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000004                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000004                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.000004                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000004                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.000004                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst        53000                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total        53000                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst        53000                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total        53000                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst        53000                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total        53000                       # average overall mshr miss latency
+system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.replacements                2062733                       # number of replacements
+system.cpu.dcache.tagsinuse               4076.661903                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                120152372                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                2066829                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                  58.133678                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle           126200130000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data    4076.661903                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.995279                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.995279                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data     88818730                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        88818730                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     31333642                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       31333642                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data     120152372                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        120152372                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    120152372                       # number of overall hits
+system.cpu.dcache.overall_hits::total       120152372                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      1960720                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       1960720                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       106109                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       106109                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data      2066829                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        2066829                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      2066829                       # number of overall misses
+system.cpu.dcache.overall_misses::total       2066829                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  28849058000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  28849058000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data   3268793000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   3268793000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  32117851000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  32117851000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  32117851000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  32117851000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     90779450                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     90779450                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data     31439751                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total     31439751                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data    122219201                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    122219201                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    122219201                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    122219201                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.021599                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.021599                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.003375                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.003375                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.016911                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.016911                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.016911                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.016911                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14713.502183                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 14713.502183                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30805.991952                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 30805.991952                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 15539.675029                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 15539.675029                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 15539.675029                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 15539.675029                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.writebacks::writebacks      1437080                       # number of writebacks
+system.cpu.dcache.writebacks::total           1437080                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1960720                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      1960720                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       106109                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       106109                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      2066829                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      2066829                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      2066829                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      2066829                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  22966898000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  22966898000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   2950464500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   2950464500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  25917362500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  25917362500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  25917362500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  25917362500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.021599                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.021599                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.003375                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.003375                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.016911                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.016911                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.016911                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.016911                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11713.502183                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11713.502183                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27805.977815                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27805.977815                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12539.674303                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 12539.674303                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12539.674303                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 12539.674303                       # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.l2cache.replacements                 49212                       # number of replacements
+system.cpu.l2cache.tagsinuse             18614.603260                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                 3296079                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                 77127                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                 42.735735                       # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::writebacks 12062.804989                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst    196.794797                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data   6355.003474                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks     0.368128                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst     0.006006                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.193939                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.568073                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.data      1927411                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total        1927411                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks      1437080                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total      1437080                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data        63651                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total        63651                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.data      1991062                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         1991062                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.data      1991062                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        1991062                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst          808                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data        33309                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total        34117                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data        42458                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total        42458                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst          808                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data        75767                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total         76575                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst          808                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data        75767                       # number of overall misses
+system.cpu.l2cache.overall_misses::total        76575                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     42016000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data   1732068000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total   1774084000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   2207845500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   2207845500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     42016000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data   3939913500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total   3981929500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     42016000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data   3939913500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total   3981929500                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst          808                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data      1960720                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total      1961528                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks      1437080                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total      1437080                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       106109                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       106109                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst          808                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data      2066829                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      2067637                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst          808                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data      2066829                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      2067637                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst            1                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.016988                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.017393                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.400136                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.400136                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst            1                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.036659                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.037035                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst            1                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.036659                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.037035                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst        52000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data        52000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total        52000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000.694804                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000.694804                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000.389352                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 52000.385243                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000.389352                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 52000.385243                       # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
+system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
+system.cpu.l2cache.writebacks::writebacks        29460                       # number of writebacks
+system.cpu.l2cache.writebacks::total            29460                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          808                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        33309                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total        34117                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        42458                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total        42458                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst          808                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data        75767                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total        76575                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst          808                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data        75767                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total        76575                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     32320000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   1332360000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total   1364680000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   1698320000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   1698320000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     32320000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   3030680000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total   3063000000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     32320000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   3030680000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total   3063000000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.016988                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.017393                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.400136                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.400136                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.036659                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.037035                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.036659                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.037035                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst        40000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total        40000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total        40000                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total        40000                       # average overall mshr miss latency
+system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+
+---------- End Simulation Statistics   ----------