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Adding gem5 source to svn.

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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1819 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
This commit is contained in:
friemel
2012-10-24 19:18:57 +00:00
parent f7ff71bd46
commit b41eec3f65
3222 changed files with 658579 additions and 1 deletions
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231
simulators/gem5/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/config.ini Normal file
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[root]
type=Root
children=system
full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
boot_osflags=a
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
readfile=
symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.cpu]
type=InOrderCPU
children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
BTBEntries=4096
BTBTagSize=16
RASSize=16
activity=0
cachePorts=2
checker=Null
choiceCtrBits=2
choicePredictorSize=8192
clock=500
cpu_id=0
defer_registration=false
div16Latency=1
div16RepeatRate=1
div24Latency=1
div24RepeatRate=1
div32Latency=1
div32RepeatRate=1
div8Latency=1
div8RepeatRate=1
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
fetchBuffSize=4
functionTrace=false
functionTraceStart=0
function_trace=false
function_trace_start=0
globalCtrBits=2
globalHistoryBits=13
globalPredictorSize=8192
instShiftAmt=2
interrupts=system.cpu.interrupts
itb=system.cpu.itb
localCtrBits=2
localHistoryBits=11
localHistoryTableSize=2048
localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
memBlockSize=64
multLatency=1
multRepeatRate=1
numThreads=1
phase=0
predType=tournament
profile=0
progress_interval=0
stageTracing=false
stageWidth=4
system=system
threadModel=SMT
tracer=system.cpu.tracer
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=262144
subblock_size=0
system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
[system.cpu.dtb]
type=AlphaTLB
size=64
[system.cpu.icache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=131072
subblock_size=0
system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.interrupts]
type=AlphaInterrupts
[system.cpu.itb]
type=AlphaTLB
size=48
[system.cpu.l2cache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=false
latency=10000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=2097152
subblock_size=0
system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
[system.cpu.toL2Bus]
type=CoherentBus
block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=gzip input.log 1
cwd=build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/inorder-timing
egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip
gid=100
input=cin
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=0
system=system
uid=100
[system.membus]
type=CoherentBus
block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
master=system.physmem.port[0]
slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=SimpleMemory
conf_table_reported=false
file=
in_addr_map=true
latency=30000
latency_var=0
null=false
range=0:134217727
zero=false
port=system.membus.master[0]

6
simulators/gem5/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simerr Executable file
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warn: Sockets disabled, not accepting gdb connections
warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
hack: be nice to actually delete the event here

42
simulators/gem5/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simout Executable file
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gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 4 2012 11:50:11
gem5 started Jun 4 2012 13:43:43
gem5 executing on zizzer
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/inorder-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
spec_init
Loading Input Data
Duplicating 262144 bytes
Duplicating 524288 bytes
Input data 1048576 bytes in length
Compressing Input Data, level 1
Compressed data 108074 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Compressing Input Data, level 3
Compressed data 97831 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Compressing Input Data, level 5
Compressed data 83382 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Compressing Input Data, level 7
Compressed data 76606 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Compressing Input Data, level 9
Compressed data 73189 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
Exiting @ tick 274300226500 because target called exit()

466
simulators/gem5/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt Normal file
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---------- Begin Simulation Statistics ----------
sim_seconds 0.274300 # Number of seconds simulated
sim_ticks 274300226500 # Number of ticks simulated
final_tick 274300226500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 112537 # Simulator instruction rate (inst/s)
host_op_rate 112537 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 51289289 # Simulator tick rate (ticks/s)
host_mem_usage 215256 # Number of bytes of host memory used
host_seconds 5348.10 # Real time elapsed on the host
sim_insts 601856964 # Number of instructions simulated
sim_ops 601856964 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 54720 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 5839360 # Number of bytes read from this memory
system.physmem.bytes_read::total 5894080 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 54720 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 54720 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 3798144 # Number of bytes written to this memory
system.physmem.bytes_written::total 3798144 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 855 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 91240 # Number of read requests responded to by this memory
system.physmem.num_reads::total 92095 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 59346 # Number of write requests responded to by this memory
system.physmem.num_writes::total 59346 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 199489 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 21288207 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 21487696 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 199489 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 199489 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 13846667 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 13846667 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 13846667 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 199489 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 21288207 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 35334364 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 114517577 # DTB read hits
system.cpu.dtb.read_misses 2631 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 114520208 # DTB read accesses
system.cpu.dtb.write_hits 39666608 # DTB write hits
system.cpu.dtb.write_misses 2302 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 39668910 # DTB write accesses
system.cpu.dtb.data_hits 154184185 # DTB hits
system.cpu.dtb.data_misses 4933 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 154189118 # DTB accesses
system.cpu.itb.fetch_hits 25020502 # ITB hits
system.cpu.itb.fetch_misses 22 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 25020524 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 17 # Number of system calls
system.cpu.numCycles 548600454 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.branch_predictor.lookups 86318297 # Number of BP lookups
system.cpu.branch_predictor.condPredicted 81372201 # Number of conditional branches predicted
system.cpu.branch_predictor.condIncorrect 36359139 # Number of conditional branches incorrect
system.cpu.branch_predictor.BTBLookups 52872243 # Number of BTB lookups
system.cpu.branch_predictor.BTBHits 34320184 # Number of BTB hits
system.cpu.branch_predictor.usedRAS 1197609 # Number of times the RAS was used to get a target.
system.cpu.branch_predictor.RASInCorrect 6 # Number of incorrect RAS predictions.
system.cpu.branch_predictor.BTBHitPct 64.911534 # BTB Hit Percentage
system.cpu.branch_predictor.predictedTaken 36897167 # Number of Branches Predicted As Taken (True).
system.cpu.branch_predictor.predictedNotTaken 49421130 # Number of Branches Predicted As Not Taken (False).
system.cpu.regfile_manager.intRegFileReads 541659172 # Number of Reads from Int. Register File
system.cpu.regfile_manager.intRegFileWrites 463854846 # Number of Writes to Int. Register File
system.cpu.regfile_manager.intRegFileAccesses 1005514018 # Total Accesses (Read+Write) to the Int. Register File
system.cpu.regfile_manager.floatRegFileReads 161 # Number of Reads from FP Register File
system.cpu.regfile_manager.floatRegFileWrites 42 # Number of Writes to FP Register File
system.cpu.regfile_manager.floatRegFileAccesses 203 # Total Accesses (Read+Write) to the FP Register File
system.cpu.regfile_manager.regForwards 254972528 # Number of Registers Read Through Forwarding Logic
system.cpu.agen_unit.agens 155051949 # Number of Address Generations
system.cpu.execution_unit.predictedTakenIncorrect 33760596 # Number of Branches Incorrectly Predicted As Taken.
system.cpu.execution_unit.predictedNotTakenIncorrect 2593556 # Number of Branches Incorrectly Predicted As Not Taken).
system.cpu.execution_unit.mispredicted 36354152 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.predicted 26193756 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.mispredictPct 58.122091 # Percentage of Incorrect Branches Predicts
system.cpu.execution_unit.executions 412334574 # Number of Instructions Executed.
system.cpu.mult_div_unit.multiplies 6482 # Number of Multipy Operations Executed
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
system.cpu.contextSwitches 1 # Number of context switches
system.cpu.threadCycles 538371184 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
system.cpu.timesIdled 412150 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 59439534 # Number of cycles cpu's stages were not processed
system.cpu.runCycles 489160920 # Number of cycles cpu stages are processed.
system.cpu.activity 89.165242 # Percentage of cycles cpu is active
system.cpu.comLoads 114514042 # Number of Load instructions committed
system.cpu.comStores 39451321 # Number of Store instructions committed
system.cpu.comBranches 62547159 # Number of Branches instructions committed
system.cpu.comNops 36304520 # Number of Nop instructions committed
system.cpu.comNonSpec 17 # Number of Non-Speculative instructions committed
system.cpu.comInts 349039879 # Number of Integer instructions committed
system.cpu.comFloats 24 # Number of Floating Point instructions committed
system.cpu.committedInsts 601856964 # Number of Instructions committed (Per-Thread)
system.cpu.committedOps 601856964 # Number of Ops committed (Per-Thread)
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
system.cpu.committedInsts_total 601856964 # Number of Instructions committed (Total)
system.cpu.cpi 0.911513 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.smt_cpi nan # CPI: Total SMT-CPI
system.cpu.cpi_total 0.911513 # CPI: Total CPI of All Threads
system.cpu.ipc 1.097077 # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.smt_ipc nan # IPC: Total SMT-IPC
system.cpu.ipc_total 1.097077 # IPC: Total IPC of All Threads
system.cpu.stage0.idleCycles 209725198 # Number of cycles 0 instructions are processed.
system.cpu.stage0.runCycles 338875256 # Number of cycles 1+ instructions are processed.
system.cpu.stage0.utilization 61.770867 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage1.idleCycles 237724577 # Number of cycles 0 instructions are processed.
system.cpu.stage1.runCycles 310875877 # Number of cycles 1+ instructions are processed.
system.cpu.stage1.utilization 56.667083 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage2.idleCycles 206774969 # Number of cycles 0 instructions are processed.
system.cpu.stage2.runCycles 341825485 # Number of cycles 1+ instructions are processed.
system.cpu.stage2.utilization 62.308641 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage3.idleCycles 437071966 # Number of cycles 0 instructions are processed.
system.cpu.stage3.runCycles 111528488 # Number of cycles 1+ instructions are processed.
system.cpu.stage3.utilization 20.329638 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage4.idleCycles 201598142 # Number of cycles 0 instructions are processed.
system.cpu.stage4.runCycles 347002312 # Number of cycles 1+ instructions are processed.
system.cpu.stage4.utilization 63.252283 # Percentage of cycles stage was utilized (processing insts).
system.cpu.icache.replacements 30 # number of replacements
system.cpu.icache.tagsinuse 728.232127 # Cycle average of tags in use
system.cpu.icache.total_refs 25019479 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 855 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 29262.548538 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 728.232127 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.355582 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.355582 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 25019479 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 25019479 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 25019479 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 25019479 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 25019479 # number of overall hits
system.cpu.icache.overall_hits::total 25019479 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 1021 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 1021 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 1021 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 1021 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 1021 # number of overall misses
system.cpu.icache.overall_misses::total 1021 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 56709500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 56709500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 56709500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 56709500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 56709500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 56709500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 25020500 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 25020500 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 25020500 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 25020500 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 25020500 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 25020500 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000041 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000041 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000041 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000041 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000041 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000041 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55543.095005 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 55543.095005 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 55543.095005 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 55543.095005 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 55543.095005 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 55543.095005 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 87500 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets 29166.666667 # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 166 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 166 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 166 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 166 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 166 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 166 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 855 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 855 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 855 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 855 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 855 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 855 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 45765000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 45765000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 45765000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 45765000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 45765000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 45765000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000034 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000034 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000034 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53526.315789 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53526.315789 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53526.315789 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 53526.315789 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53526.315789 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 53526.315789 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 451299 # number of replacements
system.cpu.dcache.tagsinuse 4094.124914 # Cycle average of tags in use
system.cpu.dcache.total_refs 152394215 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 334.641827 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 267632000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 4094.124914 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.999542 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.999542 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 114120509 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 114120509 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 38273706 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 38273706 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 152394215 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 152394215 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 152394215 # number of overall hits
system.cpu.dcache.overall_hits::total 152394215 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 393533 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 393533 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 1177615 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 1177615 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 1571148 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 1571148 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 1571148 # number of overall misses
system.cpu.dcache.overall_misses::total 1571148 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 8150462000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 8150462000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 25247540000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 25247540000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 33398002000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 33398002000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 33398002000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 33398002000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 114514042 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 114514042 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 39451321 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 39451321 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 153965363 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 153965363 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 153965363 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 153965363 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003437 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.003437 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029850 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.029850 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.010205 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.010205 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.010205 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.010205 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20711.000094 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 20711.000094 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 21439.553674 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 21439.553674 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 21257.069353 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 21257.069353 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 21257.069353 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 21257.069353 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 12006000 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 3424818500 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 2777 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 216268 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 4323.370544 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 15835.992842 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 408190 # number of writebacks
system.cpu.dcache.writebacks::total 408190 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 192301 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 192301 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 923452 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 923452 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 1115753 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 1115753 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 1115753 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 1115753 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 201232 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 201232 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 254163 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 254163 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 455395 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 455395 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 455395 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 455395 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3562095500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 3562095500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5466864500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 5466864500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9028960000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 9028960000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9028960000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 9028960000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001757 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001757 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006442 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006442 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.002958 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.002958 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17701.436650 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17701.436650 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 21509.285380 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 21509.285380 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19826.655980 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 19826.655980 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19826.655980 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 19826.655980 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 73798 # number of replacements
system.cpu.l2cache.tagsinuse 17696.811171 # Cycle average of tags in use
system.cpu.l2cache.total_refs 445686 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 89684 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 4.969515 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 16057.614667 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 28.392088 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 1610.804416 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.490040 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.000866 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.049158 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.540064 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.data 170049 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 170049 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 408190 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 408190 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 194106 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 194106 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.data 364155 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 364155 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.data 364155 # number of overall hits
system.cpu.l2cache.overall_hits::total 364155 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 855 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 31164 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 32019 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 60076 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 60076 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 855 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 91240 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 92095 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 855 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 91240 # number of overall misses
system.cpu.l2cache.overall_misses::total 92095 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 44767500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1630159000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 1674926500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3134429000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 3134429000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 44767500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 4764588000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 4809355500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 44767500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 4764588000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 4809355500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 855 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 201213 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 202068 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 408190 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 408190 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 254182 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 254182 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 855 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 455395 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 456250 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 855 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 455395 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 456250 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.154881 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.158457 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.236350 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.236350 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.200354 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.201852 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.200354 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.201852 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52359.649123 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52309.042485 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52310.393829 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52174.395765 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52174.395765 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52359.649123 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52220.385796 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 52221.678701 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52359.649123 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52220.385796 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 52221.678701 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 1278500 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 127 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 10066.929134 # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks 59346 # number of writebacks
system.cpu.l2cache.writebacks::total 59346 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 855 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 31164 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 32019 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 60076 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 60076 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 855 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 91240 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 92095 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 855 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 91240 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 92095 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 34345000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1246682000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1281027000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2406884500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2406884500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 34345000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3653566500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 3687911500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 34345000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3653566500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 3687911500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.154881 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.158457 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.236350 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.236350 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.200354 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.201852 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.200354 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.201852 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40169.590643 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40003.914773 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40008.338799 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40063.993941 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40063.993941 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40169.590643 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40043.473257 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40044.644117 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40169.590643 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40043.473257 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40044.644117 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

529
simulators/gem5/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/config.ini Normal file
View File

@ -0,0 +1,529 @@
[root]
type=Root
children=system
full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
boot_osflags=a
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
readfile=
symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.cpu]
type=DerivO3CPU
children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
LSQDepCheckShift=4
RASSize=16
SQEntries=32
SSITSize=1024
activity=0
backComSize=5
cachePorts=200
checker=Null
choiceCtrBits=2
choicePredictorSize=8192
clock=500
commitToDecodeDelay=1
commitToFetchDelay=1
commitToIEWDelay=1
commitToRenameDelay=1
commitWidth=8
cpu_id=0
decodeToFetchDelay=1
decodeToRenameDelay=1
decodeWidth=8
defer_registration=false
dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
fetchToDecodeDelay=1
fetchTrapLatency=1
fetchWidth=8
forwardComSize=5
fuPool=system.cpu.fuPool
function_trace=false
function_trace_start=0
globalCtrBits=2
globalHistoryBits=13
globalPredictorSize=8192
iewToCommitDelay=1
iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
instShiftAmt=2
interrupts=system.cpu.interrupts
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
localCtrBits=2
localHistoryBits=11
localHistoryTableSize=2048
localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
needsTSO=false
numIQEntries=64
numPhysFloatRegs=256
numPhysIntRegs=256
numROBEntries=192
numRobs=1
numThreads=1
phase=0
predType=tournament
profile=0
progress_interval=0
renameToDecodeDelay=1
renameToFetchDelay=1
renameToIEWDelay=2
renameToROBDelay=1
renameWidth=8
smtCommitPolicy=RoundRobin
smtFetchPolicy=SingleThread
smtIQPolicy=Partitioned
smtIQThreshold=100
smtLSQPolicy=Partitioned
smtLSQThreshold=100
smtNumFetchingThreads=1
smtROBPolicy=Partitioned
smtROBThreshold=100
squashWidth=8
store_set_clear_period=250000
system=system
tracer=system.cpu.tracer
trapLatency=13
wbDepth=1
wbWidth=8
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=262144
subblock_size=0
system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
[system.cpu.dtb]
type=AlphaTLB
size=64
[system.cpu.fuPool]
type=FUPool
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
[system.cpu.fuPool.FUList0]
type=FUDesc
children=opList
count=6
opList=system.cpu.fuPool.FUList0.opList
[system.cpu.fuPool.FUList0.opList]
type=OpDesc
issueLat=1
opClass=IntAlu
opLat=1
[system.cpu.fuPool.FUList1]
type=FUDesc
children=opList0 opList1
count=2
opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
[system.cpu.fuPool.FUList1.opList0]
type=OpDesc
issueLat=1
opClass=IntMult
opLat=3
[system.cpu.fuPool.FUList1.opList1]
type=OpDesc
issueLat=19
opClass=IntDiv
opLat=20
[system.cpu.fuPool.FUList2]
type=FUDesc
children=opList0 opList1 opList2
count=4
opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
[system.cpu.fuPool.FUList2.opList0]
type=OpDesc
issueLat=1
opClass=FloatAdd
opLat=2
[system.cpu.fuPool.FUList2.opList1]
type=OpDesc
issueLat=1
opClass=FloatCmp
opLat=2
[system.cpu.fuPool.FUList2.opList2]
type=OpDesc
issueLat=1
opClass=FloatCvt
opLat=2
[system.cpu.fuPool.FUList3]
type=FUDesc
children=opList0 opList1 opList2
count=2
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
[system.cpu.fuPool.FUList3.opList0]
type=OpDesc
issueLat=1
opClass=FloatMult
opLat=4
[system.cpu.fuPool.FUList3.opList1]
type=OpDesc
issueLat=12
opClass=FloatDiv
opLat=12
[system.cpu.fuPool.FUList3.opList2]
type=OpDesc
issueLat=24
opClass=FloatSqrt
opLat=24
[system.cpu.fuPool.FUList4]
type=FUDesc
children=opList
count=0
opList=system.cpu.fuPool.FUList4.opList
[system.cpu.fuPool.FUList4.opList]
type=OpDesc
issueLat=1
opClass=MemRead
opLat=1
[system.cpu.fuPool.FUList5]
type=FUDesc
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
count=4
opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
[system.cpu.fuPool.FUList5.opList00]
type=OpDesc
issueLat=1
opClass=SimdAdd
opLat=1
[system.cpu.fuPool.FUList5.opList01]
type=OpDesc
issueLat=1
opClass=SimdAddAcc
opLat=1
[system.cpu.fuPool.FUList5.opList02]
type=OpDesc
issueLat=1
opClass=SimdAlu
opLat=1
[system.cpu.fuPool.FUList5.opList03]
type=OpDesc
issueLat=1
opClass=SimdCmp
opLat=1
[system.cpu.fuPool.FUList5.opList04]
type=OpDesc
issueLat=1
opClass=SimdCvt
opLat=1
[system.cpu.fuPool.FUList5.opList05]
type=OpDesc
issueLat=1
opClass=SimdMisc
opLat=1
[system.cpu.fuPool.FUList5.opList06]
type=OpDesc
issueLat=1
opClass=SimdMult
opLat=1
[system.cpu.fuPool.FUList5.opList07]
type=OpDesc
issueLat=1
opClass=SimdMultAcc
opLat=1
[system.cpu.fuPool.FUList5.opList08]
type=OpDesc
issueLat=1
opClass=SimdShift
opLat=1
[system.cpu.fuPool.FUList5.opList09]
type=OpDesc
issueLat=1
opClass=SimdShiftAcc
opLat=1
[system.cpu.fuPool.FUList5.opList10]
type=OpDesc
issueLat=1
opClass=SimdSqrt
opLat=1
[system.cpu.fuPool.FUList5.opList11]
type=OpDesc
issueLat=1
opClass=SimdFloatAdd
opLat=1
[system.cpu.fuPool.FUList5.opList12]
type=OpDesc
issueLat=1
opClass=SimdFloatAlu
opLat=1
[system.cpu.fuPool.FUList5.opList13]
type=OpDesc
issueLat=1
opClass=SimdFloatCmp
opLat=1
[system.cpu.fuPool.FUList5.opList14]
type=OpDesc
issueLat=1
opClass=SimdFloatCvt
opLat=1
[system.cpu.fuPool.FUList5.opList15]
type=OpDesc
issueLat=1
opClass=SimdFloatDiv
opLat=1
[system.cpu.fuPool.FUList5.opList16]
type=OpDesc
issueLat=1
opClass=SimdFloatMisc
opLat=1
[system.cpu.fuPool.FUList5.opList17]
type=OpDesc
issueLat=1
opClass=SimdFloatMult
opLat=1
[system.cpu.fuPool.FUList5.opList18]
type=OpDesc
issueLat=1
opClass=SimdFloatMultAcc
opLat=1
[system.cpu.fuPool.FUList5.opList19]
type=OpDesc
issueLat=1
opClass=SimdFloatSqrt
opLat=1
[system.cpu.fuPool.FUList6]
type=FUDesc
children=opList
count=0
opList=system.cpu.fuPool.FUList6.opList
[system.cpu.fuPool.FUList6.opList]
type=OpDesc
issueLat=1
opClass=MemWrite
opLat=1
[system.cpu.fuPool.FUList7]
type=FUDesc
children=opList0 opList1
count=4
opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
[system.cpu.fuPool.FUList7.opList0]
type=OpDesc
issueLat=1
opClass=MemRead
opLat=1
[system.cpu.fuPool.FUList7.opList1]
type=OpDesc
issueLat=1
opClass=MemWrite
opLat=1
[system.cpu.fuPool.FUList8]
type=FUDesc
children=opList
count=1
opList=system.cpu.fuPool.FUList8.opList
[system.cpu.fuPool.FUList8.opList]
type=OpDesc
issueLat=3
opClass=IprAccess
opLat=3
[system.cpu.icache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=131072
subblock_size=0
system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.interrupts]
type=AlphaInterrupts
[system.cpu.itb]
type=AlphaTLB
size=48
[system.cpu.l2cache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=false
latency=1000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=2097152
subblock_size=0
system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
[system.cpu.toL2Bus]
type=CoherentBus
block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=gzip input.log 1
cwd=build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/o3-timing
egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip
gid=100
input=cin
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=0
system=system
uid=100
[system.membus]
type=CoherentBus
block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
master=system.physmem.port[0]
slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=SimpleMemory
conf_table_reported=false
file=
in_addr_map=true
latency=30000
latency_var=0
null=false
range=0:134217727
zero=false
port=system.membus.master[0]

6
simulators/gem5/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simerr Executable file
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@ -0,0 +1,6 @@
warn: Sockets disabled, not accepting gdb connections
warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
hack: be nice to actually delete the event here

42
simulators/gem5/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simout Executable file
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@ -0,0 +1,42 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 4 2012 11:50:11
gem5 started Jun 4 2012 13:42:45
gem5 executing on zizzer
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
spec_init
Loading Input Data
Duplicating 262144 bytes
Duplicating 524288 bytes
Input data 1048576 bytes in length
Compressing Input Data, level 1
Compressed data 108074 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Compressing Input Data, level 3
Compressed data 97831 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Compressing Input Data, level 5
Compressed data 83382 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Compressing Input Data, level 7
Compressed data 76606 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Compressing Input Data, level 9
Compressed data 73189 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
Exiting @ tick 134621123500 because target called exit()

682
simulators/gem5/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt Normal file
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@ -0,0 +1,682 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.134621 # Number of seconds simulated
sim_ticks 134621123500 # Number of ticks simulated
final_tick 134621123500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 192359 # Simulator instruction rate (inst/s)
host_op_rate 192359 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 45788058 # Simulator tick rate (ticks/s)
host_mem_usage 216172 # Number of bytes of host memory used
host_seconds 2940.09 # Real time elapsed on the host
sim_insts 565552443 # Number of instructions simulated
sim_ops 565552443 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 64128 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 5873472 # Number of bytes read from this memory
system.physmem.bytes_read::total 5937600 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 64128 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 64128 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 3797952 # Number of bytes written to this memory
system.physmem.bytes_written::total 3797952 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 1002 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 91773 # Number of read requests responded to by this memory
system.physmem.num_reads::total 92775 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 59343 # Number of write requests responded to by this memory
system.physmem.num_writes::total 59343 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 476359 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 43629646 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 44106005 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 476359 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 476359 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 28212155 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 28212155 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 28212155 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 476359 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 43629646 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 72318160 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 123836708 # DTB read hits
system.cpu.dtb.read_misses 23555 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 123860263 # DTB read accesses
system.cpu.dtb.write_hits 40831838 # DTB write hits
system.cpu.dtb.write_misses 31545 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 40863383 # DTB write accesses
system.cpu.dtb.data_hits 164668546 # DTB hits
system.cpu.dtb.data_misses 55100 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 164723646 # DTB accesses
system.cpu.itb.fetch_hits 66483943 # ITB hits
system.cpu.itb.fetch_misses 37 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 66483980 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 17 # Number of system calls
system.cpu.numCycles 269242248 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.BPredUnit.lookups 78494350 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 72856279 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 3049613 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 42772936 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 41636011 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 1626078 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 617 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 68428248 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 710832339 # Number of instructions fetch has processed
system.cpu.fetch.Branches 78494350 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 43262089 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 119193912 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 12932117 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 71677823 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 29 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 965 # Number of stall cycles due to pending traps
system.cpu.fetch.CacheLines 66483943 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 942005 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 269174552 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.640786 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.458790 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 149980640 55.72% 55.72% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 10366067 3.85% 59.57% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 11842490 4.40% 63.97% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 10610817 3.94% 67.91% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 6990702 2.60% 70.51% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 2664486 0.99% 71.50% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 3492691 1.30% 72.80% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 3105815 1.15% 73.95% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 70120844 26.05% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 269174552 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.291538 # Number of branch fetches per cycle
system.cpu.fetch.rate 2.640122 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 85707948 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 55913414 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 104656914 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 13023782 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 9872494 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 3909156 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 1160 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 702084562 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 4999 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 9872494 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 93982559 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 12740757 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 2287 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 104137265 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 48439190 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 690176100 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 220 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 36870562 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 5345683 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenamedOperands 527299875 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 906867454 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 906864467 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 2987 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 463854889 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 63444986 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 171 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 186 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 107659132 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 129005013 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 42430995 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 14679275 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 9584938 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 626474820 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 120 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 608397310 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 335936 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 60222555 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 33444580 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 103 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 269174552 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 2.260233 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.839356 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 54646313 20.30% 20.30% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 54798689 20.36% 40.66% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 53375432 19.83% 60.49% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 36717503 13.64% 74.13% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 30865027 11.47% 85.60% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 24096775 8.95% 94.55% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 10651297 3.96% 98.51% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 3344645 1.24% 99.75% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 678871 0.25% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 269174552 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 2904763 73.47% 73.47% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 39 0.00% 73.47% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 73.47% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 73.47% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 73.47% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 73.47% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 73.47% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 73.47% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 73.47% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 73.47% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 73.47% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 73.47% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 73.47% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 73.47% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 73.47% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 73.47% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 73.47% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 73.47% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 73.47% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 73.47% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 73.47% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 73.47% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 73.47% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 73.47% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 73.47% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 73.47% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 73.47% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 73.47% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 73.47% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 634502 16.05% 89.52% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 414382 10.48% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 441013335 72.49% 72.49% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 7329 0.00% 72.49% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 72.49% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 32 0.00% 72.49% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 5 0.00% 72.49% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 5 0.00% 72.49% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 5 0.00% 72.49% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 72.49% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 72.49% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 72.49% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 72.49% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 72.49% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 72.49% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 72.49% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 72.49% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 72.49% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 72.49% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 72.49% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 72.49% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 72.49% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 72.49% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 72.49% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 72.49% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 72.49% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 72.49% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 72.49% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 72.49% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 72.49% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 72.49% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 126118254 20.73% 93.22% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 41258345 6.78% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 608397310 # Type of FU issued
system.cpu.iq.rate 2.259665 # Inst issue rate
system.cpu.iq.fu_busy_cnt 3953686 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.006499 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 1490254859 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 686699872 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 598814509 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 3935 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 2431 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 1728 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 612349032 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 1964 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 12165746 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 14490971 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 33593 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 4856 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 2979674 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 6726 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 51107 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 9872494 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 1561922 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 98319 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 670401264 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 1688610 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 129005013 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 42430995 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 120 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 41033 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 13811 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 4856 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 1345444 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 2209649 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 3555093 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 602577350 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 123860441 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 5819960 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 43926324 # number of nop insts executed
system.cpu.iew.exec_refs 164740912 # number of memory reference insts executed
system.cpu.iew.exec_branches 67006670 # Number of branches executed
system.cpu.iew.exec_stores 40880471 # Number of stores executed
system.cpu.iew.exec_rate 2.238049 # Inst execution rate
system.cpu.iew.wb_sent 600066569 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 598816237 # cumulative count of insts written-back
system.cpu.iew.wb_producers 417486240 # num instructions producing a value
system.cpu.iew.wb_consumers 531487841 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 2.224080 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.785505 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitCommittedInsts 601856963 # The number of committed instructions
system.cpu.commit.commitCommittedOps 601856963 # The number of committed instructions
system.cpu.commit.commitSquashedInsts 68396273 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 3048532 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 259302058 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 2.321065 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.702332 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 80379492 31.00% 31.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 72839999 28.09% 59.09% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 26734500 10.31% 69.40% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 8121130 3.13% 72.53% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 10288458 3.97% 76.50% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 20405541 7.87% 84.37% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 6352213 2.45% 86.82% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 3556041 1.37% 88.19% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 30624684 11.81% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 259302058 # Number of insts commited each cycle
system.cpu.commit.committedInsts 601856963 # Number of instructions committed
system.cpu.commit.committedOps 601856963 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 153965363 # Number of memory references committed
system.cpu.commit.loads 114514042 # Number of loads committed
system.cpu.commit.membars 0 # Number of memory barriers committed
system.cpu.commit.branches 62547159 # Number of branches committed
system.cpu.commit.fp_insts 1520 # Number of committed floating point instructions.
system.cpu.commit.int_insts 563954763 # Number of committed integer instructions.
system.cpu.commit.function_calls 1197610 # Number of function calls committed.
system.cpu.commit.bw_lim_events 30624684 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 898866221 # The number of ROB reads
system.cpu.rob.rob_writes 1350401622 # The number of ROB writes
system.cpu.timesIdled 2160 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 67696 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 565552443 # Number of Instructions Simulated
system.cpu.committedOps 565552443 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 565552443 # Number of Instructions Simulated
system.cpu.cpi 0.476069 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.476069 # CPI: Total CPI of All Threads
system.cpu.ipc 2.100534 # IPC: Instructions Per Cycle
system.cpu.ipc_total 2.100534 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 848641681 # number of integer regfile reads
system.cpu.int_regfile_writes 492726607 # number of integer regfile writes
system.cpu.fp_regfile_reads 387 # number of floating regfile reads
system.cpu.fp_regfile_writes 54 # number of floating regfile writes
system.cpu.misc_regfile_reads 1 # number of misc regfile reads
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
system.cpu.icache.replacements 49 # number of replacements
system.cpu.icache.tagsinuse 844.563885 # Cycle average of tags in use
system.cpu.icache.total_refs 66482496 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 1002 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 66349.796407 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 844.563885 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.412385 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.412385 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 66482496 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 66482496 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 66482496 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 66482496 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 66482496 # number of overall hits
system.cpu.icache.overall_hits::total 66482496 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 1447 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 1447 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 1447 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 1447 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 1447 # number of overall misses
system.cpu.icache.overall_misses::total 1447 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 50567500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 50567500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 50567500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 50567500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 50567500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 50567500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 66483943 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 66483943 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 66483943 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 66483943 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 66483943 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 66483943 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000022 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000022 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000022 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000022 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000022 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000022 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34946.440912 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 34946.440912 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 34946.440912 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 34946.440912 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 34946.440912 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 34946.440912 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 445 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 445 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 445 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 445 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 445 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 445 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1002 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 1002 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 1002 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 1002 # number of demand (read+write) MSHR misses
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system.cpu.icache.overall_mshr_miss_latency::total 35750000 # number of overall MSHR miss cycles
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system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35678.642715 # average overall mshr miss latency
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system.cpu.dcache.overall_avg_miss_latency::cpu.data 15513.457453 # average overall miss latency
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system.cpu.dcache.overall_mshr_miss_latency::total 4648014495 # number of overall MSHR miss cycles
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system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 9999.192183 # average overall mshr miss latency
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system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.155864 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.235100 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.235100 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.197430 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.199156 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.197430 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.199156 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31140.718563 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31015.093158 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31018.914898 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31392.467997 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31392.467997 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31140.718563 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31261.149794 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31259.849097 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31140.718563 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31261.149794 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31259.849097 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

117
simulators/gem5/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/config.ini Normal file
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[root]
type=Root
children=system
full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
boot_osflags=a
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
readfile=
symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.cpu]
type=AtomicSimpleCPU
children=dtb interrupts itb tracer workload
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
fastmem=false
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
phase=0
profile=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
system=system
tracer=system.cpu.tracer
width=1
workload=system.cpu.workload
dcache_port=system.membus.slave[2]
icache_port=system.membus.slave[1]
[system.cpu.dtb]
type=AlphaTLB
size=64
[system.cpu.interrupts]
type=AlphaInterrupts
[system.cpu.itb]
type=AlphaTLB
size=48
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=gzip input.log 1
cwd=build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/simple-atomic
egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip
gid=100
input=cin
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=0
system=system
uid=100
[system.membus]
type=CoherentBus
block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
master=system.physmem.port[0]
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
[system.physmem]
type=SimpleMemory
conf_table_reported=false
file=
in_addr_map=true
latency=30000
latency_var=0
null=false
range=0:134217727
zero=false
port=system.membus.master[0]

7
simulators/gem5/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/simerr Executable file
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@ -0,0 +1,7 @@
warn: CoherentBus system.membus has no snooping ports attached!
warn: Sockets disabled, not accepting gdb connections
warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
hack: be nice to actually delete the event here

42
simulators/gem5/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/simout Executable file
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gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 4 2012 11:50:11
gem5 started Jun 4 2012 14:03:38
gem5 executing on zizzer
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
spec_init
Loading Input Data
Duplicating 262144 bytes
Duplicating 524288 bytes
Input data 1048576 bytes in length
Compressing Input Data, level 1
Compressed data 108074 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Compressing Input Data, level 3
Compressed data 97831 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Compressing Input Data, level 5
Compressed data 83382 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Compressing Input Data, level 7
Compressed data 76606 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Compressing Input Data, level 9
Compressed data 73189 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
Exiting @ tick 300930958000 because target called exit()

92
simulators/gem5/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt Normal file
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---------- Begin Simulation Statistics ----------
sim_seconds 0.300931 # Number of seconds simulated
sim_ticks 300930958000 # Number of ticks simulated
final_tick 300930958000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 3871430 # Simulator instruction rate (inst/s)
host_op_rate 3871429 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1935730316 # Simulator tick rate (ticks/s)
host_mem_usage 206040 # Number of bytes of host memory used
host_seconds 155.46 # Real time elapsed on the host
sim_insts 601856964 # Number of instructions simulated
sim_ops 601856964 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 2407447588 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 375543340 # Number of bytes read from this memory
system.physmem.bytes_read::total 2782990928 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 2407447588 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 2407447588 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 152669504 # Number of bytes written to this memory
system.physmem.bytes_written::total 152669504 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 601861897 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 114514042 # Number of read requests responded to by this memory
system.physmem.num_reads::total 716375939 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 39451321 # Number of write requests responded to by this memory
system.physmem.num_writes::total 39451321 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 7999999747 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 1247938539 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 9247938286 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 7999999747 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 7999999747 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 507324022 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 507324022 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 7999999747 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 1755262561 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 9755262308 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 114514042 # DTB read hits
system.cpu.dtb.read_misses 2631 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 114516673 # DTB read accesses
system.cpu.dtb.write_hits 39451321 # DTB write hits
system.cpu.dtb.write_misses 2302 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 39453623 # DTB write accesses
system.cpu.dtb.data_hits 153965363 # DTB hits
system.cpu.dtb.data_misses 4933 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 153970296 # DTB accesses
system.cpu.itb.fetch_hits 601861897 # ITB hits
system.cpu.itb.fetch_misses 20 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 601861917 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 17 # Number of system calls
system.cpu.numCycles 601861917 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 601856964 # Number of instructions committed
system.cpu.committedOps 601856964 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 563959696 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 1520 # Number of float alu accesses
system.cpu.num_func_calls 2395217 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 58554292 # number of instructions that are conditional controls
system.cpu.num_int_insts 563959696 # number of integer instructions
system.cpu.num_fp_insts 1520 # number of float instructions
system.cpu.num_int_register_reads 801088993 # number of times the integer registers were read
system.cpu.num_int_register_writes 463854847 # number of times the integer registers were written
system.cpu.num_fp_register_reads 169 # number of times the floating registers were read
system.cpu.num_fp_register_writes 42 # number of times the floating registers were written
system.cpu.num_mem_refs 153970296 # number of memory refs
system.cpu.num_load_insts 114516673 # Number of load instructions
system.cpu.num_store_insts 39453623 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 601861917 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
---------- End Simulation Statistics ----------

198
simulators/gem5/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/config.ini Normal file
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@ -0,0 +1,198 @@
[root]
type=Root
children=system
full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
boot_osflags=a
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
readfile=
symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.cpu]
type=TimingSimpleCPU
children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
phase=0
profile=0
progress_interval=0
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=262144
subblock_size=0
system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
[system.cpu.dtb]
type=AlphaTLB
size=64
[system.cpu.icache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=131072
subblock_size=0
system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.interrupts]
type=AlphaInterrupts
[system.cpu.itb]
type=AlphaTLB
size=48
[system.cpu.l2cache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=false
latency=10000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=2097152
subblock_size=0
system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
[system.cpu.toL2Bus]
type=CoherentBus
block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=gzip input.log 1
cwd=build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/simple-timing
egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip
gid=100
input=cin
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=0
system=system
uid=100
[system.membus]
type=CoherentBus
block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
master=system.physmem.port[0]
slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=SimpleMemory
conf_table_reported=false
file=
in_addr_map=true
latency=30000
latency_var=0
null=false
range=0:134217727
zero=false
port=system.membus.master[0]

6
simulators/gem5/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/simerr Executable file
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@ -0,0 +1,6 @@
warn: Sockets disabled, not accepting gdb connections
warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
hack: be nice to actually delete the event here

42
simulators/gem5/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/simout Executable file
View File

@ -0,0 +1,42 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 4 2012 11:50:11
gem5 started Jun 4 2012 13:42:36
gem5 executing on zizzer
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
spec_init
Loading Input Data
Duplicating 262144 bytes
Duplicating 524288 bytes
Input data 1048576 bytes in length
Compressing Input Data, level 1
Compressed data 108074 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Compressing Input Data, level 3
Compressed data 97831 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Compressing Input Data, level 5
Compressed data 83382 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Compressing Input Data, level 7
Compressed data 76606 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Compressing Input Data, level 9
Compressed data 73189 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
Exiting @ tick 765623032000 because target called exit()

406
simulators/gem5/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/stats.txt Normal file
View File

@ -0,0 +1,406 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.765623 # Number of seconds simulated
sim_ticks 765623032000 # Number of ticks simulated
final_tick 765623032000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1675799 # Simulator instruction rate (inst/s)
host_op_rate 1675799 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 2131786057 # Simulator tick rate (ticks/s)
host_mem_usage 214908 # Number of bytes of host memory used
host_seconds 359.15 # Real time elapsed on the host
sim_insts 601856964 # Number of instructions simulated
sim_ops 601856964 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 50880 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 5839104 # Number of bytes read from this memory
system.physmem.bytes_read::total 5889984 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 50880 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 50880 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 3797824 # Number of bytes written to this memory
system.physmem.bytes_written::total 3797824 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 795 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 91236 # Number of read requests responded to by this memory
system.physmem.num_reads::total 92031 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 59341 # Number of write requests responded to by this memory
system.physmem.num_writes::total 59341 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 66456 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 7626604 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 7693060 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 66456 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 66456 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 4960436 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 4960436 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 4960436 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 66456 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 7626604 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 12653496 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 114514042 # DTB read hits
system.cpu.dtb.read_misses 2631 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 114516673 # DTB read accesses
system.cpu.dtb.write_hits 39451321 # DTB write hits
system.cpu.dtb.write_misses 2302 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 39453623 # DTB write accesses
system.cpu.dtb.data_hits 153965363 # DTB hits
system.cpu.dtb.data_misses 4933 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 153970296 # DTB accesses
system.cpu.itb.fetch_hits 601861898 # ITB hits
system.cpu.itb.fetch_misses 20 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 601861918 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 17 # Number of system calls
system.cpu.numCycles 1531246064 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 601856964 # Number of instructions committed
system.cpu.committedOps 601856964 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 563959696 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 1520 # Number of float alu accesses
system.cpu.num_func_calls 2395217 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 58554292 # number of instructions that are conditional controls
system.cpu.num_int_insts 563959696 # number of integer instructions
system.cpu.num_fp_insts 1520 # number of float instructions
system.cpu.num_int_register_reads 801088993 # number of times the integer registers were read
system.cpu.num_int_register_writes 463854847 # number of times the integer registers were written
system.cpu.num_fp_register_reads 169 # number of times the floating registers were read
system.cpu.num_fp_register_writes 42 # number of times the floating registers were written
system.cpu.num_mem_refs 153970296 # number of memory refs
system.cpu.num_load_insts 114516673 # Number of load instructions
system.cpu.num_store_insts 39453623 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 1531246064 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.icache.replacements 24 # number of replacements
system.cpu.icache.tagsinuse 673.337154 # Cycle average of tags in use
system.cpu.icache.total_refs 601861103 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 795 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 757057.991195 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 673.337154 # Average occupied blocks per requestor
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system.cpu.icache.ReadReq_miss_latency::total 44520000 # number of ReadReq miss cycles
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system.cpu.icache.overall_miss_latency::total 44520000 # number of overall miss cycles
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system.cpu.icache.ReadReq_accesses::total 601861898 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.overall_accesses::total 601861898 # number of overall (read+write) accesses
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system.cpu.icache.ReadReq_miss_rate::total 0.000001 # miss rate for ReadReq accesses
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system.cpu.icache.overall_miss_rate::total 0.000001 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56000 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 56000 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 56000 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 56000 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 56000 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 56000 # average overall miss latency
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system.cpu.icache.demand_mshr_miss_latency::cpu.inst 42135000 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_latency::total 42135000 # number of overall MSHR miss cycles
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system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53000 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 451299 # number of replacements
system.cpu.dcache.tagsinuse 4094.170317 # Cycle average of tags in use
system.cpu.dcache.total_refs 153509968 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks.
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system.cpu.dcache.warmup_cycle 578392000 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20504.999205 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 20504.999205 # average ReadReq miss latency
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system.cpu.dcache.writebacks::writebacks 408190 # number of writebacks
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system.cpu.dcache.overall_mshr_miss_latency::total 8841257000 # number of overall MSHR miss cycles
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17504.999205 # average ReadReq mshr miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19414.479737 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 19414.479737 # average overall mshr miss latency
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system.cpu.l2cache.replacements 73734 # number of replacements
system.cpu.l2cache.tagsinuse 17823.514890 # Cycle average of tags in use
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system.cpu.l2cache.Writeback_hits::total 408190 # number of Writeback hits
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system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks 59341 # number of writebacks
system.cpu.l2cache.writebacks::total 59341 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 795 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 31167 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 31962 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 60069 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 60069 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 795 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 91236 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 92031 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 795 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 91236 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 92031 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 31800000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1246680000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1278480000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2402760000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2402760000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 31800000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3649440000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 3681240000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 31800000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3649440000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 3681240000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.154881 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.158207 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.236340 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.236340 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.200345 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.201738 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.200345 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.201738 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

547
simulators/gem5/tests/long/se/00.gzip/ref/arm/linux/o3-timing/config.ini Normal file
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@ -0,0 +1,547 @@
[root]
type=Root
children=system
full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
boot_osflags=a
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
readfile=
symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.cpu]
type=DerivO3CPU
children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
LSQDepCheckShift=4
RASSize=16
SQEntries=32
SSITSize=1024
activity=0
backComSize=5
cachePorts=200
checker=Null
choiceCtrBits=2
choicePredictorSize=8192
clock=500
commitToDecodeDelay=1
commitToFetchDelay=1
commitToIEWDelay=1
commitToRenameDelay=1
commitWidth=8
cpu_id=0
decodeToFetchDelay=1
decodeToRenameDelay=1
decodeWidth=8
defer_registration=false
dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
fetchToDecodeDelay=1
fetchTrapLatency=1
fetchWidth=8
forwardComSize=5
fuPool=system.cpu.fuPool
function_trace=false
function_trace_start=0
globalCtrBits=2
globalHistoryBits=13
globalPredictorSize=8192
iewToCommitDelay=1
iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
instShiftAmt=2
interrupts=system.cpu.interrupts
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
localCtrBits=2
localHistoryBits=11
localHistoryTableSize=2048
localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
needsTSO=false
numIQEntries=64
numPhysFloatRegs=256
numPhysIntRegs=256
numROBEntries=192
numRobs=1
numThreads=1
phase=0
predType=tournament
profile=0
progress_interval=0
renameToDecodeDelay=1
renameToFetchDelay=1
renameToIEWDelay=2
renameToROBDelay=1
renameWidth=8
smtCommitPolicy=RoundRobin
smtFetchPolicy=SingleThread
smtIQPolicy=Partitioned
smtIQThreshold=100
smtLSQPolicy=Partitioned
smtLSQThreshold=100
smtNumFetchingThreads=1
smtROBPolicy=Partitioned
smtROBThreshold=100
squashWidth=8
store_set_clear_period=250000
system=system
tracer=system.cpu.tracer
trapLatency=13
wbDepth=1
wbWidth=8
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=262144
subblock_size=0
system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
[system.cpu.dtb]
type=ArmTLB
children=walker
size=64
walker=system.cpu.dtb.walker
[system.cpu.dtb.walker]
type=ArmTableWalker
max_backoff=100000
min_backoff=0
sys=system
port=system.cpu.toL2Bus.slave[3]
[system.cpu.fuPool]
type=FUPool
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
[system.cpu.fuPool.FUList0]
type=FUDesc
children=opList
count=6
opList=system.cpu.fuPool.FUList0.opList
[system.cpu.fuPool.FUList0.opList]
type=OpDesc
issueLat=1
opClass=IntAlu
opLat=1
[system.cpu.fuPool.FUList1]
type=FUDesc
children=opList0 opList1
count=2
opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
[system.cpu.fuPool.FUList1.opList0]
type=OpDesc
issueLat=1
opClass=IntMult
opLat=3
[system.cpu.fuPool.FUList1.opList1]
type=OpDesc
issueLat=19
opClass=IntDiv
opLat=20
[system.cpu.fuPool.FUList2]
type=FUDesc
children=opList0 opList1 opList2
count=4
opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
[system.cpu.fuPool.FUList2.opList0]
type=OpDesc
issueLat=1
opClass=FloatAdd
opLat=2
[system.cpu.fuPool.FUList2.opList1]
type=OpDesc
issueLat=1
opClass=FloatCmp
opLat=2
[system.cpu.fuPool.FUList2.opList2]
type=OpDesc
issueLat=1
opClass=FloatCvt
opLat=2
[system.cpu.fuPool.FUList3]
type=FUDesc
children=opList0 opList1 opList2
count=2
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
[system.cpu.fuPool.FUList3.opList0]
type=OpDesc
issueLat=1
opClass=FloatMult
opLat=4
[system.cpu.fuPool.FUList3.opList1]
type=OpDesc
issueLat=12
opClass=FloatDiv
opLat=12
[system.cpu.fuPool.FUList3.opList2]
type=OpDesc
issueLat=24
opClass=FloatSqrt
opLat=24
[system.cpu.fuPool.FUList4]
type=FUDesc
children=opList
count=0
opList=system.cpu.fuPool.FUList4.opList
[system.cpu.fuPool.FUList4.opList]
type=OpDesc
issueLat=1
opClass=MemRead
opLat=1
[system.cpu.fuPool.FUList5]
type=FUDesc
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
count=4
opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
[system.cpu.fuPool.FUList5.opList00]
type=OpDesc
issueLat=1
opClass=SimdAdd
opLat=1
[system.cpu.fuPool.FUList5.opList01]
type=OpDesc
issueLat=1
opClass=SimdAddAcc
opLat=1
[system.cpu.fuPool.FUList5.opList02]
type=OpDesc
issueLat=1
opClass=SimdAlu
opLat=1
[system.cpu.fuPool.FUList5.opList03]
type=OpDesc
issueLat=1
opClass=SimdCmp
opLat=1
[system.cpu.fuPool.FUList5.opList04]
type=OpDesc
issueLat=1
opClass=SimdCvt
opLat=1
[system.cpu.fuPool.FUList5.opList05]
type=OpDesc
issueLat=1
opClass=SimdMisc
opLat=1
[system.cpu.fuPool.FUList5.opList06]
type=OpDesc
issueLat=1
opClass=SimdMult
opLat=1
[system.cpu.fuPool.FUList5.opList07]
type=OpDesc
issueLat=1
opClass=SimdMultAcc
opLat=1
[system.cpu.fuPool.FUList5.opList08]
type=OpDesc
issueLat=1
opClass=SimdShift
opLat=1
[system.cpu.fuPool.FUList5.opList09]
type=OpDesc
issueLat=1
opClass=SimdShiftAcc
opLat=1
[system.cpu.fuPool.FUList5.opList10]
type=OpDesc
issueLat=1
opClass=SimdSqrt
opLat=1
[system.cpu.fuPool.FUList5.opList11]
type=OpDesc
issueLat=1
opClass=SimdFloatAdd
opLat=1
[system.cpu.fuPool.FUList5.opList12]
type=OpDesc
issueLat=1
opClass=SimdFloatAlu
opLat=1
[system.cpu.fuPool.FUList5.opList13]
type=OpDesc
issueLat=1
opClass=SimdFloatCmp
opLat=1
[system.cpu.fuPool.FUList5.opList14]
type=OpDesc
issueLat=1
opClass=SimdFloatCvt
opLat=1
[system.cpu.fuPool.FUList5.opList15]
type=OpDesc
issueLat=1
opClass=SimdFloatDiv
opLat=1
[system.cpu.fuPool.FUList5.opList16]
type=OpDesc
issueLat=1
opClass=SimdFloatMisc
opLat=1
[system.cpu.fuPool.FUList5.opList17]
type=OpDesc
issueLat=1
opClass=SimdFloatMult
opLat=1
[system.cpu.fuPool.FUList5.opList18]
type=OpDesc
issueLat=1
opClass=SimdFloatMultAcc
opLat=1
[system.cpu.fuPool.FUList5.opList19]
type=OpDesc
issueLat=1
opClass=SimdFloatSqrt
opLat=1
[system.cpu.fuPool.FUList6]
type=FUDesc
children=opList
count=0
opList=system.cpu.fuPool.FUList6.opList
[system.cpu.fuPool.FUList6.opList]
type=OpDesc
issueLat=1
opClass=MemWrite
opLat=1
[system.cpu.fuPool.FUList7]
type=FUDesc
children=opList0 opList1
count=4
opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
[system.cpu.fuPool.FUList7.opList0]
type=OpDesc
issueLat=1
opClass=MemRead
opLat=1
[system.cpu.fuPool.FUList7.opList1]
type=OpDesc
issueLat=1
opClass=MemWrite
opLat=1
[system.cpu.fuPool.FUList8]
type=FUDesc
children=opList
count=1
opList=system.cpu.fuPool.FUList8.opList
[system.cpu.fuPool.FUList8.opList]
type=OpDesc
issueLat=3
opClass=IprAccess
opLat=3
[system.cpu.icache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=131072
subblock_size=0
system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.interrupts]
type=ArmInterrupts
[system.cpu.itb]
type=ArmTLB
children=walker
size=64
walker=system.cpu.itb.walker
[system.cpu.itb.walker]
type=ArmTableWalker
max_backoff=100000
min_backoff=0
sys=system
port=system.cpu.toL2Bus.slave[2]
[system.cpu.l2cache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=false
latency=1000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=2097152
subblock_size=0
system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
[system.cpu.toL2Bus]
type=CoherentBus
block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=gzip input.log 1
cwd=build/ARM/tests/opt/long/se/00.gzip/arm/linux/o3-timing
egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/cpu2000/binaries/arm/linux/gzip
gid=100
input=cin
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=0
system=system
uid=100
[system.membus]
type=CoherentBus
block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
master=system.physmem.port[0]
slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=SimpleMemory
conf_table_reported=false
file=
in_addr_map=true
latency=30000
latency_var=0
null=false
range=0:134217727
zero=false
port=system.membus.master[0]

2
simulators/gem5/tests/long/se/00.gzip/ref/arm/linux/o3-timing/simerr Executable file
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@ -0,0 +1,2 @@
warn: Sockets disabled, not accepting gdb connections
hack: be nice to actually delete the event here

41
simulators/gem5/tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout Executable file
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@ -0,0 +1,41 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 4 2012 12:14:06
gem5 started Jun 4 2012 17:27:39
gem5 executing on zizzer
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/00.gzip/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/00.gzip/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
spec_init
Loading Input Data
Duplicating 262144 bytes
Duplicating 524288 bytes
Input data 1048576 bytes in length
Compressing Input Data, level 1
Compressed data 108074 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Compressing Input Data, level 3
Compressed data 97831 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Compressing Input Data, level 5
Compressed data 83382 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Compressing Input Data, level 7
Compressed data 76606 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Compressing Input Data, level 9
Compressed data 73189 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
Exiting @ tick 164248292500 because target called exit()

724
simulators/gem5/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt Normal file
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@ -0,0 +1,724 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.164248 # Number of seconds simulated
sim_ticks 164248292500 # Number of ticks simulated
final_tick 164248292500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 143439 # Simulator instruction rate (inst/s)
host_op_rate 151568 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 41328806 # Simulator tick rate (ticks/s)
host_mem_usage 231960 # Number of bytes of host memory used
host_seconds 3974.18 # Real time elapsed on the host
sim_insts 570052728 # Number of instructions simulated
sim_ops 602360935 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 51136 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 5799296 # Number of bytes read from this memory
system.physmem.bytes_read::total 5850432 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 51136 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 51136 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 3722112 # Number of bytes written to this memory
system.physmem.bytes_written::total 3722112 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 799 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 90614 # Number of read requests responded to by this memory
system.physmem.num_reads::total 91413 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 58158 # Number of write requests responded to by this memory
system.physmem.num_writes::total 58158 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 311334 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 35308105 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 35619439 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 311334 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 311334 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 22661496 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 22661496 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 22661496 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 311334 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 35308105 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 58280935 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 48 # Number of system calls
system.cpu.numCycles 328496586 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.BPredUnit.lookups 85500889 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 80301573 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 2363462 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 47194810 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 46809578 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 1441693 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 2047 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 68928725 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 669724193 # Number of instructions fetch has processed
system.cpu.fetch.Branches 85500889 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 48251271 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 130040939 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 13471504 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 117632066 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 26 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 466 # Number of stall cycles due to pending traps
system.cpu.fetch.CacheLines 67495318 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 807242 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 327633093 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.178244 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.200456 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 197592366 60.31% 60.31% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 20955363 6.40% 66.71% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 4944852 1.51% 68.21% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 14316797 4.37% 72.58% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 8978717 2.74% 75.32% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 9406752 2.87% 78.20% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 4386482 1.34% 79.53% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 5812411 1.77% 81.31% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 61239353 18.69% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 327633093 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.260279 # Number of branch fetches per cycle
system.cpu.fetch.rate 2.038755 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 93122772 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 94805335 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 108615724 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 20060132 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 11029130 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 4785077 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 1812 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 705993706 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 5866 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 11029130 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 107405098 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 13994903 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 53643 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 114322395 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 80827924 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 697209083 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 245 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 59229209 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 19383033 # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents 653 # Number of times there has been no free registers
system.cpu.rename.RenamedOperands 723812839 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 3241314962 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 3241314834 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 128 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 627419202 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 96393637 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 6694 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 6687 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 169956085 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 172904405 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 80621547 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 21577919 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 28225780 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 681971655 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 4856 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 646826004 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 1423990 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 79433587 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 197870891 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 1925 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 327633093 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 1.974239 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.736392 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 68428283 20.89% 20.89% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 84743637 25.87% 46.75% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 75345420 23.00% 69.75% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 40565003 12.38% 82.13% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 28664322 8.75% 90.88% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 15213545 4.64% 95.52% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 5876273 1.79% 97.32% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 6659013 2.03% 99.35% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 2137597 0.65% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 327633093 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 205009 5.12% 5.12% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 5.12% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 5.12% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.12% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.12% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.12% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 5.12% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.12% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 5.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 5.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.12% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 2904405 72.49% 77.61% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 897167 22.39% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 403920644 62.45% 62.45% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 6585 0.00% 62.45% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.45% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.45% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.45% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.45% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.45% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.45% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.45% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.45% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.45% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.45% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.45% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.45% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.45% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.45% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.45% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.45% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.45% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.45% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.45% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.45% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.45% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.45% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.45% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 62.45% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.45% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.45% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.45% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 166111461 25.68% 88.13% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 76787311 11.87% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 646826004 # Type of FU issued
system.cpu.iq.rate 1.969049 # Inst issue rate
system.cpu.iq.fu_busy_cnt 4006581 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.006194 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 1626715636 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 761421594 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 638533475 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 650832565 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 30420680 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 23951584 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 127945 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 11724 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 10400307 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 12832 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 12549 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 11029130 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 827373 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 62655 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 682042744 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 662438 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 172904405 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 80621547 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 3504 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 13090 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 6258 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 11724 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 1313555 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 1583724 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 2897279 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 642671991 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 163979527 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 4154013 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 66233 # number of nop insts executed
system.cpu.iew.exec_refs 239982954 # number of memory reference insts executed
system.cpu.iew.exec_branches 74668739 # Number of branches executed
system.cpu.iew.exec_stores 76003427 # Number of stores executed
system.cpu.iew.exec_rate 1.956404 # Inst execution rate
system.cpu.iew.wb_sent 640027985 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 638533491 # cumulative count of insts written-back
system.cpu.iew.wb_producers 420151811 # num instructions producing a value
system.cpu.iew.wb_consumers 654946950 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 1.943806 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.641505 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitCommittedInsts 570052779 # The number of committed instructions
system.cpu.commit.commitCommittedOps 602360986 # The number of committed instructions
system.cpu.commit.commitSquashedInsts 79691237 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 2931 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 2423863 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 316603964 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.902569 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.239613 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 92664555 29.27% 29.27% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 103983968 32.84% 62.11% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 43054287 13.60% 75.71% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 8920631 2.82% 78.53% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 25673085 8.11% 86.64% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 13110941 4.14% 90.78% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 7578873 2.39% 93.17% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 1154724 0.36% 93.54% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 20462900 6.46% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 316603964 # Number of insts commited each cycle
system.cpu.commit.committedInsts 570052779 # Number of instructions committed
system.cpu.commit.committedOps 602360986 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 219174061 # Number of memory references committed
system.cpu.commit.loads 148952821 # Number of loads committed
system.cpu.commit.membars 1328 # Number of memory barriers committed
system.cpu.commit.branches 70828828 # Number of branches committed
system.cpu.commit.fp_insts 16 # Number of committed floating point instructions.
system.cpu.commit.int_insts 533523547 # Number of committed integer instructions.
system.cpu.commit.function_calls 997573 # Number of function calls committed.
system.cpu.commit.bw_lim_events 20462900 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 978192675 # The number of ROB reads
system.cpu.rob.rob_writes 1375166180 # The number of ROB writes
system.cpu.timesIdled 37006 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 863493 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 570052728 # Number of Instructions Simulated
system.cpu.committedOps 602360935 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 570052728 # Number of Instructions Simulated
system.cpu.cpi 0.576256 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.576256 # CPI: Total CPI of All Threads
system.cpu.ipc 1.735338 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.735338 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 3210352058 # number of integer regfile reads
system.cpu.int_regfile_writes 664199500 # number of integer regfile writes
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
system.cpu.misc_regfile_reads 905055598 # number of misc regfile reads
system.cpu.misc_regfile_writes 3110 # number of misc regfile writes
system.cpu.icache.replacements 66 # number of replacements
system.cpu.icache.tagsinuse 704.852693 # Cycle average of tags in use
system.cpu.icache.total_refs 67494169 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 836 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 80734.651914 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 704.852693 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.344166 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.344166 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 67494169 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 67494169 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 67494169 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 67494169 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 67494169 # number of overall hits
system.cpu.icache.overall_hits::total 67494169 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 1149 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 1149 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 1149 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 1149 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 1149 # number of overall misses
system.cpu.icache.overall_misses::total 1149 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 39292000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 39292000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 39292000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 39292000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 39292000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 39292000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 67495318 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 67495318 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 67495318 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 67495318 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 67495318 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 67495318 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000017 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000017 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000017 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000017 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000017 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000017 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34196.692776 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 34196.692776 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 34196.692776 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 34196.692776 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 34196.692776 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 34196.692776 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 310 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 310 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 310 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 310 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 310 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 310 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 839 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 839 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 839 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 839 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 839 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 839 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 28616000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 28616000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 28616000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 28616000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 28616000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 28616000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000012 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000012 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000012 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000012 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000012 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000012 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34107.270560 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 34107.270560 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34107.270560 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 34107.270560 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34107.270560 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 34107.270560 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 440506 # number of replacements
system.cpu.dcache.tagsinuse 4094.673413 # Cycle average of tags in use
system.cpu.dcache.total_refs 199917627 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 444602 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 449.655258 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 87177000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 4094.673413 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.999676 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.999676 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 132064751 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 132064751 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 67849620 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 67849620 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 1690 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 1690 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 1554 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 1554 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 199914371 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 199914371 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 199914371 # number of overall hits
system.cpu.dcache.overall_hits::total 199914371 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 249324 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 249324 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 1567911 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 1567911 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 16 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 16 # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data 1817235 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 1817235 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 1817235 # number of overall misses
system.cpu.dcache.overall_misses::total 1817235 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 3293272500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 3293272500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 27061002013 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 27061002013 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 203000 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 203000 # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 30354274513 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 30354274513 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 30354274513 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 30354274513 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 132314075 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 132314075 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 69417531 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 69417531 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1706 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 1706 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 1554 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 1554 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 201731606 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 201731606 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 201731606 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 201731606 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001884 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.001884 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.022587 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.022587 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.009379 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.009379 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.009008 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.009008 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.009008 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.009008 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13208.806613 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 13208.806613 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17259.271740 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 17259.271740 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12687.500000 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12687.500000 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 16703.549355 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 16703.549355 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 16703.549355 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 16703.549355 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 9569014 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 2180 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 4389.455963 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 394908 # number of writebacks
system.cpu.dcache.writebacks::total 394908 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 51828 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 51828 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1320801 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 1320801 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 16 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 16 # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 1372629 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 1372629 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 1372629 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 1372629 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 197496 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 197496 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 247110 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 247110 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 444606 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 444606 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 444606 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 444606 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1630743000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 1630743000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2541828513 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 2541828513 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4172571513 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 4172571513 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4172571513 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 4172571513 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001493 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001493 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003560 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.003560 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002204 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.002204 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002204 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.002204 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8257.093815 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 8257.093815 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10286.222787 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10286.222787 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 9384.874502 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 9384.874502 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 9384.874502 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 9384.874502 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 73212 # number of replacements
system.cpu.l2cache.tagsinuse 17814.608666 # Cycle average of tags in use
system.cpu.l2cache.total_refs 421435 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 88732 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 4.749527 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 15925.956754 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 38.298458 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 1850.353454 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.486022 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.001169 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.056468 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.543659 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 36 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 165185 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 165221 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 394908 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 394908 # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data 2 # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total 2 # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 188795 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 188795 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst 36 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 353980 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 354016 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 36 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 353980 # number of overall hits
system.cpu.l2cache.overall_hits::total 354016 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 800 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 32306 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 33106 # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data 1 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total 1 # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 58317 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 58317 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 800 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 90623 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 91423 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 800 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 90623 # number of overall misses
system.cpu.l2cache.overall_misses::total 91423 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 27465500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1108067500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 1135533000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2001435500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 2001435500 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 27465500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 3109503000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 3136968500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 27465500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 3109503000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 3136968500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 836 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 197491 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 198327 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 394908 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 394908 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 3 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total 3 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 247112 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 247112 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 836 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 444603 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 445439 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 836 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 444603 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 445439 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.956938 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.163582 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.166926 # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.333333 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.333333 # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.235994 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.235994 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.956938 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.203829 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.205242 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.956938 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.203829 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.205242 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34331.875000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34299.124002 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 34299.915423 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34319.932438 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34319.932438 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34331.875000 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34312.514483 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 34312.683898 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34331.875000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34312.514483 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 34312.683898 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 2005000 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 332 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 6039.156627 # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks 58158 # number of writebacks
system.cpu.l2cache.writebacks::total 58158 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 9 # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total 10 # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data 9 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total 10 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data 9 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total 10 # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 799 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 32297 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 33096 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1 # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total 1 # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 58317 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 58317 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 799 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 90614 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 91413 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 799 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 90614 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 91413 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 24875000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1003961000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1028836000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 31000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 31000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1821234000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1821234000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24875000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 2825195000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 2850070000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24875000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2825195000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 2850070000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.955742 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.163537 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.166876 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.333333 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.333333 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.235994 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.235994 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.955742 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.203809 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.205220 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.955742 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.203809 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.205220 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31132.665832 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31085.271078 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31086.415277 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31000 # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31229.898657 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31229.898657 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31132.665832 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31178.349924 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31177.950620 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31132.665832 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31178.349924 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31177.950620 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

135
simulators/gem5/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/config.ini Normal file
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@ -0,0 +1,135 @@
[root]
type=Root
children=system
full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
boot_osflags=a
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
readfile=
symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.cpu]
type=AtomicSimpleCPU
children=dtb interrupts itb tracer workload
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
fastmem=false
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
phase=0
profile=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
system=system
tracer=system.cpu.tracer
width=1
workload=system.cpu.workload
dcache_port=system.membus.slave[2]
icache_port=system.membus.slave[1]
[system.cpu.dtb]
type=ArmTLB
children=walker
size=64
walker=system.cpu.dtb.walker
[system.cpu.dtb.walker]
type=ArmTableWalker
max_backoff=100000
min_backoff=0
sys=system
port=system.membus.slave[4]
[system.cpu.interrupts]
type=ArmInterrupts
[system.cpu.itb]
type=ArmTLB
children=walker
size=64
walker=system.cpu.itb.walker
[system.cpu.itb.walker]
type=ArmTableWalker
max_backoff=100000
min_backoff=0
sys=system
port=system.membus.slave[3]
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=gzip input.log 1
cwd=build/ARM/tests/opt/long/se/00.gzip/arm/linux/simple-atomic
egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/cpu2000/binaries/arm/linux/gzip
gid=100
input=cin
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=0
system=system
uid=100
[system.membus]
type=CoherentBus
block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
master=system.physmem.port[0]
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port
[system.physmem]
type=SimpleMemory
conf_table_reported=false
file=
in_addr_map=true
latency=30000
latency_var=0
null=false
range=0:134217727
zero=false
port=system.membus.master[0]

2
simulators/gem5/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/simerr Executable file
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@ -0,0 +1,2 @@
warn: Sockets disabled, not accepting gdb connections
hack: be nice to actually delete the event here

41
simulators/gem5/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/simout Executable file
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@ -0,0 +1,41 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 4 2012 12:14:06
gem5 started Jun 4 2012 17:27:49
gem5 executing on zizzer
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/00.gzip/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/00.gzip/arm/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
spec_init
Loading Input Data
Duplicating 262144 bytes
Duplicating 524288 bytes
Input data 1048576 bytes in length
Compressing Input Data, level 1
Compressed data 108074 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Compressing Input Data, level 3
Compressed data 97831 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Compressing Input Data, level 5
Compressed data 83382 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Compressing Input Data, level 7
Compressed data 76606 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Compressing Input Data, level 9
Compressed data 73189 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
Exiting @ tick 301191370000 because target called exit()

102
simulators/gem5/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/stats.txt Normal file
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@ -0,0 +1,102 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.301191 # Number of seconds simulated
sim_ticks 301191370000 # Number of ticks simulated
final_tick 301191370000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 2291609 # Simulator instruction rate (inst/s)
host_op_rate 2421488 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1210789798 # Simulator tick rate (ticks/s)
host_mem_usage 221260 # Number of bytes of host memory used
host_seconds 248.76 # Real time elapsed on the host
sim_insts 570051644 # Number of instructions simulated
sim_ops 602359851 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 2280298136 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 399862021 # Number of bytes read from this memory
system.physmem.bytes_read::total 2680160157 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 2280298136 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 2280298136 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 236359611 # Number of bytes written to this memory
system.physmem.bytes_written::total 236359611 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 570074534 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 147793179 # Number of read requests responded to by this memory
system.physmem.num_reads::total 717867713 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 69418858 # Number of write requests responded to by this memory
system.physmem.num_writes::total 69418858 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 7570927866 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 1327601189 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 8898529055 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 7570927866 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 7570927866 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 784748949 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 784748949 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 7570927866 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2112350138 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 9683278004 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 48 # Number of system calls
system.cpu.numCycles 602382741 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 570051644 # Number of instructions committed
system.cpu.committedOps 602359851 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 533522639 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses
system.cpu.num_func_calls 1993546 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 67017095 # number of instructions that are conditional controls
system.cpu.num_int_insts 533522639 # number of integer instructions
system.cpu.num_fp_insts 16 # number of float instructions
system.cpu.num_int_register_reads 2770243005 # number of times the integer registers were read
system.cpu.num_int_register_writes 614470985 # number of times the integer registers were written
system.cpu.num_fp_register_reads 16 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_mem_refs 219173607 # number of memory refs
system.cpu.num_load_insts 148952594 # Number of load instructions
system.cpu.num_store_insts 70221013 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 602382741 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
---------- End Simulation Statistics ----------

216
simulators/gem5/tests/long/se/00.gzip/ref/arm/linux/simple-timing/config.ini Normal file
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[root]
type=Root
children=system
full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
boot_osflags=a
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
readfile=
symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.cpu]
type=TimingSimpleCPU
children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
phase=0
profile=0
progress_interval=0
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=262144
subblock_size=0
system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
[system.cpu.dtb]
type=ArmTLB
children=walker
size=64
walker=system.cpu.dtb.walker
[system.cpu.dtb.walker]
type=ArmTableWalker
max_backoff=100000
min_backoff=0
sys=system
port=system.cpu.toL2Bus.slave[3]
[system.cpu.icache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=131072
subblock_size=0
system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.interrupts]
type=ArmInterrupts
[system.cpu.itb]
type=ArmTLB
children=walker
size=64
walker=system.cpu.itb.walker
[system.cpu.itb.walker]
type=ArmTableWalker
max_backoff=100000
min_backoff=0
sys=system
port=system.cpu.toL2Bus.slave[2]
[system.cpu.l2cache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=false
latency=10000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=2097152
subblock_size=0
system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
[system.cpu.toL2Bus]
type=CoherentBus
block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=gzip input.log 1
cwd=build/ARM/tests/opt/long/se/00.gzip/arm/linux/simple-timing
egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/cpu2000/binaries/arm/linux/gzip
gid=100
input=cin
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=0
system=system
uid=100
[system.membus]
type=CoherentBus
block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
master=system.physmem.port[0]
slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=SimpleMemory
conf_table_reported=false
file=
in_addr_map=true
latency=30000
latency_var=0
null=false
range=0:134217727
zero=false
port=system.membus.master[0]

2
simulators/gem5/tests/long/se/00.gzip/ref/arm/linux/simple-timing/simerr Executable file
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@ -0,0 +1,2 @@
warn: Sockets disabled, not accepting gdb connections
hack: be nice to actually delete the event here

41
simulators/gem5/tests/long/se/00.gzip/ref/arm/linux/simple-timing/simout Executable file
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gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 4 2012 12:14:06
gem5 started Jun 4 2012 17:27:51
gem5 executing on zizzer
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/00.gzip/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/00.gzip/arm/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
spec_init
Loading Input Data
Duplicating 262144 bytes
Duplicating 524288 bytes
Input data 1048576 bytes in length
Compressing Input Data, level 1
Compressed data 108074 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Compressing Input Data, level 3
Compressed data 97831 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Compressing Input Data, level 5
Compressed data 83382 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Compressing Input Data, level 7
Compressed data 76606 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Compressing Input Data, level 9
Compressed data 73189 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
Exiting @ tick 796762926000 because target called exit()

427
simulators/gem5/tests/long/se/00.gzip/ref/arm/linux/simple-timing/stats.txt Normal file
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@ -0,0 +1,427 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.796763 # Number of seconds simulated
sim_ticks 796762926000 # Number of ticks simulated
final_tick 796762926000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1154549 # Simulator instruction rate (inst/s)
host_op_rate 1219245 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1618008338 # Simulator tick rate (ticks/s)
host_mem_usage 230404 # Number of bytes of host memory used
host_seconds 492.43 # Real time elapsed on the host
sim_insts 568539343 # Number of instructions simulated
sim_ops 600398281 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 39424 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 5720064 # Number of bytes read from this memory
system.physmem.bytes_read::total 5759488 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 39424 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 39424 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 3704704 # Number of bytes written to this memory
system.physmem.bytes_written::total 3704704 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 616 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 89376 # Number of read requests responded to by this memory
system.physmem.num_reads::total 89992 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 57886 # Number of write requests responded to by this memory
system.physmem.num_writes::total 57886 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 49480 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 7179129 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 7228609 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 49480 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 49480 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 4649694 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 4649694 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 4649694 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 49480 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 7179129 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 11878304 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 48 # Number of system calls
system.cpu.numCycles 1593525852 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 568539343 # Number of instructions committed
system.cpu.committedOps 600398281 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 533522639 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses
system.cpu.num_func_calls 1993546 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 67017095 # number of instructions that are conditional controls
system.cpu.num_int_insts 533522639 # number of integer instructions
system.cpu.num_fp_insts 16 # number of float instructions
system.cpu.num_int_register_reads 3212467108 # number of times the integer registers were read
system.cpu.num_int_register_writes 614470985 # number of times the integer registers were written
system.cpu.num_fp_register_reads 16 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_mem_refs 219173607 # number of memory refs
system.cpu.num_load_insts 148952594 # Number of load instructions
system.cpu.num_store_insts 70221013 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 1593525852 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.icache.replacements 12 # number of replacements
system.cpu.icache.tagsinuse 577.728532 # Cycle average of tags in use
system.cpu.icache.total_refs 570073892 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 643 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 886584.590980 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 577.728532 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.282094 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.282094 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 570073892 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 570073892 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 570073892 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 570073892 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 570073892 # number of overall hits
system.cpu.icache.overall_hits::total 570073892 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 643 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 643 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 643 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 643 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 643 # number of overall misses
system.cpu.icache.overall_misses::total 643 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 34874000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 34874000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 34874000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 34874000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 34874000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 34874000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 570074535 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 570074535 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 570074535 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 570074535 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 570074535 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 570074535 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000001 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000001 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000001 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000001 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000001 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000001 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54236.391913 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 54236.391913 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 54236.391913 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 54236.391913 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 54236.391913 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 54236.391913 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 643 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 643 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 643 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 643 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 643 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 643 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 32945000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 32945000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 32945000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 32945000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 32945000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 32945000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000001 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000001 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000001 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51236.391913 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51236.391913 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51236.391913 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 51236.391913 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51236.391913 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 51236.391913 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 433468 # number of replacements
system.cpu.dcache.tagsinuse 4094.222434 # Cycle average of tags in use
system.cpu.dcache.total_refs 216774473 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 437564 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 495.412038 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 537031000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 4094.222434 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.999566 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.999566 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 147602036 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 147602036 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 69169783 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 69169783 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 1327 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 1327 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 1327 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 1327 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 216771819 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 216771819 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 216771819 # number of overall hits
system.cpu.dcache.overall_hits::total 216771819 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 189816 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 189816 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 247748 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 247748 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 437564 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 437564 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 437564 # number of overall misses
system.cpu.dcache.overall_misses::total 437564 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 3956274000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 3956274000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 5923414000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 5923414000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 9879688000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 9879688000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 9879688000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 9879688000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 147791852 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 147791852 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 69417531 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 69417531 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1327 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 1327 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 1327 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 1327 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 217209383 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 217209383 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 217209383 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 217209383 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001284 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.001284 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003569 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.003569 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.002014 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.002014 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.002014 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.002014 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20842.679226 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 20842.679226 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 23909.028529 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 23909.028529 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 22578.841038 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 22578.841038 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 22578.841038 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 22578.841038 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 392392 # number of writebacks
system.cpu.dcache.writebacks::total 392392 # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 189816 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 189816 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 247748 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 247748 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 437564 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 437564 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 437564 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 437564 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3386826000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 3386826000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5180170000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 5180170000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8566996000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 8566996000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8566996000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 8566996000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001284 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001284 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003569 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.003569 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002014 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.002014 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002014 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.002014 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17842.679226 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17842.679226 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 20909.028529 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 20909.028529 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19578.841038 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 19578.841038 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19578.841038 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 19578.841038 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 71804 # number of replacements
system.cpu.l2cache.tagsinuse 17904.014680 # Cycle average of tags in use
system.cpu.l2cache.total_refs 411836 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 87286 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 4.718237 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 16141.835335 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 24.672100 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 1737.507245 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.492610 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.000753 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.053025 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.546387 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 27 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 158891 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 158918 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 392392 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 392392 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 189297 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 189297 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst 27 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 348188 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 348215 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 27 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 348188 # number of overall hits
system.cpu.l2cache.overall_hits::total 348215 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 616 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 30925 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 31541 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 58451 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 58451 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 616 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 89376 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 89992 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 616 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 89376 # number of overall misses
system.cpu.l2cache.overall_misses::total 89992 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 32032000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1608100000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 1640132000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3039452000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 3039452000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 32032000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 4647552000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 4679584000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 32032000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 4647552000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 4679584000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 643 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 189816 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 190459 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 392392 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 392392 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 247748 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 247748 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 643 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 437564 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 438207 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 643 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 437564 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 438207 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.958009 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.162921 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.165605 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.235929 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.235929 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.958009 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.204258 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.205364 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.958009 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.204258 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.205364 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks 57886 # number of writebacks
system.cpu.l2cache.writebacks::total 57886 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 616 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 30925 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 31541 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 58451 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 58451 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 616 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 89376 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 89992 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 616 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 89376 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 89992 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 24640000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1237000000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1261640000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2338040000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2338040000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24640000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3575040000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 3599680000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24640000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3575040000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 3599680000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.958009 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.162921 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.165605 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.235929 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.235929 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.958009 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.204258 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.205364 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.958009 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.204258 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.205364 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

529
simulators/gem5/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/config.ini Normal file
View File

@ -0,0 +1,529 @@
[root]
type=Root
children=system
full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
boot_osflags=a
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
readfile=
symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.cpu]
type=DerivO3CPU
children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
LSQDepCheckShift=4
RASSize=16
SQEntries=32
SSITSize=1024
activity=0
backComSize=5
cachePorts=200
checker=Null
choiceCtrBits=2
choicePredictorSize=8192
clock=500
commitToDecodeDelay=1
commitToFetchDelay=1
commitToIEWDelay=1
commitToRenameDelay=1
commitWidth=8
cpu_id=0
decodeToFetchDelay=1
decodeToRenameDelay=1
decodeWidth=8
defer_registration=false
dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
fetchToDecodeDelay=1
fetchTrapLatency=1
fetchWidth=8
forwardComSize=5
fuPool=system.cpu.fuPool
function_trace=false
function_trace_start=0
globalCtrBits=2
globalHistoryBits=13
globalPredictorSize=8192
iewToCommitDelay=1
iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
instShiftAmt=2
interrupts=system.cpu.interrupts
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
localCtrBits=2
localHistoryBits=11
localHistoryTableSize=2048
localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
needsTSO=false
numIQEntries=64
numPhysFloatRegs=256
numPhysIntRegs=256
numROBEntries=192
numRobs=1
numThreads=1
phase=0
predType=tournament
profile=0
progress_interval=0
renameToDecodeDelay=1
renameToFetchDelay=1
renameToIEWDelay=2
renameToROBDelay=1
renameWidth=8
smtCommitPolicy=RoundRobin
smtFetchPolicy=SingleThread
smtIQPolicy=Partitioned
smtIQThreshold=100
smtLSQPolicy=Partitioned
smtLSQThreshold=100
smtNumFetchingThreads=1
smtROBPolicy=Partitioned
smtROBThreshold=100
squashWidth=8
store_set_clear_period=250000
system=system
tracer=system.cpu.tracer
trapLatency=13
wbDepth=1
wbWidth=8
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=262144
subblock_size=0
system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
[system.cpu.dtb]
type=SparcTLB
size=64
[system.cpu.fuPool]
type=FUPool
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
[system.cpu.fuPool.FUList0]
type=FUDesc
children=opList
count=6
opList=system.cpu.fuPool.FUList0.opList
[system.cpu.fuPool.FUList0.opList]
type=OpDesc
issueLat=1
opClass=IntAlu
opLat=1
[system.cpu.fuPool.FUList1]
type=FUDesc
children=opList0 opList1
count=2
opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
[system.cpu.fuPool.FUList1.opList0]
type=OpDesc
issueLat=1
opClass=IntMult
opLat=3
[system.cpu.fuPool.FUList1.opList1]
type=OpDesc
issueLat=19
opClass=IntDiv
opLat=20
[system.cpu.fuPool.FUList2]
type=FUDesc
children=opList0 opList1 opList2
count=4
opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
[system.cpu.fuPool.FUList2.opList0]
type=OpDesc
issueLat=1
opClass=FloatAdd
opLat=2
[system.cpu.fuPool.FUList2.opList1]
type=OpDesc
issueLat=1
opClass=FloatCmp
opLat=2
[system.cpu.fuPool.FUList2.opList2]
type=OpDesc
issueLat=1
opClass=FloatCvt
opLat=2
[system.cpu.fuPool.FUList3]
type=FUDesc
children=opList0 opList1 opList2
count=2
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
[system.cpu.fuPool.FUList3.opList0]
type=OpDesc
issueLat=1
opClass=FloatMult
opLat=4
[system.cpu.fuPool.FUList3.opList1]
type=OpDesc
issueLat=12
opClass=FloatDiv
opLat=12
[system.cpu.fuPool.FUList3.opList2]
type=OpDesc
issueLat=24
opClass=FloatSqrt
opLat=24
[system.cpu.fuPool.FUList4]
type=FUDesc
children=opList
count=0
opList=system.cpu.fuPool.FUList4.opList
[system.cpu.fuPool.FUList4.opList]
type=OpDesc
issueLat=1
opClass=MemRead
opLat=1
[system.cpu.fuPool.FUList5]
type=FUDesc
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
count=4
opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
[system.cpu.fuPool.FUList5.opList00]
type=OpDesc
issueLat=1
opClass=SimdAdd
opLat=1
[system.cpu.fuPool.FUList5.opList01]
type=OpDesc
issueLat=1
opClass=SimdAddAcc
opLat=1
[system.cpu.fuPool.FUList5.opList02]
type=OpDesc
issueLat=1
opClass=SimdAlu
opLat=1
[system.cpu.fuPool.FUList5.opList03]
type=OpDesc
issueLat=1
opClass=SimdCmp
opLat=1
[system.cpu.fuPool.FUList5.opList04]
type=OpDesc
issueLat=1
opClass=SimdCvt
opLat=1
[system.cpu.fuPool.FUList5.opList05]
type=OpDesc
issueLat=1
opClass=SimdMisc
opLat=1
[system.cpu.fuPool.FUList5.opList06]
type=OpDesc
issueLat=1
opClass=SimdMult
opLat=1
[system.cpu.fuPool.FUList5.opList07]
type=OpDesc
issueLat=1
opClass=SimdMultAcc
opLat=1
[system.cpu.fuPool.FUList5.opList08]
type=OpDesc
issueLat=1
opClass=SimdShift
opLat=1
[system.cpu.fuPool.FUList5.opList09]
type=OpDesc
issueLat=1
opClass=SimdShiftAcc
opLat=1
[system.cpu.fuPool.FUList5.opList10]
type=OpDesc
issueLat=1
opClass=SimdSqrt
opLat=1
[system.cpu.fuPool.FUList5.opList11]
type=OpDesc
issueLat=1
opClass=SimdFloatAdd
opLat=1
[system.cpu.fuPool.FUList5.opList12]
type=OpDesc
issueLat=1
opClass=SimdFloatAlu
opLat=1
[system.cpu.fuPool.FUList5.opList13]
type=OpDesc
issueLat=1
opClass=SimdFloatCmp
opLat=1
[system.cpu.fuPool.FUList5.opList14]
type=OpDesc
issueLat=1
opClass=SimdFloatCvt
opLat=1
[system.cpu.fuPool.FUList5.opList15]
type=OpDesc
issueLat=1
opClass=SimdFloatDiv
opLat=1
[system.cpu.fuPool.FUList5.opList16]
type=OpDesc
issueLat=1
opClass=SimdFloatMisc
opLat=1
[system.cpu.fuPool.FUList5.opList17]
type=OpDesc
issueLat=1
opClass=SimdFloatMult
opLat=1
[system.cpu.fuPool.FUList5.opList18]
type=OpDesc
issueLat=1
opClass=SimdFloatMultAcc
opLat=1
[system.cpu.fuPool.FUList5.opList19]
type=OpDesc
issueLat=1
opClass=SimdFloatSqrt
opLat=1
[system.cpu.fuPool.FUList6]
type=FUDesc
children=opList
count=0
opList=system.cpu.fuPool.FUList6.opList
[system.cpu.fuPool.FUList6.opList]
type=OpDesc
issueLat=1
opClass=MemWrite
opLat=1
[system.cpu.fuPool.FUList7]
type=FUDesc
children=opList0 opList1
count=4
opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
[system.cpu.fuPool.FUList7.opList0]
type=OpDesc
issueLat=1
opClass=MemRead
opLat=1
[system.cpu.fuPool.FUList7.opList1]
type=OpDesc
issueLat=1
opClass=MemWrite
opLat=1
[system.cpu.fuPool.FUList8]
type=FUDesc
children=opList
count=1
opList=system.cpu.fuPool.FUList8.opList
[system.cpu.fuPool.FUList8.opList]
type=OpDesc
issueLat=3
opClass=IprAccess
opLat=3
[system.cpu.icache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=131072
subblock_size=0
system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.interrupts]
type=SparcInterrupts
[system.cpu.itb]
type=SparcTLB
size=64
[system.cpu.l2cache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=false
latency=1000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=2097152
subblock_size=0
system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
[system.cpu.toL2Bus]
type=CoherentBus
block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=gzip input.log 1
cwd=build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/o3-timing
egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/cpu2000/binaries/sparc/linux/gzip
gid=100
input=cin
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=0
system=system
uid=100
[system.membus]
type=CoherentBus
block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
master=system.physmem.port[0]
slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=SimpleMemory
conf_table_reported=false
file=
in_addr_map=true
latency=30000
latency_var=0
null=false
range=0:134217727
zero=false
port=system.membus.master[0]

2
simulators/gem5/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simerr Executable file
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@ -0,0 +1,2 @@
warn: Sockets disabled, not accepting gdb connections
hack: be nice to actually delete the event here

41
simulators/gem5/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout Executable file
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@ -0,0 +1,41 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 4 2012 12:01:47
gem5 started Jun 4 2012 14:45:35
gem5 executing on zizzer
command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
spec_init
Loading Input Data
Duplicating 262144 bytes
Duplicating 524288 bytes
Input data 1048576 bytes in length
Compressing Input Data, level 1
Compressed data 108074 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Compressing Input Data, level 3
Compressed data 97831 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Compressing Input Data, level 5
Compressed data 83382 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Compressing Input Data, level 7
Compressed data 76606 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Compressing Input Data, level 9
Compressed data 73189 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
Exiting @ tick 388554296500 because target called exit()

657
simulators/gem5/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt Normal file
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@ -0,0 +1,657 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.388554 # Number of seconds simulated
sim_ticks 388554296500 # Number of ticks simulated
final_tick 388554296500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 160259 # Simulator instruction rate (inst/s)
host_op_rate 160764 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 44440455 # Simulator tick rate (ticks/s)
host_mem_usage 224388 # Number of bytes of host memory used
host_seconds 8743.26 # Real time elapsed on the host
sim_insts 1401188958 # Number of instructions simulated
sim_ops 1405604152 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 85056 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 5902400 # Number of bytes read from this memory
system.physmem.bytes_read::total 5987456 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 85056 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 85056 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 3788160 # Number of bytes written to this memory
system.physmem.bytes_written::total 3788160 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 1329 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 92225 # Number of read requests responded to by this memory
system.physmem.num_reads::total 93554 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 59190 # Number of write requests responded to by this memory
system.physmem.num_writes::total 59190 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 218904 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 15190670 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 15409574 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 218904 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 218904 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 9749371 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 9749371 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 9749371 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 218904 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 15190670 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 25158945 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 49 # Number of system calls
system.cpu.numCycles 777108594 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.BPredUnit.lookups 98192290 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 88412741 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 3784661 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 66025458 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 65664289 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 1392 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 307 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 165888791 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 1648818264 # Number of instructions fetch has processed
system.cpu.fetch.Branches 98192290 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 65665681 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 330417282 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 21685615 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 262756820 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 127 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 2717 # Number of stall cycles due to pending traps
system.cpu.fetch.CacheLines 162823525 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 752138 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 776762747 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.128564 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.147845 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 446345465 57.46% 57.46% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 74375625 9.58% 67.04% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 37980087 4.89% 71.93% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 9083330 1.17% 73.10% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 28159964 3.63% 76.72% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 18826619 2.42% 79.15% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 11515688 1.48% 80.63% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 3871202 0.50% 81.13% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 146604767 18.87% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 776762747 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.126356 # Number of branch fetches per cycle
system.cpu.fetch.rate 2.121735 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 217443439 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 213446803 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 285373546 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 42801949 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 17697010 # Number of cycles decode is squashing
system.cpu.decode.DecodedInsts 1642584513 # Number of instructions handled by decode
system.cpu.rename.SquashCycles 17697010 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 241484414 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 36505924 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 52170824 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 303041095 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 125863480 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 1631270043 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 22 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 30873302 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 72930971 # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents 3136079 # Number of times there has been no free registers
system.cpu.rename.RenamedOperands 1360952247 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 2755876290 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 2721902713 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 33973577 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 1244770452 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 116181795 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 2680713 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 2696169 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 271856221 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 438705092 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 180250261 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 255265663 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 83296081 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 1517040384 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 2636529 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 1460865188 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 67073 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 113729678 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 136677669 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 392858 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 776762747 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 1.880710 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.430803 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 147116911 18.94% 18.94% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 184456460 23.75% 42.69% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 210881862 27.15% 69.84% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 131212379 16.89% 86.73% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 70768732 9.11% 95.84% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 20345025 2.62% 98.46% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 7834706 1.01% 99.47% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 3973798 0.51% 99.98% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 172874 0.02% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 776762747 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 106719 6.05% 6.05% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 6.05% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 6.05% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 167382 9.50% 15.55% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 15.55% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 15.55% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 15.55% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 15.55% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 15.55% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 15.55% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 15.55% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 15.55% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 15.55% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 15.55% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 15.55% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 15.55% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 15.55% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 15.55% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 15.55% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 15.55% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 15.55% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 15.55% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 15.55% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 15.55% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 15.55% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 15.55% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 15.55% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 15.55% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 15.55% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 1159607 65.79% 81.34% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 328958 18.66% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 867175983 59.36% 59.36% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 0 0.00% 59.36% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 59.36% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 2649316 0.18% 59.54% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.54% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.54% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.54% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.54% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.54% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.54% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.54% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.54% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.54% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.54% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.54% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.54% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.54% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.54% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.54% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.54% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.54% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.54% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.54% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.54% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.54% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.54% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.54% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.54% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.54% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 419771639 28.73% 88.28% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 171268250 11.72% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 1460865188 # Type of FU issued
system.cpu.iq.rate 1.879873 # Inst issue rate
system.cpu.iq.fu_busy_cnt 1762666 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.001207 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 3682454836 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 1624473314 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 1444449939 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 17868026 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 9170759 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 8547404 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 1453439561 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 9188293 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 215395742 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 36192248 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 54154 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 246172 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 13402119 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 3683 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 46778 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 17697010 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 2543877 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 131664 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 1613864484 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 4125995 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 438705092 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 180250261 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 2550339 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 45235 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 9141 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 246172 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 2357197 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 1561193 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 3918390 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 1455317466 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 417050361 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 5547722 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 94187571 # number of nop insts executed
system.cpu.iew.exec_refs 587627055 # number of memory reference insts executed
system.cpu.iew.exec_branches 89112581 # Number of branches executed
system.cpu.iew.exec_stores 170576694 # Number of stores executed
system.cpu.iew.exec_rate 1.872734 # Inst execution rate
system.cpu.iew.wb_sent 1453915806 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 1452997343 # cumulative count of insts written-back
system.cpu.iew.wb_producers 1154378236 # num instructions producing a value
system.cpu.iew.wb_consumers 1205398776 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 1.869748 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.957673 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitCommittedInsts 1485108101 # The number of committed instructions
system.cpu.commit.commitCommittedOps 1489523295 # The number of committed instructions
system.cpu.commit.commitSquashedInsts 124237250 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 2243671 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 3784661 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 759066348 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.962310 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.504596 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 240497837 31.68% 31.68% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 276436046 36.42% 68.10% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 43137006 5.68% 73.78% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 54981228 7.24% 81.03% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 19702278 2.60% 83.62% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 13356697 1.76% 85.38% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 30450827 4.01% 89.39% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 10463438 1.38% 90.77% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 70040991 9.23% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 759066348 # Number of insts commited each cycle
system.cpu.commit.committedInsts 1485108101 # Number of instructions committed
system.cpu.commit.committedOps 1489523295 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 569360986 # Number of memory references committed
system.cpu.commit.loads 402512844 # Number of loads committed
system.cpu.commit.membars 51356 # Number of memory barriers committed
system.cpu.commit.branches 86248929 # Number of branches committed
system.cpu.commit.fp_insts 8452036 # Number of committed floating point instructions.
system.cpu.commit.int_insts 1319476388 # Number of committed integer instructions.
system.cpu.commit.function_calls 1206914 # Number of function calls committed.
system.cpu.commit.bw_lim_events 70040991 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 2302721032 # The number of ROB reads
system.cpu.rob.rob_writes 3245242057 # The number of ROB writes
system.cpu.timesIdled 11126 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 345847 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 1401188958 # Number of Instructions Simulated
system.cpu.committedOps 1405604152 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 1401188958 # Number of Instructions Simulated
system.cpu.cpi 0.554607 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.554607 # CPI: Total CPI of All Threads
system.cpu.ipc 1.803080 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.803080 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 1980619731 # number of integer regfile reads
system.cpu.int_regfile_writes 1276281052 # number of integer regfile writes
system.cpu.fp_regfile_reads 16978878 # number of floating regfile reads
system.cpu.fp_regfile_writes 10499994 # number of floating regfile writes
system.cpu.misc_regfile_reads 593300909 # number of misc regfile reads
system.cpu.misc_regfile_writes 2190883 # number of misc regfile writes
system.cpu.icache.replacements 200 # number of replacements
system.cpu.icache.tagsinuse 1048.828471 # Cycle average of tags in use
system.cpu.icache.total_refs 162821549 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 1351 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 120519.281273 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 1048.828471 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.512123 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.512123 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 162821549 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 162821549 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 162821549 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 162821549 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 162821549 # number of overall hits
system.cpu.icache.overall_hits::total 162821549 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 1976 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 1976 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 1976 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 1976 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 1976 # number of overall misses
system.cpu.icache.overall_misses::total 1976 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 67232500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 67232500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 67232500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 67232500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 67232500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 67232500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 162823525 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 162823525 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 162823525 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 162823525 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 162823525 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 162823525 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000012 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000012 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000012 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000012 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000012 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000012 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34024.544534 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 34024.544534 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 34024.544534 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 34024.544534 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 34024.544534 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 34024.544534 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 624 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 624 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 624 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 624 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 624 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 624 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1352 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 1352 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 1352 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 1352 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 1352 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 1352 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 47023000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 47023000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 47023000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 47023000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 47023000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 47023000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000008 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000008 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000008 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000008 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000008 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000008 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34780.325444 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 34780.325444 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34780.325444 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 34780.325444 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34780.325444 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 34780.325444 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 458031 # number of replacements
system.cpu.dcache.tagsinuse 4095.115790 # Cycle average of tags in use
system.cpu.dcache.total_refs 365778673 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 462127 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 791.511150 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 131565000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 4095.115790 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.999784 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.999784 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 200803152 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 200803152 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 164974202 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 164974202 # number of WriteReq hits
system.cpu.dcache.SwapReq_hits::cpu.data 1319 # number of SwapReq hits
system.cpu.dcache.SwapReq_hits::total 1319 # number of SwapReq hits
system.cpu.dcache.demand_hits::cpu.data 365777354 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 365777354 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 365777354 # number of overall hits
system.cpu.dcache.overall_hits::total 365777354 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 803342 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 803342 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 1872614 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 1872614 # number of WriteReq misses
system.cpu.dcache.SwapReq_misses::cpu.data 7 # number of SwapReq misses
system.cpu.dcache.SwapReq_misses::total 7 # number of SwapReq misses
system.cpu.dcache.demand_misses::cpu.data 2675956 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 2675956 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 2675956 # number of overall misses
system.cpu.dcache.overall_misses::total 2675956 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 11885207000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 11885207000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 29671016952 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 29671016952 # number of WriteReq miss cycles
system.cpu.dcache.SwapReq_miss_latency::cpu.data 267000 # number of SwapReq miss cycles
system.cpu.dcache.SwapReq_miss_latency::total 267000 # number of SwapReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 41556223952 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 41556223952 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 41556223952 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 41556223952 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 201606494 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 201606494 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 166846816 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 166846816 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SwapReq_accesses::cpu.data 1326 # number of SwapReq accesses(hits+misses)
system.cpu.dcache.SwapReq_accesses::total 1326 # number of SwapReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 368453310 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 368453310 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 368453310 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 368453310 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003985 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.003985 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.011224 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.011224 # miss rate for WriteReq accesses
system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.005279 # miss rate for SwapReq accesses
system.cpu.dcache.SwapReq_miss_rate::total 0.005279 # miss rate for SwapReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.007263 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.007263 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.007263 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.007263 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14794.703875 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 14794.703875 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 15844.705290 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 15844.705290 # average WriteReq miss latency
system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 38142.857143 # average SwapReq miss latency
system.cpu.dcache.SwapReq_avg_miss_latency::total 38142.857143 # average SwapReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 15529.487014 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 15529.487014 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 15529.487014 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 15529.487014 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 15500 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 7 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 2214.285714 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 413195 # number of writebacks
system.cpu.dcache.writebacks::total 413195 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 603294 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 603294 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1610542 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 1610542 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 2213836 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 2213836 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 2213836 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 2213836 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 200048 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 200048 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 262072 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 262072 # number of WriteReq MSHR misses
system.cpu.dcache.SwapReq_mshr_misses::cpu.data 7 # number of SwapReq MSHR misses
system.cpu.dcache.SwapReq_mshr_misses::total 7 # number of SwapReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 462120 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 462120 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 462120 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 462120 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1554226000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 1554226000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3602715222 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3602715222 # number of WriteReq MSHR miss cycles
system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 246000 # number of SwapReq MSHR miss cycles
system.cpu.dcache.SwapReq_mshr_miss_latency::total 246000 # number of SwapReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5156941222 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 5156941222 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5156941222 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 5156941222 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000992 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000992 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001571 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.001571 # mshr miss rate for WriteReq accesses
system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.005279 # mshr miss rate for SwapReq accesses
system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.005279 # mshr miss rate for SwapReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001254 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.001254 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001254 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.001254 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7769.265376 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 7769.265376 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 13747.043644 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 13747.043644 # average WriteReq mshr miss latency
system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 35142.857143 # average SwapReq mshr miss latency
system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 35142.857143 # average SwapReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11159.311915 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 11159.311915 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11159.311915 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 11159.311915 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 75325 # number of replacements
system.cpu.l2cache.tagsinuse 17833.274372 # Cycle average of tags in use
system.cpu.l2cache.total_refs 440162 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 90846 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 4.845145 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 15764.439855 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 99.157433 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 1969.677084 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.481093 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.003026 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.060110 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.544228 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 23 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 167881 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 167904 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 413195 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 413195 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 202021 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 202021 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst 23 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 369902 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 369925 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 23 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 369902 # number of overall hits
system.cpu.l2cache.overall_hits::total 369925 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 1329 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 32167 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 33496 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 60058 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 60058 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 1329 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 92225 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 93554 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 1329 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 92225 # number of overall misses
system.cpu.l2cache.overall_misses::total 93554 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 45502500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1094618000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 1140120500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2066673500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 2066673500 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 45502500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 3161291500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 3206794000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 45502500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 3161291500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 3206794000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 1352 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 200048 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 201400 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 413195 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 413195 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 262079 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 262079 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 1352 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 462127 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 463479 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 1352 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 462127 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 463479 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.982988 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.160796 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.166316 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.229160 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.229160 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.982988 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.199566 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.201852 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.982988 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.199566 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.201852 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34238.148984 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34029.222495 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 34037.511942 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34411.294082 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34411.294082 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34238.148984 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34278.031987 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 34277.465421 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34238.148984 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34278.031987 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 34277.465421 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks 59190 # number of writebacks
system.cpu.l2cache.writebacks::total 59190 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1329 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 32167 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 33496 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 60058 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 60058 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 1329 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 92225 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 93554 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 1329 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 92225 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 93554 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 41203500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 997353500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1038557000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1880936000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1880936000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 41203500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 2878289500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 2919493000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 41203500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2878289500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 2919493000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.982988 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.160796 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.166316 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.229160 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.229160 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.982988 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.199566 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.201852 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.982988 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.199566 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.201852 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31003.386005 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31005.486990 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31005.403630 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31318.658630 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31318.658630 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31003.386005 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31209.428029 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31206.501058 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31003.386005 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31209.428029 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31206.501058 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

117
simulators/gem5/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/config.ini Normal file
View File

@ -0,0 +1,117 @@
[root]
type=Root
children=system
full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
boot_osflags=a
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
readfile=
symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.cpu]
type=AtomicSimpleCPU
children=dtb interrupts itb tracer workload
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
fastmem=false
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
phase=0
profile=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
system=system
tracer=system.cpu.tracer
width=1
workload=system.cpu.workload
dcache_port=system.membus.slave[2]
icache_port=system.membus.slave[1]
[system.cpu.dtb]
type=SparcTLB
size=64
[system.cpu.interrupts]
type=SparcInterrupts
[system.cpu.itb]
type=SparcTLB
size=64
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=gzip input.log 1
cwd=build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/simple-atomic
egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/cpu2000/binaries/sparc/linux/gzip
gid=100
input=cin
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=0
system=system
uid=100
[system.membus]
type=CoherentBus
block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
master=system.physmem.port[0]
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
[system.physmem]
type=SimpleMemory
conf_table_reported=false
file=
in_addr_map=true
latency=30000
latency_var=0
null=false
range=0:134217727
zero=false
port=system.membus.master[0]

3
simulators/gem5/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/simerr Executable file
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@ -0,0 +1,3 @@
warn: CoherentBus system.membus has no snooping ports attached!
warn: Sockets disabled, not accepting gdb connections
hack: be nice to actually delete the event here

41
simulators/gem5/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/simout Executable file
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gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 4 2012 12:01:47
gem5 started Jun 4 2012 14:45:41
gem5 executing on zizzer
command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
spec_init
Loading Input Data
Duplicating 262144 bytes
Duplicating 524288 bytes
Input data 1048576 bytes in length
Compressing Input Data, level 1
Compressed data 108074 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Compressing Input Data, level 3
Compressed data 97831 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Compressing Input Data, level 5
Compressed data 83382 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Compressing Input Data, level 7
Compressed data 76606 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Compressing Input Data, level 9
Compressed data 73189 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
Exiting @ tick 744764119000 because target called exit()

62
simulators/gem5/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/stats.txt Normal file
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---------- Begin Simulation Statistics ----------
sim_seconds 0.744764 # Number of seconds simulated
sim_ticks 744764119000 # Number of ticks simulated
final_tick 744764119000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 3186892 # Simulator instruction rate (inst/s)
host_op_rate 3196366 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1598188492 # Simulator tick rate (ticks/s)
host_mem_usage 214172 # Number of bytes of host memory used
host_seconds 466.01 # Real time elapsed on the host
sim_insts 1485108101 # Number of instructions simulated
sim_ops 1489523295 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 5940452044 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 1385817593 # Number of bytes read from this memory
system.physmem.bytes_read::total 7326269637 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 5940452044 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 5940452044 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 614672063 # Number of bytes written to this memory
system.physmem.bytes_written::total 614672063 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 1485113011 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 402512844 # Number of read requests responded to by this memory
system.physmem.num_reads::total 1887625855 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 166846816 # Number of write requests responded to by this memory
system.physmem.num_writes::total 166846816 # Number of write requests responded to by this memory
system.physmem.num_other::cpu.data 1326 # Number of other requests responded to by this memory
system.physmem.num_other::total 1326 # Number of other requests responded to by this memory
system.physmem.bw_read::cpu.inst 7976286575 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 1860746990 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 9837033566 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 7976286575 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 7976286575 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 825324485 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 825324485 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 7976286575 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2686071475 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 10662358051 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 49 # Number of system calls
system.cpu.numCycles 1489528239 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 1485108101 # Number of instructions committed
system.cpu.committedOps 1489523295 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 1319481298 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 8454127 # Number of float alu accesses
system.cpu.num_func_calls 1207835 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 78161763 # number of instructions that are conditional controls
system.cpu.num_int_insts 1319481298 # number of integer instructions
system.cpu.num_fp_insts 8454127 # number of float instructions
system.cpu.num_int_register_reads 2499743582 # number of times the integer registers were read
system.cpu.num_int_register_writes 1234343158 # number of times the integer registers were written
system.cpu.num_fp_register_reads 16769332 # number of times the floating registers were read
system.cpu.num_fp_register_writes 10359244 # number of times the floating registers were written
system.cpu.num_mem_refs 569365767 # number of memory refs
system.cpu.num_load_insts 402515346 # Number of load instructions
system.cpu.num_store_insts 166850421 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 1489528239 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
---------- End Simulation Statistics ----------

198
simulators/gem5/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/config.ini Normal file
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@ -0,0 +1,198 @@
[root]
type=Root
children=system
full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
boot_osflags=a
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
readfile=
symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.cpu]
type=TimingSimpleCPU
children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
phase=0
profile=0
progress_interval=0
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=262144
subblock_size=0
system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
[system.cpu.dtb]
type=SparcTLB
size=64
[system.cpu.icache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=131072
subblock_size=0
system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.interrupts]
type=SparcInterrupts
[system.cpu.itb]
type=SparcTLB
size=64
[system.cpu.l2cache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=false
latency=10000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=2097152
subblock_size=0
system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
[system.cpu.toL2Bus]
type=CoherentBus
block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=gzip input.log 1
cwd=build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/simple-timing
egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/cpu2000/binaries/sparc/linux/gzip
gid=100
input=cin
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=0
system=system
uid=100
[system.membus]
type=CoherentBus
block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
master=system.physmem.port[0]
slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=SimpleMemory
conf_table_reported=false
file=
in_addr_map=true
latency=30000
latency_var=0
null=false
range=0:134217727
zero=false
port=system.membus.master[0]

2
simulators/gem5/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/simerr Executable file
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@ -0,0 +1,2 @@
warn: Sockets disabled, not accepting gdb connections
hack: be nice to actually delete the event here

41
simulators/gem5/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/simout Executable file
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@ -0,0 +1,41 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 4 2012 12:01:47
gem5 started Jun 4 2012 14:45:45
gem5 executing on zizzer
command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
spec_init
Loading Input Data
Duplicating 262144 bytes
Duplicating 524288 bytes
Input data 1048576 bytes in length
Compressing Input Data, level 1
Compressed data 108074 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Compressing Input Data, level 3
Compressed data 97831 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Compressing Input Data, level 5
Compressed data 83382 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Compressing Input Data, level 7
Compressed data 76606 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Compressing Input Data, level 9
Compressed data 73189 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
Exiting @ tick 2064258667000 because target called exit()

397
simulators/gem5/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/stats.txt Normal file
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@ -0,0 +1,397 @@
---------- Begin Simulation Statistics ----------
sim_seconds 2.064259 # Number of seconds simulated
sim_ticks 2064258667000 # Number of ticks simulated
final_tick 2064258667000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1371910 # Simulator instruction rate (inst/s)
host_op_rate 1375988 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1906915769 # Simulator tick rate (ticks/s)
host_mem_usage 223048 # Number of bytes of host memory used
host_seconds 1082.51 # Real time elapsed on the host
sim_insts 1485108101 # Number of instructions simulated
sim_ops 1489523295 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 70592 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 5839360 # Number of bytes read from this memory
system.physmem.bytes_read::total 5909952 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 70592 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 70592 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 3778240 # Number of bytes written to this memory
system.physmem.bytes_written::total 3778240 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 1103 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 91240 # Number of read requests responded to by this memory
system.physmem.num_reads::total 92343 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 59035 # Number of write requests responded to by this memory
system.physmem.num_writes::total 59035 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 34197 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 2828793 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 2862990 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 34197 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 34197 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 1830313 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 1830313 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 1830313 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 34197 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2828793 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 4693303 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 49 # Number of system calls
system.cpu.numCycles 4128517334 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 1485108101 # Number of instructions committed
system.cpu.committedOps 1489523295 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 1319481298 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 8454127 # Number of float alu accesses
system.cpu.num_func_calls 1207835 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 78161763 # number of instructions that are conditional controls
system.cpu.num_int_insts 1319481298 # number of integer instructions
system.cpu.num_fp_insts 8454127 # number of float instructions
system.cpu.num_int_register_reads 2499743582 # number of times the integer registers were read
system.cpu.num_int_register_writes 1234343157 # number of times the integer registers were written
system.cpu.num_fp_register_reads 16769332 # number of times the floating registers were read
system.cpu.num_fp_register_writes 10359244 # number of times the floating registers were written
system.cpu.num_mem_refs 569365767 # number of memory refs
system.cpu.num_load_insts 402515346 # Number of load instructions
system.cpu.num_store_insts 166850421 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 4128517334 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.icache.replacements 118 # number of replacements
system.cpu.icache.tagsinuse 906.450625 # Cycle average of tags in use
system.cpu.icache.total_refs 1485111905 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 1107 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 1341564.503162 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 906.450625 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.442603 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.442603 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 1485111905 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 1485111905 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 1485111905 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 1485111905 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 1485111905 # number of overall hits
system.cpu.icache.overall_hits::total 1485111905 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 1107 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 1107 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 1107 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 1107 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 1107 # number of overall misses
system.cpu.icache.overall_misses::total 1107 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 61824000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 61824000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 61824000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 61824000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 61824000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 61824000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 1485113012 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 1485113012 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 1485113012 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 1485113012 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 1485113012 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 1485113012 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000001 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000001 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000001 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000001 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000001 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000001 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55848.238482 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 55848.238482 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 55848.238482 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 55848.238482 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 55848.238482 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 55848.238482 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1107 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 1107 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 1107 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 1107 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 1107 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 1107 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 58503000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 58503000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 58503000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 58503000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 58503000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 58503000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000001 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000001 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000001 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52848.238482 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52848.238482 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52848.238482 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 52848.238482 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52848.238482 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 52848.238482 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 449125 # number of replacements
system.cpu.dcache.tagsinuse 4095.226955 # Cycle average of tags in use
system.cpu.dcache.total_refs 568907765 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 453221 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 1255.254644 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 566994000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 4095.226955 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.999811 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.999811 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 402319358 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 402319358 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 166587088 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 166587088 # number of WriteReq hits
system.cpu.dcache.SwapReq_hits::cpu.data 1319 # number of SwapReq hits
system.cpu.dcache.SwapReq_hits::total 1319 # number of SwapReq hits
system.cpu.dcache.demand_hits::cpu.data 568906446 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 568906446 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 568906446 # number of overall hits
system.cpu.dcache.overall_hits::total 568906446 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 193486 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 193486 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 259728 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 259728 # number of WriteReq misses
system.cpu.dcache.SwapReq_misses::cpu.data 7 # number of SwapReq misses
system.cpu.dcache.SwapReq_misses::total 7 # number of SwapReq misses
system.cpu.dcache.demand_misses::cpu.data 453214 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 453214 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 453214 # number of overall misses
system.cpu.dcache.overall_misses::total 453214 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 4019834000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 4019834000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 6156948000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 6156948000 # number of WriteReq miss cycles
system.cpu.dcache.SwapReq_miss_latency::cpu.data 392000 # number of SwapReq miss cycles
system.cpu.dcache.SwapReq_miss_latency::total 392000 # number of SwapReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 10176782000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 10176782000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 10176782000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 10176782000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 402512844 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 402512844 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 166846816 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 166846816 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SwapReq_accesses::cpu.data 1326 # number of SwapReq accesses(hits+misses)
system.cpu.dcache.SwapReq_accesses::total 1326 # number of SwapReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 569359660 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 569359660 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 569359660 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 569359660 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000481 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.000481 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001557 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.001557 # miss rate for WriteReq accesses
system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.005279 # miss rate for SwapReq accesses
system.cpu.dcache.SwapReq_miss_rate::total 0.005279 # miss rate for SwapReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.000796 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.000796 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.000796 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.000796 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20775.839079 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 20775.839079 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 23705.368693 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 23705.368693 # average WriteReq miss latency
system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 56000 # average SwapReq miss latency
system.cpu.dcache.SwapReq_avg_miss_latency::total 56000 # average SwapReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 22454.694692 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 22454.694692 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 22454.694692 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 22454.694692 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 407009 # number of writebacks
system.cpu.dcache.writebacks::total 407009 # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 193486 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 193486 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 259728 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 259728 # number of WriteReq MSHR misses
system.cpu.dcache.SwapReq_mshr_misses::cpu.data 7 # number of SwapReq MSHR misses
system.cpu.dcache.SwapReq_mshr_misses::total 7 # number of SwapReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 453214 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 453214 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 453214 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 453214 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3439376000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 3439376000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5377764000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 5377764000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 371000 # number of SwapReq MSHR miss cycles
system.cpu.dcache.SwapReq_mshr_miss_latency::total 371000 # number of SwapReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8817140000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 8817140000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8817140000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 8817140000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000481 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000481 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001557 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.001557 # mshr miss rate for WriteReq accesses
system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.005279 # mshr miss rate for SwapReq accesses
system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.005279 # mshr miss rate for SwapReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000796 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.000796 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000796 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.000796 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17775.839079 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17775.839079 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 20705.368693 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 20705.368693 # average WriteReq mshr miss latency
system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 53000 # average SwapReq mshr miss latency
system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 53000 # average SwapReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19454.694692 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 19454.694692 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19454.694692 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 19454.694692 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 74112 # number of replacements
system.cpu.l2cache.tagsinuse 17723.305524 # Cycle average of tags in use
system.cpu.l2cache.total_refs 427085 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 89611 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 4.765989 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 15849.385934 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 72.801131 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 1801.118460 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.483685 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.002222 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.054966 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.540872 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 4 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 162271 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 162275 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 407009 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 407009 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 199710 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 199710 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst 4 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 361981 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 361985 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 4 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 361981 # number of overall hits
system.cpu.l2cache.overall_hits::total 361985 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 1103 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 31215 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 32318 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 60025 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 60025 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 1103 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 91240 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 92343 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 1103 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 91240 # number of overall misses
system.cpu.l2cache.overall_misses::total 92343 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 57356000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1623180000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 1680536000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3121300000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 3121300000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 57356000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 4744480000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 4801836000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 57356000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 4744480000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 4801836000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 1107 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 193486 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 194593 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 407009 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 407009 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 259735 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 259735 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 1107 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 453221 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 454328 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 1107 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 453221 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 454328 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996387 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.161330 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.166080 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.231101 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.231101 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996387 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.201315 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.203252 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996387 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.201315 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.203252 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks 59035 # number of writebacks
system.cpu.l2cache.writebacks::total 59035 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1103 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 31215 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 32318 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 60025 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 60025 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 1103 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 91240 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 92343 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 1103 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 91240 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 92343 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 44120000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1248600000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1292720000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2401000000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2401000000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 44120000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3649600000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 3693720000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 44120000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3649600000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 3693720000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996387 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.161330 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.166080 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.231101 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.231101 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996387 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.201315 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.203252 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996387 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.201315 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.203252 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

550
simulators/gem5/tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini Normal file
View File

@ -0,0 +1,550 @@
[root]
type=Root
children=system
full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
boot_osflags=a
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
readfile=
symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.cpu]
type=DerivO3CPU
children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
LSQDepCheckShift=4
RASSize=16
SQEntries=32
SSITSize=1024
activity=0
backComSize=5
cachePorts=200
checker=Null
choiceCtrBits=2
choicePredictorSize=8192
clock=500
commitToDecodeDelay=1
commitToFetchDelay=1
commitToIEWDelay=1
commitToRenameDelay=1
commitWidth=8
cpu_id=0
decodeToFetchDelay=1
decodeToRenameDelay=1
decodeWidth=8
defer_registration=false
dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
fetchToDecodeDelay=1
fetchTrapLatency=1
fetchWidth=8
forwardComSize=5
fuPool=system.cpu.fuPool
function_trace=false
function_trace_start=0
globalCtrBits=2
globalHistoryBits=13
globalPredictorSize=8192
iewToCommitDelay=1
iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
instShiftAmt=2
interrupts=system.cpu.interrupts
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
localCtrBits=2
localHistoryBits=11
localHistoryTableSize=2048
localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
needsTSO=true
numIQEntries=64
numPhysFloatRegs=256
numPhysIntRegs=256
numROBEntries=192
numRobs=1
numThreads=1
phase=0
predType=tournament
profile=0
progress_interval=0
renameToDecodeDelay=1
renameToFetchDelay=1
renameToIEWDelay=2
renameToROBDelay=1
renameWidth=8
smtCommitPolicy=RoundRobin
smtFetchPolicy=SingleThread
smtIQPolicy=Partitioned
smtIQThreshold=100
smtLSQPolicy=Partitioned
smtLSQThreshold=100
smtNumFetchingThreads=1
smtROBPolicy=Partitioned
smtROBThreshold=100
squashWidth=8
store_set_clear_period=250000
system=system
tracer=system.cpu.tracer
trapLatency=13
wbDepth=1
wbWidth=8
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=262144
subblock_size=0
system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
[system.cpu.dtb]
type=X86TLB
children=walker
size=64
walker=system.cpu.dtb.walker
[system.cpu.dtb.walker]
type=X86PagetableWalker
system=system
port=system.cpu.toL2Bus.slave[3]
[system.cpu.fuPool]
type=FUPool
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
[system.cpu.fuPool.FUList0]
type=FUDesc
children=opList
count=6
opList=system.cpu.fuPool.FUList0.opList
[system.cpu.fuPool.FUList0.opList]
type=OpDesc
issueLat=1
opClass=IntAlu
opLat=1
[system.cpu.fuPool.FUList1]
type=FUDesc
children=opList0 opList1
count=2
opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
[system.cpu.fuPool.FUList1.opList0]
type=OpDesc
issueLat=1
opClass=IntMult
opLat=3
[system.cpu.fuPool.FUList1.opList1]
type=OpDesc
issueLat=19
opClass=IntDiv
opLat=20
[system.cpu.fuPool.FUList2]
type=FUDesc
children=opList0 opList1 opList2
count=4
opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
[system.cpu.fuPool.FUList2.opList0]
type=OpDesc
issueLat=1
opClass=FloatAdd
opLat=2
[system.cpu.fuPool.FUList2.opList1]
type=OpDesc
issueLat=1
opClass=FloatCmp
opLat=2
[system.cpu.fuPool.FUList2.opList2]
type=OpDesc
issueLat=1
opClass=FloatCvt
opLat=2
[system.cpu.fuPool.FUList3]
type=FUDesc
children=opList0 opList1 opList2
count=2
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
[system.cpu.fuPool.FUList3.opList0]
type=OpDesc
issueLat=1
opClass=FloatMult
opLat=4
[system.cpu.fuPool.FUList3.opList1]
type=OpDesc
issueLat=12
opClass=FloatDiv
opLat=12
[system.cpu.fuPool.FUList3.opList2]
type=OpDesc
issueLat=24
opClass=FloatSqrt
opLat=24
[system.cpu.fuPool.FUList4]
type=FUDesc
children=opList
count=0
opList=system.cpu.fuPool.FUList4.opList
[system.cpu.fuPool.FUList4.opList]
type=OpDesc
issueLat=1
opClass=MemRead
opLat=1
[system.cpu.fuPool.FUList5]
type=FUDesc
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
count=4
opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
[system.cpu.fuPool.FUList5.opList00]
type=OpDesc
issueLat=1
opClass=SimdAdd
opLat=1
[system.cpu.fuPool.FUList5.opList01]
type=OpDesc
issueLat=1
opClass=SimdAddAcc
opLat=1
[system.cpu.fuPool.FUList5.opList02]
type=OpDesc
issueLat=1
opClass=SimdAlu
opLat=1
[system.cpu.fuPool.FUList5.opList03]
type=OpDesc
issueLat=1
opClass=SimdCmp
opLat=1
[system.cpu.fuPool.FUList5.opList04]
type=OpDesc
issueLat=1
opClass=SimdCvt
opLat=1
[system.cpu.fuPool.FUList5.opList05]
type=OpDesc
issueLat=1
opClass=SimdMisc
opLat=1
[system.cpu.fuPool.FUList5.opList06]
type=OpDesc
issueLat=1
opClass=SimdMult
opLat=1
[system.cpu.fuPool.FUList5.opList07]
type=OpDesc
issueLat=1
opClass=SimdMultAcc
opLat=1
[system.cpu.fuPool.FUList5.opList08]
type=OpDesc
issueLat=1
opClass=SimdShift
opLat=1
[system.cpu.fuPool.FUList5.opList09]
type=OpDesc
issueLat=1
opClass=SimdShiftAcc
opLat=1
[system.cpu.fuPool.FUList5.opList10]
type=OpDesc
issueLat=1
opClass=SimdSqrt
opLat=1
[system.cpu.fuPool.FUList5.opList11]
type=OpDesc
issueLat=1
opClass=SimdFloatAdd
opLat=1
[system.cpu.fuPool.FUList5.opList12]
type=OpDesc
issueLat=1
opClass=SimdFloatAlu
opLat=1
[system.cpu.fuPool.FUList5.opList13]
type=OpDesc
issueLat=1
opClass=SimdFloatCmp
opLat=1
[system.cpu.fuPool.FUList5.opList14]
type=OpDesc
issueLat=1
opClass=SimdFloatCvt
opLat=1
[system.cpu.fuPool.FUList5.opList15]
type=OpDesc
issueLat=1
opClass=SimdFloatDiv
opLat=1
[system.cpu.fuPool.FUList5.opList16]
type=OpDesc
issueLat=1
opClass=SimdFloatMisc
opLat=1
[system.cpu.fuPool.FUList5.opList17]
type=OpDesc
issueLat=1
opClass=SimdFloatMult
opLat=1
[system.cpu.fuPool.FUList5.opList18]
type=OpDesc
issueLat=1
opClass=SimdFloatMultAcc
opLat=1
[system.cpu.fuPool.FUList5.opList19]
type=OpDesc
issueLat=1
opClass=SimdFloatSqrt
opLat=1
[system.cpu.fuPool.FUList6]
type=FUDesc
children=opList
count=0
opList=system.cpu.fuPool.FUList6.opList
[system.cpu.fuPool.FUList6.opList]
type=OpDesc
issueLat=1
opClass=MemWrite
opLat=1
[system.cpu.fuPool.FUList7]
type=FUDesc
children=opList0 opList1
count=4
opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
[system.cpu.fuPool.FUList7.opList0]
type=OpDesc
issueLat=1
opClass=MemRead
opLat=1
[system.cpu.fuPool.FUList7.opList1]
type=OpDesc
issueLat=1
opClass=MemWrite
opLat=1
[system.cpu.fuPool.FUList8]
type=FUDesc
children=opList
count=1
opList=system.cpu.fuPool.FUList8.opList
[system.cpu.fuPool.FUList8.opList]
type=OpDesc
issueLat=3
opClass=IprAccess
opLat=3
[system.cpu.icache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=131072
subblock_size=0
system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.interrupts]
type=X86LocalApic
int_latency=1000
pio_addr=2305843009213693952
pio_latency=1000
system=system
int_master=system.membus.slave[2]
int_slave=system.membus.master[2]
pio=system.membus.master[1]
[system.cpu.itb]
type=X86TLB
children=walker
size=64
walker=system.cpu.itb.walker
[system.cpu.itb.walker]
type=X86PagetableWalker
system=system
port=system.cpu.toL2Bus.slave[2]
[system.cpu.l2cache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=false
latency=1000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=2097152
subblock_size=0
system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
[system.cpu.toL2Bus]
type=CoherentBus
block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=gzip input.log 1
cwd=build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing
egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/cpu2000/binaries/x86/linux/gzip
gid=100
input=cin
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=0
system=system
uid=100
[system.membus]
type=CoherentBus
block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave
slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master
[system.physmem]
type=SimpleMemory
conf_table_reported=false
file=
in_addr_map=true
latency=30000
latency_var=0
null=false
range=0:134217727
zero=false
port=system.membus.master[0]

4
simulators/gem5/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simerr Executable file
View File

@ -0,0 +1,4 @@
warn: Sockets disabled, not accepting gdb connections
warn: instruction 'fnstcw_Mw' unimplemented
warn: instruction 'fldcw_Mw' unimplemented
hack: be nice to actually delete the event here

43
simulators/gem5/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout Executable file
View File

@ -0,0 +1,43 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 4 2012 13:44:28
gem5 started Jun 4 2012 15:07:25
gem5 executing on zizzer
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
spec_init
Loading Input Data
Duplicating 262144 bytes
Duplicating 524288 bytes
Input data 1048576 bytes in length
Compressing Input Data, level 1
Compressed data 108074 bytes in length
Uncompressing Data
info: Increasing stack size by one page.
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Compressing Input Data, level 3
Compressed data 97831 bytes in length
Uncompressing Data
info: Increasing stack size by one page.
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Compressing Input Data, level 5
Compressed data 83382 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Compressing Input Data, level 7
Compressed data 76606 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Compressing Input Data, level 9
Compressed data 73189 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
Exiting @ tick 636988382500 because target called exit()

639
simulators/gem5/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt Normal file
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@ -0,0 +1,639 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.636988 # Number of seconds simulated
sim_ticks 636988382500 # Number of ticks simulated
final_tick 636988382500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 63436 # Simulator instruction rate (inst/s)
host_op_rate 116883 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 45916521 # Simulator tick rate (ticks/s)
host_mem_usage 227532 # Number of bytes of host memory used
host_seconds 13872.75 # Real time elapsed on the host
sim_insts 880025312 # Number of instructions simulated
sim_ops 1621493982 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 59200 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 5774848 # Number of bytes read from this memory
system.physmem.bytes_read::total 5834048 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 59200 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 59200 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 3731712 # Number of bytes written to this memory
system.physmem.bytes_written::total 3731712 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 925 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 90232 # Number of read requests responded to by this memory
system.physmem.num_reads::total 91157 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 58308 # Number of write requests responded to by this memory
system.physmem.num_writes::total 58308 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 92937 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 9065861 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 9158798 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 92937 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 92937 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 5858367 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 5858367 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 5858367 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 92937 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 9065861 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 15017166 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 48 # Number of system calls
system.cpu.numCycles 1273976766 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.BPredUnit.lookups 154678064 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 154678064 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 26667110 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 77406078 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 77035710 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 180711057 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 1490230522 # Number of instructions fetch has processed
system.cpu.fetch.Branches 154678064 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 77035710 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 402278451 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 93695646 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 624053491 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 174 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 1298 # Number of stall cycles due to pending traps
system.cpu.fetch.CacheLines 186830267 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 9529255 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 1273914012 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 1.999814 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.235188 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 878853214 68.99% 68.99% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 24303546 1.91% 70.90% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 15677834 1.23% 72.13% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 17928928 1.41% 73.53% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 26735770 2.10% 75.63% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 18262172 1.43% 77.07% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 28765750 2.26% 79.32% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 39797773 3.12% 82.45% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 223589025 17.55% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 1273914012 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.121414 # Number of branch fetches per cycle
system.cpu.fetch.rate 1.169747 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 300082895 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 537078967 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 281798821 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 88083788 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 66869541 # Number of cycles decode is squashing
system.cpu.decode.DecodedInsts 2368899404 # Number of instructions handled by decode
system.cpu.rename.SquashCycles 66869541 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 352603459 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 124071504 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 2838 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 302490800 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 427875870 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 2273771459 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 200 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 293326885 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 103161675 # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents 640 # Number of times there has been no free registers
system.cpu.rename.RenamedOperands 3463149697 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 7120628194 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 7120621014 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 7180 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 2493860970 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 969288727 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 110 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 110 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 746079760 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 546341437 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 222247757 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 352469730 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 147023702 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 2027529381 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 546 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 1785574895 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 118982 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 405869160 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 1051620727 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 496 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 1273914012 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 1.401645 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.311838 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 347011244 27.24% 27.24% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 447440186 35.12% 62.36% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 243114046 19.08% 81.45% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 151317631 11.88% 93.33% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 40944695 3.21% 96.54% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 32410749 2.54% 99.08% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 9957171 0.78% 99.87% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 1368147 0.11% 99.97% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 350143 0.03% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 1273914012 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 237387 9.29% 9.29% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 9.29% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 9.29% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.29% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.29% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.29% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 9.29% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.29% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.29% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.29% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.29% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.29% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.29% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.29% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.29% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 9.29% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.29% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 9.29% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.29% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.29% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.29% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.29% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.29% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.29% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.29% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.29% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.29% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.29% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.29% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 2138623 83.73% 93.02% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 178205 6.98% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 46809715 2.62% 2.62% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 1066790690 59.74% 62.37% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 0 0.00% 62.37% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.37% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.37% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.37% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.37% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.37% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.37% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.37% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 479501542 26.85% 89.22% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 192472948 10.78% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 1785574895 # Type of FU issued
system.cpu.iq.rate 1.401576 # Inst issue rate
system.cpu.iq.fu_busy_cnt 2554215 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.001430 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 4847736227 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 2433580235 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 1726806271 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 772 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 2168 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 84 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 1741319146 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 249 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 208956586 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 127299312 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 36681 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 190307 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 34061700 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 1845 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 66869541 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 356934 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 88692 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 2027529927 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 63849570 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 546341437 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 222247757 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 103 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 48888 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 421 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 190307 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 2139656 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 24653796 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 26793452 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 1767588629 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 473898164 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 17986266 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
system.cpu.iew.exec_refs 665742013 # number of memory reference insts executed
system.cpu.iew.exec_branches 109684623 # Number of branches executed
system.cpu.iew.exec_stores 191843849 # Number of stores executed
system.cpu.iew.exec_rate 1.387458 # Inst execution rate
system.cpu.iew.wb_sent 1728148485 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 1726806355 # cumulative count of insts written-back
system.cpu.iew.wb_producers 1262041827 # num instructions producing a value
system.cpu.iew.wb_consumers 2984894243 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 1.355446 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.422810 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitCommittedInsts 880025312 # The number of committed instructions
system.cpu.commit.commitCommittedOps 1621493982 # The number of committed instructions
system.cpu.commit.commitSquashedInsts 406040141 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 50 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 26667277 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 1207044471 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.343359 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.660546 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 437250010 36.22% 36.22% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 432641487 35.84% 72.07% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 93464877 7.74% 79.81% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 134893392 11.18% 90.99% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 35716518 2.96% 93.95% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 23306370 1.93% 95.88% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 25727632 2.13% 98.01% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 8874629 0.74% 98.74% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 15169556 1.26% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 1207044471 # Number of insts commited each cycle
system.cpu.commit.committedInsts 880025312 # Number of instructions committed
system.cpu.commit.committedOps 1621493982 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 607228182 # Number of memory references committed
system.cpu.commit.loads 419042125 # Number of loads committed
system.cpu.commit.membars 0 # Number of memory barriers committed
system.cpu.commit.branches 107161579 # Number of branches committed
system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
system.cpu.commit.int_insts 1621354492 # Number of committed integer instructions.
system.cpu.commit.function_calls 0 # Number of function calls committed.
system.cpu.commit.bw_lim_events 15169556 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 3219409038 # The number of ROB reads
system.cpu.rob.rob_writes 4121954747 # The number of ROB writes
system.cpu.timesIdled 1354 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 62754 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 880025312 # Number of Instructions Simulated
system.cpu.committedOps 1621493982 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 880025312 # Number of Instructions Simulated
system.cpu.cpi 1.447659 # CPI: Cycles Per Instruction
system.cpu.cpi_total 1.447659 # CPI: Total CPI of All Threads
system.cpu.ipc 0.690770 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.690770 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 4473469252 # number of integer regfile reads
system.cpu.int_regfile_writes 2589680881 # number of integer regfile writes
system.cpu.fp_regfile_reads 84 # number of floating regfile reads
system.cpu.misc_regfile_reads 911429698 # number of misc regfile reads
system.cpu.icache.replacements 22 # number of replacements
system.cpu.icache.tagsinuse 827.099302 # Cycle average of tags in use
system.cpu.icache.total_refs 186828876 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 928 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 201324.219828 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 827.099302 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.403857 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.403857 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 186828882 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 186828882 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 186828882 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 186828882 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 186828882 # number of overall hits
system.cpu.icache.overall_hits::total 186828882 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 1385 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 1385 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 1385 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 1385 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 1385 # number of overall misses
system.cpu.icache.overall_misses::total 1385 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 46636000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 46636000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 46636000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 46636000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 46636000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 46636000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 186830267 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 186830267 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 186830267 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 186830267 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 186830267 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 186830267 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000007 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000007 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000007 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000007 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000007 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000007 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 33672.202166 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 33672.202166 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 33672.202166 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 33672.202166 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 33672.202166 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 33672.202166 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 450 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 450 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 450 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 450 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 450 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 450 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 935 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 935 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 935 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 935 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 935 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 935 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 32805000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 32805000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 32805000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 32805000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 32805000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 32805000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000005 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000005 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000005 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35085.561497 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35085.561497 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35085.561497 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 35085.561497 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35085.561497 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 35085.561497 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 445407 # number of replacements
system.cpu.dcache.tagsinuse 4093.514636 # Cycle average of tags in use
system.cpu.dcache.total_refs 452671406 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 449503 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 1007.048687 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 723816000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 4093.514636 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.999393 # Average percentage of cache occupancy
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system.cpu.dcache.ReadReq_hits::cpu.data 264731564 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 264731564 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 187939830 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 187939830 # number of WriteReq hits
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system.cpu.dcache.demand_hits::total 452671394 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 452671394 # number of overall hits
system.cpu.dcache.overall_hits::total 452671394 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 206744 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 206744 # number of ReadReq misses
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system.cpu.dcache.WriteReq_misses::total 246227 # number of WriteReq misses
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system.cpu.dcache.demand_misses::total 452971 # number of demand (read+write) misses
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system.cpu.dcache.overall_misses::total 452971 # number of overall misses
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system.cpu.dcache.overall_miss_latency::total 5373046500 # number of overall miss cycles
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system.cpu.dcache.WriteReq_accesses::total 188186057 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.demand_accesses::total 453124365 # number of demand (read+write) accesses
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system.cpu.dcache.overall_miss_rate::cpu.data 0.001000 # miss rate for overall accesses
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system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 10393.162559 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 10393.162559 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 13094.918510 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 13094.918510 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 11861.789165 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 11861.789165 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 11861.789165 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 11861.789165 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
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system.cpu.dcache.writebacks::writebacks 400713 # number of writebacks
system.cpu.dcache.writebacks::total 400713 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3434 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 3434 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 25 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 25 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 3459 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 3459 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 3459 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 3459 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 203310 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 203310 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 246202 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 246202 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 449512 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 449512 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 449512 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 449512 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1511006000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 1511006000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2485166000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 2485166000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 3996172000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 3996172000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 3996172000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 3996172000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000767 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000767 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001308 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.001308 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000992 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.000992 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000992 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.000992 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7432.029905 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 7432.029905 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10094.012234 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10094.012234 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8890.022958 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 8890.022958 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8890.022958 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 8890.022958 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 72883 # number of replacements
system.cpu.l2cache.tagsinuse 17779.692577 # Cycle average of tags in use
system.cpu.l2cache.total_refs 433456 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 88505 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 4.897531 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 15879.164577 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 61.338092 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 1839.189909 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.484594 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.001872 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.056128 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.542593 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 3 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 171391 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 171394 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 400713 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 400713 # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data 7 # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total 7 # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 187882 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 187882 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 359273 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 359276 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 3 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 359273 # number of overall hits
system.cpu.l2cache.overall_hits::total 359276 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 925 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 31911 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 32836 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 58321 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 58321 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 925 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 90232 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 91157 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 925 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 90232 # number of overall misses
system.cpu.l2cache.overall_misses::total 91157 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 31707500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1094294500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 1126002000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1998540500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 1998540500 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 31707500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 3092835000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 3124542500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 31707500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 3092835000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 3124542500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 928 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 203302 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 204230 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 400713 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 400713 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 7 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total 7 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 246203 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 246203 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 928 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 449505 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 450433 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 928 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 449505 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 450433 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996767 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.156964 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.160780 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.236882 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.236882 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996767 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.200736 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.202376 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996767 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.200736 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.202376 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34278.378378 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34292.077967 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 34291.692045 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34267.939507 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34267.939507 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34278.378378 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34276.476195 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 34276.495497 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34278.378378 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34276.476195 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 34276.495497 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks 58308 # number of writebacks
system.cpu.l2cache.writebacks::total 58308 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 925 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 31911 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 32836 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 58321 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 58321 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 925 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 90232 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 91157 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 925 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 90232 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 91157 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 28735500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 989353500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1018089000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1807989500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1807989500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 28735500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 2797343000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 2826078500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 28735500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2797343000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 2826078500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996767 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.156964 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.160780 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.236882 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.236882 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996767 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.200736 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.202376 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996767 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.200736 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.202376 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31065.405405 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31003.525430 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31005.268608 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31000.660140 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31000.660140 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31065.405405 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31001.673464 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31002.320173 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31065.405405 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31001.673464 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31002.320173 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

138
simulators/gem5/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/config.ini Normal file
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[root]
type=Root
children=system
full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
boot_osflags=a
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
readfile=
symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.cpu]
type=AtomicSimpleCPU
children=dtb interrupts itb tracer workload
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
fastmem=false
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
phase=0
profile=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
system=system
tracer=system.cpu.tracer
width=1
workload=system.cpu.workload
dcache_port=system.membus.slave[2]
icache_port=system.membus.slave[1]
[system.cpu.dtb]
type=X86TLB
children=walker
size=64
walker=system.cpu.dtb.walker
[system.cpu.dtb.walker]
type=X86PagetableWalker
system=system
port=system.membus.slave[4]
[system.cpu.interrupts]
type=X86LocalApic
int_latency=1000
pio_addr=2305843009213693952
pio_latency=1000
system=system
int_master=system.membus.slave[5]
int_slave=system.membus.master[2]
pio=system.membus.master[1]
[system.cpu.itb]
type=X86TLB
children=walker
size=64
walker=system.cpu.itb.walker
[system.cpu.itb.walker]
type=X86PagetableWalker
system=system
port=system.membus.slave[3]
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=gzip input.log 1
cwd=build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-atomic
egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/cpu2000/binaries/x86/linux/gzip
gid=100
input=cin
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=0
system=system
uid=100
[system.membus]
type=CoherentBus
block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.interrupts.int_master
[system.physmem]
type=SimpleMemory
conf_table_reported=false
file=
in_addr_map=true
latency=30000
latency_var=0
null=false
range=0:134217727
zero=false
port=system.membus.master[0]

4
simulators/gem5/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simerr Executable file
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warn: Sockets disabled, not accepting gdb connections
warn: instruction 'fnstcw_Mw' unimplemented
warn: instruction 'fldcw_Mw' unimplemented
hack: be nice to actually delete the event here

42
simulators/gem5/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simout Executable file
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gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 4 2012 13:44:28
gem5 started Jun 4 2012 15:08:17
gem5 executing on zizzer
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
spec_init
Loading Input Data
Duplicating 262144 bytes
Duplicating 524288 bytes
Input data 1048576 bytes in length
Compressing Input Data, level 1
Compressed data 108074 bytes in length
Uncompressing Data
info: Increasing stack size by one page.
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Compressing Input Data, level 3
Compressed data 97831 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Compressing Input Data, level 5
Compressed data 83382 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Compressing Input Data, level 7
Compressed data 76606 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Compressing Input Data, level 9
Compressed data 73189 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
Exiting @ tick 963992704000 because target called exit()

60
simulators/gem5/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/stats.txt Normal file
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---------- Begin Simulation Statistics ----------
sim_seconds 0.963993 # Number of seconds simulated
sim_ticks 963992704000 # Number of ticks simulated
final_tick 963992704000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1254577 # Simulator instruction rate (inst/s)
host_op_rate 2311626 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1374282564 # Simulator tick rate (ticks/s)
host_mem_usage 216676 # Number of bytes of host memory used
host_seconds 701.45 # Real time elapsed on the host
sim_insts 880025313 # Number of instructions simulated
sim_ops 1621493983 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 9492133912 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 1842452913 # Number of bytes read from this memory
system.physmem.bytes_read::total 11334586825 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 9492133912 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 9492133912 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 864451000 # Number of bytes written to this memory
system.physmem.bytes_written::total 864451000 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 1186516739 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 419042125 # Number of read requests responded to by this memory
system.physmem.num_reads::total 1605558864 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 188186057 # Number of write requests responded to by this memory
system.physmem.num_writes::total 188186057 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 9846686466 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 1911272674 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 11757959140 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 9846686466 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 9846686466 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 896740189 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 896740189 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 9846686466 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2808012863 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 12654699330 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 48 # Number of system calls
system.cpu.numCycles 1927985409 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 880025313 # Number of instructions committed
system.cpu.committedOps 1621493983 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 1621354493 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu.num_func_calls 0 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 99478861 # number of instructions that are conditional controls
system.cpu.num_int_insts 1621354493 # number of integer instructions
system.cpu.num_fp_insts 0 # number of float instructions
system.cpu.num_int_register_reads 5129484088 # number of times the integer registers were read
system.cpu.num_int_register_writes 2493860970 # number of times the integer registers were written
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_mem_refs 607228182 # number of memory refs
system.cpu.num_load_insts 419042125 # Number of load instructions
system.cpu.num_store_insts 188186057 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 1927985409 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
---------- End Simulation Statistics ----------

219
simulators/gem5/tests/long/se/00.gzip/ref/x86/linux/simple-timing/config.ini Normal file
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@ -0,0 +1,219 @@
[root]
type=Root
children=system
full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
boot_osflags=a
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
readfile=
symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.cpu]
type=TimingSimpleCPU
children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
phase=0
profile=0
progress_interval=0
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=262144
subblock_size=0
system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
[system.cpu.dtb]
type=X86TLB
children=walker
size=64
walker=system.cpu.dtb.walker
[system.cpu.dtb.walker]
type=X86PagetableWalker
system=system
port=system.cpu.toL2Bus.slave[3]
[system.cpu.icache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=131072
subblock_size=0
system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.interrupts]
type=X86LocalApic
int_latency=1000
pio_addr=2305843009213693952
pio_latency=1000
system=system
int_master=system.membus.slave[2]
int_slave=system.membus.master[2]
pio=system.membus.master[1]
[system.cpu.itb]
type=X86TLB
children=walker
size=64
walker=system.cpu.itb.walker
[system.cpu.itb.walker]
type=X86PagetableWalker
system=system
port=system.cpu.toL2Bus.slave[2]
[system.cpu.l2cache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=false
latency=10000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=2097152
subblock_size=0
system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
[system.cpu.toL2Bus]
type=CoherentBus
block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=gzip input.log 1
cwd=build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-timing
egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/cpu2000/binaries/x86/linux/gzip
gid=100
input=cin
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=0
system=system
uid=100
[system.membus]
type=CoherentBus
block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave
slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master
[system.physmem]
type=SimpleMemory
conf_table_reported=false
file=
in_addr_map=true
latency=30000
latency_var=0
null=false
range=0:134217727
zero=false
port=system.membus.master[0]

4
simulators/gem5/tests/long/se/00.gzip/ref/x86/linux/simple-timing/simerr Executable file
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@ -0,0 +1,4 @@
warn: Sockets disabled, not accepting gdb connections
warn: instruction 'fnstcw_Mw' unimplemented
warn: instruction 'fldcw_Mw' unimplemented
hack: be nice to actually delete the event here

42
simulators/gem5/tests/long/se/00.gzip/ref/x86/linux/simple-timing/simout Executable file
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@ -0,0 +1,42 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 4 2012 13:44:28
gem5 started Jun 4 2012 15:13:02
gem5 executing on zizzer
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
spec_init
Loading Input Data
Duplicating 262144 bytes
Duplicating 524288 bytes
Input data 1048576 bytes in length
Compressing Input Data, level 1
Compressed data 108074 bytes in length
Uncompressing Data
info: Increasing stack size by one page.
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Compressing Input Data, level 3
Compressed data 97831 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Compressing Input Data, level 5
Compressed data 83382 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Compressing Input Data, level 7
Compressed data 76606 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Compressing Input Data, level 9
Compressed data 73189 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
Exiting @ tick 1803258587000 because target called exit()

374
simulators/gem5/tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt Normal file
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@ -0,0 +1,374 @@
---------- Begin Simulation Statistics ----------
sim_seconds 1.803259 # Number of seconds simulated
sim_ticks 1803258587000 # Number of ticks simulated
final_tick 1803258587000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 587265 # Simulator instruction rate (inst/s)
host_op_rate 1082068 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1203364849 # Simulator tick rate (ticks/s)
host_mem_usage 225604 # Number of bytes of host memory used
host_seconds 1498.51 # Real time elapsed on the host
sim_insts 880025313 # Number of instructions simulated
sim_ops 1621493983 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 46208 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 5679744 # Number of bytes read from this memory
system.physmem.bytes_read::total 5725952 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 46208 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 46208 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 3712448 # Number of bytes written to this memory
system.physmem.bytes_written::total 3712448 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 722 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 88746 # Number of read requests responded to by this memory
system.physmem.num_reads::total 89468 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 58007 # Number of write requests responded to by this memory
system.physmem.num_writes::total 58007 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 25625 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 3149711 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 3175336 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 25625 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 25625 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 2058744 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 2058744 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 2058744 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 25625 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 3149711 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 5234080 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 48 # Number of system calls
system.cpu.numCycles 3606517174 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 880025313 # Number of instructions committed
system.cpu.committedOps 1621493983 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 1621354493 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu.num_func_calls 0 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 99478861 # number of instructions that are conditional controls
system.cpu.num_int_insts 1621354493 # number of integer instructions
system.cpu.num_fp_insts 0 # number of float instructions
system.cpu.num_int_register_reads 5129484088 # number of times the integer registers were read
system.cpu.num_int_register_writes 2493860970 # number of times the integer registers were written
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_mem_refs 607228182 # number of memory refs
system.cpu.num_load_insts 419042125 # Number of load instructions
system.cpu.num_store_insts 188186057 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 3606517174 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.icache.replacements 4 # number of replacements
system.cpu.icache.tagsinuse 660.186297 # Cycle average of tags in use
system.cpu.icache.total_refs 1186516018 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 722 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 1643373.986150 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 660.186297 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.322357 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.322357 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 1186516018 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 1186516018 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 1186516018 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 1186516018 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 1186516018 # number of overall hits
system.cpu.icache.overall_hits::total 1186516018 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 722 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 722 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 722 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 722 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 722 # number of overall misses
system.cpu.icache.overall_misses::total 722 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 40432000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 40432000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 40432000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 40432000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 40432000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 40432000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 1186516740 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 1186516740 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 1186516740 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 1186516740 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 1186516740 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 1186516740 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000001 # miss rate for ReadReq accesses
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system.cpu.icache.overall_avg_miss_latency::cpu.inst 56000 # average overall miss latency
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system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.200761 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.202064 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

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simulators/gem5/tests/long/se/00.gzip/test.py Normal file
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# Copyright (c) 2006-2007 The Regents of The University of Michigan
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Korey Sewell
m5.util.addToPath('../configs/common')
from cpu2000 import gzip_log
workload = gzip_log(isa, opsys, 'smred')
root.system.cpu.workload = workload.makeLiveProcess()

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P6
15 15
255


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simulators/gem5/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini Normal file
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[root]
type=Root
children=system
full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
boot_osflags=a
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
readfile=
symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.cpu]
type=DerivO3CPU
children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
LSQDepCheckShift=4
RASSize=16
SQEntries=32
SSITSize=1024
activity=0
backComSize=5
cachePorts=200
checker=Null
choiceCtrBits=2
choicePredictorSize=8192
clock=500
commitToDecodeDelay=1
commitToFetchDelay=1
commitToIEWDelay=1
commitToRenameDelay=1
commitWidth=8
cpu_id=0
decodeToFetchDelay=1
decodeToRenameDelay=1
decodeWidth=8
defer_registration=false
dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
fetchToDecodeDelay=1
fetchTrapLatency=1
fetchWidth=8
forwardComSize=5
fuPool=system.cpu.fuPool
function_trace=false
function_trace_start=0
globalCtrBits=2
globalHistoryBits=13
globalPredictorSize=8192
iewToCommitDelay=1
iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
instShiftAmt=2
interrupts=system.cpu.interrupts
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
localCtrBits=2
localHistoryBits=11
localHistoryTableSize=2048
localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
needsTSO=false
numIQEntries=64
numPhysFloatRegs=256
numPhysIntRegs=256
numROBEntries=192
numRobs=1
numThreads=1
phase=0
predType=tournament
profile=0
progress_interval=0
renameToDecodeDelay=1
renameToFetchDelay=1
renameToIEWDelay=2
renameToROBDelay=1
renameWidth=8
smtCommitPolicy=RoundRobin
smtFetchPolicy=SingleThread
smtIQPolicy=Partitioned
smtIQThreshold=100
smtLSQPolicy=Partitioned
smtLSQThreshold=100
smtNumFetchingThreads=1
smtROBPolicy=Partitioned
smtROBThreshold=100
squashWidth=8
store_set_clear_period=250000
system=system
tracer=system.cpu.tracer
trapLatency=13
wbDepth=1
wbWidth=8
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=262144
subblock_size=0
system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
[system.cpu.dtb]
type=ArmTLB
children=walker
size=64
walker=system.cpu.dtb.walker
[system.cpu.dtb.walker]
type=ArmTableWalker
max_backoff=100000
min_backoff=0
sys=system
port=system.cpu.toL2Bus.slave[3]
[system.cpu.fuPool]
type=FUPool
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
[system.cpu.fuPool.FUList0]
type=FUDesc
children=opList
count=6
opList=system.cpu.fuPool.FUList0.opList
[system.cpu.fuPool.FUList0.opList]
type=OpDesc
issueLat=1
opClass=IntAlu
opLat=1
[system.cpu.fuPool.FUList1]
type=FUDesc
children=opList0 opList1
count=2
opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
[system.cpu.fuPool.FUList1.opList0]
type=OpDesc
issueLat=1
opClass=IntMult
opLat=3
[system.cpu.fuPool.FUList1.opList1]
type=OpDesc
issueLat=19
opClass=IntDiv
opLat=20
[system.cpu.fuPool.FUList2]
type=FUDesc
children=opList0 opList1 opList2
count=4
opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
[system.cpu.fuPool.FUList2.opList0]
type=OpDesc
issueLat=1
opClass=FloatAdd
opLat=2
[system.cpu.fuPool.FUList2.opList1]
type=OpDesc
issueLat=1
opClass=FloatCmp
opLat=2
[system.cpu.fuPool.FUList2.opList2]
type=OpDesc
issueLat=1
opClass=FloatCvt
opLat=2
[system.cpu.fuPool.FUList3]
type=FUDesc
children=opList0 opList1 opList2
count=2
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
[system.cpu.fuPool.FUList3.opList0]
type=OpDesc
issueLat=1
opClass=FloatMult
opLat=4
[system.cpu.fuPool.FUList3.opList1]
type=OpDesc
issueLat=12
opClass=FloatDiv
opLat=12
[system.cpu.fuPool.FUList3.opList2]
type=OpDesc
issueLat=24
opClass=FloatSqrt
opLat=24
[system.cpu.fuPool.FUList4]
type=FUDesc
children=opList
count=0
opList=system.cpu.fuPool.FUList4.opList
[system.cpu.fuPool.FUList4.opList]
type=OpDesc
issueLat=1
opClass=MemRead
opLat=1
[system.cpu.fuPool.FUList5]
type=FUDesc
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
count=4
opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
[system.cpu.fuPool.FUList5.opList00]
type=OpDesc
issueLat=1
opClass=SimdAdd
opLat=1
[system.cpu.fuPool.FUList5.opList01]
type=OpDesc
issueLat=1
opClass=SimdAddAcc
opLat=1
[system.cpu.fuPool.FUList5.opList02]
type=OpDesc
issueLat=1
opClass=SimdAlu
opLat=1
[system.cpu.fuPool.FUList5.opList03]
type=OpDesc
issueLat=1
opClass=SimdCmp
opLat=1
[system.cpu.fuPool.FUList5.opList04]
type=OpDesc
issueLat=1
opClass=SimdCvt
opLat=1
[system.cpu.fuPool.FUList5.opList05]
type=OpDesc
issueLat=1
opClass=SimdMisc
opLat=1
[system.cpu.fuPool.FUList5.opList06]
type=OpDesc
issueLat=1
opClass=SimdMult
opLat=1
[system.cpu.fuPool.FUList5.opList07]
type=OpDesc
issueLat=1
opClass=SimdMultAcc
opLat=1
[system.cpu.fuPool.FUList5.opList08]
type=OpDesc
issueLat=1
opClass=SimdShift
opLat=1
[system.cpu.fuPool.FUList5.opList09]
type=OpDesc
issueLat=1
opClass=SimdShiftAcc
opLat=1
[system.cpu.fuPool.FUList5.opList10]
type=OpDesc
issueLat=1
opClass=SimdSqrt
opLat=1
[system.cpu.fuPool.FUList5.opList11]
type=OpDesc
issueLat=1
opClass=SimdFloatAdd
opLat=1
[system.cpu.fuPool.FUList5.opList12]
type=OpDesc
issueLat=1
opClass=SimdFloatAlu
opLat=1
[system.cpu.fuPool.FUList5.opList13]
type=OpDesc
issueLat=1
opClass=SimdFloatCmp
opLat=1
[system.cpu.fuPool.FUList5.opList14]
type=OpDesc
issueLat=1
opClass=SimdFloatCvt
opLat=1
[system.cpu.fuPool.FUList5.opList15]
type=OpDesc
issueLat=1
opClass=SimdFloatDiv
opLat=1
[system.cpu.fuPool.FUList5.opList16]
type=OpDesc
issueLat=1
opClass=SimdFloatMisc
opLat=1
[system.cpu.fuPool.FUList5.opList17]
type=OpDesc
issueLat=1
opClass=SimdFloatMult
opLat=1
[system.cpu.fuPool.FUList5.opList18]
type=OpDesc
issueLat=1
opClass=SimdFloatMultAcc
opLat=1
[system.cpu.fuPool.FUList5.opList19]
type=OpDesc
issueLat=1
opClass=SimdFloatSqrt
opLat=1
[system.cpu.fuPool.FUList6]
type=FUDesc
children=opList
count=0
opList=system.cpu.fuPool.FUList6.opList
[system.cpu.fuPool.FUList6.opList]
type=OpDesc
issueLat=1
opClass=MemWrite
opLat=1
[system.cpu.fuPool.FUList7]
type=FUDesc
children=opList0 opList1
count=4
opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
[system.cpu.fuPool.FUList7.opList0]
type=OpDesc
issueLat=1
opClass=MemRead
opLat=1
[system.cpu.fuPool.FUList7.opList1]
type=OpDesc
issueLat=1
opClass=MemWrite
opLat=1
[system.cpu.fuPool.FUList8]
type=FUDesc
children=opList
count=1
opList=system.cpu.fuPool.FUList8.opList
[system.cpu.fuPool.FUList8.opList]
type=OpDesc
issueLat=3
opClass=IprAccess
opLat=3
[system.cpu.icache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=131072
subblock_size=0
system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.interrupts]
type=ArmInterrupts
[system.cpu.itb]
type=ArmTLB
children=walker
size=64
walker=system.cpu.itb.walker
[system.cpu.itb.walker]
type=ArmTableWalker
max_backoff=100000
min_backoff=0
sys=system
port=system.cpu.toL2Bus.slave[2]
[system.cpu.l2cache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=false
latency=1000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=2097152
subblock_size=0
system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
[system.cpu.toL2Bus]
type=CoherentBus
block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=mcf mcf.in
cwd=build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing
egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/cpu2000/binaries/arm/linux/mcf
gid=100
input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=55300000000
system=system
uid=100
[system.membus]
type=CoherentBus
block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
master=system.physmem.port[0]
slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=SimpleMemory
conf_table_reported=false
file=
in_addr_map=true
latency=30000
latency_var=0
null=false
range=0:268435455
zero=false
port=system.membus.master[0]

999
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()
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***
272
()
110
***
434
()
109
***
323
()
108
***
281
()
107
***
144
***
148
()
106
***
275
()
105
***
196
***
254
()
104
***
138
***
161
()
103
***
310
()
102
***
223
***
252
()
80
()
70
()
69
()
68
()
66
()
64
()
62
***
256
()
61
***
93
()
59
***
120
()
58
()
57
***
183
()
55
()
54
()
52
***
147
()
51
***
118
()
50
***
83
()
49
***
98
()
48
***
99
()
47
()
46
***
184
()
45
***
121
()
44
()
43
***
88
()
42
***
122
()
41
***
91
()
40
***
96
()
38
***
100
()
37
***
149
()
36
***
74
()
35
***
258
()
34
***
151
()
33
***
85
()
32
()
31
***
94
()
30
***
97
()
29
***
90
()
28
***
89
()
27
***
92
()
26
***
72
***
247
()
25
***
86
()
24
***
82
()
23
***
87
***
117
()
22
***
76
***
119
()
21
***
84
()
20
***
78
()
19
***
73
()
18
***
81
()
17
***
65
()
16
***
63
***
101
()
15
***
71
()
14
***
75
()
13
***
322
()
12
***
77
()
11
***
283
()
10
***
79
()
9
***
145
***
150
()
8
***
67
()
7
***
60
***
231
()
6
***
56
***
234
()
5
***
164
***
202
()
4
***
53
()
3
***
130
***
185
***
200
()
2
***
205
()
1
***
39
***
95

2
simulators/gem5/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simerr Executable file
View File

@ -0,0 +1,2 @@
warn: Sockets disabled, not accepting gdb connections
hack: be nice to actually delete the event here

26
simulators/gem5/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout Executable file
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@ -0,0 +1,26 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 4 2012 12:14:06
gem5 started Jun 4 2012 17:32:09
gem5 executing on zizzer
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
MCF SPEC version 1.6.I
by Andreas Loebel
Copyright (c) 1998,1999 ZIB Berlin
All Rights Reserved.
nodes : 500
active arcs : 1905
simplex iterations : 1502
flow value : 4990014995
new implicit arcs : 23867
active arcs : 25772
simplex iterations : 2663
flow value : 3080014995
checksum : 68389
optimal
Exiting @ tick 25988864000 because target called exit()

709
simulators/gem5/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt Normal file
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@ -0,0 +1,709 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.025989 # Number of seconds simulated
sim_ticks 25988864000 # Number of ticks simulated
final_tick 25988864000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 141606 # Simulator instruction rate (inst/s)
host_op_rate 142623 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 40620332 # Simulator tick rate (ticks/s)
host_mem_usage 364696 # Number of bytes of host memory used
host_seconds 639.80 # Real time elapsed on the host
sim_insts 90599356 # Number of instructions simulated
sim_ops 91249910 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 46144 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 952896 # Number of bytes read from this memory
system.physmem.bytes_read::total 999040 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 46144 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 46144 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 2048 # Number of bytes written to this memory
system.physmem.bytes_written::total 2048 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 721 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 14889 # Number of read requests responded to by this memory
system.physmem.num_reads::total 15610 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 32 # Number of write requests responded to by this memory
system.physmem.num_writes::total 32 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 1775530 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 36665550 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 38441080 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 1775530 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 1775530 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 78803 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 78803 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 78803 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 1775530 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 36665550 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 38519883 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 442 # Number of system calls
system.cpu.numCycles 51977729 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.BPredUnit.lookups 27100787 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 22324909 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 913851 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 11625204 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 11498872 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 61157 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 10323 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 14508615 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 130146910 # Number of instructions fetch has processed
system.cpu.fetch.Branches 27100787 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 11560029 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 24493529 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 4999674 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 8879281 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 2 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 50 # Number of stall cycles due to pending traps
system.cpu.fetch.CacheLines 14156722 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 388066 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 51938784 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.527703 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.247354 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 27487299 52.92% 52.92% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 3456218 6.65% 59.58% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 2037280 3.92% 63.50% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 1594827 3.07% 66.57% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 1702478 3.28% 69.85% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 2979904 5.74% 75.59% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 1536396 2.96% 78.54% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 1112311 2.14% 80.68% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 10032071 19.32% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 51938784 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.521392 # Number of branch fetches per cycle
system.cpu.fetch.rate 2.503898 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 17258666 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 6822276 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 22930941 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 878432 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 4048469 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 4484484 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 8960 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 128309268 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 42973 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 4048469 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 19038937 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 2026641 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 195067 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 21988132 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 4641538 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 124853766 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 22 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 286024 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 3901771 # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents 441 # Number of times there has been no free registers
system.cpu.rename.RenamedOperands 145615724 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 543819179 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 543813062 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 6117 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 107429479 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 38186245 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 20008 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 20006 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 11296413 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 29738779 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 5601526 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 2062082 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 1203344 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 119239629 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 22672 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 105633795 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 86270 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 27804178 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 69103102 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 12544 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 51938784 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 2.033813 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.918657 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 14084713 27.12% 27.12% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 11449450 22.04% 49.16% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 8003608 15.41% 64.57% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 6710442 12.92% 77.49% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 5305637 10.22% 87.71% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 2900837 5.59% 93.29% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 2546575 4.90% 98.19% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 460556 0.89% 99.08% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 476966 0.92% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 51938784 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 33927 5.08% 5.08% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 27 0.00% 5.08% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 5.08% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.08% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.08% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.08% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 5.08% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.08% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.08% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.08% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.08% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.08% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.08% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.08% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.08% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 5.08% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.08% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 5.08% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.08% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.08% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.08% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.08% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.08% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.08% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.08% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.08% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.08% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.08% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.08% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 354815 53.12% 58.20% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 279170 41.80% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 74740578 70.75% 70.75% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 10525 0.01% 70.76% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.76% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.76% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.76% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.76% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.76% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.76% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 1 0.00% 70.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 195 0.00% 70.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 237 0.00% 70.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 70.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.76% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 25722669 24.35% 95.12% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 5159588 4.88% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 105633795 # Type of FU issued
system.cpu.iq.rate 2.032290 # Inst issue rate
system.cpu.iq.fu_busy_cnt 667939 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.006323 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 263959647 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 147067415 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 102938725 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 936 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 1347 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 404 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 106301267 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 467 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 423068 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 7162902 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 8413 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 3100 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 854772 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 39235 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 4048469 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 193737 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 33246 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 119298911 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 399459 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 29738779 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 5601526 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 18769 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 13636 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 1014 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 3100 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 499711 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 490212 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 989923 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 104558374 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 25377273 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 1075421 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 36610 # number of nop insts executed
system.cpu.iew.exec_refs 30470186 # number of memory reference insts executed
system.cpu.iew.exec_branches 21355608 # Number of branches executed
system.cpu.iew.exec_stores 5092913 # Number of stores executed
system.cpu.iew.exec_rate 2.011600 # Inst execution rate
system.cpu.iew.wb_sent 103258351 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 102939129 # cumulative count of insts written-back
system.cpu.iew.wb_producers 62202150 # num instructions producing a value
system.cpu.iew.wb_consumers 103963576 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 1.980447 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.598307 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitCommittedInsts 90611965 # The number of committed instructions
system.cpu.commit.commitCommittedOps 91262519 # The number of committed instructions
system.cpu.commit.commitSquashedInsts 28037719 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 10128 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 916929 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 47890316 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.905657 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.507554 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 17540600 36.63% 36.63% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 13534361 28.26% 64.89% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 4502880 9.40% 74.29% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 3873758 8.09% 82.38% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 1516151 3.17% 85.54% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 799389 1.67% 87.21% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 846315 1.77% 88.98% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 253211 0.53% 89.51% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 5023651 10.49% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 47890316 # Number of insts commited each cycle
system.cpu.commit.committedInsts 90611965 # Number of instructions committed
system.cpu.commit.committedOps 91262519 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 27322631 # Number of memory references committed
system.cpu.commit.loads 22575877 # Number of loads committed
system.cpu.commit.membars 3888 # Number of memory barriers committed
system.cpu.commit.branches 18722471 # Number of branches committed
system.cpu.commit.fp_insts 48 # Number of committed floating point instructions.
system.cpu.commit.int_insts 72533322 # Number of committed integer instructions.
system.cpu.commit.function_calls 56148 # Number of function calls committed.
system.cpu.commit.bw_lim_events 5023651 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 162161169 # The number of ROB reads
system.cpu.rob.rob_writes 242671240 # The number of ROB writes
system.cpu.timesIdled 1828 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 38945 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 90599356 # Number of Instructions Simulated
system.cpu.committedOps 91249910 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 90599356 # Number of Instructions Simulated
system.cpu.cpi 0.573710 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.573710 # CPI: Total CPI of All Threads
system.cpu.ipc 1.743042 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.743042 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 497076309 # number of integer regfile reads
system.cpu.int_regfile_writes 120895703 # number of integer regfile writes
system.cpu.fp_regfile_reads 198 # number of floating regfile reads
system.cpu.fp_regfile_writes 527 # number of floating regfile writes
system.cpu.misc_regfile_reads 183813486 # number of misc regfile reads
system.cpu.misc_regfile_writes 11604 # number of misc regfile writes
system.cpu.icache.replacements 3 # number of replacements
system.cpu.icache.tagsinuse 649.670012 # Cycle average of tags in use
system.cpu.icache.total_refs 14155750 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 749 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 18899.532710 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 649.670012 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.317222 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.317222 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 14155750 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 14155750 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 14155750 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 14155750 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 14155750 # number of overall hits
system.cpu.icache.overall_hits::total 14155750 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 972 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 972 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 972 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 972 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 972 # number of overall misses
system.cpu.icache.overall_misses::total 972 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 33892500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 33892500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 33892500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 33892500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 33892500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 33892500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 14156722 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 14156722 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 14156722 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 14156722 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 14156722 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 14156722 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000069 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000069 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000069 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000069 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000069 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000069 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34868.827160 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 34868.827160 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 34868.827160 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 34868.827160 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 34868.827160 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 34868.827160 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 223 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 223 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 223 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 223 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 223 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 223 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 749 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 749 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 749 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 749 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 749 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 749 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25625000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 25625000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25625000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 25625000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25625000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 25625000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000053 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000053 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000053 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34212.283044 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 34212.283044 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34212.283044 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 34212.283044 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34212.283044 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 34212.283044 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 943602 # number of replacements
system.cpu.dcache.tagsinuse 3646.405021 # Cycle average of tags in use
system.cpu.dcache.total_refs 28436874 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 947698 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 30.006261 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 8214901000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 3646.405021 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.890236 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.890236 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 23866253 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 23866253 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 4558926 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 4558926 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 5898 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 5898 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 5797 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 5797 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 28425179 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 28425179 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 28425179 # number of overall hits
system.cpu.dcache.overall_hits::total 28425179 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 1004103 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 1004103 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 176055 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 176055 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 8 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 8 # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data 1180158 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 1180158 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 1180158 # number of overall misses
system.cpu.dcache.overall_misses::total 1180158 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 5784178500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 5784178500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 4612267011 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 4612267011 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 129000 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 129000 # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 10396445511 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 10396445511 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 10396445511 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 10396445511 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 24870356 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 24870356 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5906 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 5906 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 5797 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 5797 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 29605337 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 29605337 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 29605337 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 29605337 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040373 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.040373 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037182 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.037182 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001355 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001355 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.039863 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.039863 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.039863 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.039863 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 5760.542992 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 5760.542992 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26197.875726 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 26197.875726 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16125 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16125 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 8809.367484 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 8809.367484 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 8809.367484 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 8809.367484 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 23104055 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 8078 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 2860.120698 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 942908 # number of writebacks
system.cpu.dcache.writebacks::total 942908 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 99918 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 99918 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 132542 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 132542 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 8 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 8 # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 232460 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 232460 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 232460 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 232460 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 904185 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 904185 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43513 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 43513 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 947698 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 947698 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 947698 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 947698 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2402147500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2402147500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1077084130 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 1077084130 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 3479231630 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 3479231630 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 3479231630 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 3479231630 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036356 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036356 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009190 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009190 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032011 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.032011 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032011 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.032011 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 2656.699127 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 2656.699127 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24753.157217 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24753.157217 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 3671.245091 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 3671.245091 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 3671.245091 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 3671.245091 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 770 # number of replacements
system.cpu.l2cache.tagsinuse 10017.166349 # Cycle average of tags in use
system.cpu.l2cache.total_refs 1600694 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 15595 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 102.641488 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 9634.775304 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 182.147356 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 200.243688 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.294030 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.005559 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.006111 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.305700 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 27 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 902746 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 902773 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 942908 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 942908 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 30054 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 30054 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst 27 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 932800 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 932827 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 27 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 932800 # number of overall hits
system.cpu.l2cache.overall_hits::total 932827 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 722 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 364 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 1086 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 14534 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 14534 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 722 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 14898 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 15620 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 722 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 14898 # number of overall misses
system.cpu.l2cache.overall_misses::total 15620 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 24755500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 12471500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 37227000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 499277500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 499277500 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 24755500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 511749000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 536504500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 24755500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 511749000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 536504500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 749 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 903110 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 903859 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 942908 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 942908 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 44588 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 44588 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 749 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 947698 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 948447 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 749 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 947698 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 948447 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.963952 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000403 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.001202 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.325962 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.325962 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.963952 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.015720 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.016469 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.963952 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.015720 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.016469 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34287.396122 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34262.362637 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 34279.005525 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34352.380625 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34352.380625 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34287.396122 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34350.181232 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 34347.279129 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34287.396122 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34350.181232 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 34347.279129 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks 32 # number of writebacks
system.cpu.l2cache.writebacks::total 32 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 9 # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total 10 # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data 9 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total 10 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data 9 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total 10 # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 721 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 355 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 1076 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14534 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 14534 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 721 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 14889 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 15610 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 721 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 14889 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 15610 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 22414000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 11074500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 33488500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 452032500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 452032500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22414000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 463107000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 485521000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22414000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 463107000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 485521000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.962617 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000393 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001190 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.325962 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.325962 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.962617 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015711 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.016458 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.962617 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015711 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.016458 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31087.378641 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31195.774648 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31123.141264 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31101.726985 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31101.726985 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31087.378641 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31103.969373 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31103.203075 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31087.378641 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31103.969373 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31103.203075 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

4
simulators/gem5/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/chair.cook.ppm Normal file
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P6
15 15
255


135
simulators/gem5/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini Normal file
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[root]
type=Root
children=system
full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
boot_osflags=a
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
readfile=
symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.cpu]
type=AtomicSimpleCPU
children=dtb interrupts itb tracer workload
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
fastmem=false
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
phase=0
profile=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
system=system
tracer=system.cpu.tracer
width=1
workload=system.cpu.workload
dcache_port=system.membus.slave[2]
icache_port=system.membus.slave[1]
[system.cpu.dtb]
type=ArmTLB
children=walker
size=64
walker=system.cpu.dtb.walker
[system.cpu.dtb.walker]
type=ArmTableWalker
max_backoff=100000
min_backoff=0
sys=system
port=system.membus.slave[4]
[system.cpu.interrupts]
type=ArmInterrupts
[system.cpu.itb]
type=ArmTLB
children=walker
size=64
walker=system.cpu.itb.walker
[system.cpu.itb.walker]
type=ArmTableWalker
max_backoff=100000
min_backoff=0
sys=system
port=system.membus.slave[3]
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=mcf mcf.in
cwd=build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-atomic
egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/cpu2000/binaries/arm/linux/mcf
gid=100
input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=55300000000
system=system
uid=100
[system.membus]
type=CoherentBus
block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
master=system.physmem.port[0]
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port
[system.physmem]
type=SimpleMemory
conf_table_reported=false
file=
in_addr_map=true
latency=30000
latency_var=0
null=false
range=0:268435455
zero=false
port=system.membus.master[0]

999
simulators/gem5/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/mcf.out Normal file
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228
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298
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227
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415
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226
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264
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224
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232
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222
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233
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217
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250
()
211
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331
()
210
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394
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209
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410
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208
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321
()
207
***
327
()
206
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309
()
199
***
259
()
198
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219
()
197
***
220
()
195
***
429
()
194
***
470
()
193
***
274
()
191
***
203
()
190
***
263
()
189
215
***
230
()
188
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266
***
295
()
182
***
329
()
181
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351
()
180
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441
()
179
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453
()
178
***
418
()
177
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353
()
176
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422
()
175
***
225
***
255
()
174
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269
()
173
***
214
()
172
***
186
()
171
***
447
()
170
***
270
***
306
()
169
***
336
()
168
***
285
()
165
***
249
()
146
***
154
()
143
***
334
()
142
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216
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257
()
141
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167
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251
()
140
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293
()
139
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158
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137
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166
***
201
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136
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160
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129
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235
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127
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126
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218
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125
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123
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116
***
135
***
163
()
115
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133
***
204
***
248
()
114
***
192
***
212
()
113
***
268
()
112
***
367
()
111
***
272
()
110
***
434
()
109
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323
()
108
***
281
()
107
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144
***
148
()
106
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275
()
105
***
196
***
254
()
104
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138
***
161
()
103
***
310
()
102
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223
***
252
()
80
()
70
()
69
()
68
()
66
()
64
()
62
***
256
()
61
***
93
()
59
***
120
()
58
()
57
***
183
()
55
()
54
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52
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147
()
51
***
118
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50
***
83
()
49
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98
()
48
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99
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47
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46
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184
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121
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44
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43
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88
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91
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96
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100
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149
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258
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32
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94
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84
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78
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73
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81
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65
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16
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101
()
15
***
71
()
14
***
75
()
13
***
322
()
12
***
77
()
11
***
283
()
10
***
79
()
9
***
145
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150
()
8
***
67
()
7
***
60
***
231
()
6
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56
***
234
()
5
***
164
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202
()
4
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53
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3
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130
***
185
***
200
()
2
***
205
()
1
***
39
***
95

2
simulators/gem5/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simerr Executable file
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@ -0,0 +1,2 @@
warn: Sockets disabled, not accepting gdb connections
hack: be nice to actually delete the event here

26
simulators/gem5/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simout Executable file
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gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 4 2012 12:14:06
gem5 started Jun 4 2012 17:36:14
gem5 executing on zizzer
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
MCF SPEC version 1.6.I
by Andreas Loebel
Copyright (c) 1998,1999 ZIB Berlin
All Rights Reserved.
nodes : 500
active arcs : 1905
simplex iterations : 1502
flow value : 4990014995
new implicit arcs : 23867
active arcs : 25772
simplex iterations : 2663
flow value : 3080014995
checksum : 68389
optimal
Exiting @ tick 54240666000 because target called exit()

102
simulators/gem5/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt Normal file
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---------- Begin Simulation Statistics ----------
sim_seconds 0.054241 # Number of seconds simulated
sim_ticks 54240666000 # Number of ticks simulated
final_tick 54240666000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 2223712 # Simulator instruction rate (inst/s)
host_op_rate 2239678 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1331261387 # Simulator tick rate (ticks/s)
host_mem_usage 354056 # Number of bytes of host memory used
host_seconds 40.74 # Real time elapsed on the host
sim_insts 90602415 # Number of instructions simulated
sim_ops 91252969 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 431323116 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 90016599 # Number of bytes read from this memory
system.physmem.bytes_read::total 521339715 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 431323116 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 431323116 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 18908138 # Number of bytes written to this memory
system.physmem.bytes_written::total 18908138 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 107830779 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 22553295 # Number of read requests responded to by this memory
system.physmem.num_reads::total 130384074 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 4738868 # Number of write requests responded to by this memory
system.physmem.num_writes::total 4738868 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 7952024704 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 1659577687 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 9611602391 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 7952024704 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 7952024704 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 348597084 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 348597084 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 7952024704 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2008174771 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 9960199475 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 442 # Number of system calls
system.cpu.numCycles 108481333 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 90602415 # Number of instructions committed
system.cpu.committedOps 91252969 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 72525682 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 48 # Number of float alu accesses
system.cpu.num_func_calls 96832 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 15548926 # number of instructions that are conditional controls
system.cpu.num_int_insts 72525682 # number of integer instructions
system.cpu.num_fp_insts 48 # number of float instructions
system.cpu.num_int_register_reads 396912516 # number of times the integer registers were read
system.cpu.num_int_register_writes 106840370 # number of times the integer registers were written
system.cpu.num_fp_register_reads 54 # number of times the floating registers were read
system.cpu.num_fp_register_writes 30 # number of times the floating registers were written
system.cpu.num_mem_refs 27318811 # number of memory refs
system.cpu.num_load_insts 22573967 # Number of load instructions
system.cpu.num_store_insts 4744844 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 108481333 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
---------- End Simulation Statistics ----------

4
simulators/gem5/tests/long/se/10.mcf/ref/arm/linux/simple-timing/chair.cook.ppm Normal file
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P6
15 15
255


216
simulators/gem5/tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini Normal file
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[root]
type=Root
children=system
full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
boot_osflags=a
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
readfile=
symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.cpu]
type=TimingSimpleCPU
children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
phase=0
profile=0
progress_interval=0
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=262144
subblock_size=0
system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
[system.cpu.dtb]
type=ArmTLB
children=walker
size=64
walker=system.cpu.dtb.walker
[system.cpu.dtb.walker]
type=ArmTableWalker
max_backoff=100000
min_backoff=0
sys=system
port=system.cpu.toL2Bus.slave[3]
[system.cpu.icache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=131072
subblock_size=0
system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.interrupts]
type=ArmInterrupts
[system.cpu.itb]
type=ArmTLB
children=walker
size=64
walker=system.cpu.itb.walker
[system.cpu.itb.walker]
type=ArmTableWalker
max_backoff=100000
min_backoff=0
sys=system
port=system.cpu.toL2Bus.slave[2]
[system.cpu.l2cache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=false
latency=10000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=2097152
subblock_size=0
system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
[system.cpu.toL2Bus]
type=CoherentBus
block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=mcf mcf.in
cwd=build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-timing
egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/cpu2000/binaries/arm/linux/mcf
gid=100
input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=55300000000
system=system
uid=100
[system.membus]
type=CoherentBus
block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
master=system.physmem.port[0]
slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=SimpleMemory
conf_table_reported=false
file=
in_addr_map=true
latency=30000
latency_var=0
null=false
range=0:268435455
zero=false
port=system.membus.master[0]

999
simulators/gem5/tests/long/se/10.mcf/ref/arm/linux/simple-timing/mcf.out Normal file
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()
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***
497
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***
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317
***
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***
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***
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***
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***
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***
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***
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***
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***
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***
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***
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***
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***
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***
326
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284
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***
308
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279
***
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***
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277
***
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***
296
()
273
()
271
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265
()
246
***
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()
245
***
280
()
244
***
391
()
243
***
330
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242
***
456
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241
***
346
()
240
***
483
()
239
***
260
()
238
***
261
()
237
***
262
***
294
()
236
***
253
()
229
***
397
()
228
***
298
()
227
***
415
()
226
***
264
()
224
***
232
()
222
***
233
()
217
***
250
()
211
***
331
()
210
***
394
()
209
***
410
()
208
***
321
()
207
***
327
()
206
***
309
()
199
***
259
()
198
***
219
()
197
***
220
()
195
***
429
()
194
***
470
()
193
***
274
()
191
***
203
()
190
***
263
()
189
215
***
230
()
188
***
266
***
295
()
182
***
329
()
181
***
351
()
180
***
441
()
179
***
453
()
178
***
418
()
177
***
353
()
176
***
422
()
175
***
225
***
255
()
174
***
269
()
173
***
214
()
172
***
186
()
171
***
447
()
170
***
270
***
306
()
169
***
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***
285
()
165
***
249
()
146
***
154
()
143
***
334
()
142
***
216
***
257
()
141
***
167
***
251
()
140
***
162
***
293
()
139
***
158
()
137
***
166
***
201
()
136
***
160
()
134
***
221
()
132
***
213
()
131
***
187
()
129
***
235
()
128
***
153
()
127
***
156
()
126
***
159
***
218
()
125
***
155
()
124
***
157
()
123
***
152
()
116
***
135
***
163
()
115
***
133
***
204
***
248
()
114
***
192
***
212
()
113
***
268
()
112
***
367
()
111
***
272
()
110
***
434
()
109
***
323
()
108
***
281
()
107
***
144
***
148
()
106
***
275
()
105
***
196
***
254
()
104
***
138
***
161
()
103
***
310
()
102
***
223
***
252
()
80
()
70
()
69
()
68
()
66
()
64
()
62
***
256
()
61
***
93
()
59
***
120
()
58
()
57
***
183
()
55
()
54
()
52
***
147
()
51
***
118
()
50
***
83
()
49
***
98
()
48
***
99
()
47
()
46
***
184
()
45
***
121
()
44
()
43
***
88
()
42
***
122
()
41
***
91
()
40
***
96
()
38
***
100
()
37
***
149
()
36
***
74
()
35
***
258
()
34
***
151
()
33
***
85
()
32
()
31
***
94
()
30
***
97
()
29
***
90
()
28
***
89
()
27
***
92
()
26
***
72
***
247
()
25
***
86
()
24
***
82
()
23
***
87
***
117
()
22
***
76
***
119
()
21
***
84
()
20
***
78
()
19
***
73
()
18
***
81
()
17
***
65
()
16
***
63
***
101
()
15
***
71
()
14
***
75
()
13
***
322
()
12
***
77
()
11
***
283
()
10
***
79
()
9
***
145
***
150
()
8
***
67
()
7
***
60
***
231
()
6
***
56
***
234
()
5
***
164
***
202
()
4
***
53
()
3
***
130
***
185
***
200
()
2
***
205
()
1
***
39
***
95

2
simulators/gem5/tests/long/se/10.mcf/ref/arm/linux/simple-timing/simerr Executable file
View File

@ -0,0 +1,2 @@
warn: Sockets disabled, not accepting gdb connections
hack: be nice to actually delete the event here

26
simulators/gem5/tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout Executable file
View File

@ -0,0 +1,26 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 4 2012 12:14:06
gem5 started Jun 4 2012 17:37:05
gem5 executing on zizzer
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
MCF SPEC version 1.6.I
by Andreas Loebel
Copyright (c) 1998,1999 ZIB Berlin
All Rights Reserved.
nodes : 500
active arcs : 1905
simplex iterations : 1502
flow value : 4990014995
new implicit arcs : 23867
active arcs : 25772
simplex iterations : 2663
flow value : 3080014995
checksum : 68389
optimal
Exiting @ tick 148086239000 because target called exit()

427
simulators/gem5/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt Normal file
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@ -0,0 +1,427 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.148086 # Number of seconds simulated
sim_ticks 148086239000 # Number of ticks simulated
final_tick 148086239000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1056603 # Simulator instruction rate (inst/s)
host_op_rate 1064179 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1727464138 # Simulator tick rate (ticks/s)
host_mem_usage 363220 # Number of bytes of host memory used
host_seconds 85.72 # Real time elapsed on the host
sim_insts 90576869 # Number of instructions simulated
sim_ops 91226321 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 36992 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 949120 # Number of bytes read from this memory
system.physmem.bytes_read::total 986112 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 36992 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 36992 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 2048 # Number of bytes written to this memory
system.physmem.bytes_written::total 2048 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 578 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 14830 # Number of read requests responded to by this memory
system.physmem.num_reads::total 15408 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 32 # Number of write requests responded to by this memory
system.physmem.num_writes::total 32 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 249800 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 6409238 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 6659039 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 249800 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 249800 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 13830 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 13830 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 13830 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 249800 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 6409238 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 6672869 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 442 # Number of system calls
system.cpu.numCycles 296172478 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 90576869 # Number of instructions committed
system.cpu.committedOps 91226321 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 72525682 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 48 # Number of float alu accesses
system.cpu.num_func_calls 96832 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 15548926 # number of instructions that are conditional controls
system.cpu.num_int_insts 72525682 # number of integer instructions
system.cpu.num_fp_insts 48 # number of float instructions
system.cpu.num_int_register_reads 464563396 # number of times the integer registers were read
system.cpu.num_int_register_writes 106840370 # number of times the integer registers were written
system.cpu.num_fp_register_reads 54 # number of times the floating registers were read
system.cpu.num_fp_register_writes 30 # number of times the floating registers were written
system.cpu.num_mem_refs 27318811 # number of memory refs
system.cpu.num_load_insts 22573967 # Number of load instructions
system.cpu.num_store_insts 4744844 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 296172478 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.icache.replacements 2 # number of replacements
system.cpu.icache.tagsinuse 510.335448 # Cycle average of tags in use
system.cpu.icache.total_refs 107830181 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 599 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 180016.996661 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 510.335448 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.249187 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.249187 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 107830181 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 107830181 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 107830181 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 107830181 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 107830181 # number of overall hits
system.cpu.icache.overall_hits::total 107830181 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 599 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 599 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 599 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 599 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 599 # number of overall misses
system.cpu.icache.overall_misses::total 599 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 32662000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 32662000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 32662000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 32662000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 32662000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 32662000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 107830780 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 107830780 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 107830780 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 107830780 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 107830780 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 107830780 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000006 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000006 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000006 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000006 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000006 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000006 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54527.545910 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 54527.545910 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 54527.545910 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 54527.545910 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 54527.545910 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 54527.545910 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 599 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 599 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 599 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 599 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 599 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 599 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 30865000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 30865000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 30865000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 30865000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 30865000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 30865000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000006 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000006 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000006 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51527.545910 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51527.545910 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51527.545910 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 51527.545910 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51527.545910 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 51527.545910 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 942702 # number of replacements
system.cpu.dcache.tagsinuse 3568.549501 # Cycle average of tags in use
system.cpu.dcache.total_refs 26345365 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 946798 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 27.825751 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 54479156000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 3568.549501 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.871228 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.871228 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 21649219 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 21649219 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 4688372 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 4688372 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 3887 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 3887 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 26337591 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 26337591 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 26337591 # number of overall hits
system.cpu.dcache.overall_hits::total 26337591 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 900189 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 900189 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 46609 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 46609 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 946798 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 946798 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 946798 # number of overall misses
system.cpu.dcache.overall_misses::total 946798 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 12614490000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 12614490000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 1263542000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 1263542000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 13878032000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 13878032000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 13878032000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 13878032000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 22549408 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 22549408 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 27284389 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 27284389 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 27284389 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 27284389 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.039921 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.039921 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.009844 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.009844 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.034701 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.034701 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.034701 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.034701 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14013.157237 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 14013.157237 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27109.399472 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 27109.399472 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 14657.859438 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 14657.859438 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 14657.859438 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 14657.859438 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 942309 # number of writebacks
system.cpu.dcache.writebacks::total 942309 # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 900189 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 900189 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46609 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 46609 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 946798 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 946798 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 946798 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 946798 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9913923000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 9913923000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1123715000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 1123715000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11037638000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 11037638000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11037638000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 11037638000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.039921 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.039921 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009844 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009844 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034701 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.034701 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034701 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.034701 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11013.157237 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11013.157237 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24109.399472 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24109.399472 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11657.859438 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 11657.859438 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11657.859438 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 11657.859438 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 634 # number of replacements
system.cpu.l2cache.tagsinuse 9235.307693 # Cycle average of tags in use
system.cpu.l2cache.total_refs 1594542 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 15392 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 103.595504 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 8910.209882 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 165.071875 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 160.025936 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.271918 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.005038 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.004884 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.281839 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 21 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 899907 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 899928 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 942309 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 942309 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 32061 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 32061 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst 21 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 931968 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 931989 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 21 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 931968 # number of overall hits
system.cpu.l2cache.overall_hits::total 931989 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 578 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 282 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 860 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 14548 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 14548 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 578 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 14830 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 15408 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 578 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 14830 # number of overall misses
system.cpu.l2cache.overall_misses::total 15408 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 30056000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 14664000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 44720000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 756496000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 756496000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 30056000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 771160000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 801216000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 30056000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 771160000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 801216000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 599 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 900189 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 900788 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 942309 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 942309 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 46609 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 46609 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 599 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 946798 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 947397 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 599 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 946798 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 947397 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.964942 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000313 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.000955 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.312129 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.312129 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.964942 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.015663 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.016264 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.964942 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.015663 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.016264 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks 32 # number of writebacks
system.cpu.l2cache.writebacks::total 32 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 578 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 282 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 860 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14548 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 14548 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 578 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 14830 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 15408 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 578 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 14830 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 15408 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 23120000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 11280000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 34400000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 581920000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 581920000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 23120000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 593200000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 616320000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 23120000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 593200000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 616320000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.964942 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000313 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000955 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.312129 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.312129 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.964942 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015663 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.016264 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.964942 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015663 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.016264 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

117
simulators/gem5/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini Normal file
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[root]
type=Root
children=system
full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
boot_osflags=a
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
readfile=
symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.cpu]
type=AtomicSimpleCPU
children=dtb interrupts itb tracer workload
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
fastmem=false
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
phase=0
profile=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
system=system
tracer=system.cpu.tracer
width=1
workload=system.cpu.workload
dcache_port=system.membus.slave[2]
icache_port=system.membus.slave[1]
[system.cpu.dtb]
type=SparcTLB
size=64
[system.cpu.interrupts]
type=SparcInterrupts
[system.cpu.itb]
type=SparcTLB
size=64
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=mcf mcf.in
cwd=build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-atomic
egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/cpu2000/binaries/sparc/linux/mcf
gid=100
input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=55300000000
system=system
uid=100
[system.membus]
type=CoherentBus
block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
master=system.physmem.port[0]
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
[system.physmem]
type=SimpleMemory
conf_table_reported=false
file=
in_addr_map=true
latency=30000
latency_var=0
null=false
range=0:268435455
zero=false
port=system.membus.master[0]

999
simulators/gem5/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/mcf.out Normal file
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95

3
simulators/gem5/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simerr Executable file
View File

@ -0,0 +1,3 @@
warn: CoherentBus system.membus has no snooping ports attached!
warn: Sockets disabled, not accepting gdb connections
hack: be nice to actually delete the event here

26
simulators/gem5/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simout Executable file
View File

@ -0,0 +1,26 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 4 2012 12:01:47
gem5 started Jun 4 2012 14:53:37
gem5 executing on zizzer
command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
MCF SPEC version 1.6.I
by Andreas Loebel
Copyright (c) 1998,1999 ZIB Berlin
All Rights Reserved.
nodes : 500
active arcs : 1905
simplex iterations : 1502
flow value : 4990014995
new implicit arcs : 23867
active arcs : 25772
simplex iterations : 2663
flow value : 3080014995
checksum : 68389
optimal
Exiting @ tick 122215830000 because target called exit()

62
simulators/gem5/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt Normal file
View File

@ -0,0 +1,62 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.122216 # Number of seconds simulated
sim_ticks 122215830000 # Number of ticks simulated
final_tick 122215830000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 2951739 # Simulator instruction rate (inst/s)
host_op_rate 2951861 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1479540198 # Simulator tick rate (ticks/s)
host_mem_usage 346528 # Number of bytes of host memory used
host_seconds 82.60 # Real time elapsed on the host
sim_insts 243825163 # Number of instructions simulated
sim_ops 243835278 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 977686044 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 328674009 # Number of bytes read from this memory
system.physmem.bytes_read::total 1306360053 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 977686044 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 977686044 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 91606089 # Number of bytes written to this memory
system.physmem.bytes_written::total 91606089 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 244421511 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 82220434 # Number of read requests responded to by this memory
system.physmem.num_reads::total 326641945 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 22901951 # Number of write requests responded to by this memory
system.physmem.num_writes::total 22901951 # Number of write requests responded to by this memory
system.physmem.num_other::cpu.data 3886 # Number of other requests responded to by this memory
system.physmem.num_other::total 3886 # Number of other requests responded to by this memory
system.physmem.bw_read::cpu.inst 7999667834 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 2689291633 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 10688959466 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 7999667834 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 7999667834 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 749543566 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 749543566 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 7999667834 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 3438835198 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 11438503032 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 443 # Number of system calls
system.cpu.numCycles 244431661 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 243825163 # Number of instructions committed
system.cpu.committedOps 243835278 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 194726506 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 11630 # Number of float alu accesses
system.cpu.num_func_calls 4252956 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 18619960 # number of instructions that are conditional controls
system.cpu.num_int_insts 194726506 # number of integer instructions
system.cpu.num_fp_insts 11630 # number of float instructions
system.cpu.num_int_register_reads 456819010 # number of times the integer registers were read
system.cpu.num_int_register_writes 215451567 # number of times the integer registers were written
system.cpu.num_fp_register_reads 23256 # number of times the floating registers were read
system.cpu.num_fp_register_writes 90 # number of times the floating registers were written
system.cpu.num_mem_refs 105711442 # number of memory refs
system.cpu.num_load_insts 82803522 # Number of load instructions
system.cpu.num_store_insts 22907920 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 244431661 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
---------- End Simulation Statistics ----------

198
simulators/gem5/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini Normal file
View File

@ -0,0 +1,198 @@
[root]
type=Root
children=system
full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
boot_osflags=a
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
readfile=
symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.cpu]
type=TimingSimpleCPU
children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
phase=0
profile=0
progress_interval=0
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=262144
subblock_size=0
system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
[system.cpu.dtb]
type=SparcTLB
size=64
[system.cpu.icache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=131072
subblock_size=0
system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.interrupts]
type=SparcInterrupts
[system.cpu.itb]
type=SparcTLB
size=64
[system.cpu.l2cache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=false
latency=10000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=2097152
subblock_size=0
system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
[system.cpu.toL2Bus]
type=CoherentBus
block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=mcf mcf.in
cwd=build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-timing
egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/cpu2000/binaries/sparc/linux/mcf
gid=100
input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=55300000000
system=system
uid=100
[system.membus]
type=CoherentBus
block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
master=system.physmem.port[0]
slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=SimpleMemory
conf_table_reported=false
file=
in_addr_map=true
latency=30000
latency_var=0
null=false
range=0:268435455
zero=false
port=system.membus.master[0]

999
simulators/gem5/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/mcf.out Normal file
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6
***
56
***
234
()
5
***
164
***
202
()
4
***
53
()
3
***
130
***
185
***
200
()
2
***
205
()
1
***
39
***
95

2
simulators/gem5/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simerr Executable file
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@ -0,0 +1,2 @@
warn: Sockets disabled, not accepting gdb connections
hack: be nice to actually delete the event here

26
simulators/gem5/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout Executable file
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gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 4 2012 12:01:47
gem5 started Jun 4 2012 14:55:10
gem5 executing on zizzer
command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
MCF SPEC version 1.6.I
by Andreas Loebel
Copyright (c) 1998,1999 ZIB Berlin
All Rights Reserved.
nodes : 500
active arcs : 1905
simplex iterations : 1502
flow value : 4990014995
new implicit arcs : 23867
active arcs : 25772
simplex iterations : 2663
flow value : 3080014995
checksum : 68389
optimal
Exiting @ tick 362430887000 because target called exit()

397
simulators/gem5/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt Normal file
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---------- Begin Simulation Statistics ----------
sim_seconds 0.362431 # Number of seconds simulated
sim_ticks 362430887000 # Number of ticks simulated
final_tick 362430887000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1267775 # Simulator instruction rate (inst/s)
host_op_rate 1267827 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1884467398 # Simulator tick rate (ticks/s)
host_mem_usage 355400 # Number of bytes of host memory used
host_seconds 192.33 # Real time elapsed on the host
sim_insts 243825163 # Number of instructions simulated
sim_ops 243835278 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 56256 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 945216 # Number of bytes read from this memory
system.physmem.bytes_read::total 1001472 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 56256 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 56256 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 2560 # Number of bytes written to this memory
system.physmem.bytes_written::total 2560 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 879 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 14769 # Number of read requests responded to by this memory
system.physmem.num_reads::total 15648 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 40 # Number of write requests responded to by this memory
system.physmem.num_writes::total 40 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 155219 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 2607990 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 2763208 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 155219 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 155219 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 7063 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 7063 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 7063 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 155219 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2607990 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 2770272 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 443 # Number of system calls
system.cpu.numCycles 724861774 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 243825163 # Number of instructions committed
system.cpu.committedOps 243835278 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 194726506 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 11630 # Number of float alu accesses
system.cpu.num_func_calls 4252956 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 18619960 # number of instructions that are conditional controls
system.cpu.num_int_insts 194726506 # number of integer instructions
system.cpu.num_fp_insts 11630 # number of float instructions
system.cpu.num_int_register_reads 456819010 # number of times the integer registers were read
system.cpu.num_int_register_writes 215451566 # number of times the integer registers were written
system.cpu.num_fp_register_reads 23256 # number of times the floating registers were read
system.cpu.num_fp_register_writes 90 # number of times the floating registers were written
system.cpu.num_mem_refs 105711442 # number of memory refs
system.cpu.num_load_insts 82803522 # Number of load instructions
system.cpu.num_store_insts 22907920 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 724861774 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.icache.replacements 25 # number of replacements
system.cpu.icache.tagsinuse 725.567632 # Cycle average of tags in use
system.cpu.icache.total_refs 244420630 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 882 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 277120.895692 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 725.567632 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.354281 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.354281 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 244420630 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 244420630 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 244420630 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 244420630 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 244420630 # number of overall hits
system.cpu.icache.overall_hits::total 244420630 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 882 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 882 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 882 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 882 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 882 # number of overall misses
system.cpu.icache.overall_misses::total 882 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 49266000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 49266000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 49266000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 49266000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 49266000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 49266000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 244421512 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 244421512 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 244421512 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 244421512 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 244421512 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 244421512 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55857.142857 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 55857.142857 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 55857.142857 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 55857.142857 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 55857.142857 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 55857.142857 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 882 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 882 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 882 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 882 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 882 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 882 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 46620000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 46620000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 46620000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 46620000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 46620000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 46620000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52857.142857 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52857.142857 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52857.142857 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 52857.142857 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52857.142857 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 52857.142857 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 935475 # number of replacements
system.cpu.dcache.tagsinuse 3563.824259 # Cycle average of tags in use
system.cpu.dcache.total_refs 104186700 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 939571 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 110.887522 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 134373316000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 3563.824259 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.870074 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.870074 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 81327577 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 81327577 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 22855241 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 22855241 # number of WriteReq hits
system.cpu.dcache.SwapReq_hits::cpu.data 3882 # number of SwapReq hits
system.cpu.dcache.SwapReq_hits::total 3882 # number of SwapReq hits
system.cpu.dcache.demand_hits::cpu.data 104182818 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 104182818 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 104182818 # number of overall hits
system.cpu.dcache.overall_hits::total 104182818 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 892857 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 892857 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 46710 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 46710 # number of WriteReq misses
system.cpu.dcache.SwapReq_misses::cpu.data 4 # number of SwapReq misses
system.cpu.dcache.SwapReq_misses::total 4 # number of SwapReq misses
system.cpu.dcache.demand_misses::cpu.data 939567 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 939567 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 939567 # number of overall misses
system.cpu.dcache.overall_misses::total 939567 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 12508482000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 12508482000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 1265712000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 1265712000 # number of WriteReq miss cycles
system.cpu.dcache.SwapReq_miss_latency::cpu.data 98000 # number of SwapReq miss cycles
system.cpu.dcache.SwapReq_miss_latency::total 98000 # number of SwapReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 13774194000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 13774194000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 13774194000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 13774194000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 82220434 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 82220434 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 22901951 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 22901951 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SwapReq_accesses::cpu.data 3886 # number of SwapReq accesses(hits+misses)
system.cpu.dcache.SwapReq_accesses::total 3886 # number of SwapReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 105122385 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 105122385 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 105122385 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 105122385 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.010859 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.010859 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002040 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.002040 # miss rate for WriteReq accesses
system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.001029 # miss rate for SwapReq accesses
system.cpu.dcache.SwapReq_miss_rate::total 0.001029 # miss rate for SwapReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.008938 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.008938 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.008938 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.008938 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14009.502082 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 14009.502082 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27097.238279 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 27097.238279 # average WriteReq miss latency
system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 24500 # average SwapReq miss latency
system.cpu.dcache.SwapReq_avg_miss_latency::total 24500 # average SwapReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 14660.150899 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 14660.150899 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 14660.150899 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 14660.150899 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 935237 # number of writebacks
system.cpu.dcache.writebacks::total 935237 # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 892857 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 892857 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46710 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 46710 # number of WriteReq MSHR misses
system.cpu.dcache.SwapReq_mshr_misses::cpu.data 4 # number of SwapReq MSHR misses
system.cpu.dcache.SwapReq_mshr_misses::total 4 # number of SwapReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 939567 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 939567 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 939567 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 939567 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9829911000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 9829911000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1125582000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 1125582000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 86000 # number of SwapReq MSHR miss cycles
system.cpu.dcache.SwapReq_mshr_miss_latency::total 86000 # number of SwapReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10955493000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 10955493000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10955493000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 10955493000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.010859 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.010859 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002040 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002040 # mshr miss rate for WriteReq accesses
system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.001029 # mshr miss rate for SwapReq accesses
system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.001029 # mshr miss rate for SwapReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.008938 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.008938 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.008938 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.008938 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11009.502082 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11009.502082 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24097.238279 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24097.238279 # average WriteReq mshr miss latency
system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 21500 # average SwapReq mshr miss latency
system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 21500 # average SwapReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11660.150899 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 11660.150899 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11660.150899 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 11660.150899 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 865 # number of replacements
system.cpu.l2cache.tagsinuse 9236.752232 # Cycle average of tags in use
system.cpu.l2cache.total_refs 1585884 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 15631 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 101.457616 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 8861.245791 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 244.574580 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 130.931861 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.270424 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.007464 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.003996 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.281883 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 3 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 892655 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 892658 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 935237 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 935237 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 32147 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 32147 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 924802 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 924805 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 3 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 924802 # number of overall hits
system.cpu.l2cache.overall_hits::total 924805 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 879 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 202 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 1081 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 14567 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 14567 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 879 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 14769 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 15648 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 879 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 14769 # number of overall misses
system.cpu.l2cache.overall_misses::total 15648 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 45708000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 10504000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 56212000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 757484000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 757484000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 45708000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 767988000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 813696000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 45708000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 767988000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 813696000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 882 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 892857 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 893739 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 935237 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 935237 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 46714 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 46714 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 882 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 939571 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 940453 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 882 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 939571 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 940453 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996599 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000226 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.001210 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.311834 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.311834 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996599 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.015719 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.016639 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996599 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.015719 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.016639 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks 40 # number of writebacks
system.cpu.l2cache.writebacks::total 40 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 879 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 202 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 1081 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14567 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 14567 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 879 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 14769 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 15648 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 879 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 14769 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 15648 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 35160000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8080000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 43240000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 582680000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 582680000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 35160000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 590760000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 625920000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 35160000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 590760000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 625920000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000226 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001210 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.311834 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.311834 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015719 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.016639 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015719 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.016639 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

550
simulators/gem5/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini Normal file
View File

@ -0,0 +1,550 @@
[root]
type=Root
children=system
full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
boot_osflags=a
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
readfile=
symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.cpu]
type=DerivO3CPU
children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
LSQDepCheckShift=4
RASSize=16
SQEntries=32
SSITSize=1024
activity=0
backComSize=5
cachePorts=200
checker=Null
choiceCtrBits=2
choicePredictorSize=8192
clock=500
commitToDecodeDelay=1
commitToFetchDelay=1
commitToIEWDelay=1
commitToRenameDelay=1
commitWidth=8
cpu_id=0
decodeToFetchDelay=1
decodeToRenameDelay=1
decodeWidth=8
defer_registration=false
dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
fetchToDecodeDelay=1
fetchTrapLatency=1
fetchWidth=8
forwardComSize=5
fuPool=system.cpu.fuPool
function_trace=false
function_trace_start=0
globalCtrBits=2
globalHistoryBits=13
globalPredictorSize=8192
iewToCommitDelay=1
iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
instShiftAmt=2
interrupts=system.cpu.interrupts
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
localCtrBits=2
localHistoryBits=11
localHistoryTableSize=2048
localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
needsTSO=true
numIQEntries=64
numPhysFloatRegs=256
numPhysIntRegs=256
numROBEntries=192
numRobs=1
numThreads=1
phase=0
predType=tournament
profile=0
progress_interval=0
renameToDecodeDelay=1
renameToFetchDelay=1
renameToIEWDelay=2
renameToROBDelay=1
renameWidth=8
smtCommitPolicy=RoundRobin
smtFetchPolicy=SingleThread
smtIQPolicy=Partitioned
smtIQThreshold=100
smtLSQPolicy=Partitioned
smtLSQThreshold=100
smtNumFetchingThreads=1
smtROBPolicy=Partitioned
smtROBThreshold=100
squashWidth=8
store_set_clear_period=250000
system=system
tracer=system.cpu.tracer
trapLatency=13
wbDepth=1
wbWidth=8
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=262144
subblock_size=0
system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
[system.cpu.dtb]
type=X86TLB
children=walker
size=64
walker=system.cpu.dtb.walker
[system.cpu.dtb.walker]
type=X86PagetableWalker
system=system
port=system.cpu.toL2Bus.slave[3]
[system.cpu.fuPool]
type=FUPool
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
[system.cpu.fuPool.FUList0]
type=FUDesc
children=opList
count=6
opList=system.cpu.fuPool.FUList0.opList
[system.cpu.fuPool.FUList0.opList]
type=OpDesc
issueLat=1
opClass=IntAlu
opLat=1
[system.cpu.fuPool.FUList1]
type=FUDesc
children=opList0 opList1
count=2
opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
[system.cpu.fuPool.FUList1.opList0]
type=OpDesc
issueLat=1
opClass=IntMult
opLat=3
[system.cpu.fuPool.FUList1.opList1]
type=OpDesc
issueLat=19
opClass=IntDiv
opLat=20
[system.cpu.fuPool.FUList2]
type=FUDesc
children=opList0 opList1 opList2
count=4
opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
[system.cpu.fuPool.FUList2.opList0]
type=OpDesc
issueLat=1
opClass=FloatAdd
opLat=2
[system.cpu.fuPool.FUList2.opList1]
type=OpDesc
issueLat=1
opClass=FloatCmp
opLat=2
[system.cpu.fuPool.FUList2.opList2]
type=OpDesc
issueLat=1
opClass=FloatCvt
opLat=2
[system.cpu.fuPool.FUList3]
type=FUDesc
children=opList0 opList1 opList2
count=2
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
[system.cpu.fuPool.FUList3.opList0]
type=OpDesc
issueLat=1
opClass=FloatMult
opLat=4
[system.cpu.fuPool.FUList3.opList1]
type=OpDesc
issueLat=12
opClass=FloatDiv
opLat=12
[system.cpu.fuPool.FUList3.opList2]
type=OpDesc
issueLat=24
opClass=FloatSqrt
opLat=24
[system.cpu.fuPool.FUList4]
type=FUDesc
children=opList
count=0
opList=system.cpu.fuPool.FUList4.opList
[system.cpu.fuPool.FUList4.opList]
type=OpDesc
issueLat=1
opClass=MemRead
opLat=1
[system.cpu.fuPool.FUList5]
type=FUDesc
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
count=4
opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
[system.cpu.fuPool.FUList5.opList00]
type=OpDesc
issueLat=1
opClass=SimdAdd
opLat=1
[system.cpu.fuPool.FUList5.opList01]
type=OpDesc
issueLat=1
opClass=SimdAddAcc
opLat=1
[system.cpu.fuPool.FUList5.opList02]
type=OpDesc
issueLat=1
opClass=SimdAlu
opLat=1
[system.cpu.fuPool.FUList5.opList03]
type=OpDesc
issueLat=1
opClass=SimdCmp
opLat=1
[system.cpu.fuPool.FUList5.opList04]
type=OpDesc
issueLat=1
opClass=SimdCvt
opLat=1
[system.cpu.fuPool.FUList5.opList05]
type=OpDesc
issueLat=1
opClass=SimdMisc
opLat=1
[system.cpu.fuPool.FUList5.opList06]
type=OpDesc
issueLat=1
opClass=SimdMult
opLat=1
[system.cpu.fuPool.FUList5.opList07]
type=OpDesc
issueLat=1
opClass=SimdMultAcc
opLat=1
[system.cpu.fuPool.FUList5.opList08]
type=OpDesc
issueLat=1
opClass=SimdShift
opLat=1
[system.cpu.fuPool.FUList5.opList09]
type=OpDesc
issueLat=1
opClass=SimdShiftAcc
opLat=1
[system.cpu.fuPool.FUList5.opList10]
type=OpDesc
issueLat=1
opClass=SimdSqrt
opLat=1
[system.cpu.fuPool.FUList5.opList11]
type=OpDesc
issueLat=1
opClass=SimdFloatAdd
opLat=1
[system.cpu.fuPool.FUList5.opList12]
type=OpDesc
issueLat=1
opClass=SimdFloatAlu
opLat=1
[system.cpu.fuPool.FUList5.opList13]
type=OpDesc
issueLat=1
opClass=SimdFloatCmp
opLat=1
[system.cpu.fuPool.FUList5.opList14]
type=OpDesc
issueLat=1
opClass=SimdFloatCvt
opLat=1
[system.cpu.fuPool.FUList5.opList15]
type=OpDesc
issueLat=1
opClass=SimdFloatDiv
opLat=1
[system.cpu.fuPool.FUList5.opList16]
type=OpDesc
issueLat=1
opClass=SimdFloatMisc
opLat=1
[system.cpu.fuPool.FUList5.opList17]
type=OpDesc
issueLat=1
opClass=SimdFloatMult
opLat=1
[system.cpu.fuPool.FUList5.opList18]
type=OpDesc
issueLat=1
opClass=SimdFloatMultAcc
opLat=1
[system.cpu.fuPool.FUList5.opList19]
type=OpDesc
issueLat=1
opClass=SimdFloatSqrt
opLat=1
[system.cpu.fuPool.FUList6]
type=FUDesc
children=opList
count=0
opList=system.cpu.fuPool.FUList6.opList
[system.cpu.fuPool.FUList6.opList]
type=OpDesc
issueLat=1
opClass=MemWrite
opLat=1
[system.cpu.fuPool.FUList7]
type=FUDesc
children=opList0 opList1
count=4
opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
[system.cpu.fuPool.FUList7.opList0]
type=OpDesc
issueLat=1
opClass=MemRead
opLat=1
[system.cpu.fuPool.FUList7.opList1]
type=OpDesc
issueLat=1
opClass=MemWrite
opLat=1
[system.cpu.fuPool.FUList8]
type=FUDesc
children=opList
count=1
opList=system.cpu.fuPool.FUList8.opList
[system.cpu.fuPool.FUList8.opList]
type=OpDesc
issueLat=3
opClass=IprAccess
opLat=3
[system.cpu.icache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=131072
subblock_size=0
system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.interrupts]
type=X86LocalApic
int_latency=1000
pio_addr=2305843009213693952
pio_latency=1000
system=system
int_master=system.membus.slave[2]
int_slave=system.membus.master[2]
pio=system.membus.master[1]
[system.cpu.itb]
type=X86TLB
children=walker
size=64
walker=system.cpu.itb.walker
[system.cpu.itb.walker]
type=X86PagetableWalker
system=system
port=system.cpu.toL2Bus.slave[2]
[system.cpu.l2cache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=false
latency=1000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=2097152
subblock_size=0
system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
[system.cpu.toL2Bus]
type=CoherentBus
block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=mcf mcf.in
cwd=build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing
egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/cpu2000/binaries/x86/linux/mcf
gid=100
input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=55300000000
system=system
uid=100
[system.membus]
type=CoherentBus
block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave
slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master
[system.physmem]
type=SimpleMemory
conf_table_reported=false
file=
in_addr_map=true
latency=30000
latency_var=0
null=false
range=0:268435455
zero=false
port=system.membus.master[0]

999
simulators/gem5/tests/long/se/10.mcf/ref/x86/linux/o3-timing/mcf.out Normal file
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95

4
simulators/gem5/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simerr Executable file
View File

@ -0,0 +1,4 @@
warn: Sockets disabled, not accepting gdb connections
warn: instruction 'fnstcw_Mw' unimplemented
warn: instruction 'fldcw_Mw' unimplemented
hack: be nice to actually delete the event here

27
simulators/gem5/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout Executable file
View File

@ -0,0 +1,27 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 4 2012 13:44:28
gem5 started Jun 4 2012 15:14:48
gem5 executing on zizzer
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
MCF SPEC version 1.6.I
by Andreas Loebel
Copyright (c) 1998,1999 ZIB Berlin
All Rights Reserved.
nodes : 500
active arcs : 1905
simplex iterations : 1502
flow value : 4990014995
new implicit arcs : 23867
active arcs : 25772
simplex iterations : 2663
flow value : 3080014995
info: Increasing stack size by one page.
checksum : 68389
optimal
Exiting @ tick 67388458000 because target called exit()

652
simulators/gem5/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt Normal file
View File

@ -0,0 +1,652 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.067388 # Number of seconds simulated
sim_ticks 67388458000 # Number of ticks simulated
final_tick 67388458000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 84988 # Simulator instruction rate (inst/s)
host_op_rate 149650 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 36250631 # Simulator tick rate (ticks/s)
host_mem_usage 363056 # Number of bytes of host memory used
host_seconds 1858.96 # Real time elapsed on the host
sim_insts 157988582 # Number of instructions simulated
sim_ops 278192519 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 69248 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 3838272 # Number of bytes read from this memory
system.physmem.bytes_read::total 3907520 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 69248 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 69248 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 897536 # Number of bytes written to this memory
system.physmem.bytes_written::total 897536 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 1082 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 59973 # Number of read requests responded to by this memory
system.physmem.num_reads::total 61055 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 14024 # Number of write requests responded to by this memory
system.physmem.num_writes::total 14024 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 1027594 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 56957410 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 57985004 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 1027594 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 1027594 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 13318839 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 13318839 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 13318839 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 1027594 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 56957410 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 71303843 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 444 # Number of system calls
system.cpu.numCycles 134776917 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.BPredUnit.lookups 36128556 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 36128556 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 1088012 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 25661198 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 25550813 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 27997413 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 196488492 # Number of instructions fetch has processed
system.cpu.fetch.Branches 36128556 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 25550813 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 59432634 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 8416233 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 39238726 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 25 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 143 # Number of stall cycles due to pending traps
system.cpu.fetch.CacheLines 27278821 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 142192 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 133966907 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.578141 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.358289 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 77274639 57.68% 57.68% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 2166516 1.62% 59.30% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 2997281 2.24% 61.54% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 4102912 3.06% 64.60% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 8026102 5.99% 70.59% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 5043006 3.76% 74.35% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 2893464 2.16% 76.51% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 1468336 1.10% 77.61% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 29994651 22.39% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 133966907 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.268062 # Number of branch fetches per cycle
system.cpu.fetch.rate 1.457879 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 40465112 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 30125694 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 46506148 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 9571987 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 7297966 # Number of cycles decode is squashing
system.cpu.decode.DecodedInsts 341297669 # Number of instructions handled by decode
system.cpu.rename.SquashCycles 7297966 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 45865108 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 5065508 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 9277 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 50351191 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 25377857 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 337406380 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 13 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 3712 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 23187560 # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents 79157 # Number of times there has been no free registers
system.cpu.rename.RenamedOperands 414755881 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 1009935094 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 1009932394 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 2700 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 341010940 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 73744941 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 481 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 474 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 56192967 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 108162580 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 37173372 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 46311356 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 7909478 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 331723465 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 2616 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 311412241 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 185399 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 53269773 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 92543278 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 2170 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 133966907 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 2.324546 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.724461 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 27936582 20.85% 20.85% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 17254518 12.88% 33.73% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 25564521 19.08% 52.82% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 31166509 23.26% 76.08% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 17676068 13.19% 89.27% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 9033591 6.74% 96.02% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 3761456 2.81% 98.83% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 1501105 1.12% 99.95% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 72557 0.05% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 133966907 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 23354 1.11% 1.11% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 1.11% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 1.11% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.11% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.11% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.11% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 1.11% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.11% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 1.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 1.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.11% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 1960413 92.78% 93.89% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 129107 6.11% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 31371 0.01% 0.01% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 177196652 56.90% 56.91% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 0 0.00% 56.91% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 56.91% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 116 0.00% 56.91% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 56.91% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 56.91% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 56.91% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 56.91% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.91% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.91% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.91% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.91% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.91% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.91% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.91% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.91% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.91% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.91% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.91% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.91% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.91% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.91% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.91% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.91% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.91% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.91% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.91% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.91% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.91% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 99714062 32.02% 88.93% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 34470040 11.07% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 311412241 # Type of FU issued
system.cpu.iq.rate 2.310575 # Inst issue rate
system.cpu.iq.fu_busy_cnt 2112874 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.006785 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 759088710 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 385026224 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 308270248 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 952 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 1427 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 314 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 313493303 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 441 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 52569930 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 17383192 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 98849 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 32443 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 5733621 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 3316 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 3845 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 7297966 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 891871 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 89086 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 331726081 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 45756 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 108162580 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 37173372 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 476 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 224 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 43423 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 32443 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 615219 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 578970 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 1194189 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 309448819 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 99181332 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 1963422 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
system.cpu.iew.exec_refs 133262430 # number of memory reference insts executed
system.cpu.iew.exec_branches 31528913 # Number of branches executed
system.cpu.iew.exec_stores 34081098 # Number of stores executed
system.cpu.iew.exec_rate 2.296008 # Inst execution rate
system.cpu.iew.wb_sent 308818207 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 308270562 # cumulative count of insts written-back
system.cpu.iew.wb_producers 227514859 # num instructions producing a value
system.cpu.iew.wb_consumers 467066838 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 2.287265 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.487114 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitCommittedInsts 157988582 # The number of committed instructions
system.cpu.commit.commitCommittedOps 278192519 # The number of committed instructions
system.cpu.commit.commitSquashedInsts 53537768 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 446 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 1088027 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 126668941 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 2.196217 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.674380 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 46359304 36.60% 36.60% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 24201081 19.11% 55.70% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 16849760 13.30% 69.01% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 12619079 9.96% 78.97% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 3360251 2.65% 81.62% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 3556898 2.81% 84.43% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 2707142 2.14% 86.57% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 1157073 0.91% 87.48% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 15858353 12.52% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 126668941 # Number of insts commited each cycle
system.cpu.commit.committedInsts 157988582 # Number of instructions committed
system.cpu.commit.committedOps 278192519 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 122219139 # Number of memory references committed
system.cpu.commit.loads 90779388 # Number of loads committed
system.cpu.commit.membars 0 # Number of memory barriers committed
system.cpu.commit.branches 29309710 # Number of branches committed
system.cpu.commit.fp_insts 40 # Number of committed floating point instructions.
system.cpu.commit.int_insts 278186227 # Number of committed integer instructions.
system.cpu.commit.function_calls 0 # Number of function calls committed.
system.cpu.commit.bw_lim_events 15858353 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 442540875 # The number of ROB reads
system.cpu.rob.rob_writes 670767297 # The number of ROB writes
system.cpu.timesIdled 23993 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 810010 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 157988582 # Number of Instructions Simulated
system.cpu.committedOps 278192519 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 157988582 # Number of Instructions Simulated
system.cpu.cpi 0.853080 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.853080 # CPI: Total CPI of All Threads
system.cpu.ipc 1.172223 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.172223 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 705322547 # number of integer regfile reads
system.cpu.int_regfile_writes 373244258 # number of integer regfile writes
system.cpu.fp_regfile_reads 361 # number of floating regfile reads
system.cpu.fp_regfile_writes 193 # number of floating regfile writes
system.cpu.misc_regfile_reads 197929880 # number of misc regfile reads
system.cpu.icache.replacements 97 # number of replacements
system.cpu.icache.tagsinuse 846.508998 # Cycle average of tags in use
system.cpu.icache.total_refs 27277404 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 1093 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 24956.453797 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 846.508998 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.413334 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.413334 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 27277408 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 27277408 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 27277408 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 27277408 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 27277408 # number of overall hits
system.cpu.icache.overall_hits::total 27277408 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 1413 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 1413 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 1413 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 1413 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 1413 # number of overall misses
system.cpu.icache.overall_misses::total 1413 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 50201500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 50201500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 50201500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 50201500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 50201500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 50201500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 27278821 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 27278821 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 27278821 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 27278821 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 27278821 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 27278821 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000052 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000052 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000052 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000052 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000052 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000052 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35528.308563 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 35528.308563 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 35528.308563 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 35528.308563 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 35528.308563 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 35528.308563 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 315 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 315 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 315 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 315 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 315 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 315 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1098 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 1098 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 1098 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 1098 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 1098 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 1098 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 38330500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 38330500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 38330500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 38330500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 38330500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 38330500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000040 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34909.380692 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 34909.380692 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34909.380692 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 34909.380692 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34909.380692 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 34909.380692 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 2072128 # number of replacements
system.cpu.dcache.tagsinuse 4072.706371 # Cycle average of tags in use
system.cpu.dcache.total_refs 75623437 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 2076224 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 36.423544 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 22601159000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 4072.706371 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.994313 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.994313 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 44269678 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 44269678 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 31353743 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 31353743 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 75623421 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 75623421 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 75623421 # number of overall hits
system.cpu.dcache.overall_hits::total 75623421 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 2291019 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 2291019 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 86008 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 86008 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 2377027 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 2377027 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 2377027 # number of overall misses
system.cpu.dcache.overall_misses::total 2377027 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 13818885500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 13818885500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 1502429791 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 1502429791 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 15321315291 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 15321315291 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 15321315291 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 15321315291 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 46560697 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 46560697 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 31439751 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 31439751 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 78000448 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 78000448 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 78000448 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 78000448 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.049205 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.049205 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002736 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.002736 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.030475 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.030475 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.030475 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.030475 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 6031.763813 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 6031.763813 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17468.488873 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 17468.488873 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 6445.578990 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 6445.578990 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 6445.578990 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 6445.578990 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 1878988 # number of writebacks
system.cpu.dcache.writebacks::total 1878988 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 296886 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 296886 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3910 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 3910 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 300796 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 300796 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 300796 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 300796 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994133 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 1994133 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82098 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 82098 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 2076231 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 2076231 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 2076231 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 2076231 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5596231500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 5596231500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1158803791 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 1158803791 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6755035291 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 6755035291 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6755035291 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 6755035291 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.042829 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.042829 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002611 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002611 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026618 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.026618 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026618 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.026618 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 2806.348172 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 2806.348172 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14114.884540 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14114.884540 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 3253.508541 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 3253.508541 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 3253.508541 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 3253.508541 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 33429 # number of replacements
system.cpu.l2cache.tagsinuse 18994.164700 # Cycle average of tags in use
system.cpu.l2cache.total_refs 3761791 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 61439 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 61.228064 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 12943.264838 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 249.609803 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 5801.290058 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.394997 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.007617 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.177041 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.579656 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 12 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 1963548 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 1963560 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 1878988 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 1878988 # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 52705 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 52705 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst 12 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 2016253 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 2016265 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 12 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 2016253 # number of overall hits
system.cpu.l2cache.overall_hits::total 2016265 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 1082 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 30455 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 31537 # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data 4 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total 4 # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 29518 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 29518 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 1082 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 59973 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 61055 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 1082 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 59973 # number of overall misses
system.cpu.l2cache.overall_misses::total 61055 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 37085000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1040283500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 1077368500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1006135000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 1006135000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 37085000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 2046418500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 2083503500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 37085000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 2046418500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 2083503500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 1094 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 1994003 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 1995097 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 1878988 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 1878988 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 5 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total 5 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 82223 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 82223 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 1094 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 2076226 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 2077320 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 1094 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 2076226 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 2077320 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.989031 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.015273 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.015807 # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.800000 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.800000 # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.358999 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.358999 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.989031 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.028886 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.029391 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.989031 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.028886 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.029391 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34274.491682 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34158.052865 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 34162.047753 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34085.473271 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34085.473271 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34274.491682 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34122.330049 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 34125.026615 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34274.491682 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34122.330049 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 34125.026615 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks 14024 # number of writebacks
system.cpu.l2cache.writebacks::total 14024 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1082 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 30455 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 31537 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 4 # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total 4 # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 29518 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 29518 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 1082 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 59973 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 61055 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 1082 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 59973 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 61055 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 33615000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 944732500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 978347500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 124000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 124000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 915134000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 915134000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 33615000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1859866500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 1893481500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 33615000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1859866500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 1893481500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.989031 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.015273 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015807 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.800000 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.800000 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.358999 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.358999 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.989031 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.028886 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.029391 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.989031 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.028886 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.029391 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31067.467652 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31020.604170 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31022.212005 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31000 # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31002.574700 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31002.574700 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31067.467652 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31011.730279 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31012.718041 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31067.467652 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31011.730279 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31012.718041 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

138
simulators/gem5/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/config.ini Normal file
View File

@ -0,0 +1,138 @@
[root]
type=Root
children=system
full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
boot_osflags=a
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
readfile=
symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.cpu]
type=AtomicSimpleCPU
children=dtb interrupts itb tracer workload
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
fastmem=false
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
phase=0
profile=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
system=system
tracer=system.cpu.tracer
width=1
workload=system.cpu.workload
dcache_port=system.membus.slave[2]
icache_port=system.membus.slave[1]
[system.cpu.dtb]
type=X86TLB
children=walker
size=64
walker=system.cpu.dtb.walker
[system.cpu.dtb.walker]
type=X86PagetableWalker
system=system
port=system.membus.slave[4]
[system.cpu.interrupts]
type=X86LocalApic
int_latency=1000
pio_addr=2305843009213693952
pio_latency=1000
system=system
int_master=system.membus.slave[5]
int_slave=system.membus.master[2]
pio=system.membus.master[1]
[system.cpu.itb]
type=X86TLB
children=walker
size=64
walker=system.cpu.itb.walker
[system.cpu.itb.walker]
type=X86PagetableWalker
system=system
port=system.membus.slave[3]
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=mcf mcf.in
cwd=build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-atomic
egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/cpu2000/binaries/x86/linux/mcf
gid=100
input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=55300000000
system=system
uid=100
[system.membus]
type=CoherentBus
block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.interrupts.int_master
[system.physmem]
type=SimpleMemory
conf_table_reported=false
file=
in_addr_map=true
latency=30000
latency_var=0
null=false
range=0:268435455
zero=false
port=system.membus.master[0]

999
simulators/gem5/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/mcf.out Normal file
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@ -0,0 +1,999 @@
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1
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95

4
simulators/gem5/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simerr Executable file
View File

@ -0,0 +1,4 @@
warn: Sockets disabled, not accepting gdb connections
warn: instruction 'fnstcw_Mw' unimplemented
warn: instruction 'fldcw_Mw' unimplemented
hack: be nice to actually delete the event here

26
simulators/gem5/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simout Executable file
View File

@ -0,0 +1,26 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 4 2012 13:44:28
gem5 started Jun 4 2012 15:20:09
gem5 executing on zizzer
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
MCF SPEC version 1.6.I
by Andreas Loebel
Copyright (c) 1998,1999 ZIB Berlin
All Rights Reserved.
nodes : 500
active arcs : 1905
simplex iterations : 1502
flow value : 4990014995
new implicit arcs : 23867
active arcs : 25772
simplex iterations : 2663
flow value : 3080014995
checksum : 68389
optimal
Exiting @ tick 168950072000 because target called exit()

60
simulators/gem5/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt Normal file
View File

@ -0,0 +1,60 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.168950 # Number of seconds simulated
sim_ticks 168950072000 # Number of ticks simulated
final_tick 168950072000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1244063 # Simulator instruction rate (inst/s)
host_op_rate 2190595 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1330377575 # Simulator tick rate (ticks/s)
host_mem_usage 351912 # Number of bytes of host memory used
host_seconds 126.99 # Real time elapsed on the host
sim_insts 157988583 # Number of instructions simulated
sim_ops 278192520 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 1741569664 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 717246015 # Number of bytes read from this memory
system.physmem.bytes_read::total 2458815679 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 1741569664 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 1741569664 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 243173115 # Number of bytes written to this memory
system.physmem.bytes_written::total 243173115 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 217696208 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 90779450 # Number of read requests responded to by this memory
system.physmem.num_reads::total 308475658 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 31439751 # Number of write requests responded to by this memory
system.physmem.num_writes::total 31439751 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 10308191310 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 4245313462 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 14553504772 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 10308191310 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 10308191310 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 1439319393 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 1439319393 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 10308191310 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 5684632854 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 15992824164 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 444 # Number of system calls
system.cpu.numCycles 337900145 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 157988583 # Number of instructions committed
system.cpu.committedOps 278192520 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 278186228 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 40 # Number of float alu accesses
system.cpu.num_func_calls 0 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 18628012 # number of instructions that are conditional controls
system.cpu.num_int_insts 278186228 # number of integer instructions
system.cpu.num_fp_insts 40 # number of float instructions
system.cpu.num_int_register_reads 834011910 # number of times the integer registers were read
system.cpu.num_int_register_writes 341010914 # number of times the integer registers were written
system.cpu.num_fp_register_reads 40 # number of times the floating registers were read
system.cpu.num_fp_register_writes 26 # number of times the floating registers were written
system.cpu.num_mem_refs 122219139 # number of memory refs
system.cpu.num_load_insts 90779388 # Number of load instructions
system.cpu.num_store_insts 31439751 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 337900145 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
---------- End Simulation Statistics ----------

219
simulators/gem5/tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini Normal file
View File

@ -0,0 +1,219 @@
[root]
type=Root
children=system
full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
boot_osflags=a
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
readfile=
symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.cpu]
type=TimingSimpleCPU
children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
phase=0
profile=0
progress_interval=0
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=262144
subblock_size=0
system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
[system.cpu.dtb]
type=X86TLB
children=walker
size=64
walker=system.cpu.dtb.walker
[system.cpu.dtb.walker]
type=X86PagetableWalker
system=system
port=system.cpu.toL2Bus.slave[3]
[system.cpu.icache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=131072
subblock_size=0
system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.interrupts]
type=X86LocalApic
int_latency=1000
pio_addr=2305843009213693952
pio_latency=1000
system=system
int_master=system.membus.slave[2]
int_slave=system.membus.master[2]
pio=system.membus.master[1]
[system.cpu.itb]
type=X86TLB
children=walker
size=64
walker=system.cpu.itb.walker
[system.cpu.itb.walker]
type=X86PagetableWalker
system=system
port=system.cpu.toL2Bus.slave[2]
[system.cpu.l2cache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=false
latency=10000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=2097152
subblock_size=0
system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
[system.cpu.toL2Bus]
type=CoherentBus
block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=mcf mcf.in
cwd=build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing
egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/cpu2000/binaries/x86/linux/mcf
gid=100
input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=55300000000
system=system
uid=100
[system.membus]
type=CoherentBus
block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave
slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master
[system.physmem]
type=SimpleMemory
conf_table_reported=false
file=
in_addr_map=true
latency=30000
latency_var=0
null=false
range=0:268435455
zero=false
port=system.membus.master[0]

999
simulators/gem5/tests/long/se/10.mcf/ref/x86/linux/simple-timing/mcf.out Normal file
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@ -0,0 +1,999 @@
()
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()
499
()
498
()
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()
495
()
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()
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()
491
()
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()
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()
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()
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()
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()
484
()
482
()
481
()
480
()
479
()
478
()
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()
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()
475
()
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()
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()
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()
471
()
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()
468
()
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()
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()
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()
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()
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()
462
()
461
()
460
()
459
()
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()
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()
455
()
454
()
452
()
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()
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()
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()
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()
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()
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()
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()
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()
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()
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()
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()
438
()
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()
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()
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()
432
()
431
()
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()
427
()
425
()
424
()
423
()
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()
419
()
416
()
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()
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()
412
()
407
()
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()
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()
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()
403
()
402
()
401
()
400
()
399
()
398
()
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()
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()
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()
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()
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()
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()
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()
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()
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()
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()
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()
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()
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()
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()
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()
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()
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()
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()
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()
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()
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()
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()
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()
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()
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()
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()
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()
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()
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()
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()
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()
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()
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()
357
()
356
()
355
()
354
()
352
()
350
()
347
()
344
()
342
()
341
()
340
()
339
()
338
()
332
()
325
()
320
***
345
()
319
***
497
()
318
***
349
()
317
***
408
()
316
***
324
()
315
***
328
()
314
***
335
()
313
***
378
()
312
***
426
()
311
***
411
()
304
***
343
()
303
***
417
()
302
***
485
()
301
***
363
()
300
***
376
()
299
***
333
()
292
***
337
()
291
***
409
()
290
***
421
()
289
***
437
()
288
***
430
()
287
***
348
()
286
***
326
()
284
()
282
***
308
()
279
***
297
***
305
()
278
()
277
***
307
()
276
***
296
()
273
()
271
()
265
()
246
***
267
()
245
***
280
()
244
***
391
()
243
***
330
()
242
***
456
()
241
***
346
()
240
***
483
()
239
***
260
()
238
***
261
()
237
***
262
***
294
()
236
***
253
()
229
***
397
()
228
***
298
()
227
***
415
()
226
***
264
()
224
***
232
()
222
***
233
()
217
***
250
()
211
***
331
()
210
***
394
()
209
***
410
()
208
***
321
()
207
***
327
()
206
***
309
()
199
***
259
()
198
***
219
()
197
***
220
()
195
***
429
()
194
***
470
()
193
***
274
()
191
***
203
()
190
***
263
()
189
215
***
230
()
188
***
266
***
295
()
182
***
329
()
181
***
351
()
180
***
441
()
179
***
453
()
178
***
418
()
177
***
353
()
176
***
422
()
175
***
225
***
255
()
174
***
269
()
173
***
214
()
172
***
186
()
171
***
447
()
170
***
270
***
306
()
169
***
336
()
168
***
285
()
165
***
249
()
146
***
154
()
143
***
334
()
142
***
216
***
257
()
141
***
167
***
251
()
140
***
162
***
293
()
139
***
158
()
137
***
166
***
201
()
136
***
160
()
134
***
221
()
132
***
213
()
131
***
187
()
129
***
235
()
128
***
153
()
127
***
156
()
126
***
159
***
218
()
125
***
155
()
124
***
157
()
123
***
152
()
116
***
135
***
163
()
115
***
133
***
204
***
248
()
114
***
192
***
212
()
113
***
268
()
112
***
367
()
111
***
272
()
110
***
434
()
109
***
323
()
108
***
281
()
107
***
144
***
148
()
106
***
275
()
105
***
196
***
254
()
104
***
138
***
161
()
103
***
310
()
102
***
223
***
252
()
80
()
70
()
69
()
68
()
66
()
64
()
62
***
256
()
61
***
93
()
59
***
120
()
58
()
57
***
183
()
55
()
54
()
52
***
147
()
51
***
118
()
50
***
83
()
49
***
98
()
48
***
99
()
47
()
46
***
184
()
45
***
121
()
44
()
43
***
88
()
42
***
122
()
41
***
91
()
40
***
96
()
38
***
100
()
37
***
149
()
36
***
74
()
35
***
258
()
34
***
151
()
33
***
85
()
32
()
31
***
94
()
30
***
97
()
29
***
90
()
28
***
89
()
27
***
92
()
26
***
72
***
247
()
25
***
86
()
24
***
82
()
23
***
87
***
117
()
22
***
76
***
119
()
21
***
84
()
20
***
78
()
19
***
73
()
18
***
81
()
17
***
65
()
16
***
63
***
101
()
15
***
71
()
14
***
75
()
13
***
322
()
12
***
77
()
11
***
283
()
10
***
79
()
9
***
145
***
150
()
8
***
67
()
7
***
60
***
231
()
6
***
56
***
234
()
5
***
164
***
202
()
4
***
53
()
3
***
130
***
185
***
200
()
2
***
205
()
1
***
39
***
95

4
simulators/gem5/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simerr Executable file
View File

@ -0,0 +1,4 @@
warn: Sockets disabled, not accepting gdb connections
warn: instruction 'fnstcw_Mw' unimplemented
warn: instruction 'fldcw_Mw' unimplemented
hack: be nice to actually delete the event here

26
simulators/gem5/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout Executable file
View File

@ -0,0 +1,26 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 4 2012 13:44:28
gem5 started Jun 4 2012 15:22:27
gem5 executing on zizzer
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
MCF SPEC version 1.6.I
by Andreas Loebel
Copyright (c) 1998,1999 ZIB Berlin
All Rights Reserved.
nodes : 500
active arcs : 1905
simplex iterations : 1502
flow value : 4990014995
new implicit arcs : 23867
active arcs : 25772
simplex iterations : 2663
flow value : 3080014995
checksum : 68389
optimal
Exiting @ tick 370010840000 because target called exit()

374
simulators/gem5/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt Normal file
View File

@ -0,0 +1,374 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.370011 # Number of seconds simulated
sim_ticks 370010840000 # Number of ticks simulated
final_tick 370010840000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 564351 # Simulator instruction rate (inst/s)
host_op_rate 993732 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1321716509 # Simulator tick rate (ticks/s)
host_mem_usage 360832 # Number of bytes of host memory used
host_seconds 279.95 # Real time elapsed on the host
sim_insts 157988583 # Number of instructions simulated
sim_ops 278192520 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 51712 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 4849088 # Number of bytes read from this memory
system.physmem.bytes_read::total 4900800 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 51712 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 51712 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 1885440 # Number of bytes written to this memory
system.physmem.bytes_written::total 1885440 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 808 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 75767 # Number of read requests responded to by this memory
system.physmem.num_reads::total 76575 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 29460 # Number of write requests responded to by this memory
system.physmem.num_writes::total 29460 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 139758 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 13105259 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 13245017 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 139758 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 139758 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 5095634 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 5095634 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 5095634 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 139758 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 13105259 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 18340652 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 444 # Number of system calls
system.cpu.numCycles 740021680 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 157988583 # Number of instructions committed
system.cpu.committedOps 278192520 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 278186228 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 40 # Number of float alu accesses
system.cpu.num_func_calls 0 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 18628012 # number of instructions that are conditional controls
system.cpu.num_int_insts 278186228 # number of integer instructions
system.cpu.num_fp_insts 40 # number of float instructions
system.cpu.num_int_register_reads 834011910 # number of times the integer registers were read
system.cpu.num_int_register_writes 341010914 # number of times the integer registers were written
system.cpu.num_fp_register_reads 40 # number of times the floating registers were read
system.cpu.num_fp_register_writes 26 # number of times the floating registers were written
system.cpu.num_mem_refs 122219139 # number of memory refs
system.cpu.num_load_insts 90779388 # Number of load instructions
system.cpu.num_store_insts 31439751 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 740021680 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.icache.replacements 24 # number of replacements
system.cpu.icache.tagsinuse 666.191948 # Cycle average of tags in use
system.cpu.icache.total_refs 217695401 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 808 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 269425.001238 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 666.191948 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.325289 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.325289 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 217695401 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 217695401 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 217695401 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 217695401 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 217695401 # number of overall hits
system.cpu.icache.overall_hits::total 217695401 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 808 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 808 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 808 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 808 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 808 # number of overall misses
system.cpu.icache.overall_misses::total 808 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 45248000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 45248000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 45248000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 45248000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 45248000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 45248000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 217696209 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 217696209 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 217696209 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 217696209 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 217696209 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 217696209 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56000 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 56000 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 56000 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 56000 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 56000 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 56000 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 808 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 808 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 808 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 808 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 808 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 808 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 42824000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 42824000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 42824000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 42824000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 42824000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 42824000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53000 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 2062733 # number of replacements
system.cpu.dcache.tagsinuse 4076.661903 # Cycle average of tags in use
system.cpu.dcache.total_refs 120152372 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 2066829 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 58.133678 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 126200130000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 4076.661903 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.995279 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.995279 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 88818730 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 88818730 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 31333642 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 31333642 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 120152372 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 120152372 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 120152372 # number of overall hits
system.cpu.dcache.overall_hits::total 120152372 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 1960720 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 1960720 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 106109 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 106109 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 2066829 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 2066829 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 2066829 # number of overall misses
system.cpu.dcache.overall_misses::total 2066829 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 28849058000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 28849058000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 3268793000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 3268793000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 32117851000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 32117851000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 32117851000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 32117851000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 90779450 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 90779450 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 31439751 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 31439751 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 122219201 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 122219201 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 122219201 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 122219201 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.021599 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.021599 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003375 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.003375 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.016911 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.016911 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.016911 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.016911 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14713.502183 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 14713.502183 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30805.991952 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 30805.991952 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 15539.675029 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 15539.675029 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 15539.675029 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 15539.675029 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 1437080 # number of writebacks
system.cpu.dcache.writebacks::total 1437080 # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1960720 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 1960720 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 106109 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 106109 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 2066829 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 2066829 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 2066829 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 2066829 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 22966898000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 22966898000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2950464500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 2950464500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 25917362500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 25917362500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 25917362500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 25917362500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.021599 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.021599 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003375 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.003375 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016911 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.016911 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016911 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.016911 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11713.502183 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11713.502183 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27805.977815 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27805.977815 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12539.674303 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 12539.674303 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12539.674303 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 12539.674303 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 49212 # number of replacements
system.cpu.l2cache.tagsinuse 18614.603260 # Cycle average of tags in use
system.cpu.l2cache.total_refs 3296079 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 77127 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 42.735735 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 12062.804989 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 196.794797 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 6355.003474 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.368128 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.006006 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.193939 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.568073 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.data 1927411 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 1927411 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 1437080 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 1437080 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 63651 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 63651 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.data 1991062 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 1991062 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.data 1991062 # number of overall hits
system.cpu.l2cache.overall_hits::total 1991062 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 808 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 33309 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 34117 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 42458 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 42458 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 808 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 75767 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 76575 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 808 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 75767 # number of overall misses
system.cpu.l2cache.overall_misses::total 76575 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 42016000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1732068000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 1774084000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2207845500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 2207845500 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 42016000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 3939913500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 3981929500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 42016000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 3939913500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 3981929500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 808 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 1960720 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 1961528 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 1437080 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 1437080 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 106109 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 106109 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 808 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 2066829 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 2067637 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 808 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 2066829 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 2067637 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.016988 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.017393 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.400136 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.400136 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.036659 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.037035 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.036659 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.037035 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000.694804 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000.694804 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000.389352 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 52000.385243 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000.389352 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 52000.385243 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks 29460 # number of writebacks
system.cpu.l2cache.writebacks::total 29460 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 808 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 33309 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 34117 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 42458 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 42458 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 808 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 75767 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 76575 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 808 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 75767 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 76575 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 32320000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1332360000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1364680000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1698320000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1698320000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 32320000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3030680000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 3063000000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 32320000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3030680000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 3063000000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.016988 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.017393 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.400136 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.400136 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.036659 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.037035 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.036659 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.037035 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

34
simulators/gem5/tests/long/se/10.mcf/test.py Normal file
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@ -0,0 +1,34 @@
# Copyright (c) 2006-2007 The Regents of The University of Michigan
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Korey Sewell
m5.util.addToPath('../configs/common')
from cpu2000 import mcf
workload = mcf(isa, opsys, 'smred')
root.system.cpu.workload = workload.makeLiveProcess()
root.system.physmem.range=AddrRange('256MB')

6
simulators/gem5/tests/long/se/20.parser/ref/alpha/tru64/NOTE Normal file
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@ -0,0 +1,6 @@
I removed the reference outputs for this program because it's taking
way too long... over an hour for simple-atomic and over 19 hrs for
o3-timing. We need to find a shorter input if we want to keep this
in the regressions.
Steve

547
simulators/gem5/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini Normal file
View File

@ -0,0 +1,547 @@
[root]
type=Root
children=system
full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
boot_osflags=a
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
readfile=
symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.cpu]
type=DerivO3CPU
children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
LSQDepCheckShift=4
RASSize=16
SQEntries=32
SSITSize=1024
activity=0
backComSize=5
cachePorts=200
checker=Null
choiceCtrBits=2
choicePredictorSize=8192
clock=500
commitToDecodeDelay=1
commitToFetchDelay=1
commitToIEWDelay=1
commitToRenameDelay=1
commitWidth=8
cpu_id=0
decodeToFetchDelay=1
decodeToRenameDelay=1
decodeWidth=8
defer_registration=false
dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
fetchToDecodeDelay=1
fetchTrapLatency=1
fetchWidth=8
forwardComSize=5
fuPool=system.cpu.fuPool
function_trace=false
function_trace_start=0
globalCtrBits=2
globalHistoryBits=13
globalPredictorSize=8192
iewToCommitDelay=1
iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
instShiftAmt=2
interrupts=system.cpu.interrupts
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
localCtrBits=2
localHistoryBits=11
localHistoryTableSize=2048
localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
needsTSO=false
numIQEntries=64
numPhysFloatRegs=256
numPhysIntRegs=256
numROBEntries=192
numRobs=1
numThreads=1
phase=0
predType=tournament
profile=0
progress_interval=0
renameToDecodeDelay=1
renameToFetchDelay=1
renameToIEWDelay=2
renameToROBDelay=1
renameWidth=8
smtCommitPolicy=RoundRobin
smtFetchPolicy=SingleThread
smtIQPolicy=Partitioned
smtIQThreshold=100
smtLSQPolicy=Partitioned
smtLSQThreshold=100
smtNumFetchingThreads=1
smtROBPolicy=Partitioned
smtROBThreshold=100
squashWidth=8
store_set_clear_period=250000
system=system
tracer=system.cpu.tracer
trapLatency=13
wbDepth=1
wbWidth=8
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=262144
subblock_size=0
system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
[system.cpu.dtb]
type=ArmTLB
children=walker
size=64
walker=system.cpu.dtb.walker
[system.cpu.dtb.walker]
type=ArmTableWalker
max_backoff=100000
min_backoff=0
sys=system
port=system.cpu.toL2Bus.slave[3]
[system.cpu.fuPool]
type=FUPool
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
[system.cpu.fuPool.FUList0]
type=FUDesc
children=opList
count=6
opList=system.cpu.fuPool.FUList0.opList
[system.cpu.fuPool.FUList0.opList]
type=OpDesc
issueLat=1
opClass=IntAlu
opLat=1
[system.cpu.fuPool.FUList1]
type=FUDesc
children=opList0 opList1
count=2
opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
[system.cpu.fuPool.FUList1.opList0]
type=OpDesc
issueLat=1
opClass=IntMult
opLat=3
[system.cpu.fuPool.FUList1.opList1]
type=OpDesc
issueLat=19
opClass=IntDiv
opLat=20
[system.cpu.fuPool.FUList2]
type=FUDesc
children=opList0 opList1 opList2
count=4
opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
[system.cpu.fuPool.FUList2.opList0]
type=OpDesc
issueLat=1
opClass=FloatAdd
opLat=2
[system.cpu.fuPool.FUList2.opList1]
type=OpDesc
issueLat=1
opClass=FloatCmp
opLat=2
[system.cpu.fuPool.FUList2.opList2]
type=OpDesc
issueLat=1
opClass=FloatCvt
opLat=2
[system.cpu.fuPool.FUList3]
type=FUDesc
children=opList0 opList1 opList2
count=2
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
[system.cpu.fuPool.FUList3.opList0]
type=OpDesc
issueLat=1
opClass=FloatMult
opLat=4
[system.cpu.fuPool.FUList3.opList1]
type=OpDesc
issueLat=12
opClass=FloatDiv
opLat=12
[system.cpu.fuPool.FUList3.opList2]
type=OpDesc
issueLat=24
opClass=FloatSqrt
opLat=24
[system.cpu.fuPool.FUList4]
type=FUDesc
children=opList
count=0
opList=system.cpu.fuPool.FUList4.opList
[system.cpu.fuPool.FUList4.opList]
type=OpDesc
issueLat=1
opClass=MemRead
opLat=1
[system.cpu.fuPool.FUList5]
type=FUDesc
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
count=4
opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
[system.cpu.fuPool.FUList5.opList00]
type=OpDesc
issueLat=1
opClass=SimdAdd
opLat=1
[system.cpu.fuPool.FUList5.opList01]
type=OpDesc
issueLat=1
opClass=SimdAddAcc
opLat=1
[system.cpu.fuPool.FUList5.opList02]
type=OpDesc
issueLat=1
opClass=SimdAlu
opLat=1
[system.cpu.fuPool.FUList5.opList03]
type=OpDesc
issueLat=1
opClass=SimdCmp
opLat=1
[system.cpu.fuPool.FUList5.opList04]
type=OpDesc
issueLat=1
opClass=SimdCvt
opLat=1
[system.cpu.fuPool.FUList5.opList05]
type=OpDesc
issueLat=1
opClass=SimdMisc
opLat=1
[system.cpu.fuPool.FUList5.opList06]
type=OpDesc
issueLat=1
opClass=SimdMult
opLat=1
[system.cpu.fuPool.FUList5.opList07]
type=OpDesc
issueLat=1
opClass=SimdMultAcc
opLat=1
[system.cpu.fuPool.FUList5.opList08]
type=OpDesc
issueLat=1
opClass=SimdShift
opLat=1
[system.cpu.fuPool.FUList5.opList09]
type=OpDesc
issueLat=1
opClass=SimdShiftAcc
opLat=1
[system.cpu.fuPool.FUList5.opList10]
type=OpDesc
issueLat=1
opClass=SimdSqrt
opLat=1
[system.cpu.fuPool.FUList5.opList11]
type=OpDesc
issueLat=1
opClass=SimdFloatAdd
opLat=1
[system.cpu.fuPool.FUList5.opList12]
type=OpDesc
issueLat=1
opClass=SimdFloatAlu
opLat=1
[system.cpu.fuPool.FUList5.opList13]
type=OpDesc
issueLat=1
opClass=SimdFloatCmp
opLat=1
[system.cpu.fuPool.FUList5.opList14]
type=OpDesc
issueLat=1
opClass=SimdFloatCvt
opLat=1
[system.cpu.fuPool.FUList5.opList15]
type=OpDesc
issueLat=1
opClass=SimdFloatDiv
opLat=1
[system.cpu.fuPool.FUList5.opList16]
type=OpDesc
issueLat=1
opClass=SimdFloatMisc
opLat=1
[system.cpu.fuPool.FUList5.opList17]
type=OpDesc
issueLat=1
opClass=SimdFloatMult
opLat=1
[system.cpu.fuPool.FUList5.opList18]
type=OpDesc
issueLat=1
opClass=SimdFloatMultAcc
opLat=1
[system.cpu.fuPool.FUList5.opList19]
type=OpDesc
issueLat=1
opClass=SimdFloatSqrt
opLat=1
[system.cpu.fuPool.FUList6]
type=FUDesc
children=opList
count=0
opList=system.cpu.fuPool.FUList6.opList
[system.cpu.fuPool.FUList6.opList]
type=OpDesc
issueLat=1
opClass=MemWrite
opLat=1
[system.cpu.fuPool.FUList7]
type=FUDesc
children=opList0 opList1
count=4
opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
[system.cpu.fuPool.FUList7.opList0]
type=OpDesc
issueLat=1
opClass=MemRead
opLat=1
[system.cpu.fuPool.FUList7.opList1]
type=OpDesc
issueLat=1
opClass=MemWrite
opLat=1
[system.cpu.fuPool.FUList8]
type=FUDesc
children=opList
count=1
opList=system.cpu.fuPool.FUList8.opList
[system.cpu.fuPool.FUList8.opList]
type=OpDesc
issueLat=3
opClass=IprAccess
opLat=3
[system.cpu.icache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=131072
subblock_size=0
system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.interrupts]
type=ArmInterrupts
[system.cpu.itb]
type=ArmTLB
children=walker
size=64
walker=system.cpu.itb.walker
[system.cpu.itb.walker]
type=ArmTableWalker
max_backoff=100000
min_backoff=0
sys=system
port=system.cpu.toL2Bus.slave[2]
[system.cpu.l2cache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=false
latency=1000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=2097152
subblock_size=0
system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
[system.cpu.toL2Bus]
type=CoherentBus
block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=parser 2.1.dict -batch
cwd=build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing
egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/cpu2000/binaries/arm/linux/parser
gid=100
input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=114600000000
system=system
uid=100
[system.membus]
type=CoherentBus
block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
master=system.physmem.port[0]
slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=SimpleMemory
conf_table_reported=false
file=
in_addr_map=true
latency=30000
latency_var=0
null=false
range=0:134217727
zero=false
port=system.membus.master[0]

3
simulators/gem5/tests/long/se/20.parser/ref/arm/linux/o3-timing/simerr Executable file
View File

@ -0,0 +1,3 @@
warn: Sockets disabled, not accepting gdb connections
warn: CP14 unimplemented crn[8], opc1[2], crm[9], opc2[4]
hack: be nice to actually delete the event here

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