Adding gem5 source to svn.
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1819 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
This commit is contained in:
friemel
@ -0,0 +1,484 @@
|
||||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
full_system=true
|
||||
time_sync_enable=false
|
||||
time_sync_period=200000000
|
||||
time_sync_spin_threshold=200000
|
||||
|
||||
[system]
|
||||
type=SparcSystem
|
||||
children=bridge cpu disk0 hypervisor_desc intrctrl iobus membus nvram partition_desc physmem physmem2 rom t1000
|
||||
boot_osflags=a
|
||||
hypervisor_addr=1099243257856
|
||||
hypervisor_bin=/dist/m5/system/binaries/q_new.bin
|
||||
hypervisor_desc=system.hypervisor_desc
|
||||
hypervisor_desc_addr=133446500352
|
||||
hypervisor_desc_bin=/dist/m5/system/binaries/1up-hv.bin
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
mem_mode=atomic
|
||||
memories=system.partition_desc system.rom system.hypervisor_desc system.nvram system.physmem system.physmem2
|
||||
num_work_ids=16
|
||||
nvram=system.nvram
|
||||
nvram_addr=133429198848
|
||||
nvram_bin=/dist/m5/system/binaries/nvram1
|
||||
openboot_addr=1099243716608
|
||||
openboot_bin=/dist/m5/system/binaries/openboot_new.bin
|
||||
partition_desc=system.partition_desc
|
||||
partition_desc_addr=133445976064
|
||||
partition_desc_bin=/dist/m5/system/binaries/1up-md.bin
|
||||
readfile=tests/halt.sh
|
||||
reset_addr=1099243192320
|
||||
reset_bin=/dist/m5/system/binaries/reset_new.bin
|
||||
rom=system.rom
|
||||
symbolfile=
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.membus.slave[0]
|
||||
|
||||
[system.bridge]
|
||||
type=Bridge
|
||||
delay=100
|
||||
nack_delay=8
|
||||
ranges=133412421632:133412421639 134217728000:554050781183 644245094400:652835028991 725849473024:1095485095935 1099255955456:1099255955463
|
||||
req_size=16
|
||||
resp_size=16
|
||||
write_ack=false
|
||||
master=system.iobus.slave[0]
|
||||
slave=system.membus.master[2]
|
||||
|
||||
[system.cpu]
|
||||
type=AtomicSimpleCPU
|
||||
children=dtb interrupts itb tracer
|
||||
checker=Null
|
||||
clock=1
|
||||
cpu_id=0
|
||||
defer_registration=false
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
fastmem=false
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
interrupts=system.cpu.interrupts
|
||||
itb=system.cpu.itb
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
phase=0
|
||||
profile=0
|
||||
progress_interval=0
|
||||
simulate_data_stalls=false
|
||||
simulate_inst_stalls=false
|
||||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
width=1
|
||||
workload=
|
||||
dcache_port=system.membus.slave[2]
|
||||
icache_port=system.membus.slave[1]
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=SparcTLB
|
||||
size=64
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=SparcInterrupts
|
||||
|
||||
[system.cpu.itb]
|
||||
type=SparcTLB
|
||||
size=64
|
||||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
|
||||
[system.disk0]
|
||||
type=MmDisk
|
||||
children=image
|
||||
image=system.disk0.image
|
||||
pio_addr=134217728000
|
||||
pio_latency=2
|
||||
system=system
|
||||
pio=system.iobus.master[14]
|
||||
|
||||
[system.disk0.image]
|
||||
type=CowDiskImage
|
||||
children=child
|
||||
child=system.disk0.image.child
|
||||
image_file=
|
||||
read_only=false
|
||||
table_size=65536
|
||||
|
||||
[system.disk0.image.child]
|
||||
type=RawDiskImage
|
||||
image_file=/dist/m5/system/disks/disk.s10hw2
|
||||
read_only=true
|
||||
|
||||
[system.hypervisor_desc]
|
||||
type=SimpleMemory
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=60
|
||||
latency_var=0
|
||||
null=false
|
||||
range=133446500352:133446508543
|
||||
zero=false
|
||||
port=system.membus.master[7]
|
||||
|
||||
[system.intrctrl]
|
||||
type=IntrControl
|
||||
sys=system
|
||||
|
||||
[system.iobus]
|
||||
type=NoncoherentBus
|
||||
block_size=64
|
||||
clock=2
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
master=system.t1000.fake_clk.pio system.t1000.fake_membnks.pio system.t1000.fake_l2_1.pio system.t1000.fake_l2_2.pio system.t1000.fake_l2_3.pio system.t1000.fake_l2_4.pio system.t1000.fake_l2esr_1.pio system.t1000.fake_l2esr_2.pio system.t1000.fake_l2esr_3.pio system.t1000.fake_l2esr_4.pio system.t1000.fake_ssi.pio system.t1000.fake_jbi.pio system.t1000.puart0.pio system.t1000.hvuart.pio system.disk0.pio
|
||||
slave=system.bridge.master
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
children=badaddr_responder
|
||||
block_size=64
|
||||
clock=2
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
default=system.membus.badaddr_responder.pio
|
||||
master=system.t1000.iob.pio system.t1000.htod.pio system.bridge.slave system.physmem.port[0] system.physmem2.port[0] system.rom.port[0] system.nvram.port[0] system.hypervisor_desc.port[0] system.partition_desc.port[0]
|
||||
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
|
||||
|
||||
[system.membus.badaddr_responder]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=0
|
||||
pio_latency=2
|
||||
pio_size=8
|
||||
ret_bad_addr=true
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.membus.default
|
||||
|
||||
[system.nvram]
|
||||
type=SimpleMemory
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=60
|
||||
latency_var=0
|
||||
null=false
|
||||
range=133429198848:133429207039
|
||||
zero=false
|
||||
port=system.membus.master[6]
|
||||
|
||||
[system.partition_desc]
|
||||
type=SimpleMemory
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=60
|
||||
latency_var=0
|
||||
null=false
|
||||
range=133445976064:133445984255
|
||||
zero=false
|
||||
port=system.membus.master[8]
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=60
|
||||
latency_var=0
|
||||
null=false
|
||||
range=1048576:68157439
|
||||
zero=true
|
||||
port=system.membus.master[3]
|
||||
|
||||
[system.physmem2]
|
||||
type=SimpleMemory
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=60
|
||||
latency_var=0
|
||||
null=false
|
||||
range=2147483648:2415919103
|
||||
zero=true
|
||||
port=system.membus.master[4]
|
||||
|
||||
[system.rom]
|
||||
type=SimpleMemory
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=60
|
||||
latency_var=0
|
||||
null=false
|
||||
range=1099243192320:1099251580927
|
||||
zero=false
|
||||
port=system.membus.master[5]
|
||||
|
||||
[system.t1000]
|
||||
type=T1000
|
||||
children=fake_clk fake_jbi fake_l2_1 fake_l2_2 fake_l2_3 fake_l2_4 fake_l2esr_1 fake_l2esr_2 fake_l2esr_3 fake_l2esr_4 fake_membnks fake_ssi hterm htod hvuart iob pterm puart0
|
||||
intrctrl=system.intrctrl
|
||||
system=system
|
||||
|
||||
[system.t1000.fake_clk]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=644245094400
|
||||
pio_latency=2
|
||||
pio_size=4294967296
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[0]
|
||||
|
||||
[system.t1000.fake_jbi]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=549755813888
|
||||
pio_latency=2
|
||||
pio_size=4294967296
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[11]
|
||||
|
||||
[system.t1000.fake_l2_1]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=725849473024
|
||||
pio_latency=2
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=1
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=true
|
||||
warn_access=
|
||||
pio=system.iobus.master[2]
|
||||
|
||||
[system.t1000.fake_l2_2]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=725849473088
|
||||
pio_latency=2
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=1
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=true
|
||||
warn_access=
|
||||
pio=system.iobus.master[3]
|
||||
|
||||
[system.t1000.fake_l2_3]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=725849473152
|
||||
pio_latency=2
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=1
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=true
|
||||
warn_access=
|
||||
pio=system.iobus.master[4]
|
||||
|
||||
[system.t1000.fake_l2_4]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=725849473216
|
||||
pio_latency=2
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=1
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=true
|
||||
warn_access=
|
||||
pio=system.iobus.master[5]
|
||||
|
||||
[system.t1000.fake_l2esr_1]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=734439407616
|
||||
pio_latency=2
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=0
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=true
|
||||
warn_access=
|
||||
pio=system.iobus.master[6]
|
||||
|
||||
[system.t1000.fake_l2esr_2]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=734439407680
|
||||
pio_latency=2
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=0
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=true
|
||||
warn_access=
|
||||
pio=system.iobus.master[7]
|
||||
|
||||
[system.t1000.fake_l2esr_3]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=734439407744
|
||||
pio_latency=2
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=0
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=true
|
||||
warn_access=
|
||||
pio=system.iobus.master[8]
|
||||
|
||||
[system.t1000.fake_l2esr_4]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=734439407808
|
||||
pio_latency=2
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=0
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=true
|
||||
warn_access=
|
||||
pio=system.iobus.master[9]
|
||||
|
||||
[system.t1000.fake_membnks]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=648540061696
|
||||
pio_latency=2
|
||||
pio_size=16384
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=0
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[1]
|
||||
|
||||
[system.t1000.fake_ssi]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=1095216660480
|
||||
pio_latency=2
|
||||
pio_size=268435456
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[10]
|
||||
|
||||
[system.t1000.hterm]
|
||||
type=Terminal
|
||||
intr_control=system.intrctrl
|
||||
number=0
|
||||
output=true
|
||||
port=3456
|
||||
|
||||
[system.t1000.htod]
|
||||
type=DumbTOD
|
||||
pio_addr=1099255906296
|
||||
pio_latency=2
|
||||
system=system
|
||||
time=Thu Jan 1 00:00:00 2009
|
||||
pio=system.membus.master[1]
|
||||
|
||||
[system.t1000.hvuart]
|
||||
type=Uart8250
|
||||
pio_addr=1099255955456
|
||||
pio_latency=2
|
||||
platform=system.t1000
|
||||
system=system
|
||||
terminal=system.t1000.hterm
|
||||
pio=system.iobus.master[13]
|
||||
|
||||
[system.t1000.iob]
|
||||
type=Iob
|
||||
pio_latency=2
|
||||
platform=system.t1000
|
||||
system=system
|
||||
pio=system.membus.master[0]
|
||||
|
||||
[system.t1000.pterm]
|
||||
type=Terminal
|
||||
intr_control=system.intrctrl
|
||||
number=0
|
||||
output=true
|
||||
port=3456
|
||||
|
||||
[system.t1000.puart0]
|
||||
type=Uart8250
|
||||
pio_addr=133412421632
|
||||
pio_latency=2
|
||||
platform=system.t1000
|
||||
system=system
|
||||
terminal=system.t1000.pterm
|
||||
pio=system.iobus.master[12]
|
||||
|
||||
@ -0,0 +1,5 @@
|
||||
warn: Sockets disabled, not accepting terminal connections
|
||||
warn: CoherentBus system.membus has no snooping ports attached!
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: Don't know what interrupt to clear for console.
|
||||
hack: be nice to actually delete the event here
|
||||
@ -0,0 +1,16 @@
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jun 4 2012 12:01:47
|
||||
gem5 started Jun 4 2012 15:02:47
|
||||
gem5 executing on zizzer
|
||||
command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/fs/80.solaris-boot/sparc/solaris/t1000-simple-atomic -re tests/run.py build/SPARC/tests/opt/long/fs/80.solaris-boot/sparc/solaris/t1000-simple-atomic
|
||||
Global frequency set at 2000000000 ticks per second
|
||||
info: No kernel set for full system simulation. Assuming you know what you're doing if not SPARC ISA
|
||||
0: system.t1000.htod: Real-time clock set to Thu Jan 1 00:00:00 2009
|
||||
|
||||
0: system.t1000.htod: Real-time clock set to 1230768000
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Ignoring write to SPARC ERROR regsiter
|
||||
info: Ignoring write to SPARC ERROR regsiter
|
||||
Exiting @ tick 2233777512 because m5_exit instruction encountered
|
||||
@ -0,0 +1,133 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 1.116889 # Number of seconds simulated
|
||||
sim_ticks 2233777512 # Number of ticks simulated
|
||||
final_tick 2233777512 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 2000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 3140005 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 3141240 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 3147745 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 511524 # Number of bytes of host memory used
|
||||
host_seconds 709.64 # Real time elapsed on the host
|
||||
sim_insts 2228284650 # Number of instructions simulated
|
||||
sim_ops 2229160714 # Number of ops (including micro ops) simulated
|
||||
system.hypervisor_desc.bytes_read::cpu.data 16792 # Number of bytes read from this memory
|
||||
system.hypervisor_desc.bytes_read::total 16792 # Number of bytes read from this memory
|
||||
system.hypervisor_desc.num_reads::cpu.data 9024 # Number of read requests responded to by this memory
|
||||
system.hypervisor_desc.num_reads::total 9024 # Number of read requests responded to by this memory
|
||||
system.hypervisor_desc.bw_read::cpu.data 15035 # Total read bandwidth from this memory (bytes/s)
|
||||
system.hypervisor_desc.bw_read::total 15035 # Total read bandwidth from this memory (bytes/s)
|
||||
system.hypervisor_desc.bw_total::cpu.data 15035 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.hypervisor_desc.bw_total::total 15035 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.partition_desc.bytes_read::cpu.data 4846 # Number of bytes read from this memory
|
||||
system.partition_desc.bytes_read::total 4846 # Number of bytes read from this memory
|
||||
system.partition_desc.num_reads::cpu.data 608 # Number of read requests responded to by this memory
|
||||
system.partition_desc.num_reads::total 608 # Number of read requests responded to by this memory
|
||||
system.partition_desc.bw_read::cpu.data 4339 # Total read bandwidth from this memory (bytes/s)
|
||||
system.partition_desc.bw_read::total 4339 # Total read bandwidth from this memory (bytes/s)
|
||||
system.partition_desc.bw_total::cpu.data 4339 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.partition_desc.bw_total::total 4339 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.rom.bytes_read::cpu.inst 432296 # Number of bytes read from this memory
|
||||
system.rom.bytes_read::cpu.data 696392 # Number of bytes read from this memory
|
||||
system.rom.bytes_read::total 1128688 # Number of bytes read from this memory
|
||||
system.rom.bytes_inst_read::cpu.inst 432296 # Number of instructions bytes read from this memory
|
||||
system.rom.bytes_inst_read::total 432296 # Number of instructions bytes read from this memory
|
||||
system.rom.num_reads::cpu.inst 108074 # Number of read requests responded to by this memory
|
||||
system.rom.num_reads::cpu.data 87049 # Number of read requests responded to by this memory
|
||||
system.rom.num_reads::total 195123 # Number of read requests responded to by this memory
|
||||
system.rom.bw_read::cpu.inst 387054 # Total read bandwidth from this memory (bytes/s)
|
||||
system.rom.bw_read::cpu.data 623511 # Total read bandwidth from this memory (bytes/s)
|
||||
system.rom.bw_read::total 1010564 # Total read bandwidth from this memory (bytes/s)
|
||||
system.rom.bw_inst_read::cpu.inst 387054 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.rom.bw_inst_read::total 387054 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.rom.bw_total::cpu.inst 387054 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.rom.bw_total::cpu.data 623511 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.rom.bw_total::total 1010564 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.nvram.bytes_read::cpu.data 284 # Number of bytes read from this memory
|
||||
system.nvram.bytes_read::total 284 # Number of bytes read from this memory
|
||||
system.nvram.bytes_written::cpu.data 92 # Number of bytes written to this memory
|
||||
system.nvram.bytes_written::total 92 # Number of bytes written to this memory
|
||||
system.nvram.num_reads::cpu.data 284 # Number of read requests responded to by this memory
|
||||
system.nvram.num_reads::total 284 # Number of read requests responded to by this memory
|
||||
system.nvram.num_writes::cpu.data 92 # Number of write requests responded to by this memory
|
||||
system.nvram.num_writes::total 92 # Number of write requests responded to by this memory
|
||||
system.nvram.bw_read::cpu.data 254 # Total read bandwidth from this memory (bytes/s)
|
||||
system.nvram.bw_read::total 254 # Total read bandwidth from this memory (bytes/s)
|
||||
system.nvram.bw_write::cpu.data 82 # Write bandwidth from this memory (bytes/s)
|
||||
system.nvram.bw_write::total 82 # Write bandwidth from this memory (bytes/s)
|
||||
system.nvram.bw_total::cpu.data 337 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.nvram.bw_total::total 337 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bytes_read::cpu.inst 612291324 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 97534024 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 709825348 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 612291324 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 612291324 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::cpu.data 15400223 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 15400223 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 153072831 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 12152054 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 165224885 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::cpu.data 1927067 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 1927067 # Number of write requests responded to by this memory
|
||||
system.physmem.num_other::cpu.data 14 # Number of other requests responded to by this memory
|
||||
system.physmem.num_other::total 14 # Number of other requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 548211557 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 87326534 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 635538091 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 548211557 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 548211557 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::cpu.data 13788502 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 13788502 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 548211557 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 101115036 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 649326593 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem2.bytes_read::cpu.inst 8318106840 # Number of bytes read from this memory
|
||||
system.physmem2.bytes_read::cpu.data 1495885127 # Number of bytes read from this memory
|
||||
system.physmem2.bytes_read::total 9813991967 # Number of bytes read from this memory
|
||||
system.physmem2.bytes_inst_read::cpu.inst 8318106840 # Number of instructions bytes read from this memory
|
||||
system.physmem2.bytes_inst_read::total 8318106840 # Number of instructions bytes read from this memory
|
||||
system.physmem2.bytes_written::cpu.data 897268422 # Number of bytes written to this memory
|
||||
system.physmem2.bytes_written::total 897268422 # Number of bytes written to this memory
|
||||
system.physmem2.num_reads::cpu.inst 2079526710 # Number of read requests responded to by this memory
|
||||
system.physmem2.num_reads::cpu.data 323962420 # Number of read requests responded to by this memory
|
||||
system.physmem2.num_reads::total 2403489130 # Number of read requests responded to by this memory
|
||||
system.physmem2.num_writes::cpu.data 187387796 # Number of write requests responded to by this memory
|
||||
system.physmem2.num_writes::total 187387796 # Number of write requests responded to by this memory
|
||||
system.physmem2.num_other::cpu.data 5403067 # Number of other requests responded to by this memory
|
||||
system.physmem2.num_other::total 5403067 # Number of other requests responded to by this memory
|
||||
system.physmem2.bw_read::cpu.inst 7447569684 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem2.bw_read::cpu.data 1339332247 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem2.bw_read::total 8786901931 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem2.bw_inst_read::cpu.inst 7447569684 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem2.bw_inst_read::total 7447569684 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem2.bw_write::cpu.data 803364182 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem2.bw_write::total 803364182 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem2.bw_total::cpu.inst 7447569684 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem2.bw_total::cpu.data 2142696429 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem2.bw_total::total 9590266113 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu.numCycles 2233777513 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 2228284650 # Number of instructions committed
|
||||
system.cpu.committedOps 2229160714 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 1839325658 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 14608322 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 44037246 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 316367761 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 1839325658 # number of integer instructions
|
||||
system.cpu.num_fp_insts 14608322 # number of float instructions
|
||||
system.cpu.num_int_register_reads 4305540407 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 2100562807 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 35401841 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 22917558 # number of times the floating registers were written
|
||||
system.cpu.num_mem_refs 547951940 # number of memory refs
|
||||
system.cpu.num_load_insts 349807670 # Number of load instructions
|
||||
system.cpu.num_store_insts 198144270 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 2233777513 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
||||
system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
@ -0,0 +1,48 @@
|
||||
cpu
|
||||
|
||||
Sun Fire T2000, No Keyboard
|
||||
Copyright 2006 Sun Microsystems, Inc. All rights reserved.
|
||||
OpenBoot 4.23.0, 256 MB memory available, Serial #1122867.
|
||||
[saidi obp #30]
|
||||
Ethernet address 0:80:3:de:ad:3, Host ID: 80112233.
|
||||
|
||||
|
||||
|
||||
Boot device: /virtual-devices/disk@0 File and args: -vV
|
||||
Loading ufs-file-system package 1.4 04 Aug 1995 13:02:54.
|
||||
FCode UFS Reader 1.12 00/07/17 15:48:16.
|
||||
Loading: /platform/SUNW,Sun-Fire-T2000/ufsboot
|
||||
Loading: /platform/sun4v/ufsboot
|
||||
device path '/virtual-devices@100/disk@0:a'
|
||||
The boot filesystem is logging.
|
||||
The ufs log is empty and will not be used.
|
||||
standalone = `kernel/sparcv9/unix', args = `-v'
|
||||
|Elf64 client
|
||||
Size: /-\|/-\|0x76e40+/-\|/-\|/-\|/-\0x1c872+|/-\0x3123a Bytes
|
||||
modpath: /platform/sun4v/kernel /kernel /usr/kernel
|
||||
|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-module /platform/sun4v/kernel/sparcv9/unix: text at [0x1000000, 0x1076e3f] data at 0x1800000
|
||||
module misc/sparcv9/krtld: text at [0x1076e40, 0x108f737] data at 0x184dab0
|
||||
module /platform/sun4v/kernel/sparcv9/genunix: text at [0x108f738, 0x11dd437] data at 0x18531c0
|
||||
module /platform/sun4v/kernel/misc/sparcv9/platmod: text at [0x11dd438, 0x11dd43f] data at 0x18a4be0
|
||||
module /platform/sun4v/kernel/cpu/sparcv9/SUNW,UltraSPARC-T1: text at [0x11dd440, 0x11e06ff] data at 0x18a5300
|
||||
\
|
||||
SunOS Release 5.10 Version Generic_118822-23 64-bit
|
||||
Copyright 1983-2005 Sun Microsystems, Inc. All rights reserved.
|
||||
Use is subject to license terms.
|
||||
|/-\|/-\|/-\|/-\|/-Ethernet address = 0:80:3:de:ad:3
|
||||
\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/mem = 262144K (0x10000000)
|
||||
avail mem = 237879296
|
||||
root nexus = Sun Fire T2000
|
||||
pseudo0 at root
|
||||
pseudo0 is /pseudo
|
||||
scsi_vhci0 at root
|
||||
scsi_vhci0 is /scsi_vhci
|
||||
virtual-device: hsimd0
|
||||
hsimd0 is /virtual-devices@100/disk@0
|
||||
root on /virtual-devices@100/disk@0:a fstype ufs
|
||||
pseudo-device: dld0
|
||||
dld0 is /pseudo/dld@0
|
||||
cpu0: UltraSPARC-T1 (cpuid 0 clock 5 MHz)
|
||||
iscsi0 at root
|
||||
iscsi0 is /iscsi
|
||||
Hostname: unknown
|
||||
29
simulators/gem5/tests/long/fs/80.solaris-boot/test.py
Normal file
29
simulators/gem5/tests/long/fs/80.solaris-boot/test.py
Normal file
@ -0,0 +1,29 @@
|
||||
# Copyright (c) 2007 The Regents of The University of Michigan
|
||||
# All rights reserved.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are
|
||||
# met: redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer;
|
||||
# redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in the
|
||||
# documentation and/or other materials provided with the distribution;
|
||||
# neither the name of the copyright holders nor the names of its
|
||||
# contributors may be used to endorse or promote products derived from
|
||||
# this software without specific prior written permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
#
|
||||
# Authors: Ali Saidi
|
||||
|
||||
root.system.readfile = os.path.join(tests_root, 'halt.sh')
|
||||
Reference in New Issue
Block a user