Adding gem5 source to svn.
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1819 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
This commit is contained in:
friemel
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,5 @@
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warn: Sockets disabled, not accepting terminal connections
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||||
warn: Sockets disabled, not accepting gdb connections
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||||
warn: Prefetch instructions in Alpha do not do anything
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warn: Prefetch instructions in Alpha do not do anything
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||||
hack: be nice to actually delete the event here
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@ -0,0 +1,13 @@
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gem5 Simulator System. http://gem5.org
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||||
gem5 is copyrighted software; use the --copyright option for details.
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||||
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||||
gem5 compiled Jun 4 2012 11:50:11
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||||
gem5 started Jun 4 2012 14:31:55
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gem5 executing on zizzer
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command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual
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Global frequency set at 1000000000000 ticks per second
|
||||
info: kernel located at: /dist/m5/system/binaries/vmlinux
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||||
0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
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||||
info: Entering event queue @ 0. Starting simulation...
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info: Launching CPU 1 @ 107002000
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||||
Exiting @ tick 1899401490000 because m5_exit instruction encountered
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File diff suppressed because it is too large
Load Diff
@ -0,0 +1,113 @@
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M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
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||||
|
||||
Got Configuration 623
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||||
|
||||
memsize 8000000 pages 4000
|
||||
|
||||
First free page after ROM 0xFFFFFC0000018000
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||||
|
||||
HWRPB 0xFFFFFC0000018000 l1pt 0xFFFFFC0000040000 l2pt 0xFFFFFC0000042000 l3pt_rpb 0xFFFFFC0000044000 l3pt_kernel 0xFFFFFC0000048000 l2reserv 0xFFFFFC0000046000
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||||
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||||
kstart = 0xFFFFFC0000310000, kend = 0xFFFFFC0000855898, kentry = 0xFFFFFC0000310000, numCPUs = 0x2
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||||
|
||||
CPU Clock at 2000 MHz IntrClockFrequency=1024
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||||
|
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Booting with 2 processor(s)
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||||
KSP: 0x20043FE8 PTBR 0x20
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||||
|
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KSP: 0x20043FE8 PTBR 0x20
|
||||
|
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Console Callback at 0x0, fixup at 0x0, crb offset: 0x790
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|
||||
Memory cluster 0 [0 - 392]
|
||||
|
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Memory cluster 1 [392 - 15992]
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|
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Initalizing mdt_bitmap addr 0xFFFFFC0000038000 mem_pages 4000
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ConsoleDispatch at virt 100008D8 phys 188D8 val FFFFFC00000100A8
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Bootstraping CPU 1 with sp=0xFFFFFC0000076000
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unix_boot_mem ends at FFFFFC0000078000
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k_argc = 0
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|
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jumping to kernel at 0xFFFFFC0000310000, (PCBB 0xFFFFFC0000018180 pfn 1067)
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CallbackFixup 0 18000, t7=FFFFFC000070C000
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Entering slaveloop for cpu 1 my_rpb=FFFFFC0000018400
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Linux version 2.6.13 (hsul@zed.eecs.umich.edu) (gcc version 3.4.3) #1 SMP Sun Oct 8 19:52:07 EDT 2006
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||||
|
||||
Booting GENERIC on Tsunami variation DP264 using machine vector DP264 from SRM
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|
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Major Options: SMP LEGACY_START VERBOSE_MCHECK
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|
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Command line: root=/dev/hda1 console=ttyS0
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memcluster 0, usage 1, start 0, end 392
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|
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memcluster 1, usage 0, start 392, end 16384
|
||||
|
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freeing pages 1069:16384
|
||||
|
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reserving pages 1069:1070
|
||||
|
||||
4096K Bcache detected; load hit latency 32 cycles, load miss latency 115 cycles
|
||||
|
||||
SMP: 2 CPUs probed -- cpu_present_mask = 3
|
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|
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Built 1 zonelists
|
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|
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Kernel command line: root=/dev/hda1 console=ttyS0
|
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|
||||
PID hash table entries: 1024 (order: 10, 32768 bytes)
|
||||
|
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Using epoch = 1900
|
||||
|
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Console: colour dummy device 80x25
|
||||
|
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Dentry cache hash table entries: 32768 (order: 5, 262144 bytes)
|
||||
|
||||
Inode-cache hash table entries: 16384 (order: 4, 131072 bytes)
|
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|
||||
Memory: 118784k/131072k available (3314k kernel code, 8952k reserved, 983k data, 224k init)
|
||||
|
||||
Mount-cache hash table entries: 512
|
||||
|
||||
SMP starting up secondaries.
|
||||
|
||||
Slave CPU 1 console command START
|
||||
SlaveCmd: restart FFFFFC0000310020 FFFFFC0000310020 vptb FFFFFFFE00000000 my_rpb FFFFFC0000018400 my_rpb_phys 18400
|
||||
|
||||
Brought up 2 CPUs
|
||||
|
||||
SMP: Total of 2 processors activated (8000.15 BogoMIPS).
|
||||
|
||||
NET: Registered protocol family 16
|
||||
|
||||
EISA bus registered
|
||||
|
||||
pci: enabling save/restore of SRM state
|
||||
|
||||
SCSI subsystem initialized
|
||||
|
||||
srm_env: version 0.0.5 loaded successfully
|
||||
|
||||
Installing knfsd (copyright (C) 1996 okir@monad.swb.de).
|
||||
|
||||
Initializing Cryptographic API
|
||||
|
||||
rtc: Standard PC (1900) epoch (1900) detected
|
||||
|
||||
Real Time Clock Driver v1.12
|
||||
|
||||
Serial: 8250/16550 driver $Revision: 1.90 $ 1 ports, IRQ sharing disabled
|
||||
|
||||
ttyS0 at I/O 0x3f8 (irq = 4) is a 8250
|
||||
|
||||
io scheduler noop registered
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,5 @@
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warn: Sockets disabled, not accepting terminal connections
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: Prefetch instructions in Alpha do not do anything
|
||||
warn: Prefetch instructions in Alpha do not do anything
|
||||
hack: be nice to actually delete the event here
|
||||
@ -0,0 +1,12 @@
|
||||
gem5 Simulator System. http://gem5.org
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gem5 is copyrighted software; use the --copyright option for details.
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||||
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gem5 compiled Jun 4 2012 11:50:11
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gem5 started Jun 4 2012 14:16:04
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gem5 executing on zizzer
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command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3
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Global frequency set at 1000000000000 ticks per second
|
||||
info: kernel located at: /dist/m5/system/binaries/vmlinux
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0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
|
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info: Entering event queue @ 0. Starting simulation...
|
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Exiting @ tick 1858684403000 because m5_exit instruction encountered
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File diff suppressed because it is too large
Load Diff
@ -0,0 +1,108 @@
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||||
M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
|
||||
|
||||
Got Configuration 623
|
||||
|
||||
memsize 8000000 pages 4000
|
||||
|
||||
First free page after ROM 0xFFFFFC0000018000
|
||||
|
||||
HWRPB 0xFFFFFC0000018000 l1pt 0xFFFFFC0000040000 l2pt 0xFFFFFC0000042000 l3pt_rpb 0xFFFFFC0000044000 l3pt_kernel 0xFFFFFC0000048000 l2reserv 0xFFFFFC0000046000
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||||
|
||||
kstart = 0xFFFFFC0000310000, kend = 0xFFFFFC0000855898, kentry = 0xFFFFFC0000310000, numCPUs = 0x1
|
||||
|
||||
CPU Clock at 2000 MHz IntrClockFrequency=1024
|
||||
|
||||
Booting with 1 processor(s)
|
||||
|
||||
KSP: 0x20043FE8 PTBR 0x20
|
||||
|
||||
Console Callback at 0x0, fixup at 0x0, crb offset: 0x510
|
||||
|
||||
Memory cluster 0 [0 - 392]
|
||||
|
||||
Memory cluster 1 [392 - 15992]
|
||||
|
||||
Initalizing mdt_bitmap addr 0xFFFFFC0000038000 mem_pages 4000
|
||||
|
||||
ConsoleDispatch at virt 10000658 phys 18658 val FFFFFC00000100A8
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||||
|
||||
unix_boot_mem ends at FFFFFC0000076000
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||||
|
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k_argc = 0
|
||||
|
||||
jumping to kernel at 0xFFFFFC0000310000, (PCBB 0xFFFFFC0000018180 pfn 1067)
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||||
|
||||
CallbackFixup 0 18000, t7=FFFFFC000070C000
|
||||
|
||||
Linux version 2.6.13 (hsul@zed.eecs.umich.edu) (gcc version 3.4.3) #1 SMP Sun Oct 8 19:52:07 EDT 2006
|
||||
|
||||
Booting GENERIC on Tsunami variation DP264 using machine vector DP264 from SRM
|
||||
|
||||
Major Options: SMP LEGACY_START VERBOSE_MCHECK
|
||||
|
||||
Command line: root=/dev/hda1 console=ttyS0
|
||||
|
||||
memcluster 0, usage 1, start 0, end 392
|
||||
|
||||
memcluster 1, usage 0, start 392, end 16384
|
||||
|
||||
freeing pages 1069:16384
|
||||
|
||||
reserving pages 1069:1070
|
||||
|
||||
4096K Bcache detected; load hit latency 32 cycles, load miss latency 115 cycles
|
||||
|
||||
SMP: 1 CPUs probed -- cpu_present_mask = 1
|
||||
|
||||
Built 1 zonelists
|
||||
|
||||
Kernel command line: root=/dev/hda1 console=ttyS0
|
||||
|
||||
PID hash table entries: 1024 (order: 10, 32768 bytes)
|
||||
|
||||
Using epoch = 1900
|
||||
|
||||
Console: colour dummy device 80x25
|
||||
|
||||
Dentry cache hash table entries: 32768 (order: 5, 262144 bytes)
|
||||
|
||||
Inode-cache hash table entries: 16384 (order: 4, 131072 bytes)
|
||||
|
||||
Memory: 118784k/131072k available (3314k kernel code, 8952k reserved, 983k data, 224k init)
|
||||
|
||||
Mount-cache hash table entries: 512
|
||||
|
||||
SMP mode deactivated.
|
||||
|
||||
Brought up 1 CPUs
|
||||
|
||||
SMP: Total of 1 processors activated (4002.20 BogoMIPS).
|
||||
|
||||
NET: Registered protocol family 16
|
||||
|
||||
EISA bus registered
|
||||
|
||||
pci: enabling save/restore of SRM state
|
||||
|
||||
SCSI subsystem initialized
|
||||
|
||||
srm_env: version 0.0.5 loaded successfully
|
||||
|
||||
Installing knfsd (copyright (C) 1996 okir@monad.swb.de).
|
||||
|
||||
Initializing Cryptographic API
|
||||
|
||||
rtc: Standard PC (1900) epoch (1900) detected
|
||||
|
||||
Real Time Clock Driver v1.12
|
||||
|
||||
Serial: 8250/16550 driver $Revision: 1.90 $ 1 ports, IRQ sharing disabled
|
||||
|
||||
ttyS0 at I/O 0x3f8 (irq = 4) is a 8250
|
||||
|
||||
io scheduler noop registered
|
||||
|
||||
io scheduler anticipatory registered
|
||||
|
||||
io scheduler deadline registered
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,26 @@
|
||||
warn: Sockets disabled, not accepting vnc client connections
|
||||
warn: Sockets disabled, not accepting terminal connections
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: The clidr register always reports 0 caches.
|
||||
warn: clidr LoUIS field of 0b001 to match current ARM implementations.
|
||||
warn: The csselr register isn't implemented.
|
||||
warn: The ccsidr register isn't implemented and always reads as 0.
|
||||
warn: instruction 'mcr bpiallis' unimplemented
|
||||
warn: instruction 'mcr icialluis' unimplemented
|
||||
warn: instruction 'mcr dccimvac' unimplemented
|
||||
warn: instruction 'mcr dccmvau' unimplemented
|
||||
warn: instruction 'mcr icimvau' unimplemented
|
||||
warn: 5654850500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3704, checker: 0x3708
|
||||
warn: 5664849500: Instruction results do not match! (Values may not actually be integers) Inst: 0x36c4, checker: 0x36c8
|
||||
warn: 5704830500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3604, checker: 0x3608
|
||||
warn: 5721485500: Instruction results do not match! (Values may not actually be integers) Inst: 0x35c4, checker: 0x35c8
|
||||
warn: 6170779000: Instruction results do not match! (Values may not actually be integers) Inst: 0x34f0, checker: 0x34f8
|
||||
warn: LCD dual screen mode not supported
|
||||
warn: 53396857000: Instruction results do not match! (Values may not actually be integers) Inst: 0x19dc, checker: 0x1a04
|
||||
warn: 55147144000: Instruction results do not match! (Values may not actually be integers) Inst: 0x80d0, checker: 0xc71f6fc8
|
||||
warn: 55147144000: Instruction results do not match! (Values may not actually be integers) Inst: 0x71ef0, checker: 0x60000013
|
||||
warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
|
||||
warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
|
||||
warn: instruction 'mcr icialluis' unimplemented
|
||||
warn: instruction 'mcr bpiallis' unimplemented
|
||||
hack: be nice to actually delete the event here
|
||||
@ -0,0 +1,12 @@
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jun 4 2012 12:14:06
|
||||
gem5 started Jun 4 2012 18:58:44
|
||||
gem5 executing on zizzer
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
|
||||
info: Using bootloader at address 0x80000000
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 2501685689500 because m5_exit instruction encountered
|
||||
@ -0,0 +1,985 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 2.501686 # Number of seconds simulated
|
||||
sim_ticks 2501685689500 # Number of ticks simulated
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||||
final_tick 2501685689500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 49441 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 63837 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2075989543 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 387400 # Number of bytes of host memory used
|
||||
host_seconds 1205.06 # Real time elapsed on the host
|
||||
sim_insts 59579009 # Number of instructions simulated
|
||||
sim_ops 76926775 # Number of ops (including micro ops) simulated
|
||||
system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory
|
||||
system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory
|
||||
system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory
|
||||
system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory
|
||||
system.realview.nvmem.num_reads::cpu.inst 1 # Number of read requests responded to by this memory
|
||||
system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory
|
||||
system.realview.nvmem.bw_read::cpu.inst 26 # Total read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_read::total 26 # Total read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_inst_read::cpu.inst 26 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_inst_read::total 26 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_total::cpu.inst 26 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_total::total 26 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bytes_read::realview.clcd 118440096 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.dtb.walker 12032 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.itb.walker 896 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.inst 1119872 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 10085712 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 129658608 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 1119872 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 1119872 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 6569664 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 9585736 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::realview.clcd 14805012 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.dtb.walker 188 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.itb.walker 14 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.inst 17498 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 157623 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 14980335 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 102651 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 856669 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::realview.clcd 47344115 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.dtb.walker 4810 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.itb.walker 358 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 447647 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 4031566 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 51828496 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 447647 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 447647 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 2626095 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::cpu.data 1205616 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 3831711 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 2626095 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::realview.clcd 47344115 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.dtb.walker 4810 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.itb.walker 358 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 447647 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 5237182 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 55660207 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.l2c.replacements 119797 # number of replacements
|
||||
system.l2c.tagsinuse 26022.811009 # Cycle average of tags in use
|
||||
system.l2c.total_refs 1834134 # Total number of references to valid blocks.
|
||||
system.l2c.sampled_refs 150735 # Sample count of references to valid blocks.
|
||||
system.l2c.avg_refs 12.167937 # Average number of references to valid blocks.
|
||||
system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.l2c.occ_blocks::writebacks 14260.921168 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu.dtb.walker 79.122472 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu.itb.walker 1.014068 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu.inst 6176.146101 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu.data 5505.607200 # Average occupied blocks per requestor
|
||||
system.l2c.occ_percent::writebacks 0.217604 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu.dtb.walker 0.001207 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu.itb.walker 0.000015 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu.inst 0.094241 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu.data 0.084009 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::total 0.397077 # Average percentage of cache occupancy
|
||||
system.l2c.ReadReq_hits::cpu.dtb.walker 144170 # number of ReadReq hits
|
||||
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|
||||
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|
||||
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|
||||
system.l2c.ReadReq_hits::total 1536133 # number of ReadReq hits
|
||||
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|
||||
system.l2c.Writeback_hits::total 635023 # number of Writeback hits
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
system.l2c.demand_hits::cpu.inst 1001175 # number of demand (read+write) hits
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
system.l2c.overall_hits::cpu.inst 1001175 # number of overall hits
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
system.l2c.overall_misses::cpu.inst 17378 # number of overall misses
|
||||
system.l2c.overall_misses::cpu.data 159472 # number of overall misses
|
||||
system.l2c.overall_misses::total 177053 # number of overall misses
|
||||
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|
||||
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|
||||
system.l2c.ReadReq_miss_latency::cpu.inst 910079500 # number of ReadReq miss cycles
|
||||
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|
||||
system.l2c.ReadReq_miss_latency::total 1922778000 # number of ReadReq miss cycles
|
||||
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|
||||
system.l2c.UpgradeReq_miss_latency::total 996000 # number of UpgradeReq miss cycles
|
||||
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|
||||
system.l2c.SCUpgradeReq_miss_latency::total 104000 # number of SCUpgradeReq miss cycles
|
||||
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|
||||
system.l2c.ReadExReq_miss_latency::total 7365557000 # number of ReadExReq miss cycles
|
||||
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|
||||
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|
||||
system.l2c.demand_miss_latency::cpu.inst 910079500 # number of demand (read+write) miss cycles
|
||||
system.l2c.demand_miss_latency::cpu.data 8367653000 # number of demand (read+write) miss cycles
|
||||
system.l2c.demand_miss_latency::total 9288335000 # number of demand (read+write) miss cycles
|
||||
system.l2c.overall_miss_latency::cpu.dtb.walker 9850500 # number of overall miss cycles
|
||||
system.l2c.overall_miss_latency::cpu.itb.walker 752000 # number of overall miss cycles
|
||||
system.l2c.overall_miss_latency::cpu.inst 910079500 # number of overall miss cycles
|
||||
system.l2c.overall_miss_latency::cpu.data 8367653000 # number of overall miss cycles
|
||||
system.l2c.overall_miss_latency::total 9288335000 # number of overall miss cycles
|
||||
system.l2c.ReadReq_accesses::cpu.dtb.walker 144359 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::cpu.itb.walker 12506 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::cpu.inst 1018553 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::cpu.data 397476 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::total 1572894 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.Writeback_accesses::writebacks 635023 # number of Writeback accesses(hits+misses)
|
||||
system.l2c.Writeback_accesses::total 635023 # number of Writeback accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_accesses::cpu.data 3345 # number of UpgradeReq accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_accesses::total 3345 # number of UpgradeReq accesses(hits+misses)
|
||||
system.l2c.SCUpgradeReq_accesses::cpu.data 13 # number of SCUpgradeReq accesses(hits+misses)
|
||||
system.l2c.SCUpgradeReq_accesses::total 13 # number of SCUpgradeReq accesses(hits+misses)
|
||||
system.l2c.ReadExReq_accesses::cpu.data 246167 # number of ReadExReq accesses(hits+misses)
|
||||
system.l2c.ReadExReq_accesses::total 246167 # number of ReadExReq accesses(hits+misses)
|
||||
system.l2c.demand_accesses::cpu.dtb.walker 144359 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu.itb.walker 12506 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu.inst 1018553 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu.data 643643 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::total 1819061 # number of demand (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu.dtb.walker 144359 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu.itb.walker 12506 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu.inst 1018553 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu.data 643643 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::total 1819061 # number of overall (read+write) accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.001309 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.001119 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu.inst 0.017061 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu.data 0.048254 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::total 0.023372 # miss rate for ReadReq accesses
|
||||
system.l2c.UpgradeReq_miss_rate::cpu.data 0.986547 # miss rate for UpgradeReq accesses
|
||||
system.l2c.UpgradeReq_miss_rate::total 0.986547 # miss rate for UpgradeReq accesses
|
||||
system.l2c.SCUpgradeReq_miss_rate::cpu.data 0.384615 # miss rate for SCUpgradeReq accesses
|
||||
system.l2c.SCUpgradeReq_miss_rate::total 0.384615 # miss rate for SCUpgradeReq accesses
|
||||
system.l2c.ReadExReq_miss_rate::cpu.data 0.569906 # miss rate for ReadExReq accesses
|
||||
system.l2c.ReadExReq_miss_rate::total 0.569906 # miss rate for ReadExReq accesses
|
||||
system.l2c.demand_miss_rate::cpu.dtb.walker 0.001309 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu.itb.walker 0.001119 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu.inst 0.017061 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu.data 0.247765 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::total 0.097332 # miss rate for demand accesses
|
||||
system.l2c.overall_miss_rate::cpu.dtb.walker 0.001309 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu.itb.walker 0.001119 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu.inst 0.017061 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu.data 0.247765 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::total 0.097332 # miss rate for overall accesses
|
||||
system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52119.047619 # average ReadReq miss latency
|
||||
system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 53714.285714 # average ReadReq miss latency
|
||||
system.l2c.ReadReq_avg_miss_latency::cpu.inst 52369.634020 # average ReadReq miss latency
|
||||
system.l2c.ReadReq_avg_miss_latency::cpu.data 52246.923879 # average ReadReq miss latency
|
||||
system.l2c.ReadReq_avg_miss_latency::total 52304.833927 # average ReadReq miss latency
|
||||
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|
||||
system.l2c.UpgradeReq_avg_miss_latency::total 301.818182 # average UpgradeReq miss latency
|
||||
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|
||||
system.l2c.SCUpgradeReq_avg_miss_latency::total 20800 # average SCUpgradeReq miss latency
|
||||
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|
||||
system.l2c.ReadExReq_avg_miss_latency::total 52501.618054 # average ReadExReq miss latency
|
||||
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|
||||
system.l2c.demand_avg_miss_latency::cpu.itb.walker 53714.285714 # average overall miss latency
|
||||
system.l2c.demand_avg_miss_latency::cpu.inst 52369.634020 # average overall miss latency
|
||||
system.l2c.demand_avg_miss_latency::cpu.data 52470.985502 # average overall miss latency
|
||||
system.l2c.demand_avg_miss_latency::total 52460.760337 # average overall miss latency
|
||||
system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52119.047619 # average overall miss latency
|
||||
system.l2c.overall_avg_miss_latency::cpu.itb.walker 53714.285714 # average overall miss latency
|
||||
system.l2c.overall_avg_miss_latency::cpu.inst 52369.634020 # average overall miss latency
|
||||
system.l2c.overall_avg_miss_latency::cpu.data 52470.985502 # average overall miss latency
|
||||
system.l2c.overall_avg_miss_latency::total 52460.760337 # average overall miss latency
|
||||
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.l2c.fast_writes 0 # number of fast writes performed
|
||||
system.l2c.cache_copies 0 # number of cache copies performed
|
||||
system.l2c.writebacks::writebacks 102651 # number of writebacks
|
||||
system.l2c.writebacks::total 102651 # number of writebacks
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
system.l2c.demand_mshr_misses::cpu.inst 17364 # number of demand (read+write) MSHR misses
|
||||
system.l2c.demand_mshr_misses::cpu.data 159386 # number of demand (read+write) MSHR misses
|
||||
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|
||||
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|
||||
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|
||||
system.l2c.overall_mshr_misses::cpu.inst 17364 # number of overall MSHR misses
|
||||
system.l2c.overall_mshr_misses::cpu.data 159386 # number of overall MSHR misses
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
system.l2c.demand_mshr_miss_latency::total 7093247500 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency::cpu.dtb.walker 7532000 # number of overall MSHR miss cycles
|
||||
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|
||||
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|
||||
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|
||||
system.l2c.overall_mshr_miss_latency::total 7093247500 # number of overall MSHR miss cycles
|
||||
system.l2c.ReadReq_mshr_uncacheable_latency::cpu.inst 5427000 # number of ReadReq MSHR uncacheable cycles
|
||||
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|
||||
system.l2c.ReadReq_mshr_uncacheable_latency::total 131764013500 # number of ReadReq MSHR uncacheable cycles
|
||||
system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 32346095899 # number of WriteReq MSHR uncacheable cycles
|
||||
system.l2c.WriteReq_mshr_uncacheable_latency::total 32346095899 # number of WriteReq MSHR uncacheable cycles
|
||||
system.l2c.overall_mshr_uncacheable_latency::cpu.inst 5427000 # number of overall MSHR uncacheable cycles
|
||||
system.l2c.overall_mshr_uncacheable_latency::cpu.data 164104682399 # number of overall MSHR uncacheable cycles
|
||||
system.l2c.overall_mshr_uncacheable_latency::total 164110109399 # number of overall MSHR uncacheable cycles
|
||||
system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001302 # mshr miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001119 # mshr miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.017048 # mshr miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.048038 # mshr miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_mshr_miss_rate::total 0.023307 # mshr miss rate for ReadReq accesses
|
||||
system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.986547 # mshr miss rate for UpgradeReq accesses
|
||||
system.l2c.UpgradeReq_mshr_miss_rate::total 0.986547 # mshr miss rate for UpgradeReq accesses
|
||||
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu.data 0.384615 # mshr miss rate for SCUpgradeReq accesses
|
||||
system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.384615 # mshr miss rate for SCUpgradeReq accesses
|
||||
system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.569906 # mshr miss rate for ReadExReq accesses
|
||||
system.l2c.ReadExReq_mshr_miss_rate::total 0.569906 # mshr miss rate for ReadExReq accesses
|
||||
system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.001302 # mshr miss rate for demand accesses
|
||||
system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.001119 # mshr miss rate for demand accesses
|
||||
system.l2c.demand_mshr_miss_rate::cpu.inst 0.017048 # mshr miss rate for demand accesses
|
||||
system.l2c.demand_mshr_miss_rate::cpu.data 0.247631 # mshr miss rate for demand accesses
|
||||
system.l2c.demand_mshr_miss_rate::total 0.097277 # mshr miss rate for demand accesses
|
||||
system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.001302 # mshr miss rate for overall accesses
|
||||
system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.001119 # mshr miss rate for overall accesses
|
||||
system.l2c.overall_mshr_miss_rate::cpu.inst 0.017048 # mshr miss rate for overall accesses
|
||||
system.l2c.overall_mshr_miss_rate::cpu.data 0.247631 # mshr miss rate for overall accesses
|
||||
system.l2c.overall_mshr_miss_rate::total 0.097277 # mshr miss rate for overall accesses
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40063.829787 # average ReadReq mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 41714.285714 # average ReadReq mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40163.902327 # average ReadReq mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40096.522468 # average ReadReq mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::total 40128.887070 # average ReadReq mshr miss latency
|
||||
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40266.666667 # average UpgradeReq mshr miss latency
|
||||
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40266.666667 # average UpgradeReq mshr miss latency
|
||||
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 40000 # average SCUpgradeReq mshr miss latency
|
||||
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40000 # average SCUpgradeReq mshr miss latency
|
||||
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40074.434038 # average ReadExReq mshr miss latency
|
||||
system.l2c.ReadExReq_avg_mshr_miss_latency::total 40074.434038 # average ReadExReq mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40063.829787 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 41714.285714 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40163.902327 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu.data 40077.080170 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::total 40085.715335 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40063.829787 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 41714.285714 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40163.902327 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu.data 40077.080170 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::total 40085.715335 # average overall mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
|
||||
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
|
||||
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
||||
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
|
||||
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
||||
system.l2c.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
|
||||
system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
|
||||
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
||||
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
||||
system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
|
||||
system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
|
||||
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
|
||||
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
|
||||
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
|
||||
system.cpu.checker.dtb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.checker.dtb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.checker.dtb.read_hits 15048343 # DTB read hits
|
||||
system.cpu.checker.dtb.read_misses 7305 # DTB read misses
|
||||
system.cpu.checker.dtb.write_hits 11293933 # DTB write hits
|
||||
system.cpu.checker.dtb.write_misses 2191 # DTB write misses
|
||||
system.cpu.checker.dtb.flush_tlb 4 # Number of times complete TLB was flushed
|
||||
system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.checker.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.checker.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID
|
||||
system.cpu.checker.dtb.flush_entries 6410 # Number of entries that have been flushed from TLB
|
||||
system.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.checker.dtb.prefetch_faults 177 # Number of TLB faults due to prefetch
|
||||
system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.checker.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.checker.dtb.read_accesses 15055648 # DTB read accesses
|
||||
system.cpu.checker.dtb.write_accesses 11296124 # DTB write accesses
|
||||
system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses
|
||||
system.cpu.checker.dtb.hits 26342276 # DTB hits
|
||||
system.cpu.checker.dtb.misses 9496 # DTB misses
|
||||
system.cpu.checker.dtb.accesses 26351772 # DTB accesses
|
||||
system.cpu.checker.itb.inst_hits 60745631 # ITB inst hits
|
||||
system.cpu.checker.itb.inst_misses 4471 # ITB inst misses
|
||||
system.cpu.checker.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.checker.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.checker.itb.write_hits 0 # DTB write hits
|
||||
system.cpu.checker.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.checker.itb.flush_tlb 4 # Number of times complete TLB was flushed
|
||||
system.cpu.checker.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.checker.itb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.checker.itb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID
|
||||
system.cpu.checker.itb.flush_entries 4682 # Number of entries that have been flushed from TLB
|
||||
system.cpu.checker.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.checker.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu.checker.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.checker.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.checker.itb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.checker.itb.inst_accesses 60750102 # ITB inst accesses
|
||||
system.cpu.checker.itb.hits 60745631 # DTB hits
|
||||
system.cpu.checker.itb.misses 4471 # DTB misses
|
||||
system.cpu.checker.itb.accesses 60750102 # DTB accesses
|
||||
system.cpu.checker.numCycles 77205204 # number of cpu cycles simulated
|
||||
system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.dtb.read_hits 52103903 # DTB read hits
|
||||
system.cpu.dtb.read_misses 93079 # DTB read misses
|
||||
system.cpu.dtb.write_hits 11946241 # DTB write hits
|
||||
system.cpu.dtb.write_misses 25022 # DTB write misses
|
||||
system.cpu.dtb.flush_tlb 4 # Number of times complete TLB was flushed
|
||||
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID
|
||||
system.cpu.dtb.flush_entries 8141 # Number of entries that have been flushed from TLB
|
||||
system.cpu.dtb.align_faults 5562 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.dtb.prefetch_faults 707 # Number of TLB faults due to prefetch
|
||||
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.dtb.perms_faults 2799 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.dtb.read_accesses 52196982 # DTB read accesses
|
||||
system.cpu.dtb.write_accesses 11971263 # DTB write accesses
|
||||
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
|
||||
system.cpu.dtb.hits 64050144 # DTB hits
|
||||
system.cpu.dtb.misses 118101 # DTB misses
|
||||
system.cpu.dtb.accesses 64168245 # DTB accesses
|
||||
system.cpu.itb.inst_hits 13717584 # ITB inst hits
|
||||
system.cpu.itb.inst_misses 12272 # ITB inst misses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.write_hits 0 # DTB write hits
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.itb.flush_tlb 4 # Number of times complete TLB was flushed
|
||||
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.itb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.itb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID
|
||||
system.cpu.itb.flush_entries 5306 # Number of entries that have been flushed from TLB
|
||||
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.itb.perms_faults 6863 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.itb.inst_accesses 13729856 # ITB inst accesses
|
||||
system.cpu.itb.hits 13717584 # DTB hits
|
||||
system.cpu.itb.misses 12272 # DTB misses
|
||||
system.cpu.itb.accesses 13729856 # DTB accesses
|
||||
system.cpu.numCycles 411352060 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.BPredUnit.lookups 15654738 # Number of BP lookups
|
||||
system.cpu.BPredUnit.condPredicted 12362397 # Number of conditional branches predicted
|
||||
system.cpu.BPredUnit.condIncorrect 932839 # Number of conditional branches incorrect
|
||||
system.cpu.BPredUnit.BTBLookups 10530768 # Number of BTB lookups
|
||||
system.cpu.BPredUnit.BTBHits 8288874 # Number of BTB hits
|
||||
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu.BPredUnit.usedRAS 1329017 # Number of times the RAS was used to get a target.
|
||||
system.cpu.BPredUnit.RASInCorrect 195537 # Number of incorrect RAS predictions.
|
||||
system.cpu.fetch.icacheStallCycles 33116930 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.Insts 103031700 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.Branches 15654738 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.predictedBranches 9617891 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.Cycles 22620194 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.SquashCycles 6706106 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.TlbCycles 163882 # Number of cycles fetch has spent waiting for tlb
|
||||
system.cpu.fetch.BlockedCycles 89861042 # Number of cycles fetch has spent blocked
|
||||
system.cpu.fetch.MiscStallCycles 2823 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
||||
system.cpu.fetch.PendingTrapStallCycles 147160 # Number of stall cycles due to pending traps
|
||||
system.cpu.fetch.PendingQuiesceStallCycles 218224 # Number of stall cycles due to pending quiesce instructions
|
||||
system.cpu.fetch.IcacheWaitRetryStallCycles 462 # Number of stall cycles due to full MSHR
|
||||
system.cpu.fetch.CacheLines 13709942 # Number of cache lines fetched
|
||||
system.cpu.fetch.IcacheSquashes 998560 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.ItlbSquashes 6868 # Number of outstanding ITLB misses that were squashed
|
||||
system.cpu.fetch.rateDist::samples 150746244 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 0.848897 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 2.234280 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 128142810 85.01% 85.01% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 1478319 0.98% 85.99% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 1855018 1.23% 87.22% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 2695901 1.79% 89.01% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 1893540 1.26% 90.26% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 1191101 0.79% 91.05% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 2951659 1.96% 93.01% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 850848 0.56% 93.57% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 9687048 6.43% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::total 150746244 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.branchRate 0.038057 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.rate 0.250471 # Number of inst fetches per cycle
|
||||
system.cpu.decode.IdleCycles 35228906 # Number of cycles decode is idle
|
||||
system.cpu.decode.BlockedCycles 89710063 # Number of cycles decode is blocked
|
||||
system.cpu.decode.RunCycles 20347806 # Number of cycles decode is running
|
||||
system.cpu.decode.UnblockCycles 1026685 # Number of cycles decode is unblocking
|
||||
system.cpu.decode.SquashCycles 4432784 # Number of cycles decode is squashing
|
||||
system.cpu.decode.BranchResolved 2275641 # Number of times decode resolved a branch
|
||||
system.cpu.decode.BranchMispred 186729 # Number of times decode detected a branch misprediction
|
||||
system.cpu.decode.DecodedInsts 120042439 # Number of instructions handled by decode
|
||||
system.cpu.decode.SquashedInsts 604390 # Number of squashed instructions handled by decode
|
||||
system.cpu.rename.SquashCycles 4432784 # Number of cycles rename is squashing
|
||||
system.cpu.rename.IdleCycles 37305734 # Number of cycles rename is idle
|
||||
system.cpu.rename.BlockCycles 37165628 # Number of cycles rename is blocking
|
||||
system.cpu.rename.serializeStallCycles 46502465 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RunCycles 19251695 # Number of cycles rename is running
|
||||
system.cpu.rename.UnblockCycles 6087938 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RenamedInsts 112539597 # Number of instructions processed by rename
|
||||
system.cpu.rename.ROBFullEvents 3873 # Number of times rename has blocked due to ROB full
|
||||
system.cpu.rename.IQFullEvents 1013212 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.LSQFullEvents 4109157 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.FullRegisterEvents 45575 # Number of times there has been no free registers
|
||||
system.cpu.rename.RenamedOperands 117156815 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RenameLookups 517555842 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.int_rename_lookups 517460811 # Number of integer rename lookups
|
||||
system.cpu.rename.fp_rename_lookups 95031 # Number of floating rename lookups
|
||||
system.cpu.rename.CommittedMaps 77687687 # Number of HB maps that are committed
|
||||
system.cpu.rename.UndoneMaps 39469127 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.serializingInsts 939790 # count of serializing insts renamed
|
||||
system.cpu.rename.tempSerializingInsts 835958 # count of temporary serializing insts renamed
|
||||
system.cpu.rename.skidInsts 12443241 # count of insts added to the skid buffer
|
||||
system.cpu.memDep0.insertedLoads 21685850 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 14072237 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.conflictingLoads 1938675 # Number of conflicting loads.
|
||||
system.cpu.memDep0.conflictingStores 2482763 # Number of conflicting stores.
|
||||
system.cpu.iq.iqInstsAdded 102391550 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqNonSpecInstsAdded 1619583 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqInstsIssued 126350622 # Number of instructions issued
|
||||
system.cpu.iq.iqSquashedInstsIssued 234593 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedInstsExamined 26254924 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedOperandsExamined 71509700 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 332277 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.issued_per_cycle::samples 150746244 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::mean 0.838168 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::stdev 1.542455 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::0 105470655 69.97% 69.97% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::1 14086510 9.34% 79.31% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::2 7371222 4.89% 84.20% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::3 5923402 3.93% 88.13% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::4 12762751 8.47% 96.60% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::5 2810704 1.86% 98.46% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::6 1735902 1.15% 99.61% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::7 449258 0.30% 99.91% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::8 135840 0.09% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::total 150746244 # Number of insts issued each cycle
|
||||
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntAlu 61043 0.69% 0.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntMult 4 0.00% 0.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntDiv 0 0.00% 0.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatMult 0 0.00% 0.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdMult 0 0.00% 0.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdShift 0 0.00% 0.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::MemRead 8421186 94.66% 95.34% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::MemWrite 414230 4.66% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.FU_type_0::No_OpClass 106530 0.08% 0.08% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntAlu 59762768 47.30% 47.38% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntMult 95812 0.08% 47.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdMisc 38 0.00% 47.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdShift 45 0.00% 47.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdShiftAcc 9 0.00% 47.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMisc 2279 0.00% 47.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMultAcc 9 0.00% 47.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::MemRead 53776494 42.56% 90.02% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::MemWrite 12606638 9.98% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::total 126350622 # Type of FU issued
|
||||
system.cpu.iq.rate 0.307159 # Inst issue rate
|
||||
system.cpu.iq.fu_busy_cnt 8896463 # FU busy when requested
|
||||
system.cpu.iq.fu_busy_rate 0.070411 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.int_inst_queue_reads 412671946 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_writes 130285978 # Number of integer instruction queue writes
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 87040433 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.fp_inst_queue_reads 24078 # Number of floating instruction queue reads
|
||||
system.cpu.iq.fp_inst_queue_writes 13182 # Number of floating instruction queue writes
|
||||
system.cpu.iq.fp_inst_queue_wakeup_accesses 10434 # Number of floating instruction queue wakeup accesses
|
||||
system.cpu.iq.int_alu_accesses 135127716 # Number of integer alu accesses
|
||||
system.cpu.iq.fp_alu_accesses 12839 # Number of floating point alu accesses
|
||||
system.cpu.iew.lsq.thread0.forwLoads 636069 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread0.squashedLoads 5970496 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread0.ignoredResponses 11101 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread0.memOrderViolation 34253 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread0.squashedStores 2273952 # Number of stores squashed
|
||||
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
||||
system.cpu.iew.lsq.thread0.rescheduledLoads 34114355 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread0.cacheBlocked 1152098 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||||
system.cpu.iew.iewSquashCycles 4432784 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewBlockCycles 28604721 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewUnblockCycles 436722 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.iewDispatchedInsts 104273041 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewDispSquashedInsts 335924 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispLoadInsts 21685850 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispStoreInsts 14072237 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 992808 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewIQFullEvents 95700 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.iewLSQFullEvents 11591 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.memOrderViolationEvents 34253 # Number of memory order violations
|
||||
system.cpu.iew.predictedTakenIncorrect 552378 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.iew.predictedNotTakenIncorrect 346914 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.branchMispredicts 899292 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewExecutedInsts 123108789 # Number of executed instructions
|
||||
system.cpu.iew.iewExecLoadInsts 52799372 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 3241833 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
||||
system.cpu.iew.exec_nop 261908 # number of nop insts executed
|
||||
system.cpu.iew.exec_refs 65255060 # number of memory reference insts executed
|
||||
system.cpu.iew.exec_branches 11601340 # Number of branches executed
|
||||
system.cpu.iew.exec_stores 12455688 # Number of stores executed
|
||||
system.cpu.iew.exec_rate 0.299278 # Inst execution rate
|
||||
system.cpu.iew.wb_sent 121555618 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.wb_count 87050867 # cumulative count of insts written-back
|
||||
system.cpu.iew.wb_producers 47546734 # num instructions producing a value
|
||||
system.cpu.iew.wb_consumers 88572059 # num instructions consuming a value
|
||||
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
||||
system.cpu.iew.wb_rate 0.211621 # insts written-back per cycle
|
||||
system.cpu.iew.wb_fanout 0.536814 # average fanout of values written-back
|
||||
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||
system.cpu.commit.commitCommittedInsts 59729390 # The number of committed instructions
|
||||
system.cpu.commit.commitCommittedOps 77077156 # The number of committed instructions
|
||||
system.cpu.commit.commitSquashedInsts 27015439 # The number of squashed insts skipped by commit
|
||||
system.cpu.commit.commitNonSpecStalls 1287306 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu.commit.branchMispredicts 793496 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.committed_per_cycle::samples 146395876 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::mean 0.526498 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::stdev 1.504904 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::0 118626341 81.03% 81.03% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::1 13714527 9.37% 90.40% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::2 3991808 2.73% 93.13% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::3 2249419 1.54% 94.66% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::4 1746576 1.19% 95.86% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::5 1042045 0.71% 96.57% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::6 1550885 1.06% 97.63% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::7 665283 0.45% 98.08% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::8 2808992 1.92% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::total 146395876 # Number of insts commited each cycle
|
||||
system.cpu.commit.committedInsts 59729390 # Number of instructions committed
|
||||
system.cpu.commit.committedOps 77077156 # Number of ops (including micro ops) committed
|
||||
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
||||
system.cpu.commit.refs 27513639 # Number of memory references committed
|
||||
system.cpu.commit.loads 15715354 # Number of loads committed
|
||||
system.cpu.commit.membars 413068 # Number of memory barriers committed
|
||||
system.cpu.commit.branches 9904424 # Number of branches committed
|
||||
system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions.
|
||||
system.cpu.commit.int_insts 68617835 # Number of committed integer instructions.
|
||||
system.cpu.commit.function_calls 995976 # Number of function calls committed.
|
||||
system.cpu.commit.bw_lim_events 2808992 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
||||
system.cpu.rob.rob_reads 245922084 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 212744706 # The number of ROB writes
|
||||
system.cpu.timesIdled 1895448 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 260605816 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.quiesceCycles 4591931267 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
|
||||
system.cpu.committedInsts 59579009 # Number of Instructions Simulated
|
||||
system.cpu.committedOps 76926775 # Number of Ops (including micro ops) Simulated
|
||||
system.cpu.committedInsts_total 59579009 # Number of Instructions Simulated
|
||||
system.cpu.cpi 6.904312 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 6.904312 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 0.144837 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.144837 # IPC: Total IPC of All Threads
|
||||
system.cpu.int_regfile_reads 558200785 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 89400907 # number of integer regfile writes
|
||||
system.cpu.fp_regfile_reads 8900 # number of floating regfile reads
|
||||
system.cpu.fp_regfile_writes 2982 # number of floating regfile writes
|
||||
system.cpu.misc_regfile_reads 135543435 # number of misc regfile reads
|
||||
system.cpu.misc_regfile_writes 912729 # number of misc regfile writes
|
||||
system.cpu.icache.replacements 1019271 # number of replacements
|
||||
system.cpu.icache.tagsinuse 511.444719 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 12598089 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 1019783 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 12.353696 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 6290137000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 511.444719 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.998915 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.998915 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 12598089 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 12598089 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 12598089 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 12598089 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 12598089 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 12598089 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 1111711 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 1111711 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 1111711 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 1111711 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 1111711 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 1111711 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 16369836984 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 16369836984 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 16369836984 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 16369836984 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 16369836984 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 16369836984 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 13709800 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 13709800 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 13709800 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 13709800 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 13709800 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 13709800 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.081089 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.081089 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.081089 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.081089 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.081089 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.081089 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14724.903310 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 14724.903310 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 14724.903310 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 14724.903310 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 14724.903310 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 14724.903310 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 2973484 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 393 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs 7566.117048 # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks::writebacks 60091 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 60091 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 91891 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::total 91891 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::cpu.inst 91891 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::total 91891 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::cpu.inst 91891 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::total 91891 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1019820 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 1019820 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 1019820 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 1019820 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 1019820 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 1019820 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12187570984 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 12187570984 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12187570984 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 12187570984 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12187570984 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 12187570984 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 7292000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 7292000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 7292000 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency::total 7292000 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.074386 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.074386 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.074386 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.074386 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.074386 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.074386 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11950.707952 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11950.707952 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11950.707952 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 11950.707952 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11950.707952 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 11950.707952 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 645895 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 511.991565 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 22075422 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 646407 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 34.150964 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 49188000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 511.991565 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.999984 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.999984 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 14216478 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 14216478 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 7283636 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 7283636 # number of WriteReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::cpu.data 286092 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::total 286092 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::cpu.data 285655 # number of StoreCondReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::total 285655 # number of StoreCondReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 21500114 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 21500114 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 21500114 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 21500114 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 747655 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 747655 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 2966865 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 2966865 # number of WriteReq misses
|
||||
system.cpu.dcache.LoadLockedReq_misses::cpu.data 13747 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.LoadLockedReq_misses::total 13747 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.StoreCondReq_misses::cpu.data 13 # number of StoreCondReq misses
|
||||
system.cpu.dcache.StoreCondReq_misses::total 13 # number of StoreCondReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 3714520 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 3714520 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 3714520 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 3714520 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 11237363500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 11237363500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 110154178240 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 110154178240 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 224042000 # number of LoadLockedReq miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_miss_latency::total 224042000 # number of LoadLockedReq miss cycles
|
||||
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 394000 # number of StoreCondReq miss cycles
|
||||
system.cpu.dcache.StoreCondReq_miss_latency::total 394000 # number of StoreCondReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 121391541740 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 121391541740 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 121391541740 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 121391541740 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 14964133 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 14964133 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 10250501 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 10250501 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 299839 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::total 299839 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::cpu.data 285668 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::total 285668 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 25214634 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 25214634 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 25214634 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 25214634 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.049963 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.049963 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289436 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.289436 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045848 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045848 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000046 # miss rate for StoreCondReq accesses
|
||||
system.cpu.dcache.StoreCondReq_miss_rate::total 0.000046 # miss rate for StoreCondReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.147316 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.147316 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.147316 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.147316 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15030.145589 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 15030.145589 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37128.139717 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 37128.139717 # average WriteReq miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16297.519459 # average LoadLockedReq miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16297.519459 # average LoadLockedReq miss latency
|
||||
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 30307.692308 # average StoreCondReq miss latency
|
||||
system.cpu.dcache.StoreCondReq_avg_miss_latency::total 30307.692308 # average StoreCondReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 32680.276789 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 32680.276789 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 32680.276789 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 32680.276789 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 17091437 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 7607500 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 3024 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 268 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 5651.930225 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets 28386.194030 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 574932 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 574932 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 359686 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 359686 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2717440 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 2717440 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1386 # number of LoadLockedReq MSHR hits
|
||||
system.cpu.dcache.LoadLockedReq_mshr_hits::total 1386 # number of LoadLockedReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 3077126 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 3077126 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 3077126 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 3077126 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 387969 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 387969 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249425 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 249425 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12361 # number of LoadLockedReq MSHR misses
|
||||
system.cpu.dcache.LoadLockedReq_mshr_misses::total 12361 # number of LoadLockedReq MSHR misses
|
||||
system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 13 # number of StoreCondReq MSHR misses
|
||||
system.cpu.dcache.StoreCondReq_mshr_misses::total 13 # number of StoreCondReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 637394 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 637394 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 637394 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 637394 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5287973500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 5287973500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8908906437 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 8908906437 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 165672500 # number of LoadLockedReq MSHR miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 165672500 # number of LoadLockedReq MSHR miss cycles
|
||||
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 351500 # number of StoreCondReq MSHR miss cycles
|
||||
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 351500 # number of StoreCondReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14196879937 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 14196879937 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14196879937 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 14196879937 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 147151877500 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 147151877500 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 42255772015 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 42255772015 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 189407649515 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency::total 189407649515 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.025927 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.025927 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024333 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024333 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.041225 # mshr miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.041225 # mshr miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000046 # mshr miss rate for StoreCondReq accesses
|
||||
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000046 # mshr miss rate for StoreCondReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025279 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.025279 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025279 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.025279 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13629.886666 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13629.886666 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35717.776634 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35717.776634 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13402.839576 # average LoadLockedReq mshr miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13402.839576 # average LoadLockedReq mshr miss latency
|
||||
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 27038.461538 # average StoreCondReq mshr miss latency
|
||||
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 27038.461538 # average StoreCondReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22273.319073 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 22273.319073 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22273.319073 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 22273.319073 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.iocache.replacements 0 # number of replacements
|
||||
system.iocache.tagsinuse 0 # Cycle average of tags in use
|
||||
system.iocache.total_refs 0 # Total number of references to valid blocks.
|
||||
system.iocache.sampled_refs 0 # Sample count of references to valid blocks.
|
||||
system.iocache.avg_refs nan # Average number of references to valid blocks.
|
||||
system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.iocache.fast_writes 0 # number of fast writes performed
|
||||
system.iocache.cache_copies 0 # number of cache copies performed
|
||||
system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1296131413558 # number of ReadReq MSHR uncacheable cycles
|
||||
system.iocache.ReadReq_mshr_uncacheable_latency::total 1296131413558 # number of ReadReq MSHR uncacheable cycles
|
||||
system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1296131413558 # number of overall MSHR uncacheable cycles
|
||||
system.iocache.overall_mshr_uncacheable_latency::total 1296131413558 # number of overall MSHR uncacheable cycles
|
||||
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
|
||||
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
||||
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
|
||||
system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
||||
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
||||
system.cpu.kern.inst.quiesce 88053 # number of quiesce instructions executed
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,18 @@
|
||||
warn: Sockets disabled, not accepting vnc client connections
|
||||
warn: Sockets disabled, not accepting terminal connections
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: The clidr register always reports 0 caches.
|
||||
warn: clidr LoUIS field of 0b001 to match current ARM implementations.
|
||||
warn: The csselr register isn't implemented.
|
||||
warn: The ccsidr register isn't implemented and always reads as 0.
|
||||
warn: instruction 'mcr bpiallis' unimplemented
|
||||
warn: instruction 'mcr icialluis' unimplemented
|
||||
warn: instruction 'mcr dccimvac' unimplemented
|
||||
warn: instruction 'mcr dccmvau' unimplemented
|
||||
warn: instruction 'mcr icimvau' unimplemented
|
||||
warn: instruction 'mcr bpiallis' unimplemented
|
||||
warn: LCD dual screen mode not supported
|
||||
warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
|
||||
warn: instruction 'mcr icialluis' unimplemented
|
||||
warn: instruction 'mcr icialluis' unimplemented
|
||||
hack: be nice to actually delete the event here
|
||||
@ -0,0 +1,12 @@
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jun 4 2012 12:14:06
|
||||
gem5 started Jun 4 2012 18:58:50
|
||||
gem5 executing on zizzer
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
|
||||
info: Using bootloader at address 0x80000000
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 2570833934500 because m5_exit instruction encountered
|
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1 @@
|
||||
build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual FAILED!
|
||||
Binary file not shown.
File diff suppressed because it is too large
Load Diff
17
simulators/gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr
Executable file
17
simulators/gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr
Executable file
@ -0,0 +1,17 @@
|
||||
warn: Sockets disabled, not accepting vnc client connections
|
||||
warn: Sockets disabled, not accepting terminal connections
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: The clidr register always reports 0 caches.
|
||||
warn: clidr LoUIS field of 0b001 to match current ARM implementations.
|
||||
warn: The csselr register isn't implemented.
|
||||
warn: The ccsidr register isn't implemented and always reads as 0.
|
||||
warn: instruction 'mcr bpiallis' unimplemented
|
||||
warn: instruction 'mcr icialluis' unimplemented
|
||||
warn: instruction 'mcr dccimvac' unimplemented
|
||||
warn: instruction 'mcr dccmvau' unimplemented
|
||||
warn: instruction 'mcr icimvau' unimplemented
|
||||
warn: LCD dual screen mode not supported
|
||||
warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
|
||||
warn: instruction 'mcr icialluis' unimplemented
|
||||
warn: instruction 'mcr bpiallis' unimplemented
|
||||
hack: be nice to actually delete the event here
|
||||
12
simulators/gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout
Executable file
12
simulators/gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout
Executable file
@ -0,0 +1,12 @@
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jun 4 2012 12:14:06
|
||||
gem5 started Jun 4 2012 18:55:16
|
||||
gem5 executing on zizzer
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
|
||||
info: Using bootloader at address 0x80000000
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 2501685689500 because m5_exit instruction encountered
|
||||
@ -0,0 +1,940 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 2.501686 # Number of seconds simulated
|
||||
sim_ticks 2501685689500 # Number of ticks simulated
|
||||
final_tick 2501685689500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 57858 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 74704 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2429415836 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 387132 # Number of bytes of host memory used
|
||||
host_seconds 1029.75 # Real time elapsed on the host
|
||||
sim_insts 59579009 # Number of instructions simulated
|
||||
sim_ops 76926775 # Number of ops (including micro ops) simulated
|
||||
system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory
|
||||
system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory
|
||||
system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory
|
||||
system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory
|
||||
system.realview.nvmem.num_reads::cpu.inst 1 # Number of read requests responded to by this memory
|
||||
system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory
|
||||
system.realview.nvmem.bw_read::cpu.inst 26 # Total read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_read::total 26 # Total read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_inst_read::cpu.inst 26 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_inst_read::total 26 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_total::cpu.inst 26 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_total::total 26 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bytes_read::realview.clcd 118440096 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.dtb.walker 12032 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.itb.walker 896 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.inst 1119872 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 10085712 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 129658608 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 1119872 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 1119872 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 6569664 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 9585736 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::realview.clcd 14805012 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.dtb.walker 188 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.itb.walker 14 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.inst 17498 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 157623 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 14980335 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 102651 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 856669 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::realview.clcd 47344115 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.dtb.walker 4810 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.itb.walker 358 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 447647 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 4031566 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 51828496 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 447647 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 447647 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 2626095 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::cpu.data 1205616 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 3831711 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 2626095 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::realview.clcd 47344115 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.dtb.walker 4810 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.itb.walker 358 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 447647 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 5237182 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 55660207 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.l2c.replacements 119797 # number of replacements
|
||||
system.l2c.tagsinuse 26022.811009 # Cycle average of tags in use
|
||||
system.l2c.total_refs 1834134 # Total number of references to valid blocks.
|
||||
system.l2c.sampled_refs 150735 # Sample count of references to valid blocks.
|
||||
system.l2c.avg_refs 12.167937 # Average number of references to valid blocks.
|
||||
system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.l2c.occ_blocks::writebacks 14260.921168 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu.dtb.walker 79.122472 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu.itb.walker 1.014068 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu.inst 6176.146101 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu.data 5505.607200 # Average occupied blocks per requestor
|
||||
system.l2c.occ_percent::writebacks 0.217604 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu.dtb.walker 0.001207 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu.itb.walker 0.000015 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu.inst 0.094241 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu.data 0.084009 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::total 0.397077 # Average percentage of cache occupancy
|
||||
system.l2c.ReadReq_hits::cpu.dtb.walker 144170 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu.itb.walker 12492 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu.inst 1001175 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu.data 378296 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::total 1536133 # number of ReadReq hits
|
||||
system.l2c.Writeback_hits::writebacks 635023 # number of Writeback hits
|
||||
system.l2c.Writeback_hits::total 635023 # number of Writeback hits
|
||||
system.l2c.UpgradeReq_hits::cpu.data 45 # number of UpgradeReq hits
|
||||
system.l2c.UpgradeReq_hits::total 45 # number of UpgradeReq hits
|
||||
system.l2c.SCUpgradeReq_hits::cpu.data 8 # number of SCUpgradeReq hits
|
||||
system.l2c.SCUpgradeReq_hits::total 8 # number of SCUpgradeReq hits
|
||||
system.l2c.ReadExReq_hits::cpu.data 105875 # number of ReadExReq hits
|
||||
system.l2c.ReadExReq_hits::total 105875 # number of ReadExReq hits
|
||||
system.l2c.demand_hits::cpu.dtb.walker 144170 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu.itb.walker 12492 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu.inst 1001175 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu.data 484171 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::total 1642008 # number of demand (read+write) hits
|
||||
system.l2c.overall_hits::cpu.dtb.walker 144170 # number of overall hits
|
||||
system.l2c.overall_hits::cpu.itb.walker 12492 # number of overall hits
|
||||
system.l2c.overall_hits::cpu.inst 1001175 # number of overall hits
|
||||
system.l2c.overall_hits::cpu.data 484171 # number of overall hits
|
||||
system.l2c.overall_hits::total 1642008 # number of overall hits
|
||||
system.l2c.ReadReq_misses::cpu.dtb.walker 189 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu.itb.walker 14 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu.inst 17378 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu.data 19180 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::total 36761 # number of ReadReq misses
|
||||
system.l2c.UpgradeReq_misses::cpu.data 3300 # number of UpgradeReq misses
|
||||
system.l2c.UpgradeReq_misses::total 3300 # number of UpgradeReq misses
|
||||
system.l2c.SCUpgradeReq_misses::cpu.data 5 # number of SCUpgradeReq misses
|
||||
system.l2c.SCUpgradeReq_misses::total 5 # number of SCUpgradeReq misses
|
||||
system.l2c.ReadExReq_misses::cpu.data 140292 # number of ReadExReq misses
|
||||
system.l2c.ReadExReq_misses::total 140292 # number of ReadExReq misses
|
||||
system.l2c.demand_misses::cpu.dtb.walker 189 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu.itb.walker 14 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu.inst 17378 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu.data 159472 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::total 177053 # number of demand (read+write) misses
|
||||
system.l2c.overall_misses::cpu.dtb.walker 189 # number of overall misses
|
||||
system.l2c.overall_misses::cpu.itb.walker 14 # number of overall misses
|
||||
system.l2c.overall_misses::cpu.inst 17378 # number of overall misses
|
||||
system.l2c.overall_misses::cpu.data 159472 # number of overall misses
|
||||
system.l2c.overall_misses::total 177053 # number of overall misses
|
||||
system.l2c.ReadReq_miss_latency::cpu.dtb.walker 9850500 # number of ReadReq miss cycles
|
||||
system.l2c.ReadReq_miss_latency::cpu.itb.walker 752000 # number of ReadReq miss cycles
|
||||
system.l2c.ReadReq_miss_latency::cpu.inst 910079500 # number of ReadReq miss cycles
|
||||
system.l2c.ReadReq_miss_latency::cpu.data 1002096000 # number of ReadReq miss cycles
|
||||
system.l2c.ReadReq_miss_latency::total 1922778000 # number of ReadReq miss cycles
|
||||
system.l2c.UpgradeReq_miss_latency::cpu.data 996000 # number of UpgradeReq miss cycles
|
||||
system.l2c.UpgradeReq_miss_latency::total 996000 # number of UpgradeReq miss cycles
|
||||
system.l2c.SCUpgradeReq_miss_latency::cpu.data 104000 # number of SCUpgradeReq miss cycles
|
||||
system.l2c.SCUpgradeReq_miss_latency::total 104000 # number of SCUpgradeReq miss cycles
|
||||
system.l2c.ReadExReq_miss_latency::cpu.data 7365557000 # number of ReadExReq miss cycles
|
||||
system.l2c.ReadExReq_miss_latency::total 7365557000 # number of ReadExReq miss cycles
|
||||
system.l2c.demand_miss_latency::cpu.dtb.walker 9850500 # number of demand (read+write) miss cycles
|
||||
system.l2c.demand_miss_latency::cpu.itb.walker 752000 # number of demand (read+write) miss cycles
|
||||
system.l2c.demand_miss_latency::cpu.inst 910079500 # number of demand (read+write) miss cycles
|
||||
system.l2c.demand_miss_latency::cpu.data 8367653000 # number of demand (read+write) miss cycles
|
||||
system.l2c.demand_miss_latency::total 9288335000 # number of demand (read+write) miss cycles
|
||||
system.l2c.overall_miss_latency::cpu.dtb.walker 9850500 # number of overall miss cycles
|
||||
system.l2c.overall_miss_latency::cpu.itb.walker 752000 # number of overall miss cycles
|
||||
system.l2c.overall_miss_latency::cpu.inst 910079500 # number of overall miss cycles
|
||||
system.l2c.overall_miss_latency::cpu.data 8367653000 # number of overall miss cycles
|
||||
system.l2c.overall_miss_latency::total 9288335000 # number of overall miss cycles
|
||||
system.l2c.ReadReq_accesses::cpu.dtb.walker 144359 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::cpu.itb.walker 12506 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::cpu.inst 1018553 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::cpu.data 397476 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::total 1572894 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.Writeback_accesses::writebacks 635023 # number of Writeback accesses(hits+misses)
|
||||
system.l2c.Writeback_accesses::total 635023 # number of Writeback accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_accesses::cpu.data 3345 # number of UpgradeReq accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_accesses::total 3345 # number of UpgradeReq accesses(hits+misses)
|
||||
system.l2c.SCUpgradeReq_accesses::cpu.data 13 # number of SCUpgradeReq accesses(hits+misses)
|
||||
system.l2c.SCUpgradeReq_accesses::total 13 # number of SCUpgradeReq accesses(hits+misses)
|
||||
system.l2c.ReadExReq_accesses::cpu.data 246167 # number of ReadExReq accesses(hits+misses)
|
||||
system.l2c.ReadExReq_accesses::total 246167 # number of ReadExReq accesses(hits+misses)
|
||||
system.l2c.demand_accesses::cpu.dtb.walker 144359 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu.itb.walker 12506 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu.inst 1018553 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu.data 643643 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::total 1819061 # number of demand (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu.dtb.walker 144359 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu.itb.walker 12506 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu.inst 1018553 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu.data 643643 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::total 1819061 # number of overall (read+write) accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.001309 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.001119 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu.inst 0.017061 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu.data 0.048254 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::total 0.023372 # miss rate for ReadReq accesses
|
||||
system.l2c.UpgradeReq_miss_rate::cpu.data 0.986547 # miss rate for UpgradeReq accesses
|
||||
system.l2c.UpgradeReq_miss_rate::total 0.986547 # miss rate for UpgradeReq accesses
|
||||
system.l2c.SCUpgradeReq_miss_rate::cpu.data 0.384615 # miss rate for SCUpgradeReq accesses
|
||||
system.l2c.SCUpgradeReq_miss_rate::total 0.384615 # miss rate for SCUpgradeReq accesses
|
||||
system.l2c.ReadExReq_miss_rate::cpu.data 0.569906 # miss rate for ReadExReq accesses
|
||||
system.l2c.ReadExReq_miss_rate::total 0.569906 # miss rate for ReadExReq accesses
|
||||
system.l2c.demand_miss_rate::cpu.dtb.walker 0.001309 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu.itb.walker 0.001119 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu.inst 0.017061 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu.data 0.247765 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::total 0.097332 # miss rate for demand accesses
|
||||
system.l2c.overall_miss_rate::cpu.dtb.walker 0.001309 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu.itb.walker 0.001119 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu.inst 0.017061 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu.data 0.247765 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::total 0.097332 # miss rate for overall accesses
|
||||
system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52119.047619 # average ReadReq miss latency
|
||||
system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 53714.285714 # average ReadReq miss latency
|
||||
system.l2c.ReadReq_avg_miss_latency::cpu.inst 52369.634020 # average ReadReq miss latency
|
||||
system.l2c.ReadReq_avg_miss_latency::cpu.data 52246.923879 # average ReadReq miss latency
|
||||
system.l2c.ReadReq_avg_miss_latency::total 52304.833927 # average ReadReq miss latency
|
||||
system.l2c.UpgradeReq_avg_miss_latency::cpu.data 301.818182 # average UpgradeReq miss latency
|
||||
system.l2c.UpgradeReq_avg_miss_latency::total 301.818182 # average UpgradeReq miss latency
|
||||
system.l2c.SCUpgradeReq_avg_miss_latency::cpu.data 20800 # average SCUpgradeReq miss latency
|
||||
system.l2c.SCUpgradeReq_avg_miss_latency::total 20800 # average SCUpgradeReq miss latency
|
||||
system.l2c.ReadExReq_avg_miss_latency::cpu.data 52501.618054 # average ReadExReq miss latency
|
||||
system.l2c.ReadExReq_avg_miss_latency::total 52501.618054 # average ReadExReq miss latency
|
||||
system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52119.047619 # average overall miss latency
|
||||
system.l2c.demand_avg_miss_latency::cpu.itb.walker 53714.285714 # average overall miss latency
|
||||
system.l2c.demand_avg_miss_latency::cpu.inst 52369.634020 # average overall miss latency
|
||||
system.l2c.demand_avg_miss_latency::cpu.data 52470.985502 # average overall miss latency
|
||||
system.l2c.demand_avg_miss_latency::total 52460.760337 # average overall miss latency
|
||||
system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52119.047619 # average overall miss latency
|
||||
system.l2c.overall_avg_miss_latency::cpu.itb.walker 53714.285714 # average overall miss latency
|
||||
system.l2c.overall_avg_miss_latency::cpu.inst 52369.634020 # average overall miss latency
|
||||
system.l2c.overall_avg_miss_latency::cpu.data 52470.985502 # average overall miss latency
|
||||
system.l2c.overall_avg_miss_latency::total 52460.760337 # average overall miss latency
|
||||
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.l2c.fast_writes 0 # number of fast writes performed
|
||||
system.l2c.cache_copies 0 # number of cache copies performed
|
||||
system.l2c.writebacks::writebacks 102651 # number of writebacks
|
||||
system.l2c.writebacks::total 102651 # number of writebacks
|
||||
system.l2c.ReadReq_mshr_hits::cpu.dtb.walker 1 # number of ReadReq MSHR hits
|
||||
system.l2c.ReadReq_mshr_hits::cpu.inst 14 # number of ReadReq MSHR hits
|
||||
system.l2c.ReadReq_mshr_hits::cpu.data 86 # number of ReadReq MSHR hits
|
||||
system.l2c.ReadReq_mshr_hits::total 101 # number of ReadReq MSHR hits
|
||||
system.l2c.demand_mshr_hits::cpu.dtb.walker 1 # number of demand (read+write) MSHR hits
|
||||
system.l2c.demand_mshr_hits::cpu.inst 14 # number of demand (read+write) MSHR hits
|
||||
system.l2c.demand_mshr_hits::cpu.data 86 # number of demand (read+write) MSHR hits
|
||||
system.l2c.demand_mshr_hits::total 101 # number of demand (read+write) MSHR hits
|
||||
system.l2c.overall_mshr_hits::cpu.dtb.walker 1 # number of overall MSHR hits
|
||||
system.l2c.overall_mshr_hits::cpu.inst 14 # number of overall MSHR hits
|
||||
system.l2c.overall_mshr_hits::cpu.data 86 # number of overall MSHR hits
|
||||
system.l2c.overall_mshr_hits::total 101 # number of overall MSHR hits
|
||||
system.l2c.ReadReq_mshr_misses::cpu.dtb.walker 188 # number of ReadReq MSHR misses
|
||||
system.l2c.ReadReq_mshr_misses::cpu.itb.walker 14 # number of ReadReq MSHR misses
|
||||
system.l2c.ReadReq_mshr_misses::cpu.inst 17364 # number of ReadReq MSHR misses
|
||||
system.l2c.ReadReq_mshr_misses::cpu.data 19094 # number of ReadReq MSHR misses
|
||||
system.l2c.ReadReq_mshr_misses::total 36660 # number of ReadReq MSHR misses
|
||||
system.l2c.UpgradeReq_mshr_misses::cpu.data 3300 # number of UpgradeReq MSHR misses
|
||||
system.l2c.UpgradeReq_mshr_misses::total 3300 # number of UpgradeReq MSHR misses
|
||||
system.l2c.SCUpgradeReq_mshr_misses::cpu.data 5 # number of SCUpgradeReq MSHR misses
|
||||
system.l2c.SCUpgradeReq_mshr_misses::total 5 # number of SCUpgradeReq MSHR misses
|
||||
system.l2c.ReadExReq_mshr_misses::cpu.data 140292 # number of ReadExReq MSHR misses
|
||||
system.l2c.ReadExReq_mshr_misses::total 140292 # number of ReadExReq MSHR misses
|
||||
system.l2c.demand_mshr_misses::cpu.dtb.walker 188 # number of demand (read+write) MSHR misses
|
||||
system.l2c.demand_mshr_misses::cpu.itb.walker 14 # number of demand (read+write) MSHR misses
|
||||
system.l2c.demand_mshr_misses::cpu.inst 17364 # number of demand (read+write) MSHR misses
|
||||
system.l2c.demand_mshr_misses::cpu.data 159386 # number of demand (read+write) MSHR misses
|
||||
system.l2c.demand_mshr_misses::total 176952 # number of demand (read+write) MSHR misses
|
||||
system.l2c.overall_mshr_misses::cpu.dtb.walker 188 # number of overall MSHR misses
|
||||
system.l2c.overall_mshr_misses::cpu.itb.walker 14 # number of overall MSHR misses
|
||||
system.l2c.overall_mshr_misses::cpu.inst 17364 # number of overall MSHR misses
|
||||
system.l2c.overall_mshr_misses::cpu.data 159386 # number of overall MSHR misses
|
||||
system.l2c.overall_mshr_misses::total 176952 # number of overall MSHR misses
|
||||
system.l2c.ReadReq_mshr_miss_latency::cpu.dtb.walker 7532000 # number of ReadReq MSHR miss cycles
|
||||
system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker 584000 # number of ReadReq MSHR miss cycles
|
||||
system.l2c.ReadReq_mshr_miss_latency::cpu.inst 697406000 # number of ReadReq MSHR miss cycles
|
||||
system.l2c.ReadReq_mshr_miss_latency::cpu.data 765603000 # number of ReadReq MSHR miss cycles
|
||||
system.l2c.ReadReq_mshr_miss_latency::total 1471125000 # number of ReadReq MSHR miss cycles
|
||||
system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 132880000 # number of UpgradeReq MSHR miss cycles
|
||||
system.l2c.UpgradeReq_mshr_miss_latency::total 132880000 # number of UpgradeReq MSHR miss cycles
|
||||
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu.data 200000 # number of SCUpgradeReq MSHR miss cycles
|
||||
system.l2c.SCUpgradeReq_mshr_miss_latency::total 200000 # number of SCUpgradeReq MSHR miss cycles
|
||||
system.l2c.ReadExReq_mshr_miss_latency::cpu.data 5622122500 # number of ReadExReq MSHR miss cycles
|
||||
system.l2c.ReadExReq_mshr_miss_latency::total 5622122500 # number of ReadExReq MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_latency::cpu.dtb.walker 7532000 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_latency::cpu.itb.walker 584000 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_latency::cpu.inst 697406000 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_latency::cpu.data 6387725500 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_latency::total 7093247500 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency::cpu.dtb.walker 7532000 # number of overall MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency::cpu.itb.walker 584000 # number of overall MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency::cpu.inst 697406000 # number of overall MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency::cpu.data 6387725500 # number of overall MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency::total 7093247500 # number of overall MSHR miss cycles
|
||||
system.l2c.ReadReq_mshr_uncacheable_latency::cpu.inst 5427000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 131758586500 # number of ReadReq MSHR uncacheable cycles
|
||||
system.l2c.ReadReq_mshr_uncacheable_latency::total 131764013500 # number of ReadReq MSHR uncacheable cycles
|
||||
system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 32346095899 # number of WriteReq MSHR uncacheable cycles
|
||||
system.l2c.WriteReq_mshr_uncacheable_latency::total 32346095899 # number of WriteReq MSHR uncacheable cycles
|
||||
system.l2c.overall_mshr_uncacheable_latency::cpu.inst 5427000 # number of overall MSHR uncacheable cycles
|
||||
system.l2c.overall_mshr_uncacheable_latency::cpu.data 164104682399 # number of overall MSHR uncacheable cycles
|
||||
system.l2c.overall_mshr_uncacheable_latency::total 164110109399 # number of overall MSHR uncacheable cycles
|
||||
system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001302 # mshr miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001119 # mshr miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.017048 # mshr miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.048038 # mshr miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_mshr_miss_rate::total 0.023307 # mshr miss rate for ReadReq accesses
|
||||
system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.986547 # mshr miss rate for UpgradeReq accesses
|
||||
system.l2c.UpgradeReq_mshr_miss_rate::total 0.986547 # mshr miss rate for UpgradeReq accesses
|
||||
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu.data 0.384615 # mshr miss rate for SCUpgradeReq accesses
|
||||
system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.384615 # mshr miss rate for SCUpgradeReq accesses
|
||||
system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.569906 # mshr miss rate for ReadExReq accesses
|
||||
system.l2c.ReadExReq_mshr_miss_rate::total 0.569906 # mshr miss rate for ReadExReq accesses
|
||||
system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.001302 # mshr miss rate for demand accesses
|
||||
system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.001119 # mshr miss rate for demand accesses
|
||||
system.l2c.demand_mshr_miss_rate::cpu.inst 0.017048 # mshr miss rate for demand accesses
|
||||
system.l2c.demand_mshr_miss_rate::cpu.data 0.247631 # mshr miss rate for demand accesses
|
||||
system.l2c.demand_mshr_miss_rate::total 0.097277 # mshr miss rate for demand accesses
|
||||
system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.001302 # mshr miss rate for overall accesses
|
||||
system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.001119 # mshr miss rate for overall accesses
|
||||
system.l2c.overall_mshr_miss_rate::cpu.inst 0.017048 # mshr miss rate for overall accesses
|
||||
system.l2c.overall_mshr_miss_rate::cpu.data 0.247631 # mshr miss rate for overall accesses
|
||||
system.l2c.overall_mshr_miss_rate::total 0.097277 # mshr miss rate for overall accesses
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40063.829787 # average ReadReq mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 41714.285714 # average ReadReq mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40163.902327 # average ReadReq mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40096.522468 # average ReadReq mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::total 40128.887070 # average ReadReq mshr miss latency
|
||||
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40266.666667 # average UpgradeReq mshr miss latency
|
||||
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40266.666667 # average UpgradeReq mshr miss latency
|
||||
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 40000 # average SCUpgradeReq mshr miss latency
|
||||
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40000 # average SCUpgradeReq mshr miss latency
|
||||
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40074.434038 # average ReadExReq mshr miss latency
|
||||
system.l2c.ReadExReq_avg_mshr_miss_latency::total 40074.434038 # average ReadExReq mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40063.829787 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 41714.285714 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40163.902327 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu.data 40077.080170 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::total 40085.715335 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40063.829787 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 41714.285714 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40163.902327 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu.data 40077.080170 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::total 40085.715335 # average overall mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
|
||||
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
|
||||
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
||||
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
|
||||
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
||||
system.l2c.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
|
||||
system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
|
||||
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
||||
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
||||
system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
|
||||
system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
|
||||
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
|
||||
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
|
||||
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
|
||||
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.dtb.read_hits 52103903 # DTB read hits
|
||||
system.cpu.dtb.read_misses 93079 # DTB read misses
|
||||
system.cpu.dtb.write_hits 11946241 # DTB write hits
|
||||
system.cpu.dtb.write_misses 25022 # DTB write misses
|
||||
system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed
|
||||
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
|
||||
system.cpu.dtb.flush_entries 4532 # Number of entries that have been flushed from TLB
|
||||
system.cpu.dtb.align_faults 5562 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.dtb.prefetch_faults 707 # Number of TLB faults due to prefetch
|
||||
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.dtb.perms_faults 2799 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.dtb.read_accesses 52196982 # DTB read accesses
|
||||
system.cpu.dtb.write_accesses 11971263 # DTB write accesses
|
||||
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
|
||||
system.cpu.dtb.hits 64050144 # DTB hits
|
||||
system.cpu.dtb.misses 118101 # DTB misses
|
||||
system.cpu.dtb.accesses 64168245 # DTB accesses
|
||||
system.cpu.itb.inst_hits 13717584 # ITB inst hits
|
||||
system.cpu.itb.inst_misses 12272 # ITB inst misses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.write_hits 0 # DTB write hits
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed
|
||||
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
|
||||
system.cpu.itb.flush_entries 2655 # Number of entries that have been flushed from TLB
|
||||
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.itb.perms_faults 6863 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.itb.inst_accesses 13729856 # ITB inst accesses
|
||||
system.cpu.itb.hits 13717584 # DTB hits
|
||||
system.cpu.itb.misses 12272 # DTB misses
|
||||
system.cpu.itb.accesses 13729856 # DTB accesses
|
||||
system.cpu.numCycles 411352060 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.BPredUnit.lookups 15654738 # Number of BP lookups
|
||||
system.cpu.BPredUnit.condPredicted 12362397 # Number of conditional branches predicted
|
||||
system.cpu.BPredUnit.condIncorrect 932839 # Number of conditional branches incorrect
|
||||
system.cpu.BPredUnit.BTBLookups 10530768 # Number of BTB lookups
|
||||
system.cpu.BPredUnit.BTBHits 8288874 # Number of BTB hits
|
||||
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu.BPredUnit.usedRAS 1329017 # Number of times the RAS was used to get a target.
|
||||
system.cpu.BPredUnit.RASInCorrect 195537 # Number of incorrect RAS predictions.
|
||||
system.cpu.fetch.icacheStallCycles 33116930 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.Insts 103031700 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.Branches 15654738 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.predictedBranches 9617891 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.Cycles 22620194 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.SquashCycles 6706106 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.TlbCycles 163882 # Number of cycles fetch has spent waiting for tlb
|
||||
system.cpu.fetch.BlockedCycles 89861042 # Number of cycles fetch has spent blocked
|
||||
system.cpu.fetch.MiscStallCycles 2823 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
||||
system.cpu.fetch.PendingTrapStallCycles 147160 # Number of stall cycles due to pending traps
|
||||
system.cpu.fetch.PendingQuiesceStallCycles 218224 # Number of stall cycles due to pending quiesce instructions
|
||||
system.cpu.fetch.IcacheWaitRetryStallCycles 462 # Number of stall cycles due to full MSHR
|
||||
system.cpu.fetch.CacheLines 13709942 # Number of cache lines fetched
|
||||
system.cpu.fetch.IcacheSquashes 998560 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.ItlbSquashes 6868 # Number of outstanding ITLB misses that were squashed
|
||||
system.cpu.fetch.rateDist::samples 150746244 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 0.848897 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 2.234280 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 128142810 85.01% 85.01% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 1478319 0.98% 85.99% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 1855018 1.23% 87.22% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 2695901 1.79% 89.01% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 1893540 1.26% 90.26% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 1191101 0.79% 91.05% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 2951659 1.96% 93.01% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 850848 0.56% 93.57% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 9687048 6.43% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::total 150746244 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.branchRate 0.038057 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.rate 0.250471 # Number of inst fetches per cycle
|
||||
system.cpu.decode.IdleCycles 35228906 # Number of cycles decode is idle
|
||||
system.cpu.decode.BlockedCycles 89710063 # Number of cycles decode is blocked
|
||||
system.cpu.decode.RunCycles 20347806 # Number of cycles decode is running
|
||||
system.cpu.decode.UnblockCycles 1026685 # Number of cycles decode is unblocking
|
||||
system.cpu.decode.SquashCycles 4432784 # Number of cycles decode is squashing
|
||||
system.cpu.decode.BranchResolved 2275641 # Number of times decode resolved a branch
|
||||
system.cpu.decode.BranchMispred 186729 # Number of times decode detected a branch misprediction
|
||||
system.cpu.decode.DecodedInsts 120042439 # Number of instructions handled by decode
|
||||
system.cpu.decode.SquashedInsts 604390 # Number of squashed instructions handled by decode
|
||||
system.cpu.rename.SquashCycles 4432784 # Number of cycles rename is squashing
|
||||
system.cpu.rename.IdleCycles 37305734 # Number of cycles rename is idle
|
||||
system.cpu.rename.BlockCycles 37165628 # Number of cycles rename is blocking
|
||||
system.cpu.rename.serializeStallCycles 46502465 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RunCycles 19251695 # Number of cycles rename is running
|
||||
system.cpu.rename.UnblockCycles 6087938 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RenamedInsts 112539597 # Number of instructions processed by rename
|
||||
system.cpu.rename.ROBFullEvents 3873 # Number of times rename has blocked due to ROB full
|
||||
system.cpu.rename.IQFullEvents 1013212 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.LSQFullEvents 4109157 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.FullRegisterEvents 45575 # Number of times there has been no free registers
|
||||
system.cpu.rename.RenamedOperands 117156815 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RenameLookups 517555842 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.int_rename_lookups 517460811 # Number of integer rename lookups
|
||||
system.cpu.rename.fp_rename_lookups 95031 # Number of floating rename lookups
|
||||
system.cpu.rename.CommittedMaps 77687687 # Number of HB maps that are committed
|
||||
system.cpu.rename.UndoneMaps 39469127 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.serializingInsts 939790 # count of serializing insts renamed
|
||||
system.cpu.rename.tempSerializingInsts 835958 # count of temporary serializing insts renamed
|
||||
system.cpu.rename.skidInsts 12443241 # count of insts added to the skid buffer
|
||||
system.cpu.memDep0.insertedLoads 21685850 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 14072237 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.conflictingLoads 1938675 # Number of conflicting loads.
|
||||
system.cpu.memDep0.conflictingStores 2482763 # Number of conflicting stores.
|
||||
system.cpu.iq.iqInstsAdded 102391550 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqNonSpecInstsAdded 1619583 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqInstsIssued 126350622 # Number of instructions issued
|
||||
system.cpu.iq.iqSquashedInstsIssued 234593 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedInstsExamined 26254924 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedOperandsExamined 71509700 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 332277 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.issued_per_cycle::samples 150746244 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::mean 0.838168 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::stdev 1.542455 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::0 105470655 69.97% 69.97% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::1 14086510 9.34% 79.31% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::2 7371222 4.89% 84.20% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::3 5923402 3.93% 88.13% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::4 12762751 8.47% 96.60% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::5 2810704 1.86% 98.46% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::6 1735902 1.15% 99.61% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::7 449258 0.30% 99.91% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::8 135840 0.09% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::total 150746244 # Number of insts issued each cycle
|
||||
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntAlu 61043 0.69% 0.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntMult 4 0.00% 0.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntDiv 0 0.00% 0.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatMult 0 0.00% 0.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdMult 0 0.00% 0.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdShift 0 0.00% 0.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::MemRead 8421186 94.66% 95.34% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::MemWrite 414230 4.66% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.FU_type_0::No_OpClass 106530 0.08% 0.08% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntAlu 59762768 47.30% 47.38% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntMult 95812 0.08% 47.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdMisc 38 0.00% 47.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdShift 45 0.00% 47.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdShiftAcc 9 0.00% 47.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMisc 2279 0.00% 47.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMultAcc 9 0.00% 47.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::MemRead 53776494 42.56% 90.02% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::MemWrite 12606638 9.98% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::total 126350622 # Type of FU issued
|
||||
system.cpu.iq.rate 0.307159 # Inst issue rate
|
||||
system.cpu.iq.fu_busy_cnt 8896463 # FU busy when requested
|
||||
system.cpu.iq.fu_busy_rate 0.070411 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.int_inst_queue_reads 412671946 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_writes 130285978 # Number of integer instruction queue writes
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 87040433 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.fp_inst_queue_reads 24078 # Number of floating instruction queue reads
|
||||
system.cpu.iq.fp_inst_queue_writes 13182 # Number of floating instruction queue writes
|
||||
system.cpu.iq.fp_inst_queue_wakeup_accesses 10434 # Number of floating instruction queue wakeup accesses
|
||||
system.cpu.iq.int_alu_accesses 135127716 # Number of integer alu accesses
|
||||
system.cpu.iq.fp_alu_accesses 12839 # Number of floating point alu accesses
|
||||
system.cpu.iew.lsq.thread0.forwLoads 636069 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread0.squashedLoads 5970496 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread0.ignoredResponses 11101 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread0.memOrderViolation 34253 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread0.squashedStores 2273952 # Number of stores squashed
|
||||
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
||||
system.cpu.iew.lsq.thread0.rescheduledLoads 34114355 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread0.cacheBlocked 1152098 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||||
system.cpu.iew.iewSquashCycles 4432784 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewBlockCycles 28604721 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewUnblockCycles 436722 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.iewDispatchedInsts 104273041 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewDispSquashedInsts 335924 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispLoadInsts 21685850 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispStoreInsts 14072237 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 992808 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewIQFullEvents 95700 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.iewLSQFullEvents 11591 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.memOrderViolationEvents 34253 # Number of memory order violations
|
||||
system.cpu.iew.predictedTakenIncorrect 552378 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.iew.predictedNotTakenIncorrect 346914 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.branchMispredicts 899292 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewExecutedInsts 123108789 # Number of executed instructions
|
||||
system.cpu.iew.iewExecLoadInsts 52799372 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 3241833 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
||||
system.cpu.iew.exec_nop 261908 # number of nop insts executed
|
||||
system.cpu.iew.exec_refs 65255060 # number of memory reference insts executed
|
||||
system.cpu.iew.exec_branches 11601340 # Number of branches executed
|
||||
system.cpu.iew.exec_stores 12455688 # Number of stores executed
|
||||
system.cpu.iew.exec_rate 0.299278 # Inst execution rate
|
||||
system.cpu.iew.wb_sent 121555618 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.wb_count 87050867 # cumulative count of insts written-back
|
||||
system.cpu.iew.wb_producers 47546734 # num instructions producing a value
|
||||
system.cpu.iew.wb_consumers 88572059 # num instructions consuming a value
|
||||
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
||||
system.cpu.iew.wb_rate 0.211621 # insts written-back per cycle
|
||||
system.cpu.iew.wb_fanout 0.536814 # average fanout of values written-back
|
||||
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||
system.cpu.commit.commitCommittedInsts 59729390 # The number of committed instructions
|
||||
system.cpu.commit.commitCommittedOps 77077156 # The number of committed instructions
|
||||
system.cpu.commit.commitSquashedInsts 27015439 # The number of squashed insts skipped by commit
|
||||
system.cpu.commit.commitNonSpecStalls 1287306 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu.commit.branchMispredicts 793496 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.committed_per_cycle::samples 146395876 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::mean 0.526498 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::stdev 1.504904 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::0 118626341 81.03% 81.03% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::1 13714527 9.37% 90.40% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::2 3991808 2.73% 93.13% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::3 2249419 1.54% 94.66% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::4 1746576 1.19% 95.86% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::5 1042045 0.71% 96.57% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::6 1550885 1.06% 97.63% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::7 665283 0.45% 98.08% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::8 2808992 1.92% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::total 146395876 # Number of insts commited each cycle
|
||||
system.cpu.commit.committedInsts 59729390 # Number of instructions committed
|
||||
system.cpu.commit.committedOps 77077156 # Number of ops (including micro ops) committed
|
||||
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
||||
system.cpu.commit.refs 27513639 # Number of memory references committed
|
||||
system.cpu.commit.loads 15715354 # Number of loads committed
|
||||
system.cpu.commit.membars 413068 # Number of memory barriers committed
|
||||
system.cpu.commit.branches 9904424 # Number of branches committed
|
||||
system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions.
|
||||
system.cpu.commit.int_insts 68617835 # Number of committed integer instructions.
|
||||
system.cpu.commit.function_calls 995976 # Number of function calls committed.
|
||||
system.cpu.commit.bw_lim_events 2808992 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
||||
system.cpu.rob.rob_reads 245922084 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 212744706 # The number of ROB writes
|
||||
system.cpu.timesIdled 1895448 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 260605816 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.quiesceCycles 4591931267 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
|
||||
system.cpu.committedInsts 59579009 # Number of Instructions Simulated
|
||||
system.cpu.committedOps 76926775 # Number of Ops (including micro ops) Simulated
|
||||
system.cpu.committedInsts_total 59579009 # Number of Instructions Simulated
|
||||
system.cpu.cpi 6.904312 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 6.904312 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 0.144837 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.144837 # IPC: Total IPC of All Threads
|
||||
system.cpu.int_regfile_reads 558200782 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 89400906 # number of integer regfile writes
|
||||
system.cpu.fp_regfile_reads 8900 # number of floating regfile reads
|
||||
system.cpu.fp_regfile_writes 2982 # number of floating regfile writes
|
||||
system.cpu.misc_regfile_reads 135543435 # number of misc regfile reads
|
||||
system.cpu.misc_regfile_writes 912729 # number of misc regfile writes
|
||||
system.cpu.icache.replacements 1019271 # number of replacements
|
||||
system.cpu.icache.tagsinuse 511.444719 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 12598089 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 1019783 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 12.353696 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 6290137000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 511.444719 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.998915 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.998915 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 12598089 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 12598089 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 12598089 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 12598089 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 12598089 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 12598089 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 1111711 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 1111711 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 1111711 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 1111711 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 1111711 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 1111711 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 16369836984 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 16369836984 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 16369836984 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 16369836984 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 16369836984 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 16369836984 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 13709800 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 13709800 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 13709800 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 13709800 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 13709800 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 13709800 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.081089 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.081089 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.081089 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.081089 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.081089 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.081089 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14724.903310 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 14724.903310 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 14724.903310 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 14724.903310 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 14724.903310 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 14724.903310 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 2973484 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 393 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs 7566.117048 # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks::writebacks 60091 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 60091 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 91891 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::total 91891 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::cpu.inst 91891 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::total 91891 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::cpu.inst 91891 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::total 91891 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1019820 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 1019820 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 1019820 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 1019820 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 1019820 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 1019820 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12187570984 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 12187570984 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12187570984 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 12187570984 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12187570984 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 12187570984 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 7292000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 7292000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 7292000 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency::total 7292000 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.074386 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.074386 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.074386 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.074386 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.074386 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.074386 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11950.707952 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11950.707952 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11950.707952 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 11950.707952 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11950.707952 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 11950.707952 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 645895 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 511.991565 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 22075422 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 646407 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 34.150964 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 49188000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 511.991565 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.999984 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.999984 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 14216478 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 14216478 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 7283636 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 7283636 # number of WriteReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::cpu.data 286092 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::total 286092 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::cpu.data 285655 # number of StoreCondReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::total 285655 # number of StoreCondReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 21500114 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 21500114 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 21500114 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 21500114 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 747655 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 747655 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 2966865 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 2966865 # number of WriteReq misses
|
||||
system.cpu.dcache.LoadLockedReq_misses::cpu.data 13747 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.LoadLockedReq_misses::total 13747 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.StoreCondReq_misses::cpu.data 13 # number of StoreCondReq misses
|
||||
system.cpu.dcache.StoreCondReq_misses::total 13 # number of StoreCondReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 3714520 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 3714520 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 3714520 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 3714520 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 11237363500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 11237363500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 110154178240 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 110154178240 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 224042000 # number of LoadLockedReq miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_miss_latency::total 224042000 # number of LoadLockedReq miss cycles
|
||||
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 394000 # number of StoreCondReq miss cycles
|
||||
system.cpu.dcache.StoreCondReq_miss_latency::total 394000 # number of StoreCondReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 121391541740 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 121391541740 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 121391541740 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 121391541740 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 14964133 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 14964133 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 10250501 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 10250501 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 299839 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::total 299839 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::cpu.data 285668 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::total 285668 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 25214634 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 25214634 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 25214634 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 25214634 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.049963 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.049963 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289436 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.289436 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045848 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045848 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000046 # miss rate for StoreCondReq accesses
|
||||
system.cpu.dcache.StoreCondReq_miss_rate::total 0.000046 # miss rate for StoreCondReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.147316 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.147316 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.147316 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.147316 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15030.145589 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 15030.145589 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37128.139717 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 37128.139717 # average WriteReq miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16297.519459 # average LoadLockedReq miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16297.519459 # average LoadLockedReq miss latency
|
||||
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 30307.692308 # average StoreCondReq miss latency
|
||||
system.cpu.dcache.StoreCondReq_avg_miss_latency::total 30307.692308 # average StoreCondReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 32680.276789 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 32680.276789 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 32680.276789 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 32680.276789 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 17091437 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 7607500 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 3024 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 268 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 5651.930225 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets 28386.194030 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 574932 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 574932 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 359686 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 359686 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2717440 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 2717440 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1386 # number of LoadLockedReq MSHR hits
|
||||
system.cpu.dcache.LoadLockedReq_mshr_hits::total 1386 # number of LoadLockedReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 3077126 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 3077126 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 3077126 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 3077126 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 387969 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 387969 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249425 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 249425 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12361 # number of LoadLockedReq MSHR misses
|
||||
system.cpu.dcache.LoadLockedReq_mshr_misses::total 12361 # number of LoadLockedReq MSHR misses
|
||||
system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 13 # number of StoreCondReq MSHR misses
|
||||
system.cpu.dcache.StoreCondReq_mshr_misses::total 13 # number of StoreCondReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 637394 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 637394 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 637394 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 637394 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5287973500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 5287973500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8908906437 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 8908906437 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 165672500 # number of LoadLockedReq MSHR miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 165672500 # number of LoadLockedReq MSHR miss cycles
|
||||
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 351500 # number of StoreCondReq MSHR miss cycles
|
||||
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 351500 # number of StoreCondReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14196879937 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 14196879937 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14196879937 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 14196879937 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 147151877500 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 147151877500 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 42255772015 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 42255772015 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 189407649515 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency::total 189407649515 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.025927 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.025927 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024333 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024333 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.041225 # mshr miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.041225 # mshr miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000046 # mshr miss rate for StoreCondReq accesses
|
||||
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000046 # mshr miss rate for StoreCondReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025279 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.025279 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025279 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.025279 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13629.886666 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13629.886666 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35717.776634 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35717.776634 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13402.839576 # average LoadLockedReq mshr miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13402.839576 # average LoadLockedReq mshr miss latency
|
||||
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 27038.461538 # average StoreCondReq mshr miss latency
|
||||
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 27038.461538 # average StoreCondReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22273.319073 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 22273.319073 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22273.319073 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 22273.319073 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.iocache.replacements 0 # number of replacements
|
||||
system.iocache.tagsinuse 0 # Cycle average of tags in use
|
||||
system.iocache.total_refs 0 # Total number of references to valid blocks.
|
||||
system.iocache.sampled_refs 0 # Sample count of references to valid blocks.
|
||||
system.iocache.avg_refs nan # Average number of references to valid blocks.
|
||||
system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.iocache.fast_writes 0 # number of fast writes performed
|
||||
system.iocache.cache_copies 0 # number of cache copies performed
|
||||
system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1296131413558 # number of ReadReq MSHR uncacheable cycles
|
||||
system.iocache.ReadReq_mshr_uncacheable_latency::total 1296131413558 # number of ReadReq MSHR uncacheable cycles
|
||||
system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1296131413558 # number of overall MSHR uncacheable cycles
|
||||
system.iocache.overall_mshr_uncacheable_latency::total 1296131413558 # number of overall MSHR uncacheable cycles
|
||||
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
|
||||
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
||||
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
|
||||
system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
||||
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
||||
system.cpu.kern.inst.quiesce 88053 # number of quiesce instructions executed
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
Binary file not shown.
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,9 @@
|
||||
warn: Sockets disabled, not accepting terminal connections
|
||||
warn: Reading current count from inactive timer.
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: Don't know what interrupt to clear for console.
|
||||
warn: instruction 'fxsave' unimplemented
|
||||
warn: Tried to clear PCI interrupt 14
|
||||
warn: Unknown mouse command 0xe1.
|
||||
warn: instruction 'wbinvd' unimplemented
|
||||
hack: be nice to actually delete the event here
|
||||
@ -0,0 +1,13 @@
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jun 4 2012 13:44:28
|
||||
gem5 started Jun 4 2012 17:03:49
|
||||
gem5 executing on zizzer
|
||||
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing -re tests/run.py build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing
|
||||
warning: add_child('terminal'): child 'terminal' already has parent
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
|
||||
0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 5157514159500 because m5_exit instruction encountered
|
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,133 @@
|
||||
Linux version 2.6.22.9 (blackga@nacho) (gcc version 4.1.2 (Gentoo 4.1.2)) #2 Mon Oct 8 13:13:00 PDT 2007
|
||||
Command line: earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1
|
||||
BIOS-provided physical RAM map:
|
||||
BIOS-e820: 0000000000000000 - 0000000000100000 (reserved)
|
||||
BIOS-e820: 0000000000100000 - 0000000008000000 (usable)
|
||||
end_pfn_map = 32768
|
||||
kernel direct mapping tables up to 8000000 @ 100000-102000
|
||||
DMI 2.5 present.
|
||||
Zone PFN ranges:
|
||||
DMA 256 -> 4096
|
||||
DMA32 4096 -> 1048576
|
||||
Normal 1048576 -> 1048576
|
||||
early_node_map[1] active PFN ranges
|
||||
0: 256 -> 32768
|
||||
Intel MultiProcessor Specification v1.4
|
||||
MPTABLE: OEM ID: MPTABLE: Product ID: MPTABLE: APIC at: 0xFEE00000
|
||||
Processor #0 (Bootup-CPU)
|
||||
I/O APIC #1 at 0xFEC00000.
|
||||
Setting APIC routing to flat
|
||||
Processors: 1
|
||||
Allocating PCI resources starting at 10000000 (gap: 8000000:f8000000)
|
||||
Built 1 zonelists. Total pages: 30458
|
||||
Kernel command line: earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1
|
||||
Initializing CPU#0
|
||||
PID hash table entries: 512 (order: 9, 4096 bytes)
|
||||
time.c: Detected 2000.000 MHz processor.
|
||||
Console: colour dummy device 80x25
|
||||
console handover: boot [earlyser0] -> real [ttyS0]
|
||||
Dentry cache hash table entries: 16384 (order: 5, 131072 bytes)
|
||||
Inode-cache hash table entries: 8192 (order: 4, 65536 bytes)
|
||||
Checking aperture...
|
||||
Memory: 121556k/131072k available (3742k kernel code, 8456k reserved, 1874k data, 232k init)
|
||||
Calibrating delay loop (skipped)... 3999.96 BogoMIPS preset
|
||||
Mount-cache hash table entries: 256
|
||||
CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)
|
||||
CPU: L2 Cache: 1024K (64 bytes/line)
|
||||
CPU: Fake M5 x86_64 CPU stepping 01
|
||||
ACPI: Core revision 20070126
|
||||
ACPI Exception (tbxface-0618): AE_NO_ACPI_TABLES, While loading namespace from ACPI tables [20070126]
|
||||
ACPI: Unable to load the System Description Tables
|
||||
Using local APIC timer interrupts.
|
||||
result 7812497
|
||||
Detected 7.812 MHz APIC timer.
|
||||
NET: Registered protocol family 16
|
||||
PCI: Using configuration type 1
|
||||
ACPI: Interpreter disabled.
|
||||
Linux Plug and Play Support v0.97 (c) Adam Belay
|
||||
pnp: PnP ACPI: disabled
|
||||
SCSI subsystem initialized
|
||||
usbcore: registered new interface driver usbfs
|
||||
usbcore: registered new interface driver hub
|
||||
usbcore: registered new device driver usb
|
||||
PCI: Probing PCI hardware
|
||||
PCI-GART: No AMD northbridge found.
|
||||
NET: Registered protocol family 2
|
||||
Time: tsc clocksource has been installed.
|
||||
IP route cache hash table entries: 1024 (order: 1, 8192 bytes)
|
||||
TCP established hash table entries: 4096 (order: 4, 65536 bytes)
|
||||
TCP bind hash table entries: 4096 (order: 3, 32768 bytes)
|
||||
TCP: Hash tables configured (established 4096 bind 4096)
|
||||
TCP reno registered
|
||||
Total HugeTLB memory allocated, 0
|
||||
Installing knfsd (copyright (C) 1996 okir@monad.swb.de).
|
||||
io scheduler noop registered
|
||||
io scheduler deadline registered
|
||||
io scheduler cfq registered (default)
|
||||
Real Time Clock Driver v1.12ac
|
||||
Linux agpgart interface v0.102 (c) Dave Jones
|
||||
Serial: 8250/16550 driver $Revision: 1.90 $ 4 ports, IRQ sharing disabled
|
||||
serial8250: ttyS0 at I/O 0x3f8 (irq = 4) is a 8250
|
||||
floppy0: no floppy controllers found
|
||||
RAMDISK driver initialized: 16 RAM disks of 4096K size 1024 blocksize
|
||||
loop: module loaded
|
||||
Intel(R) PRO/1000 Network Driver - version 7.3.20-k2
|
||||
Copyright (c) 1999-2006 Intel Corporation.
|
||||
e100: Intel(R) PRO/100 Network Driver, 3.5.17-k4-NAPI
|
||||
e100: Copyright(c) 1999-2006 Intel Corporation
|
||||
forcedeth.c: Reverse Engineered nForce ethernet driver. Version 0.60.
|
||||
tun: Universal TUN/TAP device driver, 1.6
|
||||
tun: (C) 1999-2004 Max Krasnyansky <maxk@qualcomm.com>
|
||||
netconsole: not configured, aborting
|
||||
Uniform Multi-Platform E-IDE driver Revision: 7.00alpha2
|
||||
ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx
|
||||
PIIX4: IDE controller at PCI slot 0000:00:04.0
|
||||
PCI: Enabling device 0000:00:04.0 (0000 -> 0001)
|
||||
PIIX4: chipset revision 0
|
||||
PIIX4: not 100% native mode: will probe irqs later
|
||||
ide0: BM-DMA at 0x1000-0x1007, BIOS settings: hda:DMA, hdb:DMA
|
||||
ide1: BM-DMA at 0x1008-0x100f, BIOS settings: hdc:DMA, hdd:DMA
|
||||
hda: M5 IDE Disk, ATA DISK drive
|
||||
hdb: M5 IDE Disk, ATA DISK drive
|
||||
ide0 at 0x1f0-0x1f7,0x3f6 on irq 14
|
||||
hda: max request size: 128KiB
|
||||
hda: 1048320 sectors (536 MB), CHS=1040/16/63, UDMA(33)
|
||||
hda: hda1
|
||||
hdb: max request size: 128KiB
|
||||
hdb: 4177920 sectors (2139 MB), CHS=4144/16/63, UDMA(33)
|
||||
hdb: unknown partition table
|
||||
megaraid cmm: 2.20.2.7 (Release Date: Sun Jul 16 00:01:03 EST 2006)
|
||||
megaraid: 2.20.5.1 (Release Date: Thu Nov 16 15:32:35 EST 2006)
|
||||
megasas: 00.00.03.10-rc5 Thu May 17 10:09:32 PDT 2007
|
||||
Fusion MPT base driver 3.04.04
|
||||
Copyright (c) 1999-2007 LSI Logic Corporation
|
||||
Fusion MPT SPI Host driver 3.04.04
|
||||
Fusion MPT SAS Host driver 3.04.04
|
||||
ieee1394: raw1394: /dev/raw1394 device initialized
|
||||
USB Universal Host Controller Interface driver v3.0
|
||||
usbcore: registered new interface driver usblp
|
||||
drivers/usb/class/usblp.c: v0.13: USB Printer Device Class driver
|
||||
Initializing USB Mass Storage driver...
|
||||
usbcore: registered new interface driver usb-storage
|
||||
USB Mass Storage support registered.
|
||||
PNP: No PS/2 controller found. Probing ports directly.
|
||||
serio: i8042 KBD port at 0x60,0x64 irq 1
|
||||
serio: i8042 AUX port at 0x60,0x64 irq 12
|
||||
mice: PS/2 mouse device common for all mice
|
||||
input: AT Translated Set 2 keyboard as /class/input/input0
|
||||
device-mapper: ioctl: 4.11.0-ioctl (2006-10-12) initialised: dm-devel@redhat.com
|
||||
input: PS/2 Generic Mouse as /class/input/input1
|
||||
usbcore: registered new interface driver usbhid
|
||||
drivers/hid/usbhid/hid-core.c: v2.6:USB HID core driver
|
||||
oprofile: using timer interrupt.
|
||||
TCP cubic registered
|
||||
NET: Registered protocol family 1
|
||||
NET: Registered protocol family 10
|
||||
IPv6 over IPv4 tunneling driver
|
||||
NET: Registered protocol family 17
|
||||
EXT2-fs warning: mounting unchecked fs, running e2fsck is recommended
|
||||
VFS: Mounted root (ext2 filesystem).
|
||||
Freeing unused kernel memory: 232k freed
|
||||
|
||||
INIT: version 2.86 booting
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,708 @@
|
||||
|
||||
================ Begin RubySystem Configuration Print ================
|
||||
|
||||
RubySystem config:
|
||||
random_seed: 1234
|
||||
randomization: 0
|
||||
cycle_period: 500
|
||||
block_size_bytes: 64
|
||||
block_size_bits: 6
|
||||
memory_size_bytes: 134217728
|
||||
memory_size_bits: 27
|
||||
|
||||
Network Configuration
|
||||
---------------------
|
||||
network: SIMPLE_NETWORK
|
||||
topology:
|
||||
|
||||
virtual_net_0: active, unordered
|
||||
virtual_net_1: active, ordered
|
||||
virtual_net_2: active, unordered
|
||||
virtual_net_3: inactive
|
||||
virtual_net_4: inactive
|
||||
virtual_net_5: inactive
|
||||
virtual_net_6: inactive
|
||||
virtual_net_7: inactive
|
||||
virtual_net_8: inactive
|
||||
virtual_net_9: inactive
|
||||
|
||||
|
||||
Profiler Configuration
|
||||
----------------------
|
||||
periodic_stats_period: 1000000
|
||||
|
||||
================ End RubySystem Configuration Print ================
|
||||
|
||||
|
||||
Real time: Jun/04/2012 17:25:31
|
||||
|
||||
Profiler Stats
|
||||
--------------
|
||||
Elapsed_time_in_seconds: 842
|
||||
Elapsed_time_in_minutes: 14.0333
|
||||
Elapsed_time_in_hours: 0.233889
|
||||
Elapsed_time_in_days: 0.00974537
|
||||
|
||||
Virtual_time_in_seconds: 842.03
|
||||
Virtual_time_in_minutes: 14.0338
|
||||
Virtual_time_in_hours: 0.233897
|
||||
Virtual_time_in_days: 0.00974572
|
||||
|
||||
Ruby_current_time: 10609379371
|
||||
Ruby_start_time: 0
|
||||
Ruby_cycles: 10609379371
|
||||
|
||||
mbytes_resident: 268.047
|
||||
mbytes_total: 470.199
|
||||
resident_ratio: 0.570071
|
||||
|
||||
ruby_cycles_executed: [ 10609379372 10609379372 ]
|
||||
|
||||
Busy Controller Counts:
|
||||
L1Cache-0:0 L1Cache-1:0
|
||||
L2Cache-0:0
|
||||
Directory-0:0
|
||||
DMA-0:0
|
||||
|
||||
Busy Bank Count:0
|
||||
|
||||
sequencer_requests_outstanding: [binsize: 1 max: 2 count: 187820632 average: 1.00009 | standard deviation: 0.00953306 | 0 187803562 17070 ]
|
||||
|
||||
All Non-Zero Cycle Demand Cache Accesses
|
||||
----------------------------------------
|
||||
miss_latency: [binsize: 1 max: 171 count: 187820631 average: 3.39134 | standard deviation: 5.2186 | 0 0 0 185167359 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 968687 360 299 324 1431839 442 29 55471 396 374 169 16721 201 124 40 32 58 1 1 3 2 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12771 11 6 12 99731 53 39 34 64890 57 7 6 12 49 6 0 1 5 5 ]
|
||||
miss_latency_LD: [binsize: 1 max: 171 count: 14904214 average: 5.1415 | standard deviation: 9.3064 | 0 0 0 13521342 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 127527 49 51 45 1194807 288 8 19874 224 232 85 4872 149 99 34 25 32 1 1 2 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2618 2 2 1 16177 17 7 5 15599 14 3 1 4 10 3 0 0 1 1 ]
|
||||
miss_latency_ST: [binsize: 1 max: 171 count: 9480962 average: 5.51309 | standard deviation: 17.8961 | 0 0 0 9129497 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 28986 16 10 12 180921 99 2 14858 85 68 52 1857 24 15 2 2 7 0 0 0 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4517 5 0 4 70891 24 21 21 48866 33 3 5 5 39 3 0 1 4 4 ]
|
||||
miss_latency_IFETCH: [binsize: 1 max: 165 count: 162265044 average: 3.09464 | standard deviation: 1.92336 | 0 0 0 161451088 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 795815 273 223 254 225 27 19 28 19 28 0 0 0 0 0 0 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5358 4 4 7 11621 10 11 8 3 9 0 0 3 ]
|
||||
miss_latency_RMW_Read: [binsize: 1 max: 163 count: 492779 average: 6.1766 | standard deviation: 10.7903 | 0 0 0 426659 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10783 15 11 11 33161 10 0 12125 33 16 10 8497 16 8 2 2 6 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 227 0 0 0 868 1 0 0 315 1 1 ]
|
||||
miss_latency_Locked_RMW_Read: [binsize: 1 max: 161 count: 338816 average: 5.46921 | standard deviation: 8.08396 | 0 0 0 299957 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5576 7 4 2 22725 18 0 8586 35 30 22 1495 12 2 2 3 6 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 51 0 0 0 174 1 0 0 107 ]
|
||||
miss_latency_Locked_RMW_Write: [binsize: 1 max: 3 count: 338816 average: 3 | standard deviation: 0 | 0 0 0 338816 ]
|
||||
miss_latency_NULL: [binsize: 1 max: 171 count: 187820631 average: 3.39134 | standard deviation: 5.2186 | 0 0 0 185167359 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 968687 360 299 324 1431839 442 29 55471 396 374 169 16721 201 124 40 32 58 1 1 3 2 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12771 11 6 12 99731 53 39 34 64890 57 7 6 12 49 6 0 1 5 5 ]
|
||||
miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
imcomplete_wCC_Times: 0
|
||||
miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
imcomplete_dir_Times: 0
|
||||
miss_latency_LD_NULL: [binsize: 1 max: 171 count: 14904214 average: 5.1415 | standard deviation: 9.3064 | 0 0 0 13521342 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 127527 49 51 45 1194807 288 8 19874 224 232 85 4872 149 99 34 25 32 1 1 2 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2618 2 2 1 16177 17 7 5 15599 14 3 1 4 10 3 0 0 1 1 ]
|
||||
miss_latency_ST_NULL: [binsize: 1 max: 171 count: 9480962 average: 5.51309 | standard deviation: 17.8961 | 0 0 0 9129497 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 28986 16 10 12 180921 99 2 14858 85 68 52 1857 24 15 2 2 7 0 0 0 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4517 5 0 4 70891 24 21 21 48866 33 3 5 5 39 3 0 1 4 4 ]
|
||||
miss_latency_IFETCH_NULL: [binsize: 1 max: 165 count: 162265044 average: 3.09464 | standard deviation: 1.92336 | 0 0 0 161451088 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 795815 273 223 254 225 27 19 28 19 28 0 0 0 0 0 0 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5358 4 4 7 11621 10 11 8 3 9 0 0 3 ]
|
||||
miss_latency_RMW_Read_NULL: [binsize: 1 max: 163 count: 492779 average: 6.1766 | standard deviation: 10.7903 | 0 0 0 426659 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10783 15 11 11 33161 10 0 12125 33 16 10 8497 16 8 2 2 6 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 227 0 0 0 868 1 0 0 315 1 1 ]
|
||||
miss_latency_Locked_RMW_Read_NULL: [binsize: 1 max: 161 count: 338816 average: 5.46921 | standard deviation: 8.08396 | 0 0 0 299957 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5576 7 4 2 22725 18 0 8586 35 30 22 1495 12 2 2 3 6 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 51 0 0 0 174 1 0 0 107 ]
|
||||
miss_latency_Locked_RMW_Write_NULL: [binsize: 1 max: 3 count: 338816 average: 3 | standard deviation: 0 | 0 0 0 338816 ]
|
||||
|
||||
All Non-Zero Cycle SW Prefetch Requests
|
||||
------------------------------------
|
||||
prefetch_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
prefetch_latency_L2Miss:[binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
Request vs. RubySystem State Profile
|
||||
--------------------------------
|
||||
|
||||
|
||||
filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
||||
Message Delayed Cycles
|
||||
----------------------
|
||||
Total_delay_cycles: [binsize: 1 max: 13 count: 10850974 average: 0.59462 | standard deviation: 1.42374 | 9237583 1029 657 892 1609097 1059 106 119 110 244 9 6 16 47 ]
|
||||
Total_nonPF_delay_cycles: [binsize: 1 max: 9 count: 4764816 average: 0.0223746 | standard deviation: 0.296857 | 4737436 520 425 679 25631 106 3 1 10 5 ]
|
||||
virtual_network_0_delay_cycles: [binsize: 1 max: 13 count: 6086158 average: 1.04263 | standard deviation: 1.75725 | 4500147 509 232 213 1583466 953 103 118 100 239 9 6 16 47 ]
|
||||
virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_2_delay_cycles: [binsize: 1 max: 9 count: 83533 average: 0.0149761 | standard deviation: 0.225696 | 83067 123 97 98 116 28 0 0 0 4 ]
|
||||
virtual_network_3_delay_cycles: [binsize: 1 max: 9 count: 4681283 average: 0.0225067 | standard deviation: 0.297971 | 4654369 397 328 581 25515 78 3 1 10 1 ]
|
||||
virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_6_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_7_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_8_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_9_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
||||
Resource Usage
|
||||
--------------
|
||||
page_size: 4096
|
||||
user_time: 841
|
||||
system_time: 0
|
||||
page_reclaims: 69674
|
||||
page_faults: 18
|
||||
swaps: 0
|
||||
block_inputs: 16056
|
||||
block_outputs: 408
|
||||
|
||||
Network Stats
|
||||
-------------
|
||||
|
||||
total_msg_count_Control: 8492901 67943208
|
||||
total_msg_count_Request_Control: 248654 1989232
|
||||
total_msg_count_Response_Data: 8788194 632749968
|
||||
total_msg_count_Response_Control: 10854297 86834376
|
||||
total_msg_count_Writeback_Data: 4753752 342270144
|
||||
total_msg_count_Writeback_Control: 282753 2262024
|
||||
total_msgs: 33420551 total_bytes: 1134048952
|
||||
|
||||
switch_0_inlinks: 2
|
||||
switch_0_outlinks: 2
|
||||
links_utilized_percent_switch_0: 0.0323999
|
||||
links_utilized_percent_switch_0_link_0: 0.0382499 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_0_link_1: 0.02655 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_0_link_0_Request_Control: 42688 341504 [ 42688 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Response_Data: 842729 60676488 [ 0 842729 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Response_Control: 488898 3911184 [ 0 488898 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Control: 855066 6840528 [ 855066 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Response_Data: 40424 2910528 [ 0 40424 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Response_Control: 517774 4142192 [ 0 16296 501478 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Writeback_Data: 429162 30899664 [ 429108 54 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Writeback_Control: 34458 275664 [ 34458 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_1_inlinks: 2
|
||||
switch_1_outlinks: 2
|
||||
links_utilized_percent_switch_1: 0.0735359
|
||||
links_utilized_percent_switch_1_link_0: 0.0818749 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_1_link_1: 0.0651969 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_1_link_0_Request_Control: 40845 326760 [ 40845 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Response_Data: 1788501 128772072 [ 0 1788501 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Response_Control: 1235479 9883832 [ 0 1235479 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Control: 1798206 14385648 [ 1798206 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Response_Data: 34071 2453112 [ 0 34071 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Response_Control: 1270539 10164312 [ 0 17798 1252741 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Writeback_Data: 1155422 83190384 [ 1155308 114 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Writeback_Control: 59793 478344 [ 59793 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_2_inlinks: 2
|
||||
switch_2_outlinks: 2
|
||||
links_utilized_percent_switch_2: 0.110241
|
||||
links_utilized_percent_switch_2_link_0: 0.0976111 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_2_link_1: 0.122871 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_2_link_0_Control: 2653272 21226176 [ 2653272 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Response_Data: 202919 14610168 [ 0 202919 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Response_Control: 1876808 15014464 [ 0 122589 1754219 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Writeback_Data: 1584584 114090048 [ 1584416 168 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Writeback_Control: 94251 754008 [ 94251 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Control: 177695 1421560 [ 177695 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Request_Control: 81588 652704 [ 81588 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Response_Data: 2677208 192758976 [ 0 2677208 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Response_Control: 1717623 13740984 [ 0 1717623 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_3_inlinks: 2
|
||||
switch_3_outlinks: 2
|
||||
links_utilized_percent_switch_3: 0.00651138
|
||||
links_utilized_percent_switch_3_link_0: 0.00495717 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_3_link_1: 0.00806559 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_3_link_0_Control: 177695 1421560 [ 177695 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_Response_Data: 95249 6857928 [ 0 95249 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_Response_Control: 16914 135312 [ 0 16914 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Response_Data: 177695 12794040 [ 0 177695 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Response_Control: 112163 897304 [ 0 112163 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_4_inlinks: 2
|
||||
switch_4_outlinks: 2
|
||||
links_utilized_percent_switch_4: 0
|
||||
links_utilized_percent_switch_4_link_0: 0 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_4_link_1: 0 bw: 16000 base_latency: 1
|
||||
|
||||
|
||||
switch_5_inlinks: 5
|
||||
switch_5_outlinks: 5
|
||||
links_utilized_percent_switch_5: 0.0445386
|
||||
links_utilized_percent_switch_5_link_0: 0.0382499 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_5_link_1: 0.0818749 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_5_link_2: 0.0976111 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_5_link_3: 0.00495717 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_5_link_4: 0 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_5_link_0_Request_Control: 42688 341504 [ 42688 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_0_Response_Data: 842729 60676488 [ 0 842729 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_0_Response_Control: 488898 3911184 [ 0 488898 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_1_Request_Control: 40845 326760 [ 40845 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_1_Response_Data: 1788501 128772072 [ 0 1788501 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_1_Response_Control: 1235479 9883832 [ 0 1235479 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_2_Control: 2653272 21226176 [ 2653272 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_2_Response_Data: 202919 14610168 [ 0 202919 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_2_Response_Control: 1876808 15014464 [ 0 122589 1754219 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_2_Writeback_Data: 1584584 114090048 [ 1584416 168 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_2_Writeback_Control: 94251 754008 [ 94251 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_3_Control: 177695 1421560 [ 177695 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_3_Response_Data: 95249 6857928 [ 0 95249 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_3_Response_Control: 16914 135312 [ 0 16914 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
Cache Stats: system.l1_cntrl0.L1IcacheMemory
|
||||
system.l1_cntrl0.L1IcacheMemory_total_misses: 326846
|
||||
system.l1_cntrl0.L1IcacheMemory_total_demand_misses: 326846
|
||||
system.l1_cntrl0.L1IcacheMemory_total_prefetches: 0
|
||||
system.l1_cntrl0.L1IcacheMemory_total_sw_prefetches: 0
|
||||
system.l1_cntrl0.L1IcacheMemory_total_hw_prefetches: 0
|
||||
|
||||
system.l1_cntrl0.L1IcacheMemory_request_type_IFETCH: 100%
|
||||
|
||||
system.l1_cntrl0.L1IcacheMemory_access_mode_type_Supervisor: 326846 100%
|
||||
|
||||
Cache Stats: system.l1_cntrl0.L1DcacheMemory
|
||||
system.l1_cntrl0.L1DcacheMemory_total_misses: 528220
|
||||
system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 528220
|
||||
system.l1_cntrl0.L1DcacheMemory_total_prefetches: 0
|
||||
system.l1_cntrl0.L1DcacheMemory_total_sw_prefetches: 0
|
||||
system.l1_cntrl0.L1DcacheMemory_total_hw_prefetches: 0
|
||||
|
||||
system.l1_cntrl0.L1DcacheMemory_request_type_LD: 54.1774%
|
||||
system.l1_cntrl0.L1DcacheMemory_request_type_ST: 45.8226%
|
||||
|
||||
system.l1_cntrl0.L1DcacheMemory_access_mode_type_Supervisor: 528220 100%
|
||||
|
||||
--- L1Cache ---
|
||||
- Event Counts -
|
||||
Load [6224073 8680141 ] 14904214
|
||||
Ifetch [103471616 58793435 ] 162265051
|
||||
Store [5279560 5371813 ] 10651373
|
||||
Inv [16350 17912 ] 34262
|
||||
L1_Replacement [827635 1770998 ] 2598633
|
||||
Fwd_GETX [12252 11795 ] 24047
|
||||
Fwd_GETS [14082 11138 ] 25220
|
||||
Fwd_GET_INSTR [4 0 ] 4
|
||||
Data [658 968 ] 1626
|
||||
Data_Exclusive [248296 1024255 ] 1272551
|
||||
DataS_fromL1 [11138 14086 ] 25224
|
||||
Data_all_Acks [582637 749192 ] 1331829
|
||||
Ack [12337 9705 ] 22042
|
||||
Ack_all [12995 10673 ] 23668
|
||||
WB_Ack [463566 1215101 ] 1678667
|
||||
|
||||
- Transitions -
|
||||
NP Load [277889 1086402 ] 1364291
|
||||
NP Ifetch [326723 486562 ] 813285
|
||||
NP Store [224047 199057 ] 423104
|
||||
NP Inv [5639 4132 ] 9771
|
||||
NP L1_Replacement [0 0 ] 0
|
||||
|
||||
I Load [8287 10294 ] 18581
|
||||
I Ifetch [123 548 ] 671
|
||||
I Store [5660 5638 ] 11298
|
||||
I Inv [0 0 ] 0
|
||||
I L1_Replacement [8798 9094 ] 17892
|
||||
|
||||
S Load [577238 501390 ] 1078628
|
||||
S Ifetch [103144768 58306320 ] 161451088
|
||||
S Store [12337 9705 ] 22042
|
||||
S Inv [10590 13636 ] 24226
|
||||
S L1_Replacement [355271 546803 ] 902074
|
||||
|
||||
E Load [1142385 2670000 ] 3812385
|
||||
E Ifetch [0 0 ] 0
|
||||
E Store [81265 85104 ] 166369
|
||||
E Inv [67 30 ] 97
|
||||
E L1_Replacement [165622 937435 ] 1103057
|
||||
E Fwd_GETX [352 103 ] 455
|
||||
E Fwd_GETS [877 1394 ] 2271
|
||||
E Fwd_GET_INSTR [0 0 ] 0
|
||||
|
||||
M Load [4218274 4412055 ] 8630329
|
||||
M Ifetch [0 0 ] 0
|
||||
M Store [4956251 5072309 ] 10028560
|
||||
M Inv [54 114 ] 168
|
||||
M L1_Replacement [297944 277666 ] 575610
|
||||
M Fwd_GETX [11900 11692 ] 23592
|
||||
M Fwd_GETS [13205 9744 ] 22949
|
||||
M Fwd_GET_INSTR [4 0 ] 4
|
||||
|
||||
IS Load [0 0 ] 0
|
||||
IS Ifetch [0 0 ] 0
|
||||
IS Store [0 0 ] 0
|
||||
IS Inv [0 0 ] 0
|
||||
IS L1_Replacement [0 0 ] 0
|
||||
IS Data_Exclusive [248296 1024255 ] 1272551
|
||||
IS DataS_fromL1 [11138 14086 ] 25224
|
||||
IS Data_all_Acks [353588 545465 ] 899053
|
||||
|
||||
IM Load [0 0 ] 0
|
||||
IM Ifetch [0 0 ] 0
|
||||
IM Store [0 0 ] 0
|
||||
IM Inv [0 0 ] 0
|
||||
IM L1_Replacement [0 0 ] 0
|
||||
IM Data [658 968 ] 1626
|
||||
IM Data_all_Acks [229049 203727 ] 432776
|
||||
IM Ack [0 0 ] 0
|
||||
|
||||
SM Load [0 0 ] 0
|
||||
SM Ifetch [0 0 ] 0
|
||||
SM Store [0 0 ] 0
|
||||
SM Inv [0 0 ] 0
|
||||
SM L1_Replacement [0 0 ] 0
|
||||
SM Ack [12337 9705 ] 22042
|
||||
SM Ack_all [12995 10673 ] 23668
|
||||
|
||||
IS_I Load [0 0 ] 0
|
||||
IS_I Ifetch [0 0 ] 0
|
||||
IS_I Store [0 0 ] 0
|
||||
IS_I Inv [0 0 ] 0
|
||||
IS_I L1_Replacement [0 0 ] 0
|
||||
IS_I Data_Exclusive [0 0 ] 0
|
||||
IS_I DataS_fromL1 [0 0 ] 0
|
||||
IS_I Data_all_Acks [0 0 ] 0
|
||||
|
||||
M_I Load [0 0 ] 0
|
||||
M_I Ifetch [2 5 ] 7
|
||||
M_I Store [0 0 ] 0
|
||||
M_I Inv [0 0 ] 0
|
||||
M_I L1_Replacement [0 0 ] 0
|
||||
M_I Fwd_GETX [0 0 ] 0
|
||||
M_I Fwd_GETS [0 0 ] 0
|
||||
M_I Fwd_GET_INSTR [0 0 ] 0
|
||||
M_I WB_Ack [463566 1215101 ] 1678667
|
||||
|
||||
SINK_WB_ACK Load [0 0 ] 0
|
||||
SINK_WB_ACK Ifetch [0 0 ] 0
|
||||
SINK_WB_ACK Store [0 0 ] 0
|
||||
SINK_WB_ACK Inv [0 0 ] 0
|
||||
SINK_WB_ACK L1_Replacement [0 0 ] 0
|
||||
SINK_WB_ACK WB_Ack [0 0 ] 0
|
||||
|
||||
Cache Stats: system.l1_cntrl1.L1IcacheMemory
|
||||
system.l1_cntrl1.L1IcacheMemory_total_misses: 487110
|
||||
system.l1_cntrl1.L1IcacheMemory_total_demand_misses: 487110
|
||||
system.l1_cntrl1.L1IcacheMemory_total_prefetches: 0
|
||||
system.l1_cntrl1.L1IcacheMemory_total_sw_prefetches: 0
|
||||
system.l1_cntrl1.L1IcacheMemory_total_hw_prefetches: 0
|
||||
|
||||
system.l1_cntrl1.L1IcacheMemory_request_type_IFETCH: 100%
|
||||
|
||||
system.l1_cntrl1.L1IcacheMemory_access_mode_type_Supervisor: 487110 100%
|
||||
|
||||
Cache Stats: system.l1_cntrl1.L1DcacheMemory
|
||||
system.l1_cntrl1.L1DcacheMemory_total_misses: 1311096
|
||||
system.l1_cntrl1.L1DcacheMemory_total_demand_misses: 1311096
|
||||
system.l1_cntrl1.L1DcacheMemory_total_prefetches: 0
|
||||
system.l1_cntrl1.L1DcacheMemory_total_sw_prefetches: 0
|
||||
system.l1_cntrl1.L1DcacheMemory_total_hw_prefetches: 0
|
||||
|
||||
system.l1_cntrl1.L1DcacheMemory_request_type_LD: 83.6473%
|
||||
system.l1_cntrl1.L1DcacheMemory_request_type_ST: 16.3527%
|
||||
|
||||
system.l1_cntrl1.L1DcacheMemory_access_mode_type_Supervisor: 1311096 100%
|
||||
|
||||
Cache Stats: system.l2_cntrl0.L2cacheMemory
|
||||
system.l2_cntrl0.L2cacheMemory_total_misses: 226966
|
||||
system.l2_cntrl0.L2cacheMemory_total_demand_misses: 226966
|
||||
system.l2_cntrl0.L2cacheMemory_total_prefetches: 0
|
||||
system.l2_cntrl0.L2cacheMemory_total_sw_prefetches: 0
|
||||
system.l2_cntrl0.L2cacheMemory_total_hw_prefetches: 0
|
||||
|
||||
system.l2_cntrl0.L2cacheMemory_request_type_GETS: 26.2969%
|
||||
system.l2_cntrl0.L2cacheMemory_request_type_GET_INSTR: 7.50861%
|
||||
system.l2_cntrl0.L2cacheMemory_request_type_GETX: 66.1945%
|
||||
|
||||
system.l2_cntrl0.L2cacheMemory_access_mode_type_Supervisor: 226966 100%
|
||||
|
||||
--- L2Cache ---
|
||||
- Event Counts -
|
||||
L1_GET_INSTR [813956 ] 813956
|
||||
L1_GETS [1383116 ] 1383116
|
||||
L1_GETX [434406 ] 434406
|
||||
L1_UPGRADE [22042 ] 22042
|
||||
L1_PUTX [1678667 ] 1678667
|
||||
L1_PUTX_old [0 ] 0
|
||||
Fwd_L1_GETX [0 ] 0
|
||||
Fwd_L1_GETS [0 ] 0
|
||||
Fwd_L1_GET_INSTR [0 ] 0
|
||||
L2_Replacement [95206 ] 95206
|
||||
L2_Replacement_clean [16957 ] 16957
|
||||
Mem_Data [177695 ] 177695
|
||||
Mem_Ack [112163 ] 112163
|
||||
WB_Data [24702 ] 24702
|
||||
WB_Data_clean [690 ] 690
|
||||
Ack [1945 ] 1945
|
||||
Ack_all [8481 ] 8481
|
||||
Unblock [25224 ] 25224
|
||||
Unblock_Cancel [0 ] 0
|
||||
Exclusive_Unblock [1728995 ] 1728995
|
||||
MEM_Inv [0 ] 0
|
||||
|
||||
- Transitions -
|
||||
NP L1_GET_INSTR [17038 ] 17038
|
||||
NP L1_GETS [34465 ] 34465
|
||||
NP L1_GETX [126192 ] 126192
|
||||
NP L1_PUTX [0 ] 0
|
||||
NP L1_PUTX_old [0 ] 0
|
||||
|
||||
SS L1_GET_INSTR [796726 ] 796726
|
||||
SS L1_GETS [85101 ] 85101
|
||||
SS L1_GETX [1832 ] 1832
|
||||
SS L1_UPGRADE [22042 ] 22042
|
||||
SS L1_PUTX [0 ] 0
|
||||
SS L1_PUTX_old [0 ] 0
|
||||
SS L2_Replacement [266 ] 266
|
||||
SS L2_Replacement_clean [8118 ] 8118
|
||||
SS MEM_Inv [0 ] 0
|
||||
|
||||
M L1_GET_INSTR [188 ] 188
|
||||
M L1_GETS [1238086 ] 1238086
|
||||
M L1_GETX [282331 ] 282331
|
||||
M L1_PUTX [0 ] 0
|
||||
M L1_PUTX_old [0 ] 0
|
||||
M L2_Replacement [94758 ] 94758
|
||||
M L2_Replacement_clean [8756 ] 8756
|
||||
M MEM_Inv [0 ] 0
|
||||
|
||||
MT L1_GET_INSTR [4 ] 4
|
||||
MT L1_GETS [25220 ] 25220
|
||||
MT L1_GETX [24047 ] 24047
|
||||
MT L1_PUTX [1678667 ] 1678667
|
||||
MT L1_PUTX_old [0 ] 0
|
||||
MT L2_Replacement [182 ] 182
|
||||
MT L2_Replacement_clean [83 ] 83
|
||||
MT MEM_Inv [0 ] 0
|
||||
|
||||
M_I L1_GET_INSTR [0 ] 0
|
||||
M_I L1_GETS [0 ] 0
|
||||
M_I L1_GETX [0 ] 0
|
||||
M_I L1_UPGRADE [0 ] 0
|
||||
M_I L1_PUTX [0 ] 0
|
||||
M_I L1_PUTX_old [0 ] 0
|
||||
M_I Mem_Ack [112163 ] 112163
|
||||
M_I MEM_Inv [0 ] 0
|
||||
|
||||
MT_I L1_GET_INSTR [0 ] 0
|
||||
MT_I L1_GETS [0 ] 0
|
||||
MT_I L1_GETX [0 ] 0
|
||||
MT_I L1_UPGRADE [0 ] 0
|
||||
MT_I L1_PUTX [0 ] 0
|
||||
MT_I L1_PUTX_old [0 ] 0
|
||||
MT_I WB_Data [125 ] 125
|
||||
MT_I WB_Data_clean [0 ] 0
|
||||
MT_I Ack_all [57 ] 57
|
||||
MT_I MEM_Inv [0 ] 0
|
||||
|
||||
MCT_I L1_GET_INSTR [0 ] 0
|
||||
MCT_I L1_GETS [0 ] 0
|
||||
MCT_I L1_GETX [0 ] 0
|
||||
MCT_I L1_UPGRADE [0 ] 0
|
||||
MCT_I L1_PUTX [0 ] 0
|
||||
MCT_I L1_PUTX_old [0 ] 0
|
||||
MCT_I WB_Data [43 ] 43
|
||||
MCT_I WB_Data_clean [0 ] 0
|
||||
MCT_I Ack_all [40 ] 40
|
||||
|
||||
I_I L1_GET_INSTR [0 ] 0
|
||||
I_I L1_GETS [0 ] 0
|
||||
I_I L1_GETX [0 ] 0
|
||||
I_I L1_UPGRADE [0 ] 0
|
||||
I_I L1_PUTX [0 ] 0
|
||||
I_I L1_PUTX_old [0 ] 0
|
||||
I_I Ack [1679 ] 1679
|
||||
I_I Ack_all [8118 ] 8118
|
||||
|
||||
S_I L1_GET_INSTR [0 ] 0
|
||||
S_I L1_GETS [0 ] 0
|
||||
S_I L1_GETX [0 ] 0
|
||||
S_I L1_UPGRADE [0 ] 0
|
||||
S_I L1_PUTX [0 ] 0
|
||||
S_I L1_PUTX_old [0 ] 0
|
||||
S_I Ack [266 ] 266
|
||||
S_I Ack_all [266 ] 266
|
||||
S_I MEM_Inv [0 ] 0
|
||||
|
||||
ISS L1_GET_INSTR [0 ] 0
|
||||
ISS L1_GETS [0 ] 0
|
||||
ISS L1_GETX [0 ] 0
|
||||
ISS L1_PUTX [0 ] 0
|
||||
ISS L1_PUTX_old [0 ] 0
|
||||
ISS L2_Replacement [0 ] 0
|
||||
ISS L2_Replacement_clean [0 ] 0
|
||||
ISS Mem_Data [34465 ] 34465
|
||||
ISS MEM_Inv [0 ] 0
|
||||
|
||||
IS L1_GET_INSTR [0 ] 0
|
||||
IS L1_GETS [0 ] 0
|
||||
IS L1_GETX [0 ] 0
|
||||
IS L1_PUTX [0 ] 0
|
||||
IS L1_PUTX_old [0 ] 0
|
||||
IS L2_Replacement [0 ] 0
|
||||
IS L2_Replacement_clean [0 ] 0
|
||||
IS Mem_Data [17038 ] 17038
|
||||
IS MEM_Inv [0 ] 0
|
||||
|
||||
IM L1_GET_INSTR [0 ] 0
|
||||
IM L1_GETS [0 ] 0
|
||||
IM L1_GETX [0 ] 0
|
||||
IM L1_PUTX [0 ] 0
|
||||
IM L1_PUTX_old [0 ] 0
|
||||
IM L2_Replacement [0 ] 0
|
||||
IM L2_Replacement_clean [0 ] 0
|
||||
IM Mem_Data [126192 ] 126192
|
||||
IM MEM_Inv [0 ] 0
|
||||
|
||||
SS_MB L1_GET_INSTR [0 ] 0
|
||||
SS_MB L1_GETS [174 ] 174
|
||||
SS_MB L1_GETX [0 ] 0
|
||||
SS_MB L1_UPGRADE [0 ] 0
|
||||
SS_MB L1_PUTX [0 ] 0
|
||||
SS_MB L1_PUTX_old [0 ] 0
|
||||
SS_MB L2_Replacement [0 ] 0
|
||||
SS_MB L2_Replacement_clean [0 ] 0
|
||||
SS_MB Unblock_Cancel [0 ] 0
|
||||
SS_MB Exclusive_Unblock [23874 ] 23874
|
||||
SS_MB MEM_Inv [0 ] 0
|
||||
|
||||
MT_MB L1_GET_INSTR [0 ] 0
|
||||
MT_MB L1_GETS [70 ] 70
|
||||
MT_MB L1_GETX [4 ] 4
|
||||
MT_MB L1_UPGRADE [0 ] 0
|
||||
MT_MB L1_PUTX [0 ] 0
|
||||
MT_MB L1_PUTX_old [0 ] 0
|
||||
MT_MB L2_Replacement [0 ] 0
|
||||
MT_MB L2_Replacement_clean [0 ] 0
|
||||
MT_MB Unblock_Cancel [0 ] 0
|
||||
MT_MB Exclusive_Unblock [1705121 ] 1705121
|
||||
MT_MB MEM_Inv [0 ] 0
|
||||
|
||||
M_MB L1_GET_INSTR [0 ] 0
|
||||
M_MB L1_GETS [0 ] 0
|
||||
M_MB L1_GETX [0 ] 0
|
||||
M_MB L1_UPGRADE [0 ] 0
|
||||
M_MB L1_PUTX [0 ] 0
|
||||
M_MB L1_PUTX_old [0 ] 0
|
||||
M_MB L2_Replacement [0 ] 0
|
||||
M_MB L2_Replacement_clean [0 ] 0
|
||||
M_MB Exclusive_Unblock [0 ] 0
|
||||
M_MB MEM_Inv [0 ] 0
|
||||
|
||||
MT_IIB L1_GET_INSTR [0 ] 0
|
||||
MT_IIB L1_GETS [0 ] 0
|
||||
MT_IIB L1_GETX [0 ] 0
|
||||
MT_IIB L1_UPGRADE [0 ] 0
|
||||
MT_IIB L1_PUTX [0 ] 0
|
||||
MT_IIB L1_PUTX_old [0 ] 0
|
||||
MT_IIB L2_Replacement [0 ] 0
|
||||
MT_IIB L2_Replacement_clean [0 ] 0
|
||||
MT_IIB WB_Data [24523 ] 24523
|
||||
MT_IIB WB_Data_clean [689 ] 689
|
||||
MT_IIB Unblock [12 ] 12
|
||||
MT_IIB MEM_Inv [0 ] 0
|
||||
|
||||
MT_IB L1_GET_INSTR [0 ] 0
|
||||
MT_IB L1_GETS [0 ] 0
|
||||
MT_IB L1_GETX [0 ] 0
|
||||
MT_IB L1_UPGRADE [0 ] 0
|
||||
MT_IB L1_PUTX [0 ] 0
|
||||
MT_IB L1_PUTX_old [0 ] 0
|
||||
MT_IB L2_Replacement [0 ] 0
|
||||
MT_IB L2_Replacement_clean [0 ] 0
|
||||
MT_IB WB_Data [11 ] 11
|
||||
MT_IB WB_Data_clean [1 ] 1
|
||||
MT_IB Unblock_Cancel [0 ] 0
|
||||
MT_IB MEM_Inv [0 ] 0
|
||||
|
||||
MT_SB L1_GET_INSTR [0 ] 0
|
||||
MT_SB L1_GETS [0 ] 0
|
||||
MT_SB L1_GETX [0 ] 0
|
||||
MT_SB L1_UPGRADE [0 ] 0
|
||||
MT_SB L1_PUTX [0 ] 0
|
||||
MT_SB L1_PUTX_old [0 ] 0
|
||||
MT_SB L2_Replacement [0 ] 0
|
||||
MT_SB L2_Replacement_clean [0 ] 0
|
||||
MT_SB Unblock [25212 ] 25212
|
||||
MT_SB MEM_Inv [0 ] 0
|
||||
|
||||
Memory controller: system.dir_cntrl0.memBuffer:
|
||||
memory_total_requests: 272944
|
||||
memory_reads: 177695
|
||||
memory_writes: 95249
|
||||
memory_refreshes: 4108449
|
||||
memory_total_request_delays: 25207
|
||||
memory_delays_per_request: 0.0923523
|
||||
memory_delays_in_input_queue: 7
|
||||
memory_delays_behind_head_of_bank_queue: 0
|
||||
memory_delays_stalled_at_head_of_bank_queue: 25200
|
||||
memory_stalls_for_bank_busy: 11193
|
||||
memory_stalls_for_random_busy: 0
|
||||
memory_stalls_for_anti_starvation: 0
|
||||
memory_stalls_for_arbitration: 2202
|
||||
memory_stalls_for_bus: 11804
|
||||
memory_stalls_for_tfaw: 0
|
||||
memory_stalls_for_read_write_turnaround: 0
|
||||
memory_stalls_for_read_read_turnaround: 1
|
||||
accesses_per_bank: 8796 9232 8713 8487 8759 8199 8936 8313 8486 8359 8337 9440 8301 8128 8185 7202 8172 8248 8224 8141 8420 8367 8241 8178 8468 8442 8634 9202 9127 8950 10053 8204
|
||||
|
||||
--- Directory ---
|
||||
- Event Counts -
|
||||
Fetch [177695 ] 177695
|
||||
Data [95249 ] 95249
|
||||
Memory_Data [177695 ] 177695
|
||||
Memory_Ack [95249 ] 95249
|
||||
DMA_READ [0 ] 0
|
||||
DMA_WRITE [0 ] 0
|
||||
CleanReplacement [16914 ] 16914
|
||||
|
||||
- Transitions -
|
||||
I Fetch [177695 ] 177695
|
||||
I DMA_READ [0 ] 0
|
||||
I DMA_WRITE [0 ] 0
|
||||
|
||||
ID Fetch [0 ] 0
|
||||
ID Data [0 ] 0
|
||||
ID Memory_Data [0 ] 0
|
||||
ID DMA_READ [0 ] 0
|
||||
ID DMA_WRITE [0 ] 0
|
||||
|
||||
ID_W Fetch [0 ] 0
|
||||
ID_W Data [0 ] 0
|
||||
ID_W Memory_Ack [0 ] 0
|
||||
ID_W DMA_READ [0 ] 0
|
||||
ID_W DMA_WRITE [0 ] 0
|
||||
|
||||
M Data [95249 ] 95249
|
||||
M DMA_READ [0 ] 0
|
||||
M DMA_WRITE [0 ] 0
|
||||
M CleanReplacement [16914 ] 16914
|
||||
|
||||
IM Fetch [0 ] 0
|
||||
IM Data [0 ] 0
|
||||
IM Memory_Data [177695 ] 177695
|
||||
IM DMA_READ [0 ] 0
|
||||
IM DMA_WRITE [0 ] 0
|
||||
|
||||
MI Fetch [0 ] 0
|
||||
MI Data [0 ] 0
|
||||
MI Memory_Ack [95249 ] 95249
|
||||
MI DMA_READ [0 ] 0
|
||||
MI DMA_WRITE [0 ] 0
|
||||
|
||||
M_DRD Data [0 ] 0
|
||||
M_DRD DMA_READ [0 ] 0
|
||||
M_DRD DMA_WRITE [0 ] 0
|
||||
|
||||
M_DRDI Fetch [0 ] 0
|
||||
M_DRDI Data [0 ] 0
|
||||
M_DRDI Memory_Ack [0 ] 0
|
||||
M_DRDI DMA_READ [0 ] 0
|
||||
M_DRDI DMA_WRITE [0 ] 0
|
||||
|
||||
M_DWR Data [0 ] 0
|
||||
M_DWR DMA_READ [0 ] 0
|
||||
M_DWR DMA_WRITE [0 ] 0
|
||||
|
||||
M_DWRI Fetch [0 ] 0
|
||||
M_DWRI Data [0 ] 0
|
||||
M_DWRI Memory_Ack [0 ] 0
|
||||
M_DWRI DMA_READ [0 ] 0
|
||||
M_DWRI DMA_WRITE [0 ] 0
|
||||
|
||||
--- DMA ---
|
||||
- Event Counts -
|
||||
ReadRequest [0 ] 0
|
||||
WriteRequest [0 ] 0
|
||||
Data [0 ] 0
|
||||
Ack [0 ] 0
|
||||
|
||||
- Transitions -
|
||||
READY ReadRequest [0 ] 0
|
||||
READY WriteRequest [0 ] 0
|
||||
|
||||
BUSY_RD Data [0 ] 0
|
||||
|
||||
BUSY_WR Ack [0 ] 0
|
||||
|
||||
@ -0,0 +1,11 @@
|
||||
warn: Sockets disabled, not accepting terminal connections
|
||||
warn: Reading current count from inactive timer.
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: Don't know what interrupt to clear for console.
|
||||
warn: instruction 'fxsave' unimplemented
|
||||
warn: instruction 'wbinvd' unimplemented
|
||||
warn: instruction 'wbinvd' unimplemented
|
||||
hack: Assuming logical destinations are 1 << id.
|
||||
warn: Tried to clear PCI interrupt 14
|
||||
warn: Unknown mouse command 0xe1.
|
||||
hack: be nice to actually delete the event here
|
||||
@ -0,0 +1,13 @@
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jun 4 2012 13:44:12
|
||||
gem5 started Jun 4 2012 17:11:29
|
||||
gem5 executing on zizzer
|
||||
command line: build/X86_MESI_CMP_directory/gem5.opt -d build/X86_MESI_CMP_directory/tests/opt/long/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory -re tests/run.py build/X86_MESI_CMP_directory/tests/opt/long/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory
|
||||
warning: add_child('terminal'): child 'terminal' already has parent
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9.smp
|
||||
0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 5304689685500 because m5_exit instruction encountered
|
||||
@ -0,0 +1,136 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 5.304690 # Number of seconds simulated
|
||||
sim_ticks 5304689685500 # Number of ticks simulated
|
||||
final_tick 5304689685500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 163049 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 333085 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 6301127704 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 481488 # Number of bytes of host memory used
|
||||
host_seconds 841.86 # Real time elapsed on the host
|
||||
sim_insts 137264752 # Number of instructions simulated
|
||||
sim_ops 280412254 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::pc.south_bridge.ide 35144 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu0.dtb.walker 126800 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu0.itb.walker 64416 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu0.inst 827772912 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu0.data 39626426 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu1.dtb.walker 100784 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu1.itb.walker 45696 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu1.inst 470347440 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu1.data 53905938 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 1392025556 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu0.inst 827772912 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu1.inst 470347440 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 1298120352 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::pc.south_bridge.ide 2991104 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::cpu0.itb.walker 16 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::cpu0.data 32173132 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::cpu1.data 35738580 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 70902832 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::pc.south_bridge.ide 809 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu0.dtb.walker 15850 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu0.itb.walker 8052 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu0.inst 103471614 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu0.data 6642662 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu1.dtb.walker 12598 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu1.itb.walker 5712 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu1.inst 58793430 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu1.data 9050935 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 178001662 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::pc.south_bridge.ide 46736 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::cpu0.itb.walker 2 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::cpu0.data 4837067 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::cpu1.data 4982709 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 9866514 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::pc.south_bridge.ide 6625 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu0.dtb.walker 23903 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu0.itb.walker 12143 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu0.inst 156045492 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu0.data 7470074 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu1.dtb.walker 18999 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu1.itb.walker 8614 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu1.inst 88666344 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu1.data 10161940 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 262414135 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu0.inst 156045492 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu1.inst 88666344 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 244711836 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::pc.south_bridge.ide 563860 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::cpu0.itb.walker 3 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::cpu0.data 6065036 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::cpu1.data 6737167 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 13366066 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::pc.south_bridge.ide 570485 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu0.dtb.walker 23903 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu0.itb.walker 12146 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu0.inst 156045492 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu0.data 13535110 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu1.dtb.walker 18999 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu1.itb.walker 8614 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu1.inst 88666344 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu1.data 16899107 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 275780201 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
||||
system.pc.south_bridge.ide.disks0.dma_read_bytes 32768 # Number of bytes transfered via DMA reads (not PRD).
|
||||
system.pc.south_bridge.ide.disks0.dma_read_txs 30 # Number of DMA read transactions (not PRD).
|
||||
system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes.
|
||||
system.pc.south_bridge.ide.disks0.dma_write_bytes 2987008 # Number of bytes transfered via DMA writes.
|
||||
system.pc.south_bridge.ide.disks0.dma_write_txs 813 # Number of DMA write transactions.
|
||||
system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
||||
system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
|
||||
system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD).
|
||||
system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
|
||||
system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
|
||||
system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
|
||||
system.cpu0.numCycles 10608177450 # number of cpu cycles simulated
|
||||
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu0.committedInsts 88690468 # Number of instructions committed
|
||||
system.cpu0.committedOps 187060545 # Number of ops (including micro ops) committed
|
||||
system.cpu0.num_int_alu_accesses 168469813 # Number of integer alu accesses
|
||||
system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses
|
||||
system.cpu0.num_func_calls 0 # number of times a function call or return occured
|
||||
system.cpu0.num_conditional_control_insts 17923925 # number of instructions that are conditional controls
|
||||
system.cpu0.num_int_insts 168469813 # number of integer instructions
|
||||
system.cpu0.num_fp_insts 0 # number of float instructions
|
||||
system.cpu0.num_int_register_reads 517963630 # number of times the integer registers were read
|
||||
system.cpu0.num_int_register_writes 280483339 # number of times the integer registers were written
|
||||
system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read
|
||||
system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written
|
||||
system.cpu0.num_mem_refs 19132508 # number of memory refs
|
||||
system.cpu0.num_load_insts 14284566 # Number of load instructions
|
||||
system.cpu0.num_store_insts 4847942 # Number of store instructions
|
||||
system.cpu0.num_idle_cycles 10086452980.871330 # Number of idle cycles
|
||||
system.cpu0.num_busy_cycles 521724469.128670 # Number of busy cycles
|
||||
system.cpu0.not_idle_fraction 0.049181 # Percentage of non-idle cycles
|
||||
system.cpu0.idle_fraction 0.950819 # Percentage of idle cycles
|
||||
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
|
||||
system.cpu0.kern.inst.quiesce 0 # number of quiesce instructions executed
|
||||
system.cpu1.numCycles 10609379371 # number of cpu cycles simulated
|
||||
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu1.committedInsts 48574284 # Number of instructions committed
|
||||
system.cpu1.committedOps 93351709 # Number of ops (including micro ops) committed
|
||||
system.cpu1.num_int_alu_accesses 89110416 # Number of integer alu accesses
|
||||
system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses
|
||||
system.cpu1.num_func_calls 0 # number of times a function call or return occured
|
||||
system.cpu1.num_conditional_control_insts 8197841 # number of instructions that are conditional controls
|
||||
system.cpu1.num_int_insts 89110416 # number of integer instructions
|
||||
system.cpu1.num_fp_insts 0 # number of float instructions
|
||||
system.cpu1.num_int_register_reads 273178604 # number of times the integer registers were read
|
||||
system.cpu1.num_int_register_writes 138760228 # number of times the integer registers were written
|
||||
system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read
|
||||
system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written
|
||||
system.cpu1.num_mem_refs 14426742 # number of memory refs
|
||||
system.cpu1.num_load_insts 9181010 # Number of load instructions
|
||||
system.cpu1.num_store_insts 5245732 # Number of store instructions
|
||||
system.cpu1.num_idle_cycles 10273661233.326063 # Number of idle cycles
|
||||
system.cpu1.num_busy_cycles 335718137.673937 # Number of busy cycles
|
||||
system.cpu1.not_idle_fraction 0.031644 # Percentage of non-idle cycles
|
||||
system.cpu1.idle_fraction 0.968356 # Percentage of idle cycles
|
||||
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
|
||||
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
@ -0,0 +1,136 @@
|
||||
Linux version 2.6.22.9 (gblack@fajita) (gcc version 4.1.2 (Gentoo 4.1.2 p1.1)) #12 SMP Fri Feb 27 22:10:33 PST 2009
|
||||
Command line: earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1
|
||||
BIOS-provided physical RAM map:
|
||||
BIOS-e820: 0000000000000000 - 0000000000100000 (reserved)
|
||||
BIOS-e820: 0000000000100000 - 0000000008000000 (usable)
|
||||
end_pfn_map = 32768
|
||||
kernel direct mapping tables up to 8000000 @ 100000-102000
|
||||
DMI 2.5 present.
|
||||
Zone PFN ranges:
|
||||
DMA 256 -> 4096
|
||||
DMA32 4096 -> 1048576
|
||||
Normal 1048576 -> 1048576
|
||||
early_node_map[1] active PFN ranges
|
||||
0: 256 -> 32768
|
||||
Intel MultiProcessor Specification v1.4
|
||||
MPTABLE: OEM ID: MPTABLE: Product ID: MPTABLE: APIC at: 0xFEE00000
|
||||
Processor #0 (Bootup-CPU)
|
||||
Processor #1
|
||||
I/O APIC #2 at 0xFEC00000.
|
||||
Setting APIC routing to flat
|
||||
Processors: 2
|
||||
Allocating PCI resources starting at 10000000 (gap: 8000000:f8000000)
|
||||
PERCPU: Allocating 34160 bytes of per cpu data
|
||||
Built 1 zonelists. Total pages: 30461
|
||||
Kernel command line: earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1
|
||||
Initializing CPU#0
|
||||
PID hash table entries: 512 (order: 9, 4096 bytes)
|
||||
Marking TSC unstable due to TSCs unsynchronized
|
||||
time.c: Detected 1999.999 MHz processor.
|
||||
Console: colour dummy device 80x25
|
||||
console handover: boot [earlyser0] -> real [ttyS0]
|
||||
Dentry cache hash table entries: 16384 (order: 5, 131072 bytes)
|
||||
Inode-cache hash table entries: 8192 (order: 4, 65536 bytes)
|
||||
Checking aperture...
|
||||
Memory: 121384k/131072k available (3699k kernel code, 8500k reserved, 1767k data, 248k init)
|
||||
Calibrating delay loop (skipped)... 3999.96 BogoMIPS preset
|
||||
Mount-cache hash table entries: 256
|
||||
CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)
|
||||
CPU: L2 Cache: 1024K (64 bytes/line)
|
||||
Freeing SMP alternatives: 34k freed
|
||||
Using local APIC timer interrupts.
|
||||
result 7812492
|
||||
Detected 7.812 MHz APIC timer.
|
||||
Booting processor 1/2 APIC 0x1
|
||||
Initializing CPU#1
|
||||
Calibrating delay loop (skipped)... 3999.96 BogoMIPS preset
|
||||
CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)
|
||||
CPU: L2 Cache: 1024K (64 bytes/line)
|
||||
Fake M5 x86_64 CPU stepping 01
|
||||
Brought up 2 CPUs
|
||||
migration_cost=11
|
||||
NET: Registered protocol family 16
|
||||
PCI: Using configuration type 1
|
||||
SCSI subsystem initialized
|
||||
usbcore: registered new interface driver usbfs
|
||||
usbcore: registered new interface driver hub
|
||||
usbcore: registered new device driver usb
|
||||
PCI: Probing PCI hardware
|
||||
PCI-GART: No AMD northbridge found.
|
||||
NET: Registered protocol family 2
|
||||
IP route cache hash table entries: 1024 (order: 1, 8192 bytes)
|
||||
TCP established hash table entries: 4096 (order: 4, 98304 bytes)
|
||||
TCP bind hash table entries: 4096 (order: 4, 65536 bytes)
|
||||
TCP: Hash tables configured (established 4096 bind 4096)
|
||||
TCP reno registered
|
||||
Total HugeTLB memory allocated, 0
|
||||
Installing knfsd (copyright (C) 1996 okir@monad.swb.de).
|
||||
io scheduler noop registered
|
||||
io scheduler deadline registered
|
||||
io scheduler cfq registered (default)
|
||||
Real Time Clock Driver v1.12ac
|
||||
Linux agpgart interface v0.102 (c) Dave Jones
|
||||
Serial: 8250/16550 driver $Revision: 1.90 $ 4 ports, IRQ sharing disabled
|
||||
serial8250: ttyS0 at I/O 0x3f8 (irq = 4) is a 8250
|
||||
floppy0: no floppy controllers found
|
||||
RAMDISK driver initialized: 16 RAM disks of 4096K size 1024 blocksize
|
||||
loop: module loaded
|
||||
Intel(R) PRO/1000 Network Driver - version 7.3.20-k2
|
||||
Copyright (c) 1999-2006 Intel Corporation.
|
||||
e100: Intel(R) PRO/100 Network Driver, 3.5.17-k4-NAPI
|
||||
e100: Copyright(c) 1999-2006 Intel Corporation
|
||||
forcedeth.c: Reverse Engineered nForce ethernet driver. Version 0.60.
|
||||
tun: Universal TUN/TAP device driver, 1.6
|
||||
tun: (C) 1999-2004 Max Krasnyansky <maxk@qualcomm.com>
|
||||
netconsole: not configured, aborting
|
||||
Uniform Multi-Platform E-IDE driver Revision: 7.00alpha2
|
||||
ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx
|
||||
PIIX4: IDE controller at PCI slot 0000:00:04.0
|
||||
PCI: Enabling device 0000:00:04.0 (0000 -> 0001)
|
||||
PIIX4: chipset revision 0
|
||||
PIIX4: not 100% native mode: will probe irqs later
|
||||
ide0: BM-DMA at 0x1000-0x1007, BIOS settings: hda:DMA, hdb:DMA
|
||||
ide1: BM-DMA at 0x1008-0x100f, BIOS settings: hdc:DMA, hdd:DMA
|
||||
hda: M5 IDE Disk, ATA DISK drive
|
||||
hdb: M5 IDE Disk, ATA DISK drive
|
||||
ide0 at 0x1f0-0x1f7,0x3f6 on irq 14
|
||||
hda: max request size: 128KiB
|
||||
hda: 1048320 sectors (536 MB), CHS=1040/16/63, UDMA(33)
|
||||
hda: hda1
|
||||
hdb: max request size: 128KiB
|
||||
hdb: 4177920 sectors (2139 MB), CHS=4144/16/63, UDMA(33)
|
||||
hdb: unknown partition table
|
||||
megaraid cmm: 2.20.2.7 (Release Date: Sun Jul 16 00:01:03 EST 2006)
|
||||
megaraid: 2.20.5.1 (Release Date: Thu Nov 16 15:32:35 EST 2006)
|
||||
megasas: 00.00.03.10-rc5 Thu May 17 10:09:32 PDT 2007
|
||||
Fusion MPT base driver 3.04.04
|
||||
Copyright (c) 1999-2007 LSI Logic Corporation
|
||||
Fusion MPT SPI Host driver 3.04.04
|
||||
Fusion MPT SAS Host driver 3.04.04
|
||||
ieee1394: raw1394: /dev/raw1394 device initialized
|
||||
USB Universal Host Controller Interface driver v3.0
|
||||
usbcore: registered new interface driver usblp
|
||||
drivers/usb/class/usblp.c: v0.13: USB Printer Device Class driver
|
||||
Initializing USB Mass Storage driver...
|
||||
usbcore: registered new interface driver usb-storage
|
||||
USB Mass Storage support registered.
|
||||
serio: i8042 KBD port at 0x60,0x64 irq 1
|
||||
serio: i8042 AUX port at 0x60,0x64 irq 12
|
||||
mice: PS/2 mouse device common for all mice
|
||||
input: AT Translated Set 2 keyboard as /class/input/input0
|
||||
device-mapper: ioctl: 4.11.0-ioctl (2006-10-12) initialised: dm-devel@redhat.com
|
||||
usbcore: registered new interface driver usbhid
|
||||
drivers/hid/usbhid/hid-core.c: v2.6:USB HID core driver
|
||||
oprofile: using timer interrupt.
|
||||
TCP cubic registered
|
||||
NET: Registered protocol family 1
|
||||
NET: Registered protocol family 10
|
||||
IPv6 over IPv4 tunneling driver
|
||||
NET: Registered protocol family 17
|
||||
input: PS/2 Generic Mouse as /class/input/input1
|
||||
EXT2-fs warning: mounting unchecked fs, running e2fsck is recommended
|
||||
VFS: Mounted root (ext2 filesystem).
|
||||
Freeing unused kernel memory: 248k freed
|
||||
|
||||
INIT: version 2.86 booting
|
||||
|
||||
Reference in New Issue
Block a user