Adding gem5 source to svn.
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1819 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
This commit is contained in:
friemel
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,5 @@
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warn: Sockets disabled, not accepting terminal connections
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||||
warn: Sockets disabled, not accepting gdb connections
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||||
warn: Prefetch instructions in Alpha do not do anything
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warn: Prefetch instructions in Alpha do not do anything
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||||
hack: be nice to actually delete the event here
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@ -0,0 +1,13 @@
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gem5 Simulator System. http://gem5.org
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||||
gem5 is copyrighted software; use the --copyright option for details.
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||||
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||||
gem5 compiled Jun 4 2012 11:50:11
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||||
gem5 started Jun 4 2012 14:31:55
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gem5 executing on zizzer
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command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual
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Global frequency set at 1000000000000 ticks per second
|
||||
info: kernel located at: /dist/m5/system/binaries/vmlinux
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||||
0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
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||||
info: Entering event queue @ 0. Starting simulation...
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info: Launching CPU 1 @ 107002000
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||||
Exiting @ tick 1899401490000 because m5_exit instruction encountered
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File diff suppressed because it is too large
Load Diff
@ -0,0 +1,113 @@
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M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
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||||
|
||||
Got Configuration 623
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||||
|
||||
memsize 8000000 pages 4000
|
||||
|
||||
First free page after ROM 0xFFFFFC0000018000
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||||
|
||||
HWRPB 0xFFFFFC0000018000 l1pt 0xFFFFFC0000040000 l2pt 0xFFFFFC0000042000 l3pt_rpb 0xFFFFFC0000044000 l3pt_kernel 0xFFFFFC0000048000 l2reserv 0xFFFFFC0000046000
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||||
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||||
kstart = 0xFFFFFC0000310000, kend = 0xFFFFFC0000855898, kentry = 0xFFFFFC0000310000, numCPUs = 0x2
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||||
|
||||
CPU Clock at 2000 MHz IntrClockFrequency=1024
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||||
|
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Booting with 2 processor(s)
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||||
KSP: 0x20043FE8 PTBR 0x20
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||||
|
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KSP: 0x20043FE8 PTBR 0x20
|
||||
|
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Console Callback at 0x0, fixup at 0x0, crb offset: 0x790
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|
||||
Memory cluster 0 [0 - 392]
|
||||
|
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Memory cluster 1 [392 - 15992]
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|
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Initalizing mdt_bitmap addr 0xFFFFFC0000038000 mem_pages 4000
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ConsoleDispatch at virt 100008D8 phys 188D8 val FFFFFC00000100A8
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Bootstraping CPU 1 with sp=0xFFFFFC0000076000
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unix_boot_mem ends at FFFFFC0000078000
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k_argc = 0
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|
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jumping to kernel at 0xFFFFFC0000310000, (PCBB 0xFFFFFC0000018180 pfn 1067)
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CallbackFixup 0 18000, t7=FFFFFC000070C000
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Entering slaveloop for cpu 1 my_rpb=FFFFFC0000018400
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Linux version 2.6.13 (hsul@zed.eecs.umich.edu) (gcc version 3.4.3) #1 SMP Sun Oct 8 19:52:07 EDT 2006
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||||
|
||||
Booting GENERIC on Tsunami variation DP264 using machine vector DP264 from SRM
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|
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Major Options: SMP LEGACY_START VERBOSE_MCHECK
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|
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Command line: root=/dev/hda1 console=ttyS0
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memcluster 0, usage 1, start 0, end 392
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|
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memcluster 1, usage 0, start 392, end 16384
|
||||
|
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freeing pages 1069:16384
|
||||
|
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reserving pages 1069:1070
|
||||
|
||||
4096K Bcache detected; load hit latency 32 cycles, load miss latency 115 cycles
|
||||
|
||||
SMP: 2 CPUs probed -- cpu_present_mask = 3
|
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|
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Built 1 zonelists
|
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|
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Kernel command line: root=/dev/hda1 console=ttyS0
|
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|
||||
PID hash table entries: 1024 (order: 10, 32768 bytes)
|
||||
|
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Using epoch = 1900
|
||||
|
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Console: colour dummy device 80x25
|
||||
|
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Dentry cache hash table entries: 32768 (order: 5, 262144 bytes)
|
||||
|
||||
Inode-cache hash table entries: 16384 (order: 4, 131072 bytes)
|
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|
||||
Memory: 118784k/131072k available (3314k kernel code, 8952k reserved, 983k data, 224k init)
|
||||
|
||||
Mount-cache hash table entries: 512
|
||||
|
||||
SMP starting up secondaries.
|
||||
|
||||
Slave CPU 1 console command START
|
||||
SlaveCmd: restart FFFFFC0000310020 FFFFFC0000310020 vptb FFFFFFFE00000000 my_rpb FFFFFC0000018400 my_rpb_phys 18400
|
||||
|
||||
Brought up 2 CPUs
|
||||
|
||||
SMP: Total of 2 processors activated (8000.15 BogoMIPS).
|
||||
|
||||
NET: Registered protocol family 16
|
||||
|
||||
EISA bus registered
|
||||
|
||||
pci: enabling save/restore of SRM state
|
||||
|
||||
SCSI subsystem initialized
|
||||
|
||||
srm_env: version 0.0.5 loaded successfully
|
||||
|
||||
Installing knfsd (copyright (C) 1996 okir@monad.swb.de).
|
||||
|
||||
Initializing Cryptographic API
|
||||
|
||||
rtc: Standard PC (1900) epoch (1900) detected
|
||||
|
||||
Real Time Clock Driver v1.12
|
||||
|
||||
Serial: 8250/16550 driver $Revision: 1.90 $ 1 ports, IRQ sharing disabled
|
||||
|
||||
ttyS0 at I/O 0x3f8 (irq = 4) is a 8250
|
||||
|
||||
io scheduler noop registered
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,5 @@
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warn: Sockets disabled, not accepting terminal connections
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: Prefetch instructions in Alpha do not do anything
|
||||
warn: Prefetch instructions in Alpha do not do anything
|
||||
hack: be nice to actually delete the event here
|
||||
@ -0,0 +1,12 @@
|
||||
gem5 Simulator System. http://gem5.org
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gem5 is copyrighted software; use the --copyright option for details.
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||||
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gem5 compiled Jun 4 2012 11:50:11
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gem5 started Jun 4 2012 14:16:04
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gem5 executing on zizzer
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command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3
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Global frequency set at 1000000000000 ticks per second
|
||||
info: kernel located at: /dist/m5/system/binaries/vmlinux
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0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
|
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info: Entering event queue @ 0. Starting simulation...
|
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Exiting @ tick 1858684403000 because m5_exit instruction encountered
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File diff suppressed because it is too large
Load Diff
@ -0,0 +1,108 @@
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||||
M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
|
||||
|
||||
Got Configuration 623
|
||||
|
||||
memsize 8000000 pages 4000
|
||||
|
||||
First free page after ROM 0xFFFFFC0000018000
|
||||
|
||||
HWRPB 0xFFFFFC0000018000 l1pt 0xFFFFFC0000040000 l2pt 0xFFFFFC0000042000 l3pt_rpb 0xFFFFFC0000044000 l3pt_kernel 0xFFFFFC0000048000 l2reserv 0xFFFFFC0000046000
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||||
|
||||
kstart = 0xFFFFFC0000310000, kend = 0xFFFFFC0000855898, kentry = 0xFFFFFC0000310000, numCPUs = 0x1
|
||||
|
||||
CPU Clock at 2000 MHz IntrClockFrequency=1024
|
||||
|
||||
Booting with 1 processor(s)
|
||||
|
||||
KSP: 0x20043FE8 PTBR 0x20
|
||||
|
||||
Console Callback at 0x0, fixup at 0x0, crb offset: 0x510
|
||||
|
||||
Memory cluster 0 [0 - 392]
|
||||
|
||||
Memory cluster 1 [392 - 15992]
|
||||
|
||||
Initalizing mdt_bitmap addr 0xFFFFFC0000038000 mem_pages 4000
|
||||
|
||||
ConsoleDispatch at virt 10000658 phys 18658 val FFFFFC00000100A8
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||||
|
||||
unix_boot_mem ends at FFFFFC0000076000
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||||
|
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k_argc = 0
|
||||
|
||||
jumping to kernel at 0xFFFFFC0000310000, (PCBB 0xFFFFFC0000018180 pfn 1067)
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||||
|
||||
CallbackFixup 0 18000, t7=FFFFFC000070C000
|
||||
|
||||
Linux version 2.6.13 (hsul@zed.eecs.umich.edu) (gcc version 3.4.3) #1 SMP Sun Oct 8 19:52:07 EDT 2006
|
||||
|
||||
Booting GENERIC on Tsunami variation DP264 using machine vector DP264 from SRM
|
||||
|
||||
Major Options: SMP LEGACY_START VERBOSE_MCHECK
|
||||
|
||||
Command line: root=/dev/hda1 console=ttyS0
|
||||
|
||||
memcluster 0, usage 1, start 0, end 392
|
||||
|
||||
memcluster 1, usage 0, start 392, end 16384
|
||||
|
||||
freeing pages 1069:16384
|
||||
|
||||
reserving pages 1069:1070
|
||||
|
||||
4096K Bcache detected; load hit latency 32 cycles, load miss latency 115 cycles
|
||||
|
||||
SMP: 1 CPUs probed -- cpu_present_mask = 1
|
||||
|
||||
Built 1 zonelists
|
||||
|
||||
Kernel command line: root=/dev/hda1 console=ttyS0
|
||||
|
||||
PID hash table entries: 1024 (order: 10, 32768 bytes)
|
||||
|
||||
Using epoch = 1900
|
||||
|
||||
Console: colour dummy device 80x25
|
||||
|
||||
Dentry cache hash table entries: 32768 (order: 5, 262144 bytes)
|
||||
|
||||
Inode-cache hash table entries: 16384 (order: 4, 131072 bytes)
|
||||
|
||||
Memory: 118784k/131072k available (3314k kernel code, 8952k reserved, 983k data, 224k init)
|
||||
|
||||
Mount-cache hash table entries: 512
|
||||
|
||||
SMP mode deactivated.
|
||||
|
||||
Brought up 1 CPUs
|
||||
|
||||
SMP: Total of 1 processors activated (4002.20 BogoMIPS).
|
||||
|
||||
NET: Registered protocol family 16
|
||||
|
||||
EISA bus registered
|
||||
|
||||
pci: enabling save/restore of SRM state
|
||||
|
||||
SCSI subsystem initialized
|
||||
|
||||
srm_env: version 0.0.5 loaded successfully
|
||||
|
||||
Installing knfsd (copyright (C) 1996 okir@monad.swb.de).
|
||||
|
||||
Initializing Cryptographic API
|
||||
|
||||
rtc: Standard PC (1900) epoch (1900) detected
|
||||
|
||||
Real Time Clock Driver v1.12
|
||||
|
||||
Serial: 8250/16550 driver $Revision: 1.90 $ 1 ports, IRQ sharing disabled
|
||||
|
||||
ttyS0 at I/O 0x3f8 (irq = 4) is a 8250
|
||||
|
||||
io scheduler noop registered
|
||||
|
||||
io scheduler anticipatory registered
|
||||
|
||||
io scheduler deadline registered
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,26 @@
|
||||
warn: Sockets disabled, not accepting vnc client connections
|
||||
warn: Sockets disabled, not accepting terminal connections
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: The clidr register always reports 0 caches.
|
||||
warn: clidr LoUIS field of 0b001 to match current ARM implementations.
|
||||
warn: The csselr register isn't implemented.
|
||||
warn: The ccsidr register isn't implemented and always reads as 0.
|
||||
warn: instruction 'mcr bpiallis' unimplemented
|
||||
warn: instruction 'mcr icialluis' unimplemented
|
||||
warn: instruction 'mcr dccimvac' unimplemented
|
||||
warn: instruction 'mcr dccmvau' unimplemented
|
||||
warn: instruction 'mcr icimvau' unimplemented
|
||||
warn: 5654850500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3704, checker: 0x3708
|
||||
warn: 5664849500: Instruction results do not match! (Values may not actually be integers) Inst: 0x36c4, checker: 0x36c8
|
||||
warn: 5704830500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3604, checker: 0x3608
|
||||
warn: 5721485500: Instruction results do not match! (Values may not actually be integers) Inst: 0x35c4, checker: 0x35c8
|
||||
warn: 6170779000: Instruction results do not match! (Values may not actually be integers) Inst: 0x34f0, checker: 0x34f8
|
||||
warn: LCD dual screen mode not supported
|
||||
warn: 53396857000: Instruction results do not match! (Values may not actually be integers) Inst: 0x19dc, checker: 0x1a04
|
||||
warn: 55147144000: Instruction results do not match! (Values may not actually be integers) Inst: 0x80d0, checker: 0xc71f6fc8
|
||||
warn: 55147144000: Instruction results do not match! (Values may not actually be integers) Inst: 0x71ef0, checker: 0x60000013
|
||||
warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
|
||||
warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
|
||||
warn: instruction 'mcr icialluis' unimplemented
|
||||
warn: instruction 'mcr bpiallis' unimplemented
|
||||
hack: be nice to actually delete the event here
|
||||
@ -0,0 +1,12 @@
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jun 4 2012 12:14:06
|
||||
gem5 started Jun 4 2012 18:58:44
|
||||
gem5 executing on zizzer
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
|
||||
info: Using bootloader at address 0x80000000
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 2501685689500 because m5_exit instruction encountered
|
||||
@ -0,0 +1,985 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 2.501686 # Number of seconds simulated
|
||||
sim_ticks 2501685689500 # Number of ticks simulated
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||||
final_tick 2501685689500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 49441 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 63837 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2075989543 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 387400 # Number of bytes of host memory used
|
||||
host_seconds 1205.06 # Real time elapsed on the host
|
||||
sim_insts 59579009 # Number of instructions simulated
|
||||
sim_ops 76926775 # Number of ops (including micro ops) simulated
|
||||
system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory
|
||||
system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory
|
||||
system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory
|
||||
system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory
|
||||
system.realview.nvmem.num_reads::cpu.inst 1 # Number of read requests responded to by this memory
|
||||
system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory
|
||||
system.realview.nvmem.bw_read::cpu.inst 26 # Total read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_read::total 26 # Total read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_inst_read::cpu.inst 26 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_inst_read::total 26 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_total::cpu.inst 26 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_total::total 26 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bytes_read::realview.clcd 118440096 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.dtb.walker 12032 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.itb.walker 896 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.inst 1119872 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 10085712 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 129658608 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 1119872 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 1119872 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 6569664 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 9585736 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::realview.clcd 14805012 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.dtb.walker 188 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.itb.walker 14 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.inst 17498 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 157623 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 14980335 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 102651 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 856669 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::realview.clcd 47344115 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.dtb.walker 4810 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.itb.walker 358 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 447647 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 4031566 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 51828496 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 447647 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 447647 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 2626095 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::cpu.data 1205616 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 3831711 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 2626095 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::realview.clcd 47344115 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.dtb.walker 4810 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.itb.walker 358 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 447647 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 5237182 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 55660207 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.l2c.replacements 119797 # number of replacements
|
||||
system.l2c.tagsinuse 26022.811009 # Cycle average of tags in use
|
||||
system.l2c.total_refs 1834134 # Total number of references to valid blocks.
|
||||
system.l2c.sampled_refs 150735 # Sample count of references to valid blocks.
|
||||
system.l2c.avg_refs 12.167937 # Average number of references to valid blocks.
|
||||
system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.l2c.occ_blocks::writebacks 14260.921168 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu.dtb.walker 79.122472 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu.itb.walker 1.014068 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu.inst 6176.146101 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu.data 5505.607200 # Average occupied blocks per requestor
|
||||
system.l2c.occ_percent::writebacks 0.217604 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu.dtb.walker 0.001207 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu.itb.walker 0.000015 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu.inst 0.094241 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu.data 0.084009 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::total 0.397077 # Average percentage of cache occupancy
|
||||
system.l2c.ReadReq_hits::cpu.dtb.walker 144170 # number of ReadReq hits
|
||||
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|
||||
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|
||||
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|
||||
system.l2c.ReadReq_hits::total 1536133 # number of ReadReq hits
|
||||
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|
||||
system.l2c.Writeback_hits::total 635023 # number of Writeback hits
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
system.l2c.demand_hits::cpu.inst 1001175 # number of demand (read+write) hits
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
system.l2c.overall_hits::cpu.inst 1001175 # number of overall hits
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
system.l2c.overall_misses::cpu.inst 17378 # number of overall misses
|
||||
system.l2c.overall_misses::cpu.data 159472 # number of overall misses
|
||||
system.l2c.overall_misses::total 177053 # number of overall misses
|
||||
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|
||||
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|
||||
system.l2c.ReadReq_miss_latency::cpu.inst 910079500 # number of ReadReq miss cycles
|
||||
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|
||||
system.l2c.ReadReq_miss_latency::total 1922778000 # number of ReadReq miss cycles
|
||||
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|
||||
system.l2c.UpgradeReq_miss_latency::total 996000 # number of UpgradeReq miss cycles
|
||||
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|
||||
system.l2c.SCUpgradeReq_miss_latency::total 104000 # number of SCUpgradeReq miss cycles
|
||||
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|
||||
system.l2c.ReadExReq_miss_latency::total 7365557000 # number of ReadExReq miss cycles
|
||||
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|
||||
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|
||||
system.l2c.demand_miss_latency::cpu.inst 910079500 # number of demand (read+write) miss cycles
|
||||
system.l2c.demand_miss_latency::cpu.data 8367653000 # number of demand (read+write) miss cycles
|
||||
system.l2c.demand_miss_latency::total 9288335000 # number of demand (read+write) miss cycles
|
||||
system.l2c.overall_miss_latency::cpu.dtb.walker 9850500 # number of overall miss cycles
|
||||
system.l2c.overall_miss_latency::cpu.itb.walker 752000 # number of overall miss cycles
|
||||
system.l2c.overall_miss_latency::cpu.inst 910079500 # number of overall miss cycles
|
||||
system.l2c.overall_miss_latency::cpu.data 8367653000 # number of overall miss cycles
|
||||
system.l2c.overall_miss_latency::total 9288335000 # number of overall miss cycles
|
||||
system.l2c.ReadReq_accesses::cpu.dtb.walker 144359 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::cpu.itb.walker 12506 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::cpu.inst 1018553 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::cpu.data 397476 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::total 1572894 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.Writeback_accesses::writebacks 635023 # number of Writeback accesses(hits+misses)
|
||||
system.l2c.Writeback_accesses::total 635023 # number of Writeback accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_accesses::cpu.data 3345 # number of UpgradeReq accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_accesses::total 3345 # number of UpgradeReq accesses(hits+misses)
|
||||
system.l2c.SCUpgradeReq_accesses::cpu.data 13 # number of SCUpgradeReq accesses(hits+misses)
|
||||
system.l2c.SCUpgradeReq_accesses::total 13 # number of SCUpgradeReq accesses(hits+misses)
|
||||
system.l2c.ReadExReq_accesses::cpu.data 246167 # number of ReadExReq accesses(hits+misses)
|
||||
system.l2c.ReadExReq_accesses::total 246167 # number of ReadExReq accesses(hits+misses)
|
||||
system.l2c.demand_accesses::cpu.dtb.walker 144359 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu.itb.walker 12506 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu.inst 1018553 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu.data 643643 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::total 1819061 # number of demand (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu.dtb.walker 144359 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu.itb.walker 12506 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu.inst 1018553 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu.data 643643 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::total 1819061 # number of overall (read+write) accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.001309 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.001119 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu.inst 0.017061 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu.data 0.048254 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::total 0.023372 # miss rate for ReadReq accesses
|
||||
system.l2c.UpgradeReq_miss_rate::cpu.data 0.986547 # miss rate for UpgradeReq accesses
|
||||
system.l2c.UpgradeReq_miss_rate::total 0.986547 # miss rate for UpgradeReq accesses
|
||||
system.l2c.SCUpgradeReq_miss_rate::cpu.data 0.384615 # miss rate for SCUpgradeReq accesses
|
||||
system.l2c.SCUpgradeReq_miss_rate::total 0.384615 # miss rate for SCUpgradeReq accesses
|
||||
system.l2c.ReadExReq_miss_rate::cpu.data 0.569906 # miss rate for ReadExReq accesses
|
||||
system.l2c.ReadExReq_miss_rate::total 0.569906 # miss rate for ReadExReq accesses
|
||||
system.l2c.demand_miss_rate::cpu.dtb.walker 0.001309 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu.itb.walker 0.001119 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu.inst 0.017061 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu.data 0.247765 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::total 0.097332 # miss rate for demand accesses
|
||||
system.l2c.overall_miss_rate::cpu.dtb.walker 0.001309 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu.itb.walker 0.001119 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu.inst 0.017061 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu.data 0.247765 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::total 0.097332 # miss rate for overall accesses
|
||||
system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52119.047619 # average ReadReq miss latency
|
||||
system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 53714.285714 # average ReadReq miss latency
|
||||
system.l2c.ReadReq_avg_miss_latency::cpu.inst 52369.634020 # average ReadReq miss latency
|
||||
system.l2c.ReadReq_avg_miss_latency::cpu.data 52246.923879 # average ReadReq miss latency
|
||||
system.l2c.ReadReq_avg_miss_latency::total 52304.833927 # average ReadReq miss latency
|
||||
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|
||||
system.l2c.UpgradeReq_avg_miss_latency::total 301.818182 # average UpgradeReq miss latency
|
||||
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|
||||
system.l2c.SCUpgradeReq_avg_miss_latency::total 20800 # average SCUpgradeReq miss latency
|
||||
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|
||||
system.l2c.ReadExReq_avg_miss_latency::total 52501.618054 # average ReadExReq miss latency
|
||||
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|
||||
system.l2c.demand_avg_miss_latency::cpu.itb.walker 53714.285714 # average overall miss latency
|
||||
system.l2c.demand_avg_miss_latency::cpu.inst 52369.634020 # average overall miss latency
|
||||
system.l2c.demand_avg_miss_latency::cpu.data 52470.985502 # average overall miss latency
|
||||
system.l2c.demand_avg_miss_latency::total 52460.760337 # average overall miss latency
|
||||
system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52119.047619 # average overall miss latency
|
||||
system.l2c.overall_avg_miss_latency::cpu.itb.walker 53714.285714 # average overall miss latency
|
||||
system.l2c.overall_avg_miss_latency::cpu.inst 52369.634020 # average overall miss latency
|
||||
system.l2c.overall_avg_miss_latency::cpu.data 52470.985502 # average overall miss latency
|
||||
system.l2c.overall_avg_miss_latency::total 52460.760337 # average overall miss latency
|
||||
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.l2c.fast_writes 0 # number of fast writes performed
|
||||
system.l2c.cache_copies 0 # number of cache copies performed
|
||||
system.l2c.writebacks::writebacks 102651 # number of writebacks
|
||||
system.l2c.writebacks::total 102651 # number of writebacks
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
system.l2c.demand_mshr_misses::cpu.inst 17364 # number of demand (read+write) MSHR misses
|
||||
system.l2c.demand_mshr_misses::cpu.data 159386 # number of demand (read+write) MSHR misses
|
||||
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|
||||
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|
||||
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|
||||
system.l2c.overall_mshr_misses::cpu.inst 17364 # number of overall MSHR misses
|
||||
system.l2c.overall_mshr_misses::cpu.data 159386 # number of overall MSHR misses
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
system.l2c.demand_mshr_miss_latency::total 7093247500 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency::cpu.dtb.walker 7532000 # number of overall MSHR miss cycles
|
||||
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|
||||
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|
||||
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|
||||
system.l2c.overall_mshr_miss_latency::total 7093247500 # number of overall MSHR miss cycles
|
||||
system.l2c.ReadReq_mshr_uncacheable_latency::cpu.inst 5427000 # number of ReadReq MSHR uncacheable cycles
|
||||
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|
||||
system.l2c.ReadReq_mshr_uncacheable_latency::total 131764013500 # number of ReadReq MSHR uncacheable cycles
|
||||
system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 32346095899 # number of WriteReq MSHR uncacheable cycles
|
||||
system.l2c.WriteReq_mshr_uncacheable_latency::total 32346095899 # number of WriteReq MSHR uncacheable cycles
|
||||
system.l2c.overall_mshr_uncacheable_latency::cpu.inst 5427000 # number of overall MSHR uncacheable cycles
|
||||
system.l2c.overall_mshr_uncacheable_latency::cpu.data 164104682399 # number of overall MSHR uncacheable cycles
|
||||
system.l2c.overall_mshr_uncacheable_latency::total 164110109399 # number of overall MSHR uncacheable cycles
|
||||
system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001302 # mshr miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001119 # mshr miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.017048 # mshr miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.048038 # mshr miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_mshr_miss_rate::total 0.023307 # mshr miss rate for ReadReq accesses
|
||||
system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.986547 # mshr miss rate for UpgradeReq accesses
|
||||
system.l2c.UpgradeReq_mshr_miss_rate::total 0.986547 # mshr miss rate for UpgradeReq accesses
|
||||
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu.data 0.384615 # mshr miss rate for SCUpgradeReq accesses
|
||||
system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.384615 # mshr miss rate for SCUpgradeReq accesses
|
||||
system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.569906 # mshr miss rate for ReadExReq accesses
|
||||
system.l2c.ReadExReq_mshr_miss_rate::total 0.569906 # mshr miss rate for ReadExReq accesses
|
||||
system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.001302 # mshr miss rate for demand accesses
|
||||
system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.001119 # mshr miss rate for demand accesses
|
||||
system.l2c.demand_mshr_miss_rate::cpu.inst 0.017048 # mshr miss rate for demand accesses
|
||||
system.l2c.demand_mshr_miss_rate::cpu.data 0.247631 # mshr miss rate for demand accesses
|
||||
system.l2c.demand_mshr_miss_rate::total 0.097277 # mshr miss rate for demand accesses
|
||||
system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.001302 # mshr miss rate for overall accesses
|
||||
system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.001119 # mshr miss rate for overall accesses
|
||||
system.l2c.overall_mshr_miss_rate::cpu.inst 0.017048 # mshr miss rate for overall accesses
|
||||
system.l2c.overall_mshr_miss_rate::cpu.data 0.247631 # mshr miss rate for overall accesses
|
||||
system.l2c.overall_mshr_miss_rate::total 0.097277 # mshr miss rate for overall accesses
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40063.829787 # average ReadReq mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 41714.285714 # average ReadReq mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40163.902327 # average ReadReq mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40096.522468 # average ReadReq mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::total 40128.887070 # average ReadReq mshr miss latency
|
||||
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40266.666667 # average UpgradeReq mshr miss latency
|
||||
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40266.666667 # average UpgradeReq mshr miss latency
|
||||
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 40000 # average SCUpgradeReq mshr miss latency
|
||||
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40000 # average SCUpgradeReq mshr miss latency
|
||||
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40074.434038 # average ReadExReq mshr miss latency
|
||||
system.l2c.ReadExReq_avg_mshr_miss_latency::total 40074.434038 # average ReadExReq mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40063.829787 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 41714.285714 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40163.902327 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu.data 40077.080170 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::total 40085.715335 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40063.829787 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 41714.285714 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40163.902327 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu.data 40077.080170 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::total 40085.715335 # average overall mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
|
||||
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
|
||||
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
||||
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
|
||||
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
||||
system.l2c.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
|
||||
system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
|
||||
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
||||
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
||||
system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
|
||||
system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
|
||||
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
|
||||
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
|
||||
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
|
||||
system.cpu.checker.dtb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.checker.dtb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.checker.dtb.read_hits 15048343 # DTB read hits
|
||||
system.cpu.checker.dtb.read_misses 7305 # DTB read misses
|
||||
system.cpu.checker.dtb.write_hits 11293933 # DTB write hits
|
||||
system.cpu.checker.dtb.write_misses 2191 # DTB write misses
|
||||
system.cpu.checker.dtb.flush_tlb 4 # Number of times complete TLB was flushed
|
||||
system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.checker.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.checker.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID
|
||||
system.cpu.checker.dtb.flush_entries 6410 # Number of entries that have been flushed from TLB
|
||||
system.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.checker.dtb.prefetch_faults 177 # Number of TLB faults due to prefetch
|
||||
system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.checker.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.checker.dtb.read_accesses 15055648 # DTB read accesses
|
||||
system.cpu.checker.dtb.write_accesses 11296124 # DTB write accesses
|
||||
system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses
|
||||
system.cpu.checker.dtb.hits 26342276 # DTB hits
|
||||
system.cpu.checker.dtb.misses 9496 # DTB misses
|
||||
system.cpu.checker.dtb.accesses 26351772 # DTB accesses
|
||||
system.cpu.checker.itb.inst_hits 60745631 # ITB inst hits
|
||||
system.cpu.checker.itb.inst_misses 4471 # ITB inst misses
|
||||
system.cpu.checker.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.checker.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.checker.itb.write_hits 0 # DTB write hits
|
||||
system.cpu.checker.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.checker.itb.flush_tlb 4 # Number of times complete TLB was flushed
|
||||
system.cpu.checker.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.checker.itb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.checker.itb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID
|
||||
system.cpu.checker.itb.flush_entries 4682 # Number of entries that have been flushed from TLB
|
||||
system.cpu.checker.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.checker.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu.checker.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.checker.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.checker.itb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.checker.itb.inst_accesses 60750102 # ITB inst accesses
|
||||
system.cpu.checker.itb.hits 60745631 # DTB hits
|
||||
system.cpu.checker.itb.misses 4471 # DTB misses
|
||||
system.cpu.checker.itb.accesses 60750102 # DTB accesses
|
||||
system.cpu.checker.numCycles 77205204 # number of cpu cycles simulated
|
||||
system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.dtb.read_hits 52103903 # DTB read hits
|
||||
system.cpu.dtb.read_misses 93079 # DTB read misses
|
||||
system.cpu.dtb.write_hits 11946241 # DTB write hits
|
||||
system.cpu.dtb.write_misses 25022 # DTB write misses
|
||||
system.cpu.dtb.flush_tlb 4 # Number of times complete TLB was flushed
|
||||
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID
|
||||
system.cpu.dtb.flush_entries 8141 # Number of entries that have been flushed from TLB
|
||||
system.cpu.dtb.align_faults 5562 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.dtb.prefetch_faults 707 # Number of TLB faults due to prefetch
|
||||
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.dtb.perms_faults 2799 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.dtb.read_accesses 52196982 # DTB read accesses
|
||||
system.cpu.dtb.write_accesses 11971263 # DTB write accesses
|
||||
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
|
||||
system.cpu.dtb.hits 64050144 # DTB hits
|
||||
system.cpu.dtb.misses 118101 # DTB misses
|
||||
system.cpu.dtb.accesses 64168245 # DTB accesses
|
||||
system.cpu.itb.inst_hits 13717584 # ITB inst hits
|
||||
system.cpu.itb.inst_misses 12272 # ITB inst misses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.write_hits 0 # DTB write hits
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.itb.flush_tlb 4 # Number of times complete TLB was flushed
|
||||
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.itb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.itb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID
|
||||
system.cpu.itb.flush_entries 5306 # Number of entries that have been flushed from TLB
|
||||
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.itb.perms_faults 6863 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.itb.inst_accesses 13729856 # ITB inst accesses
|
||||
system.cpu.itb.hits 13717584 # DTB hits
|
||||
system.cpu.itb.misses 12272 # DTB misses
|
||||
system.cpu.itb.accesses 13729856 # DTB accesses
|
||||
system.cpu.numCycles 411352060 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.BPredUnit.lookups 15654738 # Number of BP lookups
|
||||
system.cpu.BPredUnit.condPredicted 12362397 # Number of conditional branches predicted
|
||||
system.cpu.BPredUnit.condIncorrect 932839 # Number of conditional branches incorrect
|
||||
system.cpu.BPredUnit.BTBLookups 10530768 # Number of BTB lookups
|
||||
system.cpu.BPredUnit.BTBHits 8288874 # Number of BTB hits
|
||||
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu.BPredUnit.usedRAS 1329017 # Number of times the RAS was used to get a target.
|
||||
system.cpu.BPredUnit.RASInCorrect 195537 # Number of incorrect RAS predictions.
|
||||
system.cpu.fetch.icacheStallCycles 33116930 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.Insts 103031700 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.Branches 15654738 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.predictedBranches 9617891 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.Cycles 22620194 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.SquashCycles 6706106 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.TlbCycles 163882 # Number of cycles fetch has spent waiting for tlb
|
||||
system.cpu.fetch.BlockedCycles 89861042 # Number of cycles fetch has spent blocked
|
||||
system.cpu.fetch.MiscStallCycles 2823 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
||||
system.cpu.fetch.PendingTrapStallCycles 147160 # Number of stall cycles due to pending traps
|
||||
system.cpu.fetch.PendingQuiesceStallCycles 218224 # Number of stall cycles due to pending quiesce instructions
|
||||
system.cpu.fetch.IcacheWaitRetryStallCycles 462 # Number of stall cycles due to full MSHR
|
||||
system.cpu.fetch.CacheLines 13709942 # Number of cache lines fetched
|
||||
system.cpu.fetch.IcacheSquashes 998560 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.ItlbSquashes 6868 # Number of outstanding ITLB misses that were squashed
|
||||
system.cpu.fetch.rateDist::samples 150746244 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 0.848897 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 2.234280 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 128142810 85.01% 85.01% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 1478319 0.98% 85.99% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 1855018 1.23% 87.22% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 2695901 1.79% 89.01% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 1893540 1.26% 90.26% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 1191101 0.79% 91.05% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 2951659 1.96% 93.01% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 850848 0.56% 93.57% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 9687048 6.43% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::total 150746244 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.branchRate 0.038057 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.rate 0.250471 # Number of inst fetches per cycle
|
||||
system.cpu.decode.IdleCycles 35228906 # Number of cycles decode is idle
|
||||
system.cpu.decode.BlockedCycles 89710063 # Number of cycles decode is blocked
|
||||
system.cpu.decode.RunCycles 20347806 # Number of cycles decode is running
|
||||
system.cpu.decode.UnblockCycles 1026685 # Number of cycles decode is unblocking
|
||||
system.cpu.decode.SquashCycles 4432784 # Number of cycles decode is squashing
|
||||
system.cpu.decode.BranchResolved 2275641 # Number of times decode resolved a branch
|
||||
system.cpu.decode.BranchMispred 186729 # Number of times decode detected a branch misprediction
|
||||
system.cpu.decode.DecodedInsts 120042439 # Number of instructions handled by decode
|
||||
system.cpu.decode.SquashedInsts 604390 # Number of squashed instructions handled by decode
|
||||
system.cpu.rename.SquashCycles 4432784 # Number of cycles rename is squashing
|
||||
system.cpu.rename.IdleCycles 37305734 # Number of cycles rename is idle
|
||||
system.cpu.rename.BlockCycles 37165628 # Number of cycles rename is blocking
|
||||
system.cpu.rename.serializeStallCycles 46502465 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RunCycles 19251695 # Number of cycles rename is running
|
||||
system.cpu.rename.UnblockCycles 6087938 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RenamedInsts 112539597 # Number of instructions processed by rename
|
||||
system.cpu.rename.ROBFullEvents 3873 # Number of times rename has blocked due to ROB full
|
||||
system.cpu.rename.IQFullEvents 1013212 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.LSQFullEvents 4109157 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.FullRegisterEvents 45575 # Number of times there has been no free registers
|
||||
system.cpu.rename.RenamedOperands 117156815 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RenameLookups 517555842 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.int_rename_lookups 517460811 # Number of integer rename lookups
|
||||
system.cpu.rename.fp_rename_lookups 95031 # Number of floating rename lookups
|
||||
system.cpu.rename.CommittedMaps 77687687 # Number of HB maps that are committed
|
||||
system.cpu.rename.UndoneMaps 39469127 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.serializingInsts 939790 # count of serializing insts renamed
|
||||
system.cpu.rename.tempSerializingInsts 835958 # count of temporary serializing insts renamed
|
||||
system.cpu.rename.skidInsts 12443241 # count of insts added to the skid buffer
|
||||
system.cpu.memDep0.insertedLoads 21685850 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 14072237 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.conflictingLoads 1938675 # Number of conflicting loads.
|
||||
system.cpu.memDep0.conflictingStores 2482763 # Number of conflicting stores.
|
||||
system.cpu.iq.iqInstsAdded 102391550 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqNonSpecInstsAdded 1619583 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqInstsIssued 126350622 # Number of instructions issued
|
||||
system.cpu.iq.iqSquashedInstsIssued 234593 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedInstsExamined 26254924 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedOperandsExamined 71509700 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 332277 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.issued_per_cycle::samples 150746244 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::mean 0.838168 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::stdev 1.542455 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::0 105470655 69.97% 69.97% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::1 14086510 9.34% 79.31% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::2 7371222 4.89% 84.20% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::3 5923402 3.93% 88.13% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::4 12762751 8.47% 96.60% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::5 2810704 1.86% 98.46% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::6 1735902 1.15% 99.61% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::7 449258 0.30% 99.91% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::8 135840 0.09% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::total 150746244 # Number of insts issued each cycle
|
||||
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntAlu 61043 0.69% 0.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntMult 4 0.00% 0.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntDiv 0 0.00% 0.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatMult 0 0.00% 0.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdMult 0 0.00% 0.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdShift 0 0.00% 0.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::MemRead 8421186 94.66% 95.34% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::MemWrite 414230 4.66% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.FU_type_0::No_OpClass 106530 0.08% 0.08% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntAlu 59762768 47.30% 47.38% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntMult 95812 0.08% 47.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdMisc 38 0.00% 47.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdShift 45 0.00% 47.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdShiftAcc 9 0.00% 47.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMisc 2279 0.00% 47.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMultAcc 9 0.00% 47.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::MemRead 53776494 42.56% 90.02% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::MemWrite 12606638 9.98% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::total 126350622 # Type of FU issued
|
||||
system.cpu.iq.rate 0.307159 # Inst issue rate
|
||||
system.cpu.iq.fu_busy_cnt 8896463 # FU busy when requested
|
||||
system.cpu.iq.fu_busy_rate 0.070411 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.int_inst_queue_reads 412671946 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_writes 130285978 # Number of integer instruction queue writes
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 87040433 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.fp_inst_queue_reads 24078 # Number of floating instruction queue reads
|
||||
system.cpu.iq.fp_inst_queue_writes 13182 # Number of floating instruction queue writes
|
||||
system.cpu.iq.fp_inst_queue_wakeup_accesses 10434 # Number of floating instruction queue wakeup accesses
|
||||
system.cpu.iq.int_alu_accesses 135127716 # Number of integer alu accesses
|
||||
system.cpu.iq.fp_alu_accesses 12839 # Number of floating point alu accesses
|
||||
system.cpu.iew.lsq.thread0.forwLoads 636069 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread0.squashedLoads 5970496 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread0.ignoredResponses 11101 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread0.memOrderViolation 34253 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread0.squashedStores 2273952 # Number of stores squashed
|
||||
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
||||
system.cpu.iew.lsq.thread0.rescheduledLoads 34114355 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread0.cacheBlocked 1152098 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||||
system.cpu.iew.iewSquashCycles 4432784 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewBlockCycles 28604721 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewUnblockCycles 436722 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.iewDispatchedInsts 104273041 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewDispSquashedInsts 335924 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispLoadInsts 21685850 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispStoreInsts 14072237 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 992808 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewIQFullEvents 95700 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.iewLSQFullEvents 11591 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.memOrderViolationEvents 34253 # Number of memory order violations
|
||||
system.cpu.iew.predictedTakenIncorrect 552378 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.iew.predictedNotTakenIncorrect 346914 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.branchMispredicts 899292 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewExecutedInsts 123108789 # Number of executed instructions
|
||||
system.cpu.iew.iewExecLoadInsts 52799372 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 3241833 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
||||
system.cpu.iew.exec_nop 261908 # number of nop insts executed
|
||||
system.cpu.iew.exec_refs 65255060 # number of memory reference insts executed
|
||||
system.cpu.iew.exec_branches 11601340 # Number of branches executed
|
||||
system.cpu.iew.exec_stores 12455688 # Number of stores executed
|
||||
system.cpu.iew.exec_rate 0.299278 # Inst execution rate
|
||||
system.cpu.iew.wb_sent 121555618 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.wb_count 87050867 # cumulative count of insts written-back
|
||||
system.cpu.iew.wb_producers 47546734 # num instructions producing a value
|
||||
system.cpu.iew.wb_consumers 88572059 # num instructions consuming a value
|
||||
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
||||
system.cpu.iew.wb_rate 0.211621 # insts written-back per cycle
|
||||
system.cpu.iew.wb_fanout 0.536814 # average fanout of values written-back
|
||||
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||
system.cpu.commit.commitCommittedInsts 59729390 # The number of committed instructions
|
||||
system.cpu.commit.commitCommittedOps 77077156 # The number of committed instructions
|
||||
system.cpu.commit.commitSquashedInsts 27015439 # The number of squashed insts skipped by commit
|
||||
system.cpu.commit.commitNonSpecStalls 1287306 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu.commit.branchMispredicts 793496 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.committed_per_cycle::samples 146395876 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::mean 0.526498 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::stdev 1.504904 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::0 118626341 81.03% 81.03% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::1 13714527 9.37% 90.40% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::2 3991808 2.73% 93.13% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::3 2249419 1.54% 94.66% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::4 1746576 1.19% 95.86% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::5 1042045 0.71% 96.57% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::6 1550885 1.06% 97.63% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::7 665283 0.45% 98.08% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::8 2808992 1.92% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::total 146395876 # Number of insts commited each cycle
|
||||
system.cpu.commit.committedInsts 59729390 # Number of instructions committed
|
||||
system.cpu.commit.committedOps 77077156 # Number of ops (including micro ops) committed
|
||||
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
||||
system.cpu.commit.refs 27513639 # Number of memory references committed
|
||||
system.cpu.commit.loads 15715354 # Number of loads committed
|
||||
system.cpu.commit.membars 413068 # Number of memory barriers committed
|
||||
system.cpu.commit.branches 9904424 # Number of branches committed
|
||||
system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions.
|
||||
system.cpu.commit.int_insts 68617835 # Number of committed integer instructions.
|
||||
system.cpu.commit.function_calls 995976 # Number of function calls committed.
|
||||
system.cpu.commit.bw_lim_events 2808992 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
||||
system.cpu.rob.rob_reads 245922084 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 212744706 # The number of ROB writes
|
||||
system.cpu.timesIdled 1895448 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 260605816 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.quiesceCycles 4591931267 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
|
||||
system.cpu.committedInsts 59579009 # Number of Instructions Simulated
|
||||
system.cpu.committedOps 76926775 # Number of Ops (including micro ops) Simulated
|
||||
system.cpu.committedInsts_total 59579009 # Number of Instructions Simulated
|
||||
system.cpu.cpi 6.904312 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 6.904312 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 0.144837 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.144837 # IPC: Total IPC of All Threads
|
||||
system.cpu.int_regfile_reads 558200785 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 89400907 # number of integer regfile writes
|
||||
system.cpu.fp_regfile_reads 8900 # number of floating regfile reads
|
||||
system.cpu.fp_regfile_writes 2982 # number of floating regfile writes
|
||||
system.cpu.misc_regfile_reads 135543435 # number of misc regfile reads
|
||||
system.cpu.misc_regfile_writes 912729 # number of misc regfile writes
|
||||
system.cpu.icache.replacements 1019271 # number of replacements
|
||||
system.cpu.icache.tagsinuse 511.444719 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 12598089 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 1019783 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 12.353696 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 6290137000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 511.444719 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.998915 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.998915 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 12598089 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 12598089 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 12598089 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 12598089 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 12598089 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 12598089 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 1111711 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 1111711 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 1111711 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 1111711 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 1111711 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 1111711 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 16369836984 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 16369836984 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 16369836984 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 16369836984 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 16369836984 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 16369836984 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 13709800 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 13709800 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 13709800 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 13709800 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 13709800 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 13709800 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.081089 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.081089 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.081089 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.081089 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.081089 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.081089 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14724.903310 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 14724.903310 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 14724.903310 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 14724.903310 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 14724.903310 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 14724.903310 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 2973484 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 393 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs 7566.117048 # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks::writebacks 60091 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 60091 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 91891 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::total 91891 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::cpu.inst 91891 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::total 91891 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::cpu.inst 91891 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::total 91891 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1019820 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 1019820 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 1019820 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 1019820 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 1019820 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 1019820 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12187570984 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 12187570984 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12187570984 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 12187570984 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12187570984 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 12187570984 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 7292000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 7292000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 7292000 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency::total 7292000 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.074386 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.074386 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.074386 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.074386 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.074386 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.074386 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11950.707952 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11950.707952 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11950.707952 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 11950.707952 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11950.707952 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 11950.707952 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 645895 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 511.991565 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 22075422 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 646407 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 34.150964 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 49188000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 511.991565 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.999984 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.999984 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 14216478 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 14216478 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 7283636 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 7283636 # number of WriteReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::cpu.data 286092 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::total 286092 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::cpu.data 285655 # number of StoreCondReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::total 285655 # number of StoreCondReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 21500114 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 21500114 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 21500114 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 21500114 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 747655 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 747655 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 2966865 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 2966865 # number of WriteReq misses
|
||||
system.cpu.dcache.LoadLockedReq_misses::cpu.data 13747 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.LoadLockedReq_misses::total 13747 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.StoreCondReq_misses::cpu.data 13 # number of StoreCondReq misses
|
||||
system.cpu.dcache.StoreCondReq_misses::total 13 # number of StoreCondReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 3714520 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 3714520 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 3714520 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 3714520 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 11237363500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 11237363500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 110154178240 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 110154178240 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 224042000 # number of LoadLockedReq miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_miss_latency::total 224042000 # number of LoadLockedReq miss cycles
|
||||
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 394000 # number of StoreCondReq miss cycles
|
||||
system.cpu.dcache.StoreCondReq_miss_latency::total 394000 # number of StoreCondReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 121391541740 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 121391541740 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 121391541740 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 121391541740 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 14964133 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 14964133 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 10250501 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 10250501 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 299839 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::total 299839 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::cpu.data 285668 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::total 285668 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 25214634 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 25214634 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 25214634 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 25214634 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.049963 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.049963 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289436 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.289436 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045848 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045848 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000046 # miss rate for StoreCondReq accesses
|
||||
system.cpu.dcache.StoreCondReq_miss_rate::total 0.000046 # miss rate for StoreCondReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.147316 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.147316 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.147316 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.147316 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15030.145589 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 15030.145589 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37128.139717 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 37128.139717 # average WriteReq miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16297.519459 # average LoadLockedReq miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16297.519459 # average LoadLockedReq miss latency
|
||||
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 30307.692308 # average StoreCondReq miss latency
|
||||
system.cpu.dcache.StoreCondReq_avg_miss_latency::total 30307.692308 # average StoreCondReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 32680.276789 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 32680.276789 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 32680.276789 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 32680.276789 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 17091437 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 7607500 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 3024 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 268 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 5651.930225 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets 28386.194030 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 574932 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 574932 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 359686 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 359686 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2717440 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 2717440 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1386 # number of LoadLockedReq MSHR hits
|
||||
system.cpu.dcache.LoadLockedReq_mshr_hits::total 1386 # number of LoadLockedReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 3077126 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 3077126 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 3077126 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 3077126 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 387969 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 387969 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249425 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 249425 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12361 # number of LoadLockedReq MSHR misses
|
||||
system.cpu.dcache.LoadLockedReq_mshr_misses::total 12361 # number of LoadLockedReq MSHR misses
|
||||
system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 13 # number of StoreCondReq MSHR misses
|
||||
system.cpu.dcache.StoreCondReq_mshr_misses::total 13 # number of StoreCondReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 637394 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 637394 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 637394 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 637394 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5287973500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 5287973500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8908906437 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 8908906437 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 165672500 # number of LoadLockedReq MSHR miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 165672500 # number of LoadLockedReq MSHR miss cycles
|
||||
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 351500 # number of StoreCondReq MSHR miss cycles
|
||||
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 351500 # number of StoreCondReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14196879937 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 14196879937 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14196879937 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 14196879937 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 147151877500 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 147151877500 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 42255772015 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 42255772015 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 189407649515 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency::total 189407649515 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.025927 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.025927 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024333 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024333 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.041225 # mshr miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.041225 # mshr miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000046 # mshr miss rate for StoreCondReq accesses
|
||||
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000046 # mshr miss rate for StoreCondReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025279 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.025279 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025279 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.025279 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13629.886666 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13629.886666 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35717.776634 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35717.776634 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13402.839576 # average LoadLockedReq mshr miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13402.839576 # average LoadLockedReq mshr miss latency
|
||||
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 27038.461538 # average StoreCondReq mshr miss latency
|
||||
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 27038.461538 # average StoreCondReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22273.319073 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 22273.319073 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22273.319073 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 22273.319073 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.iocache.replacements 0 # number of replacements
|
||||
system.iocache.tagsinuse 0 # Cycle average of tags in use
|
||||
system.iocache.total_refs 0 # Total number of references to valid blocks.
|
||||
system.iocache.sampled_refs 0 # Sample count of references to valid blocks.
|
||||
system.iocache.avg_refs nan # Average number of references to valid blocks.
|
||||
system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.iocache.fast_writes 0 # number of fast writes performed
|
||||
system.iocache.cache_copies 0 # number of cache copies performed
|
||||
system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1296131413558 # number of ReadReq MSHR uncacheable cycles
|
||||
system.iocache.ReadReq_mshr_uncacheable_latency::total 1296131413558 # number of ReadReq MSHR uncacheable cycles
|
||||
system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1296131413558 # number of overall MSHR uncacheable cycles
|
||||
system.iocache.overall_mshr_uncacheable_latency::total 1296131413558 # number of overall MSHR uncacheable cycles
|
||||
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
|
||||
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
||||
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
|
||||
system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
||||
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
||||
system.cpu.kern.inst.quiesce 88053 # number of quiesce instructions executed
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,18 @@
|
||||
warn: Sockets disabled, not accepting vnc client connections
|
||||
warn: Sockets disabled, not accepting terminal connections
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: The clidr register always reports 0 caches.
|
||||
warn: clidr LoUIS field of 0b001 to match current ARM implementations.
|
||||
warn: The csselr register isn't implemented.
|
||||
warn: The ccsidr register isn't implemented and always reads as 0.
|
||||
warn: instruction 'mcr bpiallis' unimplemented
|
||||
warn: instruction 'mcr icialluis' unimplemented
|
||||
warn: instruction 'mcr dccimvac' unimplemented
|
||||
warn: instruction 'mcr dccmvau' unimplemented
|
||||
warn: instruction 'mcr icimvau' unimplemented
|
||||
warn: instruction 'mcr bpiallis' unimplemented
|
||||
warn: LCD dual screen mode not supported
|
||||
warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
|
||||
warn: instruction 'mcr icialluis' unimplemented
|
||||
warn: instruction 'mcr icialluis' unimplemented
|
||||
hack: be nice to actually delete the event here
|
||||
@ -0,0 +1,12 @@
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jun 4 2012 12:14:06
|
||||
gem5 started Jun 4 2012 18:58:50
|
||||
gem5 executing on zizzer
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
|
||||
info: Using bootloader at address 0x80000000
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 2570833934500 because m5_exit instruction encountered
|
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1 @@
|
||||
build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual FAILED!
|
||||
Binary file not shown.
File diff suppressed because it is too large
Load Diff
17
simulators/gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr
Executable file
17
simulators/gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr
Executable file
@ -0,0 +1,17 @@
|
||||
warn: Sockets disabled, not accepting vnc client connections
|
||||
warn: Sockets disabled, not accepting terminal connections
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: The clidr register always reports 0 caches.
|
||||
warn: clidr LoUIS field of 0b001 to match current ARM implementations.
|
||||
warn: The csselr register isn't implemented.
|
||||
warn: The ccsidr register isn't implemented and always reads as 0.
|
||||
warn: instruction 'mcr bpiallis' unimplemented
|
||||
warn: instruction 'mcr icialluis' unimplemented
|
||||
warn: instruction 'mcr dccimvac' unimplemented
|
||||
warn: instruction 'mcr dccmvau' unimplemented
|
||||
warn: instruction 'mcr icimvau' unimplemented
|
||||
warn: LCD dual screen mode not supported
|
||||
warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
|
||||
warn: instruction 'mcr icialluis' unimplemented
|
||||
warn: instruction 'mcr bpiallis' unimplemented
|
||||
hack: be nice to actually delete the event here
|
||||
12
simulators/gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout
Executable file
12
simulators/gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout
Executable file
@ -0,0 +1,12 @@
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jun 4 2012 12:14:06
|
||||
gem5 started Jun 4 2012 18:55:16
|
||||
gem5 executing on zizzer
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
|
||||
info: Using bootloader at address 0x80000000
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 2501685689500 because m5_exit instruction encountered
|
||||
@ -0,0 +1,940 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 2.501686 # Number of seconds simulated
|
||||
sim_ticks 2501685689500 # Number of ticks simulated
|
||||
final_tick 2501685689500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 57858 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 74704 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2429415836 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 387132 # Number of bytes of host memory used
|
||||
host_seconds 1029.75 # Real time elapsed on the host
|
||||
sim_insts 59579009 # Number of instructions simulated
|
||||
sim_ops 76926775 # Number of ops (including micro ops) simulated
|
||||
system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory
|
||||
system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory
|
||||
system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory
|
||||
system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory
|
||||
system.realview.nvmem.num_reads::cpu.inst 1 # Number of read requests responded to by this memory
|
||||
system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory
|
||||
system.realview.nvmem.bw_read::cpu.inst 26 # Total read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_read::total 26 # Total read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_inst_read::cpu.inst 26 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_inst_read::total 26 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_total::cpu.inst 26 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_total::total 26 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bytes_read::realview.clcd 118440096 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.dtb.walker 12032 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.itb.walker 896 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.inst 1119872 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 10085712 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 129658608 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 1119872 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 1119872 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 6569664 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 9585736 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::realview.clcd 14805012 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.dtb.walker 188 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.itb.walker 14 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.inst 17498 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 157623 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 14980335 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 102651 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 856669 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::realview.clcd 47344115 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.dtb.walker 4810 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.itb.walker 358 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 447647 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 4031566 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 51828496 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 447647 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 447647 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 2626095 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::cpu.data 1205616 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 3831711 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 2626095 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::realview.clcd 47344115 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.dtb.walker 4810 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.itb.walker 358 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 447647 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 5237182 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 55660207 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.l2c.replacements 119797 # number of replacements
|
||||
system.l2c.tagsinuse 26022.811009 # Cycle average of tags in use
|
||||
system.l2c.total_refs 1834134 # Total number of references to valid blocks.
|
||||
system.l2c.sampled_refs 150735 # Sample count of references to valid blocks.
|
||||
system.l2c.avg_refs 12.167937 # Average number of references to valid blocks.
|
||||
system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.l2c.occ_blocks::writebacks 14260.921168 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu.dtb.walker 79.122472 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu.itb.walker 1.014068 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu.inst 6176.146101 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu.data 5505.607200 # Average occupied blocks per requestor
|
||||
system.l2c.occ_percent::writebacks 0.217604 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu.dtb.walker 0.001207 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu.itb.walker 0.000015 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu.inst 0.094241 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu.data 0.084009 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::total 0.397077 # Average percentage of cache occupancy
|
||||
system.l2c.ReadReq_hits::cpu.dtb.walker 144170 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu.itb.walker 12492 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu.inst 1001175 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu.data 378296 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::total 1536133 # number of ReadReq hits
|
||||
system.l2c.Writeback_hits::writebacks 635023 # number of Writeback hits
|
||||
system.l2c.Writeback_hits::total 635023 # number of Writeback hits
|
||||
system.l2c.UpgradeReq_hits::cpu.data 45 # number of UpgradeReq hits
|
||||
system.l2c.UpgradeReq_hits::total 45 # number of UpgradeReq hits
|
||||
system.l2c.SCUpgradeReq_hits::cpu.data 8 # number of SCUpgradeReq hits
|
||||
system.l2c.SCUpgradeReq_hits::total 8 # number of SCUpgradeReq hits
|
||||
system.l2c.ReadExReq_hits::cpu.data 105875 # number of ReadExReq hits
|
||||
system.l2c.ReadExReq_hits::total 105875 # number of ReadExReq hits
|
||||
system.l2c.demand_hits::cpu.dtb.walker 144170 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu.itb.walker 12492 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu.inst 1001175 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu.data 484171 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::total 1642008 # number of demand (read+write) hits
|
||||
system.l2c.overall_hits::cpu.dtb.walker 144170 # number of overall hits
|
||||
system.l2c.overall_hits::cpu.itb.walker 12492 # number of overall hits
|
||||
system.l2c.overall_hits::cpu.inst 1001175 # number of overall hits
|
||||
system.l2c.overall_hits::cpu.data 484171 # number of overall hits
|
||||
system.l2c.overall_hits::total 1642008 # number of overall hits
|
||||
system.l2c.ReadReq_misses::cpu.dtb.walker 189 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu.itb.walker 14 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu.inst 17378 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu.data 19180 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::total 36761 # number of ReadReq misses
|
||||
system.l2c.UpgradeReq_misses::cpu.data 3300 # number of UpgradeReq misses
|
||||
system.l2c.UpgradeReq_misses::total 3300 # number of UpgradeReq misses
|
||||
system.l2c.SCUpgradeReq_misses::cpu.data 5 # number of SCUpgradeReq misses
|
||||
system.l2c.SCUpgradeReq_misses::total 5 # number of SCUpgradeReq misses
|
||||
system.l2c.ReadExReq_misses::cpu.data 140292 # number of ReadExReq misses
|
||||
system.l2c.ReadExReq_misses::total 140292 # number of ReadExReq misses
|
||||
system.l2c.demand_misses::cpu.dtb.walker 189 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu.itb.walker 14 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu.inst 17378 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu.data 159472 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::total 177053 # number of demand (read+write) misses
|
||||
system.l2c.overall_misses::cpu.dtb.walker 189 # number of overall misses
|
||||
system.l2c.overall_misses::cpu.itb.walker 14 # number of overall misses
|
||||
system.l2c.overall_misses::cpu.inst 17378 # number of overall misses
|
||||
system.l2c.overall_misses::cpu.data 159472 # number of overall misses
|
||||
system.l2c.overall_misses::total 177053 # number of overall misses
|
||||
system.l2c.ReadReq_miss_latency::cpu.dtb.walker 9850500 # number of ReadReq miss cycles
|
||||
system.l2c.ReadReq_miss_latency::cpu.itb.walker 752000 # number of ReadReq miss cycles
|
||||
system.l2c.ReadReq_miss_latency::cpu.inst 910079500 # number of ReadReq miss cycles
|
||||
system.l2c.ReadReq_miss_latency::cpu.data 1002096000 # number of ReadReq miss cycles
|
||||
system.l2c.ReadReq_miss_latency::total 1922778000 # number of ReadReq miss cycles
|
||||
system.l2c.UpgradeReq_miss_latency::cpu.data 996000 # number of UpgradeReq miss cycles
|
||||
system.l2c.UpgradeReq_miss_latency::total 996000 # number of UpgradeReq miss cycles
|
||||
system.l2c.SCUpgradeReq_miss_latency::cpu.data 104000 # number of SCUpgradeReq miss cycles
|
||||
system.l2c.SCUpgradeReq_miss_latency::total 104000 # number of SCUpgradeReq miss cycles
|
||||
system.l2c.ReadExReq_miss_latency::cpu.data 7365557000 # number of ReadExReq miss cycles
|
||||
system.l2c.ReadExReq_miss_latency::total 7365557000 # number of ReadExReq miss cycles
|
||||
system.l2c.demand_miss_latency::cpu.dtb.walker 9850500 # number of demand (read+write) miss cycles
|
||||
system.l2c.demand_miss_latency::cpu.itb.walker 752000 # number of demand (read+write) miss cycles
|
||||
system.l2c.demand_miss_latency::cpu.inst 910079500 # number of demand (read+write) miss cycles
|
||||
system.l2c.demand_miss_latency::cpu.data 8367653000 # number of demand (read+write) miss cycles
|
||||
system.l2c.demand_miss_latency::total 9288335000 # number of demand (read+write) miss cycles
|
||||
system.l2c.overall_miss_latency::cpu.dtb.walker 9850500 # number of overall miss cycles
|
||||
system.l2c.overall_miss_latency::cpu.itb.walker 752000 # number of overall miss cycles
|
||||
system.l2c.overall_miss_latency::cpu.inst 910079500 # number of overall miss cycles
|
||||
system.l2c.overall_miss_latency::cpu.data 8367653000 # number of overall miss cycles
|
||||
system.l2c.overall_miss_latency::total 9288335000 # number of overall miss cycles
|
||||
system.l2c.ReadReq_accesses::cpu.dtb.walker 144359 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::cpu.itb.walker 12506 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::cpu.inst 1018553 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::cpu.data 397476 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::total 1572894 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.Writeback_accesses::writebacks 635023 # number of Writeback accesses(hits+misses)
|
||||
system.l2c.Writeback_accesses::total 635023 # number of Writeback accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_accesses::cpu.data 3345 # number of UpgradeReq accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_accesses::total 3345 # number of UpgradeReq accesses(hits+misses)
|
||||
system.l2c.SCUpgradeReq_accesses::cpu.data 13 # number of SCUpgradeReq accesses(hits+misses)
|
||||
system.l2c.SCUpgradeReq_accesses::total 13 # number of SCUpgradeReq accesses(hits+misses)
|
||||
system.l2c.ReadExReq_accesses::cpu.data 246167 # number of ReadExReq accesses(hits+misses)
|
||||
system.l2c.ReadExReq_accesses::total 246167 # number of ReadExReq accesses(hits+misses)
|
||||
system.l2c.demand_accesses::cpu.dtb.walker 144359 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu.itb.walker 12506 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu.inst 1018553 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu.data 643643 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::total 1819061 # number of demand (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu.dtb.walker 144359 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu.itb.walker 12506 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu.inst 1018553 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu.data 643643 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::total 1819061 # number of overall (read+write) accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.001309 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.001119 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu.inst 0.017061 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu.data 0.048254 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::total 0.023372 # miss rate for ReadReq accesses
|
||||
system.l2c.UpgradeReq_miss_rate::cpu.data 0.986547 # miss rate for UpgradeReq accesses
|
||||
system.l2c.UpgradeReq_miss_rate::total 0.986547 # miss rate for UpgradeReq accesses
|
||||
system.l2c.SCUpgradeReq_miss_rate::cpu.data 0.384615 # miss rate for SCUpgradeReq accesses
|
||||
system.l2c.SCUpgradeReq_miss_rate::total 0.384615 # miss rate for SCUpgradeReq accesses
|
||||
system.l2c.ReadExReq_miss_rate::cpu.data 0.569906 # miss rate for ReadExReq accesses
|
||||
system.l2c.ReadExReq_miss_rate::total 0.569906 # miss rate for ReadExReq accesses
|
||||
system.l2c.demand_miss_rate::cpu.dtb.walker 0.001309 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu.itb.walker 0.001119 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu.inst 0.017061 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu.data 0.247765 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::total 0.097332 # miss rate for demand accesses
|
||||
system.l2c.overall_miss_rate::cpu.dtb.walker 0.001309 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu.itb.walker 0.001119 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu.inst 0.017061 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu.data 0.247765 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::total 0.097332 # miss rate for overall accesses
|
||||
system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52119.047619 # average ReadReq miss latency
|
||||
system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 53714.285714 # average ReadReq miss latency
|
||||
system.l2c.ReadReq_avg_miss_latency::cpu.inst 52369.634020 # average ReadReq miss latency
|
||||
system.l2c.ReadReq_avg_miss_latency::cpu.data 52246.923879 # average ReadReq miss latency
|
||||
system.l2c.ReadReq_avg_miss_latency::total 52304.833927 # average ReadReq miss latency
|
||||
system.l2c.UpgradeReq_avg_miss_latency::cpu.data 301.818182 # average UpgradeReq miss latency
|
||||
system.l2c.UpgradeReq_avg_miss_latency::total 301.818182 # average UpgradeReq miss latency
|
||||
system.l2c.SCUpgradeReq_avg_miss_latency::cpu.data 20800 # average SCUpgradeReq miss latency
|
||||
system.l2c.SCUpgradeReq_avg_miss_latency::total 20800 # average SCUpgradeReq miss latency
|
||||
system.l2c.ReadExReq_avg_miss_latency::cpu.data 52501.618054 # average ReadExReq miss latency
|
||||
system.l2c.ReadExReq_avg_miss_latency::total 52501.618054 # average ReadExReq miss latency
|
||||
system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52119.047619 # average overall miss latency
|
||||
system.l2c.demand_avg_miss_latency::cpu.itb.walker 53714.285714 # average overall miss latency
|
||||
system.l2c.demand_avg_miss_latency::cpu.inst 52369.634020 # average overall miss latency
|
||||
system.l2c.demand_avg_miss_latency::cpu.data 52470.985502 # average overall miss latency
|
||||
system.l2c.demand_avg_miss_latency::total 52460.760337 # average overall miss latency
|
||||
system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52119.047619 # average overall miss latency
|
||||
system.l2c.overall_avg_miss_latency::cpu.itb.walker 53714.285714 # average overall miss latency
|
||||
system.l2c.overall_avg_miss_latency::cpu.inst 52369.634020 # average overall miss latency
|
||||
system.l2c.overall_avg_miss_latency::cpu.data 52470.985502 # average overall miss latency
|
||||
system.l2c.overall_avg_miss_latency::total 52460.760337 # average overall miss latency
|
||||
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.l2c.fast_writes 0 # number of fast writes performed
|
||||
system.l2c.cache_copies 0 # number of cache copies performed
|
||||
system.l2c.writebacks::writebacks 102651 # number of writebacks
|
||||
system.l2c.writebacks::total 102651 # number of writebacks
|
||||
system.l2c.ReadReq_mshr_hits::cpu.dtb.walker 1 # number of ReadReq MSHR hits
|
||||
system.l2c.ReadReq_mshr_hits::cpu.inst 14 # number of ReadReq MSHR hits
|
||||
system.l2c.ReadReq_mshr_hits::cpu.data 86 # number of ReadReq MSHR hits
|
||||
system.l2c.ReadReq_mshr_hits::total 101 # number of ReadReq MSHR hits
|
||||
system.l2c.demand_mshr_hits::cpu.dtb.walker 1 # number of demand (read+write) MSHR hits
|
||||
system.l2c.demand_mshr_hits::cpu.inst 14 # number of demand (read+write) MSHR hits
|
||||
system.l2c.demand_mshr_hits::cpu.data 86 # number of demand (read+write) MSHR hits
|
||||
system.l2c.demand_mshr_hits::total 101 # number of demand (read+write) MSHR hits
|
||||
system.l2c.overall_mshr_hits::cpu.dtb.walker 1 # number of overall MSHR hits
|
||||
system.l2c.overall_mshr_hits::cpu.inst 14 # number of overall MSHR hits
|
||||
system.l2c.overall_mshr_hits::cpu.data 86 # number of overall MSHR hits
|
||||
system.l2c.overall_mshr_hits::total 101 # number of overall MSHR hits
|
||||
system.l2c.ReadReq_mshr_misses::cpu.dtb.walker 188 # number of ReadReq MSHR misses
|
||||
system.l2c.ReadReq_mshr_misses::cpu.itb.walker 14 # number of ReadReq MSHR misses
|
||||
system.l2c.ReadReq_mshr_misses::cpu.inst 17364 # number of ReadReq MSHR misses
|
||||
system.l2c.ReadReq_mshr_misses::cpu.data 19094 # number of ReadReq MSHR misses
|
||||
system.l2c.ReadReq_mshr_misses::total 36660 # number of ReadReq MSHR misses
|
||||
system.l2c.UpgradeReq_mshr_misses::cpu.data 3300 # number of UpgradeReq MSHR misses
|
||||
system.l2c.UpgradeReq_mshr_misses::total 3300 # number of UpgradeReq MSHR misses
|
||||
system.l2c.SCUpgradeReq_mshr_misses::cpu.data 5 # number of SCUpgradeReq MSHR misses
|
||||
system.l2c.SCUpgradeReq_mshr_misses::total 5 # number of SCUpgradeReq MSHR misses
|
||||
system.l2c.ReadExReq_mshr_misses::cpu.data 140292 # number of ReadExReq MSHR misses
|
||||
system.l2c.ReadExReq_mshr_misses::total 140292 # number of ReadExReq MSHR misses
|
||||
system.l2c.demand_mshr_misses::cpu.dtb.walker 188 # number of demand (read+write) MSHR misses
|
||||
system.l2c.demand_mshr_misses::cpu.itb.walker 14 # number of demand (read+write) MSHR misses
|
||||
system.l2c.demand_mshr_misses::cpu.inst 17364 # number of demand (read+write) MSHR misses
|
||||
system.l2c.demand_mshr_misses::cpu.data 159386 # number of demand (read+write) MSHR misses
|
||||
system.l2c.demand_mshr_misses::total 176952 # number of demand (read+write) MSHR misses
|
||||
system.l2c.overall_mshr_misses::cpu.dtb.walker 188 # number of overall MSHR misses
|
||||
system.l2c.overall_mshr_misses::cpu.itb.walker 14 # number of overall MSHR misses
|
||||
system.l2c.overall_mshr_misses::cpu.inst 17364 # number of overall MSHR misses
|
||||
system.l2c.overall_mshr_misses::cpu.data 159386 # number of overall MSHR misses
|
||||
system.l2c.overall_mshr_misses::total 176952 # number of overall MSHR misses
|
||||
system.l2c.ReadReq_mshr_miss_latency::cpu.dtb.walker 7532000 # number of ReadReq MSHR miss cycles
|
||||
system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker 584000 # number of ReadReq MSHR miss cycles
|
||||
system.l2c.ReadReq_mshr_miss_latency::cpu.inst 697406000 # number of ReadReq MSHR miss cycles
|
||||
system.l2c.ReadReq_mshr_miss_latency::cpu.data 765603000 # number of ReadReq MSHR miss cycles
|
||||
system.l2c.ReadReq_mshr_miss_latency::total 1471125000 # number of ReadReq MSHR miss cycles
|
||||
system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 132880000 # number of UpgradeReq MSHR miss cycles
|
||||
system.l2c.UpgradeReq_mshr_miss_latency::total 132880000 # number of UpgradeReq MSHR miss cycles
|
||||
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu.data 200000 # number of SCUpgradeReq MSHR miss cycles
|
||||
system.l2c.SCUpgradeReq_mshr_miss_latency::total 200000 # number of SCUpgradeReq MSHR miss cycles
|
||||
system.l2c.ReadExReq_mshr_miss_latency::cpu.data 5622122500 # number of ReadExReq MSHR miss cycles
|
||||
system.l2c.ReadExReq_mshr_miss_latency::total 5622122500 # number of ReadExReq MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_latency::cpu.dtb.walker 7532000 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_latency::cpu.itb.walker 584000 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_latency::cpu.inst 697406000 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_latency::cpu.data 6387725500 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_latency::total 7093247500 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency::cpu.dtb.walker 7532000 # number of overall MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency::cpu.itb.walker 584000 # number of overall MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency::cpu.inst 697406000 # number of overall MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency::cpu.data 6387725500 # number of overall MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency::total 7093247500 # number of overall MSHR miss cycles
|
||||
system.l2c.ReadReq_mshr_uncacheable_latency::cpu.inst 5427000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 131758586500 # number of ReadReq MSHR uncacheable cycles
|
||||
system.l2c.ReadReq_mshr_uncacheable_latency::total 131764013500 # number of ReadReq MSHR uncacheable cycles
|
||||
system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 32346095899 # number of WriteReq MSHR uncacheable cycles
|
||||
system.l2c.WriteReq_mshr_uncacheable_latency::total 32346095899 # number of WriteReq MSHR uncacheable cycles
|
||||
system.l2c.overall_mshr_uncacheable_latency::cpu.inst 5427000 # number of overall MSHR uncacheable cycles
|
||||
system.l2c.overall_mshr_uncacheable_latency::cpu.data 164104682399 # number of overall MSHR uncacheable cycles
|
||||
system.l2c.overall_mshr_uncacheable_latency::total 164110109399 # number of overall MSHR uncacheable cycles
|
||||
system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001302 # mshr miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001119 # mshr miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.017048 # mshr miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.048038 # mshr miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_mshr_miss_rate::total 0.023307 # mshr miss rate for ReadReq accesses
|
||||
system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.986547 # mshr miss rate for UpgradeReq accesses
|
||||
system.l2c.UpgradeReq_mshr_miss_rate::total 0.986547 # mshr miss rate for UpgradeReq accesses
|
||||
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu.data 0.384615 # mshr miss rate for SCUpgradeReq accesses
|
||||
system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.384615 # mshr miss rate for SCUpgradeReq accesses
|
||||
system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.569906 # mshr miss rate for ReadExReq accesses
|
||||
system.l2c.ReadExReq_mshr_miss_rate::total 0.569906 # mshr miss rate for ReadExReq accesses
|
||||
system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.001302 # mshr miss rate for demand accesses
|
||||
system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.001119 # mshr miss rate for demand accesses
|
||||
system.l2c.demand_mshr_miss_rate::cpu.inst 0.017048 # mshr miss rate for demand accesses
|
||||
system.l2c.demand_mshr_miss_rate::cpu.data 0.247631 # mshr miss rate for demand accesses
|
||||
system.l2c.demand_mshr_miss_rate::total 0.097277 # mshr miss rate for demand accesses
|
||||
system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.001302 # mshr miss rate for overall accesses
|
||||
system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.001119 # mshr miss rate for overall accesses
|
||||
system.l2c.overall_mshr_miss_rate::cpu.inst 0.017048 # mshr miss rate for overall accesses
|
||||
system.l2c.overall_mshr_miss_rate::cpu.data 0.247631 # mshr miss rate for overall accesses
|
||||
system.l2c.overall_mshr_miss_rate::total 0.097277 # mshr miss rate for overall accesses
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40063.829787 # average ReadReq mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 41714.285714 # average ReadReq mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40163.902327 # average ReadReq mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40096.522468 # average ReadReq mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::total 40128.887070 # average ReadReq mshr miss latency
|
||||
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40266.666667 # average UpgradeReq mshr miss latency
|
||||
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40266.666667 # average UpgradeReq mshr miss latency
|
||||
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 40000 # average SCUpgradeReq mshr miss latency
|
||||
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40000 # average SCUpgradeReq mshr miss latency
|
||||
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40074.434038 # average ReadExReq mshr miss latency
|
||||
system.l2c.ReadExReq_avg_mshr_miss_latency::total 40074.434038 # average ReadExReq mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40063.829787 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 41714.285714 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40163.902327 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu.data 40077.080170 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::total 40085.715335 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40063.829787 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 41714.285714 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40163.902327 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu.data 40077.080170 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::total 40085.715335 # average overall mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
|
||||
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
|
||||
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
||||
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
|
||||
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
||||
system.l2c.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
|
||||
system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
|
||||
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
||||
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
||||
system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
|
||||
system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
|
||||
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
|
||||
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
|
||||
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
|
||||
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.dtb.read_hits 52103903 # DTB read hits
|
||||
system.cpu.dtb.read_misses 93079 # DTB read misses
|
||||
system.cpu.dtb.write_hits 11946241 # DTB write hits
|
||||
system.cpu.dtb.write_misses 25022 # DTB write misses
|
||||
system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed
|
||||
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
|
||||
system.cpu.dtb.flush_entries 4532 # Number of entries that have been flushed from TLB
|
||||
system.cpu.dtb.align_faults 5562 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.dtb.prefetch_faults 707 # Number of TLB faults due to prefetch
|
||||
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.dtb.perms_faults 2799 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.dtb.read_accesses 52196982 # DTB read accesses
|
||||
system.cpu.dtb.write_accesses 11971263 # DTB write accesses
|
||||
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
|
||||
system.cpu.dtb.hits 64050144 # DTB hits
|
||||
system.cpu.dtb.misses 118101 # DTB misses
|
||||
system.cpu.dtb.accesses 64168245 # DTB accesses
|
||||
system.cpu.itb.inst_hits 13717584 # ITB inst hits
|
||||
system.cpu.itb.inst_misses 12272 # ITB inst misses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.write_hits 0 # DTB write hits
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed
|
||||
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
|
||||
system.cpu.itb.flush_entries 2655 # Number of entries that have been flushed from TLB
|
||||
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.itb.perms_faults 6863 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.itb.inst_accesses 13729856 # ITB inst accesses
|
||||
system.cpu.itb.hits 13717584 # DTB hits
|
||||
system.cpu.itb.misses 12272 # DTB misses
|
||||
system.cpu.itb.accesses 13729856 # DTB accesses
|
||||
system.cpu.numCycles 411352060 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.BPredUnit.lookups 15654738 # Number of BP lookups
|
||||
system.cpu.BPredUnit.condPredicted 12362397 # Number of conditional branches predicted
|
||||
system.cpu.BPredUnit.condIncorrect 932839 # Number of conditional branches incorrect
|
||||
system.cpu.BPredUnit.BTBLookups 10530768 # Number of BTB lookups
|
||||
system.cpu.BPredUnit.BTBHits 8288874 # Number of BTB hits
|
||||
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu.BPredUnit.usedRAS 1329017 # Number of times the RAS was used to get a target.
|
||||
system.cpu.BPredUnit.RASInCorrect 195537 # Number of incorrect RAS predictions.
|
||||
system.cpu.fetch.icacheStallCycles 33116930 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.Insts 103031700 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.Branches 15654738 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.predictedBranches 9617891 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.Cycles 22620194 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.SquashCycles 6706106 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.TlbCycles 163882 # Number of cycles fetch has spent waiting for tlb
|
||||
system.cpu.fetch.BlockedCycles 89861042 # Number of cycles fetch has spent blocked
|
||||
system.cpu.fetch.MiscStallCycles 2823 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
||||
system.cpu.fetch.PendingTrapStallCycles 147160 # Number of stall cycles due to pending traps
|
||||
system.cpu.fetch.PendingQuiesceStallCycles 218224 # Number of stall cycles due to pending quiesce instructions
|
||||
system.cpu.fetch.IcacheWaitRetryStallCycles 462 # Number of stall cycles due to full MSHR
|
||||
system.cpu.fetch.CacheLines 13709942 # Number of cache lines fetched
|
||||
system.cpu.fetch.IcacheSquashes 998560 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.ItlbSquashes 6868 # Number of outstanding ITLB misses that were squashed
|
||||
system.cpu.fetch.rateDist::samples 150746244 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 0.848897 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 2.234280 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 128142810 85.01% 85.01% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 1478319 0.98% 85.99% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 1855018 1.23% 87.22% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 2695901 1.79% 89.01% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 1893540 1.26% 90.26% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 1191101 0.79% 91.05% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 2951659 1.96% 93.01% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 850848 0.56% 93.57% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 9687048 6.43% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::total 150746244 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.branchRate 0.038057 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.rate 0.250471 # Number of inst fetches per cycle
|
||||
system.cpu.decode.IdleCycles 35228906 # Number of cycles decode is idle
|
||||
system.cpu.decode.BlockedCycles 89710063 # Number of cycles decode is blocked
|
||||
system.cpu.decode.RunCycles 20347806 # Number of cycles decode is running
|
||||
system.cpu.decode.UnblockCycles 1026685 # Number of cycles decode is unblocking
|
||||
system.cpu.decode.SquashCycles 4432784 # Number of cycles decode is squashing
|
||||
system.cpu.decode.BranchResolved 2275641 # Number of times decode resolved a branch
|
||||
system.cpu.decode.BranchMispred 186729 # Number of times decode detected a branch misprediction
|
||||
system.cpu.decode.DecodedInsts 120042439 # Number of instructions handled by decode
|
||||
system.cpu.decode.SquashedInsts 604390 # Number of squashed instructions handled by decode
|
||||
system.cpu.rename.SquashCycles 4432784 # Number of cycles rename is squashing
|
||||
system.cpu.rename.IdleCycles 37305734 # Number of cycles rename is idle
|
||||
system.cpu.rename.BlockCycles 37165628 # Number of cycles rename is blocking
|
||||
system.cpu.rename.serializeStallCycles 46502465 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RunCycles 19251695 # Number of cycles rename is running
|
||||
system.cpu.rename.UnblockCycles 6087938 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RenamedInsts 112539597 # Number of instructions processed by rename
|
||||
system.cpu.rename.ROBFullEvents 3873 # Number of times rename has blocked due to ROB full
|
||||
system.cpu.rename.IQFullEvents 1013212 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.LSQFullEvents 4109157 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.FullRegisterEvents 45575 # Number of times there has been no free registers
|
||||
system.cpu.rename.RenamedOperands 117156815 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RenameLookups 517555842 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.int_rename_lookups 517460811 # Number of integer rename lookups
|
||||
system.cpu.rename.fp_rename_lookups 95031 # Number of floating rename lookups
|
||||
system.cpu.rename.CommittedMaps 77687687 # Number of HB maps that are committed
|
||||
system.cpu.rename.UndoneMaps 39469127 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.serializingInsts 939790 # count of serializing insts renamed
|
||||
system.cpu.rename.tempSerializingInsts 835958 # count of temporary serializing insts renamed
|
||||
system.cpu.rename.skidInsts 12443241 # count of insts added to the skid buffer
|
||||
system.cpu.memDep0.insertedLoads 21685850 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 14072237 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.conflictingLoads 1938675 # Number of conflicting loads.
|
||||
system.cpu.memDep0.conflictingStores 2482763 # Number of conflicting stores.
|
||||
system.cpu.iq.iqInstsAdded 102391550 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqNonSpecInstsAdded 1619583 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqInstsIssued 126350622 # Number of instructions issued
|
||||
system.cpu.iq.iqSquashedInstsIssued 234593 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedInstsExamined 26254924 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedOperandsExamined 71509700 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 332277 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.issued_per_cycle::samples 150746244 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::mean 0.838168 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::stdev 1.542455 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::0 105470655 69.97% 69.97% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::1 14086510 9.34% 79.31% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::2 7371222 4.89% 84.20% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::3 5923402 3.93% 88.13% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::4 12762751 8.47% 96.60% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::5 2810704 1.86% 98.46% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::6 1735902 1.15% 99.61% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::7 449258 0.30% 99.91% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::8 135840 0.09% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::total 150746244 # Number of insts issued each cycle
|
||||
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntAlu 61043 0.69% 0.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntMult 4 0.00% 0.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntDiv 0 0.00% 0.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatMult 0 0.00% 0.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdMult 0 0.00% 0.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdShift 0 0.00% 0.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::MemRead 8421186 94.66% 95.34% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::MemWrite 414230 4.66% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.FU_type_0::No_OpClass 106530 0.08% 0.08% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntAlu 59762768 47.30% 47.38% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntMult 95812 0.08% 47.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdMisc 38 0.00% 47.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdShift 45 0.00% 47.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdShiftAcc 9 0.00% 47.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMisc 2279 0.00% 47.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMultAcc 9 0.00% 47.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::MemRead 53776494 42.56% 90.02% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::MemWrite 12606638 9.98% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::total 126350622 # Type of FU issued
|
||||
system.cpu.iq.rate 0.307159 # Inst issue rate
|
||||
system.cpu.iq.fu_busy_cnt 8896463 # FU busy when requested
|
||||
system.cpu.iq.fu_busy_rate 0.070411 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.int_inst_queue_reads 412671946 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_writes 130285978 # Number of integer instruction queue writes
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 87040433 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.fp_inst_queue_reads 24078 # Number of floating instruction queue reads
|
||||
system.cpu.iq.fp_inst_queue_writes 13182 # Number of floating instruction queue writes
|
||||
system.cpu.iq.fp_inst_queue_wakeup_accesses 10434 # Number of floating instruction queue wakeup accesses
|
||||
system.cpu.iq.int_alu_accesses 135127716 # Number of integer alu accesses
|
||||
system.cpu.iq.fp_alu_accesses 12839 # Number of floating point alu accesses
|
||||
system.cpu.iew.lsq.thread0.forwLoads 636069 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread0.squashedLoads 5970496 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread0.ignoredResponses 11101 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread0.memOrderViolation 34253 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread0.squashedStores 2273952 # Number of stores squashed
|
||||
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
||||
system.cpu.iew.lsq.thread0.rescheduledLoads 34114355 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread0.cacheBlocked 1152098 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||||
system.cpu.iew.iewSquashCycles 4432784 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewBlockCycles 28604721 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewUnblockCycles 436722 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.iewDispatchedInsts 104273041 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewDispSquashedInsts 335924 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispLoadInsts 21685850 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispStoreInsts 14072237 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 992808 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewIQFullEvents 95700 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.iewLSQFullEvents 11591 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.memOrderViolationEvents 34253 # Number of memory order violations
|
||||
system.cpu.iew.predictedTakenIncorrect 552378 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.iew.predictedNotTakenIncorrect 346914 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.branchMispredicts 899292 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewExecutedInsts 123108789 # Number of executed instructions
|
||||
system.cpu.iew.iewExecLoadInsts 52799372 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 3241833 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
||||
system.cpu.iew.exec_nop 261908 # number of nop insts executed
|
||||
system.cpu.iew.exec_refs 65255060 # number of memory reference insts executed
|
||||
system.cpu.iew.exec_branches 11601340 # Number of branches executed
|
||||
system.cpu.iew.exec_stores 12455688 # Number of stores executed
|
||||
system.cpu.iew.exec_rate 0.299278 # Inst execution rate
|
||||
system.cpu.iew.wb_sent 121555618 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.wb_count 87050867 # cumulative count of insts written-back
|
||||
system.cpu.iew.wb_producers 47546734 # num instructions producing a value
|
||||
system.cpu.iew.wb_consumers 88572059 # num instructions consuming a value
|
||||
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
||||
system.cpu.iew.wb_rate 0.211621 # insts written-back per cycle
|
||||
system.cpu.iew.wb_fanout 0.536814 # average fanout of values written-back
|
||||
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||
system.cpu.commit.commitCommittedInsts 59729390 # The number of committed instructions
|
||||
system.cpu.commit.commitCommittedOps 77077156 # The number of committed instructions
|
||||
system.cpu.commit.commitSquashedInsts 27015439 # The number of squashed insts skipped by commit
|
||||
system.cpu.commit.commitNonSpecStalls 1287306 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu.commit.branchMispredicts 793496 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.committed_per_cycle::samples 146395876 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::mean 0.526498 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::stdev 1.504904 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::0 118626341 81.03% 81.03% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::1 13714527 9.37% 90.40% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::2 3991808 2.73% 93.13% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::3 2249419 1.54% 94.66% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::4 1746576 1.19% 95.86% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::5 1042045 0.71% 96.57% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::6 1550885 1.06% 97.63% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::7 665283 0.45% 98.08% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::8 2808992 1.92% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::total 146395876 # Number of insts commited each cycle
|
||||
system.cpu.commit.committedInsts 59729390 # Number of instructions committed
|
||||
system.cpu.commit.committedOps 77077156 # Number of ops (including micro ops) committed
|
||||
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
||||
system.cpu.commit.refs 27513639 # Number of memory references committed
|
||||
system.cpu.commit.loads 15715354 # Number of loads committed
|
||||
system.cpu.commit.membars 413068 # Number of memory barriers committed
|
||||
system.cpu.commit.branches 9904424 # Number of branches committed
|
||||
system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions.
|
||||
system.cpu.commit.int_insts 68617835 # Number of committed integer instructions.
|
||||
system.cpu.commit.function_calls 995976 # Number of function calls committed.
|
||||
system.cpu.commit.bw_lim_events 2808992 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
||||
system.cpu.rob.rob_reads 245922084 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 212744706 # The number of ROB writes
|
||||
system.cpu.timesIdled 1895448 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 260605816 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.quiesceCycles 4591931267 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
|
||||
system.cpu.committedInsts 59579009 # Number of Instructions Simulated
|
||||
system.cpu.committedOps 76926775 # Number of Ops (including micro ops) Simulated
|
||||
system.cpu.committedInsts_total 59579009 # Number of Instructions Simulated
|
||||
system.cpu.cpi 6.904312 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 6.904312 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 0.144837 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.144837 # IPC: Total IPC of All Threads
|
||||
system.cpu.int_regfile_reads 558200782 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 89400906 # number of integer regfile writes
|
||||
system.cpu.fp_regfile_reads 8900 # number of floating regfile reads
|
||||
system.cpu.fp_regfile_writes 2982 # number of floating regfile writes
|
||||
system.cpu.misc_regfile_reads 135543435 # number of misc regfile reads
|
||||
system.cpu.misc_regfile_writes 912729 # number of misc regfile writes
|
||||
system.cpu.icache.replacements 1019271 # number of replacements
|
||||
system.cpu.icache.tagsinuse 511.444719 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 12598089 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 1019783 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 12.353696 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 6290137000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 511.444719 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.998915 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.998915 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 12598089 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 12598089 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 12598089 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 12598089 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 12598089 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 12598089 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 1111711 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 1111711 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 1111711 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 1111711 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 1111711 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 1111711 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 16369836984 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 16369836984 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 16369836984 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 16369836984 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 16369836984 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 16369836984 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 13709800 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 13709800 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 13709800 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 13709800 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 13709800 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 13709800 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.081089 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.081089 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.081089 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.081089 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.081089 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.081089 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14724.903310 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 14724.903310 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 14724.903310 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 14724.903310 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 14724.903310 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 14724.903310 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 2973484 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 393 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs 7566.117048 # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks::writebacks 60091 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 60091 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 91891 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::total 91891 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::cpu.inst 91891 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::total 91891 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::cpu.inst 91891 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::total 91891 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1019820 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 1019820 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 1019820 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 1019820 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 1019820 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 1019820 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12187570984 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 12187570984 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12187570984 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 12187570984 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12187570984 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 12187570984 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 7292000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 7292000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 7292000 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency::total 7292000 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.074386 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.074386 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.074386 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.074386 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.074386 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.074386 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11950.707952 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11950.707952 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11950.707952 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 11950.707952 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11950.707952 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 11950.707952 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 645895 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 511.991565 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 22075422 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 646407 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 34.150964 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 49188000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 511.991565 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.999984 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.999984 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 14216478 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 14216478 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 7283636 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 7283636 # number of WriteReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::cpu.data 286092 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::total 286092 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::cpu.data 285655 # number of StoreCondReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::total 285655 # number of StoreCondReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 21500114 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 21500114 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 21500114 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 21500114 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 747655 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 747655 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 2966865 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 2966865 # number of WriteReq misses
|
||||
system.cpu.dcache.LoadLockedReq_misses::cpu.data 13747 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.LoadLockedReq_misses::total 13747 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.StoreCondReq_misses::cpu.data 13 # number of StoreCondReq misses
|
||||
system.cpu.dcache.StoreCondReq_misses::total 13 # number of StoreCondReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 3714520 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 3714520 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 3714520 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 3714520 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 11237363500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 11237363500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 110154178240 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 110154178240 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 224042000 # number of LoadLockedReq miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_miss_latency::total 224042000 # number of LoadLockedReq miss cycles
|
||||
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 394000 # number of StoreCondReq miss cycles
|
||||
system.cpu.dcache.StoreCondReq_miss_latency::total 394000 # number of StoreCondReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 121391541740 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 121391541740 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 121391541740 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 121391541740 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 14964133 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 14964133 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 10250501 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 10250501 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 299839 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::total 299839 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::cpu.data 285668 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::total 285668 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 25214634 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 25214634 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 25214634 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 25214634 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.049963 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.049963 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289436 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.289436 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045848 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045848 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000046 # miss rate for StoreCondReq accesses
|
||||
system.cpu.dcache.StoreCondReq_miss_rate::total 0.000046 # miss rate for StoreCondReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.147316 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.147316 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.147316 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.147316 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15030.145589 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 15030.145589 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37128.139717 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 37128.139717 # average WriteReq miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16297.519459 # average LoadLockedReq miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16297.519459 # average LoadLockedReq miss latency
|
||||
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 30307.692308 # average StoreCondReq miss latency
|
||||
system.cpu.dcache.StoreCondReq_avg_miss_latency::total 30307.692308 # average StoreCondReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 32680.276789 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 32680.276789 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 32680.276789 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 32680.276789 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 17091437 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 7607500 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 3024 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 268 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 5651.930225 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets 28386.194030 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 574932 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 574932 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 359686 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 359686 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2717440 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 2717440 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1386 # number of LoadLockedReq MSHR hits
|
||||
system.cpu.dcache.LoadLockedReq_mshr_hits::total 1386 # number of LoadLockedReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 3077126 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 3077126 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 3077126 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 3077126 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 387969 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 387969 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249425 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 249425 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12361 # number of LoadLockedReq MSHR misses
|
||||
system.cpu.dcache.LoadLockedReq_mshr_misses::total 12361 # number of LoadLockedReq MSHR misses
|
||||
system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 13 # number of StoreCondReq MSHR misses
|
||||
system.cpu.dcache.StoreCondReq_mshr_misses::total 13 # number of StoreCondReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 637394 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 637394 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 637394 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 637394 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5287973500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 5287973500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8908906437 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 8908906437 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 165672500 # number of LoadLockedReq MSHR miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 165672500 # number of LoadLockedReq MSHR miss cycles
|
||||
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 351500 # number of StoreCondReq MSHR miss cycles
|
||||
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 351500 # number of StoreCondReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14196879937 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 14196879937 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14196879937 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 14196879937 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 147151877500 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 147151877500 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 42255772015 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 42255772015 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 189407649515 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency::total 189407649515 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.025927 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.025927 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024333 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024333 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.041225 # mshr miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.041225 # mshr miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000046 # mshr miss rate for StoreCondReq accesses
|
||||
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000046 # mshr miss rate for StoreCondReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025279 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.025279 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025279 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.025279 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13629.886666 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13629.886666 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35717.776634 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35717.776634 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13402.839576 # average LoadLockedReq mshr miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13402.839576 # average LoadLockedReq mshr miss latency
|
||||
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 27038.461538 # average StoreCondReq mshr miss latency
|
||||
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 27038.461538 # average StoreCondReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22273.319073 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 22273.319073 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22273.319073 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 22273.319073 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.iocache.replacements 0 # number of replacements
|
||||
system.iocache.tagsinuse 0 # Cycle average of tags in use
|
||||
system.iocache.total_refs 0 # Total number of references to valid blocks.
|
||||
system.iocache.sampled_refs 0 # Sample count of references to valid blocks.
|
||||
system.iocache.avg_refs nan # Average number of references to valid blocks.
|
||||
system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.iocache.fast_writes 0 # number of fast writes performed
|
||||
system.iocache.cache_copies 0 # number of cache copies performed
|
||||
system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1296131413558 # number of ReadReq MSHR uncacheable cycles
|
||||
system.iocache.ReadReq_mshr_uncacheable_latency::total 1296131413558 # number of ReadReq MSHR uncacheable cycles
|
||||
system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1296131413558 # number of overall MSHR uncacheable cycles
|
||||
system.iocache.overall_mshr_uncacheable_latency::total 1296131413558 # number of overall MSHR uncacheable cycles
|
||||
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
|
||||
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
||||
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
|
||||
system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
||||
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
||||
system.cpu.kern.inst.quiesce 88053 # number of quiesce instructions executed
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
Binary file not shown.
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,9 @@
|
||||
warn: Sockets disabled, not accepting terminal connections
|
||||
warn: Reading current count from inactive timer.
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: Don't know what interrupt to clear for console.
|
||||
warn: instruction 'fxsave' unimplemented
|
||||
warn: Tried to clear PCI interrupt 14
|
||||
warn: Unknown mouse command 0xe1.
|
||||
warn: instruction 'wbinvd' unimplemented
|
||||
hack: be nice to actually delete the event here
|
||||
@ -0,0 +1,13 @@
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jun 4 2012 13:44:28
|
||||
gem5 started Jun 4 2012 17:03:49
|
||||
gem5 executing on zizzer
|
||||
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing -re tests/run.py build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing
|
||||
warning: add_child('terminal'): child 'terminal' already has parent
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
|
||||
0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 5157514159500 because m5_exit instruction encountered
|
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,133 @@
|
||||
Linux version 2.6.22.9 (blackga@nacho) (gcc version 4.1.2 (Gentoo 4.1.2)) #2 Mon Oct 8 13:13:00 PDT 2007
|
||||
Command line: earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1
|
||||
BIOS-provided physical RAM map:
|
||||
BIOS-e820: 0000000000000000 - 0000000000100000 (reserved)
|
||||
BIOS-e820: 0000000000100000 - 0000000008000000 (usable)
|
||||
end_pfn_map = 32768
|
||||
kernel direct mapping tables up to 8000000 @ 100000-102000
|
||||
DMI 2.5 present.
|
||||
Zone PFN ranges:
|
||||
DMA 256 -> 4096
|
||||
DMA32 4096 -> 1048576
|
||||
Normal 1048576 -> 1048576
|
||||
early_node_map[1] active PFN ranges
|
||||
0: 256 -> 32768
|
||||
Intel MultiProcessor Specification v1.4
|
||||
MPTABLE: OEM ID: MPTABLE: Product ID: MPTABLE: APIC at: 0xFEE00000
|
||||
Processor #0 (Bootup-CPU)
|
||||
I/O APIC #1 at 0xFEC00000.
|
||||
Setting APIC routing to flat
|
||||
Processors: 1
|
||||
Allocating PCI resources starting at 10000000 (gap: 8000000:f8000000)
|
||||
Built 1 zonelists. Total pages: 30458
|
||||
Kernel command line: earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1
|
||||
Initializing CPU#0
|
||||
PID hash table entries: 512 (order: 9, 4096 bytes)
|
||||
time.c: Detected 2000.000 MHz processor.
|
||||
Console: colour dummy device 80x25
|
||||
console handover: boot [earlyser0] -> real [ttyS0]
|
||||
Dentry cache hash table entries: 16384 (order: 5, 131072 bytes)
|
||||
Inode-cache hash table entries: 8192 (order: 4, 65536 bytes)
|
||||
Checking aperture...
|
||||
Memory: 121556k/131072k available (3742k kernel code, 8456k reserved, 1874k data, 232k init)
|
||||
Calibrating delay loop (skipped)... 3999.96 BogoMIPS preset
|
||||
Mount-cache hash table entries: 256
|
||||
CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)
|
||||
CPU: L2 Cache: 1024K (64 bytes/line)
|
||||
CPU: Fake M5 x86_64 CPU stepping 01
|
||||
ACPI: Core revision 20070126
|
||||
ACPI Exception (tbxface-0618): AE_NO_ACPI_TABLES, While loading namespace from ACPI tables [20070126]
|
||||
ACPI: Unable to load the System Description Tables
|
||||
Using local APIC timer interrupts.
|
||||
result 7812497
|
||||
Detected 7.812 MHz APIC timer.
|
||||
NET: Registered protocol family 16
|
||||
PCI: Using configuration type 1
|
||||
ACPI: Interpreter disabled.
|
||||
Linux Plug and Play Support v0.97 (c) Adam Belay
|
||||
pnp: PnP ACPI: disabled
|
||||
SCSI subsystem initialized
|
||||
usbcore: registered new interface driver usbfs
|
||||
usbcore: registered new interface driver hub
|
||||
usbcore: registered new device driver usb
|
||||
PCI: Probing PCI hardware
|
||||
PCI-GART: No AMD northbridge found.
|
||||
NET: Registered protocol family 2
|
||||
Time: tsc clocksource has been installed.
|
||||
IP route cache hash table entries: 1024 (order: 1, 8192 bytes)
|
||||
TCP established hash table entries: 4096 (order: 4, 65536 bytes)
|
||||
TCP bind hash table entries: 4096 (order: 3, 32768 bytes)
|
||||
TCP: Hash tables configured (established 4096 bind 4096)
|
||||
TCP reno registered
|
||||
Total HugeTLB memory allocated, 0
|
||||
Installing knfsd (copyright (C) 1996 okir@monad.swb.de).
|
||||
io scheduler noop registered
|
||||
io scheduler deadline registered
|
||||
io scheduler cfq registered (default)
|
||||
Real Time Clock Driver v1.12ac
|
||||
Linux agpgart interface v0.102 (c) Dave Jones
|
||||
Serial: 8250/16550 driver $Revision: 1.90 $ 4 ports, IRQ sharing disabled
|
||||
serial8250: ttyS0 at I/O 0x3f8 (irq = 4) is a 8250
|
||||
floppy0: no floppy controllers found
|
||||
RAMDISK driver initialized: 16 RAM disks of 4096K size 1024 blocksize
|
||||
loop: module loaded
|
||||
Intel(R) PRO/1000 Network Driver - version 7.3.20-k2
|
||||
Copyright (c) 1999-2006 Intel Corporation.
|
||||
e100: Intel(R) PRO/100 Network Driver, 3.5.17-k4-NAPI
|
||||
e100: Copyright(c) 1999-2006 Intel Corporation
|
||||
forcedeth.c: Reverse Engineered nForce ethernet driver. Version 0.60.
|
||||
tun: Universal TUN/TAP device driver, 1.6
|
||||
tun: (C) 1999-2004 Max Krasnyansky <maxk@qualcomm.com>
|
||||
netconsole: not configured, aborting
|
||||
Uniform Multi-Platform E-IDE driver Revision: 7.00alpha2
|
||||
ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx
|
||||
PIIX4: IDE controller at PCI slot 0000:00:04.0
|
||||
PCI: Enabling device 0000:00:04.0 (0000 -> 0001)
|
||||
PIIX4: chipset revision 0
|
||||
PIIX4: not 100% native mode: will probe irqs later
|
||||
ide0: BM-DMA at 0x1000-0x1007, BIOS settings: hda:DMA, hdb:DMA
|
||||
ide1: BM-DMA at 0x1008-0x100f, BIOS settings: hdc:DMA, hdd:DMA
|
||||
hda: M5 IDE Disk, ATA DISK drive
|
||||
hdb: M5 IDE Disk, ATA DISK drive
|
||||
ide0 at 0x1f0-0x1f7,0x3f6 on irq 14
|
||||
hda: max request size: 128KiB
|
||||
hda: 1048320 sectors (536 MB), CHS=1040/16/63, UDMA(33)
|
||||
hda: hda1
|
||||
hdb: max request size: 128KiB
|
||||
hdb: 4177920 sectors (2139 MB), CHS=4144/16/63, UDMA(33)
|
||||
hdb: unknown partition table
|
||||
megaraid cmm: 2.20.2.7 (Release Date: Sun Jul 16 00:01:03 EST 2006)
|
||||
megaraid: 2.20.5.1 (Release Date: Thu Nov 16 15:32:35 EST 2006)
|
||||
megasas: 00.00.03.10-rc5 Thu May 17 10:09:32 PDT 2007
|
||||
Fusion MPT base driver 3.04.04
|
||||
Copyright (c) 1999-2007 LSI Logic Corporation
|
||||
Fusion MPT SPI Host driver 3.04.04
|
||||
Fusion MPT SAS Host driver 3.04.04
|
||||
ieee1394: raw1394: /dev/raw1394 device initialized
|
||||
USB Universal Host Controller Interface driver v3.0
|
||||
usbcore: registered new interface driver usblp
|
||||
drivers/usb/class/usblp.c: v0.13: USB Printer Device Class driver
|
||||
Initializing USB Mass Storage driver...
|
||||
usbcore: registered new interface driver usb-storage
|
||||
USB Mass Storage support registered.
|
||||
PNP: No PS/2 controller found. Probing ports directly.
|
||||
serio: i8042 KBD port at 0x60,0x64 irq 1
|
||||
serio: i8042 AUX port at 0x60,0x64 irq 12
|
||||
mice: PS/2 mouse device common for all mice
|
||||
input: AT Translated Set 2 keyboard as /class/input/input0
|
||||
device-mapper: ioctl: 4.11.0-ioctl (2006-10-12) initialised: dm-devel@redhat.com
|
||||
input: PS/2 Generic Mouse as /class/input/input1
|
||||
usbcore: registered new interface driver usbhid
|
||||
drivers/hid/usbhid/hid-core.c: v2.6:USB HID core driver
|
||||
oprofile: using timer interrupt.
|
||||
TCP cubic registered
|
||||
NET: Registered protocol family 1
|
||||
NET: Registered protocol family 10
|
||||
IPv6 over IPv4 tunneling driver
|
||||
NET: Registered protocol family 17
|
||||
EXT2-fs warning: mounting unchecked fs, running e2fsck is recommended
|
||||
VFS: Mounted root (ext2 filesystem).
|
||||
Freeing unused kernel memory: 232k freed
|
||||
|
||||
INIT: version 2.86 booting
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,708 @@
|
||||
|
||||
================ Begin RubySystem Configuration Print ================
|
||||
|
||||
RubySystem config:
|
||||
random_seed: 1234
|
||||
randomization: 0
|
||||
cycle_period: 500
|
||||
block_size_bytes: 64
|
||||
block_size_bits: 6
|
||||
memory_size_bytes: 134217728
|
||||
memory_size_bits: 27
|
||||
|
||||
Network Configuration
|
||||
---------------------
|
||||
network: SIMPLE_NETWORK
|
||||
topology:
|
||||
|
||||
virtual_net_0: active, unordered
|
||||
virtual_net_1: active, ordered
|
||||
virtual_net_2: active, unordered
|
||||
virtual_net_3: inactive
|
||||
virtual_net_4: inactive
|
||||
virtual_net_5: inactive
|
||||
virtual_net_6: inactive
|
||||
virtual_net_7: inactive
|
||||
virtual_net_8: inactive
|
||||
virtual_net_9: inactive
|
||||
|
||||
|
||||
Profiler Configuration
|
||||
----------------------
|
||||
periodic_stats_period: 1000000
|
||||
|
||||
================ End RubySystem Configuration Print ================
|
||||
|
||||
|
||||
Real time: Jun/04/2012 17:25:31
|
||||
|
||||
Profiler Stats
|
||||
--------------
|
||||
Elapsed_time_in_seconds: 842
|
||||
Elapsed_time_in_minutes: 14.0333
|
||||
Elapsed_time_in_hours: 0.233889
|
||||
Elapsed_time_in_days: 0.00974537
|
||||
|
||||
Virtual_time_in_seconds: 842.03
|
||||
Virtual_time_in_minutes: 14.0338
|
||||
Virtual_time_in_hours: 0.233897
|
||||
Virtual_time_in_days: 0.00974572
|
||||
|
||||
Ruby_current_time: 10609379371
|
||||
Ruby_start_time: 0
|
||||
Ruby_cycles: 10609379371
|
||||
|
||||
mbytes_resident: 268.047
|
||||
mbytes_total: 470.199
|
||||
resident_ratio: 0.570071
|
||||
|
||||
ruby_cycles_executed: [ 10609379372 10609379372 ]
|
||||
|
||||
Busy Controller Counts:
|
||||
L1Cache-0:0 L1Cache-1:0
|
||||
L2Cache-0:0
|
||||
Directory-0:0
|
||||
DMA-0:0
|
||||
|
||||
Busy Bank Count:0
|
||||
|
||||
sequencer_requests_outstanding: [binsize: 1 max: 2 count: 187820632 average: 1.00009 | standard deviation: 0.00953306 | 0 187803562 17070 ]
|
||||
|
||||
All Non-Zero Cycle Demand Cache Accesses
|
||||
----------------------------------------
|
||||
miss_latency: [binsize: 1 max: 171 count: 187820631 average: 3.39134 | standard deviation: 5.2186 | 0 0 0 185167359 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 968687 360 299 324 1431839 442 29 55471 396 374 169 16721 201 124 40 32 58 1 1 3 2 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12771 11 6 12 99731 53 39 34 64890 57 7 6 12 49 6 0 1 5 5 ]
|
||||
miss_latency_LD: [binsize: 1 max: 171 count: 14904214 average: 5.1415 | standard deviation: 9.3064 | 0 0 0 13521342 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 127527 49 51 45 1194807 288 8 19874 224 232 85 4872 149 99 34 25 32 1 1 2 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2618 2 2 1 16177 17 7 5 15599 14 3 1 4 10 3 0 0 1 1 ]
|
||||
miss_latency_ST: [binsize: 1 max: 171 count: 9480962 average: 5.51309 | standard deviation: 17.8961 | 0 0 0 9129497 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 28986 16 10 12 180921 99 2 14858 85 68 52 1857 24 15 2 2 7 0 0 0 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4517 5 0 4 70891 24 21 21 48866 33 3 5 5 39 3 0 1 4 4 ]
|
||||
miss_latency_IFETCH: [binsize: 1 max: 165 count: 162265044 average: 3.09464 | standard deviation: 1.92336 | 0 0 0 161451088 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 795815 273 223 254 225 27 19 28 19 28 0 0 0 0 0 0 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5358 4 4 7 11621 10 11 8 3 9 0 0 3 ]
|
||||
miss_latency_RMW_Read: [binsize: 1 max: 163 count: 492779 average: 6.1766 | standard deviation: 10.7903 | 0 0 0 426659 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10783 15 11 11 33161 10 0 12125 33 16 10 8497 16 8 2 2 6 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 227 0 0 0 868 1 0 0 315 1 1 ]
|
||||
miss_latency_Locked_RMW_Read: [binsize: 1 max: 161 count: 338816 average: 5.46921 | standard deviation: 8.08396 | 0 0 0 299957 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5576 7 4 2 22725 18 0 8586 35 30 22 1495 12 2 2 3 6 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 51 0 0 0 174 1 0 0 107 ]
|
||||
miss_latency_Locked_RMW_Write: [binsize: 1 max: 3 count: 338816 average: 3 | standard deviation: 0 | 0 0 0 338816 ]
|
||||
miss_latency_NULL: [binsize: 1 max: 171 count: 187820631 average: 3.39134 | standard deviation: 5.2186 | 0 0 0 185167359 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 968687 360 299 324 1431839 442 29 55471 396 374 169 16721 201 124 40 32 58 1 1 3 2 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12771 11 6 12 99731 53 39 34 64890 57 7 6 12 49 6 0 1 5 5 ]
|
||||
miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
imcomplete_wCC_Times: 0
|
||||
miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
imcomplete_dir_Times: 0
|
||||
miss_latency_LD_NULL: [binsize: 1 max: 171 count: 14904214 average: 5.1415 | standard deviation: 9.3064 | 0 0 0 13521342 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 127527 49 51 45 1194807 288 8 19874 224 232 85 4872 149 99 34 25 32 1 1 2 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2618 2 2 1 16177 17 7 5 15599 14 3 1 4 10 3 0 0 1 1 ]
|
||||
miss_latency_ST_NULL: [binsize: 1 max: 171 count: 9480962 average: 5.51309 | standard deviation: 17.8961 | 0 0 0 9129497 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 28986 16 10 12 180921 99 2 14858 85 68 52 1857 24 15 2 2 7 0 0 0 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4517 5 0 4 70891 24 21 21 48866 33 3 5 5 39 3 0 1 4 4 ]
|
||||
miss_latency_IFETCH_NULL: [binsize: 1 max: 165 count: 162265044 average: 3.09464 | standard deviation: 1.92336 | 0 0 0 161451088 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 795815 273 223 254 225 27 19 28 19 28 0 0 0 0 0 0 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5358 4 4 7 11621 10 11 8 3 9 0 0 3 ]
|
||||
miss_latency_RMW_Read_NULL: [binsize: 1 max: 163 count: 492779 average: 6.1766 | standard deviation: 10.7903 | 0 0 0 426659 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10783 15 11 11 33161 10 0 12125 33 16 10 8497 16 8 2 2 6 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 227 0 0 0 868 1 0 0 315 1 1 ]
|
||||
miss_latency_Locked_RMW_Read_NULL: [binsize: 1 max: 161 count: 338816 average: 5.46921 | standard deviation: 8.08396 | 0 0 0 299957 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5576 7 4 2 22725 18 0 8586 35 30 22 1495 12 2 2 3 6 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 51 0 0 0 174 1 0 0 107 ]
|
||||
miss_latency_Locked_RMW_Write_NULL: [binsize: 1 max: 3 count: 338816 average: 3 | standard deviation: 0 | 0 0 0 338816 ]
|
||||
|
||||
All Non-Zero Cycle SW Prefetch Requests
|
||||
------------------------------------
|
||||
prefetch_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
prefetch_latency_L2Miss:[binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
Request vs. RubySystem State Profile
|
||||
--------------------------------
|
||||
|
||||
|
||||
filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
||||
Message Delayed Cycles
|
||||
----------------------
|
||||
Total_delay_cycles: [binsize: 1 max: 13 count: 10850974 average: 0.59462 | standard deviation: 1.42374 | 9237583 1029 657 892 1609097 1059 106 119 110 244 9 6 16 47 ]
|
||||
Total_nonPF_delay_cycles: [binsize: 1 max: 9 count: 4764816 average: 0.0223746 | standard deviation: 0.296857 | 4737436 520 425 679 25631 106 3 1 10 5 ]
|
||||
virtual_network_0_delay_cycles: [binsize: 1 max: 13 count: 6086158 average: 1.04263 | standard deviation: 1.75725 | 4500147 509 232 213 1583466 953 103 118 100 239 9 6 16 47 ]
|
||||
virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_2_delay_cycles: [binsize: 1 max: 9 count: 83533 average: 0.0149761 | standard deviation: 0.225696 | 83067 123 97 98 116 28 0 0 0 4 ]
|
||||
virtual_network_3_delay_cycles: [binsize: 1 max: 9 count: 4681283 average: 0.0225067 | standard deviation: 0.297971 | 4654369 397 328 581 25515 78 3 1 10 1 ]
|
||||
virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_6_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_7_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_8_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_9_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
||||
Resource Usage
|
||||
--------------
|
||||
page_size: 4096
|
||||
user_time: 841
|
||||
system_time: 0
|
||||
page_reclaims: 69674
|
||||
page_faults: 18
|
||||
swaps: 0
|
||||
block_inputs: 16056
|
||||
block_outputs: 408
|
||||
|
||||
Network Stats
|
||||
-------------
|
||||
|
||||
total_msg_count_Control: 8492901 67943208
|
||||
total_msg_count_Request_Control: 248654 1989232
|
||||
total_msg_count_Response_Data: 8788194 632749968
|
||||
total_msg_count_Response_Control: 10854297 86834376
|
||||
total_msg_count_Writeback_Data: 4753752 342270144
|
||||
total_msg_count_Writeback_Control: 282753 2262024
|
||||
total_msgs: 33420551 total_bytes: 1134048952
|
||||
|
||||
switch_0_inlinks: 2
|
||||
switch_0_outlinks: 2
|
||||
links_utilized_percent_switch_0: 0.0323999
|
||||
links_utilized_percent_switch_0_link_0: 0.0382499 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_0_link_1: 0.02655 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_0_link_0_Request_Control: 42688 341504 [ 42688 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Response_Data: 842729 60676488 [ 0 842729 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Response_Control: 488898 3911184 [ 0 488898 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Control: 855066 6840528 [ 855066 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Response_Data: 40424 2910528 [ 0 40424 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Response_Control: 517774 4142192 [ 0 16296 501478 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Writeback_Data: 429162 30899664 [ 429108 54 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Writeback_Control: 34458 275664 [ 34458 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_1_inlinks: 2
|
||||
switch_1_outlinks: 2
|
||||
links_utilized_percent_switch_1: 0.0735359
|
||||
links_utilized_percent_switch_1_link_0: 0.0818749 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_1_link_1: 0.0651969 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_1_link_0_Request_Control: 40845 326760 [ 40845 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Response_Data: 1788501 128772072 [ 0 1788501 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Response_Control: 1235479 9883832 [ 0 1235479 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Control: 1798206 14385648 [ 1798206 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Response_Data: 34071 2453112 [ 0 34071 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Response_Control: 1270539 10164312 [ 0 17798 1252741 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Writeback_Data: 1155422 83190384 [ 1155308 114 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Writeback_Control: 59793 478344 [ 59793 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_2_inlinks: 2
|
||||
switch_2_outlinks: 2
|
||||
links_utilized_percent_switch_2: 0.110241
|
||||
links_utilized_percent_switch_2_link_0: 0.0976111 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_2_link_1: 0.122871 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_2_link_0_Control: 2653272 21226176 [ 2653272 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Response_Data: 202919 14610168 [ 0 202919 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Response_Control: 1876808 15014464 [ 0 122589 1754219 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Writeback_Data: 1584584 114090048 [ 1584416 168 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Writeback_Control: 94251 754008 [ 94251 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Control: 177695 1421560 [ 177695 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Request_Control: 81588 652704 [ 81588 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Response_Data: 2677208 192758976 [ 0 2677208 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Response_Control: 1717623 13740984 [ 0 1717623 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_3_inlinks: 2
|
||||
switch_3_outlinks: 2
|
||||
links_utilized_percent_switch_3: 0.00651138
|
||||
links_utilized_percent_switch_3_link_0: 0.00495717 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_3_link_1: 0.00806559 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_3_link_0_Control: 177695 1421560 [ 177695 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_Response_Data: 95249 6857928 [ 0 95249 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_Response_Control: 16914 135312 [ 0 16914 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Response_Data: 177695 12794040 [ 0 177695 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Response_Control: 112163 897304 [ 0 112163 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_4_inlinks: 2
|
||||
switch_4_outlinks: 2
|
||||
links_utilized_percent_switch_4: 0
|
||||
links_utilized_percent_switch_4_link_0: 0 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_4_link_1: 0 bw: 16000 base_latency: 1
|
||||
|
||||
|
||||
switch_5_inlinks: 5
|
||||
switch_5_outlinks: 5
|
||||
links_utilized_percent_switch_5: 0.0445386
|
||||
links_utilized_percent_switch_5_link_0: 0.0382499 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_5_link_1: 0.0818749 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_5_link_2: 0.0976111 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_5_link_3: 0.00495717 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_5_link_4: 0 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_5_link_0_Request_Control: 42688 341504 [ 42688 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_0_Response_Data: 842729 60676488 [ 0 842729 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_0_Response_Control: 488898 3911184 [ 0 488898 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_1_Request_Control: 40845 326760 [ 40845 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_1_Response_Data: 1788501 128772072 [ 0 1788501 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_1_Response_Control: 1235479 9883832 [ 0 1235479 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_2_Control: 2653272 21226176 [ 2653272 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_2_Response_Data: 202919 14610168 [ 0 202919 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_2_Response_Control: 1876808 15014464 [ 0 122589 1754219 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_2_Writeback_Data: 1584584 114090048 [ 1584416 168 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_2_Writeback_Control: 94251 754008 [ 94251 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_3_Control: 177695 1421560 [ 177695 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_3_Response_Data: 95249 6857928 [ 0 95249 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_3_Response_Control: 16914 135312 [ 0 16914 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
Cache Stats: system.l1_cntrl0.L1IcacheMemory
|
||||
system.l1_cntrl0.L1IcacheMemory_total_misses: 326846
|
||||
system.l1_cntrl0.L1IcacheMemory_total_demand_misses: 326846
|
||||
system.l1_cntrl0.L1IcacheMemory_total_prefetches: 0
|
||||
system.l1_cntrl0.L1IcacheMemory_total_sw_prefetches: 0
|
||||
system.l1_cntrl0.L1IcacheMemory_total_hw_prefetches: 0
|
||||
|
||||
system.l1_cntrl0.L1IcacheMemory_request_type_IFETCH: 100%
|
||||
|
||||
system.l1_cntrl0.L1IcacheMemory_access_mode_type_Supervisor: 326846 100%
|
||||
|
||||
Cache Stats: system.l1_cntrl0.L1DcacheMemory
|
||||
system.l1_cntrl0.L1DcacheMemory_total_misses: 528220
|
||||
system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 528220
|
||||
system.l1_cntrl0.L1DcacheMemory_total_prefetches: 0
|
||||
system.l1_cntrl0.L1DcacheMemory_total_sw_prefetches: 0
|
||||
system.l1_cntrl0.L1DcacheMemory_total_hw_prefetches: 0
|
||||
|
||||
system.l1_cntrl0.L1DcacheMemory_request_type_LD: 54.1774%
|
||||
system.l1_cntrl0.L1DcacheMemory_request_type_ST: 45.8226%
|
||||
|
||||
system.l1_cntrl0.L1DcacheMemory_access_mode_type_Supervisor: 528220 100%
|
||||
|
||||
--- L1Cache ---
|
||||
- Event Counts -
|
||||
Load [6224073 8680141 ] 14904214
|
||||
Ifetch [103471616 58793435 ] 162265051
|
||||
Store [5279560 5371813 ] 10651373
|
||||
Inv [16350 17912 ] 34262
|
||||
L1_Replacement [827635 1770998 ] 2598633
|
||||
Fwd_GETX [12252 11795 ] 24047
|
||||
Fwd_GETS [14082 11138 ] 25220
|
||||
Fwd_GET_INSTR [4 0 ] 4
|
||||
Data [658 968 ] 1626
|
||||
Data_Exclusive [248296 1024255 ] 1272551
|
||||
DataS_fromL1 [11138 14086 ] 25224
|
||||
Data_all_Acks [582637 749192 ] 1331829
|
||||
Ack [12337 9705 ] 22042
|
||||
Ack_all [12995 10673 ] 23668
|
||||
WB_Ack [463566 1215101 ] 1678667
|
||||
|
||||
- Transitions -
|
||||
NP Load [277889 1086402 ] 1364291
|
||||
NP Ifetch [326723 486562 ] 813285
|
||||
NP Store [224047 199057 ] 423104
|
||||
NP Inv [5639 4132 ] 9771
|
||||
NP L1_Replacement [0 0 ] 0
|
||||
|
||||
I Load [8287 10294 ] 18581
|
||||
I Ifetch [123 548 ] 671
|
||||
I Store [5660 5638 ] 11298
|
||||
I Inv [0 0 ] 0
|
||||
I L1_Replacement [8798 9094 ] 17892
|
||||
|
||||
S Load [577238 501390 ] 1078628
|
||||
S Ifetch [103144768 58306320 ] 161451088
|
||||
S Store [12337 9705 ] 22042
|
||||
S Inv [10590 13636 ] 24226
|
||||
S L1_Replacement [355271 546803 ] 902074
|
||||
|
||||
E Load [1142385 2670000 ] 3812385
|
||||
E Ifetch [0 0 ] 0
|
||||
E Store [81265 85104 ] 166369
|
||||
E Inv [67 30 ] 97
|
||||
E L1_Replacement [165622 937435 ] 1103057
|
||||
E Fwd_GETX [352 103 ] 455
|
||||
E Fwd_GETS [877 1394 ] 2271
|
||||
E Fwd_GET_INSTR [0 0 ] 0
|
||||
|
||||
M Load [4218274 4412055 ] 8630329
|
||||
M Ifetch [0 0 ] 0
|
||||
M Store [4956251 5072309 ] 10028560
|
||||
M Inv [54 114 ] 168
|
||||
M L1_Replacement [297944 277666 ] 575610
|
||||
M Fwd_GETX [11900 11692 ] 23592
|
||||
M Fwd_GETS [13205 9744 ] 22949
|
||||
M Fwd_GET_INSTR [4 0 ] 4
|
||||
|
||||
IS Load [0 0 ] 0
|
||||
IS Ifetch [0 0 ] 0
|
||||
IS Store [0 0 ] 0
|
||||
IS Inv [0 0 ] 0
|
||||
IS L1_Replacement [0 0 ] 0
|
||||
IS Data_Exclusive [248296 1024255 ] 1272551
|
||||
IS DataS_fromL1 [11138 14086 ] 25224
|
||||
IS Data_all_Acks [353588 545465 ] 899053
|
||||
|
||||
IM Load [0 0 ] 0
|
||||
IM Ifetch [0 0 ] 0
|
||||
IM Store [0 0 ] 0
|
||||
IM Inv [0 0 ] 0
|
||||
IM L1_Replacement [0 0 ] 0
|
||||
IM Data [658 968 ] 1626
|
||||
IM Data_all_Acks [229049 203727 ] 432776
|
||||
IM Ack [0 0 ] 0
|
||||
|
||||
SM Load [0 0 ] 0
|
||||
SM Ifetch [0 0 ] 0
|
||||
SM Store [0 0 ] 0
|
||||
SM Inv [0 0 ] 0
|
||||
SM L1_Replacement [0 0 ] 0
|
||||
SM Ack [12337 9705 ] 22042
|
||||
SM Ack_all [12995 10673 ] 23668
|
||||
|
||||
IS_I Load [0 0 ] 0
|
||||
IS_I Ifetch [0 0 ] 0
|
||||
IS_I Store [0 0 ] 0
|
||||
IS_I Inv [0 0 ] 0
|
||||
IS_I L1_Replacement [0 0 ] 0
|
||||
IS_I Data_Exclusive [0 0 ] 0
|
||||
IS_I DataS_fromL1 [0 0 ] 0
|
||||
IS_I Data_all_Acks [0 0 ] 0
|
||||
|
||||
M_I Load [0 0 ] 0
|
||||
M_I Ifetch [2 5 ] 7
|
||||
M_I Store [0 0 ] 0
|
||||
M_I Inv [0 0 ] 0
|
||||
M_I L1_Replacement [0 0 ] 0
|
||||
M_I Fwd_GETX [0 0 ] 0
|
||||
M_I Fwd_GETS [0 0 ] 0
|
||||
M_I Fwd_GET_INSTR [0 0 ] 0
|
||||
M_I WB_Ack [463566 1215101 ] 1678667
|
||||
|
||||
SINK_WB_ACK Load [0 0 ] 0
|
||||
SINK_WB_ACK Ifetch [0 0 ] 0
|
||||
SINK_WB_ACK Store [0 0 ] 0
|
||||
SINK_WB_ACK Inv [0 0 ] 0
|
||||
SINK_WB_ACK L1_Replacement [0 0 ] 0
|
||||
SINK_WB_ACK WB_Ack [0 0 ] 0
|
||||
|
||||
Cache Stats: system.l1_cntrl1.L1IcacheMemory
|
||||
system.l1_cntrl1.L1IcacheMemory_total_misses: 487110
|
||||
system.l1_cntrl1.L1IcacheMemory_total_demand_misses: 487110
|
||||
system.l1_cntrl1.L1IcacheMemory_total_prefetches: 0
|
||||
system.l1_cntrl1.L1IcacheMemory_total_sw_prefetches: 0
|
||||
system.l1_cntrl1.L1IcacheMemory_total_hw_prefetches: 0
|
||||
|
||||
system.l1_cntrl1.L1IcacheMemory_request_type_IFETCH: 100%
|
||||
|
||||
system.l1_cntrl1.L1IcacheMemory_access_mode_type_Supervisor: 487110 100%
|
||||
|
||||
Cache Stats: system.l1_cntrl1.L1DcacheMemory
|
||||
system.l1_cntrl1.L1DcacheMemory_total_misses: 1311096
|
||||
system.l1_cntrl1.L1DcacheMemory_total_demand_misses: 1311096
|
||||
system.l1_cntrl1.L1DcacheMemory_total_prefetches: 0
|
||||
system.l1_cntrl1.L1DcacheMemory_total_sw_prefetches: 0
|
||||
system.l1_cntrl1.L1DcacheMemory_total_hw_prefetches: 0
|
||||
|
||||
system.l1_cntrl1.L1DcacheMemory_request_type_LD: 83.6473%
|
||||
system.l1_cntrl1.L1DcacheMemory_request_type_ST: 16.3527%
|
||||
|
||||
system.l1_cntrl1.L1DcacheMemory_access_mode_type_Supervisor: 1311096 100%
|
||||
|
||||
Cache Stats: system.l2_cntrl0.L2cacheMemory
|
||||
system.l2_cntrl0.L2cacheMemory_total_misses: 226966
|
||||
system.l2_cntrl0.L2cacheMemory_total_demand_misses: 226966
|
||||
system.l2_cntrl0.L2cacheMemory_total_prefetches: 0
|
||||
system.l2_cntrl0.L2cacheMemory_total_sw_prefetches: 0
|
||||
system.l2_cntrl0.L2cacheMemory_total_hw_prefetches: 0
|
||||
|
||||
system.l2_cntrl0.L2cacheMemory_request_type_GETS: 26.2969%
|
||||
system.l2_cntrl0.L2cacheMemory_request_type_GET_INSTR: 7.50861%
|
||||
system.l2_cntrl0.L2cacheMemory_request_type_GETX: 66.1945%
|
||||
|
||||
system.l2_cntrl0.L2cacheMemory_access_mode_type_Supervisor: 226966 100%
|
||||
|
||||
--- L2Cache ---
|
||||
- Event Counts -
|
||||
L1_GET_INSTR [813956 ] 813956
|
||||
L1_GETS [1383116 ] 1383116
|
||||
L1_GETX [434406 ] 434406
|
||||
L1_UPGRADE [22042 ] 22042
|
||||
L1_PUTX [1678667 ] 1678667
|
||||
L1_PUTX_old [0 ] 0
|
||||
Fwd_L1_GETX [0 ] 0
|
||||
Fwd_L1_GETS [0 ] 0
|
||||
Fwd_L1_GET_INSTR [0 ] 0
|
||||
L2_Replacement [95206 ] 95206
|
||||
L2_Replacement_clean [16957 ] 16957
|
||||
Mem_Data [177695 ] 177695
|
||||
Mem_Ack [112163 ] 112163
|
||||
WB_Data [24702 ] 24702
|
||||
WB_Data_clean [690 ] 690
|
||||
Ack [1945 ] 1945
|
||||
Ack_all [8481 ] 8481
|
||||
Unblock [25224 ] 25224
|
||||
Unblock_Cancel [0 ] 0
|
||||
Exclusive_Unblock [1728995 ] 1728995
|
||||
MEM_Inv [0 ] 0
|
||||
|
||||
- Transitions -
|
||||
NP L1_GET_INSTR [17038 ] 17038
|
||||
NP L1_GETS [34465 ] 34465
|
||||
NP L1_GETX [126192 ] 126192
|
||||
NP L1_PUTX [0 ] 0
|
||||
NP L1_PUTX_old [0 ] 0
|
||||
|
||||
SS L1_GET_INSTR [796726 ] 796726
|
||||
SS L1_GETS [85101 ] 85101
|
||||
SS L1_GETX [1832 ] 1832
|
||||
SS L1_UPGRADE [22042 ] 22042
|
||||
SS L1_PUTX [0 ] 0
|
||||
SS L1_PUTX_old [0 ] 0
|
||||
SS L2_Replacement [266 ] 266
|
||||
SS L2_Replacement_clean [8118 ] 8118
|
||||
SS MEM_Inv [0 ] 0
|
||||
|
||||
M L1_GET_INSTR [188 ] 188
|
||||
M L1_GETS [1238086 ] 1238086
|
||||
M L1_GETX [282331 ] 282331
|
||||
M L1_PUTX [0 ] 0
|
||||
M L1_PUTX_old [0 ] 0
|
||||
M L2_Replacement [94758 ] 94758
|
||||
M L2_Replacement_clean [8756 ] 8756
|
||||
M MEM_Inv [0 ] 0
|
||||
|
||||
MT L1_GET_INSTR [4 ] 4
|
||||
MT L1_GETS [25220 ] 25220
|
||||
MT L1_GETX [24047 ] 24047
|
||||
MT L1_PUTX [1678667 ] 1678667
|
||||
MT L1_PUTX_old [0 ] 0
|
||||
MT L2_Replacement [182 ] 182
|
||||
MT L2_Replacement_clean [83 ] 83
|
||||
MT MEM_Inv [0 ] 0
|
||||
|
||||
M_I L1_GET_INSTR [0 ] 0
|
||||
M_I L1_GETS [0 ] 0
|
||||
M_I L1_GETX [0 ] 0
|
||||
M_I L1_UPGRADE [0 ] 0
|
||||
M_I L1_PUTX [0 ] 0
|
||||
M_I L1_PUTX_old [0 ] 0
|
||||
M_I Mem_Ack [112163 ] 112163
|
||||
M_I MEM_Inv [0 ] 0
|
||||
|
||||
MT_I L1_GET_INSTR [0 ] 0
|
||||
MT_I L1_GETS [0 ] 0
|
||||
MT_I L1_GETX [0 ] 0
|
||||
MT_I L1_UPGRADE [0 ] 0
|
||||
MT_I L1_PUTX [0 ] 0
|
||||
MT_I L1_PUTX_old [0 ] 0
|
||||
MT_I WB_Data [125 ] 125
|
||||
MT_I WB_Data_clean [0 ] 0
|
||||
MT_I Ack_all [57 ] 57
|
||||
MT_I MEM_Inv [0 ] 0
|
||||
|
||||
MCT_I L1_GET_INSTR [0 ] 0
|
||||
MCT_I L1_GETS [0 ] 0
|
||||
MCT_I L1_GETX [0 ] 0
|
||||
MCT_I L1_UPGRADE [0 ] 0
|
||||
MCT_I L1_PUTX [0 ] 0
|
||||
MCT_I L1_PUTX_old [0 ] 0
|
||||
MCT_I WB_Data [43 ] 43
|
||||
MCT_I WB_Data_clean [0 ] 0
|
||||
MCT_I Ack_all [40 ] 40
|
||||
|
||||
I_I L1_GET_INSTR [0 ] 0
|
||||
I_I L1_GETS [0 ] 0
|
||||
I_I L1_GETX [0 ] 0
|
||||
I_I L1_UPGRADE [0 ] 0
|
||||
I_I L1_PUTX [0 ] 0
|
||||
I_I L1_PUTX_old [0 ] 0
|
||||
I_I Ack [1679 ] 1679
|
||||
I_I Ack_all [8118 ] 8118
|
||||
|
||||
S_I L1_GET_INSTR [0 ] 0
|
||||
S_I L1_GETS [0 ] 0
|
||||
S_I L1_GETX [0 ] 0
|
||||
S_I L1_UPGRADE [0 ] 0
|
||||
S_I L1_PUTX [0 ] 0
|
||||
S_I L1_PUTX_old [0 ] 0
|
||||
S_I Ack [266 ] 266
|
||||
S_I Ack_all [266 ] 266
|
||||
S_I MEM_Inv [0 ] 0
|
||||
|
||||
ISS L1_GET_INSTR [0 ] 0
|
||||
ISS L1_GETS [0 ] 0
|
||||
ISS L1_GETX [0 ] 0
|
||||
ISS L1_PUTX [0 ] 0
|
||||
ISS L1_PUTX_old [0 ] 0
|
||||
ISS L2_Replacement [0 ] 0
|
||||
ISS L2_Replacement_clean [0 ] 0
|
||||
ISS Mem_Data [34465 ] 34465
|
||||
ISS MEM_Inv [0 ] 0
|
||||
|
||||
IS L1_GET_INSTR [0 ] 0
|
||||
IS L1_GETS [0 ] 0
|
||||
IS L1_GETX [0 ] 0
|
||||
IS L1_PUTX [0 ] 0
|
||||
IS L1_PUTX_old [0 ] 0
|
||||
IS L2_Replacement [0 ] 0
|
||||
IS L2_Replacement_clean [0 ] 0
|
||||
IS Mem_Data [17038 ] 17038
|
||||
IS MEM_Inv [0 ] 0
|
||||
|
||||
IM L1_GET_INSTR [0 ] 0
|
||||
IM L1_GETS [0 ] 0
|
||||
IM L1_GETX [0 ] 0
|
||||
IM L1_PUTX [0 ] 0
|
||||
IM L1_PUTX_old [0 ] 0
|
||||
IM L2_Replacement [0 ] 0
|
||||
IM L2_Replacement_clean [0 ] 0
|
||||
IM Mem_Data [126192 ] 126192
|
||||
IM MEM_Inv [0 ] 0
|
||||
|
||||
SS_MB L1_GET_INSTR [0 ] 0
|
||||
SS_MB L1_GETS [174 ] 174
|
||||
SS_MB L1_GETX [0 ] 0
|
||||
SS_MB L1_UPGRADE [0 ] 0
|
||||
SS_MB L1_PUTX [0 ] 0
|
||||
SS_MB L1_PUTX_old [0 ] 0
|
||||
SS_MB L2_Replacement [0 ] 0
|
||||
SS_MB L2_Replacement_clean [0 ] 0
|
||||
SS_MB Unblock_Cancel [0 ] 0
|
||||
SS_MB Exclusive_Unblock [23874 ] 23874
|
||||
SS_MB MEM_Inv [0 ] 0
|
||||
|
||||
MT_MB L1_GET_INSTR [0 ] 0
|
||||
MT_MB L1_GETS [70 ] 70
|
||||
MT_MB L1_GETX [4 ] 4
|
||||
MT_MB L1_UPGRADE [0 ] 0
|
||||
MT_MB L1_PUTX [0 ] 0
|
||||
MT_MB L1_PUTX_old [0 ] 0
|
||||
MT_MB L2_Replacement [0 ] 0
|
||||
MT_MB L2_Replacement_clean [0 ] 0
|
||||
MT_MB Unblock_Cancel [0 ] 0
|
||||
MT_MB Exclusive_Unblock [1705121 ] 1705121
|
||||
MT_MB MEM_Inv [0 ] 0
|
||||
|
||||
M_MB L1_GET_INSTR [0 ] 0
|
||||
M_MB L1_GETS [0 ] 0
|
||||
M_MB L1_GETX [0 ] 0
|
||||
M_MB L1_UPGRADE [0 ] 0
|
||||
M_MB L1_PUTX [0 ] 0
|
||||
M_MB L1_PUTX_old [0 ] 0
|
||||
M_MB L2_Replacement [0 ] 0
|
||||
M_MB L2_Replacement_clean [0 ] 0
|
||||
M_MB Exclusive_Unblock [0 ] 0
|
||||
M_MB MEM_Inv [0 ] 0
|
||||
|
||||
MT_IIB L1_GET_INSTR [0 ] 0
|
||||
MT_IIB L1_GETS [0 ] 0
|
||||
MT_IIB L1_GETX [0 ] 0
|
||||
MT_IIB L1_UPGRADE [0 ] 0
|
||||
MT_IIB L1_PUTX [0 ] 0
|
||||
MT_IIB L1_PUTX_old [0 ] 0
|
||||
MT_IIB L2_Replacement [0 ] 0
|
||||
MT_IIB L2_Replacement_clean [0 ] 0
|
||||
MT_IIB WB_Data [24523 ] 24523
|
||||
MT_IIB WB_Data_clean [689 ] 689
|
||||
MT_IIB Unblock [12 ] 12
|
||||
MT_IIB MEM_Inv [0 ] 0
|
||||
|
||||
MT_IB L1_GET_INSTR [0 ] 0
|
||||
MT_IB L1_GETS [0 ] 0
|
||||
MT_IB L1_GETX [0 ] 0
|
||||
MT_IB L1_UPGRADE [0 ] 0
|
||||
MT_IB L1_PUTX [0 ] 0
|
||||
MT_IB L1_PUTX_old [0 ] 0
|
||||
MT_IB L2_Replacement [0 ] 0
|
||||
MT_IB L2_Replacement_clean [0 ] 0
|
||||
MT_IB WB_Data [11 ] 11
|
||||
MT_IB WB_Data_clean [1 ] 1
|
||||
MT_IB Unblock_Cancel [0 ] 0
|
||||
MT_IB MEM_Inv [0 ] 0
|
||||
|
||||
MT_SB L1_GET_INSTR [0 ] 0
|
||||
MT_SB L1_GETS [0 ] 0
|
||||
MT_SB L1_GETX [0 ] 0
|
||||
MT_SB L1_UPGRADE [0 ] 0
|
||||
MT_SB L1_PUTX [0 ] 0
|
||||
MT_SB L1_PUTX_old [0 ] 0
|
||||
MT_SB L2_Replacement [0 ] 0
|
||||
MT_SB L2_Replacement_clean [0 ] 0
|
||||
MT_SB Unblock [25212 ] 25212
|
||||
MT_SB MEM_Inv [0 ] 0
|
||||
|
||||
Memory controller: system.dir_cntrl0.memBuffer:
|
||||
memory_total_requests: 272944
|
||||
memory_reads: 177695
|
||||
memory_writes: 95249
|
||||
memory_refreshes: 4108449
|
||||
memory_total_request_delays: 25207
|
||||
memory_delays_per_request: 0.0923523
|
||||
memory_delays_in_input_queue: 7
|
||||
memory_delays_behind_head_of_bank_queue: 0
|
||||
memory_delays_stalled_at_head_of_bank_queue: 25200
|
||||
memory_stalls_for_bank_busy: 11193
|
||||
memory_stalls_for_random_busy: 0
|
||||
memory_stalls_for_anti_starvation: 0
|
||||
memory_stalls_for_arbitration: 2202
|
||||
memory_stalls_for_bus: 11804
|
||||
memory_stalls_for_tfaw: 0
|
||||
memory_stalls_for_read_write_turnaround: 0
|
||||
memory_stalls_for_read_read_turnaround: 1
|
||||
accesses_per_bank: 8796 9232 8713 8487 8759 8199 8936 8313 8486 8359 8337 9440 8301 8128 8185 7202 8172 8248 8224 8141 8420 8367 8241 8178 8468 8442 8634 9202 9127 8950 10053 8204
|
||||
|
||||
--- Directory ---
|
||||
- Event Counts -
|
||||
Fetch [177695 ] 177695
|
||||
Data [95249 ] 95249
|
||||
Memory_Data [177695 ] 177695
|
||||
Memory_Ack [95249 ] 95249
|
||||
DMA_READ [0 ] 0
|
||||
DMA_WRITE [0 ] 0
|
||||
CleanReplacement [16914 ] 16914
|
||||
|
||||
- Transitions -
|
||||
I Fetch [177695 ] 177695
|
||||
I DMA_READ [0 ] 0
|
||||
I DMA_WRITE [0 ] 0
|
||||
|
||||
ID Fetch [0 ] 0
|
||||
ID Data [0 ] 0
|
||||
ID Memory_Data [0 ] 0
|
||||
ID DMA_READ [0 ] 0
|
||||
ID DMA_WRITE [0 ] 0
|
||||
|
||||
ID_W Fetch [0 ] 0
|
||||
ID_W Data [0 ] 0
|
||||
ID_W Memory_Ack [0 ] 0
|
||||
ID_W DMA_READ [0 ] 0
|
||||
ID_W DMA_WRITE [0 ] 0
|
||||
|
||||
M Data [95249 ] 95249
|
||||
M DMA_READ [0 ] 0
|
||||
M DMA_WRITE [0 ] 0
|
||||
M CleanReplacement [16914 ] 16914
|
||||
|
||||
IM Fetch [0 ] 0
|
||||
IM Data [0 ] 0
|
||||
IM Memory_Data [177695 ] 177695
|
||||
IM DMA_READ [0 ] 0
|
||||
IM DMA_WRITE [0 ] 0
|
||||
|
||||
MI Fetch [0 ] 0
|
||||
MI Data [0 ] 0
|
||||
MI Memory_Ack [95249 ] 95249
|
||||
MI DMA_READ [0 ] 0
|
||||
MI DMA_WRITE [0 ] 0
|
||||
|
||||
M_DRD Data [0 ] 0
|
||||
M_DRD DMA_READ [0 ] 0
|
||||
M_DRD DMA_WRITE [0 ] 0
|
||||
|
||||
M_DRDI Fetch [0 ] 0
|
||||
M_DRDI Data [0 ] 0
|
||||
M_DRDI Memory_Ack [0 ] 0
|
||||
M_DRDI DMA_READ [0 ] 0
|
||||
M_DRDI DMA_WRITE [0 ] 0
|
||||
|
||||
M_DWR Data [0 ] 0
|
||||
M_DWR DMA_READ [0 ] 0
|
||||
M_DWR DMA_WRITE [0 ] 0
|
||||
|
||||
M_DWRI Fetch [0 ] 0
|
||||
M_DWRI Data [0 ] 0
|
||||
M_DWRI Memory_Ack [0 ] 0
|
||||
M_DWRI DMA_READ [0 ] 0
|
||||
M_DWRI DMA_WRITE [0 ] 0
|
||||
|
||||
--- DMA ---
|
||||
- Event Counts -
|
||||
ReadRequest [0 ] 0
|
||||
WriteRequest [0 ] 0
|
||||
Data [0 ] 0
|
||||
Ack [0 ] 0
|
||||
|
||||
- Transitions -
|
||||
READY ReadRequest [0 ] 0
|
||||
READY WriteRequest [0 ] 0
|
||||
|
||||
BUSY_RD Data [0 ] 0
|
||||
|
||||
BUSY_WR Ack [0 ] 0
|
||||
|
||||
@ -0,0 +1,11 @@
|
||||
warn: Sockets disabled, not accepting terminal connections
|
||||
warn: Reading current count from inactive timer.
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: Don't know what interrupt to clear for console.
|
||||
warn: instruction 'fxsave' unimplemented
|
||||
warn: instruction 'wbinvd' unimplemented
|
||||
warn: instruction 'wbinvd' unimplemented
|
||||
hack: Assuming logical destinations are 1 << id.
|
||||
warn: Tried to clear PCI interrupt 14
|
||||
warn: Unknown mouse command 0xe1.
|
||||
hack: be nice to actually delete the event here
|
||||
@ -0,0 +1,13 @@
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jun 4 2012 13:44:12
|
||||
gem5 started Jun 4 2012 17:11:29
|
||||
gem5 executing on zizzer
|
||||
command line: build/X86_MESI_CMP_directory/gem5.opt -d build/X86_MESI_CMP_directory/tests/opt/long/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory -re tests/run.py build/X86_MESI_CMP_directory/tests/opt/long/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory
|
||||
warning: add_child('terminal'): child 'terminal' already has parent
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9.smp
|
||||
0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 5304689685500 because m5_exit instruction encountered
|
||||
@ -0,0 +1,136 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 5.304690 # Number of seconds simulated
|
||||
sim_ticks 5304689685500 # Number of ticks simulated
|
||||
final_tick 5304689685500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 163049 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 333085 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 6301127704 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 481488 # Number of bytes of host memory used
|
||||
host_seconds 841.86 # Real time elapsed on the host
|
||||
sim_insts 137264752 # Number of instructions simulated
|
||||
sim_ops 280412254 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::pc.south_bridge.ide 35144 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu0.dtb.walker 126800 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu0.itb.walker 64416 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu0.inst 827772912 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu0.data 39626426 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu1.dtb.walker 100784 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu1.itb.walker 45696 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu1.inst 470347440 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu1.data 53905938 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 1392025556 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu0.inst 827772912 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu1.inst 470347440 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 1298120352 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::pc.south_bridge.ide 2991104 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::cpu0.itb.walker 16 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::cpu0.data 32173132 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::cpu1.data 35738580 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 70902832 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::pc.south_bridge.ide 809 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu0.dtb.walker 15850 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu0.itb.walker 8052 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu0.inst 103471614 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu0.data 6642662 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu1.dtb.walker 12598 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu1.itb.walker 5712 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu1.inst 58793430 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu1.data 9050935 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 178001662 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::pc.south_bridge.ide 46736 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::cpu0.itb.walker 2 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::cpu0.data 4837067 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::cpu1.data 4982709 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 9866514 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::pc.south_bridge.ide 6625 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu0.dtb.walker 23903 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu0.itb.walker 12143 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu0.inst 156045492 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu0.data 7470074 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu1.dtb.walker 18999 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu1.itb.walker 8614 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu1.inst 88666344 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu1.data 10161940 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 262414135 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu0.inst 156045492 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu1.inst 88666344 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 244711836 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::pc.south_bridge.ide 563860 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::cpu0.itb.walker 3 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::cpu0.data 6065036 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::cpu1.data 6737167 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 13366066 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::pc.south_bridge.ide 570485 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu0.dtb.walker 23903 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu0.itb.walker 12146 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu0.inst 156045492 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu0.data 13535110 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu1.dtb.walker 18999 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu1.itb.walker 8614 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu1.inst 88666344 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu1.data 16899107 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 275780201 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
||||
system.pc.south_bridge.ide.disks0.dma_read_bytes 32768 # Number of bytes transfered via DMA reads (not PRD).
|
||||
system.pc.south_bridge.ide.disks0.dma_read_txs 30 # Number of DMA read transactions (not PRD).
|
||||
system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes.
|
||||
system.pc.south_bridge.ide.disks0.dma_write_bytes 2987008 # Number of bytes transfered via DMA writes.
|
||||
system.pc.south_bridge.ide.disks0.dma_write_txs 813 # Number of DMA write transactions.
|
||||
system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
||||
system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
|
||||
system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD).
|
||||
system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
|
||||
system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
|
||||
system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
|
||||
system.cpu0.numCycles 10608177450 # number of cpu cycles simulated
|
||||
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu0.committedInsts 88690468 # Number of instructions committed
|
||||
system.cpu0.committedOps 187060545 # Number of ops (including micro ops) committed
|
||||
system.cpu0.num_int_alu_accesses 168469813 # Number of integer alu accesses
|
||||
system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses
|
||||
system.cpu0.num_func_calls 0 # number of times a function call or return occured
|
||||
system.cpu0.num_conditional_control_insts 17923925 # number of instructions that are conditional controls
|
||||
system.cpu0.num_int_insts 168469813 # number of integer instructions
|
||||
system.cpu0.num_fp_insts 0 # number of float instructions
|
||||
system.cpu0.num_int_register_reads 517963630 # number of times the integer registers were read
|
||||
system.cpu0.num_int_register_writes 280483339 # number of times the integer registers were written
|
||||
system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read
|
||||
system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written
|
||||
system.cpu0.num_mem_refs 19132508 # number of memory refs
|
||||
system.cpu0.num_load_insts 14284566 # Number of load instructions
|
||||
system.cpu0.num_store_insts 4847942 # Number of store instructions
|
||||
system.cpu0.num_idle_cycles 10086452980.871330 # Number of idle cycles
|
||||
system.cpu0.num_busy_cycles 521724469.128670 # Number of busy cycles
|
||||
system.cpu0.not_idle_fraction 0.049181 # Percentage of non-idle cycles
|
||||
system.cpu0.idle_fraction 0.950819 # Percentage of idle cycles
|
||||
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
|
||||
system.cpu0.kern.inst.quiesce 0 # number of quiesce instructions executed
|
||||
system.cpu1.numCycles 10609379371 # number of cpu cycles simulated
|
||||
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu1.committedInsts 48574284 # Number of instructions committed
|
||||
system.cpu1.committedOps 93351709 # Number of ops (including micro ops) committed
|
||||
system.cpu1.num_int_alu_accesses 89110416 # Number of integer alu accesses
|
||||
system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses
|
||||
system.cpu1.num_func_calls 0 # number of times a function call or return occured
|
||||
system.cpu1.num_conditional_control_insts 8197841 # number of instructions that are conditional controls
|
||||
system.cpu1.num_int_insts 89110416 # number of integer instructions
|
||||
system.cpu1.num_fp_insts 0 # number of float instructions
|
||||
system.cpu1.num_int_register_reads 273178604 # number of times the integer registers were read
|
||||
system.cpu1.num_int_register_writes 138760228 # number of times the integer registers were written
|
||||
system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read
|
||||
system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written
|
||||
system.cpu1.num_mem_refs 14426742 # number of memory refs
|
||||
system.cpu1.num_load_insts 9181010 # Number of load instructions
|
||||
system.cpu1.num_store_insts 5245732 # Number of store instructions
|
||||
system.cpu1.num_idle_cycles 10273661233.326063 # Number of idle cycles
|
||||
system.cpu1.num_busy_cycles 335718137.673937 # Number of busy cycles
|
||||
system.cpu1.not_idle_fraction 0.031644 # Percentage of non-idle cycles
|
||||
system.cpu1.idle_fraction 0.968356 # Percentage of idle cycles
|
||||
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
|
||||
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
@ -0,0 +1,136 @@
|
||||
Linux version 2.6.22.9 (gblack@fajita) (gcc version 4.1.2 (Gentoo 4.1.2 p1.1)) #12 SMP Fri Feb 27 22:10:33 PST 2009
|
||||
Command line: earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1
|
||||
BIOS-provided physical RAM map:
|
||||
BIOS-e820: 0000000000000000 - 0000000000100000 (reserved)
|
||||
BIOS-e820: 0000000000100000 - 0000000008000000 (usable)
|
||||
end_pfn_map = 32768
|
||||
kernel direct mapping tables up to 8000000 @ 100000-102000
|
||||
DMI 2.5 present.
|
||||
Zone PFN ranges:
|
||||
DMA 256 -> 4096
|
||||
DMA32 4096 -> 1048576
|
||||
Normal 1048576 -> 1048576
|
||||
early_node_map[1] active PFN ranges
|
||||
0: 256 -> 32768
|
||||
Intel MultiProcessor Specification v1.4
|
||||
MPTABLE: OEM ID: MPTABLE: Product ID: MPTABLE: APIC at: 0xFEE00000
|
||||
Processor #0 (Bootup-CPU)
|
||||
Processor #1
|
||||
I/O APIC #2 at 0xFEC00000.
|
||||
Setting APIC routing to flat
|
||||
Processors: 2
|
||||
Allocating PCI resources starting at 10000000 (gap: 8000000:f8000000)
|
||||
PERCPU: Allocating 34160 bytes of per cpu data
|
||||
Built 1 zonelists. Total pages: 30461
|
||||
Kernel command line: earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1
|
||||
Initializing CPU#0
|
||||
PID hash table entries: 512 (order: 9, 4096 bytes)
|
||||
Marking TSC unstable due to TSCs unsynchronized
|
||||
time.c: Detected 1999.999 MHz processor.
|
||||
Console: colour dummy device 80x25
|
||||
console handover: boot [earlyser0] -> real [ttyS0]
|
||||
Dentry cache hash table entries: 16384 (order: 5, 131072 bytes)
|
||||
Inode-cache hash table entries: 8192 (order: 4, 65536 bytes)
|
||||
Checking aperture...
|
||||
Memory: 121384k/131072k available (3699k kernel code, 8500k reserved, 1767k data, 248k init)
|
||||
Calibrating delay loop (skipped)... 3999.96 BogoMIPS preset
|
||||
Mount-cache hash table entries: 256
|
||||
CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)
|
||||
CPU: L2 Cache: 1024K (64 bytes/line)
|
||||
Freeing SMP alternatives: 34k freed
|
||||
Using local APIC timer interrupts.
|
||||
result 7812492
|
||||
Detected 7.812 MHz APIC timer.
|
||||
Booting processor 1/2 APIC 0x1
|
||||
Initializing CPU#1
|
||||
Calibrating delay loop (skipped)... 3999.96 BogoMIPS preset
|
||||
CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)
|
||||
CPU: L2 Cache: 1024K (64 bytes/line)
|
||||
Fake M5 x86_64 CPU stepping 01
|
||||
Brought up 2 CPUs
|
||||
migration_cost=11
|
||||
NET: Registered protocol family 16
|
||||
PCI: Using configuration type 1
|
||||
SCSI subsystem initialized
|
||||
usbcore: registered new interface driver usbfs
|
||||
usbcore: registered new interface driver hub
|
||||
usbcore: registered new device driver usb
|
||||
PCI: Probing PCI hardware
|
||||
PCI-GART: No AMD northbridge found.
|
||||
NET: Registered protocol family 2
|
||||
IP route cache hash table entries: 1024 (order: 1, 8192 bytes)
|
||||
TCP established hash table entries: 4096 (order: 4, 98304 bytes)
|
||||
TCP bind hash table entries: 4096 (order: 4, 65536 bytes)
|
||||
TCP: Hash tables configured (established 4096 bind 4096)
|
||||
TCP reno registered
|
||||
Total HugeTLB memory allocated, 0
|
||||
Installing knfsd (copyright (C) 1996 okir@monad.swb.de).
|
||||
io scheduler noop registered
|
||||
io scheduler deadline registered
|
||||
io scheduler cfq registered (default)
|
||||
Real Time Clock Driver v1.12ac
|
||||
Linux agpgart interface v0.102 (c) Dave Jones
|
||||
Serial: 8250/16550 driver $Revision: 1.90 $ 4 ports, IRQ sharing disabled
|
||||
serial8250: ttyS0 at I/O 0x3f8 (irq = 4) is a 8250
|
||||
floppy0: no floppy controllers found
|
||||
RAMDISK driver initialized: 16 RAM disks of 4096K size 1024 blocksize
|
||||
loop: module loaded
|
||||
Intel(R) PRO/1000 Network Driver - version 7.3.20-k2
|
||||
Copyright (c) 1999-2006 Intel Corporation.
|
||||
e100: Intel(R) PRO/100 Network Driver, 3.5.17-k4-NAPI
|
||||
e100: Copyright(c) 1999-2006 Intel Corporation
|
||||
forcedeth.c: Reverse Engineered nForce ethernet driver. Version 0.60.
|
||||
tun: Universal TUN/TAP device driver, 1.6
|
||||
tun: (C) 1999-2004 Max Krasnyansky <maxk@qualcomm.com>
|
||||
netconsole: not configured, aborting
|
||||
Uniform Multi-Platform E-IDE driver Revision: 7.00alpha2
|
||||
ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx
|
||||
PIIX4: IDE controller at PCI slot 0000:00:04.0
|
||||
PCI: Enabling device 0000:00:04.0 (0000 -> 0001)
|
||||
PIIX4: chipset revision 0
|
||||
PIIX4: not 100% native mode: will probe irqs later
|
||||
ide0: BM-DMA at 0x1000-0x1007, BIOS settings: hda:DMA, hdb:DMA
|
||||
ide1: BM-DMA at 0x1008-0x100f, BIOS settings: hdc:DMA, hdd:DMA
|
||||
hda: M5 IDE Disk, ATA DISK drive
|
||||
hdb: M5 IDE Disk, ATA DISK drive
|
||||
ide0 at 0x1f0-0x1f7,0x3f6 on irq 14
|
||||
hda: max request size: 128KiB
|
||||
hda: 1048320 sectors (536 MB), CHS=1040/16/63, UDMA(33)
|
||||
hda: hda1
|
||||
hdb: max request size: 128KiB
|
||||
hdb: 4177920 sectors (2139 MB), CHS=4144/16/63, UDMA(33)
|
||||
hdb: unknown partition table
|
||||
megaraid cmm: 2.20.2.7 (Release Date: Sun Jul 16 00:01:03 EST 2006)
|
||||
megaraid: 2.20.5.1 (Release Date: Thu Nov 16 15:32:35 EST 2006)
|
||||
megasas: 00.00.03.10-rc5 Thu May 17 10:09:32 PDT 2007
|
||||
Fusion MPT base driver 3.04.04
|
||||
Copyright (c) 1999-2007 LSI Logic Corporation
|
||||
Fusion MPT SPI Host driver 3.04.04
|
||||
Fusion MPT SAS Host driver 3.04.04
|
||||
ieee1394: raw1394: /dev/raw1394 device initialized
|
||||
USB Universal Host Controller Interface driver v3.0
|
||||
usbcore: registered new interface driver usblp
|
||||
drivers/usb/class/usblp.c: v0.13: USB Printer Device Class driver
|
||||
Initializing USB Mass Storage driver...
|
||||
usbcore: registered new interface driver usb-storage
|
||||
USB Mass Storage support registered.
|
||||
serio: i8042 KBD port at 0x60,0x64 irq 1
|
||||
serio: i8042 AUX port at 0x60,0x64 irq 12
|
||||
mice: PS/2 mouse device common for all mice
|
||||
input: AT Translated Set 2 keyboard as /class/input/input0
|
||||
device-mapper: ioctl: 4.11.0-ioctl (2006-10-12) initialised: dm-devel@redhat.com
|
||||
usbcore: registered new interface driver usbhid
|
||||
drivers/hid/usbhid/hid-core.c: v2.6:USB HID core driver
|
||||
oprofile: using timer interrupt.
|
||||
TCP cubic registered
|
||||
NET: Registered protocol family 1
|
||||
NET: Registered protocol family 10
|
||||
IPv6 over IPv4 tunneling driver
|
||||
NET: Registered protocol family 17
|
||||
input: PS/2 Generic Mouse as /class/input/input1
|
||||
EXT2-fs warning: mounting unchecked fs, running e2fsck is recommended
|
||||
VFS: Mounted root (ext2 filesystem).
|
||||
Freeing unused kernel memory: 248k freed
|
||||
|
||||
INIT: version 2.86 booting
|
||||
|
||||
29
simulators/gem5/tests/long/fs/10.linux-boot/test.py
Normal file
29
simulators/gem5/tests/long/fs/10.linux-boot/test.py
Normal file
@ -0,0 +1,29 @@
|
||||
# Copyright (c) 2006 The Regents of The University of Michigan
|
||||
# All rights reserved.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are
|
||||
# met: redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer;
|
||||
# redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in the
|
||||
# documentation and/or other materials provided with the distribution;
|
||||
# neither the name of the copyright holders nor the names of its
|
||||
# contributors may be used to endorse or promote products derived from
|
||||
# this software without specific prior written permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
#
|
||||
# Authors: Steve Reinhardt
|
||||
|
||||
root.system.readfile = os.path.join(tests_root, 'halt.sh')
|
||||
@ -0,0 +1,484 @@
|
||||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
full_system=true
|
||||
time_sync_enable=false
|
||||
time_sync_period=200000000
|
||||
time_sync_spin_threshold=200000
|
||||
|
||||
[system]
|
||||
type=SparcSystem
|
||||
children=bridge cpu disk0 hypervisor_desc intrctrl iobus membus nvram partition_desc physmem physmem2 rom t1000
|
||||
boot_osflags=a
|
||||
hypervisor_addr=1099243257856
|
||||
hypervisor_bin=/dist/m5/system/binaries/q_new.bin
|
||||
hypervisor_desc=system.hypervisor_desc
|
||||
hypervisor_desc_addr=133446500352
|
||||
hypervisor_desc_bin=/dist/m5/system/binaries/1up-hv.bin
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
mem_mode=atomic
|
||||
memories=system.partition_desc system.rom system.hypervisor_desc system.nvram system.physmem system.physmem2
|
||||
num_work_ids=16
|
||||
nvram=system.nvram
|
||||
nvram_addr=133429198848
|
||||
nvram_bin=/dist/m5/system/binaries/nvram1
|
||||
openboot_addr=1099243716608
|
||||
openboot_bin=/dist/m5/system/binaries/openboot_new.bin
|
||||
partition_desc=system.partition_desc
|
||||
partition_desc_addr=133445976064
|
||||
partition_desc_bin=/dist/m5/system/binaries/1up-md.bin
|
||||
readfile=tests/halt.sh
|
||||
reset_addr=1099243192320
|
||||
reset_bin=/dist/m5/system/binaries/reset_new.bin
|
||||
rom=system.rom
|
||||
symbolfile=
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.membus.slave[0]
|
||||
|
||||
[system.bridge]
|
||||
type=Bridge
|
||||
delay=100
|
||||
nack_delay=8
|
||||
ranges=133412421632:133412421639 134217728000:554050781183 644245094400:652835028991 725849473024:1095485095935 1099255955456:1099255955463
|
||||
req_size=16
|
||||
resp_size=16
|
||||
write_ack=false
|
||||
master=system.iobus.slave[0]
|
||||
slave=system.membus.master[2]
|
||||
|
||||
[system.cpu]
|
||||
type=AtomicSimpleCPU
|
||||
children=dtb interrupts itb tracer
|
||||
checker=Null
|
||||
clock=1
|
||||
cpu_id=0
|
||||
defer_registration=false
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
fastmem=false
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
interrupts=system.cpu.interrupts
|
||||
itb=system.cpu.itb
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
phase=0
|
||||
profile=0
|
||||
progress_interval=0
|
||||
simulate_data_stalls=false
|
||||
simulate_inst_stalls=false
|
||||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
width=1
|
||||
workload=
|
||||
dcache_port=system.membus.slave[2]
|
||||
icache_port=system.membus.slave[1]
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=SparcTLB
|
||||
size=64
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=SparcInterrupts
|
||||
|
||||
[system.cpu.itb]
|
||||
type=SparcTLB
|
||||
size=64
|
||||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
|
||||
[system.disk0]
|
||||
type=MmDisk
|
||||
children=image
|
||||
image=system.disk0.image
|
||||
pio_addr=134217728000
|
||||
pio_latency=2
|
||||
system=system
|
||||
pio=system.iobus.master[14]
|
||||
|
||||
[system.disk0.image]
|
||||
type=CowDiskImage
|
||||
children=child
|
||||
child=system.disk0.image.child
|
||||
image_file=
|
||||
read_only=false
|
||||
table_size=65536
|
||||
|
||||
[system.disk0.image.child]
|
||||
type=RawDiskImage
|
||||
image_file=/dist/m5/system/disks/disk.s10hw2
|
||||
read_only=true
|
||||
|
||||
[system.hypervisor_desc]
|
||||
type=SimpleMemory
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=60
|
||||
latency_var=0
|
||||
null=false
|
||||
range=133446500352:133446508543
|
||||
zero=false
|
||||
port=system.membus.master[7]
|
||||
|
||||
[system.intrctrl]
|
||||
type=IntrControl
|
||||
sys=system
|
||||
|
||||
[system.iobus]
|
||||
type=NoncoherentBus
|
||||
block_size=64
|
||||
clock=2
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
master=system.t1000.fake_clk.pio system.t1000.fake_membnks.pio system.t1000.fake_l2_1.pio system.t1000.fake_l2_2.pio system.t1000.fake_l2_3.pio system.t1000.fake_l2_4.pio system.t1000.fake_l2esr_1.pio system.t1000.fake_l2esr_2.pio system.t1000.fake_l2esr_3.pio system.t1000.fake_l2esr_4.pio system.t1000.fake_ssi.pio system.t1000.fake_jbi.pio system.t1000.puart0.pio system.t1000.hvuart.pio system.disk0.pio
|
||||
slave=system.bridge.master
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
children=badaddr_responder
|
||||
block_size=64
|
||||
clock=2
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
default=system.membus.badaddr_responder.pio
|
||||
master=system.t1000.iob.pio system.t1000.htod.pio system.bridge.slave system.physmem.port[0] system.physmem2.port[0] system.rom.port[0] system.nvram.port[0] system.hypervisor_desc.port[0] system.partition_desc.port[0]
|
||||
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
|
||||
|
||||
[system.membus.badaddr_responder]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=0
|
||||
pio_latency=2
|
||||
pio_size=8
|
||||
ret_bad_addr=true
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.membus.default
|
||||
|
||||
[system.nvram]
|
||||
type=SimpleMemory
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=60
|
||||
latency_var=0
|
||||
null=false
|
||||
range=133429198848:133429207039
|
||||
zero=false
|
||||
port=system.membus.master[6]
|
||||
|
||||
[system.partition_desc]
|
||||
type=SimpleMemory
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=60
|
||||
latency_var=0
|
||||
null=false
|
||||
range=133445976064:133445984255
|
||||
zero=false
|
||||
port=system.membus.master[8]
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=60
|
||||
latency_var=0
|
||||
null=false
|
||||
range=1048576:68157439
|
||||
zero=true
|
||||
port=system.membus.master[3]
|
||||
|
||||
[system.physmem2]
|
||||
type=SimpleMemory
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=60
|
||||
latency_var=0
|
||||
null=false
|
||||
range=2147483648:2415919103
|
||||
zero=true
|
||||
port=system.membus.master[4]
|
||||
|
||||
[system.rom]
|
||||
type=SimpleMemory
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=60
|
||||
latency_var=0
|
||||
null=false
|
||||
range=1099243192320:1099251580927
|
||||
zero=false
|
||||
port=system.membus.master[5]
|
||||
|
||||
[system.t1000]
|
||||
type=T1000
|
||||
children=fake_clk fake_jbi fake_l2_1 fake_l2_2 fake_l2_3 fake_l2_4 fake_l2esr_1 fake_l2esr_2 fake_l2esr_3 fake_l2esr_4 fake_membnks fake_ssi hterm htod hvuart iob pterm puart0
|
||||
intrctrl=system.intrctrl
|
||||
system=system
|
||||
|
||||
[system.t1000.fake_clk]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=644245094400
|
||||
pio_latency=2
|
||||
pio_size=4294967296
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[0]
|
||||
|
||||
[system.t1000.fake_jbi]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=549755813888
|
||||
pio_latency=2
|
||||
pio_size=4294967296
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[11]
|
||||
|
||||
[system.t1000.fake_l2_1]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=725849473024
|
||||
pio_latency=2
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=1
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=true
|
||||
warn_access=
|
||||
pio=system.iobus.master[2]
|
||||
|
||||
[system.t1000.fake_l2_2]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=725849473088
|
||||
pio_latency=2
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=1
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=true
|
||||
warn_access=
|
||||
pio=system.iobus.master[3]
|
||||
|
||||
[system.t1000.fake_l2_3]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=725849473152
|
||||
pio_latency=2
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=1
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=true
|
||||
warn_access=
|
||||
pio=system.iobus.master[4]
|
||||
|
||||
[system.t1000.fake_l2_4]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=725849473216
|
||||
pio_latency=2
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=1
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=true
|
||||
warn_access=
|
||||
pio=system.iobus.master[5]
|
||||
|
||||
[system.t1000.fake_l2esr_1]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=734439407616
|
||||
pio_latency=2
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=0
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=true
|
||||
warn_access=
|
||||
pio=system.iobus.master[6]
|
||||
|
||||
[system.t1000.fake_l2esr_2]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=734439407680
|
||||
pio_latency=2
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=0
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=true
|
||||
warn_access=
|
||||
pio=system.iobus.master[7]
|
||||
|
||||
[system.t1000.fake_l2esr_3]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=734439407744
|
||||
pio_latency=2
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=0
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=true
|
||||
warn_access=
|
||||
pio=system.iobus.master[8]
|
||||
|
||||
[system.t1000.fake_l2esr_4]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=734439407808
|
||||
pio_latency=2
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=0
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=true
|
||||
warn_access=
|
||||
pio=system.iobus.master[9]
|
||||
|
||||
[system.t1000.fake_membnks]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=648540061696
|
||||
pio_latency=2
|
||||
pio_size=16384
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=0
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[1]
|
||||
|
||||
[system.t1000.fake_ssi]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=1095216660480
|
||||
pio_latency=2
|
||||
pio_size=268435456
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[10]
|
||||
|
||||
[system.t1000.hterm]
|
||||
type=Terminal
|
||||
intr_control=system.intrctrl
|
||||
number=0
|
||||
output=true
|
||||
port=3456
|
||||
|
||||
[system.t1000.htod]
|
||||
type=DumbTOD
|
||||
pio_addr=1099255906296
|
||||
pio_latency=2
|
||||
system=system
|
||||
time=Thu Jan 1 00:00:00 2009
|
||||
pio=system.membus.master[1]
|
||||
|
||||
[system.t1000.hvuart]
|
||||
type=Uart8250
|
||||
pio_addr=1099255955456
|
||||
pio_latency=2
|
||||
platform=system.t1000
|
||||
system=system
|
||||
terminal=system.t1000.hterm
|
||||
pio=system.iobus.master[13]
|
||||
|
||||
[system.t1000.iob]
|
||||
type=Iob
|
||||
pio_latency=2
|
||||
platform=system.t1000
|
||||
system=system
|
||||
pio=system.membus.master[0]
|
||||
|
||||
[system.t1000.pterm]
|
||||
type=Terminal
|
||||
intr_control=system.intrctrl
|
||||
number=0
|
||||
output=true
|
||||
port=3456
|
||||
|
||||
[system.t1000.puart0]
|
||||
type=Uart8250
|
||||
pio_addr=133412421632
|
||||
pio_latency=2
|
||||
platform=system.t1000
|
||||
system=system
|
||||
terminal=system.t1000.pterm
|
||||
pio=system.iobus.master[12]
|
||||
|
||||
@ -0,0 +1,5 @@
|
||||
warn: Sockets disabled, not accepting terminal connections
|
||||
warn: CoherentBus system.membus has no snooping ports attached!
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: Don't know what interrupt to clear for console.
|
||||
hack: be nice to actually delete the event here
|
||||
@ -0,0 +1,16 @@
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jun 4 2012 12:01:47
|
||||
gem5 started Jun 4 2012 15:02:47
|
||||
gem5 executing on zizzer
|
||||
command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/fs/80.solaris-boot/sparc/solaris/t1000-simple-atomic -re tests/run.py build/SPARC/tests/opt/long/fs/80.solaris-boot/sparc/solaris/t1000-simple-atomic
|
||||
Global frequency set at 2000000000 ticks per second
|
||||
info: No kernel set for full system simulation. Assuming you know what you're doing if not SPARC ISA
|
||||
0: system.t1000.htod: Real-time clock set to Thu Jan 1 00:00:00 2009
|
||||
|
||||
0: system.t1000.htod: Real-time clock set to 1230768000
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Ignoring write to SPARC ERROR regsiter
|
||||
info: Ignoring write to SPARC ERROR regsiter
|
||||
Exiting @ tick 2233777512 because m5_exit instruction encountered
|
||||
@ -0,0 +1,133 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 1.116889 # Number of seconds simulated
|
||||
sim_ticks 2233777512 # Number of ticks simulated
|
||||
final_tick 2233777512 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 2000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 3140005 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 3141240 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 3147745 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 511524 # Number of bytes of host memory used
|
||||
host_seconds 709.64 # Real time elapsed on the host
|
||||
sim_insts 2228284650 # Number of instructions simulated
|
||||
sim_ops 2229160714 # Number of ops (including micro ops) simulated
|
||||
system.hypervisor_desc.bytes_read::cpu.data 16792 # Number of bytes read from this memory
|
||||
system.hypervisor_desc.bytes_read::total 16792 # Number of bytes read from this memory
|
||||
system.hypervisor_desc.num_reads::cpu.data 9024 # Number of read requests responded to by this memory
|
||||
system.hypervisor_desc.num_reads::total 9024 # Number of read requests responded to by this memory
|
||||
system.hypervisor_desc.bw_read::cpu.data 15035 # Total read bandwidth from this memory (bytes/s)
|
||||
system.hypervisor_desc.bw_read::total 15035 # Total read bandwidth from this memory (bytes/s)
|
||||
system.hypervisor_desc.bw_total::cpu.data 15035 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.hypervisor_desc.bw_total::total 15035 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.partition_desc.bytes_read::cpu.data 4846 # Number of bytes read from this memory
|
||||
system.partition_desc.bytes_read::total 4846 # Number of bytes read from this memory
|
||||
system.partition_desc.num_reads::cpu.data 608 # Number of read requests responded to by this memory
|
||||
system.partition_desc.num_reads::total 608 # Number of read requests responded to by this memory
|
||||
system.partition_desc.bw_read::cpu.data 4339 # Total read bandwidth from this memory (bytes/s)
|
||||
system.partition_desc.bw_read::total 4339 # Total read bandwidth from this memory (bytes/s)
|
||||
system.partition_desc.bw_total::cpu.data 4339 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.partition_desc.bw_total::total 4339 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.rom.bytes_read::cpu.inst 432296 # Number of bytes read from this memory
|
||||
system.rom.bytes_read::cpu.data 696392 # Number of bytes read from this memory
|
||||
system.rom.bytes_read::total 1128688 # Number of bytes read from this memory
|
||||
system.rom.bytes_inst_read::cpu.inst 432296 # Number of instructions bytes read from this memory
|
||||
system.rom.bytes_inst_read::total 432296 # Number of instructions bytes read from this memory
|
||||
system.rom.num_reads::cpu.inst 108074 # Number of read requests responded to by this memory
|
||||
system.rom.num_reads::cpu.data 87049 # Number of read requests responded to by this memory
|
||||
system.rom.num_reads::total 195123 # Number of read requests responded to by this memory
|
||||
system.rom.bw_read::cpu.inst 387054 # Total read bandwidth from this memory (bytes/s)
|
||||
system.rom.bw_read::cpu.data 623511 # Total read bandwidth from this memory (bytes/s)
|
||||
system.rom.bw_read::total 1010564 # Total read bandwidth from this memory (bytes/s)
|
||||
system.rom.bw_inst_read::cpu.inst 387054 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.rom.bw_inst_read::total 387054 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.rom.bw_total::cpu.inst 387054 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.rom.bw_total::cpu.data 623511 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.rom.bw_total::total 1010564 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.nvram.bytes_read::cpu.data 284 # Number of bytes read from this memory
|
||||
system.nvram.bytes_read::total 284 # Number of bytes read from this memory
|
||||
system.nvram.bytes_written::cpu.data 92 # Number of bytes written to this memory
|
||||
system.nvram.bytes_written::total 92 # Number of bytes written to this memory
|
||||
system.nvram.num_reads::cpu.data 284 # Number of read requests responded to by this memory
|
||||
system.nvram.num_reads::total 284 # Number of read requests responded to by this memory
|
||||
system.nvram.num_writes::cpu.data 92 # Number of write requests responded to by this memory
|
||||
system.nvram.num_writes::total 92 # Number of write requests responded to by this memory
|
||||
system.nvram.bw_read::cpu.data 254 # Total read bandwidth from this memory (bytes/s)
|
||||
system.nvram.bw_read::total 254 # Total read bandwidth from this memory (bytes/s)
|
||||
system.nvram.bw_write::cpu.data 82 # Write bandwidth from this memory (bytes/s)
|
||||
system.nvram.bw_write::total 82 # Write bandwidth from this memory (bytes/s)
|
||||
system.nvram.bw_total::cpu.data 337 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.nvram.bw_total::total 337 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bytes_read::cpu.inst 612291324 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 97534024 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 709825348 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 612291324 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 612291324 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::cpu.data 15400223 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 15400223 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 153072831 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 12152054 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 165224885 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::cpu.data 1927067 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 1927067 # Number of write requests responded to by this memory
|
||||
system.physmem.num_other::cpu.data 14 # Number of other requests responded to by this memory
|
||||
system.physmem.num_other::total 14 # Number of other requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 548211557 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 87326534 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 635538091 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 548211557 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 548211557 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::cpu.data 13788502 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 13788502 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 548211557 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 101115036 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 649326593 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem2.bytes_read::cpu.inst 8318106840 # Number of bytes read from this memory
|
||||
system.physmem2.bytes_read::cpu.data 1495885127 # Number of bytes read from this memory
|
||||
system.physmem2.bytes_read::total 9813991967 # Number of bytes read from this memory
|
||||
system.physmem2.bytes_inst_read::cpu.inst 8318106840 # Number of instructions bytes read from this memory
|
||||
system.physmem2.bytes_inst_read::total 8318106840 # Number of instructions bytes read from this memory
|
||||
system.physmem2.bytes_written::cpu.data 897268422 # Number of bytes written to this memory
|
||||
system.physmem2.bytes_written::total 897268422 # Number of bytes written to this memory
|
||||
system.physmem2.num_reads::cpu.inst 2079526710 # Number of read requests responded to by this memory
|
||||
system.physmem2.num_reads::cpu.data 323962420 # Number of read requests responded to by this memory
|
||||
system.physmem2.num_reads::total 2403489130 # Number of read requests responded to by this memory
|
||||
system.physmem2.num_writes::cpu.data 187387796 # Number of write requests responded to by this memory
|
||||
system.physmem2.num_writes::total 187387796 # Number of write requests responded to by this memory
|
||||
system.physmem2.num_other::cpu.data 5403067 # Number of other requests responded to by this memory
|
||||
system.physmem2.num_other::total 5403067 # Number of other requests responded to by this memory
|
||||
system.physmem2.bw_read::cpu.inst 7447569684 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem2.bw_read::cpu.data 1339332247 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem2.bw_read::total 8786901931 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem2.bw_inst_read::cpu.inst 7447569684 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem2.bw_inst_read::total 7447569684 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem2.bw_write::cpu.data 803364182 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem2.bw_write::total 803364182 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem2.bw_total::cpu.inst 7447569684 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem2.bw_total::cpu.data 2142696429 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem2.bw_total::total 9590266113 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu.numCycles 2233777513 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 2228284650 # Number of instructions committed
|
||||
system.cpu.committedOps 2229160714 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 1839325658 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 14608322 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 44037246 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 316367761 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 1839325658 # number of integer instructions
|
||||
system.cpu.num_fp_insts 14608322 # number of float instructions
|
||||
system.cpu.num_int_register_reads 4305540407 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 2100562807 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 35401841 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 22917558 # number of times the floating registers were written
|
||||
system.cpu.num_mem_refs 547951940 # number of memory refs
|
||||
system.cpu.num_load_insts 349807670 # Number of load instructions
|
||||
system.cpu.num_store_insts 198144270 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 2233777513 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
||||
system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
@ -0,0 +1,48 @@
|
||||
cpu
|
||||
|
||||
Sun Fire T2000, No Keyboard
|
||||
Copyright 2006 Sun Microsystems, Inc. All rights reserved.
|
||||
OpenBoot 4.23.0, 256 MB memory available, Serial #1122867.
|
||||
[saidi obp #30]
|
||||
Ethernet address 0:80:3:de:ad:3, Host ID: 80112233.
|
||||
|
||||
|
||||
|
||||
Boot device: /virtual-devices/disk@0 File and args: -vV
|
||||
Loading ufs-file-system package 1.4 04 Aug 1995 13:02:54.
|
||||
FCode UFS Reader 1.12 00/07/17 15:48:16.
|
||||
Loading: /platform/SUNW,Sun-Fire-T2000/ufsboot
|
||||
Loading: /platform/sun4v/ufsboot
|
||||
device path '/virtual-devices@100/disk@0:a'
|
||||
The boot filesystem is logging.
|
||||
The ufs log is empty and will not be used.
|
||||
standalone = `kernel/sparcv9/unix', args = `-v'
|
||||
|Elf64 client
|
||||
Size: /-\|/-\|0x76e40+/-\|/-\|/-\|/-\0x1c872+|/-\0x3123a Bytes
|
||||
modpath: /platform/sun4v/kernel /kernel /usr/kernel
|
||||
|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-module /platform/sun4v/kernel/sparcv9/unix: text at [0x1000000, 0x1076e3f] data at 0x1800000
|
||||
module misc/sparcv9/krtld: text at [0x1076e40, 0x108f737] data at 0x184dab0
|
||||
module /platform/sun4v/kernel/sparcv9/genunix: text at [0x108f738, 0x11dd437] data at 0x18531c0
|
||||
module /platform/sun4v/kernel/misc/sparcv9/platmod: text at [0x11dd438, 0x11dd43f] data at 0x18a4be0
|
||||
module /platform/sun4v/kernel/cpu/sparcv9/SUNW,UltraSPARC-T1: text at [0x11dd440, 0x11e06ff] data at 0x18a5300
|
||||
\
|
||||
SunOS Release 5.10 Version Generic_118822-23 64-bit
|
||||
Copyright 1983-2005 Sun Microsystems, Inc. All rights reserved.
|
||||
Use is subject to license terms.
|
||||
|/-\|/-\|/-\|/-\|/-Ethernet address = 0:80:3:de:ad:3
|
||||
\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/mem = 262144K (0x10000000)
|
||||
avail mem = 237879296
|
||||
root nexus = Sun Fire T2000
|
||||
pseudo0 at root
|
||||
pseudo0 is /pseudo
|
||||
scsi_vhci0 at root
|
||||
scsi_vhci0 is /scsi_vhci
|
||||
virtual-device: hsimd0
|
||||
hsimd0 is /virtual-devices@100/disk@0
|
||||
root on /virtual-devices@100/disk@0:a fstype ufs
|
||||
pseudo-device: dld0
|
||||
dld0 is /pseudo/dld@0
|
||||
cpu0: UltraSPARC-T1 (cpuid 0 clock 5 MHz)
|
||||
iscsi0 at root
|
||||
iscsi0 is /iscsi
|
||||
Hostname: unknown
|
||||
29
simulators/gem5/tests/long/fs/80.solaris-boot/test.py
Normal file
29
simulators/gem5/tests/long/fs/80.solaris-boot/test.py
Normal file
@ -0,0 +1,29 @@
|
||||
# Copyright (c) 2007 The Regents of The University of Michigan
|
||||
# All rights reserved.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are
|
||||
# met: redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer;
|
||||
# redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in the
|
||||
# documentation and/or other materials provided with the distribution;
|
||||
# neither the name of the copyright holders nor the names of its
|
||||
# contributors may be used to endorse or promote products derived from
|
||||
# this software without specific prior written permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
#
|
||||
# Authors: Ali Saidi
|
||||
|
||||
root.system.readfile = os.path.join(tests_root, 'halt.sh')
|
||||
@ -0,0 +1,231 @@
|
||||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
full_system=false
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
||||
[system]
|
||||
type=System
|
||||
children=cpu membus physmem
|
||||
boot_osflags=a
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
mem_mode=atomic
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
readfile=
|
||||
symbolfile=
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.membus.slave[0]
|
||||
|
||||
[system.cpu]
|
||||
type=InOrderCPU
|
||||
children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
|
||||
BTBEntries=4096
|
||||
BTBTagSize=16
|
||||
RASSize=16
|
||||
activity=0
|
||||
cachePorts=2
|
||||
checker=Null
|
||||
choiceCtrBits=2
|
||||
choicePredictorSize=8192
|
||||
clock=500
|
||||
cpu_id=0
|
||||
defer_registration=false
|
||||
div16Latency=1
|
||||
div16RepeatRate=1
|
||||
div24Latency=1
|
||||
div24RepeatRate=1
|
||||
div32Latency=1
|
||||
div32RepeatRate=1
|
||||
div8Latency=1
|
||||
div8RepeatRate=1
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
fetchBuffSize=4
|
||||
functionTrace=false
|
||||
functionTraceStart=0
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
globalCtrBits=2
|
||||
globalHistoryBits=13
|
||||
globalPredictorSize=8192
|
||||
instShiftAmt=2
|
||||
interrupts=system.cpu.interrupts
|
||||
itb=system.cpu.itb
|
||||
localCtrBits=2
|
||||
localHistoryBits=11
|
||||
localHistoryTableSize=2048
|
||||
localPredictorSize=2048
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
memBlockSize=64
|
||||
multLatency=1
|
||||
multRepeatRate=1
|
||||
numThreads=1
|
||||
phase=0
|
||||
predType=tournament
|
||||
profile=0
|
||||
progress_interval=0
|
||||
stageTracing=false
|
||||
stageWidth=4
|
||||
system=system
|
||||
threadModel=SMT
|
||||
tracer=system.cpu.tracer
|
||||
workload=system.cpu.workload
|
||||
dcache_port=system.cpu.dcache.cpu_side
|
||||
icache_port=system.cpu.icache.cpu_side
|
||||
|
||||
[system.cpu.dcache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=262144
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.dcache_port
|
||||
mem_side=system.cpu.toL2Bus.slave[1]
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=AlphaTLB
|
||||
size=64
|
||||
|
||||
[system.cpu.icache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=131072
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.icache_port
|
||||
mem_side=system.cpu.toL2Bus.slave[0]
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=AlphaInterrupts
|
||||
|
||||
[system.cpu.itb]
|
||||
type=AlphaTLB
|
||||
size=48
|
||||
|
||||
[system.cpu.l2cache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=false
|
||||
latency=10000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=2097152
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.toL2Bus.master[0]
|
||||
mem_side=system.membus.slave[1]
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
master=system.cpu.l2cache.cpu_side
|
||||
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
|
||||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
|
||||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=gzip input.log 1
|
||||
cwd=build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/inorder-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
ppid=99
|
||||
simpoint=0
|
||||
system=system
|
||||
uid=100
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
master=system.physmem.port[0]
|
||||
slave=system.system_port system.cpu.l2cache.mem_side
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.membus.master[0]
|
||||
|
||||
@ -0,0 +1,6 @@
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: Prefetch instructions in Alpha do not do anything
|
||||
warn: Prefetch instructions in Alpha do not do anything
|
||||
warn: Prefetch instructions in Alpha do not do anything
|
||||
warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
|
||||
hack: be nice to actually delete the event here
|
||||
42
simulators/gem5/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simout
Executable file
42
simulators/gem5/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simout
Executable file
@ -0,0 +1,42 @@
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jun 4 2012 11:50:11
|
||||
gem5 started Jun 4 2012 13:43:43
|
||||
gem5 executing on zizzer
|
||||
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/inorder-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
spec_init
|
||||
Loading Input Data
|
||||
Duplicating 262144 bytes
|
||||
Duplicating 524288 bytes
|
||||
Input data 1048576 bytes in length
|
||||
Compressing Input Data, level 1
|
||||
Compressed data 108074 bytes in length
|
||||
Uncompressing Data
|
||||
Uncompressed data 1048576 bytes in length
|
||||
Uncompressed data compared correctly
|
||||
Compressing Input Data, level 3
|
||||
Compressed data 97831 bytes in length
|
||||
Uncompressing Data
|
||||
Uncompressed data 1048576 bytes in length
|
||||
Uncompressed data compared correctly
|
||||
Compressing Input Data, level 5
|
||||
Compressed data 83382 bytes in length
|
||||
Uncompressing Data
|
||||
Uncompressed data 1048576 bytes in length
|
||||
Uncompressed data compared correctly
|
||||
Compressing Input Data, level 7
|
||||
Compressed data 76606 bytes in length
|
||||
Uncompressing Data
|
||||
Uncompressed data 1048576 bytes in length
|
||||
Uncompressed data compared correctly
|
||||
Compressing Input Data, level 9
|
||||
Compressed data 73189 bytes in length
|
||||
Uncompressing Data
|
||||
Uncompressed data 1048576 bytes in length
|
||||
Uncompressed data compared correctly
|
||||
Tested 1MB buffer: OK!
|
||||
Exiting @ tick 274300226500 because target called exit()
|
||||
@ -0,0 +1,466 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.274300 # Number of seconds simulated
|
||||
sim_ticks 274300226500 # Number of ticks simulated
|
||||
final_tick 274300226500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 112537 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 112537 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 51289289 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 215256 # Number of bytes of host memory used
|
||||
host_seconds 5348.10 # Real time elapsed on the host
|
||||
sim_insts 601856964 # Number of instructions simulated
|
||||
sim_ops 601856964 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 54720 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 5839360 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 5894080 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 54720 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 54720 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 3798144 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 3798144 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 855 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 91240 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 92095 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 59346 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 59346 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 199489 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 21288207 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 21487696 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 199489 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 199489 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 13846667 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 13846667 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 13846667 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 199489 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 21288207 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 35334364 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
||||
system.cpu.dtb.read_hits 114517577 # DTB read hits
|
||||
system.cpu.dtb.read_misses 2631 # DTB read misses
|
||||
system.cpu.dtb.read_acv 0 # DTB read access violations
|
||||
system.cpu.dtb.read_accesses 114520208 # DTB read accesses
|
||||
system.cpu.dtb.write_hits 39666608 # DTB write hits
|
||||
system.cpu.dtb.write_misses 2302 # DTB write misses
|
||||
system.cpu.dtb.write_acv 0 # DTB write access violations
|
||||
system.cpu.dtb.write_accesses 39668910 # DTB write accesses
|
||||
system.cpu.dtb.data_hits 154184185 # DTB hits
|
||||
system.cpu.dtb.data_misses 4933 # DTB misses
|
||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
||||
system.cpu.dtb.data_accesses 154189118 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 25020502 # ITB hits
|
||||
system.cpu.itb.fetch_misses 22 # ITB misses
|
||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
||||
system.cpu.itb.fetch_accesses 25020524 # ITB accesses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.itb.write_hits 0 # DTB write hits
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.itb.write_acv 0 # DTB write access violations
|
||||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.itb.data_hits 0 # DTB hits
|
||||
system.cpu.itb.data_misses 0 # DTB misses
|
||||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 17 # Number of system calls
|
||||
system.cpu.numCycles 548600454 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.branch_predictor.lookups 86318297 # Number of BP lookups
|
||||
system.cpu.branch_predictor.condPredicted 81372201 # Number of conditional branches predicted
|
||||
system.cpu.branch_predictor.condIncorrect 36359139 # Number of conditional branches incorrect
|
||||
system.cpu.branch_predictor.BTBLookups 52872243 # Number of BTB lookups
|
||||
system.cpu.branch_predictor.BTBHits 34320184 # Number of BTB hits
|
||||
system.cpu.branch_predictor.usedRAS 1197609 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branch_predictor.RASInCorrect 6 # Number of incorrect RAS predictions.
|
||||
system.cpu.branch_predictor.BTBHitPct 64.911534 # BTB Hit Percentage
|
||||
system.cpu.branch_predictor.predictedTaken 36897167 # Number of Branches Predicted As Taken (True).
|
||||
system.cpu.branch_predictor.predictedNotTaken 49421130 # Number of Branches Predicted As Not Taken (False).
|
||||
system.cpu.regfile_manager.intRegFileReads 541659172 # Number of Reads from Int. Register File
|
||||
system.cpu.regfile_manager.intRegFileWrites 463854846 # Number of Writes to Int. Register File
|
||||
system.cpu.regfile_manager.intRegFileAccesses 1005514018 # Total Accesses (Read+Write) to the Int. Register File
|
||||
system.cpu.regfile_manager.floatRegFileReads 161 # Number of Reads from FP Register File
|
||||
system.cpu.regfile_manager.floatRegFileWrites 42 # Number of Writes to FP Register File
|
||||
system.cpu.regfile_manager.floatRegFileAccesses 203 # Total Accesses (Read+Write) to the FP Register File
|
||||
system.cpu.regfile_manager.regForwards 254972528 # Number of Registers Read Through Forwarding Logic
|
||||
system.cpu.agen_unit.agens 155051949 # Number of Address Generations
|
||||
system.cpu.execution_unit.predictedTakenIncorrect 33760596 # Number of Branches Incorrectly Predicted As Taken.
|
||||
system.cpu.execution_unit.predictedNotTakenIncorrect 2593556 # Number of Branches Incorrectly Predicted As Not Taken).
|
||||
system.cpu.execution_unit.mispredicted 36354152 # Number of Branches Incorrectly Predicted
|
||||
system.cpu.execution_unit.predicted 26193756 # Number of Branches Incorrectly Predicted
|
||||
system.cpu.execution_unit.mispredictPct 58.122091 # Percentage of Incorrect Branches Predicts
|
||||
system.cpu.execution_unit.executions 412334574 # Number of Instructions Executed.
|
||||
system.cpu.mult_div_unit.multiplies 6482 # Number of Multipy Operations Executed
|
||||
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
|
||||
system.cpu.contextSwitches 1 # Number of context switches
|
||||
system.cpu.threadCycles 538371184 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
|
||||
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
|
||||
system.cpu.timesIdled 412150 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 59439534 # Number of cycles cpu's stages were not processed
|
||||
system.cpu.runCycles 489160920 # Number of cycles cpu stages are processed.
|
||||
system.cpu.activity 89.165242 # Percentage of cycles cpu is active
|
||||
system.cpu.comLoads 114514042 # Number of Load instructions committed
|
||||
system.cpu.comStores 39451321 # Number of Store instructions committed
|
||||
system.cpu.comBranches 62547159 # Number of Branches instructions committed
|
||||
system.cpu.comNops 36304520 # Number of Nop instructions committed
|
||||
system.cpu.comNonSpec 17 # Number of Non-Speculative instructions committed
|
||||
system.cpu.comInts 349039879 # Number of Integer instructions committed
|
||||
system.cpu.comFloats 24 # Number of Floating Point instructions committed
|
||||
system.cpu.committedInsts 601856964 # Number of Instructions committed (Per-Thread)
|
||||
system.cpu.committedOps 601856964 # Number of Ops committed (Per-Thread)
|
||||
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
|
||||
system.cpu.committedInsts_total 601856964 # Number of Instructions committed (Total)
|
||||
system.cpu.cpi 0.911513 # CPI: Cycles Per Instruction (Per-Thread)
|
||||
system.cpu.smt_cpi nan # CPI: Total SMT-CPI
|
||||
system.cpu.cpi_total 0.911513 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 1.097077 # IPC: Instructions Per Cycle (Per-Thread)
|
||||
system.cpu.smt_ipc nan # IPC: Total SMT-IPC
|
||||
system.cpu.ipc_total 1.097077 # IPC: Total IPC of All Threads
|
||||
system.cpu.stage0.idleCycles 209725198 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage0.runCycles 338875256 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage0.utilization 61.770867 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage1.idleCycles 237724577 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage1.runCycles 310875877 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage1.utilization 56.667083 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage2.idleCycles 206774969 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage2.runCycles 341825485 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage2.utilization 62.308641 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage3.idleCycles 437071966 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage3.runCycles 111528488 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage3.utilization 20.329638 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage4.idleCycles 201598142 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage4.runCycles 347002312 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage4.utilization 63.252283 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.icache.replacements 30 # number of replacements
|
||||
system.cpu.icache.tagsinuse 728.232127 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 25019479 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 855 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 29262.548538 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 728.232127 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.355582 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.355582 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 25019479 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 25019479 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 25019479 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 25019479 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 25019479 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 25019479 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 1021 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 1021 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 1021 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 1021 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 1021 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 1021 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 56709500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 56709500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 56709500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 56709500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 56709500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 56709500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 25020500 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 25020500 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 25020500 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 25020500 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 25020500 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 25020500 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000041 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.000041 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000041 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.000041 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000041 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000041 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55543.095005 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 55543.095005 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 55543.095005 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 55543.095005 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 55543.095005 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 55543.095005 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 87500 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets 29166.666667 # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 166 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::total 166 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::cpu.inst 166 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::total 166 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::cpu.inst 166 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::total 166 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 855 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 855 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 855 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 855 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 855 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 855 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 45765000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 45765000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 45765000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 45765000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 45765000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 45765000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000034 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000034 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000034 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53526.315789 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53526.315789 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53526.315789 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 53526.315789 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53526.315789 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 53526.315789 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 451299 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 4094.124914 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 152394215 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 334.641827 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 267632000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 4094.124914 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.999542 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.999542 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 114120509 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 114120509 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 38273706 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 38273706 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 152394215 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 152394215 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 152394215 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 152394215 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 393533 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 393533 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 1177615 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 1177615 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 1571148 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 1571148 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 1571148 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 1571148 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 8150462000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 8150462000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 25247540000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 25247540000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 33398002000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 33398002000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 33398002000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 33398002000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 114514042 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 114514042 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 39451321 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 39451321 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 153965363 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 153965363 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 153965363 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 153965363 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003437 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.003437 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029850 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.029850 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.010205 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.010205 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.010205 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.010205 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20711.000094 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 20711.000094 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 21439.553674 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 21439.553674 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 21257.069353 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 21257.069353 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 21257.069353 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 21257.069353 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 12006000 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 3424818500 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 2777 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 216268 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 4323.370544 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets 15835.992842 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 408190 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 408190 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 192301 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 192301 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 923452 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 923452 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 1115753 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 1115753 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 1115753 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 1115753 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 201232 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 201232 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 254163 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 254163 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 455395 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 455395 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 455395 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 455395 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3562095500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 3562095500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5466864500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 5466864500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9028960000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 9028960000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9028960000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 9028960000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001757 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001757 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006442 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006442 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.002958 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.002958 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17701.436650 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17701.436650 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 21509.285380 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 21509.285380 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19826.655980 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 19826.655980 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19826.655980 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 19826.655980 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 73798 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 17696.811171 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 445686 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 89684 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 4.969515 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::writebacks 16057.614667 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 28.392088 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 1610.804416 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.490040 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.000866 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.049158 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.540064 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 170049 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 170049 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 408190 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 408190 # number of Writeback hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 194106 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 194106 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 364155 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 364155 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 364155 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 364155 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 855 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.data 31164 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 32019 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 60076 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 60076 # number of ReadExReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 855 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 91240 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 92095 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 855 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 91240 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 92095 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 44767500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1630159000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 1674926500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3134429000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 3134429000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 44767500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 4764588000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 4809355500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 44767500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 4764588000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 4809355500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 855 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 201213 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 202068 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 408190 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 408190 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 254182 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 254182 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 855 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 455395 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 456250 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 855 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 455395 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 456250 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.154881 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.158457 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.236350 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.236350 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.200354 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.201852 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.200354 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.201852 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52359.649123 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52309.042485 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52310.393829 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52174.395765 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52174.395765 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52359.649123 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52220.385796 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52221.678701 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52359.649123 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52220.385796 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52221.678701 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 1278500 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 127 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 10066.929134 # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks::writebacks 59346 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 59346 # number of writebacks
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 855 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 31164 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::total 32019 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 60076 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 60076 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 855 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 91240 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 92095 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 855 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 91240 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 92095 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 34345000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1246682000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1281027000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2406884500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2406884500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 34345000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3653566500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 3687911500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 34345000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3653566500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 3687911500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.154881 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.158457 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.236350 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.236350 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.200354 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.201852 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.200354 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.201852 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40169.590643 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40003.914773 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40008.338799 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40063.993941 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40063.993941 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40169.590643 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40043.473257 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40044.644117 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40169.590643 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40043.473257 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40044.644117 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
@ -0,0 +1,529 @@
|
||||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
full_system=false
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
||||
[system]
|
||||
type=System
|
||||
children=cpu membus physmem
|
||||
boot_osflags=a
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
mem_mode=atomic
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
readfile=
|
||||
symbolfile=
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.membus.slave[0]
|
||||
|
||||
[system.cpu]
|
||||
type=DerivO3CPU
|
||||
children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
|
||||
BTBEntries=4096
|
||||
BTBTagSize=16
|
||||
LFSTSize=1024
|
||||
LQEntries=32
|
||||
LSQCheckLoads=true
|
||||
LSQDepCheckShift=4
|
||||
RASSize=16
|
||||
SQEntries=32
|
||||
SSITSize=1024
|
||||
activity=0
|
||||
backComSize=5
|
||||
cachePorts=200
|
||||
checker=Null
|
||||
choiceCtrBits=2
|
||||
choicePredictorSize=8192
|
||||
clock=500
|
||||
commitToDecodeDelay=1
|
||||
commitToFetchDelay=1
|
||||
commitToIEWDelay=1
|
||||
commitToRenameDelay=1
|
||||
commitWidth=8
|
||||
cpu_id=0
|
||||
decodeToFetchDelay=1
|
||||
decodeToRenameDelay=1
|
||||
decodeWidth=8
|
||||
defer_registration=false
|
||||
dispatchWidth=8
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
fetchToDecodeDelay=1
|
||||
fetchTrapLatency=1
|
||||
fetchWidth=8
|
||||
forwardComSize=5
|
||||
fuPool=system.cpu.fuPool
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
globalCtrBits=2
|
||||
globalHistoryBits=13
|
||||
globalPredictorSize=8192
|
||||
iewToCommitDelay=1
|
||||
iewToDecodeDelay=1
|
||||
iewToFetchDelay=1
|
||||
iewToRenameDelay=1
|
||||
instShiftAmt=2
|
||||
interrupts=system.cpu.interrupts
|
||||
issueToExecuteDelay=1
|
||||
issueWidth=8
|
||||
itb=system.cpu.itb
|
||||
localCtrBits=2
|
||||
localHistoryBits=11
|
||||
localHistoryTableSize=2048
|
||||
localPredictorSize=2048
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
needsTSO=false
|
||||
numIQEntries=64
|
||||
numPhysFloatRegs=256
|
||||
numPhysIntRegs=256
|
||||
numROBEntries=192
|
||||
numRobs=1
|
||||
numThreads=1
|
||||
phase=0
|
||||
predType=tournament
|
||||
profile=0
|
||||
progress_interval=0
|
||||
renameToDecodeDelay=1
|
||||
renameToFetchDelay=1
|
||||
renameToIEWDelay=2
|
||||
renameToROBDelay=1
|
||||
renameWidth=8
|
||||
smtCommitPolicy=RoundRobin
|
||||
smtFetchPolicy=SingleThread
|
||||
smtIQPolicy=Partitioned
|
||||
smtIQThreshold=100
|
||||
smtLSQPolicy=Partitioned
|
||||
smtLSQThreshold=100
|
||||
smtNumFetchingThreads=1
|
||||
smtROBPolicy=Partitioned
|
||||
smtROBThreshold=100
|
||||
squashWidth=8
|
||||
store_set_clear_period=250000
|
||||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
trapLatency=13
|
||||
wbDepth=1
|
||||
wbWidth=8
|
||||
workload=system.cpu.workload
|
||||
dcache_port=system.cpu.dcache.cpu_side
|
||||
icache_port=system.cpu.icache.cpu_side
|
||||
|
||||
[system.cpu.dcache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=262144
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=20
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.dcache_port
|
||||
mem_side=system.cpu.toL2Bus.slave[1]
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=AlphaTLB
|
||||
size=64
|
||||
|
||||
[system.cpu.fuPool]
|
||||
type=FUPool
|
||||
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
|
||||
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
|
||||
|
||||
[system.cpu.fuPool.FUList0]
|
||||
type=FUDesc
|
||||
children=opList
|
||||
count=6
|
||||
opList=system.cpu.fuPool.FUList0.opList
|
||||
|
||||
[system.cpu.fuPool.FUList0.opList]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=IntAlu
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList1]
|
||||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=2
|
||||
opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=IntMult
|
||||
opLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList1]
|
||||
type=OpDesc
|
||||
issueLat=19
|
||||
opClass=IntDiv
|
||||
opLat=20
|
||||
|
||||
[system.cpu.fuPool.FUList2]
|
||||
type=FUDesc
|
||||
children=opList0 opList1 opList2
|
||||
count=4
|
||||
opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=FloatAdd
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList1]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=FloatCmp
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList2]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=FloatCvt
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList3]
|
||||
type=FUDesc
|
||||
children=opList0 opList1 opList2
|
||||
count=2
|
||||
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=FloatMult
|
||||
opLat=4
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList1]
|
||||
type=OpDesc
|
||||
issueLat=12
|
||||
opClass=FloatDiv
|
||||
opLat=12
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList2]
|
||||
type=OpDesc
|
||||
issueLat=24
|
||||
opClass=FloatSqrt
|
||||
opLat=24
|
||||
|
||||
[system.cpu.fuPool.FUList4]
|
||||
type=FUDesc
|
||||
children=opList
|
||||
count=0
|
||||
opList=system.cpu.fuPool.FUList4.opList
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5]
|
||||
type=FUDesc
|
||||
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
|
||||
count=4
|
||||
opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList00]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdAdd
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList01]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdAddAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList02]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdAlu
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList03]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdCmp
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList04]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdCvt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList05]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdMisc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList06]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdMult
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList07]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdMultAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList08]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdShift
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList09]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdShiftAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList10]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdSqrt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList11]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatAdd
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList12]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatAlu
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList13]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatCmp
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList14]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatCvt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList15]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatDiv
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList16]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatMisc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList17]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatMult
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList18]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatMultAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList19]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatSqrt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList6]
|
||||
type=FUDesc
|
||||
children=opList
|
||||
count=0
|
||||
opList=system.cpu.fuPool.FUList6.opList
|
||||
|
||||
[system.cpu.fuPool.FUList6.opList]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList7]
|
||||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=4
|
||||
opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList1]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList8]
|
||||
type=FUDesc
|
||||
children=opList
|
||||
count=1
|
||||
opList=system.cpu.fuPool.FUList8.opList
|
||||
|
||||
[system.cpu.fuPool.FUList8.opList]
|
||||
type=OpDesc
|
||||
issueLat=3
|
||||
opClass=IprAccess
|
||||
opLat=3
|
||||
|
||||
[system.cpu.icache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=131072
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=20
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.icache_port
|
||||
mem_side=system.cpu.toL2Bus.slave[0]
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=AlphaInterrupts
|
||||
|
||||
[system.cpu.itb]
|
||||
type=AlphaTLB
|
||||
size=48
|
||||
|
||||
[system.cpu.l2cache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=false
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=2097152
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.toL2Bus.master[0]
|
||||
mem_side=system.membus.slave[1]
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
master=system.cpu.l2cache.cpu_side
|
||||
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
|
||||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
|
||||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=gzip input.log 1
|
||||
cwd=build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/o3-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
ppid=99
|
||||
simpoint=0
|
||||
system=system
|
||||
uid=100
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
master=system.physmem.port[0]
|
||||
slave=system.system_port system.cpu.l2cache.mem_side
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.membus.master[0]
|
||||
|
||||
6
simulators/gem5/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simerr
Executable file
6
simulators/gem5/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simerr
Executable file
@ -0,0 +1,6 @@
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: Prefetch instructions in Alpha do not do anything
|
||||
warn: Prefetch instructions in Alpha do not do anything
|
||||
warn: Prefetch instructions in Alpha do not do anything
|
||||
warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
|
||||
hack: be nice to actually delete the event here
|
||||
42
simulators/gem5/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simout
Executable file
42
simulators/gem5/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simout
Executable file
@ -0,0 +1,42 @@
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jun 4 2012 11:50:11
|
||||
gem5 started Jun 4 2012 13:42:45
|
||||
gem5 executing on zizzer
|
||||
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
spec_init
|
||||
Loading Input Data
|
||||
Duplicating 262144 bytes
|
||||
Duplicating 524288 bytes
|
||||
Input data 1048576 bytes in length
|
||||
Compressing Input Data, level 1
|
||||
Compressed data 108074 bytes in length
|
||||
Uncompressing Data
|
||||
Uncompressed data 1048576 bytes in length
|
||||
Uncompressed data compared correctly
|
||||
Compressing Input Data, level 3
|
||||
Compressed data 97831 bytes in length
|
||||
Uncompressing Data
|
||||
Uncompressed data 1048576 bytes in length
|
||||
Uncompressed data compared correctly
|
||||
Compressing Input Data, level 5
|
||||
Compressed data 83382 bytes in length
|
||||
Uncompressing Data
|
||||
Uncompressed data 1048576 bytes in length
|
||||
Uncompressed data compared correctly
|
||||
Compressing Input Data, level 7
|
||||
Compressed data 76606 bytes in length
|
||||
Uncompressing Data
|
||||
Uncompressed data 1048576 bytes in length
|
||||
Uncompressed data compared correctly
|
||||
Compressing Input Data, level 9
|
||||
Compressed data 73189 bytes in length
|
||||
Uncompressing Data
|
||||
Uncompressed data 1048576 bytes in length
|
||||
Uncompressed data compared correctly
|
||||
Tested 1MB buffer: OK!
|
||||
Exiting @ tick 134621123500 because target called exit()
|
||||
@ -0,0 +1,682 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.134621 # Number of seconds simulated
|
||||
sim_ticks 134621123500 # Number of ticks simulated
|
||||
final_tick 134621123500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 192359 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 192359 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 45788058 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 216172 # Number of bytes of host memory used
|
||||
host_seconds 2940.09 # Real time elapsed on the host
|
||||
sim_insts 565552443 # Number of instructions simulated
|
||||
sim_ops 565552443 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 64128 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 5873472 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 5937600 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 64128 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 64128 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 3797952 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 3797952 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 1002 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 91773 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 92775 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 59343 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 59343 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 476359 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 43629646 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 44106005 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 476359 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 476359 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 28212155 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 28212155 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 28212155 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 476359 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 43629646 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 72318160 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
||||
system.cpu.dtb.read_hits 123836708 # DTB read hits
|
||||
system.cpu.dtb.read_misses 23555 # DTB read misses
|
||||
system.cpu.dtb.read_acv 0 # DTB read access violations
|
||||
system.cpu.dtb.read_accesses 123860263 # DTB read accesses
|
||||
system.cpu.dtb.write_hits 40831838 # DTB write hits
|
||||
system.cpu.dtb.write_misses 31545 # DTB write misses
|
||||
system.cpu.dtb.write_acv 0 # DTB write access violations
|
||||
system.cpu.dtb.write_accesses 40863383 # DTB write accesses
|
||||
system.cpu.dtb.data_hits 164668546 # DTB hits
|
||||
system.cpu.dtb.data_misses 55100 # DTB misses
|
||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
||||
system.cpu.dtb.data_accesses 164723646 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 66483943 # ITB hits
|
||||
system.cpu.itb.fetch_misses 37 # ITB misses
|
||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
||||
system.cpu.itb.fetch_accesses 66483980 # ITB accesses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.itb.write_hits 0 # DTB write hits
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.itb.write_acv 0 # DTB write access violations
|
||||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.itb.data_hits 0 # DTB hits
|
||||
system.cpu.itb.data_misses 0 # DTB misses
|
||||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 17 # Number of system calls
|
||||
system.cpu.numCycles 269242248 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.BPredUnit.lookups 78494350 # Number of BP lookups
|
||||
system.cpu.BPredUnit.condPredicted 72856279 # Number of conditional branches predicted
|
||||
system.cpu.BPredUnit.condIncorrect 3049613 # Number of conditional branches incorrect
|
||||
system.cpu.BPredUnit.BTBLookups 42772936 # Number of BTB lookups
|
||||
system.cpu.BPredUnit.BTBHits 41636011 # Number of BTB hits
|
||||
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu.BPredUnit.usedRAS 1626078 # Number of times the RAS was used to get a target.
|
||||
system.cpu.BPredUnit.RASInCorrect 617 # Number of incorrect RAS predictions.
|
||||
system.cpu.fetch.icacheStallCycles 68428248 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.Insts 710832339 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.Branches 78494350 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.predictedBranches 43262089 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.Cycles 119193912 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.SquashCycles 12932117 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.BlockedCycles 71677823 # Number of cycles fetch has spent blocked
|
||||
system.cpu.fetch.MiscStallCycles 29 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
||||
system.cpu.fetch.PendingTrapStallCycles 965 # Number of stall cycles due to pending traps
|
||||
system.cpu.fetch.CacheLines 66483943 # Number of cache lines fetched
|
||||
system.cpu.fetch.IcacheSquashes 942005 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.rateDist::samples 269174552 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 2.640786 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 3.458790 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 149980640 55.72% 55.72% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 10366067 3.85% 59.57% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 11842490 4.40% 63.97% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 10610817 3.94% 67.91% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 6990702 2.60% 70.51% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 2664486 0.99% 71.50% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 3492691 1.30% 72.80% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 3105815 1.15% 73.95% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 70120844 26.05% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::total 269174552 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.branchRate 0.291538 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.rate 2.640122 # Number of inst fetches per cycle
|
||||
system.cpu.decode.IdleCycles 85707948 # Number of cycles decode is idle
|
||||
system.cpu.decode.BlockedCycles 55913414 # Number of cycles decode is blocked
|
||||
system.cpu.decode.RunCycles 104656914 # Number of cycles decode is running
|
||||
system.cpu.decode.UnblockCycles 13023782 # Number of cycles decode is unblocking
|
||||
system.cpu.decode.SquashCycles 9872494 # Number of cycles decode is squashing
|
||||
system.cpu.decode.BranchResolved 3909156 # Number of times decode resolved a branch
|
||||
system.cpu.decode.BranchMispred 1160 # Number of times decode detected a branch misprediction
|
||||
system.cpu.decode.DecodedInsts 702084562 # Number of instructions handled by decode
|
||||
system.cpu.decode.SquashedInsts 4999 # Number of squashed instructions handled by decode
|
||||
system.cpu.rename.SquashCycles 9872494 # Number of cycles rename is squashing
|
||||
system.cpu.rename.IdleCycles 93982559 # Number of cycles rename is idle
|
||||
system.cpu.rename.BlockCycles 12740757 # Number of cycles rename is blocking
|
||||
system.cpu.rename.serializeStallCycles 2287 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RunCycles 104137265 # Number of cycles rename is running
|
||||
system.cpu.rename.UnblockCycles 48439190 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RenamedInsts 690176100 # Number of instructions processed by rename
|
||||
system.cpu.rename.ROBFullEvents 220 # Number of times rename has blocked due to ROB full
|
||||
system.cpu.rename.IQFullEvents 36870562 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.LSQFullEvents 5345683 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RenamedOperands 527299875 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RenameLookups 906867454 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.int_rename_lookups 906864467 # Number of integer rename lookups
|
||||
system.cpu.rename.fp_rename_lookups 2987 # Number of floating rename lookups
|
||||
system.cpu.rename.CommittedMaps 463854889 # Number of HB maps that are committed
|
||||
system.cpu.rename.UndoneMaps 63444986 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.serializingInsts 171 # count of serializing insts renamed
|
||||
system.cpu.rename.tempSerializingInsts 186 # count of temporary serializing insts renamed
|
||||
system.cpu.rename.skidInsts 107659132 # count of insts added to the skid buffer
|
||||
system.cpu.memDep0.insertedLoads 129005013 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 42430995 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.conflictingLoads 14679275 # Number of conflicting loads.
|
||||
system.cpu.memDep0.conflictingStores 9584938 # Number of conflicting stores.
|
||||
system.cpu.iq.iqInstsAdded 626474820 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqNonSpecInstsAdded 120 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqInstsIssued 608397310 # Number of instructions issued
|
||||
system.cpu.iq.iqSquashedInstsIssued 335936 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedInstsExamined 60222555 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedOperandsExamined 33444580 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 103 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.issued_per_cycle::samples 269174552 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::mean 2.260233 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::stdev 1.839356 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::0 54646313 20.30% 20.30% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::1 54798689 20.36% 40.66% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::2 53375432 19.83% 60.49% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::3 36717503 13.64% 74.13% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::4 30865027 11.47% 85.60% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::5 24096775 8.95% 94.55% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::6 10651297 3.96% 98.51% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::7 3344645 1.24% 99.75% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::8 678871 0.25% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::total 269174552 # Number of insts issued each cycle
|
||||
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntAlu 2904763 73.47% 73.47% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntMult 39 0.00% 73.47% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntDiv 0 0.00% 73.47% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatAdd 0 0.00% 73.47% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatCmp 0 0.00% 73.47% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatCvt 0 0.00% 73.47% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatMult 0 0.00% 73.47% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatDiv 0 0.00% 73.47% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 73.47% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdAdd 0 0.00% 73.47% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 73.47% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdAlu 0 0.00% 73.47% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdCmp 0 0.00% 73.47% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdCvt 0 0.00% 73.47% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdMisc 0 0.00% 73.47% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdMult 0 0.00% 73.47% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 73.47% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdShift 0 0.00% 73.47% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 73.47% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 73.47% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 73.47% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 73.47% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 73.47% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 73.47% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 73.47% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 73.47% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 73.47% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 73.47% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 73.47% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::MemRead 634502 16.05% 89.52% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::MemWrite 414382 10.48% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntAlu 441013335 72.49% 72.49% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntMult 7329 0.00% 72.49% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 72.49% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatAdd 32 0.00% 72.49% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatCmp 5 0.00% 72.49% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatCvt 5 0.00% 72.49% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatMult 5 0.00% 72.49% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 72.49% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 72.49% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 72.49% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 72.49% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 72.49% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 72.49% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 72.49% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 72.49% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 72.49% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 72.49% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 72.49% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 72.49% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 72.49% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 72.49% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 72.49% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 72.49% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 72.49% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 72.49% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 72.49% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 72.49% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 72.49% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 72.49% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::MemRead 126118254 20.73% 93.22% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::MemWrite 41258345 6.78% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::total 608397310 # Type of FU issued
|
||||
system.cpu.iq.rate 2.259665 # Inst issue rate
|
||||
system.cpu.iq.fu_busy_cnt 3953686 # FU busy when requested
|
||||
system.cpu.iq.fu_busy_rate 0.006499 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.int_inst_queue_reads 1490254859 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_writes 686699872 # Number of integer instruction queue writes
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 598814509 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.fp_inst_queue_reads 3935 # Number of floating instruction queue reads
|
||||
system.cpu.iq.fp_inst_queue_writes 2431 # Number of floating instruction queue writes
|
||||
system.cpu.iq.fp_inst_queue_wakeup_accesses 1728 # Number of floating instruction queue wakeup accesses
|
||||
system.cpu.iq.int_alu_accesses 612349032 # Number of integer alu accesses
|
||||
system.cpu.iq.fp_alu_accesses 1964 # Number of floating point alu accesses
|
||||
system.cpu.iew.lsq.thread0.forwLoads 12165746 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread0.squashedLoads 14490971 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread0.ignoredResponses 33593 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread0.memOrderViolation 4856 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread0.squashedStores 2979674 # Number of stores squashed
|
||||
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
||||
system.cpu.iew.lsq.thread0.rescheduledLoads 6726 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread0.cacheBlocked 51107 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||||
system.cpu.iew.iewSquashCycles 9872494 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewBlockCycles 1561922 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewUnblockCycles 98319 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.iewDispatchedInsts 670401264 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewDispSquashedInsts 1688610 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispLoadInsts 129005013 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispStoreInsts 42430995 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 120 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewIQFullEvents 41033 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.iewLSQFullEvents 13811 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.memOrderViolationEvents 4856 # Number of memory order violations
|
||||
system.cpu.iew.predictedTakenIncorrect 1345444 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.iew.predictedNotTakenIncorrect 2209649 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.branchMispredicts 3555093 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewExecutedInsts 602577350 # Number of executed instructions
|
||||
system.cpu.iew.iewExecLoadInsts 123860441 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 5819960 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
||||
system.cpu.iew.exec_nop 43926324 # number of nop insts executed
|
||||
system.cpu.iew.exec_refs 164740912 # number of memory reference insts executed
|
||||
system.cpu.iew.exec_branches 67006670 # Number of branches executed
|
||||
system.cpu.iew.exec_stores 40880471 # Number of stores executed
|
||||
system.cpu.iew.exec_rate 2.238049 # Inst execution rate
|
||||
system.cpu.iew.wb_sent 600066569 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.wb_count 598816237 # cumulative count of insts written-back
|
||||
system.cpu.iew.wb_producers 417486240 # num instructions producing a value
|
||||
system.cpu.iew.wb_consumers 531487841 # num instructions consuming a value
|
||||
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
||||
system.cpu.iew.wb_rate 2.224080 # insts written-back per cycle
|
||||
system.cpu.iew.wb_fanout 0.785505 # average fanout of values written-back
|
||||
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||
system.cpu.commit.commitCommittedInsts 601856963 # The number of committed instructions
|
||||
system.cpu.commit.commitCommittedOps 601856963 # The number of committed instructions
|
||||
system.cpu.commit.commitSquashedInsts 68396273 # The number of squashed insts skipped by commit
|
||||
system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu.commit.branchMispredicts 3048532 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.committed_per_cycle::samples 259302058 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::mean 2.321065 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::stdev 2.702332 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::0 80379492 31.00% 31.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::1 72839999 28.09% 59.09% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::2 26734500 10.31% 69.40% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::3 8121130 3.13% 72.53% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::4 10288458 3.97% 76.50% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::5 20405541 7.87% 84.37% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::6 6352213 2.45% 86.82% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::7 3556041 1.37% 88.19% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::8 30624684 11.81% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::total 259302058 # Number of insts commited each cycle
|
||||
system.cpu.commit.committedInsts 601856963 # Number of instructions committed
|
||||
system.cpu.commit.committedOps 601856963 # Number of ops (including micro ops) committed
|
||||
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
||||
system.cpu.commit.refs 153965363 # Number of memory references committed
|
||||
system.cpu.commit.loads 114514042 # Number of loads committed
|
||||
system.cpu.commit.membars 0 # Number of memory barriers committed
|
||||
system.cpu.commit.branches 62547159 # Number of branches committed
|
||||
system.cpu.commit.fp_insts 1520 # Number of committed floating point instructions.
|
||||
system.cpu.commit.int_insts 563954763 # Number of committed integer instructions.
|
||||
system.cpu.commit.function_calls 1197610 # Number of function calls committed.
|
||||
system.cpu.commit.bw_lim_events 30624684 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
||||
system.cpu.rob.rob_reads 898866221 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 1350401622 # The number of ROB writes
|
||||
system.cpu.timesIdled 2160 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 67696 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.committedInsts 565552443 # Number of Instructions Simulated
|
||||
system.cpu.committedOps 565552443 # Number of Ops (including micro ops) Simulated
|
||||
system.cpu.committedInsts_total 565552443 # Number of Instructions Simulated
|
||||
system.cpu.cpi 0.476069 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 0.476069 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 2.100534 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 2.100534 # IPC: Total IPC of All Threads
|
||||
system.cpu.int_regfile_reads 848641681 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 492726607 # number of integer regfile writes
|
||||
system.cpu.fp_regfile_reads 387 # number of floating regfile reads
|
||||
system.cpu.fp_regfile_writes 54 # number of floating regfile writes
|
||||
system.cpu.misc_regfile_reads 1 # number of misc regfile reads
|
||||
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
|
||||
system.cpu.icache.replacements 49 # number of replacements
|
||||
system.cpu.icache.tagsinuse 844.563885 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 66482496 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 1002 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 66349.796407 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 844.563885 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.412385 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.412385 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 66482496 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 66482496 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 66482496 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 66482496 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 66482496 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 66482496 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 1447 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 1447 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 1447 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 1447 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 1447 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 1447 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 50567500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 50567500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 50567500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 50567500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 50567500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 50567500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 66483943 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 66483943 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 66483943 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 66483943 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 66483943 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 66483943 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000022 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.000022 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000022 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.000022 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000022 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000022 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34946.440912 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 34946.440912 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 34946.440912 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 34946.440912 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 34946.440912 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 34946.440912 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 445 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::total 445 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::cpu.inst 445 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::total 445 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::cpu.inst 445 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::total 445 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1002 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 1002 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 1002 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 1002 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 1002 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 1002 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 35750000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 35750000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 35750000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 35750000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 35750000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 35750000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000015 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000015 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000015 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000015 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000015 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000015 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35678.642715 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35678.642715 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35678.642715 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 35678.642715 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35678.642715 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 35678.642715 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 460743 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 4093.783086 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 149091432 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 464839 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 320.737787 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 126301000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 4093.783086 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.999459 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.999459 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 110940808 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 110940808 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 38150562 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 38150562 # number of WriteReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::cpu.data 62 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::total 62 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 149091370 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 149091370 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 149091370 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 149091370 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 722352 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 722352 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 1300759 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 1300759 # number of WriteReq misses
|
||||
system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 2023111 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 2023111 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 2023111 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 2023111 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 11755158500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 11755158500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 19630287922 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 19630287922 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 3500 # number of LoadLockedReq miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_miss_latency::total 3500 # number of LoadLockedReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 31385446422 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 31385446422 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 31385446422 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 31385446422 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 111663160 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 111663160 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 39451321 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 39451321 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 63 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::total 63 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 151114481 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 151114481 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 151114481 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 151114481 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.006469 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.006469 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032971 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.032971 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.015873 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.015873 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.013388 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.013388 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.013388 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.013388 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16273.449094 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 16273.449094 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 15091.410417 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 15091.410417 # average WriteReq miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 3500 # average LoadLockedReq miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 3500 # average LoadLockedReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 15513.457453 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 15513.457453 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 15513.457453 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 15513.457453 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 678496 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 191500 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 100 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 11 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 6784.960000 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets 17409.090909 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 415225 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 415225 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 512035 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 512035 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1046237 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 1046237 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1 # number of LoadLockedReq MSHR hits
|
||||
system.cpu.dcache.LoadLockedReq_mshr_hits::total 1 # number of LoadLockedReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 1558272 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 1558272 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 1558272 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 1558272 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 210317 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 210317 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 254522 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 254522 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 464839 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 464839 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 464839 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 464839 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1619332500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 1619332500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3028681995 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3028681995 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4648014495 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 4648014495 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4648014495 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 4648014495 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001883 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001883 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006452 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006452 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003076 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.003076 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003076 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.003076 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7699.484588 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 7699.484588 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 11899.490005 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 11899.490005 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 9999.192183 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 9999.192183 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 9999.192183 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 9999.192183 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 74480 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 17651.004599 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 461925 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 90375 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 5.111203 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::writebacks 15915.661195 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 39.497783 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 1695.845621 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.485707 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.001205 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.051753 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.538666 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 178382 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 178382 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 415225 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 415225 # number of Writeback hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 194684 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 194684 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 373066 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 373066 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 373066 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 373066 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 1002 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.data 31935 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 32937 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 59838 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 59838 # number of ReadExReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 1002 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 91773 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 92775 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 1002 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 91773 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 92775 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 34422500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1098528500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 1132951000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2066830500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 2066830500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 34422500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 3165359000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 3199781500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 34422500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 3165359000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 3199781500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 1002 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 210317 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 211319 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 415225 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 415225 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 254522 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 254522 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 1002 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 464839 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 465841 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 1002 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 464839 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 465841 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.151842 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.155864 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.235100 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.235100 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.197430 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.199156 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.197430 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.199156 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34353.792415 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34398.888367 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 34397.516471 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34540.434172 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34540.434172 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34353.792415 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34491.179323 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 34489.695500 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34353.792415 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34491.179323 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 34489.695500 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 339500 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 49 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 6928.571429 # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks::writebacks 59343 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 59343 # number of writebacks
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1002 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 31935 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::total 32937 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 59838 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 59838 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 1002 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 91773 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 92775 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 1002 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 91773 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 92775 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 31203000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 990467000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1021670000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1878462500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1878462500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 31203000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 2868929500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 2900132500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 31203000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2868929500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 2900132500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.151842 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.155864 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.235100 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.235100 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.197430 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.199156 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.197430 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.199156 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31140.718563 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31015.093158 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31018.914898 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31392.467997 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31392.467997 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31140.718563 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31261.149794 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31259.849097 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31140.718563 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31261.149794 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31259.849097 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
@ -0,0 +1,117 @@
|
||||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
full_system=false
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
||||
[system]
|
||||
type=System
|
||||
children=cpu membus physmem
|
||||
boot_osflags=a
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
mem_mode=atomic
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
readfile=
|
||||
symbolfile=
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.membus.slave[0]
|
||||
|
||||
[system.cpu]
|
||||
type=AtomicSimpleCPU
|
||||
children=dtb interrupts itb tracer workload
|
||||
checker=Null
|
||||
clock=500
|
||||
cpu_id=0
|
||||
defer_registration=false
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
fastmem=false
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
interrupts=system.cpu.interrupts
|
||||
itb=system.cpu.itb
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
phase=0
|
||||
profile=0
|
||||
progress_interval=0
|
||||
simulate_data_stalls=false
|
||||
simulate_inst_stalls=false
|
||||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
width=1
|
||||
workload=system.cpu.workload
|
||||
dcache_port=system.membus.slave[2]
|
||||
icache_port=system.membus.slave[1]
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=AlphaTLB
|
||||
size=64
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=AlphaInterrupts
|
||||
|
||||
[system.cpu.itb]
|
||||
type=AlphaTLB
|
||||
size=48
|
||||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
|
||||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=gzip input.log 1
|
||||
cwd=build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/simple-atomic
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
ppid=99
|
||||
simpoint=0
|
||||
system=system
|
||||
uid=100
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
master=system.physmem.port[0]
|
||||
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.membus.master[0]
|
||||
|
||||
@ -0,0 +1,7 @@
|
||||
warn: CoherentBus system.membus has no snooping ports attached!
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: Prefetch instructions in Alpha do not do anything
|
||||
warn: Prefetch instructions in Alpha do not do anything
|
||||
warn: Prefetch instructions in Alpha do not do anything
|
||||
warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
|
||||
hack: be nice to actually delete the event here
|
||||
42
simulators/gem5/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/simout
Executable file
42
simulators/gem5/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/simout
Executable file
@ -0,0 +1,42 @@
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jun 4 2012 11:50:11
|
||||
gem5 started Jun 4 2012 14:03:38
|
||||
gem5 executing on zizzer
|
||||
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/simple-atomic
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
spec_init
|
||||
Loading Input Data
|
||||
Duplicating 262144 bytes
|
||||
Duplicating 524288 bytes
|
||||
Input data 1048576 bytes in length
|
||||
Compressing Input Data, level 1
|
||||
Compressed data 108074 bytes in length
|
||||
Uncompressing Data
|
||||
Uncompressed data 1048576 bytes in length
|
||||
Uncompressed data compared correctly
|
||||
Compressing Input Data, level 3
|
||||
Compressed data 97831 bytes in length
|
||||
Uncompressing Data
|
||||
Uncompressed data 1048576 bytes in length
|
||||
Uncompressed data compared correctly
|
||||
Compressing Input Data, level 5
|
||||
Compressed data 83382 bytes in length
|
||||
Uncompressing Data
|
||||
Uncompressed data 1048576 bytes in length
|
||||
Uncompressed data compared correctly
|
||||
Compressing Input Data, level 7
|
||||
Compressed data 76606 bytes in length
|
||||
Uncompressing Data
|
||||
Uncompressed data 1048576 bytes in length
|
||||
Uncompressed data compared correctly
|
||||
Compressing Input Data, level 9
|
||||
Compressed data 73189 bytes in length
|
||||
Uncompressing Data
|
||||
Uncompressed data 1048576 bytes in length
|
||||
Uncompressed data compared correctly
|
||||
Tested 1MB buffer: OK!
|
||||
Exiting @ tick 300930958000 because target called exit()
|
||||
@ -0,0 +1,92 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.300931 # Number of seconds simulated
|
||||
sim_ticks 300930958000 # Number of ticks simulated
|
||||
final_tick 300930958000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 3871430 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 3871429 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1935730316 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 206040 # Number of bytes of host memory used
|
||||
host_seconds 155.46 # Real time elapsed on the host
|
||||
sim_insts 601856964 # Number of instructions simulated
|
||||
sim_ops 601856964 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 2407447588 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 375543340 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 2782990928 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 2407447588 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 2407447588 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::cpu.data 152669504 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 152669504 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 601861897 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 114514042 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 716375939 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::cpu.data 39451321 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 39451321 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 7999999747 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 1247938539 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 9247938286 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 7999999747 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 7999999747 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::cpu.data 507324022 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 507324022 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 7999999747 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 1755262561 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 9755262308 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
||||
system.cpu.dtb.read_hits 114514042 # DTB read hits
|
||||
system.cpu.dtb.read_misses 2631 # DTB read misses
|
||||
system.cpu.dtb.read_acv 0 # DTB read access violations
|
||||
system.cpu.dtb.read_accesses 114516673 # DTB read accesses
|
||||
system.cpu.dtb.write_hits 39451321 # DTB write hits
|
||||
system.cpu.dtb.write_misses 2302 # DTB write misses
|
||||
system.cpu.dtb.write_acv 0 # DTB write access violations
|
||||
system.cpu.dtb.write_accesses 39453623 # DTB write accesses
|
||||
system.cpu.dtb.data_hits 153965363 # DTB hits
|
||||
system.cpu.dtb.data_misses 4933 # DTB misses
|
||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
||||
system.cpu.dtb.data_accesses 153970296 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 601861897 # ITB hits
|
||||
system.cpu.itb.fetch_misses 20 # ITB misses
|
||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
||||
system.cpu.itb.fetch_accesses 601861917 # ITB accesses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.itb.write_hits 0 # DTB write hits
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.itb.write_acv 0 # DTB write access violations
|
||||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.itb.data_hits 0 # DTB hits
|
||||
system.cpu.itb.data_misses 0 # DTB misses
|
||||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 17 # Number of system calls
|
||||
system.cpu.numCycles 601861917 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 601856964 # Number of instructions committed
|
||||
system.cpu.committedOps 601856964 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 563959696 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 1520 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 2395217 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 58554292 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 563959696 # number of integer instructions
|
||||
system.cpu.num_fp_insts 1520 # number of float instructions
|
||||
system.cpu.num_int_register_reads 801088993 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 463854847 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 169 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 42 # number of times the floating registers were written
|
||||
system.cpu.num_mem_refs 153970296 # number of memory refs
|
||||
system.cpu.num_load_insts 114516673 # Number of load instructions
|
||||
system.cpu.num_store_insts 39453623 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 601861917 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
@ -0,0 +1,198 @@
|
||||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
full_system=false
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
||||
[system]
|
||||
type=System
|
||||
children=cpu membus physmem
|
||||
boot_osflags=a
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
mem_mode=atomic
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
readfile=
|
||||
symbolfile=
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.membus.slave[0]
|
||||
|
||||
[system.cpu]
|
||||
type=TimingSimpleCPU
|
||||
children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
|
||||
checker=Null
|
||||
clock=500
|
||||
cpu_id=0
|
||||
defer_registration=false
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
interrupts=system.cpu.interrupts
|
||||
itb=system.cpu.itb
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
phase=0
|
||||
profile=0
|
||||
progress_interval=0
|
||||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
workload=system.cpu.workload
|
||||
dcache_port=system.cpu.dcache.cpu_side
|
||||
icache_port=system.cpu.icache.cpu_side
|
||||
|
||||
[system.cpu.dcache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=262144
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.dcache_port
|
||||
mem_side=system.cpu.toL2Bus.slave[1]
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=AlphaTLB
|
||||
size=64
|
||||
|
||||
[system.cpu.icache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=131072
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.icache_port
|
||||
mem_side=system.cpu.toL2Bus.slave[0]
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=AlphaInterrupts
|
||||
|
||||
[system.cpu.itb]
|
||||
type=AlphaTLB
|
||||
size=48
|
||||
|
||||
[system.cpu.l2cache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=false
|
||||
latency=10000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=2097152
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.toL2Bus.master[0]
|
||||
mem_side=system.membus.slave[1]
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
master=system.cpu.l2cache.cpu_side
|
||||
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
|
||||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
|
||||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=gzip input.log 1
|
||||
cwd=build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/simple-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
ppid=99
|
||||
simpoint=0
|
||||
system=system
|
||||
uid=100
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
master=system.physmem.port[0]
|
||||
slave=system.system_port system.cpu.l2cache.mem_side
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.membus.master[0]
|
||||
|
||||
@ -0,0 +1,6 @@
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: Prefetch instructions in Alpha do not do anything
|
||||
warn: Prefetch instructions in Alpha do not do anything
|
||||
warn: Prefetch instructions in Alpha do not do anything
|
||||
warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
|
||||
hack: be nice to actually delete the event here
|
||||
42
simulators/gem5/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/simout
Executable file
42
simulators/gem5/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/simout
Executable file
@ -0,0 +1,42 @@
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jun 4 2012 11:50:11
|
||||
gem5 started Jun 4 2012 13:42:36
|
||||
gem5 executing on zizzer
|
||||
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/simple-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
spec_init
|
||||
Loading Input Data
|
||||
Duplicating 262144 bytes
|
||||
Duplicating 524288 bytes
|
||||
Input data 1048576 bytes in length
|
||||
Compressing Input Data, level 1
|
||||
Compressed data 108074 bytes in length
|
||||
Uncompressing Data
|
||||
Uncompressed data 1048576 bytes in length
|
||||
Uncompressed data compared correctly
|
||||
Compressing Input Data, level 3
|
||||
Compressed data 97831 bytes in length
|
||||
Uncompressing Data
|
||||
Uncompressed data 1048576 bytes in length
|
||||
Uncompressed data compared correctly
|
||||
Compressing Input Data, level 5
|
||||
Compressed data 83382 bytes in length
|
||||
Uncompressing Data
|
||||
Uncompressed data 1048576 bytes in length
|
||||
Uncompressed data compared correctly
|
||||
Compressing Input Data, level 7
|
||||
Compressed data 76606 bytes in length
|
||||
Uncompressing Data
|
||||
Uncompressed data 1048576 bytes in length
|
||||
Uncompressed data compared correctly
|
||||
Compressing Input Data, level 9
|
||||
Compressed data 73189 bytes in length
|
||||
Uncompressing Data
|
||||
Uncompressed data 1048576 bytes in length
|
||||
Uncompressed data compared correctly
|
||||
Tested 1MB buffer: OK!
|
||||
Exiting @ tick 765623032000 because target called exit()
|
||||
@ -0,0 +1,406 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.765623 # Number of seconds simulated
|
||||
sim_ticks 765623032000 # Number of ticks simulated
|
||||
final_tick 765623032000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1675799 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1675799 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2131786057 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 214908 # Number of bytes of host memory used
|
||||
host_seconds 359.15 # Real time elapsed on the host
|
||||
sim_insts 601856964 # Number of instructions simulated
|
||||
sim_ops 601856964 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 50880 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 5839104 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 5889984 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 50880 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 50880 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 3797824 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 3797824 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 795 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 91236 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 92031 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 59341 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 59341 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 66456 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 7626604 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 7693060 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 66456 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 66456 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 4960436 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 4960436 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 4960436 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 66456 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 7626604 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 12653496 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
||||
system.cpu.dtb.read_hits 114514042 # DTB read hits
|
||||
system.cpu.dtb.read_misses 2631 # DTB read misses
|
||||
system.cpu.dtb.read_acv 0 # DTB read access violations
|
||||
system.cpu.dtb.read_accesses 114516673 # DTB read accesses
|
||||
system.cpu.dtb.write_hits 39451321 # DTB write hits
|
||||
system.cpu.dtb.write_misses 2302 # DTB write misses
|
||||
system.cpu.dtb.write_acv 0 # DTB write access violations
|
||||
system.cpu.dtb.write_accesses 39453623 # DTB write accesses
|
||||
system.cpu.dtb.data_hits 153965363 # DTB hits
|
||||
system.cpu.dtb.data_misses 4933 # DTB misses
|
||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
||||
system.cpu.dtb.data_accesses 153970296 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 601861898 # ITB hits
|
||||
system.cpu.itb.fetch_misses 20 # ITB misses
|
||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
||||
system.cpu.itb.fetch_accesses 601861918 # ITB accesses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.itb.write_hits 0 # DTB write hits
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.itb.write_acv 0 # DTB write access violations
|
||||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.itb.data_hits 0 # DTB hits
|
||||
system.cpu.itb.data_misses 0 # DTB misses
|
||||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 17 # Number of system calls
|
||||
system.cpu.numCycles 1531246064 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 601856964 # Number of instructions committed
|
||||
system.cpu.committedOps 601856964 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 563959696 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 1520 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 2395217 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 58554292 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 563959696 # number of integer instructions
|
||||
system.cpu.num_fp_insts 1520 # number of float instructions
|
||||
system.cpu.num_int_register_reads 801088993 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 463854847 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 169 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 42 # number of times the floating registers were written
|
||||
system.cpu.num_mem_refs 153970296 # number of memory refs
|
||||
system.cpu.num_load_insts 114516673 # Number of load instructions
|
||||
system.cpu.num_store_insts 39453623 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 1531246064 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.icache.replacements 24 # number of replacements
|
||||
system.cpu.icache.tagsinuse 673.337154 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 601861103 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 795 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 757057.991195 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 673.337154 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.328778 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.328778 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 601861103 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 601861103 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 601861103 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 601861103 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 601861103 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 601861103 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 795 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 795 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 795 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 795 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 795 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 795 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 44520000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 44520000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 44520000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 44520000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 44520000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 44520000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 601861898 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 601861898 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 601861898 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 601861898 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 601861898 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 601861898 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000001 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.000001 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000001 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.000001 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000001 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000001 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56000 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 56000 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 56000 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 56000 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 56000 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 56000 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 795 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 795 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 795 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 795 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 795 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 795 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 42135000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 42135000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 42135000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 42135000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 42135000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 42135000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000001 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000001 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000001 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53000 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 451299 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 4094.170317 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 153509968 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 337.091905 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 578392000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 4094.170317 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.999553 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.999553 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 114312810 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 114312810 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 39197158 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 39197158 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 153509968 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 153509968 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 153509968 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 153509968 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 201232 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 201232 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 254163 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 254163 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 455395 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 455395 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 455395 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 455395 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 4126262000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 4126262000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 6081180000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 6081180000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 10207442000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 10207442000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 10207442000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 10207442000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 114514042 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 114514042 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 39451321 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 39451321 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 153965363 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 153965363 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 153965363 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 153965363 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001757 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.001757 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006442 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.006442 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.002958 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.002958 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.002958 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.002958 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20504.999205 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 20504.999205 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 23926.299265 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 23926.299265 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 22414.479737 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 22414.479737 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 22414.479737 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 22414.479737 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 408190 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 408190 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 201232 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 201232 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 254163 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 254163 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 455395 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 455395 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 455395 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 455395 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3522566000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 3522566000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5318691000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 5318691000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8841257000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 8841257000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8841257000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 8841257000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001757 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001757 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006442 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006442 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.002958 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.002958 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17504.999205 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17504.999205 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 20926.299265 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 20926.299265 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19414.479737 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 19414.479737 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19414.479737 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 19414.479737 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 73734 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 17823.514890 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 445709 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 89622 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 4.973210 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::writebacks 16101.078831 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 29.487971 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 1692.948088 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.491366 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.000900 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.051665 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.543931 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 170065 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 170065 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 408190 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 408190 # number of Writeback hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 194094 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 194094 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 364159 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 364159 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 364159 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 364159 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 795 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.data 31167 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 31962 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 60069 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 60069 # number of ReadExReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 795 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 91236 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 92031 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 795 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 91236 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 92031 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 41340000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1620684000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 1662024000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3123588000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 3123588000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 41340000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 4744272000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 4785612000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 41340000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 4744272000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 4785612000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 795 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 201232 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 202027 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 408190 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 408190 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 254163 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 254163 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 795 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 455395 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 456190 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 795 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 455395 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 456190 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.154881 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.158207 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.236340 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.236340 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.200345 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.201738 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.200345 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.201738 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks::writebacks 59341 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 59341 # number of writebacks
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 795 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 31167 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::total 31962 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 60069 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 60069 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 795 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 91236 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 92031 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 795 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 91236 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 92031 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 31800000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1246680000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1278480000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2402760000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2402760000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 31800000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3649440000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 3681240000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 31800000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3649440000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 3681240000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.154881 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.158207 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.236340 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.236340 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.200345 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.201738 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.200345 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.201738 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
@ -0,0 +1,547 @@
|
||||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
full_system=false
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
||||
[system]
|
||||
type=System
|
||||
children=cpu membus physmem
|
||||
boot_osflags=a
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
mem_mode=atomic
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
readfile=
|
||||
symbolfile=
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.membus.slave[0]
|
||||
|
||||
[system.cpu]
|
||||
type=DerivO3CPU
|
||||
children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
|
||||
BTBEntries=4096
|
||||
BTBTagSize=16
|
||||
LFSTSize=1024
|
||||
LQEntries=32
|
||||
LSQCheckLoads=true
|
||||
LSQDepCheckShift=4
|
||||
RASSize=16
|
||||
SQEntries=32
|
||||
SSITSize=1024
|
||||
activity=0
|
||||
backComSize=5
|
||||
cachePorts=200
|
||||
checker=Null
|
||||
choiceCtrBits=2
|
||||
choicePredictorSize=8192
|
||||
clock=500
|
||||
commitToDecodeDelay=1
|
||||
commitToFetchDelay=1
|
||||
commitToIEWDelay=1
|
||||
commitToRenameDelay=1
|
||||
commitWidth=8
|
||||
cpu_id=0
|
||||
decodeToFetchDelay=1
|
||||
decodeToRenameDelay=1
|
||||
decodeWidth=8
|
||||
defer_registration=false
|
||||
dispatchWidth=8
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
fetchToDecodeDelay=1
|
||||
fetchTrapLatency=1
|
||||
fetchWidth=8
|
||||
forwardComSize=5
|
||||
fuPool=system.cpu.fuPool
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
globalCtrBits=2
|
||||
globalHistoryBits=13
|
||||
globalPredictorSize=8192
|
||||
iewToCommitDelay=1
|
||||
iewToDecodeDelay=1
|
||||
iewToFetchDelay=1
|
||||
iewToRenameDelay=1
|
||||
instShiftAmt=2
|
||||
interrupts=system.cpu.interrupts
|
||||
issueToExecuteDelay=1
|
||||
issueWidth=8
|
||||
itb=system.cpu.itb
|
||||
localCtrBits=2
|
||||
localHistoryBits=11
|
||||
localHistoryTableSize=2048
|
||||
localPredictorSize=2048
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
needsTSO=false
|
||||
numIQEntries=64
|
||||
numPhysFloatRegs=256
|
||||
numPhysIntRegs=256
|
||||
numROBEntries=192
|
||||
numRobs=1
|
||||
numThreads=1
|
||||
phase=0
|
||||
predType=tournament
|
||||
profile=0
|
||||
progress_interval=0
|
||||
renameToDecodeDelay=1
|
||||
renameToFetchDelay=1
|
||||
renameToIEWDelay=2
|
||||
renameToROBDelay=1
|
||||
renameWidth=8
|
||||
smtCommitPolicy=RoundRobin
|
||||
smtFetchPolicy=SingleThread
|
||||
smtIQPolicy=Partitioned
|
||||
smtIQThreshold=100
|
||||
smtLSQPolicy=Partitioned
|
||||
smtLSQThreshold=100
|
||||
smtNumFetchingThreads=1
|
||||
smtROBPolicy=Partitioned
|
||||
smtROBThreshold=100
|
||||
squashWidth=8
|
||||
store_set_clear_period=250000
|
||||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
trapLatency=13
|
||||
wbDepth=1
|
||||
wbWidth=8
|
||||
workload=system.cpu.workload
|
||||
dcache_port=system.cpu.dcache.cpu_side
|
||||
icache_port=system.cpu.icache.cpu_side
|
||||
|
||||
[system.cpu.dcache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=262144
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=20
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.dcache_port
|
||||
mem_side=system.cpu.toL2Bus.slave[1]
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
size=64
|
||||
walker=system.cpu.dtb.walker
|
||||
|
||||
[system.cpu.dtb.walker]
|
||||
type=ArmTableWalker
|
||||
max_backoff=100000
|
||||
min_backoff=0
|
||||
sys=system
|
||||
port=system.cpu.toL2Bus.slave[3]
|
||||
|
||||
[system.cpu.fuPool]
|
||||
type=FUPool
|
||||
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
|
||||
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
|
||||
|
||||
[system.cpu.fuPool.FUList0]
|
||||
type=FUDesc
|
||||
children=opList
|
||||
count=6
|
||||
opList=system.cpu.fuPool.FUList0.opList
|
||||
|
||||
[system.cpu.fuPool.FUList0.opList]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=IntAlu
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList1]
|
||||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=2
|
||||
opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=IntMult
|
||||
opLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList1]
|
||||
type=OpDesc
|
||||
issueLat=19
|
||||
opClass=IntDiv
|
||||
opLat=20
|
||||
|
||||
[system.cpu.fuPool.FUList2]
|
||||
type=FUDesc
|
||||
children=opList0 opList1 opList2
|
||||
count=4
|
||||
opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=FloatAdd
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList1]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=FloatCmp
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList2]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=FloatCvt
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList3]
|
||||
type=FUDesc
|
||||
children=opList0 opList1 opList2
|
||||
count=2
|
||||
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=FloatMult
|
||||
opLat=4
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList1]
|
||||
type=OpDesc
|
||||
issueLat=12
|
||||
opClass=FloatDiv
|
||||
opLat=12
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList2]
|
||||
type=OpDesc
|
||||
issueLat=24
|
||||
opClass=FloatSqrt
|
||||
opLat=24
|
||||
|
||||
[system.cpu.fuPool.FUList4]
|
||||
type=FUDesc
|
||||
children=opList
|
||||
count=0
|
||||
opList=system.cpu.fuPool.FUList4.opList
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5]
|
||||
type=FUDesc
|
||||
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
|
||||
count=4
|
||||
opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList00]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdAdd
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList01]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdAddAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList02]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdAlu
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList03]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdCmp
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList04]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdCvt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList05]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdMisc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList06]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdMult
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList07]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdMultAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList08]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdShift
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList09]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdShiftAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList10]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdSqrt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList11]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatAdd
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList12]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatAlu
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList13]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatCmp
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList14]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatCvt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList15]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatDiv
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList16]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatMisc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList17]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatMult
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList18]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatMultAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList19]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatSqrt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList6]
|
||||
type=FUDesc
|
||||
children=opList
|
||||
count=0
|
||||
opList=system.cpu.fuPool.FUList6.opList
|
||||
|
||||
[system.cpu.fuPool.FUList6.opList]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList7]
|
||||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=4
|
||||
opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList1]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList8]
|
||||
type=FUDesc
|
||||
children=opList
|
||||
count=1
|
||||
opList=system.cpu.fuPool.FUList8.opList
|
||||
|
||||
[system.cpu.fuPool.FUList8.opList]
|
||||
type=OpDesc
|
||||
issueLat=3
|
||||
opClass=IprAccess
|
||||
opLat=3
|
||||
|
||||
[system.cpu.icache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=131072
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=20
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.icache_port
|
||||
mem_side=system.cpu.toL2Bus.slave[0]
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=ArmInterrupts
|
||||
|
||||
[system.cpu.itb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
size=64
|
||||
walker=system.cpu.itb.walker
|
||||
|
||||
[system.cpu.itb.walker]
|
||||
type=ArmTableWalker
|
||||
max_backoff=100000
|
||||
min_backoff=0
|
||||
sys=system
|
||||
port=system.cpu.toL2Bus.slave[2]
|
||||
|
||||
[system.cpu.l2cache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=false
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=2097152
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.toL2Bus.master[0]
|
||||
mem_side=system.membus.slave[1]
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
master=system.cpu.l2cache.cpu_side
|
||||
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
|
||||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
|
||||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=gzip input.log 1
|
||||
cwd=build/ARM/tests/opt/long/se/00.gzip/arm/linux/o3-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/cpu2000/binaries/arm/linux/gzip
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
ppid=99
|
||||
simpoint=0
|
||||
system=system
|
||||
uid=100
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
master=system.physmem.port[0]
|
||||
slave=system.system_port system.cpu.l2cache.mem_side
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.membus.master[0]
|
||||
|
||||
2
simulators/gem5/tests/long/se/00.gzip/ref/arm/linux/o3-timing/simerr
Executable file
2
simulators/gem5/tests/long/se/00.gzip/ref/arm/linux/o3-timing/simerr
Executable file
@ -0,0 +1,2 @@
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
hack: be nice to actually delete the event here
|
||||
41
simulators/gem5/tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout
Executable file
41
simulators/gem5/tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout
Executable file
@ -0,0 +1,41 @@
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jun 4 2012 12:14:06
|
||||
gem5 started Jun 4 2012 17:27:39
|
||||
gem5 executing on zizzer
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/00.gzip/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/00.gzip/arm/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
spec_init
|
||||
Loading Input Data
|
||||
Duplicating 262144 bytes
|
||||
Duplicating 524288 bytes
|
||||
Input data 1048576 bytes in length
|
||||
Compressing Input Data, level 1
|
||||
Compressed data 108074 bytes in length
|
||||
Uncompressing Data
|
||||
Uncompressed data 1048576 bytes in length
|
||||
Uncompressed data compared correctly
|
||||
Compressing Input Data, level 3
|
||||
Compressed data 97831 bytes in length
|
||||
Uncompressing Data
|
||||
Uncompressed data 1048576 bytes in length
|
||||
Uncompressed data compared correctly
|
||||
Compressing Input Data, level 5
|
||||
Compressed data 83382 bytes in length
|
||||
Uncompressing Data
|
||||
Uncompressed data 1048576 bytes in length
|
||||
Uncompressed data compared correctly
|
||||
Compressing Input Data, level 7
|
||||
Compressed data 76606 bytes in length
|
||||
Uncompressing Data
|
||||
Uncompressed data 1048576 bytes in length
|
||||
Uncompressed data compared correctly
|
||||
Compressing Input Data, level 9
|
||||
Compressed data 73189 bytes in length
|
||||
Uncompressing Data
|
||||
Uncompressed data 1048576 bytes in length
|
||||
Uncompressed data compared correctly
|
||||
Tested 1MB buffer: OK!
|
||||
Exiting @ tick 164248292500 because target called exit()
|
||||
@ -0,0 +1,724 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.164248 # Number of seconds simulated
|
||||
sim_ticks 164248292500 # Number of ticks simulated
|
||||
final_tick 164248292500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 143439 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 151568 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 41328806 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 231960 # Number of bytes of host memory used
|
||||
host_seconds 3974.18 # Real time elapsed on the host
|
||||
sim_insts 570052728 # Number of instructions simulated
|
||||
sim_ops 602360935 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 51136 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 5799296 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 5850432 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 51136 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 51136 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 3722112 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 3722112 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 799 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 90614 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 91413 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 58158 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 58158 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 311334 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 35308105 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 35619439 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 311334 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 311334 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 22661496 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 22661496 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 22661496 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 311334 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 35308105 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 58280935 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.dtb.read_hits 0 # DTB read hits
|
||||
system.cpu.dtb.read_misses 0 # DTB read misses
|
||||
system.cpu.dtb.write_hits 0 # DTB write hits
|
||||
system.cpu.dtb.write_misses 0 # DTB write misses
|
||||
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
|
||||
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||||
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
|
||||
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.dtb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.dtb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
|
||||
system.cpu.dtb.hits 0 # DTB hits
|
||||
system.cpu.dtb.misses 0 # DTB misses
|
||||
system.cpu.dtb.accesses 0 # DTB accesses
|
||||
system.cpu.itb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.itb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.write_hits 0 # DTB write hits
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
|
||||
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||||
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
|
||||
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.itb.inst_accesses 0 # ITB inst accesses
|
||||
system.cpu.itb.hits 0 # DTB hits
|
||||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 48 # Number of system calls
|
||||
system.cpu.numCycles 328496586 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.BPredUnit.lookups 85500889 # Number of BP lookups
|
||||
system.cpu.BPredUnit.condPredicted 80301573 # Number of conditional branches predicted
|
||||
system.cpu.BPredUnit.condIncorrect 2363462 # Number of conditional branches incorrect
|
||||
system.cpu.BPredUnit.BTBLookups 47194810 # Number of BTB lookups
|
||||
system.cpu.BPredUnit.BTBHits 46809578 # Number of BTB hits
|
||||
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu.BPredUnit.usedRAS 1441693 # Number of times the RAS was used to get a target.
|
||||
system.cpu.BPredUnit.RASInCorrect 2047 # Number of incorrect RAS predictions.
|
||||
system.cpu.fetch.icacheStallCycles 68928725 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.Insts 669724193 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.Branches 85500889 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.predictedBranches 48251271 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.Cycles 130040939 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.SquashCycles 13471504 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.BlockedCycles 117632066 # Number of cycles fetch has spent blocked
|
||||
system.cpu.fetch.MiscStallCycles 26 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
||||
system.cpu.fetch.PendingTrapStallCycles 466 # Number of stall cycles due to pending traps
|
||||
system.cpu.fetch.CacheLines 67495318 # Number of cache lines fetched
|
||||
system.cpu.fetch.IcacheSquashes 807242 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.rateDist::samples 327633093 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 2.178244 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 3.200456 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 197592366 60.31% 60.31% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 20955363 6.40% 66.71% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 4944852 1.51% 68.21% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 14316797 4.37% 72.58% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 8978717 2.74% 75.32% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 9406752 2.87% 78.20% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 4386482 1.34% 79.53% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 5812411 1.77% 81.31% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 61239353 18.69% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::total 327633093 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.branchRate 0.260279 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.rate 2.038755 # Number of inst fetches per cycle
|
||||
system.cpu.decode.IdleCycles 93122772 # Number of cycles decode is idle
|
||||
system.cpu.decode.BlockedCycles 94805335 # Number of cycles decode is blocked
|
||||
system.cpu.decode.RunCycles 108615724 # Number of cycles decode is running
|
||||
system.cpu.decode.UnblockCycles 20060132 # Number of cycles decode is unblocking
|
||||
system.cpu.decode.SquashCycles 11029130 # Number of cycles decode is squashing
|
||||
system.cpu.decode.BranchResolved 4785077 # Number of times decode resolved a branch
|
||||
system.cpu.decode.BranchMispred 1812 # Number of times decode detected a branch misprediction
|
||||
system.cpu.decode.DecodedInsts 705993706 # Number of instructions handled by decode
|
||||
system.cpu.decode.SquashedInsts 5866 # Number of squashed instructions handled by decode
|
||||
system.cpu.rename.SquashCycles 11029130 # Number of cycles rename is squashing
|
||||
system.cpu.rename.IdleCycles 107405098 # Number of cycles rename is idle
|
||||
system.cpu.rename.BlockCycles 13994903 # Number of cycles rename is blocking
|
||||
system.cpu.rename.serializeStallCycles 53643 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RunCycles 114322395 # Number of cycles rename is running
|
||||
system.cpu.rename.UnblockCycles 80827924 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RenamedInsts 697209083 # Number of instructions processed by rename
|
||||
system.cpu.rename.ROBFullEvents 245 # Number of times rename has blocked due to ROB full
|
||||
system.cpu.rename.IQFullEvents 59229209 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.LSQFullEvents 19383033 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.FullRegisterEvents 653 # Number of times there has been no free registers
|
||||
system.cpu.rename.RenamedOperands 723812839 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RenameLookups 3241314962 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.int_rename_lookups 3241314834 # Number of integer rename lookups
|
||||
system.cpu.rename.fp_rename_lookups 128 # Number of floating rename lookups
|
||||
system.cpu.rename.CommittedMaps 627419202 # Number of HB maps that are committed
|
||||
system.cpu.rename.UndoneMaps 96393637 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.serializingInsts 6694 # count of serializing insts renamed
|
||||
system.cpu.rename.tempSerializingInsts 6687 # count of temporary serializing insts renamed
|
||||
system.cpu.rename.skidInsts 169956085 # count of insts added to the skid buffer
|
||||
system.cpu.memDep0.insertedLoads 172904405 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 80621547 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.conflictingLoads 21577919 # Number of conflicting loads.
|
||||
system.cpu.memDep0.conflictingStores 28225780 # Number of conflicting stores.
|
||||
system.cpu.iq.iqInstsAdded 681971655 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqNonSpecInstsAdded 4856 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqInstsIssued 646826004 # Number of instructions issued
|
||||
system.cpu.iq.iqSquashedInstsIssued 1423990 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedInstsExamined 79433587 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedOperandsExamined 197870891 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 1925 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.issued_per_cycle::samples 327633093 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::mean 1.974239 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::stdev 1.736392 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::0 68428283 20.89% 20.89% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::1 84743637 25.87% 46.75% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::2 75345420 23.00% 69.75% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::3 40565003 12.38% 82.13% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::4 28664322 8.75% 90.88% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::5 15213545 4.64% 95.52% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::6 5876273 1.79% 97.32% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::7 6659013 2.03% 99.35% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::8 2137597 0.65% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::total 327633093 # Number of insts issued each cycle
|
||||
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntAlu 205009 5.12% 5.12% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntMult 0 0.00% 5.12% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntDiv 0 0.00% 5.12% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.12% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.12% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.12% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatMult 0 0.00% 5.12% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.12% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.12% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.12% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.12% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.12% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.12% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.12% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.12% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdMult 0 0.00% 5.12% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.12% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdShift 0 0.00% 5.12% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.12% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.12% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.12% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.12% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.12% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.12% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.12% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.12% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.12% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.12% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.12% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::MemRead 2904405 72.49% 77.61% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::MemWrite 897167 22.39% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntAlu 403920644 62.45% 62.45% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntMult 6585 0.00% 62.45% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.45% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.45% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.45% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.45% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.45% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.45% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.45% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.45% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.45% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.45% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.45% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.45% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.45% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.45% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.45% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.45% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.45% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.45% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.45% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.45% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.45% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.45% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.45% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 62.45% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.45% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.45% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.45% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::MemRead 166111461 25.68% 88.13% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::MemWrite 76787311 11.87% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::total 646826004 # Type of FU issued
|
||||
system.cpu.iq.rate 1.969049 # Inst issue rate
|
||||
system.cpu.iq.fu_busy_cnt 4006581 # FU busy when requested
|
||||
system.cpu.iq.fu_busy_rate 0.006194 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.int_inst_queue_reads 1626715636 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_writes 761421594 # Number of integer instruction queue writes
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 638533475 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads
|
||||
system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes
|
||||
system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses
|
||||
system.cpu.iq.int_alu_accesses 650832565 # Number of integer alu accesses
|
||||
system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses
|
||||
system.cpu.iew.lsq.thread0.forwLoads 30420680 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread0.squashedLoads 23951584 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread0.ignoredResponses 127945 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread0.memOrderViolation 11724 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread0.squashedStores 10400307 # Number of stores squashed
|
||||
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
||||
system.cpu.iew.lsq.thread0.rescheduledLoads 12832 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread0.cacheBlocked 12549 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||||
system.cpu.iew.iewSquashCycles 11029130 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewBlockCycles 827373 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewUnblockCycles 62655 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.iewDispatchedInsts 682042744 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewDispSquashedInsts 662438 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispLoadInsts 172904405 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispStoreInsts 80621547 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 3504 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewIQFullEvents 13090 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.iewLSQFullEvents 6258 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.memOrderViolationEvents 11724 # Number of memory order violations
|
||||
system.cpu.iew.predictedTakenIncorrect 1313555 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.iew.predictedNotTakenIncorrect 1583724 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.branchMispredicts 2897279 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewExecutedInsts 642671991 # Number of executed instructions
|
||||
system.cpu.iew.iewExecLoadInsts 163979527 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 4154013 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
||||
system.cpu.iew.exec_nop 66233 # number of nop insts executed
|
||||
system.cpu.iew.exec_refs 239982954 # number of memory reference insts executed
|
||||
system.cpu.iew.exec_branches 74668739 # Number of branches executed
|
||||
system.cpu.iew.exec_stores 76003427 # Number of stores executed
|
||||
system.cpu.iew.exec_rate 1.956404 # Inst execution rate
|
||||
system.cpu.iew.wb_sent 640027985 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.wb_count 638533491 # cumulative count of insts written-back
|
||||
system.cpu.iew.wb_producers 420151811 # num instructions producing a value
|
||||
system.cpu.iew.wb_consumers 654946950 # num instructions consuming a value
|
||||
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
||||
system.cpu.iew.wb_rate 1.943806 # insts written-back per cycle
|
||||
system.cpu.iew.wb_fanout 0.641505 # average fanout of values written-back
|
||||
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||
system.cpu.commit.commitCommittedInsts 570052779 # The number of committed instructions
|
||||
system.cpu.commit.commitCommittedOps 602360986 # The number of committed instructions
|
||||
system.cpu.commit.commitSquashedInsts 79691237 # The number of squashed insts skipped by commit
|
||||
system.cpu.commit.commitNonSpecStalls 2931 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu.commit.branchMispredicts 2423863 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.committed_per_cycle::samples 316603964 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::mean 1.902569 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::stdev 2.239613 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::0 92664555 29.27% 29.27% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::1 103983968 32.84% 62.11% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::2 43054287 13.60% 75.71% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::3 8920631 2.82% 78.53% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::4 25673085 8.11% 86.64% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::5 13110941 4.14% 90.78% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::6 7578873 2.39% 93.17% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::7 1154724 0.36% 93.54% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::8 20462900 6.46% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::total 316603964 # Number of insts commited each cycle
|
||||
system.cpu.commit.committedInsts 570052779 # Number of instructions committed
|
||||
system.cpu.commit.committedOps 602360986 # Number of ops (including micro ops) committed
|
||||
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
||||
system.cpu.commit.refs 219174061 # Number of memory references committed
|
||||
system.cpu.commit.loads 148952821 # Number of loads committed
|
||||
system.cpu.commit.membars 1328 # Number of memory barriers committed
|
||||
system.cpu.commit.branches 70828828 # Number of branches committed
|
||||
system.cpu.commit.fp_insts 16 # Number of committed floating point instructions.
|
||||
system.cpu.commit.int_insts 533523547 # Number of committed integer instructions.
|
||||
system.cpu.commit.function_calls 997573 # Number of function calls committed.
|
||||
system.cpu.commit.bw_lim_events 20462900 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
||||
system.cpu.rob.rob_reads 978192675 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 1375166180 # The number of ROB writes
|
||||
system.cpu.timesIdled 37006 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 863493 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.committedInsts 570052728 # Number of Instructions Simulated
|
||||
system.cpu.committedOps 602360935 # Number of Ops (including micro ops) Simulated
|
||||
system.cpu.committedInsts_total 570052728 # Number of Instructions Simulated
|
||||
system.cpu.cpi 0.576256 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 0.576256 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 1.735338 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 1.735338 # IPC: Total IPC of All Threads
|
||||
system.cpu.int_regfile_reads 3210352058 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 664199500 # number of integer regfile writes
|
||||
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
|
||||
system.cpu.misc_regfile_reads 905055598 # number of misc regfile reads
|
||||
system.cpu.misc_regfile_writes 3110 # number of misc regfile writes
|
||||
system.cpu.icache.replacements 66 # number of replacements
|
||||
system.cpu.icache.tagsinuse 704.852693 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 67494169 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 836 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 80734.651914 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 704.852693 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.344166 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.344166 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 67494169 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 67494169 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 67494169 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 67494169 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 67494169 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 67494169 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 1149 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 1149 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 1149 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 1149 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 1149 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 1149 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 39292000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 39292000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 39292000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 39292000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 39292000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 39292000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 67495318 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 67495318 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 67495318 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 67495318 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 67495318 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 67495318 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000017 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.000017 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000017 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.000017 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000017 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000017 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34196.692776 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 34196.692776 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 34196.692776 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 34196.692776 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 34196.692776 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 34196.692776 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 310 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::total 310 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::cpu.inst 310 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::total 310 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::cpu.inst 310 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::total 310 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 839 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 839 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 839 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 839 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 839 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 839 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 28616000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 28616000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 28616000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 28616000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 28616000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 28616000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000012 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000012 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000012 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000012 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000012 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000012 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34107.270560 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 34107.270560 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34107.270560 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 34107.270560 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34107.270560 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 34107.270560 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 440506 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 4094.673413 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 199917627 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 444602 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 449.655258 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 87177000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 4094.673413 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.999676 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.999676 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 132064751 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 132064751 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 67849620 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 67849620 # number of WriteReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::cpu.data 1690 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::total 1690 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::cpu.data 1554 # number of StoreCondReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::total 1554 # number of StoreCondReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 199914371 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 199914371 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 199914371 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 199914371 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 249324 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 249324 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 1567911 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 1567911 # number of WriteReq misses
|
||||
system.cpu.dcache.LoadLockedReq_misses::cpu.data 16 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.LoadLockedReq_misses::total 16 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 1817235 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 1817235 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 1817235 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 1817235 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 3293272500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 3293272500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 27061002013 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 27061002013 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 203000 # number of LoadLockedReq miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_miss_latency::total 203000 # number of LoadLockedReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 30354274513 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 30354274513 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 30354274513 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 30354274513 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 132314075 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 132314075 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 69417531 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 69417531 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1706 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::total 1706 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::cpu.data 1554 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::total 1554 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 201731606 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 201731606 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 201731606 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 201731606 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001884 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.001884 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.022587 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.022587 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.009379 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.009379 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.009008 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.009008 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.009008 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.009008 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13208.806613 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 13208.806613 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17259.271740 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 17259.271740 # average WriteReq miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12687.500000 # average LoadLockedReq miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12687.500000 # average LoadLockedReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 16703.549355 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 16703.549355 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 16703.549355 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 16703.549355 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 9569014 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 2180 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 4389.455963 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 394908 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 394908 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 51828 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 51828 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1320801 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 1320801 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 16 # number of LoadLockedReq MSHR hits
|
||||
system.cpu.dcache.LoadLockedReq_mshr_hits::total 16 # number of LoadLockedReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 1372629 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 1372629 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 1372629 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 1372629 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 197496 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 197496 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 247110 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 247110 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 444606 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 444606 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 444606 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 444606 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1630743000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 1630743000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2541828513 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 2541828513 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4172571513 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 4172571513 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4172571513 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 4172571513 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001493 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001493 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003560 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.003560 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002204 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.002204 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002204 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.002204 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8257.093815 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 8257.093815 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10286.222787 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10286.222787 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 9384.874502 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 9384.874502 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 9384.874502 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 9384.874502 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 73212 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 17814.608666 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 421435 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 88732 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 4.749527 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::writebacks 15925.956754 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 38.298458 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 1850.353454 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.486022 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.001169 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.056468 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.543659 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 36 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 165185 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 165221 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 394908 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 394908 # number of Writeback hits
|
||||
system.cpu.l2cache.UpgradeReq_hits::cpu.data 2 # number of UpgradeReq hits
|
||||
system.cpu.l2cache.UpgradeReq_hits::total 2 # number of UpgradeReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 188795 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 188795 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 36 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 353980 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 354016 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 36 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 353980 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 354016 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 800 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.data 32306 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 33106 # number of ReadReq misses
|
||||
system.cpu.l2cache.UpgradeReq_misses::cpu.data 1 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_misses::total 1 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 58317 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 58317 # number of ReadExReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 800 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 90623 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 91423 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 800 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 90623 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 91423 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 27465500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1108067500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 1135533000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2001435500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 2001435500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 27465500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 3109503000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 3136968500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 27465500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 3109503000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 3136968500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 836 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 197491 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 198327 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 394908 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 394908 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 3 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_accesses::total 3 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 247112 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 247112 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 836 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 444603 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 445439 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 836 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 444603 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 445439 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.956938 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.163582 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.166926 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.333333 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.333333 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.235994 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.235994 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.956938 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.203829 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.205242 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.956938 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.203829 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.205242 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34331.875000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34299.124002 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 34299.915423 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34319.932438 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34319.932438 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34331.875000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34312.514483 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 34312.683898 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34331.875000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34312.514483 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 34312.683898 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 2005000 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 332 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 6039.156627 # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks::writebacks 58158 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 58158 # number of writebacks
|
||||
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits
|
||||
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 9 # number of ReadReq MSHR hits
|
||||
system.cpu.l2cache.ReadReq_mshr_hits::total 10 # number of ReadReq MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_hits::cpu.data 9 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_hits::total 10 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_hits::cpu.data 9 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_hits::total 10 # number of overall MSHR hits
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 799 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 32297 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::total 33096 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses::total 1 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 58317 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 58317 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 799 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 90614 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 91413 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 799 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 90614 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 91413 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 24875000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1003961000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1028836000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 31000 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 31000 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1821234000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1821234000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24875000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 2825195000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 2850070000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24875000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2825195000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 2850070000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.955742 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.163537 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.166876 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.333333 # mshr miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.333333 # mshr miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.235994 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.235994 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.955742 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.203809 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.205220 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.955742 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.203809 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.205220 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31132.665832 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31085.271078 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31086.415277 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31000 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31229.898657 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31229.898657 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31132.665832 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31178.349924 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31177.950620 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31132.665832 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31178.349924 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31177.950620 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
@ -0,0 +1,135 @@
|
||||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
full_system=false
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
||||
[system]
|
||||
type=System
|
||||
children=cpu membus physmem
|
||||
boot_osflags=a
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
mem_mode=atomic
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
readfile=
|
||||
symbolfile=
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.membus.slave[0]
|
||||
|
||||
[system.cpu]
|
||||
type=AtomicSimpleCPU
|
||||
children=dtb interrupts itb tracer workload
|
||||
checker=Null
|
||||
clock=500
|
||||
cpu_id=0
|
||||
defer_registration=false
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
fastmem=false
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
interrupts=system.cpu.interrupts
|
||||
itb=system.cpu.itb
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
phase=0
|
||||
profile=0
|
||||
progress_interval=0
|
||||
simulate_data_stalls=false
|
||||
simulate_inst_stalls=false
|
||||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
width=1
|
||||
workload=system.cpu.workload
|
||||
dcache_port=system.membus.slave[2]
|
||||
icache_port=system.membus.slave[1]
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
size=64
|
||||
walker=system.cpu.dtb.walker
|
||||
|
||||
[system.cpu.dtb.walker]
|
||||
type=ArmTableWalker
|
||||
max_backoff=100000
|
||||
min_backoff=0
|
||||
sys=system
|
||||
port=system.membus.slave[4]
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=ArmInterrupts
|
||||
|
||||
[system.cpu.itb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
size=64
|
||||
walker=system.cpu.itb.walker
|
||||
|
||||
[system.cpu.itb.walker]
|
||||
type=ArmTableWalker
|
||||
max_backoff=100000
|
||||
min_backoff=0
|
||||
sys=system
|
||||
port=system.membus.slave[3]
|
||||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
|
||||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=gzip input.log 1
|
||||
cwd=build/ARM/tests/opt/long/se/00.gzip/arm/linux/simple-atomic
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/cpu2000/binaries/arm/linux/gzip
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
ppid=99
|
||||
simpoint=0
|
||||
system=system
|
||||
uid=100
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
master=system.physmem.port[0]
|
||||
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.membus.master[0]
|
||||
|
||||
2
simulators/gem5/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/simerr
Executable file
2
simulators/gem5/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/simerr
Executable file
@ -0,0 +1,2 @@
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
hack: be nice to actually delete the event here
|
||||
41
simulators/gem5/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/simout
Executable file
41
simulators/gem5/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/simout
Executable file
@ -0,0 +1,41 @@
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jun 4 2012 12:14:06
|
||||
gem5 started Jun 4 2012 17:27:49
|
||||
gem5 executing on zizzer
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/00.gzip/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/00.gzip/arm/linux/simple-atomic
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
spec_init
|
||||
Loading Input Data
|
||||
Duplicating 262144 bytes
|
||||
Duplicating 524288 bytes
|
||||
Input data 1048576 bytes in length
|
||||
Compressing Input Data, level 1
|
||||
Compressed data 108074 bytes in length
|
||||
Uncompressing Data
|
||||
Uncompressed data 1048576 bytes in length
|
||||
Uncompressed data compared correctly
|
||||
Compressing Input Data, level 3
|
||||
Compressed data 97831 bytes in length
|
||||
Uncompressing Data
|
||||
Uncompressed data 1048576 bytes in length
|
||||
Uncompressed data compared correctly
|
||||
Compressing Input Data, level 5
|
||||
Compressed data 83382 bytes in length
|
||||
Uncompressing Data
|
||||
Uncompressed data 1048576 bytes in length
|
||||
Uncompressed data compared correctly
|
||||
Compressing Input Data, level 7
|
||||
Compressed data 76606 bytes in length
|
||||
Uncompressing Data
|
||||
Uncompressed data 1048576 bytes in length
|
||||
Uncompressed data compared correctly
|
||||
Compressing Input Data, level 9
|
||||
Compressed data 73189 bytes in length
|
||||
Uncompressing Data
|
||||
Uncompressed data 1048576 bytes in length
|
||||
Uncompressed data compared correctly
|
||||
Tested 1MB buffer: OK!
|
||||
Exiting @ tick 301191370000 because target called exit()
|
||||
@ -0,0 +1,102 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.301191 # Number of seconds simulated
|
||||
sim_ticks 301191370000 # Number of ticks simulated
|
||||
final_tick 301191370000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 2291609 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2421488 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1210789798 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 221260 # Number of bytes of host memory used
|
||||
host_seconds 248.76 # Real time elapsed on the host
|
||||
sim_insts 570051644 # Number of instructions simulated
|
||||
sim_ops 602359851 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 2280298136 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 399862021 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 2680160157 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 2280298136 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 2280298136 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::cpu.data 236359611 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 236359611 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 570074534 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 147793179 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 717867713 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::cpu.data 69418858 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 69418858 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 7570927866 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 1327601189 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 8898529055 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 7570927866 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 7570927866 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::cpu.data 784748949 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 784748949 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 7570927866 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 2112350138 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 9683278004 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.dtb.read_hits 0 # DTB read hits
|
||||
system.cpu.dtb.read_misses 0 # DTB read misses
|
||||
system.cpu.dtb.write_hits 0 # DTB write hits
|
||||
system.cpu.dtb.write_misses 0 # DTB write misses
|
||||
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
|
||||
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||||
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
|
||||
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.dtb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.dtb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
|
||||
system.cpu.dtb.hits 0 # DTB hits
|
||||
system.cpu.dtb.misses 0 # DTB misses
|
||||
system.cpu.dtb.accesses 0 # DTB accesses
|
||||
system.cpu.itb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.itb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.write_hits 0 # DTB write hits
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
|
||||
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||||
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
|
||||
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.itb.inst_accesses 0 # ITB inst accesses
|
||||
system.cpu.itb.hits 0 # DTB hits
|
||||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 48 # Number of system calls
|
||||
system.cpu.numCycles 602382741 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 570051644 # Number of instructions committed
|
||||
system.cpu.committedOps 602359851 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 533522639 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 1993546 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 67017095 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 533522639 # number of integer instructions
|
||||
system.cpu.num_fp_insts 16 # number of float instructions
|
||||
system.cpu.num_int_register_reads 2770243005 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 614470985 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 16 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
|
||||
system.cpu.num_mem_refs 219173607 # number of memory refs
|
||||
system.cpu.num_load_insts 148952594 # Number of load instructions
|
||||
system.cpu.num_store_insts 70221013 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 602382741 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
@ -0,0 +1,216 @@
|
||||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
full_system=false
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
||||
[system]
|
||||
type=System
|
||||
children=cpu membus physmem
|
||||
boot_osflags=a
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
mem_mode=atomic
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
readfile=
|
||||
symbolfile=
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.membus.slave[0]
|
||||
|
||||
[system.cpu]
|
||||
type=TimingSimpleCPU
|
||||
children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
|
||||
checker=Null
|
||||
clock=500
|
||||
cpu_id=0
|
||||
defer_registration=false
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
interrupts=system.cpu.interrupts
|
||||
itb=system.cpu.itb
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
phase=0
|
||||
profile=0
|
||||
progress_interval=0
|
||||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
workload=system.cpu.workload
|
||||
dcache_port=system.cpu.dcache.cpu_side
|
||||
icache_port=system.cpu.icache.cpu_side
|
||||
|
||||
[system.cpu.dcache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=262144
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.dcache_port
|
||||
mem_side=system.cpu.toL2Bus.slave[1]
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
size=64
|
||||
walker=system.cpu.dtb.walker
|
||||
|
||||
[system.cpu.dtb.walker]
|
||||
type=ArmTableWalker
|
||||
max_backoff=100000
|
||||
min_backoff=0
|
||||
sys=system
|
||||
port=system.cpu.toL2Bus.slave[3]
|
||||
|
||||
[system.cpu.icache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=131072
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.icache_port
|
||||
mem_side=system.cpu.toL2Bus.slave[0]
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=ArmInterrupts
|
||||
|
||||
[system.cpu.itb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
size=64
|
||||
walker=system.cpu.itb.walker
|
||||
|
||||
[system.cpu.itb.walker]
|
||||
type=ArmTableWalker
|
||||
max_backoff=100000
|
||||
min_backoff=0
|
||||
sys=system
|
||||
port=system.cpu.toL2Bus.slave[2]
|
||||
|
||||
[system.cpu.l2cache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=false
|
||||
latency=10000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=2097152
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.toL2Bus.master[0]
|
||||
mem_side=system.membus.slave[1]
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
master=system.cpu.l2cache.cpu_side
|
||||
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
|
||||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
|
||||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=gzip input.log 1
|
||||
cwd=build/ARM/tests/opt/long/se/00.gzip/arm/linux/simple-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/cpu2000/binaries/arm/linux/gzip
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
ppid=99
|
||||
simpoint=0
|
||||
system=system
|
||||
uid=100
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
master=system.physmem.port[0]
|
||||
slave=system.system_port system.cpu.l2cache.mem_side
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.membus.master[0]
|
||||
|
||||
2
simulators/gem5/tests/long/se/00.gzip/ref/arm/linux/simple-timing/simerr
Executable file
2
simulators/gem5/tests/long/se/00.gzip/ref/arm/linux/simple-timing/simerr
Executable file
@ -0,0 +1,2 @@
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
hack: be nice to actually delete the event here
|
||||
41
simulators/gem5/tests/long/se/00.gzip/ref/arm/linux/simple-timing/simout
Executable file
41
simulators/gem5/tests/long/se/00.gzip/ref/arm/linux/simple-timing/simout
Executable file
@ -0,0 +1,41 @@
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jun 4 2012 12:14:06
|
||||
gem5 started Jun 4 2012 17:27:51
|
||||
gem5 executing on zizzer
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/00.gzip/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/00.gzip/arm/linux/simple-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
spec_init
|
||||
Loading Input Data
|
||||
Duplicating 262144 bytes
|
||||
Duplicating 524288 bytes
|
||||
Input data 1048576 bytes in length
|
||||
Compressing Input Data, level 1
|
||||
Compressed data 108074 bytes in length
|
||||
Uncompressing Data
|
||||
Uncompressed data 1048576 bytes in length
|
||||
Uncompressed data compared correctly
|
||||
Compressing Input Data, level 3
|
||||
Compressed data 97831 bytes in length
|
||||
Uncompressing Data
|
||||
Uncompressed data 1048576 bytes in length
|
||||
Uncompressed data compared correctly
|
||||
Compressing Input Data, level 5
|
||||
Compressed data 83382 bytes in length
|
||||
Uncompressing Data
|
||||
Uncompressed data 1048576 bytes in length
|
||||
Uncompressed data compared correctly
|
||||
Compressing Input Data, level 7
|
||||
Compressed data 76606 bytes in length
|
||||
Uncompressing Data
|
||||
Uncompressed data 1048576 bytes in length
|
||||
Uncompressed data compared correctly
|
||||
Compressing Input Data, level 9
|
||||
Compressed data 73189 bytes in length
|
||||
Uncompressing Data
|
||||
Uncompressed data 1048576 bytes in length
|
||||
Uncompressed data compared correctly
|
||||
Tested 1MB buffer: OK!
|
||||
Exiting @ tick 796762926000 because target called exit()
|
||||
@ -0,0 +1,427 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.796763 # Number of seconds simulated
|
||||
sim_ticks 796762926000 # Number of ticks simulated
|
||||
final_tick 796762926000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1154549 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1219245 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1618008338 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 230404 # Number of bytes of host memory used
|
||||
host_seconds 492.43 # Real time elapsed on the host
|
||||
sim_insts 568539343 # Number of instructions simulated
|
||||
sim_ops 600398281 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 39424 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 5720064 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 5759488 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 39424 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 39424 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 3704704 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 3704704 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 616 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 89376 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 89992 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 57886 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 57886 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 49480 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 7179129 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 7228609 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 49480 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 49480 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 4649694 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 4649694 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 4649694 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 49480 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 7179129 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 11878304 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.dtb.read_hits 0 # DTB read hits
|
||||
system.cpu.dtb.read_misses 0 # DTB read misses
|
||||
system.cpu.dtb.write_hits 0 # DTB write hits
|
||||
system.cpu.dtb.write_misses 0 # DTB write misses
|
||||
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
|
||||
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||||
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
|
||||
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.dtb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.dtb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
|
||||
system.cpu.dtb.hits 0 # DTB hits
|
||||
system.cpu.dtb.misses 0 # DTB misses
|
||||
system.cpu.dtb.accesses 0 # DTB accesses
|
||||
system.cpu.itb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.itb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.write_hits 0 # DTB write hits
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
|
||||
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||||
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
|
||||
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.itb.inst_accesses 0 # ITB inst accesses
|
||||
system.cpu.itb.hits 0 # DTB hits
|
||||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 48 # Number of system calls
|
||||
system.cpu.numCycles 1593525852 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 568539343 # Number of instructions committed
|
||||
system.cpu.committedOps 600398281 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 533522639 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 1993546 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 67017095 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 533522639 # number of integer instructions
|
||||
system.cpu.num_fp_insts 16 # number of float instructions
|
||||
system.cpu.num_int_register_reads 3212467108 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 614470985 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 16 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
|
||||
system.cpu.num_mem_refs 219173607 # number of memory refs
|
||||
system.cpu.num_load_insts 148952594 # Number of load instructions
|
||||
system.cpu.num_store_insts 70221013 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 1593525852 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.icache.replacements 12 # number of replacements
|
||||
system.cpu.icache.tagsinuse 577.728532 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 570073892 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 643 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 886584.590980 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 577.728532 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.282094 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.282094 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 570073892 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 570073892 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 570073892 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 570073892 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 570073892 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 570073892 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 643 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 643 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 643 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 643 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 643 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 643 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 34874000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 34874000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 34874000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 34874000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 34874000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 34874000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 570074535 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 570074535 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 570074535 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 570074535 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 570074535 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 570074535 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000001 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.000001 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000001 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.000001 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000001 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000001 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54236.391913 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 54236.391913 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 54236.391913 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 54236.391913 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 54236.391913 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 54236.391913 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 643 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 643 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 643 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 643 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 643 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 643 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 32945000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 32945000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 32945000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 32945000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 32945000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 32945000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000001 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000001 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000001 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51236.391913 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51236.391913 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51236.391913 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 51236.391913 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51236.391913 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 51236.391913 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 433468 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 4094.222434 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 216774473 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 437564 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 495.412038 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 537031000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 4094.222434 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.999566 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.999566 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 147602036 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 147602036 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 69169783 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 69169783 # number of WriteReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::cpu.data 1327 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::total 1327 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::cpu.data 1327 # number of StoreCondReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::total 1327 # number of StoreCondReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 216771819 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 216771819 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 216771819 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 216771819 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 189816 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 189816 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 247748 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 247748 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 437564 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 437564 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 437564 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 437564 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 3956274000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 3956274000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 5923414000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 5923414000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 9879688000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 9879688000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 9879688000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 9879688000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 147791852 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 147791852 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 69417531 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 69417531 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1327 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::total 1327 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::cpu.data 1327 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::total 1327 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 217209383 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 217209383 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 217209383 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 217209383 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001284 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.001284 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003569 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.003569 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.002014 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.002014 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.002014 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.002014 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20842.679226 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 20842.679226 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 23909.028529 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 23909.028529 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 22578.841038 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 22578.841038 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 22578.841038 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 22578.841038 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 392392 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 392392 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 189816 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 189816 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 247748 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 247748 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 437564 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 437564 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 437564 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 437564 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3386826000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 3386826000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5180170000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 5180170000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8566996000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 8566996000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8566996000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 8566996000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001284 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001284 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003569 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.003569 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002014 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.002014 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002014 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.002014 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17842.679226 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17842.679226 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 20909.028529 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 20909.028529 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19578.841038 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 19578.841038 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19578.841038 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 19578.841038 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 71804 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 17904.014680 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 411836 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 87286 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 4.718237 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::writebacks 16141.835335 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 24.672100 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 1737.507245 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.492610 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.000753 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.053025 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.546387 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 27 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 158891 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 158918 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 392392 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 392392 # number of Writeback hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 189297 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 189297 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 27 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 348188 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 348215 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 27 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 348188 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 348215 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 616 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.data 30925 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 31541 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 58451 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 58451 # number of ReadExReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 616 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 89376 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 89992 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 616 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 89376 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 89992 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 32032000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1608100000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 1640132000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3039452000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 3039452000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 32032000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 4647552000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 4679584000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 32032000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 4647552000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 4679584000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 643 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 189816 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 190459 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 392392 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 392392 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 247748 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 247748 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 643 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 437564 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 438207 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 643 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 437564 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 438207 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.958009 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.162921 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.165605 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.235929 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.235929 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.958009 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.204258 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.205364 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.958009 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.204258 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.205364 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks::writebacks 57886 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 57886 # number of writebacks
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 616 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 30925 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::total 31541 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 58451 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 58451 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 616 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 89376 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 89992 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 616 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 89376 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 89992 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 24640000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1237000000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1261640000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2338040000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2338040000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24640000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3575040000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 3599680000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24640000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3575040000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 3599680000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.958009 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.162921 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.165605 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.235929 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.235929 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.958009 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.204258 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.205364 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.958009 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.204258 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.205364 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
@ -0,0 +1,529 @@
|
||||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
full_system=false
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
||||
[system]
|
||||
type=System
|
||||
children=cpu membus physmem
|
||||
boot_osflags=a
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
mem_mode=atomic
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
readfile=
|
||||
symbolfile=
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.membus.slave[0]
|
||||
|
||||
[system.cpu]
|
||||
type=DerivO3CPU
|
||||
children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
|
||||
BTBEntries=4096
|
||||
BTBTagSize=16
|
||||
LFSTSize=1024
|
||||
LQEntries=32
|
||||
LSQCheckLoads=true
|
||||
LSQDepCheckShift=4
|
||||
RASSize=16
|
||||
SQEntries=32
|
||||
SSITSize=1024
|
||||
activity=0
|
||||
backComSize=5
|
||||
cachePorts=200
|
||||
checker=Null
|
||||
choiceCtrBits=2
|
||||
choicePredictorSize=8192
|
||||
clock=500
|
||||
commitToDecodeDelay=1
|
||||
commitToFetchDelay=1
|
||||
commitToIEWDelay=1
|
||||
commitToRenameDelay=1
|
||||
commitWidth=8
|
||||
cpu_id=0
|
||||
decodeToFetchDelay=1
|
||||
decodeToRenameDelay=1
|
||||
decodeWidth=8
|
||||
defer_registration=false
|
||||
dispatchWidth=8
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
fetchToDecodeDelay=1
|
||||
fetchTrapLatency=1
|
||||
fetchWidth=8
|
||||
forwardComSize=5
|
||||
fuPool=system.cpu.fuPool
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
globalCtrBits=2
|
||||
globalHistoryBits=13
|
||||
globalPredictorSize=8192
|
||||
iewToCommitDelay=1
|
||||
iewToDecodeDelay=1
|
||||
iewToFetchDelay=1
|
||||
iewToRenameDelay=1
|
||||
instShiftAmt=2
|
||||
interrupts=system.cpu.interrupts
|
||||
issueToExecuteDelay=1
|
||||
issueWidth=8
|
||||
itb=system.cpu.itb
|
||||
localCtrBits=2
|
||||
localHistoryBits=11
|
||||
localHistoryTableSize=2048
|
||||
localPredictorSize=2048
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
needsTSO=false
|
||||
numIQEntries=64
|
||||
numPhysFloatRegs=256
|
||||
numPhysIntRegs=256
|
||||
numROBEntries=192
|
||||
numRobs=1
|
||||
numThreads=1
|
||||
phase=0
|
||||
predType=tournament
|
||||
profile=0
|
||||
progress_interval=0
|
||||
renameToDecodeDelay=1
|
||||
renameToFetchDelay=1
|
||||
renameToIEWDelay=2
|
||||
renameToROBDelay=1
|
||||
renameWidth=8
|
||||
smtCommitPolicy=RoundRobin
|
||||
smtFetchPolicy=SingleThread
|
||||
smtIQPolicy=Partitioned
|
||||
smtIQThreshold=100
|
||||
smtLSQPolicy=Partitioned
|
||||
smtLSQThreshold=100
|
||||
smtNumFetchingThreads=1
|
||||
smtROBPolicy=Partitioned
|
||||
smtROBThreshold=100
|
||||
squashWidth=8
|
||||
store_set_clear_period=250000
|
||||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
trapLatency=13
|
||||
wbDepth=1
|
||||
wbWidth=8
|
||||
workload=system.cpu.workload
|
||||
dcache_port=system.cpu.dcache.cpu_side
|
||||
icache_port=system.cpu.icache.cpu_side
|
||||
|
||||
[system.cpu.dcache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=262144
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=20
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.dcache_port
|
||||
mem_side=system.cpu.toL2Bus.slave[1]
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=SparcTLB
|
||||
size=64
|
||||
|
||||
[system.cpu.fuPool]
|
||||
type=FUPool
|
||||
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
|
||||
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
|
||||
|
||||
[system.cpu.fuPool.FUList0]
|
||||
type=FUDesc
|
||||
children=opList
|
||||
count=6
|
||||
opList=system.cpu.fuPool.FUList0.opList
|
||||
|
||||
[system.cpu.fuPool.FUList0.opList]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=IntAlu
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList1]
|
||||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=2
|
||||
opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=IntMult
|
||||
opLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList1]
|
||||
type=OpDesc
|
||||
issueLat=19
|
||||
opClass=IntDiv
|
||||
opLat=20
|
||||
|
||||
[system.cpu.fuPool.FUList2]
|
||||
type=FUDesc
|
||||
children=opList0 opList1 opList2
|
||||
count=4
|
||||
opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=FloatAdd
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList1]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=FloatCmp
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList2]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=FloatCvt
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList3]
|
||||
type=FUDesc
|
||||
children=opList0 opList1 opList2
|
||||
count=2
|
||||
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=FloatMult
|
||||
opLat=4
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList1]
|
||||
type=OpDesc
|
||||
issueLat=12
|
||||
opClass=FloatDiv
|
||||
opLat=12
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList2]
|
||||
type=OpDesc
|
||||
issueLat=24
|
||||
opClass=FloatSqrt
|
||||
opLat=24
|
||||
|
||||
[system.cpu.fuPool.FUList4]
|
||||
type=FUDesc
|
||||
children=opList
|
||||
count=0
|
||||
opList=system.cpu.fuPool.FUList4.opList
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5]
|
||||
type=FUDesc
|
||||
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
|
||||
count=4
|
||||
opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList00]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdAdd
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList01]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdAddAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList02]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdAlu
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList03]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdCmp
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList04]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdCvt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList05]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdMisc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList06]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdMult
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList07]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdMultAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList08]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdShift
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList09]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdShiftAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList10]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdSqrt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList11]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatAdd
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList12]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatAlu
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList13]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatCmp
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList14]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatCvt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList15]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatDiv
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList16]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatMisc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList17]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatMult
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList18]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatMultAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList19]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatSqrt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList6]
|
||||
type=FUDesc
|
||||
children=opList
|
||||
count=0
|
||||
opList=system.cpu.fuPool.FUList6.opList
|
||||
|
||||
[system.cpu.fuPool.FUList6.opList]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList7]
|
||||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=4
|
||||
opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList1]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList8]
|
||||
type=FUDesc
|
||||
children=opList
|
||||
count=1
|
||||
opList=system.cpu.fuPool.FUList8.opList
|
||||
|
||||
[system.cpu.fuPool.FUList8.opList]
|
||||
type=OpDesc
|
||||
issueLat=3
|
||||
opClass=IprAccess
|
||||
opLat=3
|
||||
|
||||
[system.cpu.icache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=131072
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=20
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.icache_port
|
||||
mem_side=system.cpu.toL2Bus.slave[0]
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=SparcInterrupts
|
||||
|
||||
[system.cpu.itb]
|
||||
type=SparcTLB
|
||||
size=64
|
||||
|
||||
[system.cpu.l2cache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=false
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=2097152
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.toL2Bus.master[0]
|
||||
mem_side=system.membus.slave[1]
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
master=system.cpu.l2cache.cpu_side
|
||||
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
|
||||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
|
||||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=gzip input.log 1
|
||||
cwd=build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/o3-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/cpu2000/binaries/sparc/linux/gzip
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
ppid=99
|
||||
simpoint=0
|
||||
system=system
|
||||
uid=100
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
master=system.physmem.port[0]
|
||||
slave=system.system_port system.cpu.l2cache.mem_side
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.membus.master[0]
|
||||
|
||||
2
simulators/gem5/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simerr
Executable file
2
simulators/gem5/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simerr
Executable file
@ -0,0 +1,2 @@
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
hack: be nice to actually delete the event here
|
||||
41
simulators/gem5/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout
Executable file
41
simulators/gem5/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout
Executable file
@ -0,0 +1,41 @@
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jun 4 2012 12:01:47
|
||||
gem5 started Jun 4 2012 14:45:35
|
||||
gem5 executing on zizzer
|
||||
command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
spec_init
|
||||
Loading Input Data
|
||||
Duplicating 262144 bytes
|
||||
Duplicating 524288 bytes
|
||||
Input data 1048576 bytes in length
|
||||
Compressing Input Data, level 1
|
||||
Compressed data 108074 bytes in length
|
||||
Uncompressing Data
|
||||
Uncompressed data 1048576 bytes in length
|
||||
Uncompressed data compared correctly
|
||||
Compressing Input Data, level 3
|
||||
Compressed data 97831 bytes in length
|
||||
Uncompressing Data
|
||||
Uncompressed data 1048576 bytes in length
|
||||
Uncompressed data compared correctly
|
||||
Compressing Input Data, level 5
|
||||
Compressed data 83382 bytes in length
|
||||
Uncompressing Data
|
||||
Uncompressed data 1048576 bytes in length
|
||||
Uncompressed data compared correctly
|
||||
Compressing Input Data, level 7
|
||||
Compressed data 76606 bytes in length
|
||||
Uncompressing Data
|
||||
Uncompressed data 1048576 bytes in length
|
||||
Uncompressed data compared correctly
|
||||
Compressing Input Data, level 9
|
||||
Compressed data 73189 bytes in length
|
||||
Uncompressing Data
|
||||
Uncompressed data 1048576 bytes in length
|
||||
Uncompressed data compared correctly
|
||||
Tested 1MB buffer: OK!
|
||||
Exiting @ tick 388554296500 because target called exit()
|
||||
@ -0,0 +1,657 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.388554 # Number of seconds simulated
|
||||
sim_ticks 388554296500 # Number of ticks simulated
|
||||
final_tick 388554296500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 160259 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 160764 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 44440455 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 224388 # Number of bytes of host memory used
|
||||
host_seconds 8743.26 # Real time elapsed on the host
|
||||
sim_insts 1401188958 # Number of instructions simulated
|
||||
sim_ops 1405604152 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 85056 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 5902400 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 5987456 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 85056 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 85056 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 3788160 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 3788160 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 1329 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 92225 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 93554 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 59190 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 59190 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 218904 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 15190670 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 15409574 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 218904 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 218904 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 9749371 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 9749371 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 9749371 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 218904 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 15190670 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 25158945 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu.workload.num_syscalls 49 # Number of system calls
|
||||
system.cpu.numCycles 777108594 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.BPredUnit.lookups 98192290 # Number of BP lookups
|
||||
system.cpu.BPredUnit.condPredicted 88412741 # Number of conditional branches predicted
|
||||
system.cpu.BPredUnit.condIncorrect 3784661 # Number of conditional branches incorrect
|
||||
system.cpu.BPredUnit.BTBLookups 66025458 # Number of BTB lookups
|
||||
system.cpu.BPredUnit.BTBHits 65664289 # Number of BTB hits
|
||||
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu.BPredUnit.usedRAS 1392 # Number of times the RAS was used to get a target.
|
||||
system.cpu.BPredUnit.RASInCorrect 307 # Number of incorrect RAS predictions.
|
||||
system.cpu.fetch.icacheStallCycles 165888791 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.Insts 1648818264 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.Branches 98192290 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.predictedBranches 65665681 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.Cycles 330417282 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.SquashCycles 21685615 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.BlockedCycles 262756820 # Number of cycles fetch has spent blocked
|
||||
system.cpu.fetch.MiscStallCycles 127 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
||||
system.cpu.fetch.PendingTrapStallCycles 2717 # Number of stall cycles due to pending traps
|
||||
system.cpu.fetch.CacheLines 162823525 # Number of cache lines fetched
|
||||
system.cpu.fetch.IcacheSquashes 752138 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.rateDist::samples 776762747 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 2.128564 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 3.147845 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 446345465 57.46% 57.46% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 74375625 9.58% 67.04% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 37980087 4.89% 71.93% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 9083330 1.17% 73.10% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 28159964 3.63% 76.72% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 18826619 2.42% 79.15% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 11515688 1.48% 80.63% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 3871202 0.50% 81.13% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 146604767 18.87% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::total 776762747 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.branchRate 0.126356 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.rate 2.121735 # Number of inst fetches per cycle
|
||||
system.cpu.decode.IdleCycles 217443439 # Number of cycles decode is idle
|
||||
system.cpu.decode.BlockedCycles 213446803 # Number of cycles decode is blocked
|
||||
system.cpu.decode.RunCycles 285373546 # Number of cycles decode is running
|
||||
system.cpu.decode.UnblockCycles 42801949 # Number of cycles decode is unblocking
|
||||
system.cpu.decode.SquashCycles 17697010 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DecodedInsts 1642584513 # Number of instructions handled by decode
|
||||
system.cpu.rename.SquashCycles 17697010 # Number of cycles rename is squashing
|
||||
system.cpu.rename.IdleCycles 241484414 # Number of cycles rename is idle
|
||||
system.cpu.rename.BlockCycles 36505924 # Number of cycles rename is blocking
|
||||
system.cpu.rename.serializeStallCycles 52170824 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RunCycles 303041095 # Number of cycles rename is running
|
||||
system.cpu.rename.UnblockCycles 125863480 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RenamedInsts 1631270043 # Number of instructions processed by rename
|
||||
system.cpu.rename.ROBFullEvents 22 # Number of times rename has blocked due to ROB full
|
||||
system.cpu.rename.IQFullEvents 30873302 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.LSQFullEvents 72930971 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.FullRegisterEvents 3136079 # Number of times there has been no free registers
|
||||
system.cpu.rename.RenamedOperands 1360952247 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RenameLookups 2755876290 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.int_rename_lookups 2721902713 # Number of integer rename lookups
|
||||
system.cpu.rename.fp_rename_lookups 33973577 # Number of floating rename lookups
|
||||
system.cpu.rename.CommittedMaps 1244770452 # Number of HB maps that are committed
|
||||
system.cpu.rename.UndoneMaps 116181795 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.serializingInsts 2680713 # count of serializing insts renamed
|
||||
system.cpu.rename.tempSerializingInsts 2696169 # count of temporary serializing insts renamed
|
||||
system.cpu.rename.skidInsts 271856221 # count of insts added to the skid buffer
|
||||
system.cpu.memDep0.insertedLoads 438705092 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 180250261 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.conflictingLoads 255265663 # Number of conflicting loads.
|
||||
system.cpu.memDep0.conflictingStores 83296081 # Number of conflicting stores.
|
||||
system.cpu.iq.iqInstsAdded 1517040384 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqNonSpecInstsAdded 2636529 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqInstsIssued 1460865188 # Number of instructions issued
|
||||
system.cpu.iq.iqSquashedInstsIssued 67073 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedInstsExamined 113729678 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedOperandsExamined 136677669 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 392858 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.issued_per_cycle::samples 776762747 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::mean 1.880710 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::stdev 1.430803 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::0 147116911 18.94% 18.94% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::1 184456460 23.75% 42.69% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::2 210881862 27.15% 69.84% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::3 131212379 16.89% 86.73% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::4 70768732 9.11% 95.84% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::5 20345025 2.62% 98.46% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::6 7834706 1.01% 99.47% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::7 3973798 0.51% 99.98% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::8 172874 0.02% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::total 776762747 # Number of insts issued each cycle
|
||||
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntAlu 106719 6.05% 6.05% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntMult 0 0.00% 6.05% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntDiv 0 0.00% 6.05% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatAdd 167382 9.50% 15.55% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatCmp 0 0.00% 15.55% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatCvt 0 0.00% 15.55% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatMult 0 0.00% 15.55% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatDiv 0 0.00% 15.55% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 15.55% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdAdd 0 0.00% 15.55% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 15.55% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdAlu 0 0.00% 15.55% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdCmp 0 0.00% 15.55% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdCvt 0 0.00% 15.55% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdMisc 0 0.00% 15.55% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdMult 0 0.00% 15.55% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 15.55% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdShift 0 0.00% 15.55% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 15.55% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 15.55% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 15.55% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 15.55% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 15.55% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 15.55% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 15.55% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 15.55% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 15.55% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 15.55% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 15.55% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::MemRead 1159607 65.79% 81.34% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::MemWrite 328958 18.66% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntAlu 867175983 59.36% 59.36% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntMult 0 0.00% 59.36% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 59.36% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatAdd 2649316 0.18% 59.54% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.54% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.54% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.54% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.54% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.54% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.54% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.54% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.54% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.54% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.54% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.54% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.54% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.54% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.54% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.54% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.54% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.54% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.54% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.54% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.54% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.54% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.54% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.54% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.54% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.54% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::MemRead 419771639 28.73% 88.28% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::MemWrite 171268250 11.72% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::total 1460865188 # Type of FU issued
|
||||
system.cpu.iq.rate 1.879873 # Inst issue rate
|
||||
system.cpu.iq.fu_busy_cnt 1762666 # FU busy when requested
|
||||
system.cpu.iq.fu_busy_rate 0.001207 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.int_inst_queue_reads 3682454836 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_writes 1624473314 # Number of integer instruction queue writes
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 1444449939 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.fp_inst_queue_reads 17868026 # Number of floating instruction queue reads
|
||||
system.cpu.iq.fp_inst_queue_writes 9170759 # Number of floating instruction queue writes
|
||||
system.cpu.iq.fp_inst_queue_wakeup_accesses 8547404 # Number of floating instruction queue wakeup accesses
|
||||
system.cpu.iq.int_alu_accesses 1453439561 # Number of integer alu accesses
|
||||
system.cpu.iq.fp_alu_accesses 9188293 # Number of floating point alu accesses
|
||||
system.cpu.iew.lsq.thread0.forwLoads 215395742 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread0.squashedLoads 36192248 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread0.ignoredResponses 54154 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread0.memOrderViolation 246172 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread0.squashedStores 13402119 # Number of stores squashed
|
||||
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
||||
system.cpu.iew.lsq.thread0.rescheduledLoads 3683 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread0.cacheBlocked 46778 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||||
system.cpu.iew.iewSquashCycles 17697010 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewBlockCycles 2543877 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewUnblockCycles 131664 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.iewDispatchedInsts 1613864484 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewDispSquashedInsts 4125995 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispLoadInsts 438705092 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispStoreInsts 180250261 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 2550339 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewIQFullEvents 45235 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.iewLSQFullEvents 9141 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.memOrderViolationEvents 246172 # Number of memory order violations
|
||||
system.cpu.iew.predictedTakenIncorrect 2357197 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.iew.predictedNotTakenIncorrect 1561193 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.branchMispredicts 3918390 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewExecutedInsts 1455317466 # Number of executed instructions
|
||||
system.cpu.iew.iewExecLoadInsts 417050361 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 5547722 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
||||
system.cpu.iew.exec_nop 94187571 # number of nop insts executed
|
||||
system.cpu.iew.exec_refs 587627055 # number of memory reference insts executed
|
||||
system.cpu.iew.exec_branches 89112581 # Number of branches executed
|
||||
system.cpu.iew.exec_stores 170576694 # Number of stores executed
|
||||
system.cpu.iew.exec_rate 1.872734 # Inst execution rate
|
||||
system.cpu.iew.wb_sent 1453915806 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.wb_count 1452997343 # cumulative count of insts written-back
|
||||
system.cpu.iew.wb_producers 1154378236 # num instructions producing a value
|
||||
system.cpu.iew.wb_consumers 1205398776 # num instructions consuming a value
|
||||
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
||||
system.cpu.iew.wb_rate 1.869748 # insts written-back per cycle
|
||||
system.cpu.iew.wb_fanout 0.957673 # average fanout of values written-back
|
||||
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||
system.cpu.commit.commitCommittedInsts 1485108101 # The number of committed instructions
|
||||
system.cpu.commit.commitCommittedOps 1489523295 # The number of committed instructions
|
||||
system.cpu.commit.commitSquashedInsts 124237250 # The number of squashed insts skipped by commit
|
||||
system.cpu.commit.commitNonSpecStalls 2243671 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu.commit.branchMispredicts 3784661 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.committed_per_cycle::samples 759066348 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::mean 1.962310 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::stdev 2.504596 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::0 240497837 31.68% 31.68% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::1 276436046 36.42% 68.10% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::2 43137006 5.68% 73.78% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::3 54981228 7.24% 81.03% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::4 19702278 2.60% 83.62% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::5 13356697 1.76% 85.38% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::6 30450827 4.01% 89.39% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::7 10463438 1.38% 90.77% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::8 70040991 9.23% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::total 759066348 # Number of insts commited each cycle
|
||||
system.cpu.commit.committedInsts 1485108101 # Number of instructions committed
|
||||
system.cpu.commit.committedOps 1489523295 # Number of ops (including micro ops) committed
|
||||
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
||||
system.cpu.commit.refs 569360986 # Number of memory references committed
|
||||
system.cpu.commit.loads 402512844 # Number of loads committed
|
||||
system.cpu.commit.membars 51356 # Number of memory barriers committed
|
||||
system.cpu.commit.branches 86248929 # Number of branches committed
|
||||
system.cpu.commit.fp_insts 8452036 # Number of committed floating point instructions.
|
||||
system.cpu.commit.int_insts 1319476388 # Number of committed integer instructions.
|
||||
system.cpu.commit.function_calls 1206914 # Number of function calls committed.
|
||||
system.cpu.commit.bw_lim_events 70040991 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
||||
system.cpu.rob.rob_reads 2302721032 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 3245242057 # The number of ROB writes
|
||||
system.cpu.timesIdled 11126 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 345847 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.committedInsts 1401188958 # Number of Instructions Simulated
|
||||
system.cpu.committedOps 1405604152 # Number of Ops (including micro ops) Simulated
|
||||
system.cpu.committedInsts_total 1401188958 # Number of Instructions Simulated
|
||||
system.cpu.cpi 0.554607 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 0.554607 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 1.803080 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 1.803080 # IPC: Total IPC of All Threads
|
||||
system.cpu.int_regfile_reads 1980619731 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 1276281052 # number of integer regfile writes
|
||||
system.cpu.fp_regfile_reads 16978878 # number of floating regfile reads
|
||||
system.cpu.fp_regfile_writes 10499994 # number of floating regfile writes
|
||||
system.cpu.misc_regfile_reads 593300909 # number of misc regfile reads
|
||||
system.cpu.misc_regfile_writes 2190883 # number of misc regfile writes
|
||||
system.cpu.icache.replacements 200 # number of replacements
|
||||
system.cpu.icache.tagsinuse 1048.828471 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 162821549 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 1351 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 120519.281273 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 1048.828471 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.512123 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.512123 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 162821549 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 162821549 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 162821549 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 162821549 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 162821549 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 162821549 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 1976 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 1976 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 1976 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 1976 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 1976 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 1976 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 67232500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 67232500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 67232500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 67232500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 67232500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 67232500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 162823525 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 162823525 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 162823525 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 162823525 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 162823525 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 162823525 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000012 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.000012 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000012 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.000012 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000012 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000012 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34024.544534 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 34024.544534 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 34024.544534 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 34024.544534 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 34024.544534 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 34024.544534 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 624 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::total 624 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::cpu.inst 624 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::total 624 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::cpu.inst 624 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::total 624 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1352 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 1352 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 1352 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 1352 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 1352 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 1352 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 47023000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 47023000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 47023000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 47023000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 47023000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 47023000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000008 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000008 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000008 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000008 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000008 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000008 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34780.325444 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 34780.325444 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34780.325444 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 34780.325444 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34780.325444 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 34780.325444 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 458031 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 4095.115790 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 365778673 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 462127 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 791.511150 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 131565000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 4095.115790 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.999784 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.999784 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 200803152 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 200803152 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 164974202 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 164974202 # number of WriteReq hits
|
||||
system.cpu.dcache.SwapReq_hits::cpu.data 1319 # number of SwapReq hits
|
||||
system.cpu.dcache.SwapReq_hits::total 1319 # number of SwapReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 365777354 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 365777354 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 365777354 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 365777354 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 803342 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 803342 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 1872614 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 1872614 # number of WriteReq misses
|
||||
system.cpu.dcache.SwapReq_misses::cpu.data 7 # number of SwapReq misses
|
||||
system.cpu.dcache.SwapReq_misses::total 7 # number of SwapReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 2675956 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 2675956 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 2675956 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 2675956 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 11885207000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 11885207000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 29671016952 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 29671016952 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.SwapReq_miss_latency::cpu.data 267000 # number of SwapReq miss cycles
|
||||
system.cpu.dcache.SwapReq_miss_latency::total 267000 # number of SwapReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 41556223952 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 41556223952 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 41556223952 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 41556223952 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 201606494 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 201606494 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 166846816 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 166846816 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.SwapReq_accesses::cpu.data 1326 # number of SwapReq accesses(hits+misses)
|
||||
system.cpu.dcache.SwapReq_accesses::total 1326 # number of SwapReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 368453310 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 368453310 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 368453310 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 368453310 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003985 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.003985 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.011224 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.011224 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.005279 # miss rate for SwapReq accesses
|
||||
system.cpu.dcache.SwapReq_miss_rate::total 0.005279 # miss rate for SwapReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.007263 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.007263 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.007263 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.007263 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14794.703875 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 14794.703875 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 15844.705290 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 15844.705290 # average WriteReq miss latency
|
||||
system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 38142.857143 # average SwapReq miss latency
|
||||
system.cpu.dcache.SwapReq_avg_miss_latency::total 38142.857143 # average SwapReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 15529.487014 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 15529.487014 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 15529.487014 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 15529.487014 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 15500 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 7 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 2214.285714 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 413195 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 413195 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 603294 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 603294 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1610542 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 1610542 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 2213836 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 2213836 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 2213836 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 2213836 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 200048 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 200048 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 262072 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 262072 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.SwapReq_mshr_misses::cpu.data 7 # number of SwapReq MSHR misses
|
||||
system.cpu.dcache.SwapReq_mshr_misses::total 7 # number of SwapReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 462120 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 462120 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 462120 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 462120 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1554226000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 1554226000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3602715222 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3602715222 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 246000 # number of SwapReq MSHR miss cycles
|
||||
system.cpu.dcache.SwapReq_mshr_miss_latency::total 246000 # number of SwapReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5156941222 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 5156941222 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5156941222 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 5156941222 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000992 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000992 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001571 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.001571 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.005279 # mshr miss rate for SwapReq accesses
|
||||
system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.005279 # mshr miss rate for SwapReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001254 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.001254 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001254 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.001254 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7769.265376 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 7769.265376 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 13747.043644 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 13747.043644 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 35142.857143 # average SwapReq mshr miss latency
|
||||
system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 35142.857143 # average SwapReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11159.311915 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 11159.311915 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11159.311915 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 11159.311915 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 75325 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 17833.274372 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 440162 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 90846 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 4.845145 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::writebacks 15764.439855 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 99.157433 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 1969.677084 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.481093 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.003026 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.060110 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.544228 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 23 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 167881 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 167904 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 413195 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 413195 # number of Writeback hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 202021 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 202021 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 23 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 369902 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 369925 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 23 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 369902 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 369925 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 1329 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.data 32167 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 33496 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 60058 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 60058 # number of ReadExReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 1329 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 92225 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 93554 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 1329 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 92225 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 93554 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 45502500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1094618000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 1140120500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2066673500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 2066673500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 45502500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 3161291500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 3206794000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 45502500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 3161291500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 3206794000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 1352 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 200048 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 201400 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 413195 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 413195 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 262079 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 262079 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 1352 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 462127 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 463479 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 1352 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 462127 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 463479 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.982988 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.160796 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.166316 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.229160 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.229160 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.982988 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.199566 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.201852 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.982988 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.199566 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.201852 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34238.148984 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34029.222495 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 34037.511942 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34411.294082 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34411.294082 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34238.148984 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34278.031987 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 34277.465421 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34238.148984 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34278.031987 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 34277.465421 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks::writebacks 59190 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 59190 # number of writebacks
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1329 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 32167 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::total 33496 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 60058 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 60058 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 1329 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 92225 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 93554 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 1329 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 92225 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 93554 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 41203500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 997353500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1038557000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1880936000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1880936000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 41203500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 2878289500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 2919493000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 41203500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2878289500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 2919493000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.982988 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.160796 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.166316 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.229160 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.229160 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.982988 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.199566 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.201852 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.982988 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.199566 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.201852 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31003.386005 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31005.486990 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31005.403630 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31318.658630 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31318.658630 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31003.386005 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31209.428029 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31206.501058 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31003.386005 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31209.428029 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31206.501058 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
@ -0,0 +1,117 @@
|
||||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
full_system=false
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
||||
[system]
|
||||
type=System
|
||||
children=cpu membus physmem
|
||||
boot_osflags=a
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
mem_mode=atomic
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
readfile=
|
||||
symbolfile=
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.membus.slave[0]
|
||||
|
||||
[system.cpu]
|
||||
type=AtomicSimpleCPU
|
||||
children=dtb interrupts itb tracer workload
|
||||
checker=Null
|
||||
clock=500
|
||||
cpu_id=0
|
||||
defer_registration=false
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
fastmem=false
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
interrupts=system.cpu.interrupts
|
||||
itb=system.cpu.itb
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
phase=0
|
||||
profile=0
|
||||
progress_interval=0
|
||||
simulate_data_stalls=false
|
||||
simulate_inst_stalls=false
|
||||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
width=1
|
||||
workload=system.cpu.workload
|
||||
dcache_port=system.membus.slave[2]
|
||||
icache_port=system.membus.slave[1]
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=SparcTLB
|
||||
size=64
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=SparcInterrupts
|
||||
|
||||
[system.cpu.itb]
|
||||
type=SparcTLB
|
||||
size=64
|
||||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
|
||||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=gzip input.log 1
|
||||
cwd=build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/simple-atomic
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/cpu2000/binaries/sparc/linux/gzip
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
ppid=99
|
||||
simpoint=0
|
||||
system=system
|
||||
uid=100
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
master=system.physmem.port[0]
|
||||
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.membus.master[0]
|
||||
|
||||
@ -0,0 +1,3 @@
|
||||
warn: CoherentBus system.membus has no snooping ports attached!
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
hack: be nice to actually delete the event here
|
||||
41
simulators/gem5/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/simout
Executable file
41
simulators/gem5/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/simout
Executable file
@ -0,0 +1,41 @@
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jun 4 2012 12:01:47
|
||||
gem5 started Jun 4 2012 14:45:41
|
||||
gem5 executing on zizzer
|
||||
command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/simple-atomic
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
spec_init
|
||||
Loading Input Data
|
||||
Duplicating 262144 bytes
|
||||
Duplicating 524288 bytes
|
||||
Input data 1048576 bytes in length
|
||||
Compressing Input Data, level 1
|
||||
Compressed data 108074 bytes in length
|
||||
Uncompressing Data
|
||||
Uncompressed data 1048576 bytes in length
|
||||
Uncompressed data compared correctly
|
||||
Compressing Input Data, level 3
|
||||
Compressed data 97831 bytes in length
|
||||
Uncompressing Data
|
||||
Uncompressed data 1048576 bytes in length
|
||||
Uncompressed data compared correctly
|
||||
Compressing Input Data, level 5
|
||||
Compressed data 83382 bytes in length
|
||||
Uncompressing Data
|
||||
Uncompressed data 1048576 bytes in length
|
||||
Uncompressed data compared correctly
|
||||
Compressing Input Data, level 7
|
||||
Compressed data 76606 bytes in length
|
||||
Uncompressing Data
|
||||
Uncompressed data 1048576 bytes in length
|
||||
Uncompressed data compared correctly
|
||||
Compressing Input Data, level 9
|
||||
Compressed data 73189 bytes in length
|
||||
Uncompressing Data
|
||||
Uncompressed data 1048576 bytes in length
|
||||
Uncompressed data compared correctly
|
||||
Tested 1MB buffer: OK!
|
||||
Exiting @ tick 744764119000 because target called exit()
|
||||
@ -0,0 +1,62 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.744764 # Number of seconds simulated
|
||||
sim_ticks 744764119000 # Number of ticks simulated
|
||||
final_tick 744764119000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 3186892 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 3196366 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1598188492 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 214172 # Number of bytes of host memory used
|
||||
host_seconds 466.01 # Real time elapsed on the host
|
||||
sim_insts 1485108101 # Number of instructions simulated
|
||||
sim_ops 1489523295 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 5940452044 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 1385817593 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 7326269637 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 5940452044 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 5940452044 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::cpu.data 614672063 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 614672063 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 1485113011 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 402512844 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 1887625855 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::cpu.data 166846816 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 166846816 # Number of write requests responded to by this memory
|
||||
system.physmem.num_other::cpu.data 1326 # Number of other requests responded to by this memory
|
||||
system.physmem.num_other::total 1326 # Number of other requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 7976286575 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 1860746990 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 9837033566 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 7976286575 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 7976286575 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::cpu.data 825324485 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 825324485 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 7976286575 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 2686071475 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 10662358051 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu.workload.num_syscalls 49 # Number of system calls
|
||||
system.cpu.numCycles 1489528239 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 1485108101 # Number of instructions committed
|
||||
system.cpu.committedOps 1489523295 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 1319481298 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 8454127 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 1207835 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 78161763 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 1319481298 # number of integer instructions
|
||||
system.cpu.num_fp_insts 8454127 # number of float instructions
|
||||
system.cpu.num_int_register_reads 2499743582 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 1234343158 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 16769332 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 10359244 # number of times the floating registers were written
|
||||
system.cpu.num_mem_refs 569365767 # number of memory refs
|
||||
system.cpu.num_load_insts 402515346 # Number of load instructions
|
||||
system.cpu.num_store_insts 166850421 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 1489528239 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
@ -0,0 +1,198 @@
|
||||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
full_system=false
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
||||
[system]
|
||||
type=System
|
||||
children=cpu membus physmem
|
||||
boot_osflags=a
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
mem_mode=atomic
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
readfile=
|
||||
symbolfile=
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.membus.slave[0]
|
||||
|
||||
[system.cpu]
|
||||
type=TimingSimpleCPU
|
||||
children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
|
||||
checker=Null
|
||||
clock=500
|
||||
cpu_id=0
|
||||
defer_registration=false
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
interrupts=system.cpu.interrupts
|
||||
itb=system.cpu.itb
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
phase=0
|
||||
profile=0
|
||||
progress_interval=0
|
||||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
workload=system.cpu.workload
|
||||
dcache_port=system.cpu.dcache.cpu_side
|
||||
icache_port=system.cpu.icache.cpu_side
|
||||
|
||||
[system.cpu.dcache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=262144
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.dcache_port
|
||||
mem_side=system.cpu.toL2Bus.slave[1]
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=SparcTLB
|
||||
size=64
|
||||
|
||||
[system.cpu.icache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=131072
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.icache_port
|
||||
mem_side=system.cpu.toL2Bus.slave[0]
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=SparcInterrupts
|
||||
|
||||
[system.cpu.itb]
|
||||
type=SparcTLB
|
||||
size=64
|
||||
|
||||
[system.cpu.l2cache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=false
|
||||
latency=10000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=2097152
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.toL2Bus.master[0]
|
||||
mem_side=system.membus.slave[1]
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
master=system.cpu.l2cache.cpu_side
|
||||
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
|
||||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
|
||||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=gzip input.log 1
|
||||
cwd=build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/simple-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/cpu2000/binaries/sparc/linux/gzip
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
ppid=99
|
||||
simpoint=0
|
||||
system=system
|
||||
uid=100
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
master=system.physmem.port[0]
|
||||
slave=system.system_port system.cpu.l2cache.mem_side
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.membus.master[0]
|
||||
|
||||
@ -0,0 +1,2 @@
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
hack: be nice to actually delete the event here
|
||||
41
simulators/gem5/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/simout
Executable file
41
simulators/gem5/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/simout
Executable file
@ -0,0 +1,41 @@
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jun 4 2012 12:01:47
|
||||
gem5 started Jun 4 2012 14:45:45
|
||||
gem5 executing on zizzer
|
||||
command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/simple-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
spec_init
|
||||
Loading Input Data
|
||||
Duplicating 262144 bytes
|
||||
Duplicating 524288 bytes
|
||||
Input data 1048576 bytes in length
|
||||
Compressing Input Data, level 1
|
||||
Compressed data 108074 bytes in length
|
||||
Uncompressing Data
|
||||
Uncompressed data 1048576 bytes in length
|
||||
Uncompressed data compared correctly
|
||||
Compressing Input Data, level 3
|
||||
Compressed data 97831 bytes in length
|
||||
Uncompressing Data
|
||||
Uncompressed data 1048576 bytes in length
|
||||
Uncompressed data compared correctly
|
||||
Compressing Input Data, level 5
|
||||
Compressed data 83382 bytes in length
|
||||
Uncompressing Data
|
||||
Uncompressed data 1048576 bytes in length
|
||||
Uncompressed data compared correctly
|
||||
Compressing Input Data, level 7
|
||||
Compressed data 76606 bytes in length
|
||||
Uncompressing Data
|
||||
Uncompressed data 1048576 bytes in length
|
||||
Uncompressed data compared correctly
|
||||
Compressing Input Data, level 9
|
||||
Compressed data 73189 bytes in length
|
||||
Uncompressing Data
|
||||
Uncompressed data 1048576 bytes in length
|
||||
Uncompressed data compared correctly
|
||||
Tested 1MB buffer: OK!
|
||||
Exiting @ tick 2064258667000 because target called exit()
|
||||
@ -0,0 +1,397 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 2.064259 # Number of seconds simulated
|
||||
sim_ticks 2064258667000 # Number of ticks simulated
|
||||
final_tick 2064258667000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1371910 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1375988 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1906915769 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 223048 # Number of bytes of host memory used
|
||||
host_seconds 1082.51 # Real time elapsed on the host
|
||||
sim_insts 1485108101 # Number of instructions simulated
|
||||
sim_ops 1489523295 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 70592 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 5839360 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 5909952 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 70592 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 70592 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 3778240 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 3778240 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 1103 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 91240 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 92343 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 59035 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 59035 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 34197 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 2828793 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 2862990 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 34197 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 34197 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 1830313 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 1830313 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 1830313 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 34197 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 2828793 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 4693303 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu.workload.num_syscalls 49 # Number of system calls
|
||||
system.cpu.numCycles 4128517334 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 1485108101 # Number of instructions committed
|
||||
system.cpu.committedOps 1489523295 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 1319481298 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 8454127 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 1207835 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 78161763 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 1319481298 # number of integer instructions
|
||||
system.cpu.num_fp_insts 8454127 # number of float instructions
|
||||
system.cpu.num_int_register_reads 2499743582 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 1234343157 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 16769332 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 10359244 # number of times the floating registers were written
|
||||
system.cpu.num_mem_refs 569365767 # number of memory refs
|
||||
system.cpu.num_load_insts 402515346 # Number of load instructions
|
||||
system.cpu.num_store_insts 166850421 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 4128517334 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.icache.replacements 118 # number of replacements
|
||||
system.cpu.icache.tagsinuse 906.450625 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 1485111905 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 1107 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 1341564.503162 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 906.450625 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.442603 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.442603 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 1485111905 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 1485111905 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 1485111905 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 1485111905 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 1485111905 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 1485111905 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 1107 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 1107 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 1107 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 1107 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 1107 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 1107 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 61824000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 61824000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 61824000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 61824000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 61824000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 61824000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 1485113012 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 1485113012 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 1485113012 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 1485113012 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 1485113012 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 1485113012 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000001 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.000001 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000001 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.000001 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000001 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000001 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55848.238482 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 55848.238482 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 55848.238482 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 55848.238482 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 55848.238482 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 55848.238482 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1107 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 1107 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 1107 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 1107 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 1107 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 1107 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 58503000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 58503000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 58503000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 58503000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 58503000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 58503000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000001 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000001 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000001 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52848.238482 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52848.238482 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52848.238482 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 52848.238482 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52848.238482 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 52848.238482 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 449125 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 4095.226955 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 568907765 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 453221 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 1255.254644 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 566994000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 4095.226955 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.999811 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.999811 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 402319358 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 402319358 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 166587088 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 166587088 # number of WriteReq hits
|
||||
system.cpu.dcache.SwapReq_hits::cpu.data 1319 # number of SwapReq hits
|
||||
system.cpu.dcache.SwapReq_hits::total 1319 # number of SwapReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 568906446 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 568906446 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 568906446 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 568906446 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 193486 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 193486 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 259728 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 259728 # number of WriteReq misses
|
||||
system.cpu.dcache.SwapReq_misses::cpu.data 7 # number of SwapReq misses
|
||||
system.cpu.dcache.SwapReq_misses::total 7 # number of SwapReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 453214 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 453214 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 453214 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 453214 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 4019834000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 4019834000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 6156948000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 6156948000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.SwapReq_miss_latency::cpu.data 392000 # number of SwapReq miss cycles
|
||||
system.cpu.dcache.SwapReq_miss_latency::total 392000 # number of SwapReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 10176782000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 10176782000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 10176782000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 10176782000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 402512844 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 402512844 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 166846816 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 166846816 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.SwapReq_accesses::cpu.data 1326 # number of SwapReq accesses(hits+misses)
|
||||
system.cpu.dcache.SwapReq_accesses::total 1326 # number of SwapReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 569359660 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 569359660 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 569359660 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 569359660 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000481 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.000481 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001557 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.001557 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.005279 # miss rate for SwapReq accesses
|
||||
system.cpu.dcache.SwapReq_miss_rate::total 0.005279 # miss rate for SwapReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.000796 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.000796 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.000796 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.000796 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20775.839079 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 20775.839079 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 23705.368693 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 23705.368693 # average WriteReq miss latency
|
||||
system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 56000 # average SwapReq miss latency
|
||||
system.cpu.dcache.SwapReq_avg_miss_latency::total 56000 # average SwapReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 22454.694692 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 22454.694692 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 22454.694692 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 22454.694692 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 407009 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 407009 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 193486 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 193486 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 259728 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 259728 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.SwapReq_mshr_misses::cpu.data 7 # number of SwapReq MSHR misses
|
||||
system.cpu.dcache.SwapReq_mshr_misses::total 7 # number of SwapReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 453214 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 453214 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 453214 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 453214 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3439376000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 3439376000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5377764000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 5377764000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 371000 # number of SwapReq MSHR miss cycles
|
||||
system.cpu.dcache.SwapReq_mshr_miss_latency::total 371000 # number of SwapReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8817140000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 8817140000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8817140000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 8817140000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000481 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000481 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001557 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.001557 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.005279 # mshr miss rate for SwapReq accesses
|
||||
system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.005279 # mshr miss rate for SwapReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000796 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.000796 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000796 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.000796 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17775.839079 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17775.839079 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 20705.368693 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 20705.368693 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 53000 # average SwapReq mshr miss latency
|
||||
system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 53000 # average SwapReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19454.694692 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 19454.694692 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19454.694692 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 19454.694692 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 74112 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 17723.305524 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 427085 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 89611 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 4.765989 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::writebacks 15849.385934 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 72.801131 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 1801.118460 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.483685 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.002222 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.054966 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.540872 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 4 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 162271 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 162275 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 407009 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 407009 # number of Writeback hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 199710 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 199710 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 4 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 361981 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 361985 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 4 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 361981 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 361985 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 1103 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.data 31215 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 32318 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 60025 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 60025 # number of ReadExReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 1103 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 91240 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 92343 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 1103 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 91240 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 92343 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 57356000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1623180000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 1680536000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3121300000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 3121300000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 57356000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 4744480000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 4801836000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 57356000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 4744480000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 4801836000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 1107 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 193486 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 194593 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 407009 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 407009 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 259735 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 259735 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 1107 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 453221 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 454328 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 1107 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 453221 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 454328 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996387 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.161330 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.166080 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.231101 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.231101 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996387 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.201315 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.203252 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996387 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.201315 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.203252 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks::writebacks 59035 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 59035 # number of writebacks
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1103 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 31215 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::total 32318 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 60025 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 60025 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 1103 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 91240 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 92343 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 1103 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 91240 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 92343 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 44120000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1248600000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1292720000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2401000000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2401000000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 44120000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3649600000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 3693720000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 44120000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3649600000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 3693720000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996387 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.161330 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.166080 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.231101 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.231101 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996387 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.201315 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.203252 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996387 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.201315 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.203252 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
@ -0,0 +1,550 @@
|
||||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
full_system=false
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
||||
[system]
|
||||
type=System
|
||||
children=cpu membus physmem
|
||||
boot_osflags=a
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
mem_mode=atomic
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
readfile=
|
||||
symbolfile=
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.membus.slave[0]
|
||||
|
||||
[system.cpu]
|
||||
type=DerivO3CPU
|
||||
children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
|
||||
BTBEntries=4096
|
||||
BTBTagSize=16
|
||||
LFSTSize=1024
|
||||
LQEntries=32
|
||||
LSQCheckLoads=true
|
||||
LSQDepCheckShift=4
|
||||
RASSize=16
|
||||
SQEntries=32
|
||||
SSITSize=1024
|
||||
activity=0
|
||||
backComSize=5
|
||||
cachePorts=200
|
||||
checker=Null
|
||||
choiceCtrBits=2
|
||||
choicePredictorSize=8192
|
||||
clock=500
|
||||
commitToDecodeDelay=1
|
||||
commitToFetchDelay=1
|
||||
commitToIEWDelay=1
|
||||
commitToRenameDelay=1
|
||||
commitWidth=8
|
||||
cpu_id=0
|
||||
decodeToFetchDelay=1
|
||||
decodeToRenameDelay=1
|
||||
decodeWidth=8
|
||||
defer_registration=false
|
||||
dispatchWidth=8
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
fetchToDecodeDelay=1
|
||||
fetchTrapLatency=1
|
||||
fetchWidth=8
|
||||
forwardComSize=5
|
||||
fuPool=system.cpu.fuPool
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
globalCtrBits=2
|
||||
globalHistoryBits=13
|
||||
globalPredictorSize=8192
|
||||
iewToCommitDelay=1
|
||||
iewToDecodeDelay=1
|
||||
iewToFetchDelay=1
|
||||
iewToRenameDelay=1
|
||||
instShiftAmt=2
|
||||
interrupts=system.cpu.interrupts
|
||||
issueToExecuteDelay=1
|
||||
issueWidth=8
|
||||
itb=system.cpu.itb
|
||||
localCtrBits=2
|
||||
localHistoryBits=11
|
||||
localHistoryTableSize=2048
|
||||
localPredictorSize=2048
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
needsTSO=true
|
||||
numIQEntries=64
|
||||
numPhysFloatRegs=256
|
||||
numPhysIntRegs=256
|
||||
numROBEntries=192
|
||||
numRobs=1
|
||||
numThreads=1
|
||||
phase=0
|
||||
predType=tournament
|
||||
profile=0
|
||||
progress_interval=0
|
||||
renameToDecodeDelay=1
|
||||
renameToFetchDelay=1
|
||||
renameToIEWDelay=2
|
||||
renameToROBDelay=1
|
||||
renameWidth=8
|
||||
smtCommitPolicy=RoundRobin
|
||||
smtFetchPolicy=SingleThread
|
||||
smtIQPolicy=Partitioned
|
||||
smtIQThreshold=100
|
||||
smtLSQPolicy=Partitioned
|
||||
smtLSQThreshold=100
|
||||
smtNumFetchingThreads=1
|
||||
smtROBPolicy=Partitioned
|
||||
smtROBThreshold=100
|
||||
squashWidth=8
|
||||
store_set_clear_period=250000
|
||||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
trapLatency=13
|
||||
wbDepth=1
|
||||
wbWidth=8
|
||||
workload=system.cpu.workload
|
||||
dcache_port=system.cpu.dcache.cpu_side
|
||||
icache_port=system.cpu.icache.cpu_side
|
||||
|
||||
[system.cpu.dcache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=262144
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=20
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.dcache_port
|
||||
mem_side=system.cpu.toL2Bus.slave[1]
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=X86TLB
|
||||
children=walker
|
||||
size=64
|
||||
walker=system.cpu.dtb.walker
|
||||
|
||||
[system.cpu.dtb.walker]
|
||||
type=X86PagetableWalker
|
||||
system=system
|
||||
port=system.cpu.toL2Bus.slave[3]
|
||||
|
||||
[system.cpu.fuPool]
|
||||
type=FUPool
|
||||
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
|
||||
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
|
||||
|
||||
[system.cpu.fuPool.FUList0]
|
||||
type=FUDesc
|
||||
children=opList
|
||||
count=6
|
||||
opList=system.cpu.fuPool.FUList0.opList
|
||||
|
||||
[system.cpu.fuPool.FUList0.opList]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=IntAlu
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList1]
|
||||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=2
|
||||
opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=IntMult
|
||||
opLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList1]
|
||||
type=OpDesc
|
||||
issueLat=19
|
||||
opClass=IntDiv
|
||||
opLat=20
|
||||
|
||||
[system.cpu.fuPool.FUList2]
|
||||
type=FUDesc
|
||||
children=opList0 opList1 opList2
|
||||
count=4
|
||||
opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=FloatAdd
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList1]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=FloatCmp
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList2]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=FloatCvt
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList3]
|
||||
type=FUDesc
|
||||
children=opList0 opList1 opList2
|
||||
count=2
|
||||
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=FloatMult
|
||||
opLat=4
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList1]
|
||||
type=OpDesc
|
||||
issueLat=12
|
||||
opClass=FloatDiv
|
||||
opLat=12
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList2]
|
||||
type=OpDesc
|
||||
issueLat=24
|
||||
opClass=FloatSqrt
|
||||
opLat=24
|
||||
|
||||
[system.cpu.fuPool.FUList4]
|
||||
type=FUDesc
|
||||
children=opList
|
||||
count=0
|
||||
opList=system.cpu.fuPool.FUList4.opList
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5]
|
||||
type=FUDesc
|
||||
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
|
||||
count=4
|
||||
opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList00]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdAdd
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList01]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdAddAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList02]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdAlu
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList03]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdCmp
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList04]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdCvt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList05]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdMisc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList06]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdMult
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList07]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdMultAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList08]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdShift
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList09]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdShiftAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList10]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdSqrt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList11]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatAdd
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList12]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatAlu
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList13]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatCmp
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList14]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatCvt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList15]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatDiv
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList16]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatMisc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList17]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatMult
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList18]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatMultAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList19]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatSqrt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList6]
|
||||
type=FUDesc
|
||||
children=opList
|
||||
count=0
|
||||
opList=system.cpu.fuPool.FUList6.opList
|
||||
|
||||
[system.cpu.fuPool.FUList6.opList]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList7]
|
||||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=4
|
||||
opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList1]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList8]
|
||||
type=FUDesc
|
||||
children=opList
|
||||
count=1
|
||||
opList=system.cpu.fuPool.FUList8.opList
|
||||
|
||||
[system.cpu.fuPool.FUList8.opList]
|
||||
type=OpDesc
|
||||
issueLat=3
|
||||
opClass=IprAccess
|
||||
opLat=3
|
||||
|
||||
[system.cpu.icache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=131072
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=20
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.icache_port
|
||||
mem_side=system.cpu.toL2Bus.slave[0]
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=X86LocalApic
|
||||
int_latency=1000
|
||||
pio_addr=2305843009213693952
|
||||
pio_latency=1000
|
||||
system=system
|
||||
int_master=system.membus.slave[2]
|
||||
int_slave=system.membus.master[2]
|
||||
pio=system.membus.master[1]
|
||||
|
||||
[system.cpu.itb]
|
||||
type=X86TLB
|
||||
children=walker
|
||||
size=64
|
||||
walker=system.cpu.itb.walker
|
||||
|
||||
[system.cpu.itb.walker]
|
||||
type=X86PagetableWalker
|
||||
system=system
|
||||
port=system.cpu.toL2Bus.slave[2]
|
||||
|
||||
[system.cpu.l2cache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=false
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=2097152
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.toL2Bus.master[0]
|
||||
mem_side=system.membus.slave[1]
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
master=system.cpu.l2cache.cpu_side
|
||||
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
|
||||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
|
||||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=gzip input.log 1
|
||||
cwd=build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/cpu2000/binaries/x86/linux/gzip
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
ppid=99
|
||||
simpoint=0
|
||||
system=system
|
||||
uid=100
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave
|
||||
slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.membus.master[0]
|
||||
|
||||
4
simulators/gem5/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simerr
Executable file
4
simulators/gem5/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simerr
Executable file
@ -0,0 +1,4 @@
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: instruction 'fnstcw_Mw' unimplemented
|
||||
warn: instruction 'fldcw_Mw' unimplemented
|
||||
hack: be nice to actually delete the event here
|
||||
43
simulators/gem5/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout
Executable file
43
simulators/gem5/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout
Executable file
@ -0,0 +1,43 @@
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jun 4 2012 13:44:28
|
||||
gem5 started Jun 4 2012 15:07:25
|
||||
gem5 executing on zizzer
|
||||
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
spec_init
|
||||
Loading Input Data
|
||||
Duplicating 262144 bytes
|
||||
Duplicating 524288 bytes
|
||||
Input data 1048576 bytes in length
|
||||
Compressing Input Data, level 1
|
||||
Compressed data 108074 bytes in length
|
||||
Uncompressing Data
|
||||
info: Increasing stack size by one page.
|
||||
Uncompressed data 1048576 bytes in length
|
||||
Uncompressed data compared correctly
|
||||
Compressing Input Data, level 3
|
||||
Compressed data 97831 bytes in length
|
||||
Uncompressing Data
|
||||
info: Increasing stack size by one page.
|
||||
Uncompressed data 1048576 bytes in length
|
||||
Uncompressed data compared correctly
|
||||
Compressing Input Data, level 5
|
||||
Compressed data 83382 bytes in length
|
||||
Uncompressing Data
|
||||
Uncompressed data 1048576 bytes in length
|
||||
Uncompressed data compared correctly
|
||||
Compressing Input Data, level 7
|
||||
Compressed data 76606 bytes in length
|
||||
Uncompressing Data
|
||||
Uncompressed data 1048576 bytes in length
|
||||
Uncompressed data compared correctly
|
||||
Compressing Input Data, level 9
|
||||
Compressed data 73189 bytes in length
|
||||
Uncompressing Data
|
||||
Uncompressed data 1048576 bytes in length
|
||||
Uncompressed data compared correctly
|
||||
Tested 1MB buffer: OK!
|
||||
Exiting @ tick 636988382500 because target called exit()
|
||||
@ -0,0 +1,639 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.636988 # Number of seconds simulated
|
||||
sim_ticks 636988382500 # Number of ticks simulated
|
||||
final_tick 636988382500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 63436 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 116883 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 45916521 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 227532 # Number of bytes of host memory used
|
||||
host_seconds 13872.75 # Real time elapsed on the host
|
||||
sim_insts 880025312 # Number of instructions simulated
|
||||
sim_ops 1621493982 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 59200 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 5774848 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 5834048 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 59200 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 59200 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 3731712 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 3731712 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 925 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 90232 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 91157 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 58308 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 58308 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 92937 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 9065861 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 9158798 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 92937 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 92937 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 5858367 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 5858367 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 5858367 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 92937 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 9065861 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 15017166 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu.workload.num_syscalls 48 # Number of system calls
|
||||
system.cpu.numCycles 1273976766 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.BPredUnit.lookups 154678064 # Number of BP lookups
|
||||
system.cpu.BPredUnit.condPredicted 154678064 # Number of conditional branches predicted
|
||||
system.cpu.BPredUnit.condIncorrect 26667110 # Number of conditional branches incorrect
|
||||
system.cpu.BPredUnit.BTBLookups 77406078 # Number of BTB lookups
|
||||
system.cpu.BPredUnit.BTBHits 77035710 # Number of BTB hits
|
||||
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
|
||||
system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
|
||||
system.cpu.fetch.icacheStallCycles 180711057 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.Insts 1490230522 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.Branches 154678064 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.predictedBranches 77035710 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.Cycles 402278451 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.SquashCycles 93695646 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.BlockedCycles 624053491 # Number of cycles fetch has spent blocked
|
||||
system.cpu.fetch.MiscStallCycles 174 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
||||
system.cpu.fetch.PendingTrapStallCycles 1298 # Number of stall cycles due to pending traps
|
||||
system.cpu.fetch.CacheLines 186830267 # Number of cache lines fetched
|
||||
system.cpu.fetch.IcacheSquashes 9529255 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.rateDist::samples 1273914012 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 1.999814 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 3.235188 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 878853214 68.99% 68.99% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 24303546 1.91% 70.90% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 15677834 1.23% 72.13% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 17928928 1.41% 73.53% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 26735770 2.10% 75.63% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 18262172 1.43% 77.07% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 28765750 2.26% 79.32% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 39797773 3.12% 82.45% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 223589025 17.55% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::total 1273914012 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.branchRate 0.121414 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.rate 1.169747 # Number of inst fetches per cycle
|
||||
system.cpu.decode.IdleCycles 300082895 # Number of cycles decode is idle
|
||||
system.cpu.decode.BlockedCycles 537078967 # Number of cycles decode is blocked
|
||||
system.cpu.decode.RunCycles 281798821 # Number of cycles decode is running
|
||||
system.cpu.decode.UnblockCycles 88083788 # Number of cycles decode is unblocking
|
||||
system.cpu.decode.SquashCycles 66869541 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DecodedInsts 2368899404 # Number of instructions handled by decode
|
||||
system.cpu.rename.SquashCycles 66869541 # Number of cycles rename is squashing
|
||||
system.cpu.rename.IdleCycles 352603459 # Number of cycles rename is idle
|
||||
system.cpu.rename.BlockCycles 124071504 # Number of cycles rename is blocking
|
||||
system.cpu.rename.serializeStallCycles 2838 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RunCycles 302490800 # Number of cycles rename is running
|
||||
system.cpu.rename.UnblockCycles 427875870 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RenamedInsts 2273771459 # Number of instructions processed by rename
|
||||
system.cpu.rename.ROBFullEvents 200 # Number of times rename has blocked due to ROB full
|
||||
system.cpu.rename.IQFullEvents 293326885 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.LSQFullEvents 103161675 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.FullRegisterEvents 640 # Number of times there has been no free registers
|
||||
system.cpu.rename.RenamedOperands 3463149697 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RenameLookups 7120628194 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.int_rename_lookups 7120621014 # Number of integer rename lookups
|
||||
system.cpu.rename.fp_rename_lookups 7180 # Number of floating rename lookups
|
||||
system.cpu.rename.CommittedMaps 2493860970 # Number of HB maps that are committed
|
||||
system.cpu.rename.UndoneMaps 969288727 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.serializingInsts 110 # count of serializing insts renamed
|
||||
system.cpu.rename.tempSerializingInsts 110 # count of temporary serializing insts renamed
|
||||
system.cpu.rename.skidInsts 746079760 # count of insts added to the skid buffer
|
||||
system.cpu.memDep0.insertedLoads 546341437 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 222247757 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.conflictingLoads 352469730 # Number of conflicting loads.
|
||||
system.cpu.memDep0.conflictingStores 147023702 # Number of conflicting stores.
|
||||
system.cpu.iq.iqInstsAdded 2027529381 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqNonSpecInstsAdded 546 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqInstsIssued 1785574895 # Number of instructions issued
|
||||
system.cpu.iq.iqSquashedInstsIssued 118982 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedInstsExamined 405869160 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedOperandsExamined 1051620727 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 496 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.issued_per_cycle::samples 1273914012 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::mean 1.401645 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::stdev 1.311838 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::0 347011244 27.24% 27.24% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::1 447440186 35.12% 62.36% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::2 243114046 19.08% 81.45% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::3 151317631 11.88% 93.33% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::4 40944695 3.21% 96.54% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::5 32410749 2.54% 99.08% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::6 9957171 0.78% 99.87% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::7 1368147 0.11% 99.97% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::8 350143 0.03% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::total 1273914012 # Number of insts issued each cycle
|
||||
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntAlu 237387 9.29% 9.29% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntMult 0 0.00% 9.29% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntDiv 0 0.00% 9.29% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.29% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.29% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.29% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatMult 0 0.00% 9.29% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.29% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.29% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.29% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.29% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.29% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.29% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.29% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.29% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdMult 0 0.00% 9.29% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.29% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdShift 0 0.00% 9.29% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.29% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.29% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.29% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.29% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.29% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.29% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.29% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.29% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.29% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.29% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.29% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::MemRead 2138623 83.73% 93.02% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::MemWrite 178205 6.98% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.FU_type_0::No_OpClass 46809715 2.62% 2.62% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntAlu 1066790690 59.74% 62.37% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntMult 0 0.00% 62.37% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.37% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.37% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.37% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.37% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.37% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.37% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.37% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.37% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.37% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.37% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.37% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.37% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.37% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.37% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.37% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.37% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.37% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.37% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.37% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.37% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.37% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.37% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.37% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.37% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.37% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.37% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.37% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::MemRead 479501542 26.85% 89.22% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::MemWrite 192472948 10.78% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::total 1785574895 # Type of FU issued
|
||||
system.cpu.iq.rate 1.401576 # Inst issue rate
|
||||
system.cpu.iq.fu_busy_cnt 2554215 # FU busy when requested
|
||||
system.cpu.iq.fu_busy_rate 0.001430 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.int_inst_queue_reads 4847736227 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_writes 2433580235 # Number of integer instruction queue writes
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 1726806271 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.fp_inst_queue_reads 772 # Number of floating instruction queue reads
|
||||
system.cpu.iq.fp_inst_queue_writes 2168 # Number of floating instruction queue writes
|
||||
system.cpu.iq.fp_inst_queue_wakeup_accesses 84 # Number of floating instruction queue wakeup accesses
|
||||
system.cpu.iq.int_alu_accesses 1741319146 # Number of integer alu accesses
|
||||
system.cpu.iq.fp_alu_accesses 249 # Number of floating point alu accesses
|
||||
system.cpu.iew.lsq.thread0.forwLoads 208956586 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread0.squashedLoads 127299312 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread0.ignoredResponses 36681 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread0.memOrderViolation 190307 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread0.squashedStores 34061700 # Number of stores squashed
|
||||
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
||||
system.cpu.iew.lsq.thread0.rescheduledLoads 1845 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||||
system.cpu.iew.iewSquashCycles 66869541 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewBlockCycles 356934 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewUnblockCycles 88692 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.iewDispatchedInsts 2027529927 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewDispSquashedInsts 63849570 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispLoadInsts 546341437 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispStoreInsts 222247757 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 103 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewIQFullEvents 48888 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.iewLSQFullEvents 421 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.memOrderViolationEvents 190307 # Number of memory order violations
|
||||
system.cpu.iew.predictedTakenIncorrect 2139656 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.iew.predictedNotTakenIncorrect 24653796 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.branchMispredicts 26793452 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewExecutedInsts 1767588629 # Number of executed instructions
|
||||
system.cpu.iew.iewExecLoadInsts 473898164 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 17986266 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
||||
system.cpu.iew.exec_nop 0 # number of nop insts executed
|
||||
system.cpu.iew.exec_refs 665742013 # number of memory reference insts executed
|
||||
system.cpu.iew.exec_branches 109684623 # Number of branches executed
|
||||
system.cpu.iew.exec_stores 191843849 # Number of stores executed
|
||||
system.cpu.iew.exec_rate 1.387458 # Inst execution rate
|
||||
system.cpu.iew.wb_sent 1728148485 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.wb_count 1726806355 # cumulative count of insts written-back
|
||||
system.cpu.iew.wb_producers 1262041827 # num instructions producing a value
|
||||
system.cpu.iew.wb_consumers 2984894243 # num instructions consuming a value
|
||||
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
||||
system.cpu.iew.wb_rate 1.355446 # insts written-back per cycle
|
||||
system.cpu.iew.wb_fanout 0.422810 # average fanout of values written-back
|
||||
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||
system.cpu.commit.commitCommittedInsts 880025312 # The number of committed instructions
|
||||
system.cpu.commit.commitCommittedOps 1621493982 # The number of committed instructions
|
||||
system.cpu.commit.commitSquashedInsts 406040141 # The number of squashed insts skipped by commit
|
||||
system.cpu.commit.commitNonSpecStalls 50 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu.commit.branchMispredicts 26667277 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.committed_per_cycle::samples 1207044471 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::mean 1.343359 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::stdev 1.660546 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::0 437250010 36.22% 36.22% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::1 432641487 35.84% 72.07% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::2 93464877 7.74% 79.81% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::3 134893392 11.18% 90.99% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::4 35716518 2.96% 93.95% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::5 23306370 1.93% 95.88% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::6 25727632 2.13% 98.01% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::7 8874629 0.74% 98.74% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::8 15169556 1.26% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::total 1207044471 # Number of insts commited each cycle
|
||||
system.cpu.commit.committedInsts 880025312 # Number of instructions committed
|
||||
system.cpu.commit.committedOps 1621493982 # Number of ops (including micro ops) committed
|
||||
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
||||
system.cpu.commit.refs 607228182 # Number of memory references committed
|
||||
system.cpu.commit.loads 419042125 # Number of loads committed
|
||||
system.cpu.commit.membars 0 # Number of memory barriers committed
|
||||
system.cpu.commit.branches 107161579 # Number of branches committed
|
||||
system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
|
||||
system.cpu.commit.int_insts 1621354492 # Number of committed integer instructions.
|
||||
system.cpu.commit.function_calls 0 # Number of function calls committed.
|
||||
system.cpu.commit.bw_lim_events 15169556 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
||||
system.cpu.rob.rob_reads 3219409038 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 4121954747 # The number of ROB writes
|
||||
system.cpu.timesIdled 1354 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 62754 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.committedInsts 880025312 # Number of Instructions Simulated
|
||||
system.cpu.committedOps 1621493982 # Number of Ops (including micro ops) Simulated
|
||||
system.cpu.committedInsts_total 880025312 # Number of Instructions Simulated
|
||||
system.cpu.cpi 1.447659 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 1.447659 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 0.690770 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.690770 # IPC: Total IPC of All Threads
|
||||
system.cpu.int_regfile_reads 4473469252 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 2589680881 # number of integer regfile writes
|
||||
system.cpu.fp_regfile_reads 84 # number of floating regfile reads
|
||||
system.cpu.misc_regfile_reads 911429698 # number of misc regfile reads
|
||||
system.cpu.icache.replacements 22 # number of replacements
|
||||
system.cpu.icache.tagsinuse 827.099302 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 186828876 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 928 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 201324.219828 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 827.099302 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.403857 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.403857 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 186828882 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 186828882 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 186828882 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 186828882 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 186828882 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 186828882 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 1385 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 1385 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 1385 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 1385 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 1385 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 1385 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 46636000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 46636000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 46636000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 46636000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 46636000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 46636000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 186830267 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 186830267 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 186830267 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 186830267 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 186830267 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 186830267 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000007 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.000007 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000007 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.000007 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000007 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000007 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 33672.202166 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 33672.202166 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 33672.202166 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 33672.202166 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 33672.202166 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 33672.202166 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 450 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::total 450 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::cpu.inst 450 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::total 450 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::cpu.inst 450 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::total 450 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 935 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 935 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 935 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 935 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 935 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 935 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 32805000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 32805000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 32805000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 32805000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 32805000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 32805000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000005 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000005 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000005 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35085.561497 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35085.561497 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35085.561497 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 35085.561497 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35085.561497 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 35085.561497 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 445407 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 4093.514636 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 452671406 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 449503 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 1007.048687 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 723816000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 4093.514636 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.999393 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.999393 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 264731564 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 264731564 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 187939830 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 187939830 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 452671394 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 452671394 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 452671394 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 452671394 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 206744 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 206744 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 246227 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 246227 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 452971 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 452971 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 452971 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 452971 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 2148724000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 2148724000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 3224322500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 3224322500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 5373046500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 5373046500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 5373046500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 5373046500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 264938308 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 264938308 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 188186057 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 188186057 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 453124365 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 453124365 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 453124365 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 453124365 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000780 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.000780 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001308 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.001308 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.001000 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.001000 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.001000 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.001000 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 10393.162559 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 10393.162559 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 13094.918510 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 13094.918510 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 11861.789165 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 11861.789165 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 11861.789165 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 11861.789165 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 400713 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 400713 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3434 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 3434 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 25 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 25 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 3459 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 3459 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 3459 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 3459 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 203310 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 203310 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 246202 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 246202 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 449512 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 449512 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 449512 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 449512 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1511006000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 1511006000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2485166000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 2485166000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 3996172000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 3996172000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 3996172000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 3996172000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000767 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000767 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001308 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.001308 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000992 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.000992 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000992 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.000992 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7432.029905 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 7432.029905 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10094.012234 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10094.012234 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8890.022958 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 8890.022958 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8890.022958 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 8890.022958 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 72883 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 17779.692577 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 433456 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 88505 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 4.897531 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::writebacks 15879.164577 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 61.338092 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 1839.189909 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.484594 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.001872 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.056128 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.542593 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 3 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 171391 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 171394 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 400713 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 400713 # number of Writeback hits
|
||||
system.cpu.l2cache.UpgradeReq_hits::cpu.data 7 # number of UpgradeReq hits
|
||||
system.cpu.l2cache.UpgradeReq_hits::total 7 # number of UpgradeReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 187882 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 187882 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 359273 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 359276 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 3 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 359273 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 359276 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 925 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.data 31911 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 32836 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 58321 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 58321 # number of ReadExReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 925 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 90232 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 91157 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 925 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 90232 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 91157 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 31707500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1094294500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 1126002000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1998540500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 1998540500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 31707500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 3092835000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 3124542500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 31707500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 3092835000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 3124542500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 928 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 203302 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 204230 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 400713 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 400713 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 7 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_accesses::total 7 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 246203 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 246203 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 928 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 449505 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 450433 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 928 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 449505 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 450433 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996767 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.156964 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.160780 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.236882 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.236882 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996767 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.200736 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.202376 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996767 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.200736 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.202376 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34278.378378 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34292.077967 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 34291.692045 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34267.939507 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34267.939507 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34278.378378 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34276.476195 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 34276.495497 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34278.378378 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34276.476195 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 34276.495497 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks::writebacks 58308 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 58308 # number of writebacks
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 925 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 31911 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::total 32836 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 58321 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 58321 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 925 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 90232 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 91157 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 925 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 90232 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 91157 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 28735500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 989353500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1018089000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1807989500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1807989500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 28735500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 2797343000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 2826078500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 28735500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2797343000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 2826078500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996767 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.156964 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.160780 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.236882 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.236882 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996767 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.200736 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.202376 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996767 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.200736 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.202376 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31065.405405 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31003.525430 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31005.268608 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31000.660140 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31000.660140 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31065.405405 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31001.673464 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31002.320173 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31065.405405 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31001.673464 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31002.320173 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
@ -0,0 +1,138 @@
|
||||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
full_system=false
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
||||
[system]
|
||||
type=System
|
||||
children=cpu membus physmem
|
||||
boot_osflags=a
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
mem_mode=atomic
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
readfile=
|
||||
symbolfile=
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.membus.slave[0]
|
||||
|
||||
[system.cpu]
|
||||
type=AtomicSimpleCPU
|
||||
children=dtb interrupts itb tracer workload
|
||||
checker=Null
|
||||
clock=500
|
||||
cpu_id=0
|
||||
defer_registration=false
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
fastmem=false
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
interrupts=system.cpu.interrupts
|
||||
itb=system.cpu.itb
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
phase=0
|
||||
profile=0
|
||||
progress_interval=0
|
||||
simulate_data_stalls=false
|
||||
simulate_inst_stalls=false
|
||||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
width=1
|
||||
workload=system.cpu.workload
|
||||
dcache_port=system.membus.slave[2]
|
||||
icache_port=system.membus.slave[1]
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=X86TLB
|
||||
children=walker
|
||||
size=64
|
||||
walker=system.cpu.dtb.walker
|
||||
|
||||
[system.cpu.dtb.walker]
|
||||
type=X86PagetableWalker
|
||||
system=system
|
||||
port=system.membus.slave[4]
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=X86LocalApic
|
||||
int_latency=1000
|
||||
pio_addr=2305843009213693952
|
||||
pio_latency=1000
|
||||
system=system
|
||||
int_master=system.membus.slave[5]
|
||||
int_slave=system.membus.master[2]
|
||||
pio=system.membus.master[1]
|
||||
|
||||
[system.cpu.itb]
|
||||
type=X86TLB
|
||||
children=walker
|
||||
size=64
|
||||
walker=system.cpu.itb.walker
|
||||
|
||||
[system.cpu.itb.walker]
|
||||
type=X86PagetableWalker
|
||||
system=system
|
||||
port=system.membus.slave[3]
|
||||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
|
||||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=gzip input.log 1
|
||||
cwd=build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-atomic
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/cpu2000/binaries/x86/linux/gzip
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
ppid=99
|
||||
simpoint=0
|
||||
system=system
|
||||
uid=100
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave
|
||||
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.interrupts.int_master
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.membus.master[0]
|
||||
|
||||
4
simulators/gem5/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simerr
Executable file
4
simulators/gem5/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simerr
Executable file
@ -0,0 +1,4 @@
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: instruction 'fnstcw_Mw' unimplemented
|
||||
warn: instruction 'fldcw_Mw' unimplemented
|
||||
hack: be nice to actually delete the event here
|
||||
42
simulators/gem5/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simout
Executable file
42
simulators/gem5/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simout
Executable file
@ -0,0 +1,42 @@
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jun 4 2012 13:44:28
|
||||
gem5 started Jun 4 2012 15:08:17
|
||||
gem5 executing on zizzer
|
||||
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-atomic
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
spec_init
|
||||
Loading Input Data
|
||||
Duplicating 262144 bytes
|
||||
Duplicating 524288 bytes
|
||||
Input data 1048576 bytes in length
|
||||
Compressing Input Data, level 1
|
||||
Compressed data 108074 bytes in length
|
||||
Uncompressing Data
|
||||
info: Increasing stack size by one page.
|
||||
Uncompressed data 1048576 bytes in length
|
||||
Uncompressed data compared correctly
|
||||
Compressing Input Data, level 3
|
||||
Compressed data 97831 bytes in length
|
||||
Uncompressing Data
|
||||
Uncompressed data 1048576 bytes in length
|
||||
Uncompressed data compared correctly
|
||||
Compressing Input Data, level 5
|
||||
Compressed data 83382 bytes in length
|
||||
Uncompressing Data
|
||||
Uncompressed data 1048576 bytes in length
|
||||
Uncompressed data compared correctly
|
||||
Compressing Input Data, level 7
|
||||
Compressed data 76606 bytes in length
|
||||
Uncompressing Data
|
||||
Uncompressed data 1048576 bytes in length
|
||||
Uncompressed data compared correctly
|
||||
Compressing Input Data, level 9
|
||||
Compressed data 73189 bytes in length
|
||||
Uncompressing Data
|
||||
Uncompressed data 1048576 bytes in length
|
||||
Uncompressed data compared correctly
|
||||
Tested 1MB buffer: OK!
|
||||
Exiting @ tick 963992704000 because target called exit()
|
||||
@ -0,0 +1,60 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.963993 # Number of seconds simulated
|
||||
sim_ticks 963992704000 # Number of ticks simulated
|
||||
final_tick 963992704000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1254577 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2311626 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1374282564 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 216676 # Number of bytes of host memory used
|
||||
host_seconds 701.45 # Real time elapsed on the host
|
||||
sim_insts 880025313 # Number of instructions simulated
|
||||
sim_ops 1621493983 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 9492133912 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 1842452913 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 11334586825 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 9492133912 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 9492133912 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::cpu.data 864451000 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 864451000 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 1186516739 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 419042125 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 1605558864 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::cpu.data 188186057 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 188186057 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 9846686466 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 1911272674 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 11757959140 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 9846686466 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 9846686466 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::cpu.data 896740189 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 896740189 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 9846686466 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 2808012863 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 12654699330 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu.workload.num_syscalls 48 # Number of system calls
|
||||
system.cpu.numCycles 1927985409 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 880025313 # Number of instructions committed
|
||||
system.cpu.committedOps 1621493983 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 1621354493 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 0 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 99478861 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 1621354493 # number of integer instructions
|
||||
system.cpu.num_fp_insts 0 # number of float instructions
|
||||
system.cpu.num_int_register_reads 5129484088 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 2493860970 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
|
||||
system.cpu.num_mem_refs 607228182 # number of memory refs
|
||||
system.cpu.num_load_insts 419042125 # Number of load instructions
|
||||
system.cpu.num_store_insts 188186057 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 1927985409 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
@ -0,0 +1,219 @@
|
||||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
full_system=false
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
||||
[system]
|
||||
type=System
|
||||
children=cpu membus physmem
|
||||
boot_osflags=a
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
mem_mode=atomic
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
readfile=
|
||||
symbolfile=
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.membus.slave[0]
|
||||
|
||||
[system.cpu]
|
||||
type=TimingSimpleCPU
|
||||
children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
|
||||
checker=Null
|
||||
clock=500
|
||||
cpu_id=0
|
||||
defer_registration=false
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
interrupts=system.cpu.interrupts
|
||||
itb=system.cpu.itb
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
phase=0
|
||||
profile=0
|
||||
progress_interval=0
|
||||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
workload=system.cpu.workload
|
||||
dcache_port=system.cpu.dcache.cpu_side
|
||||
icache_port=system.cpu.icache.cpu_side
|
||||
|
||||
[system.cpu.dcache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=262144
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.dcache_port
|
||||
mem_side=system.cpu.toL2Bus.slave[1]
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=X86TLB
|
||||
children=walker
|
||||
size=64
|
||||
walker=system.cpu.dtb.walker
|
||||
|
||||
[system.cpu.dtb.walker]
|
||||
type=X86PagetableWalker
|
||||
system=system
|
||||
port=system.cpu.toL2Bus.slave[3]
|
||||
|
||||
[system.cpu.icache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=131072
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.icache_port
|
||||
mem_side=system.cpu.toL2Bus.slave[0]
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=X86LocalApic
|
||||
int_latency=1000
|
||||
pio_addr=2305843009213693952
|
||||
pio_latency=1000
|
||||
system=system
|
||||
int_master=system.membus.slave[2]
|
||||
int_slave=system.membus.master[2]
|
||||
pio=system.membus.master[1]
|
||||
|
||||
[system.cpu.itb]
|
||||
type=X86TLB
|
||||
children=walker
|
||||
size=64
|
||||
walker=system.cpu.itb.walker
|
||||
|
||||
[system.cpu.itb.walker]
|
||||
type=X86PagetableWalker
|
||||
system=system
|
||||
port=system.cpu.toL2Bus.slave[2]
|
||||
|
||||
[system.cpu.l2cache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=false
|
||||
latency=10000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=2097152
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.toL2Bus.master[0]
|
||||
mem_side=system.membus.slave[1]
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
master=system.cpu.l2cache.cpu_side
|
||||
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
|
||||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
|
||||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=gzip input.log 1
|
||||
cwd=build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/cpu2000/binaries/x86/linux/gzip
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
ppid=99
|
||||
simpoint=0
|
||||
system=system
|
||||
uid=100
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave
|
||||
slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.membus.master[0]
|
||||
|
||||
4
simulators/gem5/tests/long/se/00.gzip/ref/x86/linux/simple-timing/simerr
Executable file
4
simulators/gem5/tests/long/se/00.gzip/ref/x86/linux/simple-timing/simerr
Executable file
@ -0,0 +1,4 @@
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: instruction 'fnstcw_Mw' unimplemented
|
||||
warn: instruction 'fldcw_Mw' unimplemented
|
||||
hack: be nice to actually delete the event here
|
||||
42
simulators/gem5/tests/long/se/00.gzip/ref/x86/linux/simple-timing/simout
Executable file
42
simulators/gem5/tests/long/se/00.gzip/ref/x86/linux/simple-timing/simout
Executable file
@ -0,0 +1,42 @@
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jun 4 2012 13:44:28
|
||||
gem5 started Jun 4 2012 15:13:02
|
||||
gem5 executing on zizzer
|
||||
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
spec_init
|
||||
Loading Input Data
|
||||
Duplicating 262144 bytes
|
||||
Duplicating 524288 bytes
|
||||
Input data 1048576 bytes in length
|
||||
Compressing Input Data, level 1
|
||||
Compressed data 108074 bytes in length
|
||||
Uncompressing Data
|
||||
info: Increasing stack size by one page.
|
||||
Uncompressed data 1048576 bytes in length
|
||||
Uncompressed data compared correctly
|
||||
Compressing Input Data, level 3
|
||||
Compressed data 97831 bytes in length
|
||||
Uncompressing Data
|
||||
Uncompressed data 1048576 bytes in length
|
||||
Uncompressed data compared correctly
|
||||
Compressing Input Data, level 5
|
||||
Compressed data 83382 bytes in length
|
||||
Uncompressing Data
|
||||
Uncompressed data 1048576 bytes in length
|
||||
Uncompressed data compared correctly
|
||||
Compressing Input Data, level 7
|
||||
Compressed data 76606 bytes in length
|
||||
Uncompressing Data
|
||||
Uncompressed data 1048576 bytes in length
|
||||
Uncompressed data compared correctly
|
||||
Compressing Input Data, level 9
|
||||
Compressed data 73189 bytes in length
|
||||
Uncompressing Data
|
||||
Uncompressed data 1048576 bytes in length
|
||||
Uncompressed data compared correctly
|
||||
Tested 1MB buffer: OK!
|
||||
Exiting @ tick 1803258587000 because target called exit()
|
||||
@ -0,0 +1,374 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 1.803259 # Number of seconds simulated
|
||||
sim_ticks 1803258587000 # Number of ticks simulated
|
||||
final_tick 1803258587000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 587265 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1082068 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1203364849 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 225604 # Number of bytes of host memory used
|
||||
host_seconds 1498.51 # Real time elapsed on the host
|
||||
sim_insts 880025313 # Number of instructions simulated
|
||||
sim_ops 1621493983 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 46208 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 5679744 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 5725952 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 46208 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 46208 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 3712448 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 3712448 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 722 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 88746 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 89468 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 58007 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 58007 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 25625 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 3149711 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 3175336 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 25625 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 25625 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 2058744 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 2058744 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 2058744 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 25625 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 3149711 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 5234080 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu.workload.num_syscalls 48 # Number of system calls
|
||||
system.cpu.numCycles 3606517174 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 880025313 # Number of instructions committed
|
||||
system.cpu.committedOps 1621493983 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 1621354493 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 0 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 99478861 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 1621354493 # number of integer instructions
|
||||
system.cpu.num_fp_insts 0 # number of float instructions
|
||||
system.cpu.num_int_register_reads 5129484088 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 2493860970 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
|
||||
system.cpu.num_mem_refs 607228182 # number of memory refs
|
||||
system.cpu.num_load_insts 419042125 # Number of load instructions
|
||||
system.cpu.num_store_insts 188186057 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 3606517174 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.icache.replacements 4 # number of replacements
|
||||
system.cpu.icache.tagsinuse 660.186297 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 1186516018 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 722 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 1643373.986150 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 660.186297 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.322357 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.322357 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 1186516018 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 1186516018 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 1186516018 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 1186516018 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 1186516018 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 1186516018 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 722 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 722 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 722 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 722 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 722 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 722 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 40432000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 40432000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 40432000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 40432000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 40432000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 40432000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 1186516740 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 1186516740 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 1186516740 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 1186516740 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 1186516740 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 1186516740 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000001 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.000001 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000001 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.000001 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000001 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000001 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56000 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 56000 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 56000 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 56000 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 56000 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 56000 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 722 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 722 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 722 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 722 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 722 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 722 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 38266000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 38266000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 38266000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 38266000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 38266000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 38266000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000001 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000001 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000001 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53000 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 437952 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 4094.896939 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 606786134 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 442048 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 1372.670239 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 778540000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 4094.896939 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.999731 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.999731 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 418844799 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 418844799 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 187941335 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 187941335 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 606786134 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 606786134 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 606786134 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 606786134 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 197326 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 197326 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 244722 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 244722 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 442048 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 442048 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 442048 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 442048 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 4043270000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 4043270000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 5872734000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 5872734000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 9916004000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 9916004000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 9916004000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 9916004000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 419042125 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 419042125 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 188186057 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 188186057 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 607228182 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 607228182 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 607228182 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 607228182 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000471 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.000471 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001300 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.001300 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.000728 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.000728 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.000728 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.000728 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20490.305383 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 20490.305383 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 23997.572756 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 23997.572756 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 22431.962140 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 22431.962140 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 22431.962140 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 22431.962140 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 396372 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 396372 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 197326 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 197326 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 244722 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 244722 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 442048 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 442048 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 442048 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 442048 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3451292000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 3451292000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5138568000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 5138568000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8589860000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 8589860000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8589860000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 8589860000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000471 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000471 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001300 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.001300 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000728 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.000728 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000728 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.000728 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17490.305383 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17490.305383 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 20997.572756 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 20997.572756 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19431.962140 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 19431.962140 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19431.962140 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 19431.962140 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 71208 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 18056.923092 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 423014 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 86793 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 4.873826 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::writebacks 16187.723361 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 48.180025 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 1821.019706 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.494010 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.001470 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.055573 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.551054 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 166833 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 166833 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 396372 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 396372 # number of Writeback hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 186469 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 186469 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 353302 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 353302 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 353302 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 353302 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 722 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.data 30493 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 31215 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 58253 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 58253 # number of ReadExReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 722 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 88746 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 89468 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 722 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 88746 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 89468 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 37544000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1585636000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 1623180000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3029156000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 3029156000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 37544000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 4614792000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 4652336000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 37544000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 4614792000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 4652336000 # number of overall miss cycles
|
||||
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|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 197326 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 198048 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 396372 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 396372 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 244722 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 244722 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 722 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 442048 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 442770 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 722 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 442048 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 442770 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.154531 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.157613 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.238037 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.238037 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.200761 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.202064 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.200761 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.202064 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks::writebacks 58007 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 58007 # number of writebacks
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 722 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 30493 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::total 31215 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 58253 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 58253 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 722 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 88746 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 89468 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 722 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 88746 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 89468 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 28880000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1219720000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1248600000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2330120000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2330120000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 28880000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3549840000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 3578720000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 28880000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3549840000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 3578720000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.154531 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.157613 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.238037 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.238037 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.200761 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.202064 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.200761 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.202064 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
33
simulators/gem5/tests/long/se/00.gzip/test.py
Normal file
33
simulators/gem5/tests/long/se/00.gzip/test.py
Normal file
@ -0,0 +1,33 @@
|
||||
# Copyright (c) 2006-2007 The Regents of The University of Michigan
|
||||
# All rights reserved.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are
|
||||
# met: redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer;
|
||||
# redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in the
|
||||
# documentation and/or other materials provided with the distribution;
|
||||
# neither the name of the copyright holders nor the names of its
|
||||
# contributors may be used to endorse or promote products derived from
|
||||
# this software without specific prior written permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
#
|
||||
# Authors: Korey Sewell
|
||||
|
||||
m5.util.addToPath('../configs/common')
|
||||
from cpu2000 import gzip_log
|
||||
|
||||
workload = gzip_log(isa, opsys, 'smred')
|
||||
root.system.cpu.workload = workload.makeLiveProcess()
|
||||
@ -0,0 +1,4 @@
|
||||
P6
|
||||
15 15
|
||||
255
|
||||
|
||||
@ -0,0 +1,547 @@
|
||||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
full_system=false
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
||||
[system]
|
||||
type=System
|
||||
children=cpu membus physmem
|
||||
boot_osflags=a
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
mem_mode=atomic
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
readfile=
|
||||
symbolfile=
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.membus.slave[0]
|
||||
|
||||
[system.cpu]
|
||||
type=DerivO3CPU
|
||||
children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
|
||||
BTBEntries=4096
|
||||
BTBTagSize=16
|
||||
LFSTSize=1024
|
||||
LQEntries=32
|
||||
LSQCheckLoads=true
|
||||
LSQDepCheckShift=4
|
||||
RASSize=16
|
||||
SQEntries=32
|
||||
SSITSize=1024
|
||||
activity=0
|
||||
backComSize=5
|
||||
cachePorts=200
|
||||
checker=Null
|
||||
choiceCtrBits=2
|
||||
choicePredictorSize=8192
|
||||
clock=500
|
||||
commitToDecodeDelay=1
|
||||
commitToFetchDelay=1
|
||||
commitToIEWDelay=1
|
||||
commitToRenameDelay=1
|
||||
commitWidth=8
|
||||
cpu_id=0
|
||||
decodeToFetchDelay=1
|
||||
decodeToRenameDelay=1
|
||||
decodeWidth=8
|
||||
defer_registration=false
|
||||
dispatchWidth=8
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
fetchToDecodeDelay=1
|
||||
fetchTrapLatency=1
|
||||
fetchWidth=8
|
||||
forwardComSize=5
|
||||
fuPool=system.cpu.fuPool
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
globalCtrBits=2
|
||||
globalHistoryBits=13
|
||||
globalPredictorSize=8192
|
||||
iewToCommitDelay=1
|
||||
iewToDecodeDelay=1
|
||||
iewToFetchDelay=1
|
||||
iewToRenameDelay=1
|
||||
instShiftAmt=2
|
||||
interrupts=system.cpu.interrupts
|
||||
issueToExecuteDelay=1
|
||||
issueWidth=8
|
||||
itb=system.cpu.itb
|
||||
localCtrBits=2
|
||||
localHistoryBits=11
|
||||
localHistoryTableSize=2048
|
||||
localPredictorSize=2048
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
needsTSO=false
|
||||
numIQEntries=64
|
||||
numPhysFloatRegs=256
|
||||
numPhysIntRegs=256
|
||||
numROBEntries=192
|
||||
numRobs=1
|
||||
numThreads=1
|
||||
phase=0
|
||||
predType=tournament
|
||||
profile=0
|
||||
progress_interval=0
|
||||
renameToDecodeDelay=1
|
||||
renameToFetchDelay=1
|
||||
renameToIEWDelay=2
|
||||
renameToROBDelay=1
|
||||
renameWidth=8
|
||||
smtCommitPolicy=RoundRobin
|
||||
smtFetchPolicy=SingleThread
|
||||
smtIQPolicy=Partitioned
|
||||
smtIQThreshold=100
|
||||
smtLSQPolicy=Partitioned
|
||||
smtLSQThreshold=100
|
||||
smtNumFetchingThreads=1
|
||||
smtROBPolicy=Partitioned
|
||||
smtROBThreshold=100
|
||||
squashWidth=8
|
||||
store_set_clear_period=250000
|
||||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
trapLatency=13
|
||||
wbDepth=1
|
||||
wbWidth=8
|
||||
workload=system.cpu.workload
|
||||
dcache_port=system.cpu.dcache.cpu_side
|
||||
icache_port=system.cpu.icache.cpu_side
|
||||
|
||||
[system.cpu.dcache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=262144
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=20
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.dcache_port
|
||||
mem_side=system.cpu.toL2Bus.slave[1]
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
size=64
|
||||
walker=system.cpu.dtb.walker
|
||||
|
||||
[system.cpu.dtb.walker]
|
||||
type=ArmTableWalker
|
||||
max_backoff=100000
|
||||
min_backoff=0
|
||||
sys=system
|
||||
port=system.cpu.toL2Bus.slave[3]
|
||||
|
||||
[system.cpu.fuPool]
|
||||
type=FUPool
|
||||
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
|
||||
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
|
||||
|
||||
[system.cpu.fuPool.FUList0]
|
||||
type=FUDesc
|
||||
children=opList
|
||||
count=6
|
||||
opList=system.cpu.fuPool.FUList0.opList
|
||||
|
||||
[system.cpu.fuPool.FUList0.opList]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=IntAlu
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList1]
|
||||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=2
|
||||
opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=IntMult
|
||||
opLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList1]
|
||||
type=OpDesc
|
||||
issueLat=19
|
||||
opClass=IntDiv
|
||||
opLat=20
|
||||
|
||||
[system.cpu.fuPool.FUList2]
|
||||
type=FUDesc
|
||||
children=opList0 opList1 opList2
|
||||
count=4
|
||||
opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=FloatAdd
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList1]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=FloatCmp
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList2]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=FloatCvt
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList3]
|
||||
type=FUDesc
|
||||
children=opList0 opList1 opList2
|
||||
count=2
|
||||
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=FloatMult
|
||||
opLat=4
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList1]
|
||||
type=OpDesc
|
||||
issueLat=12
|
||||
opClass=FloatDiv
|
||||
opLat=12
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList2]
|
||||
type=OpDesc
|
||||
issueLat=24
|
||||
opClass=FloatSqrt
|
||||
opLat=24
|
||||
|
||||
[system.cpu.fuPool.FUList4]
|
||||
type=FUDesc
|
||||
children=opList
|
||||
count=0
|
||||
opList=system.cpu.fuPool.FUList4.opList
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5]
|
||||
type=FUDesc
|
||||
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
|
||||
count=4
|
||||
opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList00]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdAdd
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList01]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdAddAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList02]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdAlu
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList03]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdCmp
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList04]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdCvt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList05]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdMisc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList06]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdMult
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList07]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdMultAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList08]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdShift
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList09]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdShiftAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList10]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdSqrt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList11]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatAdd
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList12]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatAlu
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList13]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatCmp
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList14]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatCvt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList15]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatDiv
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList16]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatMisc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList17]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatMult
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList18]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatMultAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList19]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatSqrt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList6]
|
||||
type=FUDesc
|
||||
children=opList
|
||||
count=0
|
||||
opList=system.cpu.fuPool.FUList6.opList
|
||||
|
||||
[system.cpu.fuPool.FUList6.opList]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList7]
|
||||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=4
|
||||
opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList1]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList8]
|
||||
type=FUDesc
|
||||
children=opList
|
||||
count=1
|
||||
opList=system.cpu.fuPool.FUList8.opList
|
||||
|
||||
[system.cpu.fuPool.FUList8.opList]
|
||||
type=OpDesc
|
||||
issueLat=3
|
||||
opClass=IprAccess
|
||||
opLat=3
|
||||
|
||||
[system.cpu.icache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=131072
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=20
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.icache_port
|
||||
mem_side=system.cpu.toL2Bus.slave[0]
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=ArmInterrupts
|
||||
|
||||
[system.cpu.itb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
size=64
|
||||
walker=system.cpu.itb.walker
|
||||
|
||||
[system.cpu.itb.walker]
|
||||
type=ArmTableWalker
|
||||
max_backoff=100000
|
||||
min_backoff=0
|
||||
sys=system
|
||||
port=system.cpu.toL2Bus.slave[2]
|
||||
|
||||
[system.cpu.l2cache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=false
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=2097152
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.toL2Bus.master[0]
|
||||
mem_side=system.membus.slave[1]
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
master=system.cpu.l2cache.cpu_side
|
||||
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
|
||||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
|
||||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=mcf mcf.in
|
||||
cwd=build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/cpu2000/binaries/arm/linux/mcf
|
||||
gid=100
|
||||
input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
ppid=99
|
||||
simpoint=55300000000
|
||||
system=system
|
||||
uid=100
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
master=system.physmem.port[0]
|
||||
slave=system.system_port system.cpu.l2cache.mem_side
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:268435455
|
||||
zero=false
|
||||
port=system.membus.master[0]
|
||||
|
||||
@ -0,0 +1,999 @@
|
||||
()
|
||||
500
|
||||
()
|
||||
499
|
||||
()
|
||||
498
|
||||
()
|
||||
496
|
||||
()
|
||||
495
|
||||
()
|
||||
494
|
||||
()
|
||||
493
|
||||
()
|
||||
492
|
||||
()
|
||||
491
|
||||
()
|
||||
490
|
||||
()
|
||||
489
|
||||
()
|
||||
488
|
||||
()
|
||||
487
|
||||
()
|
||||
486
|
||||
()
|
||||
484
|
||||
()
|
||||
482
|
||||
()
|
||||
481
|
||||
()
|
||||
480
|
||||
()
|
||||
479
|
||||
()
|
||||
478
|
||||
()
|
||||
477
|
||||
()
|
||||
476
|
||||
()
|
||||
475
|
||||
()
|
||||
474
|
||||
()
|
||||
473
|
||||
()
|
||||
472
|
||||
()
|
||||
471
|
||||
()
|
||||
469
|
||||
()
|
||||
468
|
||||
()
|
||||
467
|
||||
()
|
||||
466
|
||||
()
|
||||
465
|
||||
()
|
||||
464
|
||||
()
|
||||
463
|
||||
()
|
||||
462
|
||||
()
|
||||
461
|
||||
()
|
||||
460
|
||||
()
|
||||
459
|
||||
()
|
||||
458
|
||||
()
|
||||
457
|
||||
()
|
||||
455
|
||||
()
|
||||
454
|
||||
()
|
||||
452
|
||||
()
|
||||
451
|
||||
()
|
||||
450
|
||||
()
|
||||
449
|
||||
()
|
||||
448
|
||||
()
|
||||
446
|
||||
()
|
||||
445
|
||||
()
|
||||
444
|
||||
()
|
||||
443
|
||||
()
|
||||
442
|
||||
()
|
||||
440
|
||||
()
|
||||
439
|
||||
()
|
||||
438
|
||||
()
|
||||
436
|
||||
()
|
||||
435
|
||||
()
|
||||
433
|
||||
()
|
||||
432
|
||||
()
|
||||
431
|
||||
()
|
||||
428
|
||||
()
|
||||
427
|
||||
()
|
||||
425
|
||||
()
|
||||
424
|
||||
()
|
||||
423
|
||||
()
|
||||
420
|
||||
()
|
||||
419
|
||||
()
|
||||
416
|
||||
()
|
||||
414
|
||||
()
|
||||
413
|
||||
()
|
||||
412
|
||||
()
|
||||
407
|
||||
()
|
||||
406
|
||||
()
|
||||
405
|
||||
()
|
||||
404
|
||||
()
|
||||
403
|
||||
()
|
||||
402
|
||||
()
|
||||
401
|
||||
()
|
||||
400
|
||||
()
|
||||
399
|
||||
()
|
||||
398
|
||||
()
|
||||
396
|
||||
()
|
||||
395
|
||||
()
|
||||
393
|
||||
()
|
||||
392
|
||||
()
|
||||
390
|
||||
()
|
||||
389
|
||||
()
|
||||
388
|
||||
()
|
||||
387
|
||||
()
|
||||
386
|
||||
()
|
||||
385
|
||||
()
|
||||
384
|
||||
()
|
||||
383
|
||||
()
|
||||
382
|
||||
()
|
||||
381
|
||||
()
|
||||
380
|
||||
()
|
||||
379
|
||||
()
|
||||
377
|
||||
()
|
||||
375
|
||||
()
|
||||
374
|
||||
()
|
||||
373
|
||||
()
|
||||
372
|
||||
()
|
||||
371
|
||||
()
|
||||
370
|
||||
()
|
||||
369
|
||||
()
|
||||
368
|
||||
()
|
||||
366
|
||||
()
|
||||
365
|
||||
()
|
||||
364
|
||||
()
|
||||
362
|
||||
()
|
||||
361
|
||||
()
|
||||
360
|
||||
()
|
||||
359
|
||||
()
|
||||
358
|
||||
()
|
||||
357
|
||||
()
|
||||
356
|
||||
()
|
||||
355
|
||||
()
|
||||
354
|
||||
()
|
||||
352
|
||||
()
|
||||
350
|
||||
()
|
||||
347
|
||||
()
|
||||
344
|
||||
()
|
||||
342
|
||||
()
|
||||
341
|
||||
()
|
||||
340
|
||||
()
|
||||
339
|
||||
()
|
||||
338
|
||||
()
|
||||
332
|
||||
()
|
||||
325
|
||||
()
|
||||
320
|
||||
***
|
||||
345
|
||||
()
|
||||
319
|
||||
***
|
||||
497
|
||||
()
|
||||
318
|
||||
***
|
||||
349
|
||||
()
|
||||
317
|
||||
***
|
||||
408
|
||||
()
|
||||
316
|
||||
***
|
||||
324
|
||||
()
|
||||
315
|
||||
***
|
||||
328
|
||||
()
|
||||
314
|
||||
***
|
||||
335
|
||||
()
|
||||
313
|
||||
***
|
||||
378
|
||||
()
|
||||
312
|
||||
***
|
||||
426
|
||||
()
|
||||
311
|
||||
***
|
||||
411
|
||||
()
|
||||
304
|
||||
***
|
||||
343
|
||||
()
|
||||
303
|
||||
***
|
||||
417
|
||||
()
|
||||
302
|
||||
***
|
||||
485
|
||||
()
|
||||
301
|
||||
***
|
||||
363
|
||||
()
|
||||
300
|
||||
***
|
||||
376
|
||||
()
|
||||
299
|
||||
***
|
||||
333
|
||||
()
|
||||
292
|
||||
***
|
||||
337
|
||||
()
|
||||
291
|
||||
***
|
||||
409
|
||||
()
|
||||
290
|
||||
***
|
||||
421
|
||||
()
|
||||
289
|
||||
***
|
||||
437
|
||||
()
|
||||
288
|
||||
***
|
||||
430
|
||||
()
|
||||
287
|
||||
***
|
||||
348
|
||||
()
|
||||
286
|
||||
***
|
||||
326
|
||||
()
|
||||
284
|
||||
()
|
||||
282
|
||||
***
|
||||
308
|
||||
()
|
||||
279
|
||||
***
|
||||
297
|
||||
***
|
||||
305
|
||||
()
|
||||
278
|
||||
()
|
||||
277
|
||||
***
|
||||
307
|
||||
()
|
||||
276
|
||||
***
|
||||
296
|
||||
()
|
||||
273
|
||||
()
|
||||
271
|
||||
()
|
||||
265
|
||||
()
|
||||
246
|
||||
***
|
||||
267
|
||||
()
|
||||
245
|
||||
***
|
||||
280
|
||||
()
|
||||
244
|
||||
***
|
||||
391
|
||||
()
|
||||
243
|
||||
***
|
||||
330
|
||||
()
|
||||
242
|
||||
***
|
||||
456
|
||||
()
|
||||
241
|
||||
***
|
||||
346
|
||||
()
|
||||
240
|
||||
***
|
||||
483
|
||||
()
|
||||
239
|
||||
***
|
||||
260
|
||||
()
|
||||
238
|
||||
***
|
||||
261
|
||||
()
|
||||
237
|
||||
***
|
||||
262
|
||||
***
|
||||
294
|
||||
()
|
||||
236
|
||||
***
|
||||
253
|
||||
()
|
||||
229
|
||||
***
|
||||
397
|
||||
()
|
||||
228
|
||||
***
|
||||
298
|
||||
()
|
||||
227
|
||||
***
|
||||
415
|
||||
()
|
||||
226
|
||||
***
|
||||
264
|
||||
()
|
||||
224
|
||||
***
|
||||
232
|
||||
()
|
||||
222
|
||||
***
|
||||
233
|
||||
()
|
||||
217
|
||||
***
|
||||
250
|
||||
()
|
||||
211
|
||||
***
|
||||
331
|
||||
()
|
||||
210
|
||||
***
|
||||
394
|
||||
()
|
||||
209
|
||||
***
|
||||
410
|
||||
()
|
||||
208
|
||||
***
|
||||
321
|
||||
()
|
||||
207
|
||||
***
|
||||
327
|
||||
()
|
||||
206
|
||||
***
|
||||
309
|
||||
()
|
||||
199
|
||||
***
|
||||
259
|
||||
()
|
||||
198
|
||||
***
|
||||
219
|
||||
()
|
||||
197
|
||||
***
|
||||
220
|
||||
()
|
||||
195
|
||||
***
|
||||
429
|
||||
()
|
||||
194
|
||||
***
|
||||
470
|
||||
()
|
||||
193
|
||||
***
|
||||
274
|
||||
()
|
||||
191
|
||||
***
|
||||
203
|
||||
()
|
||||
190
|
||||
***
|
||||
263
|
||||
()
|
||||
189
|
||||
215
|
||||
***
|
||||
230
|
||||
()
|
||||
188
|
||||
***
|
||||
266
|
||||
***
|
||||
295
|
||||
()
|
||||
182
|
||||
***
|
||||
329
|
||||
()
|
||||
181
|
||||
***
|
||||
351
|
||||
()
|
||||
180
|
||||
***
|
||||
441
|
||||
()
|
||||
179
|
||||
***
|
||||
453
|
||||
()
|
||||
178
|
||||
***
|
||||
418
|
||||
()
|
||||
177
|
||||
***
|
||||
353
|
||||
()
|
||||
176
|
||||
***
|
||||
422
|
||||
()
|
||||
175
|
||||
***
|
||||
225
|
||||
***
|
||||
255
|
||||
()
|
||||
174
|
||||
***
|
||||
269
|
||||
()
|
||||
173
|
||||
***
|
||||
214
|
||||
()
|
||||
172
|
||||
***
|
||||
186
|
||||
()
|
||||
171
|
||||
***
|
||||
447
|
||||
()
|
||||
170
|
||||
***
|
||||
270
|
||||
***
|
||||
306
|
||||
()
|
||||
169
|
||||
***
|
||||
336
|
||||
()
|
||||
168
|
||||
***
|
||||
285
|
||||
()
|
||||
165
|
||||
***
|
||||
249
|
||||
()
|
||||
146
|
||||
***
|
||||
154
|
||||
()
|
||||
143
|
||||
***
|
||||
334
|
||||
()
|
||||
142
|
||||
***
|
||||
216
|
||||
***
|
||||
257
|
||||
()
|
||||
141
|
||||
***
|
||||
167
|
||||
***
|
||||
251
|
||||
()
|
||||
140
|
||||
***
|
||||
162
|
||||
***
|
||||
293
|
||||
()
|
||||
139
|
||||
***
|
||||
158
|
||||
()
|
||||
137
|
||||
***
|
||||
166
|
||||
***
|
||||
201
|
||||
()
|
||||
136
|
||||
***
|
||||
160
|
||||
()
|
||||
134
|
||||
***
|
||||
221
|
||||
()
|
||||
132
|
||||
***
|
||||
213
|
||||
()
|
||||
131
|
||||
***
|
||||
187
|
||||
()
|
||||
129
|
||||
***
|
||||
235
|
||||
()
|
||||
128
|
||||
***
|
||||
153
|
||||
()
|
||||
127
|
||||
***
|
||||
156
|
||||
()
|
||||
126
|
||||
***
|
||||
159
|
||||
***
|
||||
218
|
||||
()
|
||||
125
|
||||
***
|
||||
155
|
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()
|
||||
124
|
||||
***
|
||||
157
|
||||
()
|
||||
123
|
||||
***
|
||||
152
|
||||
()
|
||||
116
|
||||
***
|
||||
135
|
||||
***
|
||||
163
|
||||
()
|
||||
115
|
||||
***
|
||||
133
|
||||
***
|
||||
204
|
||||
***
|
||||
248
|
||||
()
|
||||
114
|
||||
***
|
||||
192
|
||||
***
|
||||
212
|
||||
()
|
||||
113
|
||||
***
|
||||
268
|
||||
()
|
||||
112
|
||||
***
|
||||
367
|
||||
()
|
||||
111
|
||||
***
|
||||
272
|
||||
()
|
||||
110
|
||||
***
|
||||
434
|
||||
()
|
||||
109
|
||||
***
|
||||
323
|
||||
()
|
||||
108
|
||||
***
|
||||
281
|
||||
()
|
||||
107
|
||||
***
|
||||
144
|
||||
***
|
||||
148
|
||||
()
|
||||
106
|
||||
***
|
||||
275
|
||||
()
|
||||
105
|
||||
***
|
||||
196
|
||||
***
|
||||
254
|
||||
()
|
||||
104
|
||||
***
|
||||
138
|
||||
***
|
||||
161
|
||||
()
|
||||
103
|
||||
***
|
||||
310
|
||||
()
|
||||
102
|
||||
***
|
||||
223
|
||||
***
|
||||
252
|
||||
()
|
||||
80
|
||||
()
|
||||
70
|
||||
()
|
||||
69
|
||||
()
|
||||
68
|
||||
()
|
||||
66
|
||||
()
|
||||
64
|
||||
()
|
||||
62
|
||||
***
|
||||
256
|
||||
()
|
||||
61
|
||||
***
|
||||
93
|
||||
()
|
||||
59
|
||||
***
|
||||
120
|
||||
()
|
||||
58
|
||||
()
|
||||
57
|
||||
***
|
||||
183
|
||||
()
|
||||
55
|
||||
()
|
||||
54
|
||||
()
|
||||
52
|
||||
***
|
||||
147
|
||||
()
|
||||
51
|
||||
***
|
||||
118
|
||||
()
|
||||
50
|
||||
***
|
||||
83
|
||||
()
|
||||
49
|
||||
***
|
||||
98
|
||||
()
|
||||
48
|
||||
***
|
||||
99
|
||||
()
|
||||
47
|
||||
()
|
||||
46
|
||||
***
|
||||
184
|
||||
()
|
||||
45
|
||||
***
|
||||
121
|
||||
()
|
||||
44
|
||||
()
|
||||
43
|
||||
***
|
||||
88
|
||||
()
|
||||
42
|
||||
***
|
||||
122
|
||||
()
|
||||
41
|
||||
***
|
||||
91
|
||||
()
|
||||
40
|
||||
***
|
||||
96
|
||||
()
|
||||
38
|
||||
***
|
||||
100
|
||||
()
|
||||
37
|
||||
***
|
||||
149
|
||||
()
|
||||
36
|
||||
***
|
||||
74
|
||||
()
|
||||
35
|
||||
***
|
||||
258
|
||||
()
|
||||
34
|
||||
***
|
||||
151
|
||||
()
|
||||
33
|
||||
***
|
||||
85
|
||||
()
|
||||
32
|
||||
()
|
||||
31
|
||||
***
|
||||
94
|
||||
()
|
||||
30
|
||||
***
|
||||
97
|
||||
()
|
||||
29
|
||||
***
|
||||
90
|
||||
()
|
||||
28
|
||||
***
|
||||
89
|
||||
()
|
||||
27
|
||||
***
|
||||
92
|
||||
()
|
||||
26
|
||||
***
|
||||
72
|
||||
***
|
||||
247
|
||||
()
|
||||
25
|
||||
***
|
||||
86
|
||||
()
|
||||
24
|
||||
***
|
||||
82
|
||||
()
|
||||
23
|
||||
***
|
||||
87
|
||||
***
|
||||
117
|
||||
()
|
||||
22
|
||||
***
|
||||
76
|
||||
***
|
||||
119
|
||||
()
|
||||
21
|
||||
***
|
||||
84
|
||||
()
|
||||
20
|
||||
***
|
||||
78
|
||||
()
|
||||
19
|
||||
***
|
||||
73
|
||||
()
|
||||
18
|
||||
***
|
||||
81
|
||||
()
|
||||
17
|
||||
***
|
||||
65
|
||||
()
|
||||
16
|
||||
***
|
||||
63
|
||||
***
|
||||
101
|
||||
()
|
||||
15
|
||||
***
|
||||
71
|
||||
()
|
||||
14
|
||||
***
|
||||
75
|
||||
()
|
||||
13
|
||||
***
|
||||
322
|
||||
()
|
||||
12
|
||||
***
|
||||
77
|
||||
()
|
||||
11
|
||||
***
|
||||
283
|
||||
()
|
||||
10
|
||||
***
|
||||
79
|
||||
()
|
||||
9
|
||||
***
|
||||
145
|
||||
***
|
||||
150
|
||||
()
|
||||
8
|
||||
***
|
||||
67
|
||||
()
|
||||
7
|
||||
***
|
||||
60
|
||||
***
|
||||
231
|
||||
()
|
||||
6
|
||||
***
|
||||
56
|
||||
***
|
||||
234
|
||||
()
|
||||
5
|
||||
***
|
||||
164
|
||||
***
|
||||
202
|
||||
()
|
||||
4
|
||||
***
|
||||
53
|
||||
()
|
||||
3
|
||||
***
|
||||
130
|
||||
***
|
||||
185
|
||||
***
|
||||
200
|
||||
()
|
||||
2
|
||||
***
|
||||
205
|
||||
()
|
||||
1
|
||||
***
|
||||
39
|
||||
***
|
||||
95
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user