Adding gem5 source to svn.

git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1819 8c4709b5-6ec9-48aa-a5cd-a96041d1645a

simulators/gem5/tests/SConscript

@@ -0,0 +1,333 @@
+# -*- mode:python -*-
+
+# Copyright (c) 2004-2006 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Steve Reinhardt
+#          Kevin Lim
+
+import os, signal
+import sys, time
+import glob
+from SCons.Script.SConscript import SConsEnvironment
+
+Import('env')
+
+env['DIFFOUT'] = File('diff-out')
+
+# get the termcap from the environment
+termcap = env['TERMCAP']
+
+# Dict that accumulates lists of tests by category (quick, medium, long)
+env.Tests = {}
+
+def contents(node):
+    return file(str(node)).read()
+
+# functions to parse return value from scons Execute()... not the same
+# as wait() etc., so python built-in os funcs don't work.
+def signaled(status):
+    return (status & 0x80) != 0;
+
+def signum(status):
+    return (status & 0x7f);
+
+# List of signals that indicate that we should retry the test rather
+# than consider it failed.
+retry_signals = (signal.SIGTERM, signal.SIGKILL, signal.SIGINT,
+                 signal.SIGQUIT, signal.SIGHUP)
+
+# regular expressions of lines to ignore when diffing outputs
+output_ignore_regexes = (
+    '^command line:',		# for stdout file
+    '^M5 compiled ',		# for stderr file
+    '^M5 started ',		# for stderr file
+    '^M5 executing on ',	# for stderr file
+    '^Simulation complete at',	# for stderr file
+    '^Listening for',		# for stderr file
+    'listening for remote gdb',	# for stderr file
+    )
+
+output_ignore_args = ' '.join(["-I '"+s+"'" for s in output_ignore_regexes])
+
+output_ignore_args += ' --exclude=stats.txt --exclude=outdiff'
+
+def run_test(target, source, env):
+    """Check output from running test.
+
+    Targets are as follows:
+    target[0] : status
+
+    Sources are:
+    source[0] : M5 binary
+    source[1] : tests/run.py script
+    source[2] : reference stats file
+
+    """
+    # make sure target files are all gone
+    for t in target:
+        if os.path.exists(t.abspath):
+            env.Execute(Delete(t.abspath))
+
+    tgt_dir = os.path.dirname(str(target[0]))
+
+    # Base command for running test.  We mess around with indirectly
+    # referring to files via SOURCES and TARGETS so that scons can mess
+    # with paths all it wants to and we still get the right files.
+    cmd = '${SOURCES[0]} -d %s -re ${SOURCES[1]} %s' % (tgt_dir, tgt_dir)
+
+    # Prefix test run with batch job submission command if appropriate.
+    # Batch command also supports timeout arg (in seconds, not minutes).
+    timeout = 15 * 60 # used to be a param, probably should be again
+    if env['BATCH']:
+        cmd = '%s -t %d %s' % (env['BATCH_CMD'], timeout, cmd)
+
+    pre_exec_time = time.time()
+    status = env.Execute(env.subst(cmd, target=target, source=source))
+    if status == 0:
+        # M5 terminated normally.
+        # Run diff on output & ref directories to find differences.
+        # Exclude the stats file since we will use diff-out on that.
+
+        # NFS file systems can be annoying and not have updated yet
+        # wait until we see the file modified
+        statsdiff = os.path.join(tgt_dir, 'statsdiff')
+        m_time = 0
+        nap = 0
+        while m_time < pre_exec_time and nap < 10:
+            try:
+                m_time = os.stat(statsdiff).st_mtime
+            except OSError:
+                pass
+            time.sleep(1)
+            nap += 1
+
+        outdiff = os.path.join(tgt_dir, 'outdiff')
+        # tack 'true' on the end so scons doesn't report diff's
+        # non-zero exit code as a build error
+        diffcmd = 'diff -ubrs %s ${SOURCES[2].dir} %s > %s; true' \
+                  % (output_ignore_args, tgt_dir, outdiff)
+        env.Execute(env.subst(diffcmd, target=target, source=source))
+        print "===== Output differences ====="
+        print contents(outdiff)
+        # Run diff-out on stats.txt file
+        diffcmd = '$DIFFOUT ${SOURCES[2]} %s > %s' \
+                  % (os.path.join(tgt_dir, 'stats.txt'), statsdiff)
+        diffcmd = env.subst(diffcmd, target=target, source=source)
+        status = env.Execute(diffcmd, strfunction=None)
+        print "===== Statistics differences ====="
+        print contents(statsdiff)
+
+    else: # m5 exit status != 0
+        # M5 did not terminate properly, so no need to check the output
+        if signaled(status):
+            print 'M5 terminated with signal', signum(status)
+            if signum(status) in retry_signals:
+                # Consider the test incomplete; don't create a 'status' output.
+                # Hand the return status to scons and let scons decide what
+                # to do about it (typically terminate unless run with -k).
+                return status
+        else:
+            print 'M5 exited with non-zero status', status
+        # complete but failed execution (call to exit() with non-zero
+        # status, SIGABORT due to assertion failure, etc.)... fall through
+        # and generate FAILED status as if output comparison had failed
+
+    # Generate status file contents based on exit status of m5 or diff-out
+    if status == 0:
+        status_str = "passed."
+    else:
+        status_str = "FAILED!"
+    f = file(str(target[0]), 'w')
+    print >>f, tgt_dir, status_str
+    f.close()
+    # done
+    return 0
+
+def run_test_string(target, source, env):
+    return env.subst("Running test in ${TARGETS[0].dir}.",
+                     target=target, source=source)
+
+testAction = env.Action(run_test, run_test_string)
+
+def print_test(target, source, env):
+    # print the status with colours to make it easier to see what
+    # passed and what failed
+    line = contents(source[0])
+
+    # split the line to words and get the last one
+    words = line.split()
+    status = words[-1]
+
+    # if the test failed make it red, if it passed make it green, and
+    # skip the punctuation
+    if status == "FAILED!":
+        status = termcap.Red + status[:-1] + termcap.Normal + status[-1]
+    elif status == "passed.":
+        status = termcap.Green + status[:-1] + termcap.Normal + status[-1]
+
+    # put it back in the list and join with space
+    words[-1] = status
+    line = " ".join(words)
+
+    print '***** ' + line
+    return 0
+
+printAction = env.Action(print_test, strfunction = None)
+
+# Static vars for update_test:
+# - long-winded message about ignored sources
+ignore_msg = '''
+Note: The following file(s) will not be copied.  New non-standard
+      output files must be copied manually once before --update-ref will
+      recognize them as outputs.  Otherwise they are assumed to be
+      inputs and are ignored.
+'''
+# - reference files always needed
+needed_files = set(['simout', 'simerr', 'stats.txt', 'config.ini'])
+# - source files we always want to ignore
+known_ignores = set(['status', 'outdiff', 'statsdiff'])
+
+def update_test(target, source, env):
+    """Update reference test outputs.
+
+    Target is phony.  First two sources are the ref & new stats.txt file
+    files, respectively.  We actually copy everything in the
+    respective directories except the status & diff output files.
+
+    """
+    dest_dir = str(source[0].get_dir())
+    src_dir = str(source[1].get_dir())
+    dest_files = set(os.listdir(dest_dir))
+    src_files = set(os.listdir(src_dir))
+    # Copy all of the required files plus any existing dest files.
+    wanted_files = needed_files | dest_files
+    missing_files = wanted_files - src_files
+    if len(missing_files) > 0:
+        print "  WARNING: the following file(s) are missing " \
+              "and will not be updated:"
+        print "    ", " ,".join(missing_files)
+    copy_files = wanted_files - missing_files
+    warn_ignored_files = (src_files - copy_files) - known_ignores
+    if len(warn_ignored_files) > 0:
+        print ignore_msg,
+        print "       ", ", ".join(warn_ignored_files)
+    for f in copy_files:
+        if f in dest_files:
+            print "  Replacing file", f
+            dest_files.remove(f)
+        else:
+            print "  Creating new file", f
+        copyAction = Copy(os.path.join(dest_dir, f), os.path.join(src_dir, f))
+        copyAction.strfunction = None
+        env.Execute(copyAction)
+    return 0
+
+def update_test_string(target, source, env):
+    return env.subst("Updating ${SOURCES[0].dir} from ${SOURCES[1].dir}",
+                     target=target, source=source)
+
+updateAction = env.Action(update_test, update_test_string)
+
+def test_builder(env, ref_dir):
+    """Define a test."""
+
+    (category, mode, name, _ref, isa, opsys, config) = ref_dir.split('/')
+    assert(_ref == 'ref')
+
+    # target path (where test output goes) is the same except without
+    # the 'ref' component
+    tgt_dir = os.path.join(category, mode, name, isa, opsys, config)
+
+    # prepend file name with tgt_dir
+    def tgt(f):
+        return os.path.join(tgt_dir, f)
+
+    ref_stats = os.path.join(ref_dir, 'stats.txt')
+    new_stats = tgt('stats.txt')
+    status_file = tgt('status')
+
+    env.Command([status_file],
+                [env.M5Binary, 'run.py', ref_stats],
+                testAction)
+
+    # phony target to echo status
+    if GetOption('update_ref'):
+        p = env.Command(tgt('_update'),
+                        [ref_stats, new_stats, status_file],
+                        updateAction)
+    else:
+        p = env.Command(tgt('_print'), [status_file], printAction)
+
+    env.AlwaysBuild(p)
+
+
+# Figure out applicable configs based on build type
+configs = []
+if env['TARGET_ISA'] == 'alpha':
+    configs += ['tsunami-simple-atomic',
+                'tsunami-simple-timing',
+                'tsunami-simple-atomic-dual',
+                'tsunami-simple-timing-dual',
+                'twosys-tsunami-simple-atomic',
+                'tsunami-o3', 'tsunami-o3-dual',
+                'tsunami-inorder']
+if env['TARGET_ISA'] == 'sparc':
+    configs += ['t1000-simple-atomic',
+                't1000-simple-timing']
+if env['TARGET_ISA'] == 'arm':
+    configs += ['simple-atomic-dummychecker',
+                'o3-timing-checker',
+                'realview-simple-atomic',
+                'realview-simple-atomic-dual',
+                'realview-simple-timing',
+                'realview-simple-timing-dual',
+                'realview-o3',
+                'realview-o3-checker',
+                'realview-o3-dual']
+if env['TARGET_ISA'] == 'x86':
+    configs += ['pc-simple-atomic',
+                'pc-simple-timing',
+                'pc-o3-timing']
+
+configs += ['simple-atomic', 'simple-timing', 'o3-timing', 'memtest',
+            'simple-atomic-mp', 'simple-timing-mp', 'o3-timing-mp',
+            'inorder-timing', 'rubytest']
+
+if env['PROTOCOL'] != 'None':
+    if env['PROTOCOL'] == 'MI_example':
+        configs += [c + "-ruby" for c in configs]
+    else:
+        configs = [c + "-ruby-" + env['PROTOCOL'] for c in configs]
+
+cwd = os.getcwd()
+os.chdir(str(Dir('.').srcdir))
+for config in configs:
+    dirs = glob.glob('*/*/*/ref/%s/*/%s' % (env['TARGET_ISA'], config))
+    for d in dirs:
+        if not os.path.exists(os.path.join(d, 'skip')):
+            test_builder(env, d)
+os.chdir(cwd)

simulators/gem5/tests/configs/inorder-timing.py

@@ -0,0 +1,59 @@
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Steve Reinhardt
+
+import m5
+from m5.objects import *
+m5.util.addToPath('../configs/common')
+
+class MyCache(BaseCache):
+    assoc = 2
+    block_size = 64
+    latency = '1ns'
+    mshrs = 10
+    tgts_per_mshr = 5
+
+class MyL1Cache(MyCache):
+    is_top_level = True
+
+cpu = InOrderCPU(cpu_id=0)
+cpu.addTwoLevelCacheHierarchy(MyL1Cache(size = '128kB'),
+                              MyL1Cache(size = '256kB'),
+                              MyCache(size = '2MB', latency='10ns'))
+
+cpu.clock = '2GHz'
+
+system = System(cpu = cpu,
+                physmem = SimpleMemory(),
+                membus = CoherentBus())
+system.system_port = system.membus.slave
+system.physmem.port = system.membus.master
+# create the interrupt controller
+cpu.createInterruptController()
+cpu.connectAllPorts(system.membus)
+
+root = Root(full_system = False, system = system)

simulators/gem5/tests/configs/memtest-ruby.py

@@ -0,0 +1,115 @@
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
+# Copyright (c) 2010 Advanced Micro Devices, Inc.
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Ron Dreslinski
+
+import m5
+from m5.objects import *
+from m5.defines import buildEnv
+from m5.util import addToPath
+import os, optparse, sys
+
+# Get paths we might need
+config_path = os.path.dirname(os.path.abspath(__file__))
+config_root = os.path.dirname(config_path)
+m5_root = os.path.dirname(config_root)
+addToPath(config_root+'/configs/common')
+addToPath(config_root+'/configs/ruby')
+
+import Ruby
+import Options
+
+parser = optparse.OptionParser()
+Options.addCommonOptions(parser)
+
+# Add the ruby specific and protocol specific options
+Ruby.define_options(parser)
+
+(options, args) = parser.parse_args()
+
+#
+# Set the default cache size and associativity to be very small to encourage
+# races between requests and writebacks.
+#
+options.l1d_size="256B"
+options.l1i_size="256B"
+options.l2_size="512B"
+options.l3_size="1kB"
+options.l1d_assoc=2
+options.l1i_assoc=2
+options.l2_assoc=2
+options.l3_assoc=2
+
+#MAX CORES IS 8 with the fals sharing method
+nb_cores = 8
+
+# ruby does not support atomic, functional, or uncacheable accesses
+cpus = [ MemTest(atomic=False, percent_functional=50,
+                 percent_uncacheable=0, suppress_func_warnings=True) \
+         for i in xrange(nb_cores) ]
+
+# overwrite options.num_cpus with the nb_cores value
+options.num_cpus = nb_cores
+ 
+# system simulated
+system = System(cpu = cpus,
+                funcmem = SimpleMemory(in_addr_map = False),
+                physmem = SimpleMemory())
+
+Ruby.create_system(options, system)
+
+assert(len(cpus) == len(system.ruby._cpu_ruby_ports))
+
+for (i, ruby_port) in enumerate(system.ruby._cpu_ruby_ports):
+     #
+     # Tie the cpu test and functional ports to the ruby cpu ports and
+     # physmem, respectively
+     #
+     cpus[i].test = ruby_port.slave
+     cpus[i].functional = system.funcmem.port
+     
+     #
+     # Since the memtester is incredibly bursty, increase the deadlock
+     # threshold to 1 million cycles
+     #
+     ruby_port.deadlock_threshold = 1000000
+
+     #
+     # Ruby doesn't need the backing image of memory when running with
+     # the tester.
+     #
+     ruby_port.access_phys_mem = False
+
+# -----------------------
+# run simulation
+# -----------------------
+
+root = Root(full_system = False, system = system)
+root.system.mem_mode = 'timing'
+
+# Not much point in this being higher than the L1 latency
+m5.ticks.setGlobalFrequency('1ns')

simulators/gem5/tests/configs/memtest.py

@@ -0,0 +1,92 @@
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Ron Dreslinski
+
+import m5
+from m5.objects import *
+
+# --------------------
+# Base L1 Cache
+# ====================
+
+class L1(BaseCache):
+    latency = '1ns'
+    block_size = 64
+    mshrs = 12
+    tgts_per_mshr = 8
+    is_top_level = True
+
+# ----------------------
+# Base L2 Cache
+# ----------------------
+
+class L2(BaseCache):
+    block_size = 64
+    latency = '10ns'
+    mshrs = 92
+    tgts_per_mshr = 16
+    write_buffers = 8
+
+#MAX CORES IS 8 with the fals sharing method
+nb_cores = 8
+cpus = [ MemTest() for i in xrange(nb_cores) ]
+
+# system simulated
+system = System(cpu = cpus, funcmem = SimpleMemory(in_addr_map = False),
+                physmem = SimpleMemory(),
+                membus = CoherentBus(clock="500GHz", width=16))
+
+# l2cache & bus
+system.toL2Bus = CoherentBus(clock="500GHz", width=16)
+system.l2c = L2(size='64kB', assoc=8)
+system.l2c.cpu_side = system.toL2Bus.master
+
+# connect l2c to membus
+system.l2c.mem_side = system.membus.slave
+
+# add L1 caches
+for cpu in cpus:
+    cpu.l1c = L1(size = '32kB', assoc = 4)
+    cpu.l1c.cpu_side = cpu.test
+    cpu.l1c.mem_side = system.toL2Bus.slave
+    system.funcmem.port = cpu.functional
+
+system.system_port = system.membus.slave
+
+# connect memory to membus
+system.physmem.port = system.membus.master
+
+
+# -----------------------
+# run simulation
+# -----------------------
+
+root = Root( full_system = False, system = system )
+root.system.mem_mode = 'timing'
+#root.trace.flags="Cache CachePort MemoryAccess"
+#root.trace.cycle=1
+

simulators/gem5/tests/configs/o3-timing-checker.py

@@ -0,0 +1,68 @@
+# Copyright (c) 2011 ARM Limited
+# All rights reserved
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder.  You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Geoffrey Blake
+
+import m5
+from m5.objects import *
+m5.util.addToPath('../configs/common')
+
+class MyCache(BaseCache):
+    assoc = 2
+    block_size = 64
+    latency = '1ns'
+    mshrs = 10
+    tgts_per_mshr = 5
+
+class MyL1Cache(MyCache):
+    is_top_level = True
+    tgts_per_mshr = 20
+
+cpu = DerivO3CPU(cpu_id=0)
+cpu.createInterruptController()
+cpu.addCheckerCpu()
+cpu.addTwoLevelCacheHierarchy(MyL1Cache(size = '128kB'),
+                              MyL1Cache(size = '256kB'),
+                              MyCache(size = '2MB'))
+cpu.clock = '2GHz'
+
+system = System(cpu = cpu,
+                physmem = SimpleMemory(),
+                membus = CoherentBus())
+system.system_port = system.membus.slave
+system.physmem.port = system.membus.master
+cpu.connectAllPorts(system.membus)
+
+root = Root(full_system = False, system = system)

simulators/gem5/tests/configs/o3-timing-mp-ruby.py

@@ -0,0 +1,59 @@
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Ron Dreslinski
+
+import m5
+from m5.objects import *
+m5.util.addToPath('../configs/common')
+
+nb_cores = 4
+cpus = [ DerivO3CPU(cpu_id=i) for i in xrange(nb_cores) ]
+
+import ruby_config
+ruby_memory = ruby_config.generate("TwoLevel_SplitL1UnifiedL2.rb", nb_cores)
+
+# system simulated
+system = System(cpu = cpus, physmem = ruby_memory, membus = CoherentBus())
+
+for cpu in cpus:
+    # create the interrupt controller
+    cpu.createInterruptController()
+    cpu.connectAllPorts(system.membus)
+    cpu.clock = '2GHz'
+
+# connect memory to membus
+system.physmem.port = system.membus.master
+
+# Connect the system port for loading of binaries etc
+system.system_port = system.membus.slave
+
+# -----------------------
+# run simulation
+# -----------------------
+
+root = Root(full_system = False, system = system)
+root.system.mem_mode = 'timing'

simulators/gem5/tests/configs/o3-timing-mp.py

@@ -0,0 +1,92 @@
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Ron Dreslinski
+
+import m5
+from m5.objects import *
+m5.util.addToPath('../configs/common')
+
+# --------------------
+# Base L1 Cache
+# ====================
+
+class L1(BaseCache):
+    latency = '1ns'
+    block_size = 64
+    mshrs = 4
+    tgts_per_mshr = 20
+    is_top_level = True
+
+# ----------------------
+# Base L2 Cache
+# ----------------------
+
+class L2(BaseCache):
+    block_size = 64
+    latency = '10ns'
+    mshrs = 92
+    tgts_per_mshr = 16
+    write_buffers = 8
+
+nb_cores = 4
+cpus = [ DerivO3CPU(cpu_id=i) for i in xrange(nb_cores) ]
+
+# system simulated
+system = System(cpu = cpus, physmem = SimpleMemory(), membus = CoherentBus())
+
+# l2cache & bus
+system.toL2Bus = CoherentBus()
+system.l2c = L2(size='4MB', assoc=8)
+system.l2c.cpu_side = system.toL2Bus.master
+
+# connect l2c to membus
+system.l2c.mem_side = system.membus.slave
+
+# add L1 caches
+for cpu in cpus:
+    cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
+                                L1(size = '32kB', assoc = 4))
+    # create the interrupt controller
+    cpu.createInterruptController()
+    # connect cpu level-1 caches to shared level-2 cache
+    cpu.connectAllPorts(system.toL2Bus, system.membus)
+    cpu.clock = '2GHz'
+
+# connect memory to membus
+system.physmem.port = system.membus.master
+
+# connect system port to membus
+system.system_port = system.membus.slave
+
+# -----------------------
+# run simulation
+# -----------------------
+
+root = Root( full_system = False, system = system )
+root.system.mem_mode = 'timing'
+#root.trace.flags="Bus Cache"
+#root.trace.flags = "BusAddrRanges"

simulators/gem5/tests/configs/o3-timing-ruby.py

@@ -0,0 +1,51 @@
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Steve Reinhardt
+
+import m5
+from m5.objects import *
+m5.util.addToPath('../configs/common')
+
+
+import ruby_config
+ruby_memory = ruby_config.generate("TwoLevel_SplitL1UnifiedL2.rb", 1)
+
+cpu = DerivO3CPU(cpu_id=0)
+cpu.clock = '2GHz'
+
+system = System(cpu = cpu,
+                physmem = ruby_memory,
+                membus = CoherentBus())
+system.physmem.port = system.membus.master
+# create the interrupt controller
+cpu.createInterruptController()
+cpu.connectAllPorts(system.membus)
+
+# Connect the system port for loading of binaries etc
+system.system_port = system.membus.slave
+
+root = Root(full_system = False, system = system)

simulators/gem5/tests/configs/o3-timing.py

@@ -0,0 +1,59 @@
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Steve Reinhardt
+
+import m5
+from m5.objects import *
+m5.util.addToPath('../configs/common')
+
+class MyCache(BaseCache):
+    assoc = 2
+    block_size = 64
+    latency = '1ns'
+    mshrs = 10
+    tgts_per_mshr = 5
+
+class MyL1Cache(MyCache):
+    is_top_level = True
+    tgts_per_mshr = 20
+
+cpu = DerivO3CPU(cpu_id=0)
+cpu.addTwoLevelCacheHierarchy(MyL1Cache(size = '128kB'),
+                              MyL1Cache(size = '256kB'),
+                              MyCache(size = '2MB'))
+cpu.clock = '2GHz'
+
+system = System(cpu = cpu,
+                physmem = SimpleMemory(),
+                membus = CoherentBus())
+system.system_port = system.membus.slave
+system.physmem.port = system.membus.master
+# create the interrupt controller
+cpu.createInterruptController()
+cpu.connectAllPorts(system.membus)
+
+root = Root(full_system = False, system = system)

simulators/gem5/tests/configs/pc-o3-timing.py

@@ -0,0 +1,115 @@
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Steve Reinhardt
+
+import m5
+from m5.objects import *
+m5.util.addToPath('../configs/common')
+from Benchmarks import SysConfig
+import FSConfig
+
+mem_size = '128MB'
+
+# --------------------
+# Base L1 Cache
+# ====================
+
+class L1(BaseCache):
+    latency = '1ns'
+    block_size = 64
+    mshrs = 4
+    tgts_per_mshr = 20
+    is_top_level = True
+
+# ----------------------
+# Base L2 Cache
+# ----------------------
+
+class L2(BaseCache):
+    block_size = 64
+    latency = '10ns'
+    mshrs = 92
+    tgts_per_mshr = 16
+    write_buffers = 8
+
+# ---------------------
+# Page table walker cache
+# ---------------------
+class PageTableWalkerCache(BaseCache):
+    assoc = 2
+    block_size = 64
+    latency = '1ns'
+    mshrs = 10
+    size = '1kB'
+    tgts_per_mshr = 12
+
+# ---------------------
+# I/O Cache
+# ---------------------
+class IOCache(BaseCache):
+    assoc = 8
+    block_size = 64
+    latency = '50ns'
+    mshrs = 20
+    size = '1kB'
+    tgts_per_mshr = 12
+    addr_ranges = [AddrRange(0, size=mem_size)]
+    forward_snoops = False
+
+#cpu
+cpu = DerivO3CPU(cpu_id=0)
+#the system
+mdesc = SysConfig(disk = 'linux-x86.img')
+system = FSConfig.makeLinuxX86System('timing', mdesc=mdesc)
+system.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9')
+system.iocache = IOCache()
+system.iocache.cpu_side = system.iobus.master
+system.iocache.mem_side = system.membus.slave
+
+system.cpu = cpu
+#create the l1/l2 bus
+system.toL2Bus = CoherentBus()
+
+#connect up the l2 cache
+system.l2c = L2(size='4MB', assoc=8)
+system.l2c.cpu_side = system.toL2Bus.master
+system.l2c.mem_side = system.membus.slave
+
+#connect up the cpu and l1s
+cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
+                            L1(size = '32kB', assoc = 4),
+                            PageTableWalkerCache(),
+                            PageTableWalkerCache())
+# create the interrupt controller
+cpu.createInterruptController()
+# connect cpu level-1 caches to shared level-2 cache
+cpu.connectAllPorts(system.toL2Bus, system.membus)
+cpu.clock = '2GHz'
+
+root = Root(full_system=True, system=system)
+m5.ticks.setGlobalFrequency('1THz')
+

simulators/gem5/tests/configs/pc-simple-atomic.py

@@ -0,0 +1,117 @@
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Steve Reinhardt
+
+import m5
+from m5.objects import *
+m5.util.addToPath('../configs/common')
+from Benchmarks import SysConfig
+import FSConfig
+
+mem_size = '128MB'
+
+# --------------------
+# Base L1 Cache
+# ====================
+
+class L1(BaseCache):
+    latency = '1ns'
+    block_size = 64
+    mshrs = 4
+    tgts_per_mshr = 8
+    is_top_level = True
+
+# ----------------------
+# Base L2 Cache
+# ----------------------
+
+class L2(BaseCache):
+    block_size = 64
+    latency = '10ns'
+    mshrs = 92
+    tgts_per_mshr = 16
+    write_buffers = 8
+
+# ---------------------
+# Page table walker cache
+# ---------------------
+class PageTableWalkerCache(BaseCache):
+    assoc = 2
+    block_size = 64
+    latency = '1ns'
+    mshrs = 10
+    size = '1kB'
+    tgts_per_mshr = 12
+    is_top_level = True
+
+# ---------------------
+# I/O Cache
+# ---------------------
+class IOCache(BaseCache):
+    assoc = 8
+    block_size = 64
+    latency = '50ns'
+    mshrs = 20
+    size = '1kB'
+    tgts_per_mshr = 12
+    addr_ranges = [AddrRange(0, size=mem_size)]
+    forward_snoops = False
+    is_top_level = True
+
+#cpu
+cpu = AtomicSimpleCPU(cpu_id=0)
+#the system
+mdesc = SysConfig(disk = 'linux-x86.img')
+system = FSConfig.makeLinuxX86System('atomic', mdesc=mdesc)
+system.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9')
+system.iocache = IOCache()
+system.iocache.cpu_side = system.iobus.master
+system.iocache.mem_side = system.membus.slave
+
+system.cpu = cpu
+#create the l1/l2 bus
+system.toL2Bus = CoherentBus()
+
+#connect up the l2 cache
+system.l2c = L2(size='4MB', assoc=8)
+system.l2c.cpu_side = system.toL2Bus.master
+system.l2c.mem_side = system.membus.slave
+
+#connect up the cpu and l1s
+cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
+                            L1(size = '32kB', assoc = 4),
+                            PageTableWalkerCache(),
+                            PageTableWalkerCache())
+# create the interrupt controller
+cpu.createInterruptController()
+# connect cpu level-1 caches to shared level-2 cache
+cpu.connectAllPorts(system.toL2Bus, system.membus)
+cpu.clock = '2GHz'
+
+root = Root(full_system=True, system=system)
+m5.ticks.setGlobalFrequency('1THz')
+

simulators/gem5/tests/configs/pc-simple-timing-ruby.py

@@ -0,0 +1,77 @@
+# Copyright (c) 2012 Mark D. Hill and David A. Wood
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Nilay Vaish
+
+import m5, os, optparse, sys
+from m5.objects import *
+m5.util.addToPath('../configs/common')
+from Benchmarks import SysConfig
+import FSConfig
+
+m5.util.addToPath('../configs/ruby')
+import Ruby
+import Options
+
+# Add the ruby specific and protocol specific options
+parser = optparse.OptionParser()
+Options.addCommonOptions(parser)
+Ruby.define_options(parser)
+(options, args) = parser.parse_args()
+
+# Set the default cache size and associativity to be very small to encourage
+# races between requests and writebacks.
+options.l1d_size="32kB"
+options.l1i_size="32kB"
+options.l2_size="4MB"
+options.l1d_assoc=2
+options.l1i_assoc=2
+options.l2_assoc=2
+options.num_cpus = 2
+
+#the system
+mdesc = SysConfig(disk = 'linux-x86.img')
+system = FSConfig.makeLinuxX86System('timing', options.num_cpus,
+                                     mdesc=mdesc, Ruby=True)
+system.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9.smp')
+system.cpu = [TimingSimpleCPU(cpu_id=i) for i in xrange(options.num_cpus)]
+Ruby.create_system(options, system, system.piobus, system._dma_ports)
+
+for (i, cpu) in enumerate(system.cpu):
+    # create the interrupt controller
+    cpu.createInterruptController()
+    # Tie the cpu ports to the correct ruby system ports
+    cpu.icache_port = system.ruby._cpu_ruby_ports[i].slave
+    cpu.dcache_port = system.ruby._cpu_ruby_ports[i].slave
+    cpu.itb.walker.port = system.ruby._cpu_ruby_ports[i].slave
+    cpu.dtb.walker.port = system.ruby._cpu_ruby_ports[i].slave
+    cpu.interrupts.pio = system.piobus.master
+    cpu.interrupts.int_master = system.piobus.slave
+    cpu.interrupts.int_slave = system.piobus.master
+    cpu.clock = '2GHz'
+
+root = Root(full_system = True, system = system)
+m5.ticks.setGlobalFrequency('1THz')

simulators/gem5/tests/configs/pc-simple-timing.py

@@ -0,0 +1,117 @@
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Steve Reinhardt
+
+import m5
+from m5.objects import *
+m5.util.addToPath('../configs/common')
+from Benchmarks import SysConfig
+import FSConfig
+
+
+mem_size = '128MB'
+
+# --------------------
+# Base L1 Cache
+# ====================
+
+class L1(BaseCache):
+    latency = '1ns'
+    block_size = 64
+    mshrs = 4
+    tgts_per_mshr = 8
+    is_top_level = True
+
+# ----------------------
+# Base L2 Cache
+# ----------------------
+
+class L2(BaseCache):
+    block_size = 64
+    latency = '10ns'
+    mshrs = 92
+    tgts_per_mshr = 16
+    write_buffers = 8
+
+# ---------------------
+# Page table walker cache
+# ---------------------
+class PageTableWalkerCache(BaseCache):
+    assoc = 2
+    block_size = 64
+    latency = '1ns'
+    mshrs = 10
+    size = '1kB'
+    tgts_per_mshr = 12
+
+# ---------------------
+# I/O Cache
+# ---------------------
+class IOCache(BaseCache):
+    assoc = 8
+    block_size = 64
+    latency = '50ns'
+    mshrs = 20
+    size = '1kB'
+    tgts_per_mshr = 12
+    addr_ranges = [AddrRange(0, size=mem_size)]
+    forward_snoops = False
+
+#cpu
+cpu = TimingSimpleCPU(cpu_id=0)
+#the system
+mdesc = SysConfig(disk = 'linux-x86.img')
+system = FSConfig.makeLinuxX86System('timing', mdesc = mdesc)
+system.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9')
+
+system.cpu = cpu
+#create the l1/l2 bus
+system.toL2Bus = CoherentBus()
+system.iocache = IOCache()
+system.iocache.cpu_side = system.iobus.master
+system.iocache.mem_side = system.membus.slave
+
+
+#connect up the l2 cache
+system.l2c = L2(size='4MB', assoc=8)
+system.l2c.cpu_side = system.toL2Bus.master
+system.l2c.mem_side = system.membus.slave
+
+#connect up the cpu and l1s
+cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
+                            L1(size = '32kB', assoc = 4),
+                            PageTableWalkerCache(),
+                            PageTableWalkerCache())
+# create the interrupt controller
+cpu.createInterruptController()
+# connect cpu level-1 caches to shared level-2 cache
+cpu.connectAllPorts(system.toL2Bus, system.membus)
+cpu.clock = '2GHz'
+
+root = Root(full_system=True, system=system)
+m5.ticks.setGlobalFrequency('1THz')
+

simulators/gem5/tests/configs/realview-o3-checker.py

@@ -0,0 +1,109 @@
+# Copyright (c) 2011 ARM Limited
+# All rights reserved
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder.  You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Geoffrey Blake
+
+import m5
+from m5.objects import *
+m5.util.addToPath('../configs/common')
+import FSConfig
+
+
+# --------------------
+# Base L1 Cache
+# ====================
+
+class L1(BaseCache):
+    latency = '1ns'
+    block_size = 64
+    mshrs = 4
+    tgts_per_mshr = 20
+    is_top_level = True
+
+# ----------------------
+# Base L2 Cache
+# ----------------------
+
+class L2(BaseCache):
+    block_size = 64
+    latency = '10ns'
+    mshrs = 92
+    tgts_per_mshr = 16
+    write_buffers = 8
+
+# ---------------------
+# I/O Cache
+# ---------------------
+class IOCache(BaseCache):
+    assoc = 8
+    block_size = 64
+    latency = '50ns'
+    mshrs = 20
+    size = '1kB'
+    tgts_per_mshr = 12
+    addr_ranges = [AddrRange(0, size='256MB')]
+    forward_snoops = False
+
+#cpu
+cpu = DerivO3CPU(cpu_id=0)
+#the system
+system = FSConfig.makeArmSystem('timing', "RealView_PBX", None, False)
+
+system.cpu = cpu
+#create the l1/l2 bus
+system.toL2Bus = CoherentBus()
+system.iocache = IOCache()
+system.iocache.cpu_side = system.iobus.master
+system.iocache.mem_side = system.membus.slave
+
+
+#connect up the l2 cache
+system.l2c = L2(size='4MB', assoc=8)
+system.l2c.cpu_side = system.toL2Bus.master
+system.l2c.mem_side = system.membus.slave
+
+#connect up the checker
+cpu.addCheckerCpu()
+#connect up the cpu and l1s
+cpu.createInterruptController()
+cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
+                            L1(size = '32kB', assoc = 4))
+# connect cpu level-1 caches to shared level-2 cache
+cpu.connectAllPorts(system.toL2Bus, system.membus)
+cpu.clock = '2GHz'
+
+root = Root(full_system=True, system=system)
+m5.ticks.setGlobalFrequency('1THz')
+

simulators/gem5/tests/configs/realview-o3-dual.py

@@ -0,0 +1,100 @@
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Steve Reinhardt
+
+import m5
+from m5.objects import *
+m5.util.addToPath('../configs/common')
+import FSConfig
+from Benchmarks import *
+
+# --------------------
+# Base L1 Cache
+# ====================
+
+class L1(BaseCache):
+    latency = '1ns'
+    block_size = 64
+    mshrs = 4
+    tgts_per_mshr = 20
+    is_top_level = True
+
+# ----------------------
+# Base L2 Cache
+# ----------------------
+
+class L2(BaseCache):
+    block_size = 64
+    latency = '10ns'
+    mshrs = 92
+    tgts_per_mshr = 16
+    write_buffers = 8
+
+# ---------------------
+# I/O Cache
+# ---------------------
+class IOCache(BaseCache):
+    assoc = 8
+    block_size = 64
+    latency = '50ns'
+    mshrs = 20
+    size = '1kB'
+    tgts_per_mshr = 12
+    addr_ranges = [AddrRange(0, size='256MB')]
+    forward_snoops = False
+
+#cpu
+cpus = [DerivO3CPU(cpu_id=i) for i in xrange(2) ]
+#the system
+system = FSConfig.makeArmSystem('timing', "RealView_PBX", None, False)
+system.iocache = IOCache()
+system.iocache.cpu_side = system.iobus.master
+system.iocache.mem_side = system.membus.slave
+
+system.cpu = cpus
+#create the l1/l2 bus
+system.toL2Bus = CoherentBus()
+
+#connect up the l2 cache
+system.l2c = L2(size='4MB', assoc=8)
+system.l2c.cpu_side = system.toL2Bus.master
+system.l2c.mem_side = system.membus.slave
+
+#connect up the cpu and l1s
+for c in cpus:
+    c.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
+                                L1(size = '32kB', assoc = 4))
+    # create the interrupt controller
+    c.createInterruptController()
+    # connect cpu level-1 caches to shared level-2 cache
+    c.connectAllPorts(system.toL2Bus, system.membus)
+    c.clock = '2GHz'
+
+
+root = Root(full_system=True, system=system)
+m5.ticks.setGlobalFrequency('1THz')
+

simulators/gem5/tests/configs/realview-o3.py

@@ -0,0 +1,99 @@
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Steve Reinhardt
+
+import m5
+from m5.objects import *
+m5.util.addToPath('../configs/common')
+import FSConfig
+
+
+# --------------------
+# Base L1 Cache
+# ====================
+
+class L1(BaseCache):
+    latency = '1ns'
+    block_size = 64
+    mshrs = 4
+    tgts_per_mshr = 20
+    is_top_level = True
+
+# ----------------------
+# Base L2 Cache
+# ----------------------
+
+class L2(BaseCache):
+    block_size = 64
+    latency = '10ns'
+    mshrs = 92
+    tgts_per_mshr = 16
+    write_buffers = 8
+
+# ---------------------
+# I/O Cache
+# ---------------------
+class IOCache(BaseCache):
+    assoc = 8
+    block_size = 64
+    latency = '50ns'
+    mshrs = 20
+    size = '1kB'
+    tgts_per_mshr = 12
+    addr_ranges = [AddrRange(0, size='256MB')]
+    forward_snoops = False
+
+#cpu
+cpu = DerivO3CPU(cpu_id=0)
+#the system
+system = FSConfig.makeArmSystem('timing', "RealView_PBX", None, False)
+
+system.cpu = cpu
+#create the l1/l2 bus
+system.toL2Bus = CoherentBus()
+system.iocache = IOCache()
+system.iocache.cpu_side = system.iobus.master
+system.iocache.mem_side = system.membus.slave
+
+
+#connect up the l2 cache
+system.l2c = L2(size='4MB', assoc=8)
+system.l2c.cpu_side = system.toL2Bus.master
+system.l2c.mem_side = system.membus.slave
+
+#connect up the cpu and l1s
+cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
+                            L1(size = '32kB', assoc = 4))
+# create the interrupt controller
+cpu.createInterruptController()
+# connect cpu level-1 caches to shared level-2 cache
+cpu.connectAllPorts(system.toL2Bus, system.membus)
+cpu.clock = '2GHz'
+
+root = Root(full_system=True, system=system)
+m5.ticks.setGlobalFrequency('1THz')
+

simulators/gem5/tests/configs/realview-simple-atomic-dual.py

@@ -0,0 +1,100 @@
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Steve Reinhardt
+
+import m5
+from m5.objects import *
+m5.util.addToPath('../configs/common')
+import FSConfig
+from Benchmarks import *
+
+# --------------------
+# Base L1 Cache
+# ====================
+
+class L1(BaseCache):
+    latency = '1ns'
+    block_size = 64
+    mshrs = 4
+    tgts_per_mshr = 8
+    is_top_level = True
+
+# ----------------------
+# Base L2 Cache
+# ----------------------
+
+class L2(BaseCache):
+    block_size = 64
+    latency = '10ns'
+    mshrs = 92
+    tgts_per_mshr = 16
+    write_buffers = 8
+
+# ---------------------
+# I/O Cache
+# ---------------------
+class IOCache(BaseCache):
+    assoc = 8
+    block_size = 64
+    latency = '50ns'
+    mshrs = 20
+    size = '1kB'
+    tgts_per_mshr = 12
+    addr_ranges = [AddrRange(0, size='256MB')]
+    forward_snoops = False
+
+#cpu
+cpus = [AtomicSimpleCPU(cpu_id=i) for i in xrange(2) ]
+#the system
+system = FSConfig.makeArmSystem('atomic', "RealView_PBX", None, False)
+system.iocache = IOCache()
+system.iocache.cpu_side = system.iobus.master
+system.iocache.mem_side = system.membus.slave
+
+system.cpu = cpus
+#create the l1/l2 bus
+system.toL2Bus = CoherentBus()
+
+#connect up the l2 cache
+system.l2c = L2(size='4MB', assoc=8)
+system.l2c.cpu_side = system.toL2Bus.master
+system.l2c.mem_side = system.membus.slave
+
+#connect up the cpu and l1s
+for c in cpus:
+    c.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
+                                L1(size = '32kB', assoc = 4))
+    # create the interrupt controller
+    c.createInterruptController()
+    # connect cpu level-1 caches to shared level-2 cache
+    c.connectAllPorts(system.toL2Bus, system.membus)
+    c.clock = '2GHz'
+
+
+root = Root(full_system=True, system=system)
+m5.ticks.setGlobalFrequency('1THz')
+

simulators/gem5/tests/configs/realview-simple-atomic.py

@@ -0,0 +1,97 @@
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Steve Reinhardt
+
+import m5
+from m5.objects import *
+m5.util.addToPath('../configs/common')
+import FSConfig
+
+# --------------------
+# Base L1 Cache
+# ====================
+
+class L1(BaseCache):
+    latency = '1ns'
+    block_size = 64
+    mshrs = 4
+    tgts_per_mshr = 8
+    is_top_level = True
+
+# ----------------------
+# Base L2 Cache
+# ----------------------
+
+class L2(BaseCache):
+    block_size = 64
+    latency = '10ns'
+    mshrs = 92
+    tgts_per_mshr = 16
+    write_buffers = 8
+
+# ---------------------
+# I/O Cache
+# ---------------------
+class IOCache(BaseCache):
+    assoc = 8
+    block_size = 64
+    latency = '50ns'
+    mshrs = 20
+    size = '1kB'
+    tgts_per_mshr = 12
+    addr_ranges = [AddrRange(0, size='256MB')]
+    forward_snoops = False
+
+#cpu
+cpu = AtomicSimpleCPU(cpu_id=0)
+#the system
+system = FSConfig.makeArmSystem('atomic', "RealView_PBX", None, False)
+system.iocache = IOCache()
+system.iocache.cpu_side = system.iobus.master
+system.iocache.mem_side = system.membus.slave
+
+system.cpu = cpu
+#create the l1/l2 bus
+system.toL2Bus = CoherentBus()
+
+#connect up the l2 cache
+system.l2c = L2(size='4MB', assoc=8)
+system.l2c.cpu_side = system.toL2Bus.master
+system.l2c.mem_side = system.membus.slave
+
+#connect up the cpu and l1s
+cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
+                            L1(size = '32kB', assoc = 4))
+# create the interrupt controller
+cpu.createInterruptController()
+# connect cpu level-1 caches to shared level-2 cache
+cpu.connectAllPorts(system.toL2Bus, system.membus)
+cpu.clock = '2GHz'
+
+root = Root(full_system=True, system=system)
+m5.ticks.setGlobalFrequency('1THz')
+

simulators/gem5/tests/configs/realview-simple-timing-dual.py

@@ -0,0 +1,100 @@
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Steve Reinhardt
+
+import m5
+from m5.objects import *
+m5.util.addToPath('../configs/common')
+import FSConfig
+from Benchmarks import *
+
+# --------------------
+# Base L1 Cache
+# ====================
+
+class L1(BaseCache):
+    latency = '1ns'
+    block_size = 64
+    mshrs = 4
+    tgts_per_mshr = 8
+    is_top_level = True
+
+# ----------------------
+# Base L2 Cache
+# ----------------------
+
+class L2(BaseCache):
+    block_size = 64
+    latency = '10ns'
+    mshrs = 92
+    tgts_per_mshr = 16
+    write_buffers = 8
+
+# ---------------------
+# I/O Cache
+# ---------------------
+class IOCache(BaseCache):
+    assoc = 8
+    block_size = 64
+    latency = '50ns'
+    mshrs = 20
+    size = '1kB'
+    tgts_per_mshr = 12
+    addr_ranges = [AddrRange(0, size='256MB')]
+    forward_snoops = False
+
+#cpu
+cpus = [TimingSimpleCPU(cpu_id=i) for i in xrange(2) ]
+#the system
+system = FSConfig.makeArmSystem('timing', "RealView_PBX", None, False)
+system.iocache = IOCache()
+system.iocache.cpu_side = system.iobus.master
+system.iocache.mem_side = system.membus.slave
+
+system.cpu = cpus
+#create the l1/l2 bus
+system.toL2Bus = CoherentBus()
+
+#connect up the l2 cache
+system.l2c = L2(size='4MB', assoc=8)
+system.l2c.cpu_side = system.toL2Bus.master
+system.l2c.mem_side = system.membus.slave
+
+#connect up the cpu and l1s
+for c in cpus:
+    c.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
+                                L1(size = '32kB', assoc = 4))
+    # create the interrupt controller
+    c.createInterruptController()
+    # connect cpu level-1 caches to shared level-2 cache
+    c.connectAllPorts(system.toL2Bus, system.membus)
+    c.clock = '2GHz'
+
+
+root = Root(full_system=True, system=system)
+m5.ticks.setGlobalFrequency('1THz')
+

simulators/gem5/tests/configs/realview-simple-timing.py

@@ -0,0 +1,99 @@
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Steve Reinhardt
+
+import m5
+from m5.objects import *
+m5.util.addToPath('../configs/common')
+import FSConfig
+
+
+# --------------------
+# Base L1 Cache
+# ====================
+
+class L1(BaseCache):
+    latency = '1ns'
+    block_size = 64
+    mshrs = 4
+    tgts_per_mshr = 8
+    is_top_level = True
+
+# ----------------------
+# Base L2 Cache
+# ----------------------
+
+class L2(BaseCache):
+    block_size = 64
+    latency = '10ns'
+    mshrs = 92
+    tgts_per_mshr = 16
+    write_buffers = 8
+
+# ---------------------
+# I/O Cache
+# ---------------------
+class IOCache(BaseCache):
+    assoc = 8
+    block_size = 64
+    latency = '50ns'
+    mshrs = 20
+    size = '1kB'
+    tgts_per_mshr = 12
+    addr_ranges = [AddrRange(0, size='256MB')]
+    forward_snoops = False
+
+#cpu
+cpu = TimingSimpleCPU(cpu_id=0)
+#the system
+system = FSConfig.makeArmSystem('timing', "RealView_PBX", None, False)
+
+system.cpu = cpu
+#create the l1/l2 bus
+system.toL2Bus = CoherentBus()
+system.iocache = IOCache()
+system.iocache.cpu_side = system.iobus.master
+system.iocache.mem_side = system.membus.slave
+
+
+#connect up the l2 cache
+system.l2c = L2(size='4MB', assoc=8)
+system.l2c.cpu_side = system.toL2Bus.master
+system.l2c.mem_side = system.membus.slave
+
+#connect up the cpu and l1s
+cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
+                            L1(size = '32kB', assoc = 4))
+# create the interrupt controller
+cpu.createInterruptController()
+# connect cpu level-1 caches to shared level-2 cache
+cpu.connectAllPorts(system.toL2Bus, system.membus)
+cpu.clock = '2GHz'
+
+root = Root(full_system=True, system=system)
+m5.ticks.setGlobalFrequency('1THz')
+

simulators/gem5/tests/configs/rubytest-ruby.py

@@ -0,0 +1,120 @@
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
+# Copyright (c) 2009 Advanced Micro Devices, Inc.
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Ron Dreslinski
+#          Brad Beckmann
+
+import m5
+from m5.objects import *
+from m5.defines import buildEnv
+from m5.util import addToPath
+import os, optparse, sys
+
+# Get paths we might need.  It's expected this file is in m5/configs/example.
+config_path = os.path.dirname(os.path.abspath(__file__))
+config_root = os.path.dirname(config_path)
+m5_root = os.path.dirname(config_root)
+addToPath(config_root+'/configs/common')
+addToPath(config_root+'/configs/ruby')
+
+import Ruby
+import Options
+
+parser = optparse.OptionParser()
+Options.addCommonOptions(parser)
+
+# Add the ruby specific and protocol specific options
+Ruby.define_options(parser)
+
+(options, args) = parser.parse_args()
+
+#
+# Set the default cache size and associativity to be very small to encourage
+# races between requests and writebacks.
+#
+options.l1d_size="256B"
+options.l1i_size="256B"
+options.l2_size="512B"
+options.l3_size="1kB"
+options.l1d_assoc=2
+options.l1i_assoc=2
+options.l2_assoc=2
+options.l3_assoc=2
+
+# Turn on flush check for the hammer protocol
+check_flush = False
+if buildEnv['PROTOCOL'] == 'MOESI_hammer':
+    check_flush = True
+
+#
+# create the tester and system, including ruby
+#
+tester = RubyTester(check_flush = check_flush, checks_to_complete = 100,
+                    wakeup_frequency = 10, num_cpus = options.num_cpus)
+
+system = System(tester = tester, physmem = SimpleMemory())
+
+Ruby.create_system(options, system)
+
+assert(options.num_cpus == len(system.ruby._cpu_ruby_ports))
+
+#
+# The tester is most effective when randomization is turned on and
+# artifical delay is randomly inserted on messages
+#
+system.ruby.randomization = True
+
+for ruby_port in system.ruby._cpu_ruby_ports:
+    #
+    # Tie the ruby tester ports to the ruby cpu read and write ports
+    #
+    if ruby_port.support_data_reqs:
+         tester.cpuDataPort = ruby_port.slave
+    if ruby_port.support_inst_reqs:
+         tester.cpuInstPort = ruby_port.slave
+
+    #
+    # Tell the sequencer this is the ruby tester so that it
+    # copies the subblock back to the checker
+    #
+    ruby_port.using_ruby_tester = True
+
+    #
+    # Ruby doesn't need the backing image of memory when running with
+    # the tester.
+    #
+    ruby_port.access_phys_mem = False
+
+# -----------------------
+# run simulation
+# -----------------------
+
+root = Root(full_system = False, system = system )
+root.system.mem_mode = 'timing'
+
+# Not much point in this being higher than the L1 latency
+m5.ticks.setGlobalFrequency('1ns')

simulators/gem5/tests/configs/simple-atomic-dummychecker.py

@@ -0,0 +1,51 @@
+# Copyright (c) 2011 ARM Limited
+# All rights reserved
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder.  You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Geoffrey Blake
+
+import m5
+from m5.objects import *
+
+system = System(cpu = AtomicSimpleCPU(cpu_id=0),
+                physmem = SimpleMemory(),
+                membus = CoherentBus())
+system.system_port = system.membus.slave
+system.physmem.port = system.membus.master
+system.cpu.addCheckerCpu()
+system.cpu.createInterruptController()
+system.cpu.connectAllPorts(system.membus)
+system.cpu.clock = '2GHz'
+
+root = Root(full_system = False, system = system)

simulators/gem5/tests/configs/simple-atomic-mp-ruby.py

@@ -0,0 +1,58 @@
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Ron Dreslinski
+
+import m5
+from m5.objects import *
+
+
+nb_cores = 4
+cpus = [ AtomicSimpleCPU(cpu_id=i) for i in xrange(nb_cores) ]
+
+import ruby_config
+ruby_memory = ruby_config.generate("TwoLevel_SplitL1UnifiedL2.rb", nb_cores)
+
+# system simulated
+system = System(cpu = cpus, physmem = ruby_memory, membus = CoherentBus())
+
+# add L1 caches
+for cpu in cpus:
+    cpu.connectAllPorts(system.membus)
+    cpu.clock = '2GHz'
+
+# connect memory to membus
+system.physmem.port = system.membus.master
+
+# Connect the system port for loading of binaries etc
+system.system_port = system.membus.slave
+
+# -----------------------
+# run simulation
+# -----------------------
+
+root = Root(full_system = False, system = system)
+root.system.mem_mode = 'atomic'

simulators/gem5/tests/configs/simple-atomic-mp.py

@@ -0,0 +1,91 @@
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Ron Dreslinski
+
+import m5
+from m5.objects import *
+
+# --------------------
+# Base L1 Cache
+# ====================
+
+class L1(BaseCache):
+    latency = '1ns'
+    block_size = 64
+    mshrs = 4
+    tgts_per_mshr = 8
+    is_top_level = True
+
+# ----------------------
+# Base L2 Cache
+# ----------------------
+
+class L2(BaseCache):
+    block_size = 64
+    latency = '10ns'
+    mshrs = 92
+    tgts_per_mshr = 16
+    write_buffers = 8
+
+nb_cores = 4
+cpus = [ AtomicSimpleCPU(cpu_id=i) for i in xrange(nb_cores) ]
+
+# system simulated
+system = System(cpu = cpus,
+                physmem = SimpleMemory(range = AddrRange('1024MB')),
+                membus = CoherentBus())
+
+# l2cache & bus
+system.toL2Bus = CoherentBus()
+system.l2c = L2(size='4MB', assoc=8)
+system.l2c.cpu_side = system.toL2Bus.master
+
+# connect l2c to membus
+system.l2c.mem_side = system.membus.slave
+
+# add L1 caches
+for cpu in cpus:
+    cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
+                                L1(size = '32kB', assoc = 4))
+    # create the interrupt controller
+    cpu.createInterruptController()
+    # connect cpu level-1 caches to shared level-2 cache
+    cpu.connectAllPorts(system.toL2Bus, system.membus)
+    cpu.clock = '2GHz'
+
+# connect memory to membus
+system.physmem.port = system.membus.master
+
+# connect system port to membus
+system.system_port = system.membus.slave
+
+# -----------------------
+# run simulation
+# -----------------------
+
+root = Root( full_system = False, system = system )
+root.system.mem_mode = 'atomic'

simulators/gem5/tests/configs/simple-atomic.py

@@ -0,0 +1,42 @@
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Steve Reinhardt
+
+import m5
+from m5.objects import *
+
+system = System(cpu = AtomicSimpleCPU(cpu_id=0),
+                physmem = SimpleMemory(),
+                membus = CoherentBus())
+system.system_port = system.membus.slave
+system.physmem.port = system.membus.master
+# create the interrupt controller
+system.cpu.createInterruptController()
+system.cpu.connectAllPorts(system.membus)
+system.cpu.clock = '2GHz'
+
+root = Root(full_system = False, system = system)

simulators/gem5/tests/configs/simple-timing-mp-ruby.py

@@ -0,0 +1,96 @@
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Ron Dreslinski
+
+import m5
+from m5.objects import *
+from m5.defines import buildEnv
+from m5.util import addToPath
+import os, optparse, sys
+
+# Get paths we might need
+config_path = os.path.dirname(os.path.abspath(__file__))
+config_root = os.path.dirname(config_path)
+m5_root = os.path.dirname(config_root)
+addToPath(config_root+'/configs/common')
+addToPath(config_root+'/configs/ruby')
+
+import Options
+import Ruby
+
+parser = optparse.OptionParser()
+Options.addCommonOptions(parser)
+
+# Add the ruby specific and protocol specific options
+Ruby.define_options(parser)
+
+(options, args) = parser.parse_args()
+
+#
+# Set the default cache size and associativity to be very small to encourage
+# races between requests and writebacks.
+#
+options.l1d_size="256B"
+options.l1i_size="256B"
+options.l2_size="512B"
+options.l3_size="1kB"
+options.l1d_assoc=2
+options.l1i_assoc=2
+options.l2_assoc=2
+options.l3_assoc=2
+
+nb_cores = 4
+cpus = [ TimingSimpleCPU(cpu_id=i) for i in xrange(nb_cores) ]
+
+# overwrite the num_cpus to equal nb_cores
+options.num_cpus = nb_cores
+
+# system simulated
+system = System(cpu = cpus, physmem = SimpleMemory())
+
+Ruby.create_system(options, system)
+
+assert(options.num_cpus == len(system.ruby._cpu_ruby_ports))
+
+for (i, cpu) in enumerate(system.cpu):
+    # create the interrupt controller
+    cpu.createInterruptController()
+
+    #
+    # Tie the cpu ports to the ruby cpu ports
+    #
+    cpu.connectAllPorts(system.ruby._cpu_ruby_ports[i])
+
+# -----------------------
+# run simulation
+# -----------------------
+
+root = Root( full_system=False, system = system )
+root.system.mem_mode = 'timing'
+
+# Not much point in this being higher than the L1 latency
+m5.ticks.setGlobalFrequency('1ns')

simulators/gem5/tests/configs/simple-timing-mp.py

@@ -0,0 +1,89 @@
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Ron Dreslinski
+
+import m5
+from m5.objects import *
+
+# --------------------
+# Base L1 Cache
+# ====================
+
+class L1(BaseCache):
+    latency = '1ns'
+    block_size = 64
+    mshrs = 4
+    tgts_per_mshr = 8
+    is_top_level = True
+
+# ----------------------
+# Base L2 Cache
+# ----------------------
+
+class L2(BaseCache):
+    block_size = 64
+    latency = '10ns'
+    mshrs = 92
+    tgts_per_mshr = 16
+    write_buffers = 8
+
+nb_cores = 4
+cpus = [ TimingSimpleCPU(cpu_id=i) for i in xrange(nb_cores) ]
+
+# system simulated
+system = System(cpu = cpus, physmem = SimpleMemory(), membus = CoherentBus())
+
+# l2cache & bus
+system.toL2Bus = CoherentBus()
+system.l2c = L2(size='4MB', assoc=8)
+system.l2c.cpu_side = system.toL2Bus.master
+
+# connect l2c to membus
+system.l2c.mem_side = system.membus.slave
+
+# add L1 caches
+for cpu in cpus:
+    cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
+                                L1(size = '32kB', assoc = 4))
+    # create the interrupt controller
+    cpu.createInterruptController()
+    # connect cpu level-1 caches to shared level-2 cache
+    cpu.connectAllPorts(system.toL2Bus, system.membus)
+    cpu.clock = '2GHz'
+
+system.system_port = system.membus.slave
+
+# connect memory to membus
+system.physmem.port = system.membus.master
+
+
+# -----------------------
+# run simulation
+# -----------------------
+
+root = Root( full_system = False, system = system )
+root.system.mem_mode = 'timing'

simulators/gem5/tests/configs/simple-timing-ruby.py

@@ -0,0 +1,92 @@
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Steve Reinhardt
+
+import m5
+from m5.objects import *
+from m5.defines import buildEnv
+from m5.util import addToPath
+import os, optparse, sys
+
+# Get paths we might need
+config_path = os.path.dirname(os.path.abspath(__file__))
+config_root = os.path.dirname(config_path)
+addToPath(config_root+'/configs/common')
+addToPath(config_root+'/configs/ruby')
+
+import Ruby
+import Options
+
+parser = optparse.OptionParser()
+Options.addCommonOptions(parser)
+
+# Add the ruby specific and protocol specific options
+Ruby.define_options(parser)
+
+(options, args) = parser.parse_args()
+
+#
+# Set the default cache size and associativity to be very small to encourage
+# races between requests and writebacks.
+#
+options.l1d_size="256B"
+options.l1i_size="256B"
+options.l2_size="512B"
+options.l3_size="1kB"
+options.l1d_assoc=2
+options.l1i_assoc=2
+options.l2_assoc=2
+options.l3_assoc=2
+
+# this is a uniprocessor only test
+options.num_cpus = 1
+
+cpu = TimingSimpleCPU(cpu_id=0)
+system = System(cpu = cpu, physmem = SimpleMemory())
+
+Ruby.create_system(options, system)
+
+assert(len(system.ruby._cpu_ruby_ports) == 1)
+
+# create the interrupt controller
+cpu.createInterruptController()
+
+#
+# Tie the cpu cache ports to the ruby cpu ports and
+# physmem, respectively
+#
+cpu.connectAllPorts(system.ruby._cpu_ruby_ports[0])
+
+# -----------------------
+# run simulation
+# -----------------------
+
+root = Root(full_system = False, system = system)
+root.system.mem_mode = 'timing'
+
+# Not much point in this being higher than the L1 latency
+m5.ticks.setGlobalFrequency('1ns')

simulators/gem5/tests/configs/simple-timing.py

@@ -0,0 +1,56 @@
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Steve Reinhardt
+
+import m5
+from m5.objects import *
+
+class MyCache(BaseCache):
+    assoc = 2
+    block_size = 64
+    latency = '1ns'
+    mshrs = 10
+    tgts_per_mshr = 5
+
+class MyL1Cache(MyCache):
+    is_top_level = True
+
+cpu = TimingSimpleCPU(cpu_id=0)
+cpu.addTwoLevelCacheHierarchy(MyL1Cache(size = '128kB'),
+                              MyL1Cache(size = '256kB'),
+                              MyCache(size = '2MB', latency='10ns'))
+system = System(cpu = cpu,
+                physmem = SimpleMemory(),
+                membus = CoherentBus())
+system.system_port = system.membus.slave
+system.physmem.port = system.membus.master
+# create the interrupt controller
+cpu.createInterruptController()
+cpu.connectAllPorts(system.membus)
+cpu.clock = '2GHz'
+
+root = Root(full_system=False, system = system)

simulators/gem5/tests/configs/t1000-simple-atomic.py

@@ -0,0 +1,43 @@
+# Copyright (c) 2007 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Ali Saidi
+
+import m5
+from m5.objects import *
+m5.util.addToPath('../configs/common')
+import FSConfig
+
+cpu = AtomicSimpleCPU(cpu_id=0)
+system = FSConfig.makeSparcSystem('atomic')
+system.cpu = cpu
+# create the interrupt controller
+cpu.createInterruptController()
+cpu.connectAllPorts(system.membus)
+
+root = Root(full_system=True, system=system)
+
+m5.ticks.setGlobalFrequency('2GHz')

simulators/gem5/tests/configs/tsunami-inorder.py

@@ -0,0 +1,101 @@
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Steve Reinhardt
+
+import m5
+from m5.objects import *
+m5.util.addToPath('../configs/common')
+import FSConfig
+
+
+# --------------------
+# Base L1 Cache
+# ====================
+
+class L1(BaseCache):
+    latency = '1ns'
+    block_size = 64
+    mshrs = 4
+    tgts_per_mshr = 8
+    is_top_level = True
+
+# ----------------------
+# Base L2 Cache
+# ----------------------
+
+class L2(BaseCache):
+    block_size = 64
+    latency = '10ns'
+    mshrs = 92
+    tgts_per_mshr = 16
+    write_buffers = 8
+
+# ---------------------
+# I/O Cache
+# ---------------------
+class IOCache(BaseCache):
+    assoc = 8
+    block_size = 64
+    latency = '50ns'
+    mshrs = 20
+    size = '1kB'
+    tgts_per_mshr = 12
+    addr_ranges = [AddrRange(0, size='8GB')]
+    forward_snoops = False
+    is_top_level = True
+
+#cpu
+cpu = InOrderCPU(cpu_id=0)
+cpu.stageWidth = 4
+cpu.fetchBuffSize = 1
+
+#the system
+system = FSConfig.makeLinuxAlphaSystem('timing')
+
+system.cpu = cpu
+#create the l1/l2 bus
+system.toL2Bus = CoherentBus()
+system.iocache = IOCache()
+system.iocache.cpu_side = system.iobus.master
+system.iocache.mem_side = system.membus.slave
+
+
+#connect up the l2 cache
+system.l2c = L2(size='4MB', assoc=8)
+system.l2c.cpu_side = system.toL2Bus.master
+system.l2c.mem_side = system.membus.slave
+
+#connect up the cpu and l1s
+cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
+                            L1(size = '32kB', assoc = 4))
+# connect cpu level-1 caches to shared level-2 cache
+cpu.connectAllPorts(system.toL2Bus, system.membus)
+cpu.clock = '2GHz'
+
+root = Root(full_system=True, system=system)
+m5.ticks.setGlobalFrequency('1THz')
+

simulators/gem5/tests/configs/tsunami-o3-dual.py

@@ -0,0 +1,101 @@
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Steve Reinhardt
+
+import m5
+from m5.objects import *
+m5.util.addToPath('../configs/common')
+import FSConfig
+
+
+# --------------------
+# Base L1 Cache
+# ====================
+
+class L1(BaseCache):
+    latency = '1ns'
+    block_size = 64
+    mshrs = 4
+    tgts_per_mshr = 20
+    is_top_level = True
+
+# ----------------------
+# Base L2 Cache
+# ----------------------
+
+class L2(BaseCache):
+    block_size = 64
+    latency = '10ns'
+    mshrs = 92
+    tgts_per_mshr = 16
+    write_buffers = 8
+
+# ---------------------
+# I/O Cache
+# ---------------------
+class IOCache(BaseCache):
+    assoc = 8
+    block_size = 64
+    latency = '50ns'
+    mshrs = 20
+    size = '1kB'
+    tgts_per_mshr = 12
+    addr_ranges = [AddrRange(0, size='8GB')]
+    forward_snoops = False
+    is_top_level = True
+
+#cpu
+cpus = [ DerivO3CPU(cpu_id=i) for i in xrange(2) ]
+#the system
+system = FSConfig.makeLinuxAlphaSystem('timing')
+
+system.cpu = cpus
+#create the l1/l2 bus
+system.toL2Bus = CoherentBus()
+system.iocache = IOCache()
+system.iocache.cpu_side = system.iobus.master
+system.iocache.mem_side = system.membus.slave
+
+
+#connect up the l2 cache
+system.l2c = L2(size='4MB', assoc=8)
+system.l2c.cpu_side = system.toL2Bus.master
+system.l2c.mem_side = system.membus.slave
+
+#connect up the cpu and l1s
+for c in cpus:
+    c.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
+                                L1(size = '32kB', assoc = 4))
+    # create the interrupt controller
+    c.createInterruptController()
+    # connect cpu level-1 caches to shared level-2 cache
+    c.connectAllPorts(system.toL2Bus, system.membus)
+    c.clock = '2GHz'
+
+root = Root(full_system=True, system=system)
+m5.ticks.setGlobalFrequency('1THz')
+

simulators/gem5/tests/configs/tsunami-o3.py

@@ -0,0 +1,100 @@
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Steve Reinhardt
+
+import m5
+from m5.objects import *
+m5.util.addToPath('../configs/common')
+import FSConfig
+
+
+# --------------------
+# Base L1 Cache
+# ====================
+
+class L1(BaseCache):
+    latency = '1ns'
+    block_size = 64
+    mshrs = 4
+    tgts_per_mshr = 20
+    is_top_level = True
+
+# ----------------------
+# Base L2 Cache
+# ----------------------
+
+class L2(BaseCache):
+    block_size = 64
+    latency = '10ns'
+    mshrs = 92
+    tgts_per_mshr = 16
+    write_buffers = 8
+
+# ---------------------
+# I/O Cache
+# ---------------------
+class IOCache(BaseCache):
+    assoc = 8
+    block_size = 64
+    latency = '50ns'
+    mshrs = 20
+    size = '1kB'
+    tgts_per_mshr = 12
+    addr_ranges = [AddrRange(0, size='8GB')]
+    forward_snoops = False
+    is_top_level = True
+
+#cpu
+cpu = DerivO3CPU(cpu_id=0)
+#the system
+system = FSConfig.makeLinuxAlphaSystem('timing')
+
+system.cpu = cpu
+#create the l1/l2 bus
+system.toL2Bus = CoherentBus()
+system.iocache = IOCache()
+system.iocache.cpu_side = system.iobus.master
+system.iocache.mem_side = system.membus.slave
+
+
+#connect up the l2 cache
+system.l2c = L2(size='4MB', assoc=8)
+system.l2c.cpu_side = system.toL2Bus.master
+system.l2c.mem_side = system.membus.slave
+
+#connect up the cpu and l1s
+cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
+                            L1(size = '32kB', assoc = 4))
+# create the interrupt controller
+cpu.createInterruptController()
+# connect cpu level-1 caches to shared level-2 cache
+cpu.connectAllPorts(system.toL2Bus, system.membus)
+cpu.clock = '2GHz'
+
+root = Root(full_system=True, system=system)
+m5.ticks.setGlobalFrequency('1THz')
+

simulators/gem5/tests/configs/tsunami-simple-atomic-dual.py

@@ -0,0 +1,98 @@
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Steve Reinhardt
+
+import m5
+from m5.objects import *
+m5.util.addToPath('../configs/common')
+import FSConfig
+
+# --------------------
+# Base L1 Cache
+# ====================
+
+class L1(BaseCache):
+    latency = '1ns'
+    block_size = 64
+    mshrs = 4
+    tgts_per_mshr = 8
+    is_top_level = True
+
+# ----------------------
+# Base L2 Cache
+# ----------------------
+
+class L2(BaseCache):
+    block_size = 64
+    latency = '10ns'
+    mshrs = 92
+    tgts_per_mshr = 16
+    write_buffers = 8
+
+# ---------------------
+# I/O Cache
+# ---------------------
+class IOCache(BaseCache):
+    assoc = 8
+    block_size = 64
+    latency = '50ns'
+    mshrs = 20
+    size = '1kB'
+    tgts_per_mshr = 12
+    addr_ranges = [AddrRange(0, size='8GB')]
+    forward_snoops = False
+    is_top_level = True
+
+#cpu
+cpus = [ AtomicSimpleCPU(cpu_id=i) for i in xrange(2) ]
+#the system
+system = FSConfig.makeLinuxAlphaSystem('atomic')
+system.iocache = IOCache()
+system.iocache.cpu_side = system.iobus.master
+system.iocache.mem_side = system.membus.slave
+
+system.cpu = cpus
+#create the l1/l2 bus
+system.toL2Bus = CoherentBus()
+
+#connect up the l2 cache
+system.l2c = L2(size='4MB', assoc=8)
+system.l2c.cpu_side = system.toL2Bus.master
+system.l2c.mem_side = system.membus.slave
+
+#connect up the cpu and l1s
+for c in cpus:
+    c.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
+                                L1(size = '32kB', assoc = 4))
+    # create the interrupt controller
+    c.createInterruptController()
+    # connect cpu level-1 caches to shared level-2 cache
+    c.connectAllPorts(system.toL2Bus, system.membus)
+    c.clock = '2GHz'
+
+root = Root(full_system=True, system=system)
+m5.ticks.setGlobalFrequency('1THz')

simulators/gem5/tests/configs/tsunami-simple-atomic.py

@@ -0,0 +1,98 @@
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Steve Reinhardt
+
+import m5
+from m5.objects import *
+m5.util.addToPath('../configs/common')
+import FSConfig
+
+# --------------------
+# Base L1 Cache
+# ====================
+
+class L1(BaseCache):
+    latency = '1ns'
+    block_size = 64
+    mshrs = 4
+    tgts_per_mshr = 8
+    is_top_level = True
+
+# ----------------------
+# Base L2 Cache
+# ----------------------
+
+class L2(BaseCache):
+    block_size = 64
+    latency = '10ns'
+    mshrs = 92
+    tgts_per_mshr = 16
+    write_buffers = 8
+
+# ---------------------
+# I/O Cache
+# ---------------------
+class IOCache(BaseCache):
+    assoc = 8
+    block_size = 64
+    latency = '50ns'
+    mshrs = 20
+    size = '1kB'
+    tgts_per_mshr = 12
+    addr_ranges = [AddrRange(0, size='8GB')]
+    forward_snoops = False
+    is_top_level = True
+
+#cpu
+cpu = AtomicSimpleCPU(cpu_id=0)
+#the system
+system = FSConfig.makeLinuxAlphaSystem('atomic')
+system.iocache = IOCache()
+system.iocache.cpu_side = system.iobus.master
+system.iocache.mem_side = system.membus.slave
+
+system.cpu = cpu
+#create the l1/l2 bus
+system.toL2Bus = CoherentBus()
+
+#connect up the l2 cache
+system.l2c = L2(size='4MB', assoc=8)
+system.l2c.cpu_side = system.toL2Bus.master
+system.l2c.mem_side = system.membus.slave
+
+#connect up the cpu and l1s
+cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
+                            L1(size = '32kB', assoc = 4))
+# create the interrupt controller
+cpu.createInterruptController()
+# connect cpu level-1 caches to shared level-2 cache
+cpu.connectAllPorts(system.toL2Bus, system.membus)
+cpu.clock = '2GHz'
+
+root = Root(full_system=True, system=system)
+m5.ticks.setGlobalFrequency('1THz')
+

simulators/gem5/tests/configs/tsunami-simple-timing-dual.py

@@ -0,0 +1,100 @@
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Steve Reinhardt
+
+import m5
+from m5.objects import *
+m5.util.addToPath('../configs/common')
+import FSConfig
+
+# --------------------
+# Base L1 Cache
+# ====================
+
+class L1(BaseCache):
+    latency = '1ns'
+    block_size = 64
+    mshrs = 4
+    tgts_per_mshr = 8
+    is_top_level = True
+
+# ----------------------
+# Base L2 Cache
+# ----------------------
+
+class L2(BaseCache):
+    block_size = 64
+    latency = '10ns'
+    mshrs = 92
+    tgts_per_mshr = 16
+    write_buffers = 8
+
+# ---------------------
+# I/O Cache
+# ---------------------
+class IOCache(BaseCache):
+    assoc = 8
+    block_size = 64
+    latency = '50ns'
+    mshrs = 20
+    size = '1kB'
+    tgts_per_mshr = 12
+    addr_ranges = [AddrRange(0, size='8GB')]
+    forward_snoops = False
+    is_top_level = True
+
+#cpu
+cpus = [ TimingSimpleCPU(cpu_id=i) for i in xrange(2) ]
+#the system
+system = FSConfig.makeLinuxAlphaSystem('timing')
+system.iocache = IOCache()
+system.iocache.cpu_side = system.iobus.master
+system.iocache.mem_side = system.membus.slave
+
+system.cpu = cpus
+#create the l1/l2 bus
+system.toL2Bus = CoherentBus()
+
+#connect up the l2 cache
+system.l2c = L2(size='4MB', assoc=8)
+system.l2c.cpu_side = system.toL2Bus.master
+system.l2c.mem_side = system.membus.slave
+
+#connect up the cpu and l1s
+for c in cpus:
+    c.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
+                                L1(size = '32kB', assoc = 4))
+    # create the interrupt controller
+    c.createInterruptController()
+    # connect cpu level-1 caches to shared level-2 cache
+    c.connectAllPorts(system.toL2Bus, system.membus)
+    c.clock = '2GHz'
+
+root = Root(full_system=True, system=system)
+m5.ticks.setGlobalFrequency('1THz')
+
+

simulators/gem5/tests/configs/tsunami-simple-timing.py

@@ -0,0 +1,100 @@
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Steve Reinhardt
+
+import m5
+from m5.objects import *
+m5.util.addToPath('../configs/common')
+import FSConfig
+
+
+# --------------------
+# Base L1 Cache
+# ====================
+
+class L1(BaseCache):
+    latency = '1ns'
+    block_size = 64
+    mshrs = 4
+    tgts_per_mshr = 8
+    is_top_level = True
+
+# ----------------------
+# Base L2 Cache
+# ----------------------
+
+class L2(BaseCache):
+    block_size = 64
+    latency = '10ns'
+    mshrs = 92
+    tgts_per_mshr = 16
+    write_buffers = 8
+
+# ---------------------
+# I/O Cache
+# ---------------------
+class IOCache(BaseCache):
+    assoc = 8
+    block_size = 64
+    latency = '50ns'
+    mshrs = 20
+    size = '1kB'
+    tgts_per_mshr = 12
+    addr_ranges = [AddrRange(0, size='8GB')]
+    forward_snoops = False
+    is_top_level = True
+
+#cpu
+cpu = TimingSimpleCPU(cpu_id=0)
+#the system
+system = FSConfig.makeLinuxAlphaSystem('timing')
+
+system.cpu = cpu
+#create the l1/l2 bus
+system.toL2Bus = CoherentBus()
+system.iocache = IOCache()
+system.iocache.cpu_side = system.iobus.master
+system.iocache.mem_side = system.membus.slave
+
+
+#connect up the l2 cache
+system.l2c = L2(size='4MB', assoc=8)
+system.l2c.cpu_side = system.toL2Bus.master
+system.l2c.mem_side = system.membus.slave
+
+#connect up the cpu and l1s
+cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
+                            L1(size = '32kB', assoc = 4))
+# create the interrupt controller
+cpu.createInterruptController()
+# connect cpu level-1 caches to shared level-2 cache
+cpu.connectAllPorts(system.toL2Bus, system.membus)
+cpu.clock = '2GHz'
+
+root = Root(full_system=True, system=system)
+m5.ticks.setGlobalFrequency('1THz')
+

simulators/gem5/tests/configs/twosys-tsunami-simple-atomic.py

@@ -0,0 +1,62 @@
+# Copyright (c) 2006 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Lisa Hsu
+
+import m5
+from m5.objects import *
+m5.util.addToPath('../configs/common')
+from FSConfig import *
+from Benchmarks import *
+
+test_sys = makeLinuxAlphaSystem('atomic',
+                                 SysConfig('netperf-stream-client.rcS'))
+test_sys.cpu = AtomicSimpleCPU(cpu_id=0)
+# create the interrupt controller
+test_sys.cpu.createInterruptController()
+test_sys.cpu.connectAllPorts(test_sys.membus)
+# In contrast to the other (one-system) Tsunami configurations we do
+# not have an IO cache but instead rely on an IO bridge for accesses
+# from masters on the IO bus to the memory bus
+test_sys.iobridge = Bridge(delay='50ns', nack_delay='4ns',
+                           ranges = [AddrRange(0, '8GB')])
+test_sys.iobridge.slave = test_sys.iobus.master
+test_sys.iobridge.master = test_sys.membus.slave
+
+drive_sys = makeLinuxAlphaSystem('atomic',
+                                 SysConfig('netperf-server.rcS'))
+drive_sys.cpu = AtomicSimpleCPU(cpu_id=0)
+# create the interrupt controller
+drive_sys.cpu.createInterruptController()
+drive_sys.cpu.connectAllPorts(drive_sys.membus)
+drive_sys.iobridge = Bridge(delay='50ns', nack_delay='4ns',
+                            ranges = [AddrRange(0, '8GB')])
+drive_sys.iobridge.slave = drive_sys.iobus.master
+drive_sys.iobridge.master = drive_sys.membus.slave
+
+root = makeDualRoot(True, test_sys, drive_sys, "ethertrace")
+
+maxtick = 199999999

simulators/gem5/tests/diff-out

@@ -0,0 +1,372 @@
+#!/usr/bin/perl
+# Copyright (c) 2001-2005 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Steve Reinhardt
+
+#
+# This script diffs two SimpleScalar statistics output files.
+#
+
+use Getopt::Std;
+
+getopts('adn:t:h');
+
+if ($#ARGV < 1)
+{
+    print "\nError: need two file arguments (<reference> <new>).\n";
+    print "   Options: -d = Ignore distributions\n";
+    print "            -a = Sort errors alphabetically (default: by percentage)\n";
+    print "            -h = Diff header info separately from stats\n";
+    print "            -n <num> = Print top <num> errors (default 20, 0 for all)\n";
+    print "            -t <num> = Ignore errors below <num> percent (default 0)\n\n";
+    exit;
+}
+
+open(REF, "<$ARGV[0]") or die "Error: can't open $ARGV[0].\n";
+open(NEW, "<$ARGV[1]") or die "Error: can't open $ARGV[1].\n";
+
+
+#
+# Things that really should be adjustable via the command line
+#
+
+# Ignorable error (in percent)
+$err_thresh = defined($opt_t) ? $opt_t : 0;
+
+# Number of stats to print before omitting
+$omit_count = defined($opt_n) ? $opt_n : 20;
+
+
+#
+# First copy everything up to the simulation statistics to a pair of
+# temporary files, stripping out date-related items, and do a plain
+# diff.  Any differences in the arguments are not necessarily an issue;
+# any differences in the program output should be caught by the EIO
+# mechanism if an EIO file is used.
+# 
+
+# copy_header takes input filehandle and output filename
+
+sub copy_header
+{
+    my ($inhandle, $outname) = @_;
+
+    open(OUTPUT, ">$outname") or die "Error: can't open $outname.\n";
+
+    while (<$inhandle>)
+    {
+	# strip out lines that can vary
+	next if /^(command line:|M5 compiled on |M5 simulation started |M5 executing on )/;
+	last if /Begin Simulation Statistics/;
+	print OUTPUT;
+    }
+    close OUTPUT;
+}
+
+if ($opt_h) {
+
+    # Diff header separately from stats
+
+    $refheader = "/tmp/smt-test.refheader.$$";
+    $newheader = "/tmp/smt-test.newheader.$$";
+
+    copy_header(\*REF, $refheader);
+    copy_header(\*NEW, $newheader);
+
+    print "\n===== Header and program output differences =====\n\n";
+
+    print `diff $refheader $newheader`;
+
+    print "\n===== Statistics differences =====\n\n";
+}
+
+#
+# Now parse statistics
+#
+
+#
+# This function takes an open filehandle and returns a reference to
+# a hash containing all the statistics variables and their values.
+#
+sub parse_file
+{
+    $stathandle = shift;
+
+    $in_dist = undef;
+    $hashref = { };	# initialize hash for values
+
+    while (<$stathandle>)
+    {
+	next if /^\s*$/;	# skip blank lines
+	last if /End Simulation Statistics/;
+
+	s/ *#.*//;		# strip comments
+
+	if (/^Memory usage: (\d+) KBytes/) {
+	    $stat = 'memory usage';
+	    $value = $1;
+	}
+	elsif ($in_dist) {
+	    if (/(.*)\.end_dist/) {
+		# end line of distribution: clear $in_dist flag
+		$in_dist = undef;
+		next;
+	    }
+	    if ($opt_d) {
+		next;		#  bail out if we are ignoring dists...
+	    } elsif (/(.*)\.(min|max)_value/) {
+		# treat these like normal stats
+		($stat, $value) = /^(\S+)\s+(.*)/;
+	    } else {
+		($stat, $value) =
+		  /^(\S+(?:.*\S)?)\s+(\d+)\s+\d+\.\d+%/;
+		$stat = $in_dist . '::' . $stat;
+	    }
+	}
+	else {
+	    if (/(.*)\.start_dist/) {
+		# start line of distribution: set $in_dist flag
+		# and save distribution name for future reference
+		$in_dist = $1;
+		$stat = $1;
+		$value = 0;
+	    }
+	    else {
+		($stat, $value) = /^(\S+)\s+(.*)/;
+	    }
+	}
+
+	$$hashref{$stat} = $value;
+    }
+
+    close($stathandle);
+    return $hashref;
+}
+
+
+#
+# pct_diff($old, $new) returns percent difference from $old to $new.
+#
+sub pct_diff
+{
+    my ($old, $new) = @_;
+    return ($old == 0) ? (($new == 0) ? 0 : 9999) : 100 * ($new - $old) / $old;
+}
+
+
+#
+# Statistics to ignore: these relate to simulator performance, not
+# correctness, so don't fail on changes here.
+#
+%ignore = (
+  'host_seconds' => 1,
+  'host_tick_rate' => 1,
+  'host_inst_rate' => 1,
+  'host_op_rate' => 1,
+  'host_mem_usage' => 1
+);
+
+#
+# List of key statistics (always displayed)
+#  ==> list stats here WITHOUT trailing thread ID
+#
+@key_stat_list = (
+  'ipc',
+  'committedInsts',
+  'committedOps',
+  'sim_insts',
+  'sim_ops',
+  'sim_ticks',
+  'host_inst_rate',
+  'host_mem_usage'
+);
+
+$key_stat_pattern = join('|', @key_stat_list);
+
+# initialize first statistics from each file
+
+$max_err_mag = 0;
+
+$refhash = parse_file(\*REF);
+$newhash = parse_file(\*NEW);
+
+# The string sim-smt prints on a divide by zero
+$divbyzero = '<err: divide by zero>';
+
+foreach $stat (sort keys %$refhash)
+{
+    $refvalue = $$refhash{$stat};
+    $newvalue = $$newhash{$stat};
+
+    if (!defined($newvalue)) {
+	# stat missing from new file
+	push @missing_stats, $stat;
+	next;
+    }
+
+    if ($stat =~ /($key_stat_pattern)/o) {
+	# key statistics: always record & display changes in these
+	push @key_stats, [$stat, $refvalue, $newvalue];
+    }
+
+    if ($ignore{$stat} or $refvalue eq $newvalue) {
+	# stat is in "ignore" list, or hasn't changed
+    }
+    else {
+	if ($refvalue eq $divbyzero || $newvalue eq $divbyzero) {
+	    # one or the other was a divide by zero:
+	    # no point in trying to quantify error
+	    print "$stat: $refvalue --> $newvalue\n";
+	}
+	else {
+	    $reldiff = pct_diff($refvalue, $newvalue);
+	    $diffmag = abs($reldiff);
+
+	    if ($diffmag > $err_thresh) {
+		push @errs,
+		[$stat, $refvalue, $newvalue, $reldiff];
+	    }
+
+	    if ($diffmag > $max_err_mag) {
+		$max_err_mag = $diffmag;
+	    }
+	}
+    }
+
+    # remove from new hash so we can detect added stats
+    delete $$newhash{$stat};
+}
+
+
+#
+# All done.  Print comparison summary.
+#
+
+printf("Maximum error magnitude: %+f%%\n\n", $max_err_mag);
+
+printf("  %-30s %10s %10s %10s   %7s\n", ' ', 'Reference', 'New Value', 'Abs Diff', 'Pct Chg');
+
+printf("Key statistics:\n\n");
+
+foreach $key_stat (@key_stats)
+{
+    ($statname, $refvalue, $newvalue, $reldiff) = @$key_stat;
+
+    # deduce format from reference value
+    $pointpos = rindex($refvalue, '.');
+    $digits = ($pointpos < 0) ? 0 :(length($refvalue) - $pointpos - 1);
+    $fmt = "%10.${digits}f";
+
+    # print differing values with absolute and relative error
+    printf("  %-30s $fmt $fmt $fmt  %+7.2f%%\n",
+	   $statname, $refvalue, $newvalue,
+	   $newvalue - $refvalue, pct_diff($refvalue, $newvalue));
+}
+
+printf("\nDifferences > %d%%:\n\n", $err_thresh);
+
+if ($opt_a) {
+    # leave stats sorted alphabetically, doesn't make sense to cut them off
+    $omit_count = 0;
+} else {
+    # sort differences by percent change
+    @errs = sort { abs($$b[3]) <=> abs($$a[3]) } @errs;
+}
+
+$num_errs = 0;
+
+foreach $err (@errs)
+{
+    ($statname, $refvalue, $newvalue, $reldiff) = @$err;
+
+    # deduce format from reference value
+    $pointpos1 = rindex($refvalue, '.');
+    $digits1 = ($pointpos1 < 0) ? 0 :(length($refvalue) - $pointpos1 - 1);
+    $pointpos2 = rindex($newvalue, '.');
+    $digits2 = ($pointpos2 < 0) ? 0 :(length($newvalue) - $pointpos2 - 1);
+    $digits = ($digits1 > $digits2) ? $digits1 : $digits2;
+    $fmt = "%10.${digits}f";
+
+    # print differing values with absolute and relative error
+    printf("  %-30s $fmt $fmt $fmt  %+7.2f%%\n",
+	   $statname, $refvalue, $newvalue, $newvalue - $refvalue, $reldiff);
+
+    # only print top N errors
+    if ($omit_count > 0 && ++$num_errs >= $omit_count)
+    {
+	print "[... showing top $omit_count errors only, additional errors omitted ...]\n";
+	last;
+    }
+}
+
+#
+# Report missing stats
+#
+# get count
+$missing_stats = scalar(@missing_stats);
+
+if ($missing_stats)
+{
+    print "\nMissing $missing_stats reference statistics:\n\n";
+    foreach $stat (@missing_stats)
+    {
+#	print "\t$stat\n";
+	printf "  %-50s    ", $stat;
+	print  "$$refhash{$stat}\n";
+    }
+}
+
+#
+# Any stats left in newhash are added since the reference file
+#
+
+@added_stats = keys %$newhash;
+
+# get count
+$added_stats = scalar(@added_stats);
+
+if ($added_stats)
+{
+    print "\nFound $added_stats new statistics:\n\n";
+    foreach $stat (sort @added_stats)
+    {
+#	print "\t$stat\n";
+	printf "  %-50s    ", $stat;
+	print  "$$newhash{$stat}\n";
+    }
+}
+
+cleanup();
+# Exit code is 0 if all stats are found (with no extras) & no stats error, 1 otherwise
+$status = ($missing_stats == 0 && $added_stats == 0 && $max_err_mag == 0.0) ? 0 : 1;
+exit $status;
+
+sub cleanup
+{
+    unlink($refheader) if ($refheader);
+    unlink($newheader) if ($newheader);
+}

simulators/gem5/tests/halt.sh

@@ -0,0 +1 @@
+m5 exit

simulators/gem5/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simerr

@@ -0,0 +1,5 @@
+warn: Sockets disabled, not accepting terminal connections
+warn: Sockets disabled, not accepting gdb connections
+warn: Prefetch instructions in Alpha do not do anything
+warn: Prefetch instructions in Alpha do not do anything
+hack: be nice to actually delete the event here

simulators/gem5/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout

@@ -0,0 +1,13 @@
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jun  4 2012 11:50:11
+gem5 started Jun  4 2012 14:31:55
+gem5 executing on zizzer
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual
+Global frequency set at 1000000000000 ticks per second
+info: kernel located at: /dist/m5/system/binaries/vmlinux
+      0: system.tsunami.io.rtc: Real-time clock set to Thu Jan  1 00:00:00 2009
+info: Entering event queue @ 0.  Starting simulation...
+info: Launching CPU 1 @ 107002000
+Exiting @ tick 1899401490000 because m5_exit instruction encountered

simulators/gem5/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/system.terminal

@@ -0,0 +1,113 @@
+M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
+
+Got Configuration 623
+
+memsize 8000000 pages 4000 
+
+First free page after ROM 0xFFFFFC0000018000
+
+HWRPB 0xFFFFFC0000018000 l1pt 0xFFFFFC0000040000 l2pt 0xFFFFFC0000042000 l3pt_rpb 0xFFFFFC0000044000 l3pt_kernel 0xFFFFFC0000048000 l2reserv 0xFFFFFC0000046000
+
+kstart = 0xFFFFFC0000310000, kend = 0xFFFFFC0000855898, kentry = 0xFFFFFC0000310000, numCPUs = 0x2
+
+CPU Clock at 2000 MHz IntrClockFrequency=1024 
+
+Booting with 2 processor(s) 
+
+KSP: 0x20043FE8 PTBR 0x20
+
+KSP: 0x20043FE8 PTBR 0x20
+
+Console Callback at 0x0, fixup at 0x0, crb offset: 0x790
+
+Memory cluster 0 [0 - 392]
+
+Memory cluster 1 [392 - 15992]
+
+Initalizing mdt_bitmap addr 0xFFFFFC0000038000 mem_pages 4000 
+
+ConsoleDispatch at virt 100008D8 phys 188D8 val FFFFFC00000100A8
+
+Bootstraping CPU 1 with sp=0xFFFFFC0000076000
+
+unix_boot_mem ends at FFFFFC0000078000 
+
+k_argc = 0 
+
+jumping to kernel at 0xFFFFFC0000310000, (PCBB 0xFFFFFC0000018180 pfn 1067)
+
+CallbackFixup 0 18000, t7=FFFFFC000070C000
+
+Entering slaveloop for cpu 1 my_rpb=FFFFFC0000018400
+
+Linux version 2.6.13 (hsul@zed.eecs.umich.edu) (gcc version 3.4.3) #1 SMP Sun Oct 8 19:52:07 EDT 2006
+
+Booting GENERIC on Tsunami variation DP264 using machine vector DP264 from SRM
+
+Major Options: SMP LEGACY_START VERBOSE_MCHECK 
+
+Command line: root=/dev/hda1 console=ttyS0
+
+memcluster 0, usage 1, start        0, end      392
+
+memcluster 1, usage 0, start      392, end    16384
+
+freeing pages 1069:16384
+
+reserving pages 1069:1070
+
+4096K Bcache detected; load hit latency 32 cycles, load miss latency 115 cycles
+
+SMP: 2 CPUs probed -- cpu_present_mask = 3
+
+Built 1 zonelists
+
+Kernel command line: root=/dev/hda1 console=ttyS0
+
+PID hash table entries: 1024 (order: 10, 32768 bytes)
+
+Using epoch = 1900
+
+Console: colour dummy device 80x25
+
+Dentry cache hash table entries: 32768 (order: 5, 262144 bytes)
+
+Inode-cache hash table entries: 16384 (order: 4, 131072 bytes)
+
+Memory: 118784k/131072k available (3314k kernel code, 8952k reserved, 983k data, 224k init)
+
+Mount-cache hash table entries: 512
+
+SMP starting up secondaries.
+
+Slave CPU 1 console command START
+SlaveCmd: restart FFFFFC0000310020 FFFFFC0000310020 vptb FFFFFFFE00000000 my_rpb FFFFFC0000018400 my_rpb_phys 18400
+
+Brought up 2 CPUs
+
+SMP: Total of 2 processors activated (8000.15 BogoMIPS).
+
+NET: Registered protocol family 16
+
+EISA bus registered
+
+pci: enabling save/restore of SRM state
+
+SCSI subsystem initialized
+
+srm_env: version 0.0.5 loaded successfully
+
+Installing knfsd (copyright (C) 1996 okir@monad.swb.de).
+
+Initializing Cryptographic API
+
+rtc: Standard PC (1900) epoch (1900) detected
+
+Real Time Clock Driver v1.12
+
+Serial: 8250/16550 driver $Revision: 1.90 $ 1 ports, IRQ sharing disabled
+
+ttyS0 at I/O 0x3f8 (irq = 4) is a 8250
+
+io scheduler noop registered
+

simulators/gem5/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simerr

@@ -0,0 +1,5 @@
+warn: Sockets disabled, not accepting terminal connections
+warn: Sockets disabled, not accepting gdb connections
+warn: Prefetch instructions in Alpha do not do anything
+warn: Prefetch instructions in Alpha do not do anything
+hack: be nice to actually delete the event here

simulators/gem5/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout

@@ -0,0 +1,12 @@
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jun  4 2012 11:50:11
+gem5 started Jun  4 2012 14:16:04
+gem5 executing on zizzer
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3
+Global frequency set at 1000000000000 ticks per second
+info: kernel located at: /dist/m5/system/binaries/vmlinux
+      0: system.tsunami.io.rtc: Real-time clock set to Thu Jan  1 00:00:00 2009
+info: Entering event queue @ 0.  Starting simulation...
+Exiting @ tick 1858684403000 because m5_exit instruction encountered

simulators/gem5/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/system.terminal

@@ -0,0 +1,108 @@
+M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
+
+Got Configuration 623
+
+memsize 8000000 pages 4000 
+
+First free page after ROM 0xFFFFFC0000018000
+
+HWRPB 0xFFFFFC0000018000 l1pt 0xFFFFFC0000040000 l2pt 0xFFFFFC0000042000 l3pt_rpb 0xFFFFFC0000044000 l3pt_kernel 0xFFFFFC0000048000 l2reserv 0xFFFFFC0000046000
+
+kstart = 0xFFFFFC0000310000, kend = 0xFFFFFC0000855898, kentry = 0xFFFFFC0000310000, numCPUs = 0x1
+
+CPU Clock at 2000 MHz IntrClockFrequency=1024 
+
+Booting with 1 processor(s) 
+
+KSP: 0x20043FE8 PTBR 0x20
+
+Console Callback at 0x0, fixup at 0x0, crb offset: 0x510
+
+Memory cluster 0 [0 - 392]
+
+Memory cluster 1 [392 - 15992]
+
+Initalizing mdt_bitmap addr 0xFFFFFC0000038000 mem_pages 4000 
+
+ConsoleDispatch at virt 10000658 phys 18658 val FFFFFC00000100A8
+
+unix_boot_mem ends at FFFFFC0000076000 
+
+k_argc = 0 
+
+jumping to kernel at 0xFFFFFC0000310000, (PCBB 0xFFFFFC0000018180 pfn 1067)
+
+CallbackFixup 0 18000, t7=FFFFFC000070C000
+
+Linux version 2.6.13 (hsul@zed.eecs.umich.edu) (gcc version 3.4.3) #1 SMP Sun Oct 8 19:52:07 EDT 2006
+
+Booting GENERIC on Tsunami variation DP264 using machine vector DP264 from SRM
+
+Major Options: SMP LEGACY_START VERBOSE_MCHECK 
+
+Command line: root=/dev/hda1 console=ttyS0
+
+memcluster 0, usage 1, start        0, end      392
+
+memcluster 1, usage 0, start      392, end    16384
+
+freeing pages 1069:16384
+
+reserving pages 1069:1070
+
+4096K Bcache detected; load hit latency 32 cycles, load miss latency 115 cycles
+
+SMP: 1 CPUs probed -- cpu_present_mask = 1
+
+Built 1 zonelists
+
+Kernel command line: root=/dev/hda1 console=ttyS0
+
+PID hash table entries: 1024 (order: 10, 32768 bytes)
+
+Using epoch = 1900
+
+Console: colour dummy device 80x25
+
+Dentry cache hash table entries: 32768 (order: 5, 262144 bytes)
+
+Inode-cache hash table entries: 16384 (order: 4, 131072 bytes)
+
+Memory: 118784k/131072k available (3314k kernel code, 8952k reserved, 983k data, 224k init)
+
+Mount-cache hash table entries: 512
+
+SMP mode deactivated.
+
+Brought up 1 CPUs
+
+SMP: Total of 1 processors activated (4002.20 BogoMIPS).
+
+NET: Registered protocol family 16
+
+EISA bus registered
+
+pci: enabling save/restore of SRM state
+
+SCSI subsystem initialized
+
+srm_env: version 0.0.5 loaded successfully
+
+Installing knfsd (copyright (C) 1996 okir@monad.swb.de).
+
+Initializing Cryptographic API
+
+rtc: Standard PC (1900) epoch (1900) detected
+
+Real Time Clock Driver v1.12
+
+Serial: 8250/16550 driver $Revision: 1.90 $ 1 ports, IRQ sharing disabled
+
+ttyS0 at I/O 0x3f8 (irq = 4) is a 8250
+
+io scheduler noop registered
+
+io scheduler anticipatory registered
+
+io scheduler deadline registered
+

simulators/gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr

@@ -0,0 +1,26 @@
+warn: Sockets disabled, not accepting vnc client connections
+warn: Sockets disabled, not accepting terminal connections
+warn: Sockets disabled, not accepting gdb connections
+warn: The clidr register always reports 0 caches.
+warn: clidr LoUIS field of 0b001 to match current ARM implementations.
+warn: The csselr register isn't implemented.
+warn: The ccsidr register isn't implemented and always reads as 0.
+warn: 	instruction 'mcr bpiallis' unimplemented
+warn: 	instruction 'mcr icialluis' unimplemented
+warn: 	instruction 'mcr dccimvac' unimplemented
+warn: 	instruction 'mcr dccmvau' unimplemented
+warn: 	instruction 'mcr icimvau' unimplemented
+warn: 5654850500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3704, checker: 0x3708
+warn: 5664849500: Instruction results do not match! (Values may not actually be integers) Inst: 0x36c4, checker: 0x36c8
+warn: 5704830500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3604, checker: 0x3608
+warn: 5721485500: Instruction results do not match! (Values may not actually be integers) Inst: 0x35c4, checker: 0x35c8
+warn: 6170779000: Instruction results do not match! (Values may not actually be integers) Inst: 0x34f0, checker: 0x34f8
+warn: LCD dual screen mode not supported
+warn: 53396857000: Instruction results do not match! (Values may not actually be integers) Inst: 0x19dc, checker: 0x1a04
+warn: 55147144000: Instruction results do not match! (Values may not actually be integers) Inst: 0x80d0, checker: 0xc71f6fc8
+warn: 55147144000: Instruction results do not match! (Values may not actually be integers) Inst: 0x71ef0, checker: 0x60000013
+warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
+warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
+warn: 	instruction 'mcr icialluis' unimplemented
+warn: 	instruction 'mcr bpiallis' unimplemented
+hack: be nice to actually delete the event here

simulators/gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout

@@ -0,0 +1,12 @@
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jun  4 2012 12:14:06
+gem5 started Jun  4 2012 18:58:44
+gem5 executing on zizzer
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker
+Global frequency set at 1000000000000 ticks per second
+info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
+info: Using bootloader at address 0x80000000
+info: Entering event queue @ 0.  Starting simulation...
+Exiting @ tick 2501685689500 because m5_exit instruction encountered

simulators/gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt

@@ -0,0 +1,985 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds                                  2.501686                       # Number of seconds simulated
+sim_ticks                                2501685689500                       # Number of ticks simulated
+final_tick                               2501685689500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                  49441                       # Simulator instruction rate (inst/s)
+host_op_rate                                    63837                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2075989543                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 387400                       # Number of bytes of host memory used
+host_seconds                                  1205.06                       # Real time elapsed on the host
+sim_insts                                    59579009                       # Number of instructions simulated
+sim_ops                                      76926775                       # Number of ops (including micro ops) simulated
+system.realview.nvmem.bytes_read::cpu.inst           64                       # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total            64                       # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu.inst           64                       # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total           64                       # Number of instructions bytes read from this memory
+system.realview.nvmem.num_reads::cpu.inst            1                       # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total              1                       # Number of read requests responded to by this memory
+system.realview.nvmem.bw_read::cpu.inst            26                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total               26                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu.inst           26                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total           26                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu.inst           26                       # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total              26                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::realview.clcd    118440096                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.dtb.walker        12032                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.itb.walker          896                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst           1119872                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          10085712                       # Number of bytes read from this memory
+system.physmem.bytes_read::total            129658608                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst      1119872                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         1119872                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      6569664                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu.data        3016072                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           9585736                       # Number of bytes written to this memory
+system.physmem.num_reads::realview.clcd      14805012                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.dtb.walker          188                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.itb.walker           14                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst              17498                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             157623                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total              14980335                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          102651                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu.data            754018                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               856669                       # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.clcd        47344115                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.dtb.walker           4810                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.itb.walker            358                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               447647                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              4031566                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                51828496                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          447647                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             447647                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           2626095                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data             1205616                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                3831711                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           2626095                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.clcd       47344115                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker          4810                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.itb.walker           358                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              447647                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             5237182                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               55660207                       # Total bandwidth to/from this memory (bytes/s)
+system.l2c.replacements                        119797                       # number of replacements
+system.l2c.tagsinuse                     26022.811009                       # Cycle average of tags in use
+system.l2c.total_refs                         1834134                       # Total number of references to valid blocks.
+system.l2c.sampled_refs                        150735                       # Sample count of references to valid blocks.
+system.l2c.avg_refs                         12.167937                       # Average number of references to valid blocks.
+system.l2c.warmup_cycle                             0                       # Cycle when the warmup percentage was hit.
+system.l2c.occ_blocks::writebacks        14260.921168                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.dtb.walker       79.122472                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.itb.walker        1.014068                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.inst           6176.146101                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.data           5505.607200                       # Average occupied blocks per requestor
+system.l2c.occ_percent::writebacks           0.217604                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu.dtb.walker       0.001207                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu.itb.walker       0.000015                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu.inst             0.094241                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu.data             0.084009                       # Average percentage of cache occupancy
+system.l2c.occ_percent::total                0.397077                       # Average percentage of cache occupancy
+system.l2c.ReadReq_hits::cpu.dtb.walker        144170                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu.itb.walker         12492                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu.inst             1001175                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu.data              378296                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                1536133                       # number of ReadReq hits
+system.l2c.Writeback_hits::writebacks          635023                       # number of Writeback hits
+system.l2c.Writeback_hits::total               635023                       # number of Writeback hits
+system.l2c.UpgradeReq_hits::cpu.data               45                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total                  45                       # number of UpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu.data              8                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::total                 8                       # number of SCUpgradeReq hits
+system.l2c.ReadExReq_hits::cpu.data            105875                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total               105875                       # number of ReadExReq hits
+system.l2c.demand_hits::cpu.dtb.walker         144170                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu.itb.walker          12492                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu.inst              1001175                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu.data               484171                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                 1642008                       # number of demand (read+write) hits
+system.l2c.overall_hits::cpu.dtb.walker        144170                       # number of overall hits
+system.l2c.overall_hits::cpu.itb.walker         12492                       # number of overall hits
+system.l2c.overall_hits::cpu.inst             1001175                       # number of overall hits
+system.l2c.overall_hits::cpu.data              484171                       # number of overall hits
+system.l2c.overall_hits::total                1642008                       # number of overall hits
+system.l2c.ReadReq_misses::cpu.dtb.walker          189                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu.itb.walker           14                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu.inst             17378                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu.data             19180                       # number of ReadReq misses
+system.l2c.ReadReq_misses::total                36761                       # number of ReadReq misses
+system.l2c.UpgradeReq_misses::cpu.data           3300                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total              3300                       # number of UpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu.data            5                       # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::total               5                       # number of SCUpgradeReq misses
+system.l2c.ReadExReq_misses::cpu.data          140292                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total             140292                       # number of ReadExReq misses
+system.l2c.demand_misses::cpu.dtb.walker          189                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu.itb.walker           14                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu.inst              17378                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu.data             159472                       # number of demand (read+write) misses
+system.l2c.demand_misses::total                177053                       # number of demand (read+write) misses
+system.l2c.overall_misses::cpu.dtb.walker          189                       # number of overall misses
+system.l2c.overall_misses::cpu.itb.walker           14                       # number of overall misses
+system.l2c.overall_misses::cpu.inst             17378                       # number of overall misses
+system.l2c.overall_misses::cpu.data            159472                       # number of overall misses
+system.l2c.overall_misses::total               177053                       # number of overall misses
+system.l2c.ReadReq_miss_latency::cpu.dtb.walker      9850500                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu.itb.walker       752000                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu.inst    910079500                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu.data   1002096000                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::total     1922778000                       # number of ReadReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu.data       996000                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total       996000                       # number of UpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::cpu.data       104000                       # number of SCUpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::total       104000                       # number of SCUpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu.data   7365557000                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total   7365557000                       # number of ReadExReq miss cycles
+system.l2c.demand_miss_latency::cpu.dtb.walker      9850500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu.itb.walker       752000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu.inst    910079500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu.data   8367653000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total      9288335000                       # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency::cpu.dtb.walker      9850500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu.itb.walker       752000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu.inst    910079500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu.data   8367653000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::total     9288335000                       # number of overall miss cycles
+system.l2c.ReadReq_accesses::cpu.dtb.walker       144359                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu.itb.walker        12506                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu.inst         1018553                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu.data          397476                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total            1572894                       # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks       635023                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total           635023                       # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu.data         3345                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total            3345                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu.data           13                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total            13                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu.data        246167                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total           246167                       # number of ReadExReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu.dtb.walker       144359                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu.itb.walker        12506                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu.inst          1018553                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu.data           643643                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total             1819061                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu.dtb.walker       144359                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu.itb.walker        12506                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu.inst         1018553                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu.data          643643                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total            1819061                       # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::cpu.dtb.walker     0.001309                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu.itb.walker     0.001119                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu.inst       0.017061                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu.data       0.048254                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total          0.023372                       # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu.data     0.986547                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.986547                       # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu.data     0.384615                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total     0.384615                       # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu.data     0.569906                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.569906                       # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::cpu.dtb.walker     0.001309                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu.itb.walker     0.001119                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu.inst        0.017061                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu.data        0.247765                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.097332                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu.dtb.walker     0.001309                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu.itb.walker     0.001119                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu.inst       0.017061                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu.data       0.247765                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.097332                       # miss rate for overall accesses
+system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52119.047619                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 53714.285714                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu.inst 52369.634020                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu.data 52246.923879                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 52304.833927                       # average ReadReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu.data   301.818182                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total   301.818182                       # average UpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu.data        20800                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::total        20800                       # average SCUpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu.data 52501.618054                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 52501.618054                       # average ReadExReq miss latency
+system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52119.047619                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu.itb.walker 53714.285714                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu.inst 52369.634020                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu.data 52470.985502                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 52460.760337                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52119.047619                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu.itb.walker 53714.285714                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu.inst 52369.634020                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu.data 52470.985502                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 52460.760337                       # average overall miss latency
+system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
+system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
+system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
+system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
+system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.l2c.fast_writes                              0                       # number of fast writes performed
+system.l2c.cache_copies                             0                       # number of cache copies performed
+system.l2c.writebacks::writebacks              102651                       # number of writebacks
+system.l2c.writebacks::total                   102651                       # number of writebacks
+system.l2c.ReadReq_mshr_hits::cpu.dtb.walker            1                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::cpu.inst             14                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::cpu.data             86                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::total               101                       # number of ReadReq MSHR hits
+system.l2c.demand_mshr_hits::cpu.dtb.walker            1                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu.inst              14                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu.data              86                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::total                101                       # number of demand (read+write) MSHR hits
+system.l2c.overall_mshr_hits::cpu.dtb.walker            1                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu.inst             14                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu.data             86                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::total               101                       # number of overall MSHR hits
+system.l2c.ReadReq_mshr_misses::cpu.dtb.walker          188                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu.itb.walker           14                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu.inst        17364                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu.data        19094                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::total           36660                       # number of ReadReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu.data         3300                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total         3300                       # number of UpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu.data            5                       # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::total            5                       # number of SCUpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu.data       140292                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total        140292                       # number of ReadExReq MSHR misses
+system.l2c.demand_mshr_misses::cpu.dtb.walker          188                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu.itb.walker           14                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu.inst         17364                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu.data        159386                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total           176952                       # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses::cpu.dtb.walker          188                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu.itb.walker           14                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu.inst        17364                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu.data       159386                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total          176952                       # number of overall MSHR misses
+system.l2c.ReadReq_mshr_miss_latency::cpu.dtb.walker      7532000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker       584000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu.inst    697406000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu.data    765603000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::total   1471125000                       # number of ReadReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu.data    132880000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total    132880000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu.data       200000                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::total       200000                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu.data   5622122500                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total   5622122500                       # number of ReadExReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu.dtb.walker      7532000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu.itb.walker       584000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu.inst    697406000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu.data   6387725500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total   7093247500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu.dtb.walker      7532000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu.itb.walker       584000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu.inst    697406000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu.data   6387725500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total   7093247500                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu.inst      5427000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 131758586500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total 131764013500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data  32346095899                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total  32346095899                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu.inst      5427000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu.data 164104682399                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total 164110109399                       # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.001302                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker     0.001119                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu.inst     0.017048                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu.data     0.048038                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total     0.023307                       # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu.data     0.986547                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.986547                       # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu.data     0.384615                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.384615                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu.data     0.569906                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.569906                       # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu.dtb.walker     0.001302                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu.itb.walker     0.001119                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu.inst     0.017048                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu.data     0.247631                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.097277                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu.dtb.walker     0.001302                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu.itb.walker     0.001119                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu.inst     0.017048                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu.data     0.247631                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.097277                       # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40063.829787                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 41714.285714                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40163.902327                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40096.522468                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 40128.887070                       # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40266.666667                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40266.666667                       # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        40000                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total        40000                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40074.434038                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 40074.434038                       # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40063.829787                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 41714.285714                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40163.902327                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu.data 40077.080170                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 40085.715335                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40063.829787                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 41714.285714                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40163.902327                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu.data 40077.080170                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 40085.715335                       # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
+system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
+system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
+system.cf0.dma_read_bytes                           0                       # Number of bytes transfered via DMA reads (not PRD).
+system.cf0.dma_read_txs                             0                       # Number of DMA read transactions (not PRD).
+system.cf0.dma_write_full_pages                     0                       # Number of full page size DMA writes.
+system.cf0.dma_write_bytes                          0                       # Number of bytes transfered via DMA writes.
+system.cf0.dma_write_txs                            0                       # Number of DMA write transactions.
+system.cpu.checker.dtb.inst_hits                    0                       # ITB inst hits
+system.cpu.checker.dtb.inst_misses                  0                       # ITB inst misses
+system.cpu.checker.dtb.read_hits             15048343                       # DTB read hits
+system.cpu.checker.dtb.read_misses               7305                       # DTB read misses
+system.cpu.checker.dtb.write_hits            11293933                       # DTB write hits
+system.cpu.checker.dtb.write_misses              2191                       # DTB write misses
+system.cpu.checker.dtb.flush_tlb                    4                       # Number of times complete TLB was flushed
+system.cpu.checker.dtb.flush_tlb_mva                0                       # Number of times TLB was flushed by MVA
+system.cpu.checker.dtb.flush_tlb_mva_asid         2878                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.checker.dtb.flush_tlb_asid             126                       # Number of times TLB was flushed by ASID
+system.cpu.checker.dtb.flush_entries             6410                       # Number of entries that have been flushed from TLB
+system.cpu.checker.dtb.align_faults                 0                       # Number of TLB faults due to alignment restrictions
+system.cpu.checker.dtb.prefetch_faults            177                       # Number of TLB faults due to prefetch
+system.cpu.checker.dtb.domain_faults                0                       # Number of TLB faults due to domain restrictions
+system.cpu.checker.dtb.perms_faults               452                       # Number of TLB faults due to permissions restrictions
+system.cpu.checker.dtb.read_accesses         15055648                       # DTB read accesses
+system.cpu.checker.dtb.write_accesses        11296124                       # DTB write accesses
+system.cpu.checker.dtb.inst_accesses                0                       # ITB inst accesses
+system.cpu.checker.dtb.hits                  26342276                       # DTB hits
+system.cpu.checker.dtb.misses                    9496                       # DTB misses
+system.cpu.checker.dtb.accesses              26351772                       # DTB accesses
+system.cpu.checker.itb.inst_hits             60745631                       # ITB inst hits
+system.cpu.checker.itb.inst_misses               4471                       # ITB inst misses
+system.cpu.checker.itb.read_hits                    0                       # DTB read hits
+system.cpu.checker.itb.read_misses                  0                       # DTB read misses
+system.cpu.checker.itb.write_hits                   0                       # DTB write hits
+system.cpu.checker.itb.write_misses                 0                       # DTB write misses
+system.cpu.checker.itb.flush_tlb                    4                       # Number of times complete TLB was flushed
+system.cpu.checker.itb.flush_tlb_mva                0                       # Number of times TLB was flushed by MVA
+system.cpu.checker.itb.flush_tlb_mva_asid         2878                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.checker.itb.flush_tlb_asid             126                       # Number of times TLB was flushed by ASID
+system.cpu.checker.itb.flush_entries             4682                       # Number of entries that have been flushed from TLB
+system.cpu.checker.itb.align_faults                 0                       # Number of TLB faults due to alignment restrictions
+system.cpu.checker.itb.prefetch_faults              0                       # Number of TLB faults due to prefetch
+system.cpu.checker.itb.domain_faults                0                       # Number of TLB faults due to domain restrictions
+system.cpu.checker.itb.perms_faults                 0                       # Number of TLB faults due to permissions restrictions
+system.cpu.checker.itb.read_accesses                0                       # DTB read accesses
+system.cpu.checker.itb.write_accesses               0                       # DTB write accesses
+system.cpu.checker.itb.inst_accesses         60750102                       # ITB inst accesses
+system.cpu.checker.itb.hits                  60745631                       # DTB hits
+system.cpu.checker.itb.misses                    4471                       # DTB misses
+system.cpu.checker.itb.accesses              60750102                       # DTB accesses
+system.cpu.checker.numCycles                 77205204                       # number of cpu cycles simulated
+system.cpu.checker.numWorkItemsStarted              0                       # number of work items this cpu started
+system.cpu.checker.numWorkItemsCompleted            0                       # number of work items this cpu completed
+system.cpu.dtb.inst_hits                            0                       # ITB inst hits
+system.cpu.dtb.inst_misses                          0                       # ITB inst misses
+system.cpu.dtb.read_hits                     52103903                       # DTB read hits
+system.cpu.dtb.read_misses                      93079                       # DTB read misses
+system.cpu.dtb.write_hits                    11946241                       # DTB write hits
+system.cpu.dtb.write_misses                     25022                       # DTB write misses
+system.cpu.dtb.flush_tlb                            4                       # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid                2878                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid                     126                       # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries                     8141                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults                      5562                       # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults                    707                       # Number of TLB faults due to prefetch
+system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.dtb.perms_faults                      2799                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                 52196982                       # DTB read accesses
+system.cpu.dtb.write_accesses                11971263                       # DTB write accesses
+system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.dtb.hits                          64050144                       # DTB hits
+system.cpu.dtb.misses                          118101                       # DTB misses
+system.cpu.dtb.accesses                      64168245                       # DTB accesses
+system.cpu.itb.inst_hits                     13717584                       # ITB inst hits
+system.cpu.itb.inst_misses                      12272                       # ITB inst misses
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
+system.cpu.itb.flush_tlb                            4                       # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid                2878                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid                     126                       # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries                     5306                       # Number of entries that have been flushed from TLB
+system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.itb.perms_faults                      6863                       # Number of TLB faults due to permissions restrictions
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.inst_accesses                 13729856                       # ITB inst accesses
+system.cpu.itb.hits                          13717584                       # DTB hits
+system.cpu.itb.misses                           12272                       # DTB misses
+system.cpu.itb.accesses                      13729856                       # DTB accesses
+system.cpu.numCycles                        411352060                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.BPredUnit.lookups                 15654738                       # Number of BP lookups
+system.cpu.BPredUnit.condPredicted           12362397                       # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect             932839                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups              10530768                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                  8288874                       # Number of BTB hits
+system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.BPredUnit.usedRAS                  1329017                       # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect              195537                       # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles           33116930                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      103031700                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    15654738                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches            9617891                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                      22620194                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 6706106                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles                     163882                       # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.BlockedCycles               89861042                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                 2823                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles        147160                       # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles       218224                       # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles          462                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                  13709942                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                998560                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes                    6868                       # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples          150746244                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              0.848897                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.234280                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                128142810     85.01%     85.01% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  1478319      0.98%     85.99% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  1855018      1.23%     87.22% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                  2695901      1.79%     89.01% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  1893540      1.26%     90.26% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                  1191101      0.79%     91.05% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                  2951659      1.96%     93.01% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                   850848      0.56%     93.57% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                  9687048      6.43%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::total            150746244                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.038057                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.250471                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 35228906                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              89710063                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  20347806                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               1026685                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                4432784                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved              2275641                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                186729                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              120042439                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                604390                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                4432784                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 37305734                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                37165628                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles       46502465                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  19251695                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles               6087938                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              112539597                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                  3873                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                1013212                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents               4109157                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents            45575                       # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands           117156815                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups             517555842                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        517460811                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups             95031                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps              77687687                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                 39469127                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts             939790                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts         835958                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  12443241                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             21685850                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            14072237                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           1938675                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          2482763                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  102391550                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded             1619583                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 126350622                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            234593                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        26254924                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     71509700                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved         332277                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     150746244                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.838168                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.542455                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           105470655     69.97%     69.97% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            14086510      9.34%     79.31% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2             7371222      4.89%     84.20% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3             5923402      3.93%     88.13% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            12762751      8.47%     96.60% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5             2810704      1.86%     98.46% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             1735902      1.15%     99.61% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7              449258      0.30%     99.91% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              135840      0.09%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       150746244                       # Number of insts issued each cycle
+system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                   61043      0.69%      0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      4      0.00%      0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                8421186     94.66%     95.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                414230      4.66%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
+system.cpu.iq.FU_type_0::No_OpClass            106530      0.08%      0.08% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu              59762768     47.30%     47.38% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                95812      0.08%     47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                  38      0.00%     47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                 45      0.00%     47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               9      0.00%     47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc           2279      0.00%     47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            9      0.00%     47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             53776494     42.56%     90.02% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            12606638      9.98%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::total              126350622                       # Type of FU issued
+system.cpu.iq.rate                           0.307159                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     8896463                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.070411                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          412671946                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         130285978                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses     87040433                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads               24078                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes              13182                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses        10434                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              135127716                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                   12839                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads           636069                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
+system.cpu.iew.lsq.thread0.squashedLoads      5970496                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        11101                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        34253                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      2273952                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
+system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
+system.cpu.iew.lsq.thread0.rescheduledLoads     34114355                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked       1152098                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
+system.cpu.iew.iewSquashCycles                4432784                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                28604721                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                436722                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           104273041                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            335924                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts              21685850                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             14072237                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts             992808                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                  95700                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                 11591                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          34253                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         552378                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       346914                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts               899292                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             123108789                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              52799372                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           3241833                       # Number of squashed instructions skipped in execute
+system.cpu.iew.exec_swp                             0                       # number of swp insts executed
+system.cpu.iew.exec_nop                        261908                       # number of nop insts executed
+system.cpu.iew.exec_refs                     65255060                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 11601340                       # Number of branches executed
+system.cpu.iew.exec_stores                   12455688                       # Number of stores executed
+system.cpu.iew.exec_rate                     0.299278                       # Inst execution rate
+system.cpu.iew.wb_sent                      121555618                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                      87050867                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                  47546734                       # num instructions producing a value
+system.cpu.iew.wb_consumers                  88572059                       # num instructions consuming a value
+system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
+system.cpu.iew.wb_rate                       0.211621                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.536814                       # average fanout of values written-back
+system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu.commit.commitCommittedInsts       59729390                       # The number of committed instructions
+system.cpu.commit.commitCommittedOps         77077156                       # The number of committed instructions
+system.cpu.commit.commitSquashedInsts        27015439                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls         1287306                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts            793496                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    146395876                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.526498                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.504904                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    118626341     81.03%     81.03% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     13714527      9.37%     90.40% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2      3991808      2.73%     93.13% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      2249419      1.54%     94.66% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      1746576      1.19%     95.86% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      1042045      0.71%     96.57% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      1550885      1.06%     97.63% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7       665283      0.45%     98.08% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      2808992      1.92%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    146395876                       # Number of insts commited each cycle
+system.cpu.commit.committedInsts             59729390                       # Number of instructions committed
+system.cpu.commit.committedOps               77077156                       # Number of ops (including micro ops) committed
+system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
+system.cpu.commit.refs                       27513639                       # Number of memory references committed
+system.cpu.commit.loads                      15715354                       # Number of loads committed
+system.cpu.commit.membars                      413068                       # Number of memory barriers committed
+system.cpu.commit.branches                    9904424                       # Number of branches committed
+system.cpu.commit.fp_insts                      10212                       # Number of committed floating point instructions.
+system.cpu.commit.int_insts                  68617835                       # Number of committed integer instructions.
+system.cpu.commit.function_calls               995976                       # Number of function calls committed.
+system.cpu.commit.bw_lim_events               2808992                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
+system.cpu.rob.rob_reads                    245922084                       # The number of ROB reads
+system.cpu.rob.rob_writes                   212744706                       # The number of ROB writes
+system.cpu.timesIdled                         1895448                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                       260605816                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.quiesceCycles                   4591931267                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.committedInsts                    59579009                       # Number of Instructions Simulated
+system.cpu.committedOps                      76926775                       # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total              59579009                       # Number of Instructions Simulated
+system.cpu.cpi                               6.904312                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         6.904312                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.144837                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.144837                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                558200785                       # number of integer regfile reads
+system.cpu.int_regfile_writes                89400907                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                      8900                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                     2982                       # number of floating regfile writes
+system.cpu.misc_regfile_reads               135543435                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                 912729                       # number of misc regfile writes
+system.cpu.icache.replacements                1019271                       # number of replacements
+system.cpu.icache.tagsinuse                511.444719                       # Cycle average of tags in use
+system.cpu.icache.total_refs                 12598089                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                1019783                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs                  12.353696                       # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle             6290137000                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::cpu.inst     511.444719                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.998915                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.998915                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst     12598089                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        12598089                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      12598089                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         12598089                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     12598089                       # number of overall hits
+system.cpu.icache.overall_hits::total        12598089                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst      1111711                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total       1111711                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst      1111711                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total        1111711                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst      1111711                       # number of overall misses
+system.cpu.icache.overall_misses::total       1111711                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst  16369836984                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total  16369836984                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst  16369836984                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total  16369836984                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst  16369836984                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total  16369836984                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     13709800                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     13709800                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     13709800                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     13709800                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     13709800                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     13709800                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.081089                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.081089                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.081089                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.081089                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.081089                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.081089                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14724.903310                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 14724.903310                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 14724.903310                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 14724.903310                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 14724.903310                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 14724.903310                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs      2973484                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs               393                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs  7566.117048                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.icache.fast_writes                       0                       # number of fast writes performed
+system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.writebacks::writebacks        60091                       # number of writebacks
+system.cpu.icache.writebacks::total             60091                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst        91891                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total        91891                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst        91891                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total        91891                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst        91891                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total        91891                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1019820                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total      1019820                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst      1019820                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total      1019820                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst      1019820                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total      1019820                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  12187570984                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total  12187570984                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst  12187570984                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total  12187570984                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst  12187570984                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total  12187570984                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst      7292000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_uncacheable_latency::total      7292000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst      7292000                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_latency::total      7292000                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.074386                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.074386                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.074386                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.074386                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.074386                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.074386                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11950.707952                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11950.707952                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11950.707952                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 11950.707952                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11950.707952                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 11950.707952                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
+system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average overall mshr uncacheable latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
+system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.replacements                 645895                       # number of replacements
+system.cpu.dcache.tagsinuse                511.991565                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                 22075422                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                 646407                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                  34.150964                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle               49188000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data     511.991565                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.999984                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.999984                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data     14216478                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        14216478                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      7283636                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        7283636                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data       286092                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total       286092                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data       285655                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total       285655                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data      21500114                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         21500114                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     21500114                       # number of overall hits
+system.cpu.dcache.overall_hits::total        21500114                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       747655                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        747655                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      2966865                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      2966865                       # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data        13747                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total        13747                       # number of LoadLockedReq misses
+system.cpu.dcache.StoreCondReq_misses::cpu.data           13                       # number of StoreCondReq misses
+system.cpu.dcache.StoreCondReq_misses::total           13                       # number of StoreCondReq misses
+system.cpu.dcache.demand_misses::cpu.data      3714520                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        3714520                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      3714520                       # number of overall misses
+system.cpu.dcache.overall_misses::total       3714520                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  11237363500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  11237363500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 110154178240                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 110154178240                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    224042000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total    224042000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       394000                       # number of StoreCondReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::total       394000                       # number of StoreCondReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 121391541740                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 121391541740                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 121391541740                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 121391541740                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     14964133                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     14964133                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data     10250501                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total     10250501                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data       299839                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total       299839                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data       285668                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total       285668                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     25214634                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     25214634                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     25214634                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     25214634                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.049963                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.049963                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.289436                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.289436                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.045848                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.045848                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000046                       # miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::total     0.000046                       # miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.147316                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.147316                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.147316                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.147316                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15030.145589                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 15030.145589                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37128.139717                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 37128.139717                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16297.519459                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16297.519459                       # average LoadLockedReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 30307.692308                       # average StoreCondReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::total 30307.692308                       # average StoreCondReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 32680.276789                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 32680.276789                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 32680.276789                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 32680.276789                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs     17091437                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets      7607500                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs              3024                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets             268                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs  5651.930225                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 28386.194030                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.writebacks::writebacks       574932                       # number of writebacks
+system.cpu.dcache.writebacks::total            574932                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       359686                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       359686                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data      2717440                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total      2717440                       # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data         1386                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total         1386                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data      3077126                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      3077126                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      3077126                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      3077126                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data       387969                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       387969                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       249425                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       249425                       # number of WriteReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        12361                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total        12361                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data           13                       # number of StoreCondReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::total           13                       # number of StoreCondReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data       637394                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       637394                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       637394                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       637394                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   5287973500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   5287973500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   8908906437                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   8908906437                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    165672500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    165672500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       351500                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       351500                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  14196879937                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  14196879937                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  14196879937                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  14196879937                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 147151877500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 147151877500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data  42255772015                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total  42255772015                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 189407649515                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total 189407649515                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.025927                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.025927                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.024333                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.024333                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.041225                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.041225                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000046                       # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000046                       # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.025279                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.025279                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.025279                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.025279                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13629.886666                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13629.886666                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35717.776634                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35717.776634                       # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13402.839576                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13402.839576                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 27038.461538                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 27038.461538                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22273.319073                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 22273.319073                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22273.319073                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 22273.319073                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.iocache.replacements                         0                       # number of replacements
+system.iocache.tagsinuse                            0                       # Cycle average of tags in use
+system.iocache.total_refs                           0                       # Total number of references to valid blocks.
+system.iocache.sampled_refs                         0                       # Sample count of references to valid blocks.
+system.iocache.avg_refs                           nan                       # Average number of references to valid blocks.
+system.iocache.warmup_cycle                         0                       # Cycle when the warmup percentage was hit.
+system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
+system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
+system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.iocache.fast_writes                          0                       # number of fast writes performed
+system.iocache.cache_copies                         0                       # number of cache copies performed
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1296131413558                       # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 1296131413558                       # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1296131413558                       # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 1296131413558                       # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average ReadReq mshr uncacheable latency
+system.iocache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
+system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average overall mshr uncacheable latency
+system.iocache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
+system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
+system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
+system.cpu.kern.inst.quiesce                    88053                       # number of quiesce instructions executed
+
+---------- End Simulation Statistics   ----------

simulators/gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr

@@ -0,0 +1,18 @@
+warn: Sockets disabled, not accepting vnc client connections
+warn: Sockets disabled, not accepting terminal connections
+warn: Sockets disabled, not accepting gdb connections
+warn: The clidr register always reports 0 caches.
+warn: clidr LoUIS field of 0b001 to match current ARM implementations.
+warn: The csselr register isn't implemented.
+warn: The ccsidr register isn't implemented and always reads as 0.
+warn: 	instruction 'mcr bpiallis' unimplemented
+warn: 	instruction 'mcr icialluis' unimplemented
+warn: 	instruction 'mcr dccimvac' unimplemented
+warn: 	instruction 'mcr dccmvau' unimplemented
+warn: 	instruction 'mcr icimvau' unimplemented
+warn: 	instruction 'mcr bpiallis' unimplemented
+warn: LCD dual screen mode not supported
+warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
+warn: 	instruction 'mcr icialluis' unimplemented
+warn: 	instruction 'mcr icialluis' unimplemented
+hack: be nice to actually delete the event here

simulators/gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout

@@ -0,0 +1,12 @@
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jun  4 2012 12:14:06
+gem5 started Jun  4 2012 18:58:50
+gem5 executing on zizzer
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual
+Global frequency set at 1000000000000 ticks per second
+info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
+info: Using bootloader at address 0x80000000
+info: Entering event queue @ 0.  Starting simulation...
+Exiting @ tick 2570833934500 because m5_exit instruction encountered

simulators/gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/status

@@ -0,0 +1 @@
+build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual FAILED!

simulators/gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr

@@ -0,0 +1,17 @@
+warn: Sockets disabled, not accepting vnc client connections
+warn: Sockets disabled, not accepting terminal connections
+warn: Sockets disabled, not accepting gdb connections
+warn: The clidr register always reports 0 caches.
+warn: clidr LoUIS field of 0b001 to match current ARM implementations.
+warn: The csselr register isn't implemented.
+warn: The ccsidr register isn't implemented and always reads as 0.
+warn: 	instruction 'mcr bpiallis' unimplemented
+warn: 	instruction 'mcr icialluis' unimplemented
+warn: 	instruction 'mcr dccimvac' unimplemented
+warn: 	instruction 'mcr dccmvau' unimplemented
+warn: 	instruction 'mcr icimvau' unimplemented
+warn: LCD dual screen mode not supported
+warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
+warn: 	instruction 'mcr icialluis' unimplemented
+warn: 	instruction 'mcr bpiallis' unimplemented
+hack: be nice to actually delete the event here

simulators/gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout

@@ -0,0 +1,12 @@
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jun  4 2012 12:14:06
+gem5 started Jun  4 2012 18:55:16
+gem5 executing on zizzer
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3
+Global frequency set at 1000000000000 ticks per second
+info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
+info: Using bootloader at address 0x80000000
+info: Entering event queue @ 0.  Starting simulation...
+Exiting @ tick 2501685689500 because m5_exit instruction encountered

simulators/gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt

@@ -0,0 +1,940 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds                                  2.501686                       # Number of seconds simulated
+sim_ticks                                2501685689500                       # Number of ticks simulated
+final_tick                               2501685689500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                  57858                       # Simulator instruction rate (inst/s)
+host_op_rate                                    74704                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2429415836                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 387132                       # Number of bytes of host memory used
+host_seconds                                  1029.75                       # Real time elapsed on the host
+sim_insts                                    59579009                       # Number of instructions simulated
+sim_ops                                      76926775                       # Number of ops (including micro ops) simulated
+system.realview.nvmem.bytes_read::cpu.inst           64                       # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total            64                       # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu.inst           64                       # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total           64                       # Number of instructions bytes read from this memory
+system.realview.nvmem.num_reads::cpu.inst            1                       # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total              1                       # Number of read requests responded to by this memory
+system.realview.nvmem.bw_read::cpu.inst            26                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total               26                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu.inst           26                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total           26                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu.inst           26                       # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total              26                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::realview.clcd    118440096                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.dtb.walker        12032                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.itb.walker          896                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst           1119872                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          10085712                       # Number of bytes read from this memory
+system.physmem.bytes_read::total            129658608                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst      1119872                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         1119872                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      6569664                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu.data        3016072                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           9585736                       # Number of bytes written to this memory
+system.physmem.num_reads::realview.clcd      14805012                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.dtb.walker          188                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.itb.walker           14                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst              17498                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             157623                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total              14980335                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          102651                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu.data            754018                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               856669                       # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.clcd        47344115                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.dtb.walker           4810                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.itb.walker            358                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               447647                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              4031566                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                51828496                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          447647                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             447647                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           2626095                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data             1205616                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                3831711                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           2626095                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.clcd       47344115                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker          4810                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.itb.walker           358                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              447647                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             5237182                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               55660207                       # Total bandwidth to/from this memory (bytes/s)
+system.l2c.replacements                        119797                       # number of replacements
+system.l2c.tagsinuse                     26022.811009                       # Cycle average of tags in use
+system.l2c.total_refs                         1834134                       # Total number of references to valid blocks.
+system.l2c.sampled_refs                        150735                       # Sample count of references to valid blocks.
+system.l2c.avg_refs                         12.167937                       # Average number of references to valid blocks.
+system.l2c.warmup_cycle                             0                       # Cycle when the warmup percentage was hit.
+system.l2c.occ_blocks::writebacks        14260.921168                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.dtb.walker       79.122472                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.itb.walker        1.014068                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.inst           6176.146101                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.data           5505.607200                       # Average occupied blocks per requestor
+system.l2c.occ_percent::writebacks           0.217604                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu.dtb.walker       0.001207                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu.itb.walker       0.000015                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu.inst             0.094241                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu.data             0.084009                       # Average percentage of cache occupancy
+system.l2c.occ_percent::total                0.397077                       # Average percentage of cache occupancy
+system.l2c.ReadReq_hits::cpu.dtb.walker        144170                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu.itb.walker         12492                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu.inst             1001175                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu.data              378296                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                1536133                       # number of ReadReq hits
+system.l2c.Writeback_hits::writebacks          635023                       # number of Writeback hits
+system.l2c.Writeback_hits::total               635023                       # number of Writeback hits
+system.l2c.UpgradeReq_hits::cpu.data               45                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total                  45                       # number of UpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu.data              8                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::total                 8                       # number of SCUpgradeReq hits
+system.l2c.ReadExReq_hits::cpu.data            105875                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total               105875                       # number of ReadExReq hits
+system.l2c.demand_hits::cpu.dtb.walker         144170                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu.itb.walker          12492                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu.inst              1001175                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu.data               484171                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                 1642008                       # number of demand (read+write) hits
+system.l2c.overall_hits::cpu.dtb.walker        144170                       # number of overall hits
+system.l2c.overall_hits::cpu.itb.walker         12492                       # number of overall hits
+system.l2c.overall_hits::cpu.inst             1001175                       # number of overall hits
+system.l2c.overall_hits::cpu.data              484171                       # number of overall hits
+system.l2c.overall_hits::total                1642008                       # number of overall hits
+system.l2c.ReadReq_misses::cpu.dtb.walker          189                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu.itb.walker           14                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu.inst             17378                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu.data             19180                       # number of ReadReq misses
+system.l2c.ReadReq_misses::total                36761                       # number of ReadReq misses
+system.l2c.UpgradeReq_misses::cpu.data           3300                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total              3300                       # number of UpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu.data            5                       # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::total               5                       # number of SCUpgradeReq misses
+system.l2c.ReadExReq_misses::cpu.data          140292                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total             140292                       # number of ReadExReq misses
+system.l2c.demand_misses::cpu.dtb.walker          189                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu.itb.walker           14                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu.inst              17378                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu.data             159472                       # number of demand (read+write) misses
+system.l2c.demand_misses::total                177053                       # number of demand (read+write) misses
+system.l2c.overall_misses::cpu.dtb.walker          189                       # number of overall misses
+system.l2c.overall_misses::cpu.itb.walker           14                       # number of overall misses
+system.l2c.overall_misses::cpu.inst             17378                       # number of overall misses
+system.l2c.overall_misses::cpu.data            159472                       # number of overall misses
+system.l2c.overall_misses::total               177053                       # number of overall misses
+system.l2c.ReadReq_miss_latency::cpu.dtb.walker      9850500                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu.itb.walker       752000                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu.inst    910079500                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu.data   1002096000                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::total     1922778000                       # number of ReadReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu.data       996000                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total       996000                       # number of UpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::cpu.data       104000                       # number of SCUpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::total       104000                       # number of SCUpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu.data   7365557000                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total   7365557000                       # number of ReadExReq miss cycles
+system.l2c.demand_miss_latency::cpu.dtb.walker      9850500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu.itb.walker       752000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu.inst    910079500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu.data   8367653000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total      9288335000                       # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency::cpu.dtb.walker      9850500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu.itb.walker       752000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu.inst    910079500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu.data   8367653000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::total     9288335000                       # number of overall miss cycles
+system.l2c.ReadReq_accesses::cpu.dtb.walker       144359                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu.itb.walker        12506                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu.inst         1018553                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu.data          397476                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total            1572894                       # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks       635023                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total           635023                       # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu.data         3345                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total            3345                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu.data           13                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total            13                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu.data        246167                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total           246167                       # number of ReadExReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu.dtb.walker       144359                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu.itb.walker        12506                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu.inst          1018553                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu.data           643643                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total             1819061                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu.dtb.walker       144359                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu.itb.walker        12506                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu.inst         1018553                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu.data          643643                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total            1819061                       # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::cpu.dtb.walker     0.001309                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu.itb.walker     0.001119                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu.inst       0.017061                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu.data       0.048254                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total          0.023372                       # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu.data     0.986547                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.986547                       # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu.data     0.384615                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total     0.384615                       # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu.data     0.569906                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.569906                       # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::cpu.dtb.walker     0.001309                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu.itb.walker     0.001119                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu.inst        0.017061                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu.data        0.247765                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.097332                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu.dtb.walker     0.001309                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu.itb.walker     0.001119                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu.inst       0.017061                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu.data       0.247765                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.097332                       # miss rate for overall accesses
+system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52119.047619                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 53714.285714                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu.inst 52369.634020                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu.data 52246.923879                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 52304.833927                       # average ReadReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu.data   301.818182                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total   301.818182                       # average UpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu.data        20800                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::total        20800                       # average SCUpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu.data 52501.618054                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 52501.618054                       # average ReadExReq miss latency
+system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52119.047619                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu.itb.walker 53714.285714                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu.inst 52369.634020                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu.data 52470.985502                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 52460.760337                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52119.047619                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu.itb.walker 53714.285714                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu.inst 52369.634020                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu.data 52470.985502                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 52460.760337                       # average overall miss latency
+system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
+system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
+system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
+system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
+system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.l2c.fast_writes                              0                       # number of fast writes performed
+system.l2c.cache_copies                             0                       # number of cache copies performed
+system.l2c.writebacks::writebacks              102651                       # number of writebacks
+system.l2c.writebacks::total                   102651                       # number of writebacks
+system.l2c.ReadReq_mshr_hits::cpu.dtb.walker            1                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::cpu.inst             14                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::cpu.data             86                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::total               101                       # number of ReadReq MSHR hits
+system.l2c.demand_mshr_hits::cpu.dtb.walker            1                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu.inst              14                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu.data              86                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::total                101                       # number of demand (read+write) MSHR hits
+system.l2c.overall_mshr_hits::cpu.dtb.walker            1                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu.inst             14                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu.data             86                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::total               101                       # number of overall MSHR hits
+system.l2c.ReadReq_mshr_misses::cpu.dtb.walker          188                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu.itb.walker           14                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu.inst        17364                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu.data        19094                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::total           36660                       # number of ReadReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu.data         3300                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total         3300                       # number of UpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu.data            5                       # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::total            5                       # number of SCUpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu.data       140292                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total        140292                       # number of ReadExReq MSHR misses
+system.l2c.demand_mshr_misses::cpu.dtb.walker          188                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu.itb.walker           14                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu.inst         17364                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu.data        159386                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total           176952                       # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses::cpu.dtb.walker          188                       # number of overall MSHR misses
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+system.l2c.overall_mshr_misses::cpu.inst        17364                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu.data       159386                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total          176952                       # number of overall MSHR misses
+system.l2c.ReadReq_mshr_miss_latency::cpu.dtb.walker      7532000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker       584000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu.inst    697406000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu.data    765603000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::total   1471125000                       # number of ReadReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu.data    132880000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total    132880000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu.data       200000                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::total       200000                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu.data   5622122500                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total   5622122500                       # number of ReadExReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu.dtb.walker      7532000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu.itb.walker       584000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu.inst    697406000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu.data   6387725500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total   7093247500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu.dtb.walker      7532000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu.itb.walker       584000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu.inst    697406000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu.data   6387725500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total   7093247500                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu.inst      5427000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 131758586500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total 131764013500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data  32346095899                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total  32346095899                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu.inst      5427000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu.data 164104682399                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total 164110109399                       # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.001302                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker     0.001119                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu.inst     0.017048                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu.data     0.048038                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total     0.023307                       # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu.data     0.986547                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.986547                       # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu.data     0.384615                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.384615                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu.data     0.569906                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.569906                       # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu.dtb.walker     0.001302                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu.itb.walker     0.001119                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu.inst     0.017048                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu.data     0.247631                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.097277                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu.dtb.walker     0.001302                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu.itb.walker     0.001119                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu.inst     0.017048                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu.data     0.247631                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.097277                       # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40063.829787                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 41714.285714                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40163.902327                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40096.522468                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 40128.887070                       # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40266.666667                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40266.666667                       # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        40000                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total        40000                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40074.434038                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 40074.434038                       # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40063.829787                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 41714.285714                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40163.902327                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu.data 40077.080170                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 40085.715335                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40063.829787                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 41714.285714                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40163.902327                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu.data 40077.080170                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 40085.715335                       # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
+system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
+system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
+system.cf0.dma_read_bytes                           0                       # Number of bytes transfered via DMA reads (not PRD).
+system.cf0.dma_read_txs                             0                       # Number of DMA read transactions (not PRD).
+system.cf0.dma_write_full_pages                     0                       # Number of full page size DMA writes.
+system.cf0.dma_write_bytes                          0                       # Number of bytes transfered via DMA writes.
+system.cf0.dma_write_txs                            0                       # Number of DMA write transactions.
+system.cpu.dtb.inst_hits                            0                       # ITB inst hits
+system.cpu.dtb.inst_misses                          0                       # ITB inst misses
+system.cpu.dtb.read_hits                     52103903                       # DTB read hits
+system.cpu.dtb.read_misses                      93079                       # DTB read misses
+system.cpu.dtb.write_hits                    11946241                       # DTB write hits
+system.cpu.dtb.write_misses                     25022                       # DTB write misses
+system.cpu.dtb.flush_tlb                            2                       # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid                1439                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid                      63                       # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries                     4532                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults                      5562                       # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults                    707                       # Number of TLB faults due to prefetch
+system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.dtb.perms_faults                      2799                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                 52196982                       # DTB read accesses
+system.cpu.dtb.write_accesses                11971263                       # DTB write accesses
+system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.dtb.hits                          64050144                       # DTB hits
+system.cpu.dtb.misses                          118101                       # DTB misses
+system.cpu.dtb.accesses                      64168245                       # DTB accesses
+system.cpu.itb.inst_hits                     13717584                       # ITB inst hits
+system.cpu.itb.inst_misses                      12272                       # ITB inst misses
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
+system.cpu.itb.flush_tlb                            2                       # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid                1439                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid                      63                       # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries                     2655                       # Number of entries that have been flushed from TLB
+system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.itb.perms_faults                      6863                       # Number of TLB faults due to permissions restrictions
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.inst_accesses                 13729856                       # ITB inst accesses
+system.cpu.itb.hits                          13717584                       # DTB hits
+system.cpu.itb.misses                           12272                       # DTB misses
+system.cpu.itb.accesses                      13729856                       # DTB accesses
+system.cpu.numCycles                        411352060                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.BPredUnit.lookups                 15654738                       # Number of BP lookups
+system.cpu.BPredUnit.condPredicted           12362397                       # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect             932839                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups              10530768                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                  8288874                       # Number of BTB hits
+system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.BPredUnit.usedRAS                  1329017                       # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect              195537                       # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles           33116930                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      103031700                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    15654738                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches            9617891                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                      22620194                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 6706106                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles                     163882                       # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.BlockedCycles               89861042                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                 2823                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles        147160                       # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles       218224                       # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles          462                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                  13709942                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                998560                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes                    6868                       # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples          150746244                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              0.848897                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.234280                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                128142810     85.01%     85.01% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  1478319      0.98%     85.99% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  1855018      1.23%     87.22% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                  2695901      1.79%     89.01% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  1893540      1.26%     90.26% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                  1191101      0.79%     91.05% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                  2951659      1.96%     93.01% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                   850848      0.56%     93.57% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                  9687048      6.43%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::total            150746244                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.038057                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.250471                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 35228906                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              89710063                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  20347806                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               1026685                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                4432784                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved              2275641                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                186729                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              120042439                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                604390                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                4432784                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 37305734                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                37165628                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles       46502465                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  19251695                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles               6087938                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              112539597                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                  3873                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                1013212                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents               4109157                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents            45575                       # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands           117156815                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups             517555842                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        517460811                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups             95031                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps              77687687                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                 39469127                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts             939790                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts         835958                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  12443241                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             21685850                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            14072237                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           1938675                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          2482763                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  102391550                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded             1619583                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 126350622                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            234593                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        26254924                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     71509700                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved         332277                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     150746244                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.838168                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.542455                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           105470655     69.97%     69.97% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            14086510      9.34%     79.31% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2             7371222      4.89%     84.20% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3             5923402      3.93%     88.13% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            12762751      8.47%     96.60% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5             2810704      1.86%     98.46% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             1735902      1.15%     99.61% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7              449258      0.30%     99.91% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              135840      0.09%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       150746244                       # Number of insts issued each cycle
+system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                   61043      0.69%      0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      4      0.00%      0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                8421186     94.66%     95.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                414230      4.66%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
+system.cpu.iq.FU_type_0::No_OpClass            106530      0.08%      0.08% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu              59762768     47.30%     47.38% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                95812      0.08%     47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                  38      0.00%     47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                 45      0.00%     47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               9      0.00%     47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc           2279      0.00%     47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            9      0.00%     47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             53776494     42.56%     90.02% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            12606638      9.98%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::total              126350622                       # Type of FU issued
+system.cpu.iq.rate                           0.307159                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     8896463                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.070411                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          412671946                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         130285978                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses     87040433                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads               24078                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes              13182                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses        10434                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              135127716                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                   12839                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads           636069                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
+system.cpu.iew.lsq.thread0.squashedLoads      5970496                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        11101                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        34253                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      2273952                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
+system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
+system.cpu.iew.lsq.thread0.rescheduledLoads     34114355                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked       1152098                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
+system.cpu.iew.iewSquashCycles                4432784                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                28604721                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                436722                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           104273041                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            335924                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts              21685850                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             14072237                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts             992808                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                  95700                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                 11591                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          34253                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         552378                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       346914                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts               899292                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             123108789                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              52799372                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           3241833                       # Number of squashed instructions skipped in execute
+system.cpu.iew.exec_swp                             0                       # number of swp insts executed
+system.cpu.iew.exec_nop                        261908                       # number of nop insts executed
+system.cpu.iew.exec_refs                     65255060                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 11601340                       # Number of branches executed
+system.cpu.iew.exec_stores                   12455688                       # Number of stores executed
+system.cpu.iew.exec_rate                     0.299278                       # Inst execution rate
+system.cpu.iew.wb_sent                      121555618                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                      87050867                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                  47546734                       # num instructions producing a value
+system.cpu.iew.wb_consumers                  88572059                       # num instructions consuming a value
+system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
+system.cpu.iew.wb_rate                       0.211621                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.536814                       # average fanout of values written-back
+system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu.commit.commitCommittedInsts       59729390                       # The number of committed instructions
+system.cpu.commit.commitCommittedOps         77077156                       # The number of committed instructions
+system.cpu.commit.commitSquashedInsts        27015439                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls         1287306                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts            793496                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    146395876                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.526498                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.504904                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    118626341     81.03%     81.03% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     13714527      9.37%     90.40% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2      3991808      2.73%     93.13% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      2249419      1.54%     94.66% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      1746576      1.19%     95.86% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      1042045      0.71%     96.57% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      1550885      1.06%     97.63% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7       665283      0.45%     98.08% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      2808992      1.92%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    146395876                       # Number of insts commited each cycle
+system.cpu.commit.committedInsts             59729390                       # Number of instructions committed
+system.cpu.commit.committedOps               77077156                       # Number of ops (including micro ops) committed
+system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
+system.cpu.commit.refs                       27513639                       # Number of memory references committed
+system.cpu.commit.loads                      15715354                       # Number of loads committed
+system.cpu.commit.membars                      413068                       # Number of memory barriers committed
+system.cpu.commit.branches                    9904424                       # Number of branches committed
+system.cpu.commit.fp_insts                      10212                       # Number of committed floating point instructions.
+system.cpu.commit.int_insts                  68617835                       # Number of committed integer instructions.
+system.cpu.commit.function_calls               995976                       # Number of function calls committed.
+system.cpu.commit.bw_lim_events               2808992                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
+system.cpu.rob.rob_reads                    245922084                       # The number of ROB reads
+system.cpu.rob.rob_writes                   212744706                       # The number of ROB writes
+system.cpu.timesIdled                         1895448                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                       260605816                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.quiesceCycles                   4591931267                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.committedInsts                    59579009                       # Number of Instructions Simulated
+system.cpu.committedOps                      76926775                       # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total              59579009                       # Number of Instructions Simulated
+system.cpu.cpi                               6.904312                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         6.904312                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.144837                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.144837                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                558200782                       # number of integer regfile reads
+system.cpu.int_regfile_writes                89400906                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                      8900                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                     2982                       # number of floating regfile writes
+system.cpu.misc_regfile_reads               135543435                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                 912729                       # number of misc regfile writes
+system.cpu.icache.replacements                1019271                       # number of replacements
+system.cpu.icache.tagsinuse                511.444719                       # Cycle average of tags in use
+system.cpu.icache.total_refs                 12598089                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                1019783                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs                  12.353696                       # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle             6290137000                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::cpu.inst     511.444719                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.998915                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.998915                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst     12598089                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        12598089                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      12598089                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         12598089                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     12598089                       # number of overall hits
+system.cpu.icache.overall_hits::total        12598089                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst      1111711                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total       1111711                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst      1111711                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total        1111711                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst      1111711                       # number of overall misses
+system.cpu.icache.overall_misses::total       1111711                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst  16369836984                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total  16369836984                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst  16369836984                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total  16369836984                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst  16369836984                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total  16369836984                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     13709800                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     13709800                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     13709800                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     13709800                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     13709800                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     13709800                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.081089                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.081089                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.081089                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.081089                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.081089                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.081089                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14724.903310                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 14724.903310                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 14724.903310                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 14724.903310                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 14724.903310                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 14724.903310                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs      2973484                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs               393                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs  7566.117048                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.icache.fast_writes                       0                       # number of fast writes performed
+system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.writebacks::writebacks        60091                       # number of writebacks
+system.cpu.icache.writebacks::total             60091                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst        91891                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total        91891                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst        91891                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total        91891                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst        91891                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total        91891                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1019820                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total      1019820                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst      1019820                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total      1019820                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst      1019820                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total      1019820                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  12187570984                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total  12187570984                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst  12187570984                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total  12187570984                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst  12187570984                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total  12187570984                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst      7292000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_uncacheable_latency::total      7292000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst      7292000                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_latency::total      7292000                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.074386                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.074386                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.074386                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.074386                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.074386                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.074386                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11950.707952                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11950.707952                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11950.707952                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 11950.707952                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11950.707952                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 11950.707952                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
+system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average overall mshr uncacheable latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
+system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.replacements                 645895                       # number of replacements
+system.cpu.dcache.tagsinuse                511.991565                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                 22075422                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                 646407                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                  34.150964                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle               49188000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data     511.991565                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.999984                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.999984                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data     14216478                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        14216478                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      7283636                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        7283636                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data       286092                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total       286092                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data       285655                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total       285655                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data      21500114                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         21500114                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     21500114                       # number of overall hits
+system.cpu.dcache.overall_hits::total        21500114                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       747655                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        747655                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      2966865                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      2966865                       # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data        13747                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total        13747                       # number of LoadLockedReq misses
+system.cpu.dcache.StoreCondReq_misses::cpu.data           13                       # number of StoreCondReq misses
+system.cpu.dcache.StoreCondReq_misses::total           13                       # number of StoreCondReq misses
+system.cpu.dcache.demand_misses::cpu.data      3714520                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        3714520                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      3714520                       # number of overall misses
+system.cpu.dcache.overall_misses::total       3714520                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  11237363500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  11237363500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 110154178240                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 110154178240                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    224042000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total    224042000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       394000                       # number of StoreCondReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::total       394000                       # number of StoreCondReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 121391541740                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 121391541740                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 121391541740                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 121391541740                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     14964133                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     14964133                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data     10250501                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total     10250501                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data       299839                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total       299839                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data       285668                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total       285668                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     25214634                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     25214634                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     25214634                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     25214634                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.049963                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.049963                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.289436                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.289436                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.045848                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.045848                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000046                       # miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::total     0.000046                       # miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.147316                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.147316                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.147316                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.147316                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15030.145589                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 15030.145589                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37128.139717                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 37128.139717                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16297.519459                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16297.519459                       # average LoadLockedReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 30307.692308                       # average StoreCondReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::total 30307.692308                       # average StoreCondReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 32680.276789                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 32680.276789                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 32680.276789                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 32680.276789                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs     17091437                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets      7607500                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs              3024                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets             268                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs  5651.930225                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 28386.194030                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.writebacks::writebacks       574932                       # number of writebacks
+system.cpu.dcache.writebacks::total            574932                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       359686                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       359686                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data      2717440                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total      2717440                       # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data         1386                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total         1386                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data      3077126                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      3077126                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      3077126                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      3077126                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data       387969                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       387969                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       249425                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       249425                       # number of WriteReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        12361                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total        12361                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data           13                       # number of StoreCondReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::total           13                       # number of StoreCondReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data       637394                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       637394                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       637394                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       637394                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   5287973500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   5287973500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   8908906437                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   8908906437                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    165672500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    165672500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       351500                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       351500                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  14196879937                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  14196879937                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  14196879937                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  14196879937                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 147151877500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 147151877500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data  42255772015                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total  42255772015                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 189407649515                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total 189407649515                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.025927                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.025927                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.024333                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.024333                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.041225                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.041225                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000046                       # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000046                       # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.025279                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.025279                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.025279                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.025279                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13629.886666                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13629.886666                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35717.776634                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35717.776634                       # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13402.839576                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13402.839576                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 27038.461538                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 27038.461538                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22273.319073                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 22273.319073                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22273.319073                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 22273.319073                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.iocache.replacements                         0                       # number of replacements
+system.iocache.tagsinuse                            0                       # Cycle average of tags in use
+system.iocache.total_refs                           0                       # Total number of references to valid blocks.
+system.iocache.sampled_refs                         0                       # Sample count of references to valid blocks.
+system.iocache.avg_refs                           nan                       # Average number of references to valid blocks.
+system.iocache.warmup_cycle                         0                       # Cycle when the warmup percentage was hit.
+system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
+system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
+system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.iocache.fast_writes                          0                       # number of fast writes performed
+system.iocache.cache_copies                         0                       # number of cache copies performed
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1296131413558                       # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 1296131413558                       # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1296131413558                       # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 1296131413558                       # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average ReadReq mshr uncacheable latency
+system.iocache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
+system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average overall mshr uncacheable latency
+system.iocache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
+system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
+system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
+system.cpu.kern.inst.quiesce                    88053                       # number of quiesce instructions executed
+
+---------- End Simulation Statistics   ----------

simulators/gem5/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simerr

@@ -0,0 +1,9 @@
+warn: Sockets disabled, not accepting terminal connections
+warn: Reading current count from inactive timer.
+warn: Sockets disabled, not accepting gdb connections
+warn: Don't know what interrupt to clear for console.
+warn: instruction 'fxsave' unimplemented
+warn: Tried to clear PCI interrupt 14
+warn: Unknown mouse command 0xe1.
+warn: instruction 'wbinvd' unimplemented
+hack: be nice to actually delete the event here

simulators/gem5/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout

@@ -0,0 +1,13 @@
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jun  4 2012 13:44:28
+gem5 started Jun  4 2012 17:03:49
+gem5 executing on zizzer
+command line: build/X86/gem5.opt -d build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing -re tests/run.py build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing
+warning: add_child('terminal'): child 'terminal' already has parent
+Global frequency set at 1000000000000 ticks per second
+info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
+      0: rtc: Real-time clock set to Sun Jan  1 00:00:00 2012
+info: Entering event queue @ 0.  Starting simulation...
+Exiting @ tick 5157514159500 because m5_exit instruction encountered

simulators/gem5/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal

@@ -0,0 +1,133 @@
+Linux version 2.6.22.9 (blackga@nacho) (gcc version 4.1.2 (Gentoo 4.1.2)) #2 Mon Oct 8 13:13:00 PDT 2007
+Command line: earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1
+BIOS-provided physical RAM map:
+ BIOS-e820: 0000000000000000 - 0000000000100000 (reserved)
+ BIOS-e820: 0000000000100000 - 0000000008000000 (usable)
+end_pfn_map = 32768
+kernel direct mapping tables up to 8000000 @ 100000-102000
+DMI 2.5 present.
+Zone PFN ranges:
+  DMA           256 ->     4096
+  DMA32        4096 ->  1048576
+  Normal    1048576 ->  1048576
+early_node_map[1] active PFN ranges
+    0:      256 ->    32768
+Intel MultiProcessor Specification v1.4
+MPTABLE: OEM ID:  MPTABLE: Product ID:  MPTABLE: APIC at: 0xFEE00000
+Processor #0 (Bootup-CPU)
+I/O APIC #1 at 0xFEC00000.
+Setting APIC routing to flat
+Processors: 1
+Allocating PCI resources starting at 10000000 (gap: 8000000:f8000000)
+Built 1 zonelists.  Total pages: 30458
+Kernel command line: earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1
+Initializing CPU#0
+PID hash table entries: 512 (order: 9, 4096 bytes)
+time.c: Detected 2000.000 MHz processor.
+Console: colour dummy device 80x25
+console handover: boot [earlyser0] -> real [ttyS0]
+Dentry cache hash table entries: 16384 (order: 5, 131072 bytes)
+Inode-cache hash table entries: 8192 (order: 4, 65536 bytes)
+Checking aperture...
+Memory: 121556k/131072k available (3742k kernel code, 8456k reserved, 1874k data, 232k init)
+Calibrating delay loop (skipped)... 3999.96 BogoMIPS preset
+Mount-cache hash table entries: 256
+CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)
+CPU: L2 Cache: 1024K (64 bytes/line)
+CPU: Fake M5 x86_64 CPU stepping 01
+ACPI: Core revision 20070126
+ACPI Exception (tbxface-0618): AE_NO_ACPI_TABLES, While loading namespace from ACPI tables [20070126]
+ACPI: Unable to load the System Description Tables
+Using local APIC timer interrupts.
+result 7812497
+Detected 7.812 MHz APIC timer.
+NET: Registered protocol family 16
+PCI: Using configuration type 1
+ACPI: Interpreter disabled.
+Linux Plug and Play Support v0.97 (c) Adam Belay
+pnp: PnP ACPI: disabled
+SCSI subsystem initialized
+usbcore: registered new interface driver usbfs
+usbcore: registered new interface driver hub
+usbcore: registered new device driver usb
+PCI: Probing PCI hardware
+PCI-GART: No AMD northbridge found.
+NET: Registered protocol family 2
+Time: tsc clocksource has been installed.
+IP route cache hash table entries: 1024 (order: 1, 8192 bytes)
+TCP established hash table entries: 4096 (order: 4, 65536 bytes)
+TCP bind hash table entries: 4096 (order: 3, 32768 bytes)
+TCP: Hash tables configured (established 4096 bind 4096)
+TCP reno registered
+Total HugeTLB memory allocated, 0
+Installing knfsd (copyright (C) 1996 okir@monad.swb.de).
+io scheduler noop registered
+io scheduler deadline registered
+io scheduler cfq registered (default)
+Real Time Clock Driver v1.12ac
+Linux agpgart interface v0.102 (c) Dave Jones
+Serial: 8250/16550 driver $Revision: 1.90 $ 4 ports, IRQ sharing disabled
+serial8250: ttyS0 at I/O 0x3f8 (irq = 4) is a 8250
+floppy0: no floppy controllers found
+RAMDISK driver initialized: 16 RAM disks of 4096K size 1024 blocksize
+loop: module loaded
+Intel(R) PRO/1000 Network Driver - version 7.3.20-k2
+Copyright (c) 1999-2006 Intel Corporation.
+e100: Intel(R) PRO/100 Network Driver, 3.5.17-k4-NAPI
+e100: Copyright(c) 1999-2006 Intel Corporation
+forcedeth.c: Reverse Engineered nForce ethernet driver. Version 0.60.
+tun: Universal TUN/TAP device driver, 1.6
+tun: (C) 1999-2004 Max Krasnyansky <maxk@qualcomm.com>
+netconsole: not configured, aborting
+Uniform Multi-Platform E-IDE driver Revision: 7.00alpha2
+ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx
+PIIX4: IDE controller at PCI slot 0000:00:04.0
+PCI: Enabling device 0000:00:04.0 (0000 -> 0001)
+PIIX4: chipset revision 0
+PIIX4: not 100% native mode: will probe irqs later
+    ide0: BM-DMA at 0x1000-0x1007, BIOS settings: hda:DMA, hdb:DMA
+    ide1: BM-DMA at 0x1008-0x100f, BIOS settings: hdc:DMA, hdd:DMA
+hda: M5 IDE Disk, ATA DISK drive
+hdb: M5 IDE Disk, ATA DISK drive
+ide0 at 0x1f0-0x1f7,0x3f6 on irq 14
+hda: max request size: 128KiB
+hda: 1048320 sectors (536 MB), CHS=1040/16/63, UDMA(33)
+ hda: hda1
+hdb: max request size: 128KiB
+hdb: 4177920 sectors (2139 MB), CHS=4144/16/63, UDMA(33)
+ hdb: unknown partition table
+megaraid cmm: 2.20.2.7 (Release Date: Sun Jul 16 00:01:03 EST 2006)
+megaraid: 2.20.5.1 (Release Date: Thu Nov 16 15:32:35 EST 2006)
+megasas: 00.00.03.10-rc5 Thu May 17 10:09:32 PDT 2007
+Fusion MPT base driver 3.04.04
+Copyright (c) 1999-2007 LSI Logic Corporation
+Fusion MPT SPI Host driver 3.04.04
+Fusion MPT SAS Host driver 3.04.04
+ieee1394: raw1394: /dev/raw1394 device initialized
+USB Universal Host Controller Interface driver v3.0
+usbcore: registered new interface driver usblp
+drivers/usb/class/usblp.c: v0.13: USB Printer Device Class driver
+Initializing USB Mass Storage driver...
+usbcore: registered new interface driver usb-storage
+USB Mass Storage support registered.
+PNP: No PS/2 controller found. Probing ports directly.
+serio: i8042 KBD port at 0x60,0x64 irq 1
+serio: i8042 AUX port at 0x60,0x64 irq 12
+mice: PS/2 mouse device common for all mice
+input: AT Translated Set 2 keyboard as /class/input/input0
+device-mapper: ioctl: 4.11.0-ioctl (2006-10-12) initialised: dm-devel@redhat.com
+input: PS/2 Generic Mouse as /class/input/input1
+usbcore: registered new interface driver usbhid
+drivers/hid/usbhid/hid-core.c: v2.6:USB HID core driver
+oprofile: using timer interrupt.
+TCP cubic registered
+NET: Registered protocol family 1
+NET: Registered protocol family 10
+IPv6 over IPv4 tunneling driver
+NET: Registered protocol family 17
+EXT2-fs warning: mounting unchecked fs, running e2fsck is recommended
+VFS: Mounted root (ext2 filesystem).
+Freeing unused kernel memory: 232k freed
+
+INIT: version 2.86 booting
+

simulators/gem5/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/ruby.stats

@@ -0,0 +1,708 @@
+
+================ Begin RubySystem Configuration Print ================
+
+RubySystem config:
+  random_seed: 1234
+  randomization: 0
+  cycle_period: 500
+  block_size_bytes: 64
+  block_size_bits: 6
+  memory_size_bytes: 134217728
+  memory_size_bits: 27
+
+Network Configuration
+---------------------
+network: SIMPLE_NETWORK
+topology: 
+
+virtual_net_0: active, unordered
+virtual_net_1: active, ordered
+virtual_net_2: active, unordered
+virtual_net_3: inactive
+virtual_net_4: inactive
+virtual_net_5: inactive
+virtual_net_6: inactive
+virtual_net_7: inactive
+virtual_net_8: inactive
+virtual_net_9: inactive
+
+
+Profiler Configuration
+----------------------
+periodic_stats_period: 1000000
+
+================ End RubySystem Configuration Print ================
+
+
+Real time: Jun/04/2012 17:25:31
+
+Profiler Stats
+--------------
+Elapsed_time_in_seconds: 842
+Elapsed_time_in_minutes: 14.0333
+Elapsed_time_in_hours: 0.233889
+Elapsed_time_in_days: 0.00974537
+
+Virtual_time_in_seconds: 842.03
+Virtual_time_in_minutes: 14.0338
+Virtual_time_in_hours:   0.233897
+Virtual_time_in_days:    0.00974572
+
+Ruby_current_time: 10609379371
+Ruby_start_time: 0
+Ruby_cycles: 10609379371
+
+mbytes_resident: 268.047
+mbytes_total: 470.199
+resident_ratio: 0.570071
+
+ruby_cycles_executed: [ 10609379372 10609379372 ]
+
+Busy Controller Counts:
+L1Cache-0:0  L1Cache-1:0  
+L2Cache-0:0  
+Directory-0:0  
+DMA-0:0  
+
+Busy Bank Count:0
+
+sequencer_requests_outstanding: [binsize: 1 max: 2 count: 187820632 average: 1.00009 | standard deviation: 0.00953306 | 0 187803562 17070 ]
+
+All Non-Zero Cycle Demand Cache Accesses
+----------------------------------------
+miss_latency: [binsize: 1 max: 171 count: 187820631 average: 3.39134 | standard deviation: 5.2186 | 0 0 0 185167359 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 968687 360 299 324 1431839 442 29 55471 396 374 169 16721 201 124 40 32 58 1 1 3 2 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12771 11 6 12 99731 53 39 34 64890 57 7 6 12 49 6 0 1 5 5 ]
+miss_latency_LD: [binsize: 1 max: 171 count: 14904214 average: 5.1415 | standard deviation: 9.3064 | 0 0 0 13521342 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 127527 49 51 45 1194807 288 8 19874 224 232 85 4872 149 99 34 25 32 1 1 2 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2618 2 2 1 16177 17 7 5 15599 14 3 1 4 10 3 0 0 1 1 ]
+miss_latency_ST: [binsize: 1 max: 171 count: 9480962 average: 5.51309 | standard deviation: 17.8961 | 0 0 0 9129497 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 28986 16 10 12 180921 99 2 14858 85 68 52 1857 24 15 2 2 7 0 0 0 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4517 5 0 4 70891 24 21 21 48866 33 3 5 5 39 3 0 1 4 4 ]
+miss_latency_IFETCH: [binsize: 1 max: 165 count: 162265044 average: 3.09464 | standard deviation: 1.92336 | 0 0 0 161451088 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 795815 273 223 254 225 27 19 28 19 28 0 0 0 0 0 0 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5358 4 4 7 11621 10 11 8 3 9 0 0 3 ]
+miss_latency_RMW_Read: [binsize: 1 max: 163 count: 492779 average: 6.1766 | standard deviation: 10.7903 | 0 0 0 426659 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10783 15 11 11 33161 10 0 12125 33 16 10 8497 16 8 2 2 6 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 227 0 0 0 868 1 0 0 315 1 1 ]
+miss_latency_Locked_RMW_Read: [binsize: 1 max: 161 count: 338816 average: 5.46921 | standard deviation: 8.08396 | 0 0 0 299957 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5576 7 4 2 22725 18 0 8586 35 30 22 1495 12 2 2 3 6 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 51 0 0 0 174 1 0 0 107 ]
+miss_latency_Locked_RMW_Write: [binsize: 1 max: 3 count: 338816 average:     3 | standard deviation: 0 | 0 0 0 338816 ]
+miss_latency_NULL: [binsize: 1 max: 171 count: 187820631 average: 3.39134 | standard deviation: 5.2186 | 0 0 0 185167359 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 968687 360 299 324 1431839 442 29 55471 396 374 169 16721 201 124 40 32 58 1 1 3 2 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12771 11 6 12 99731 53 39 34 64890 57 7 6 12 49 6 0 1 5 5 ]
+miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+imcomplete_wCC_Times: 0
+miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+imcomplete_dir_Times: 0
+miss_latency_LD_NULL: [binsize: 1 max: 171 count: 14904214 average: 5.1415 | standard deviation: 9.3064 | 0 0 0 13521342 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 127527 49 51 45 1194807 288 8 19874 224 232 85 4872 149 99 34 25 32 1 1 2 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2618 2 2 1 16177 17 7 5 15599 14 3 1 4 10 3 0 0 1 1 ]
+miss_latency_ST_NULL: [binsize: 1 max: 171 count: 9480962 average: 5.51309 | standard deviation: 17.8961 | 0 0 0 9129497 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 28986 16 10 12 180921 99 2 14858 85 68 52 1857 24 15 2 2 7 0 0 0 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4517 5 0 4 70891 24 21 21 48866 33 3 5 5 39 3 0 1 4 4 ]
+miss_latency_IFETCH_NULL: [binsize: 1 max: 165 count: 162265044 average: 3.09464 | standard deviation: 1.92336 | 0 0 0 161451088 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 795815 273 223 254 225 27 19 28 19 28 0 0 0 0 0 0 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5358 4 4 7 11621 10 11 8 3 9 0 0 3 ]
+miss_latency_RMW_Read_NULL: [binsize: 1 max: 163 count: 492779 average: 6.1766 | standard deviation: 10.7903 | 0 0 0 426659 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10783 15 11 11 33161 10 0 12125 33 16 10 8497 16 8 2 2 6 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 227 0 0 0 868 1 0 0 315 1 1 ]
+miss_latency_Locked_RMW_Read_NULL: [binsize: 1 max: 161 count: 338816 average: 5.46921 | standard deviation: 8.08396 | 0 0 0 299957 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5576 7 4 2 22725 18 0 8586 35 30 22 1495 12 2 2 3 6 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 51 0 0 0 174 1 0 0 107 ]
+miss_latency_Locked_RMW_Write_NULL: [binsize: 1 max: 3 count: 338816 average:     3 | standard deviation: 0 | 0 0 0 338816 ]
+
+All Non-Zero Cycle SW Prefetch Requests
+------------------------------------
+prefetch_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+prefetch_latency_L2Miss:[binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+Request vs. RubySystem State Profile
+--------------------------------
+
+
+filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+Message Delayed Cycles
+----------------------
+Total_delay_cycles: [binsize: 1 max: 13 count: 10850974 average: 0.59462 | standard deviation: 1.42374 | 9237583 1029 657 892 1609097 1059 106 119 110 244 9 6 16 47 ]
+Total_nonPF_delay_cycles: [binsize: 1 max: 9 count: 4764816 average: 0.0223746 | standard deviation: 0.296857 | 4737436 520 425 679 25631 106 3 1 10 5 ]
+  virtual_network_0_delay_cycles: [binsize: 1 max: 13 count: 6086158 average: 1.04263 | standard deviation: 1.75725 | 4500147 509 232 213 1583466 953 103 118 100 239 9 6 16 47 ]
+  virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+  virtual_network_2_delay_cycles: [binsize: 1 max: 9 count: 83533 average: 0.0149761 | standard deviation: 0.225696 | 83067 123 97 98 116 28 0 0 0 4 ]
+  virtual_network_3_delay_cycles: [binsize: 1 max: 9 count: 4681283 average: 0.0225067 | standard deviation: 0.297971 | 4654369 397 328 581 25515 78 3 1 10 1 ]
+  virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+  virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+  virtual_network_6_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+  virtual_network_7_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+  virtual_network_8_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+  virtual_network_9_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+Resource Usage
+--------------
+page_size: 4096
+user_time: 841
+system_time: 0
+page_reclaims: 69674
+page_faults: 18
+swaps: 0
+block_inputs: 16056
+block_outputs: 408
+
+Network Stats
+-------------
+
+total_msg_count_Control: 8492901 67943208
+total_msg_count_Request_Control: 248654 1989232
+total_msg_count_Response_Data: 8788194 632749968
+total_msg_count_Response_Control: 10854297 86834376
+total_msg_count_Writeback_Data: 4753752 342270144
+total_msg_count_Writeback_Control: 282753 2262024
+total_msgs: 33420551 total_bytes: 1134048952
+
+switch_0_inlinks: 2
+switch_0_outlinks: 2
+links_utilized_percent_switch_0: 0.0323999
+  links_utilized_percent_switch_0_link_0: 0.0382499 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_0_link_1: 0.02655 bw: 16000 base_latency: 1
+
+  outgoing_messages_switch_0_link_0_Request_Control: 42688 341504 [ 42688 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_0_Response_Data: 842729 60676488 [ 0 842729 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_0_Response_Control: 488898 3911184 [ 0 488898 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_1_Control: 855066 6840528 [ 855066 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_1_Response_Data: 40424 2910528 [ 0 40424 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_1_Response_Control: 517774 4142192 [ 0 16296 501478 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_1_Writeback_Data: 429162 30899664 [ 429108 54 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_1_Writeback_Control: 34458 275664 [ 34458 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+
+switch_1_inlinks: 2
+switch_1_outlinks: 2
+links_utilized_percent_switch_1: 0.0735359
+  links_utilized_percent_switch_1_link_0: 0.0818749 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_1_link_1: 0.0651969 bw: 16000 base_latency: 1
+
+  outgoing_messages_switch_1_link_0_Request_Control: 40845 326760 [ 40845 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_0_Response_Data: 1788501 128772072 [ 0 1788501 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_0_Response_Control: 1235479 9883832 [ 0 1235479 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_1_Control: 1798206 14385648 [ 1798206 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_1_Response_Data: 34071 2453112 [ 0 34071 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_1_Response_Control: 1270539 10164312 [ 0 17798 1252741 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_1_Writeback_Data: 1155422 83190384 [ 1155308 114 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_1_Writeback_Control: 59793 478344 [ 59793 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+
+switch_2_inlinks: 2
+switch_2_outlinks: 2
+links_utilized_percent_switch_2: 0.110241
+  links_utilized_percent_switch_2_link_0: 0.0976111 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_2_link_1: 0.122871 bw: 16000 base_latency: 1
+
+  outgoing_messages_switch_2_link_0_Control: 2653272 21226176 [ 2653272 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_0_Response_Data: 202919 14610168 [ 0 202919 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_0_Response_Control: 1876808 15014464 [ 0 122589 1754219 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_0_Writeback_Data: 1584584 114090048 [ 1584416 168 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_0_Writeback_Control: 94251 754008 [ 94251 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_1_Control: 177695 1421560 [ 177695 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_1_Request_Control: 81588 652704 [ 81588 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_1_Response_Data: 2677208 192758976 [ 0 2677208 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_1_Response_Control: 1717623 13740984 [ 0 1717623 0 0 0 0 0 0 0 0 ] base_latency: 1
+
+switch_3_inlinks: 2
+switch_3_outlinks: 2
+links_utilized_percent_switch_3: 0.00651138
+  links_utilized_percent_switch_3_link_0: 0.00495717 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_3_link_1: 0.00806559 bw: 16000 base_latency: 1
+
+  outgoing_messages_switch_3_link_0_Control: 177695 1421560 [ 177695 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_0_Response_Data: 95249 6857928 [ 0 95249 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_0_Response_Control: 16914 135312 [ 0 16914 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_1_Response_Data: 177695 12794040 [ 0 177695 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_1_Response_Control: 112163 897304 [ 0 112163 0 0 0 0 0 0 0 0 ] base_latency: 1
+
+switch_4_inlinks: 2
+switch_4_outlinks: 2
+links_utilized_percent_switch_4: 0
+  links_utilized_percent_switch_4_link_0: 0 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_4_link_1: 0 bw: 16000 base_latency: 1
+
+
+switch_5_inlinks: 5
+switch_5_outlinks: 5
+links_utilized_percent_switch_5: 0.0445386
+  links_utilized_percent_switch_5_link_0: 0.0382499 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_5_link_1: 0.0818749 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_5_link_2: 0.0976111 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_5_link_3: 0.00495717 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_5_link_4: 0 bw: 16000 base_latency: 1
+
+  outgoing_messages_switch_5_link_0_Request_Control: 42688 341504 [ 42688 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_5_link_0_Response_Data: 842729 60676488 [ 0 842729 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_5_link_0_Response_Control: 488898 3911184 [ 0 488898 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_5_link_1_Request_Control: 40845 326760 [ 40845 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_5_link_1_Response_Data: 1788501 128772072 [ 0 1788501 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_5_link_1_Response_Control: 1235479 9883832 [ 0 1235479 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_5_link_2_Control: 2653272 21226176 [ 2653272 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_5_link_2_Response_Data: 202919 14610168 [ 0 202919 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_5_link_2_Response_Control: 1876808 15014464 [ 0 122589 1754219 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_5_link_2_Writeback_Data: 1584584 114090048 [ 1584416 168 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_5_link_2_Writeback_Control: 94251 754008 [ 94251 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_5_link_3_Control: 177695 1421560 [ 177695 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_5_link_3_Response_Data: 95249 6857928 [ 0 95249 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_5_link_3_Response_Control: 16914 135312 [ 0 16914 0 0 0 0 0 0 0 0 ] base_latency: 1
+
+Cache Stats: system.l1_cntrl0.L1IcacheMemory
+  system.l1_cntrl0.L1IcacheMemory_total_misses: 326846
+  system.l1_cntrl0.L1IcacheMemory_total_demand_misses: 326846
+  system.l1_cntrl0.L1IcacheMemory_total_prefetches: 0
+  system.l1_cntrl0.L1IcacheMemory_total_sw_prefetches: 0
+  system.l1_cntrl0.L1IcacheMemory_total_hw_prefetches: 0
+
+  system.l1_cntrl0.L1IcacheMemory_request_type_IFETCH:   100%
+
+  system.l1_cntrl0.L1IcacheMemory_access_mode_type_Supervisor:   326846    100%
+
+Cache Stats: system.l1_cntrl0.L1DcacheMemory
+  system.l1_cntrl0.L1DcacheMemory_total_misses: 528220
+  system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 528220
+  system.l1_cntrl0.L1DcacheMemory_total_prefetches: 0
+  system.l1_cntrl0.L1DcacheMemory_total_sw_prefetches: 0
+  system.l1_cntrl0.L1DcacheMemory_total_hw_prefetches: 0
+
+  system.l1_cntrl0.L1DcacheMemory_request_type_LD:   54.1774%
+  system.l1_cntrl0.L1DcacheMemory_request_type_ST:   45.8226%
+
+  system.l1_cntrl0.L1DcacheMemory_access_mode_type_Supervisor:   528220    100%
+
+ --- L1Cache ---
+ - Event Counts -
+Load [6224073 8680141 ] 14904214
+Ifetch [103471616 58793435 ] 162265051
+Store [5279560 5371813 ] 10651373
+Inv [16350 17912 ] 34262
+L1_Replacement [827635 1770998 ] 2598633
+Fwd_GETX [12252 11795 ] 24047
+Fwd_GETS [14082 11138 ] 25220
+Fwd_GET_INSTR [4 0 ] 4
+Data [658 968 ] 1626
+Data_Exclusive [248296 1024255 ] 1272551
+DataS_fromL1 [11138 14086 ] 25224
+Data_all_Acks [582637 749192 ] 1331829
+Ack [12337 9705 ] 22042
+Ack_all [12995 10673 ] 23668
+WB_Ack [463566 1215101 ] 1678667
+
+ - Transitions -
+NP  Load [277889 1086402 ] 1364291
+NP  Ifetch [326723 486562 ] 813285
+NP  Store [224047 199057 ] 423104
+NP  Inv [5639 4132 ] 9771
+NP  L1_Replacement [0 0 ] 0
+
+I  Load [8287 10294 ] 18581
+I  Ifetch [123 548 ] 671
+I  Store [5660 5638 ] 11298
+I  Inv [0 0 ] 0
+I  L1_Replacement [8798 9094 ] 17892
+
+S  Load [577238 501390 ] 1078628
+S  Ifetch [103144768 58306320 ] 161451088
+S  Store [12337 9705 ] 22042
+S  Inv [10590 13636 ] 24226
+S  L1_Replacement [355271 546803 ] 902074
+
+E  Load [1142385 2670000 ] 3812385
+E  Ifetch [0 0 ] 0
+E  Store [81265 85104 ] 166369
+E  Inv [67 30 ] 97
+E  L1_Replacement [165622 937435 ] 1103057
+E  Fwd_GETX [352 103 ] 455
+E  Fwd_GETS [877 1394 ] 2271
+E  Fwd_GET_INSTR [0 0 ] 0
+
+M  Load [4218274 4412055 ] 8630329
+M  Ifetch [0 0 ] 0
+M  Store [4956251 5072309 ] 10028560
+M  Inv [54 114 ] 168
+M  L1_Replacement [297944 277666 ] 575610
+M  Fwd_GETX [11900 11692 ] 23592
+M  Fwd_GETS [13205 9744 ] 22949
+M  Fwd_GET_INSTR [4 0 ] 4
+
+IS  Load [0 0 ] 0
+IS  Ifetch [0 0 ] 0
+IS  Store [0 0 ] 0
+IS  Inv [0 0 ] 0
+IS  L1_Replacement [0 0 ] 0
+IS  Data_Exclusive [248296 1024255 ] 1272551
+IS  DataS_fromL1 [11138 14086 ] 25224
+IS  Data_all_Acks [353588 545465 ] 899053
+
+IM  Load [0 0 ] 0
+IM  Ifetch [0 0 ] 0
+IM  Store [0 0 ] 0
+IM  Inv [0 0 ] 0
+IM  L1_Replacement [0 0 ] 0
+IM  Data [658 968 ] 1626
+IM  Data_all_Acks [229049 203727 ] 432776
+IM  Ack [0 0 ] 0
+
+SM  Load [0 0 ] 0
+SM  Ifetch [0 0 ] 0
+SM  Store [0 0 ] 0
+SM  Inv [0 0 ] 0
+SM  L1_Replacement [0 0 ] 0
+SM  Ack [12337 9705 ] 22042
+SM  Ack_all [12995 10673 ] 23668
+
+IS_I  Load [0 0 ] 0
+IS_I  Ifetch [0 0 ] 0
+IS_I  Store [0 0 ] 0
+IS_I  Inv [0 0 ] 0
+IS_I  L1_Replacement [0 0 ] 0
+IS_I  Data_Exclusive [0 0 ] 0
+IS_I  DataS_fromL1 [0 0 ] 0
+IS_I  Data_all_Acks [0 0 ] 0
+
+M_I  Load [0 0 ] 0
+M_I  Ifetch [2 5 ] 7
+M_I  Store [0 0 ] 0
+M_I  Inv [0 0 ] 0
+M_I  L1_Replacement [0 0 ] 0
+M_I  Fwd_GETX [0 0 ] 0
+M_I  Fwd_GETS [0 0 ] 0
+M_I  Fwd_GET_INSTR [0 0 ] 0
+M_I  WB_Ack [463566 1215101 ] 1678667
+
+SINK_WB_ACK  Load [0 0 ] 0
+SINK_WB_ACK  Ifetch [0 0 ] 0
+SINK_WB_ACK  Store [0 0 ] 0
+SINK_WB_ACK  Inv [0 0 ] 0
+SINK_WB_ACK  L1_Replacement [0 0 ] 0
+SINK_WB_ACK  WB_Ack [0 0 ] 0
+
+Cache Stats: system.l1_cntrl1.L1IcacheMemory
+  system.l1_cntrl1.L1IcacheMemory_total_misses: 487110
+  system.l1_cntrl1.L1IcacheMemory_total_demand_misses: 487110
+  system.l1_cntrl1.L1IcacheMemory_total_prefetches: 0
+  system.l1_cntrl1.L1IcacheMemory_total_sw_prefetches: 0
+  system.l1_cntrl1.L1IcacheMemory_total_hw_prefetches: 0
+
+  system.l1_cntrl1.L1IcacheMemory_request_type_IFETCH:   100%
+
+  system.l1_cntrl1.L1IcacheMemory_access_mode_type_Supervisor:   487110    100%
+
+Cache Stats: system.l1_cntrl1.L1DcacheMemory
+  system.l1_cntrl1.L1DcacheMemory_total_misses: 1311096
+  system.l1_cntrl1.L1DcacheMemory_total_demand_misses: 1311096
+  system.l1_cntrl1.L1DcacheMemory_total_prefetches: 0
+  system.l1_cntrl1.L1DcacheMemory_total_sw_prefetches: 0
+  system.l1_cntrl1.L1DcacheMemory_total_hw_prefetches: 0
+
+  system.l1_cntrl1.L1DcacheMemory_request_type_LD:   83.6473%
+  system.l1_cntrl1.L1DcacheMemory_request_type_ST:   16.3527%
+
+  system.l1_cntrl1.L1DcacheMemory_access_mode_type_Supervisor:   1311096    100%
+
+Cache Stats: system.l2_cntrl0.L2cacheMemory
+  system.l2_cntrl0.L2cacheMemory_total_misses: 226966
+  system.l2_cntrl0.L2cacheMemory_total_demand_misses: 226966
+  system.l2_cntrl0.L2cacheMemory_total_prefetches: 0
+  system.l2_cntrl0.L2cacheMemory_total_sw_prefetches: 0
+  system.l2_cntrl0.L2cacheMemory_total_hw_prefetches: 0
+
+  system.l2_cntrl0.L2cacheMemory_request_type_GETS:   26.2969%
+  system.l2_cntrl0.L2cacheMemory_request_type_GET_INSTR:   7.50861%
+  system.l2_cntrl0.L2cacheMemory_request_type_GETX:   66.1945%
+
+  system.l2_cntrl0.L2cacheMemory_access_mode_type_Supervisor:   226966    100%
+
+ --- L2Cache ---
+ - Event Counts -
+L1_GET_INSTR [813956 ] 813956
+L1_GETS [1383116 ] 1383116
+L1_GETX [434406 ] 434406
+L1_UPGRADE [22042 ] 22042
+L1_PUTX [1678667 ] 1678667
+L1_PUTX_old [0 ] 0
+Fwd_L1_GETX [0 ] 0
+Fwd_L1_GETS [0 ] 0
+Fwd_L1_GET_INSTR [0 ] 0
+L2_Replacement [95206 ] 95206
+L2_Replacement_clean [16957 ] 16957
+Mem_Data [177695 ] 177695
+Mem_Ack [112163 ] 112163
+WB_Data [24702 ] 24702
+WB_Data_clean [690 ] 690
+Ack [1945 ] 1945
+Ack_all [8481 ] 8481
+Unblock [25224 ] 25224
+Unblock_Cancel [0 ] 0
+Exclusive_Unblock [1728995 ] 1728995
+MEM_Inv [0 ] 0
+
+ - Transitions -
+NP  L1_GET_INSTR [17038 ] 17038
+NP  L1_GETS [34465 ] 34465
+NP  L1_GETX [126192 ] 126192
+NP  L1_PUTX [0 ] 0
+NP  L1_PUTX_old [0 ] 0
+
+SS  L1_GET_INSTR [796726 ] 796726
+SS  L1_GETS [85101 ] 85101
+SS  L1_GETX [1832 ] 1832
+SS  L1_UPGRADE [22042 ] 22042
+SS  L1_PUTX [0 ] 0
+SS  L1_PUTX_old [0 ] 0
+SS  L2_Replacement [266 ] 266
+SS  L2_Replacement_clean [8118 ] 8118
+SS  MEM_Inv [0 ] 0
+
+M  L1_GET_INSTR [188 ] 188
+M  L1_GETS [1238086 ] 1238086
+M  L1_GETX [282331 ] 282331
+M  L1_PUTX [0 ] 0
+M  L1_PUTX_old [0 ] 0
+M  L2_Replacement [94758 ] 94758
+M  L2_Replacement_clean [8756 ] 8756
+M  MEM_Inv [0 ] 0
+
+MT  L1_GET_INSTR [4 ] 4
+MT  L1_GETS [25220 ] 25220
+MT  L1_GETX [24047 ] 24047
+MT  L1_PUTX [1678667 ] 1678667
+MT  L1_PUTX_old [0 ] 0
+MT  L2_Replacement [182 ] 182
+MT  L2_Replacement_clean [83 ] 83
+MT  MEM_Inv [0 ] 0
+
+M_I  L1_GET_INSTR [0 ] 0
+M_I  L1_GETS [0 ] 0
+M_I  L1_GETX [0 ] 0
+M_I  L1_UPGRADE [0 ] 0
+M_I  L1_PUTX [0 ] 0
+M_I  L1_PUTX_old [0 ] 0
+M_I  Mem_Ack [112163 ] 112163
+M_I  MEM_Inv [0 ] 0
+
+MT_I  L1_GET_INSTR [0 ] 0
+MT_I  L1_GETS [0 ] 0
+MT_I  L1_GETX [0 ] 0
+MT_I  L1_UPGRADE [0 ] 0
+MT_I  L1_PUTX [0 ] 0
+MT_I  L1_PUTX_old [0 ] 0
+MT_I  WB_Data [125 ] 125
+MT_I  WB_Data_clean [0 ] 0
+MT_I  Ack_all [57 ] 57
+MT_I  MEM_Inv [0 ] 0
+
+MCT_I  L1_GET_INSTR [0 ] 0
+MCT_I  L1_GETS [0 ] 0
+MCT_I  L1_GETX [0 ] 0
+MCT_I  L1_UPGRADE [0 ] 0
+MCT_I  L1_PUTX [0 ] 0
+MCT_I  L1_PUTX_old [0 ] 0
+MCT_I  WB_Data [43 ] 43
+MCT_I  WB_Data_clean [0 ] 0
+MCT_I  Ack_all [40 ] 40
+
+I_I  L1_GET_INSTR [0 ] 0
+I_I  L1_GETS [0 ] 0
+I_I  L1_GETX [0 ] 0
+I_I  L1_UPGRADE [0 ] 0
+I_I  L1_PUTX [0 ] 0
+I_I  L1_PUTX_old [0 ] 0
+I_I  Ack [1679 ] 1679
+I_I  Ack_all [8118 ] 8118
+
+S_I  L1_GET_INSTR [0 ] 0
+S_I  L1_GETS [0 ] 0
+S_I  L1_GETX [0 ] 0
+S_I  L1_UPGRADE [0 ] 0
+S_I  L1_PUTX [0 ] 0
+S_I  L1_PUTX_old [0 ] 0
+S_I  Ack [266 ] 266
+S_I  Ack_all [266 ] 266
+S_I  MEM_Inv [0 ] 0
+
+ISS  L1_GET_INSTR [0 ] 0
+ISS  L1_GETS [0 ] 0
+ISS  L1_GETX [0 ] 0
+ISS  L1_PUTX [0 ] 0
+ISS  L1_PUTX_old [0 ] 0
+ISS  L2_Replacement [0 ] 0
+ISS  L2_Replacement_clean [0 ] 0
+ISS  Mem_Data [34465 ] 34465
+ISS  MEM_Inv [0 ] 0
+
+IS  L1_GET_INSTR [0 ] 0
+IS  L1_GETS [0 ] 0
+IS  L1_GETX [0 ] 0
+IS  L1_PUTX [0 ] 0
+IS  L1_PUTX_old [0 ] 0
+IS  L2_Replacement [0 ] 0
+IS  L2_Replacement_clean [0 ] 0
+IS  Mem_Data [17038 ] 17038
+IS  MEM_Inv [0 ] 0
+
+IM  L1_GET_INSTR [0 ] 0
+IM  L1_GETS [0 ] 0
+IM  L1_GETX [0 ] 0
+IM  L1_PUTX [0 ] 0
+IM  L1_PUTX_old [0 ] 0
+IM  L2_Replacement [0 ] 0
+IM  L2_Replacement_clean [0 ] 0
+IM  Mem_Data [126192 ] 126192
+IM  MEM_Inv [0 ] 0
+
+SS_MB  L1_GET_INSTR [0 ] 0
+SS_MB  L1_GETS [174 ] 174
+SS_MB  L1_GETX [0 ] 0
+SS_MB  L1_UPGRADE [0 ] 0
+SS_MB  L1_PUTX [0 ] 0
+SS_MB  L1_PUTX_old [0 ] 0
+SS_MB  L2_Replacement [0 ] 0
+SS_MB  L2_Replacement_clean [0 ] 0
+SS_MB  Unblock_Cancel [0 ] 0
+SS_MB  Exclusive_Unblock [23874 ] 23874
+SS_MB  MEM_Inv [0 ] 0
+
+MT_MB  L1_GET_INSTR [0 ] 0
+MT_MB  L1_GETS [70 ] 70
+MT_MB  L1_GETX [4 ] 4
+MT_MB  L1_UPGRADE [0 ] 0
+MT_MB  L1_PUTX [0 ] 0
+MT_MB  L1_PUTX_old [0 ] 0
+MT_MB  L2_Replacement [0 ] 0
+MT_MB  L2_Replacement_clean [0 ] 0
+MT_MB  Unblock_Cancel [0 ] 0
+MT_MB  Exclusive_Unblock [1705121 ] 1705121
+MT_MB  MEM_Inv [0 ] 0
+
+M_MB  L1_GET_INSTR [0 ] 0
+M_MB  L1_GETS [0 ] 0
+M_MB  L1_GETX [0 ] 0
+M_MB  L1_UPGRADE [0 ] 0
+M_MB  L1_PUTX [0 ] 0
+M_MB  L1_PUTX_old [0 ] 0
+M_MB  L2_Replacement [0 ] 0
+M_MB  L2_Replacement_clean [0 ] 0
+M_MB  Exclusive_Unblock [0 ] 0
+M_MB  MEM_Inv [0 ] 0
+
+MT_IIB  L1_GET_INSTR [0 ] 0
+MT_IIB  L1_GETS [0 ] 0
+MT_IIB  L1_GETX [0 ] 0
+MT_IIB  L1_UPGRADE [0 ] 0
+MT_IIB  L1_PUTX [0 ] 0
+MT_IIB  L1_PUTX_old [0 ] 0
+MT_IIB  L2_Replacement [0 ] 0
+MT_IIB  L2_Replacement_clean [0 ] 0
+MT_IIB  WB_Data [24523 ] 24523
+MT_IIB  WB_Data_clean [689 ] 689
+MT_IIB  Unblock [12 ] 12
+MT_IIB  MEM_Inv [0 ] 0
+
+MT_IB  L1_GET_INSTR [0 ] 0
+MT_IB  L1_GETS [0 ] 0
+MT_IB  L1_GETX [0 ] 0
+MT_IB  L1_UPGRADE [0 ] 0
+MT_IB  L1_PUTX [0 ] 0
+MT_IB  L1_PUTX_old [0 ] 0
+MT_IB  L2_Replacement [0 ] 0
+MT_IB  L2_Replacement_clean [0 ] 0
+MT_IB  WB_Data [11 ] 11
+MT_IB  WB_Data_clean [1 ] 1
+MT_IB  Unblock_Cancel [0 ] 0
+MT_IB  MEM_Inv [0 ] 0
+
+MT_SB  L1_GET_INSTR [0 ] 0
+MT_SB  L1_GETS [0 ] 0
+MT_SB  L1_GETX [0 ] 0
+MT_SB  L1_UPGRADE [0 ] 0
+MT_SB  L1_PUTX [0 ] 0
+MT_SB  L1_PUTX_old [0 ] 0
+MT_SB  L2_Replacement [0 ] 0
+MT_SB  L2_Replacement_clean [0 ] 0
+MT_SB  Unblock [25212 ] 25212
+MT_SB  MEM_Inv [0 ] 0
+
+Memory controller: system.dir_cntrl0.memBuffer:
+  memory_total_requests: 272944
+  memory_reads: 177695
+  memory_writes: 95249
+  memory_refreshes: 4108449
+  memory_total_request_delays: 25207
+  memory_delays_per_request: 0.0923523
+  memory_delays_in_input_queue: 7
+  memory_delays_behind_head_of_bank_queue: 0
+  memory_delays_stalled_at_head_of_bank_queue: 25200
+  memory_stalls_for_bank_busy: 11193
+  memory_stalls_for_random_busy: 0
+  memory_stalls_for_anti_starvation: 0
+  memory_stalls_for_arbitration: 2202
+  memory_stalls_for_bus: 11804
+  memory_stalls_for_tfaw: 0
+  memory_stalls_for_read_write_turnaround: 0
+  memory_stalls_for_read_read_turnaround: 1
+  accesses_per_bank: 8796  9232  8713  8487  8759  8199  8936  8313  8486  8359  8337  9440  8301  8128  8185  7202  8172  8248  8224  8141  8420  8367  8241  8178  8468  8442  8634  9202  9127  8950  10053  8204  
+
+ --- Directory ---
+ - Event Counts -
+Fetch [177695 ] 177695
+Data [95249 ] 95249
+Memory_Data [177695 ] 177695
+Memory_Ack [95249 ] 95249
+DMA_READ [0 ] 0
+DMA_WRITE [0 ] 0
+CleanReplacement [16914 ] 16914
+
+ - Transitions -
+I  Fetch [177695 ] 177695
+I  DMA_READ [0 ] 0
+I  DMA_WRITE [0 ] 0
+
+ID  Fetch [0 ] 0
+ID  Data [0 ] 0
+ID  Memory_Data [0 ] 0
+ID  DMA_READ [0 ] 0
+ID  DMA_WRITE [0 ] 0
+
+ID_W  Fetch [0 ] 0
+ID_W  Data [0 ] 0
+ID_W  Memory_Ack [0 ] 0
+ID_W  DMA_READ [0 ] 0
+ID_W  DMA_WRITE [0 ] 0
+
+M  Data [95249 ] 95249
+M  DMA_READ [0 ] 0
+M  DMA_WRITE [0 ] 0
+M  CleanReplacement [16914 ] 16914
+
+IM  Fetch [0 ] 0
+IM  Data [0 ] 0
+IM  Memory_Data [177695 ] 177695
+IM  DMA_READ [0 ] 0
+IM  DMA_WRITE [0 ] 0
+
+MI  Fetch [0 ] 0
+MI  Data [0 ] 0
+MI  Memory_Ack [95249 ] 95249
+MI  DMA_READ [0 ] 0
+MI  DMA_WRITE [0 ] 0
+
+M_DRD  Data [0 ] 0
+M_DRD  DMA_READ [0 ] 0
+M_DRD  DMA_WRITE [0 ] 0
+
+M_DRDI  Fetch [0 ] 0
+M_DRDI  Data [0 ] 0
+M_DRDI  Memory_Ack [0 ] 0
+M_DRDI  DMA_READ [0 ] 0
+M_DRDI  DMA_WRITE [0 ] 0
+
+M_DWR  Data [0 ] 0
+M_DWR  DMA_READ [0 ] 0
+M_DWR  DMA_WRITE [0 ] 0
+
+M_DWRI  Fetch [0 ] 0
+M_DWRI  Data [0 ] 0
+M_DWRI  Memory_Ack [0 ] 0
+M_DWRI  DMA_READ [0 ] 0
+M_DWRI  DMA_WRITE [0 ] 0
+
+ --- DMA ---
+ - Event Counts -
+ReadRequest [0 ] 0
+WriteRequest [0 ] 0
+Data [0 ] 0
+Ack [0 ] 0
+
+ - Transitions -
+READY  ReadRequest [0 ] 0
+READY  WriteRequest [0 ] 0
+
+BUSY_RD  Data [0 ] 0
+
+BUSY_WR  Ack [0 ] 0
+

simulators/gem5/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simerr

@@ -0,0 +1,11 @@
+warn: Sockets disabled, not accepting terminal connections
+warn: Reading current count from inactive timer.
+warn: Sockets disabled, not accepting gdb connections
+warn: Don't know what interrupt to clear for console.
+warn: instruction 'fxsave' unimplemented
+warn: instruction 'wbinvd' unimplemented
+warn: instruction 'wbinvd' unimplemented
+hack: Assuming logical destinations are 1 << id.
+warn: Tried to clear PCI interrupt 14
+warn: Unknown mouse command 0xe1.
+hack: be nice to actually delete the event here

simulators/gem5/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simout

@@ -0,0 +1,13 @@
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jun  4 2012 13:44:12
+gem5 started Jun  4 2012 17:11:29
+gem5 executing on zizzer
+command line: build/X86_MESI_CMP_directory/gem5.opt -d build/X86_MESI_CMP_directory/tests/opt/long/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory -re tests/run.py build/X86_MESI_CMP_directory/tests/opt/long/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory
+warning: add_child('terminal'): child 'terminal' already has parent
+Global frequency set at 1000000000000 ticks per second
+info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9.smp
+      0: rtc: Real-time clock set to Sun Jan  1 00:00:00 2012
+info: Entering event queue @ 0.  Starting simulation...
+Exiting @ tick 5304689685500 because m5_exit instruction encountered

simulators/gem5/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt

@@ -0,0 +1,136 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds                                  5.304690                       # Number of seconds simulated
+sim_ticks                                5304689685500                       # Number of ticks simulated
+final_tick                               5304689685500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                 163049                       # Simulator instruction rate (inst/s)
+host_op_rate                                   333085                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             6301127704                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 481488                       # Number of bytes of host memory used
+host_seconds                                   841.86                       # Real time elapsed on the host
+sim_insts                                   137264752                       # Number of instructions simulated
+sim_ops                                     280412254                       # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::pc.south_bridge.ide        35144                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.dtb.walker       126800                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker        64416                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst        827772912                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data         39626426                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker       100784                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.itb.walker        45696                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst        470347440                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data         53905938                       # Number of bytes read from this memory
+system.physmem.bytes_read::total           1392025556                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst    827772912                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst    470347440                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total      1298120352                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::pc.south_bridge.ide      2991104                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu0.itb.walker           16                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu0.data      32173132                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu1.data      35738580                       # Number of bytes written to this memory
+system.physmem.bytes_written::total          70902832                       # Number of bytes written to this memory
+system.physmem.num_reads::pc.south_bridge.ide          809                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.dtb.walker        15850                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker         8052                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst         103471614                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data           6642662                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker        12598                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.itb.walker         5712                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst          58793430                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data           9050935                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total             178001662                       # Number of read requests responded to by this memory
+system.physmem.num_writes::pc.south_bridge.ide        46736                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu0.itb.walker            2                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu0.data          4837067                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu1.data          4982709                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total              9866514                       # Number of write requests responded to by this memory
+system.physmem.bw_read::pc.south_bridge.ide         6625                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.dtb.walker         23903                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker         12143                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst           156045492                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data             7470074                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker         18999                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.itb.walker          8614                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst            88666344                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data            10161940                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               262414135                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst      156045492                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst       88666344                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total          244711836                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::pc.south_bridge.ide       563860                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.itb.walker            3                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data            6065036                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu1.data            6737167                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               13366066                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::pc.south_bridge.ide       570485                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker        23903                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker        12146                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst          156045492                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data           13535110                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker        18999                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.itb.walker         8614                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst           88666344                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data           16899107                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              275780201                       # Total bandwidth to/from this memory (bytes/s)
+system.pc.south_bridge.ide.disks0.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
+system.pc.south_bridge.ide.disks0.dma_read_bytes        32768                       # Number of bytes transfered via DMA reads (not PRD).
+system.pc.south_bridge.ide.disks0.dma_read_txs           30                       # Number of DMA read transactions (not PRD).
+system.pc.south_bridge.ide.disks0.dma_write_full_pages          693                       # Number of full page size DMA writes.
+system.pc.south_bridge.ide.disks0.dma_write_bytes      2987008                       # Number of bytes transfered via DMA writes.
+system.pc.south_bridge.ide.disks0.dma_write_txs          813                       # Number of DMA write transactions.
+system.pc.south_bridge.ide.disks1.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
+system.pc.south_bridge.ide.disks1.dma_read_bytes            0                       # Number of bytes transfered via DMA reads (not PRD).
+system.pc.south_bridge.ide.disks1.dma_read_txs            0                       # Number of DMA read transactions (not PRD).
+system.pc.south_bridge.ide.disks1.dma_write_full_pages            1                       # Number of full page size DMA writes.
+system.pc.south_bridge.ide.disks1.dma_write_bytes         4096                       # Number of bytes transfered via DMA writes.
+system.pc.south_bridge.ide.disks1.dma_write_txs            1                       # Number of DMA write transactions.
+system.cpu0.numCycles                     10608177450                       # number of cpu cycles simulated
+system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
+system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
+system.cpu0.committedInsts                   88690468                       # Number of instructions committed
+system.cpu0.committedOps                    187060545                       # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses            168469813                       # Number of integer alu accesses
+system.cpu0.num_fp_alu_accesses                     0                       # Number of float alu accesses
+system.cpu0.num_func_calls                          0                       # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts     17923925                       # number of instructions that are conditional controls
+system.cpu0.num_int_insts                   168469813                       # number of integer instructions
+system.cpu0.num_fp_insts                            0                       # number of float instructions
+system.cpu0.num_int_register_reads          517963630                       # number of times the integer registers were read
+system.cpu0.num_int_register_writes         280483339                       # number of times the integer registers were written
+system.cpu0.num_fp_register_reads                   0                       # number of times the floating registers were read
+system.cpu0.num_fp_register_writes                  0                       # number of times the floating registers were written
+system.cpu0.num_mem_refs                     19132508                       # number of memory refs
+system.cpu0.num_load_insts                   14284566                       # Number of load instructions
+system.cpu0.num_store_insts                   4847942                       # Number of store instructions
+system.cpu0.num_idle_cycles              10086452980.871330                       # Number of idle cycles
+system.cpu0.num_busy_cycles              521724469.128670                       # Number of busy cycles
+system.cpu0.not_idle_fraction                0.049181                       # Percentage of non-idle cycles
+system.cpu0.idle_fraction                    0.950819                       # Percentage of idle cycles
+system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
+system.cpu0.kern.inst.quiesce                       0                       # number of quiesce instructions executed
+system.cpu1.numCycles                     10609379371                       # number of cpu cycles simulated
+system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
+system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
+system.cpu1.committedInsts                   48574284                       # Number of instructions committed
+system.cpu1.committedOps                     93351709                       # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses             89110416                       # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses                     0                       # Number of float alu accesses
+system.cpu1.num_func_calls                          0                       # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts      8197841                       # number of instructions that are conditional controls
+system.cpu1.num_int_insts                    89110416                       # number of integer instructions
+system.cpu1.num_fp_insts                            0                       # number of float instructions
+system.cpu1.num_int_register_reads          273178604                       # number of times the integer registers were read
+system.cpu1.num_int_register_writes         138760228                       # number of times the integer registers were written
+system.cpu1.num_fp_register_reads                   0                       # number of times the floating registers were read
+system.cpu1.num_fp_register_writes                  0                       # number of times the floating registers were written
+system.cpu1.num_mem_refs                     14426742                       # number of memory refs
+system.cpu1.num_load_insts                    9181010                       # Number of load instructions
+system.cpu1.num_store_insts                   5245732                       # Number of store instructions
+system.cpu1.num_idle_cycles              10273661233.326063                       # Number of idle cycles
+system.cpu1.num_busy_cycles              335718137.673937                       # Number of busy cycles
+system.cpu1.not_idle_fraction                0.031644                       # Percentage of non-idle cycles
+system.cpu1.idle_fraction                    0.968356                       # Percentage of idle cycles
+system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
+system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
+
+---------- End Simulation Statistics   ----------

simulators/gem5/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/system.pc.com_1.terminal

@@ -0,0 +1,136 @@
+Linux version 2.6.22.9 (gblack@fajita) (gcc version 4.1.2 (Gentoo 4.1.2 p1.1)) #12 SMP Fri Feb 27 22:10:33 PST 2009
+Command line: earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1
+BIOS-provided physical RAM map:
+ BIOS-e820: 0000000000000000 - 0000000000100000 (reserved)
+ BIOS-e820: 0000000000100000 - 0000000008000000 (usable)
+end_pfn_map = 32768
+kernel direct mapping tables up to 8000000 @ 100000-102000
+DMI 2.5 present.
+Zone PFN ranges:
+  DMA           256 ->     4096
+  DMA32        4096 ->  1048576
+  Normal    1048576 ->  1048576
+early_node_map[1] active PFN ranges
+    0:      256 ->    32768
+Intel MultiProcessor Specification v1.4
+MPTABLE: OEM ID:  MPTABLE: Product ID:  MPTABLE: APIC at: 0xFEE00000
+Processor #0 (Bootup-CPU)
+Processor #1
+I/O APIC #2 at 0xFEC00000.
+Setting APIC routing to flat
+Processors: 2
+Allocating PCI resources starting at 10000000 (gap: 8000000:f8000000)
+PERCPU: Allocating 34160 bytes of per cpu data
+Built 1 zonelists.  Total pages: 30461
+Kernel command line: earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1
+Initializing CPU#0
+PID hash table entries: 512 (order: 9, 4096 bytes)
+Marking TSC unstable due to TSCs unsynchronized
+time.c: Detected 1999.999 MHz processor.
+Console: colour dummy device 80x25
+console handover: boot [earlyser0] -> real [ttyS0]
+Dentry cache hash table entries: 16384 (order: 5, 131072 bytes)
+Inode-cache hash table entries: 8192 (order: 4, 65536 bytes)
+Checking aperture...
+Memory: 121384k/131072k available (3699k kernel code, 8500k reserved, 1767k data, 248k init)
+Calibrating delay loop (skipped)... 3999.96 BogoMIPS preset
+Mount-cache hash table entries: 256
+CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)
+CPU: L2 Cache: 1024K (64 bytes/line)
+Freeing SMP alternatives: 34k freed
+Using local APIC timer interrupts.
+result 7812492
+Detected 7.812 MHz APIC timer.
+Booting processor 1/2 APIC 0x1
+Initializing CPU#1
+Calibrating delay loop (skipped)... 3999.96 BogoMIPS preset
+CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)
+CPU: L2 Cache: 1024K (64 bytes/line)
+Fake M5 x86_64 CPU stepping 01
+Brought up 2 CPUs
+migration_cost=11
+NET: Registered protocol family 16
+PCI: Using configuration type 1
+SCSI subsystem initialized
+usbcore: registered new interface driver usbfs
+usbcore: registered new interface driver hub
+usbcore: registered new device driver usb
+PCI: Probing PCI hardware
+PCI-GART: No AMD northbridge found.
+NET: Registered protocol family 2
+IP route cache hash table entries: 1024 (order: 1, 8192 bytes)
+TCP established hash table entries: 4096 (order: 4, 98304 bytes)
+TCP bind hash table entries: 4096 (order: 4, 65536 bytes)
+TCP: Hash tables configured (established 4096 bind 4096)
+TCP reno registered
+Total HugeTLB memory allocated, 0
+Installing knfsd (copyright (C) 1996 okir@monad.swb.de).
+io scheduler noop registered
+io scheduler deadline registered
+io scheduler cfq registered (default)
+Real Time Clock Driver v1.12ac
+Linux agpgart interface v0.102 (c) Dave Jones
+Serial: 8250/16550 driver $Revision: 1.90 $ 4 ports, IRQ sharing disabled
+serial8250: ttyS0 at I/O 0x3f8 (irq = 4) is a 8250
+floppy0: no floppy controllers found
+RAMDISK driver initialized: 16 RAM disks of 4096K size 1024 blocksize
+loop: module loaded
+Intel(R) PRO/1000 Network Driver - version 7.3.20-k2
+Copyright (c) 1999-2006 Intel Corporation.
+e100: Intel(R) PRO/100 Network Driver, 3.5.17-k4-NAPI
+e100: Copyright(c) 1999-2006 Intel Corporation
+forcedeth.c: Reverse Engineered nForce ethernet driver. Version 0.60.
+tun: Universal TUN/TAP device driver, 1.6
+tun: (C) 1999-2004 Max Krasnyansky <maxk@qualcomm.com>
+netconsole: not configured, aborting
+Uniform Multi-Platform E-IDE driver Revision: 7.00alpha2
+ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx
+PIIX4: IDE controller at PCI slot 0000:00:04.0
+PCI: Enabling device 0000:00:04.0 (0000 -> 0001)
+PIIX4: chipset revision 0
+PIIX4: not 100% native mode: will probe irqs later
+    ide0: BM-DMA at 0x1000-0x1007, BIOS settings: hda:DMA, hdb:DMA
+    ide1: BM-DMA at 0x1008-0x100f, BIOS settings: hdc:DMA, hdd:DMA
+hda: M5 IDE Disk, ATA DISK drive
+hdb: M5 IDE Disk, ATA DISK drive
+ide0 at 0x1f0-0x1f7,0x3f6 on irq 14
+hda: max request size: 128KiB
+hda: 1048320 sectors (536 MB), CHS=1040/16/63, UDMA(33)
+ hda: hda1
+hdb: max request size: 128KiB
+hdb: 4177920 sectors (2139 MB), CHS=4144/16/63, UDMA(33)
+ hdb: unknown partition table
+megaraid cmm: 2.20.2.7 (Release Date: Sun Jul 16 00:01:03 EST 2006)
+megaraid: 2.20.5.1 (Release Date: Thu Nov 16 15:32:35 EST 2006)
+megasas: 00.00.03.10-rc5 Thu May 17 10:09:32 PDT 2007
+Fusion MPT base driver 3.04.04
+Copyright (c) 1999-2007 LSI Logic Corporation
+Fusion MPT SPI Host driver 3.04.04
+Fusion MPT SAS Host driver 3.04.04
+ieee1394: raw1394: /dev/raw1394 device initialized
+USB Universal Host Controller Interface driver v3.0
+usbcore: registered new interface driver usblp
+drivers/usb/class/usblp.c: v0.13: USB Printer Device Class driver
+Initializing USB Mass Storage driver...
+usbcore: registered new interface driver usb-storage
+USB Mass Storage support registered.
+serio: i8042 KBD port at 0x60,0x64 irq 1
+serio: i8042 AUX port at 0x60,0x64 irq 12
+mice: PS/2 mouse device common for all mice
+input: AT Translated Set 2 keyboard as /class/input/input0
+device-mapper: ioctl: 4.11.0-ioctl (2006-10-12) initialised: dm-devel@redhat.com
+usbcore: registered new interface driver usbhid
+drivers/hid/usbhid/hid-core.c: v2.6:USB HID core driver
+oprofile: using timer interrupt.
+TCP cubic registered
+NET: Registered protocol family 1
+NET: Registered protocol family 10
+IPv6 over IPv4 tunneling driver
+NET: Registered protocol family 17
+input: PS/2 Generic Mouse as /class/input/input1
+EXT2-fs warning: mounting unchecked fs, running e2fsck is recommended
+VFS: Mounted root (ext2 filesystem).
+Freeing unused kernel memory: 248k freed
+
+INIT: version 2.86 booting
+

simulators/gem5/tests/long/fs/10.linux-boot/test.py

@@ -0,0 +1,29 @@
+# Copyright (c) 2006 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Steve Reinhardt
+
+root.system.readfile = os.path.join(tests_root, 'halt.sh')

simulators/gem5/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini

@@ -0,0 +1,484 @@
+[root]
+type=Root
+children=system
+full_system=true
+time_sync_enable=false
+time_sync_period=200000000
+time_sync_spin_threshold=200000
+
+[system]
+type=SparcSystem
+children=bridge cpu disk0 hypervisor_desc intrctrl iobus membus nvram partition_desc physmem physmem2 rom t1000
+boot_osflags=a
+hypervisor_addr=1099243257856
+hypervisor_bin=/dist/m5/system/binaries/q_new.bin
+hypervisor_desc=system.hypervisor_desc
+hypervisor_desc_addr=133446500352
+hypervisor_desc_bin=/dist/m5/system/binaries/1up-hv.bin
+init_param=0
+kernel=
+load_addr_mask=1099511627775
+mem_mode=atomic
+memories=system.partition_desc system.rom system.hypervisor_desc system.nvram system.physmem system.physmem2
+num_work_ids=16
+nvram=system.nvram
+nvram_addr=133429198848
+nvram_bin=/dist/m5/system/binaries/nvram1
+openboot_addr=1099243716608
+openboot_bin=/dist/m5/system/binaries/openboot_new.bin
+partition_desc=system.partition_desc
+partition_desc_addr=133445976064
+partition_desc_bin=/dist/m5/system/binaries/1up-md.bin
+readfile=tests/halt.sh
+reset_addr=1099243192320
+reset_bin=/dist/m5/system/binaries/reset_new.bin
+rom=system.rom
+symbolfile=
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.slave[0]
+
+[system.bridge]
+type=Bridge
+delay=100
+nack_delay=8
+ranges=133412421632:133412421639 134217728000:554050781183 644245094400:652835028991 725849473024:1095485095935 1099255955456:1099255955463
+req_size=16
+resp_size=16
+write_ack=false
+master=system.iobus.slave[0]
+slave=system.membus.master[2]
+
+[system.cpu]
+type=AtomicSimpleCPU
+children=dtb interrupts itb tracer
+checker=Null
+clock=1
+cpu_id=0
+defer_registration=false
+do_checkpoint_insts=true
+do_quiesce=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+fastmem=false
+function_trace=false
+function_trace_start=0
+interrupts=system.cpu.interrupts
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+phase=0
+profile=0
+progress_interval=0
+simulate_data_stalls=false
+simulate_inst_stalls=false
+system=system
+tracer=system.cpu.tracer
+width=1
+workload=
+dcache_port=system.membus.slave[2]
+icache_port=system.membus.slave[1]
+
+[system.cpu.dtb]
+type=SparcTLB
+size=64
+
+[system.cpu.interrupts]
+type=SparcInterrupts
+
+[system.cpu.itb]
+type=SparcTLB
+size=64
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.disk0]
+type=MmDisk
+children=image
+image=system.disk0.image
+pio_addr=134217728000
+pio_latency=2
+system=system
+pio=system.iobus.master[14]
+
+[system.disk0.image]
+type=CowDiskImage
+children=child
+child=system.disk0.image.child
+image_file=
+read_only=false
+table_size=65536
+
+[system.disk0.image.child]
+type=RawDiskImage
+image_file=/dist/m5/system/disks/disk.s10hw2
+read_only=true
+
+[system.hypervisor_desc]
+type=SimpleMemory
+conf_table_reported=false
+file=
+in_addr_map=true
+latency=60
+latency_var=0
+null=false
+range=133446500352:133446508543
+zero=false
+port=system.membus.master[7]
+
+[system.intrctrl]
+type=IntrControl
+sys=system
+
+[system.iobus]
+type=NoncoherentBus
+block_size=64
+clock=2
+header_cycles=1
+use_default_range=false
+width=64
+master=system.t1000.fake_clk.pio system.t1000.fake_membnks.pio system.t1000.fake_l2_1.pio system.t1000.fake_l2_2.pio system.t1000.fake_l2_3.pio system.t1000.fake_l2_4.pio system.t1000.fake_l2esr_1.pio system.t1000.fake_l2esr_2.pio system.t1000.fake_l2esr_3.pio system.t1000.fake_l2esr_4.pio system.t1000.fake_ssi.pio system.t1000.fake_jbi.pio system.t1000.puart0.pio system.t1000.hvuart.pio system.disk0.pio
+slave=system.bridge.master
+
+[system.membus]
+type=CoherentBus
+children=badaddr_responder
+block_size=64
+clock=2
+header_cycles=1
+use_default_range=false
+width=64
+default=system.membus.badaddr_responder.pio
+master=system.t1000.iob.pio system.t1000.htod.pio system.bridge.slave system.physmem.port[0] system.physmem2.port[0] system.rom.port[0] system.nvram.port[0] system.hypervisor_desc.port[0] system.partition_desc.port[0]
+slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
+
+[system.membus.badaddr_responder]
+type=IsaFake
+fake_mem=false
+pio_addr=0
+pio_latency=2
+pio_size=8
+ret_bad_addr=true
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.membus.default
+
+[system.nvram]
+type=SimpleMemory
+conf_table_reported=false
+file=
+in_addr_map=true
+latency=60
+latency_var=0
+null=false
+range=133429198848:133429207039
+zero=false
+port=system.membus.master[6]
+
+[system.partition_desc]
+type=SimpleMemory
+conf_table_reported=false
+file=
+in_addr_map=true
+latency=60
+latency_var=0
+null=false
+range=133445976064:133445984255
+zero=false
+port=system.membus.master[8]
+
+[system.physmem]
+type=SimpleMemory
+conf_table_reported=false
+file=
+in_addr_map=true
+latency=60
+latency_var=0
+null=false
+range=1048576:68157439
+zero=true
+port=system.membus.master[3]
+
+[system.physmem2]
+type=SimpleMemory
+conf_table_reported=false
+file=
+in_addr_map=true
+latency=60
+latency_var=0
+null=false
+range=2147483648:2415919103
+zero=true
+port=system.membus.master[4]
+
+[system.rom]
+type=SimpleMemory
+conf_table_reported=false
+file=
+in_addr_map=true
+latency=60
+latency_var=0
+null=false
+range=1099243192320:1099251580927
+zero=false
+port=system.membus.master[5]
+
+[system.t1000]
+type=T1000
+children=fake_clk fake_jbi fake_l2_1 fake_l2_2 fake_l2_3 fake_l2_4 fake_l2esr_1 fake_l2esr_2 fake_l2esr_3 fake_l2esr_4 fake_membnks fake_ssi hterm htod hvuart iob pterm puart0
+intrctrl=system.intrctrl
+system=system
+
+[system.t1000.fake_clk]
+type=IsaFake
+fake_mem=false
+pio_addr=644245094400
+pio_latency=2
+pio_size=4294967296
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[0]
+
+[system.t1000.fake_jbi]
+type=IsaFake
+fake_mem=false
+pio_addr=549755813888
+pio_latency=2
+pio_size=4294967296
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[11]
+
+[system.t1000.fake_l2_1]
+type=IsaFake
+fake_mem=false
+pio_addr=725849473024
+pio_latency=2
+pio_size=8
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=1
+ret_data8=255
+system=system
+update_data=true
+warn_access=
+pio=system.iobus.master[2]
+
+[system.t1000.fake_l2_2]
+type=IsaFake
+fake_mem=false
+pio_addr=725849473088
+pio_latency=2
+pio_size=8
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=1
+ret_data8=255
+system=system
+update_data=true
+warn_access=
+pio=system.iobus.master[3]
+
+[system.t1000.fake_l2_3]
+type=IsaFake
+fake_mem=false
+pio_addr=725849473152
+pio_latency=2
+pio_size=8
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=1
+ret_data8=255
+system=system
+update_data=true
+warn_access=
+pio=system.iobus.master[4]
+
+[system.t1000.fake_l2_4]
+type=IsaFake
+fake_mem=false
+pio_addr=725849473216
+pio_latency=2
+pio_size=8
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=1
+ret_data8=255
+system=system
+update_data=true
+warn_access=
+pio=system.iobus.master[5]
+
+[system.t1000.fake_l2esr_1]
+type=IsaFake
+fake_mem=false
+pio_addr=734439407616
+pio_latency=2
+pio_size=8
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=0
+ret_data8=255
+system=system
+update_data=true
+warn_access=
+pio=system.iobus.master[6]
+
+[system.t1000.fake_l2esr_2]
+type=IsaFake
+fake_mem=false
+pio_addr=734439407680
+pio_latency=2
+pio_size=8
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=0
+ret_data8=255
+system=system
+update_data=true
+warn_access=
+pio=system.iobus.master[7]
+
+[system.t1000.fake_l2esr_3]
+type=IsaFake
+fake_mem=false
+pio_addr=734439407744
+pio_latency=2
+pio_size=8
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=0
+ret_data8=255
+system=system
+update_data=true
+warn_access=
+pio=system.iobus.master[8]
+
+[system.t1000.fake_l2esr_4]
+type=IsaFake
+fake_mem=false
+pio_addr=734439407808
+pio_latency=2
+pio_size=8
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=0
+ret_data8=255
+system=system
+update_data=true
+warn_access=
+pio=system.iobus.master[9]
+
+[system.t1000.fake_membnks]
+type=IsaFake
+fake_mem=false
+pio_addr=648540061696
+pio_latency=2
+pio_size=16384
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=0
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[1]
+
+[system.t1000.fake_ssi]
+type=IsaFake
+fake_mem=false
+pio_addr=1095216660480
+pio_latency=2
+pio_size=268435456
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[10]
+
+[system.t1000.hterm]
+type=Terminal
+intr_control=system.intrctrl
+number=0
+output=true
+port=3456
+
+[system.t1000.htod]
+type=DumbTOD
+pio_addr=1099255906296
+pio_latency=2
+system=system
+time=Thu Jan  1 00:00:00 2009
+pio=system.membus.master[1]
+
+[system.t1000.hvuart]
+type=Uart8250
+pio_addr=1099255955456
+pio_latency=2
+platform=system.t1000
+system=system
+terminal=system.t1000.hterm
+pio=system.iobus.master[13]
+
+[system.t1000.iob]
+type=Iob
+pio_latency=2
+platform=system.t1000
+system=system
+pio=system.membus.master[0]
+
+[system.t1000.pterm]
+type=Terminal
+intr_control=system.intrctrl
+number=0
+output=true
+port=3456
+
+[system.t1000.puart0]
+type=Uart8250
+pio_addr=133412421632
+pio_latency=2
+platform=system.t1000
+system=system
+terminal=system.t1000.pterm
+pio=system.iobus.master[12]
+

simulators/gem5/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simerr

@@ -0,0 +1,5 @@
+warn: Sockets disabled, not accepting terminal connections
+warn: CoherentBus system.membus has no snooping ports attached!
+warn: Sockets disabled, not accepting gdb connections
+warn: Don't know what interrupt to clear for console.
+hack: be nice to actually delete the event here

simulators/gem5/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout

@@ -0,0 +1,16 @@
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jun  4 2012 12:01:47
+gem5 started Jun  4 2012 15:02:47
+gem5 executing on zizzer
+command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/fs/80.solaris-boot/sparc/solaris/t1000-simple-atomic -re tests/run.py build/SPARC/tests/opt/long/fs/80.solaris-boot/sparc/solaris/t1000-simple-atomic
+Global frequency set at 2000000000 ticks per second
+info: No kernel set for full system simulation. Assuming you know what you're doing if not SPARC ISA
+      0: system.t1000.htod: Real-time clock set to Thu Jan  1 00:00:00 2009
+
+      0: system.t1000.htod: Real-time clock set to 1230768000
+info: Entering event queue @ 0.  Starting simulation...
+info: Ignoring write to SPARC ERROR regsiter
+info: Ignoring write to SPARC ERROR regsiter
+Exiting @ tick 2233777512 because m5_exit instruction encountered

simulators/gem5/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt

@@ -0,0 +1,133 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds                                  1.116889                       # Number of seconds simulated
+sim_ticks                                  2233777512                       # Number of ticks simulated
+final_tick                                 2233777512                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                   2000000000                       # Frequency of simulated ticks
+host_inst_rate                                3140005                       # Simulator instruction rate (inst/s)
+host_op_rate                                  3141240                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                3147745                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 511524                       # Number of bytes of host memory used
+host_seconds                                   709.64                       # Real time elapsed on the host
+sim_insts                                  2228284650                       # Number of instructions simulated
+sim_ops                                    2229160714                       # Number of ops (including micro ops) simulated
+system.hypervisor_desc.bytes_read::cpu.data        16792                       # Number of bytes read from this memory
+system.hypervisor_desc.bytes_read::total        16792                       # Number of bytes read from this memory
+system.hypervisor_desc.num_reads::cpu.data         9024                       # Number of read requests responded to by this memory
+system.hypervisor_desc.num_reads::total          9024                       # Number of read requests responded to by this memory
+system.hypervisor_desc.bw_read::cpu.data        15035                       # Total read bandwidth from this memory (bytes/s)
+system.hypervisor_desc.bw_read::total           15035                       # Total read bandwidth from this memory (bytes/s)
+system.hypervisor_desc.bw_total::cpu.data        15035                       # Total bandwidth to/from this memory (bytes/s)
+system.hypervisor_desc.bw_total::total          15035                       # Total bandwidth to/from this memory (bytes/s)
+system.partition_desc.bytes_read::cpu.data         4846                       # Number of bytes read from this memory
+system.partition_desc.bytes_read::total          4846                       # Number of bytes read from this memory
+system.partition_desc.num_reads::cpu.data          608                       # Number of read requests responded to by this memory
+system.partition_desc.num_reads::total            608                       # Number of read requests responded to by this memory
+system.partition_desc.bw_read::cpu.data          4339                       # Total read bandwidth from this memory (bytes/s)
+system.partition_desc.bw_read::total             4339                       # Total read bandwidth from this memory (bytes/s)
+system.partition_desc.bw_total::cpu.data         4339                       # Total bandwidth to/from this memory (bytes/s)
+system.partition_desc.bw_total::total            4339                       # Total bandwidth to/from this memory (bytes/s)
+system.rom.bytes_read::cpu.inst                432296                       # Number of bytes read from this memory
+system.rom.bytes_read::cpu.data                696392                       # Number of bytes read from this memory
+system.rom.bytes_read::total                  1128688                       # Number of bytes read from this memory
+system.rom.bytes_inst_read::cpu.inst           432296                       # Number of instructions bytes read from this memory
+system.rom.bytes_inst_read::total              432296                       # Number of instructions bytes read from this memory
+system.rom.num_reads::cpu.inst                 108074                       # Number of read requests responded to by this memory
+system.rom.num_reads::cpu.data                  87049                       # Number of read requests responded to by this memory
+system.rom.num_reads::total                    195123                       # Number of read requests responded to by this memory
+system.rom.bw_read::cpu.inst                   387054                       # Total read bandwidth from this memory (bytes/s)
+system.rom.bw_read::cpu.data                   623511                       # Total read bandwidth from this memory (bytes/s)
+system.rom.bw_read::total                     1010564                       # Total read bandwidth from this memory (bytes/s)
+system.rom.bw_inst_read::cpu.inst              387054                       # Instruction read bandwidth from this memory (bytes/s)
+system.rom.bw_inst_read::total                 387054                       # Instruction read bandwidth from this memory (bytes/s)
+system.rom.bw_total::cpu.inst                  387054                       # Total bandwidth to/from this memory (bytes/s)
+system.rom.bw_total::cpu.data                  623511                       # Total bandwidth to/from this memory (bytes/s)
+system.rom.bw_total::total                    1010564                       # Total bandwidth to/from this memory (bytes/s)
+system.nvram.bytes_read::cpu.data                 284                       # Number of bytes read from this memory
+system.nvram.bytes_read::total                    284                       # Number of bytes read from this memory
+system.nvram.bytes_written::cpu.data               92                       # Number of bytes written to this memory
+system.nvram.bytes_written::total                  92                       # Number of bytes written to this memory
+system.nvram.num_reads::cpu.data                  284                       # Number of read requests responded to by this memory
+system.nvram.num_reads::total                     284                       # Number of read requests responded to by this memory
+system.nvram.num_writes::cpu.data                  92                       # Number of write requests responded to by this memory
+system.nvram.num_writes::total                     92                       # Number of write requests responded to by this memory
+system.nvram.bw_read::cpu.data                    254                       # Total read bandwidth from this memory (bytes/s)
+system.nvram.bw_read::total                       254                       # Total read bandwidth from this memory (bytes/s)
+system.nvram.bw_write::cpu.data                    82                       # Write bandwidth from this memory (bytes/s)
+system.nvram.bw_write::total                       82                       # Write bandwidth from this memory (bytes/s)
+system.nvram.bw_total::cpu.data                   337                       # Total bandwidth to/from this memory (bytes/s)
+system.nvram.bw_total::total                      337                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::cpu.inst         612291324                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          97534024                       # Number of bytes read from this memory
+system.physmem.bytes_read::total            709825348                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst    612291324                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total       612291324                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::cpu.data       15400223                       # Number of bytes written to this memory
+system.physmem.bytes_written::total          15400223                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst          153072831                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data           12152054                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total             165224885                       # Number of read requests responded to by this memory
+system.physmem.num_writes::cpu.data           1927067                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total              1927067                       # Number of write requests responded to by this memory
+system.physmem.num_other::cpu.data                 14                       # Number of other requests responded to by this memory
+system.physmem.num_other::total                    14                       # Number of other requests responded to by this memory
+system.physmem.bw_read::cpu.inst            548211557                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             87326534                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               635538091                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst       548211557                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total          548211557                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data            13788502                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               13788502                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst           548211557                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           101115036                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              649326593                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem2.bytes_read::cpu.inst       8318106840                       # Number of bytes read from this memory
+system.physmem2.bytes_read::cpu.data       1495885127                       # Number of bytes read from this memory
+system.physmem2.bytes_read::total          9813991967                       # Number of bytes read from this memory
+system.physmem2.bytes_inst_read::cpu.inst   8318106840                       # Number of instructions bytes read from this memory
+system.physmem2.bytes_inst_read::total     8318106840                       # Number of instructions bytes read from this memory
+system.physmem2.bytes_written::cpu.data     897268422                       # Number of bytes written to this memory
+system.physmem2.bytes_written::total        897268422                       # Number of bytes written to this memory
+system.physmem2.num_reads::cpu.inst        2079526710                       # Number of read requests responded to by this memory
+system.physmem2.num_reads::cpu.data         323962420                       # Number of read requests responded to by this memory
+system.physmem2.num_reads::total           2403489130                       # Number of read requests responded to by this memory
+system.physmem2.num_writes::cpu.data        187387796                       # Number of write requests responded to by this memory
+system.physmem2.num_writes::total           187387796                       # Number of write requests responded to by this memory
+system.physmem2.num_other::cpu.data           5403067                       # Number of other requests responded to by this memory
+system.physmem2.num_other::total              5403067                       # Number of other requests responded to by this memory
+system.physmem2.bw_read::cpu.inst          7447569684                       # Total read bandwidth from this memory (bytes/s)
+system.physmem2.bw_read::cpu.data          1339332247                       # Total read bandwidth from this memory (bytes/s)
+system.physmem2.bw_read::total             8786901931                       # Total read bandwidth from this memory (bytes/s)
+system.physmem2.bw_inst_read::cpu.inst     7447569684                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem2.bw_inst_read::total        7447569684                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem2.bw_write::cpu.data          803364182                       # Write bandwidth from this memory (bytes/s)
+system.physmem2.bw_write::total             803364182                       # Write bandwidth from this memory (bytes/s)
+system.physmem2.bw_total::cpu.inst         7447569684                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem2.bw_total::cpu.data         2142696429                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem2.bw_total::total            9590266113                       # Total bandwidth to/from this memory (bytes/s)
+system.cpu.numCycles                       2233777513                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.committedInsts                  2228284650                       # Number of instructions committed
+system.cpu.committedOps                    2229160714                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses            1839325658                       # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses               14608322                       # Number of float alu accesses
+system.cpu.num_func_calls                    44037246                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts    316367761                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                   1839325658                       # number of integer instructions
+system.cpu.num_fp_insts                      14608322                       # number of float instructions
+system.cpu.num_int_register_reads          4305540407                       # number of times the integer registers were read
+system.cpu.num_int_register_writes         2100562807                       # number of times the integer registers were written
+system.cpu.num_fp_register_reads             35401841                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes            22917558                       # number of times the floating registers were written
+system.cpu.num_mem_refs                     547951940                       # number of memory refs
+system.cpu.num_load_insts                   349807670                       # Number of load instructions
+system.cpu.num_store_insts                  198144270                       # Number of store instructions
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
+system.cpu.num_busy_cycles                 2233777513                       # Number of busy cycles
+system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                            0                       # Percentage of idle cycles
+system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
+system.cpu.kern.inst.quiesce                        0                       # number of quiesce instructions executed
+
+---------- End Simulation Statistics   ----------

simulators/gem5/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/system.t1000.pterm

@@ -0,0 +1,48 @@
+cpu 
+
+Sun Fire T2000, No Keyboard
+Copyright 2006 Sun Microsystems, Inc.  All rights reserved.
+OpenBoot 4.23.0, 256 MB memory available, Serial #1122867.
+[saidi obp #30]
+Ethernet address 0:80:3:de:ad:3, Host ID: 80112233.
+
+
+
+Boot device: /virtual-devices/disk@0  File and args: -vV
+Loading ufs-file-system package 1.4 04 Aug 1995 13:02:54. 
+FCode UFS Reader 1.12 00/07/17 15:48:16. 
+Loading: /platform/SUNW,Sun-Fire-T2000/ufsboot
+Loading: /platform/sun4v/ufsboot
+device path '/virtual-devices@100/disk@0:a'
+The boot filesystem is logging.
+The ufs log is empty and will not be used.
+standalone = `kernel/sparcv9/unix', args = `-v'
+|Elf64 client
+Size: /-\|/-\|0x76e40+/-\|/-\|/-\|/-\0x1c872+|/-\0x3123a Bytes
+modpath: /platform/sun4v/kernel /kernel /usr/kernel
+|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-module /platform/sun4v/kernel/sparcv9/unix: text at [0x1000000, 0x1076e3f] data at 0x1800000
+module misc/sparcv9/krtld: text at [0x1076e40, 0x108f737] data at 0x184dab0
+module /platform/sun4v/kernel/sparcv9/genunix: text at [0x108f738, 0x11dd437] data at 0x18531c0
+module /platform/sun4v/kernel/misc/sparcv9/platmod: text at [0x11dd438, 0x11dd43f] data at 0x18a4be0
+module /platform/sun4v/kernel/cpu/sparcv9/SUNW,UltraSPARC-T1: text at [0x11dd440, 0x11e06ff] data at 0x18a5300
+\
+SunOS Release 5.10 Version Generic_118822-23 64-bit
+Copyright 1983-2005 Sun Microsystems, Inc.  All rights reserved.
+Use is subject to license terms.
+|/-\|/-\|/-\|/-\|/-Ethernet address = 0:80:3:de:ad:3
+\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/mem = 262144K (0x10000000)
+avail mem = 237879296
+root nexus = Sun Fire T2000
+pseudo0 at root
+pseudo0 is /pseudo
+scsi_vhci0 at root
+scsi_vhci0 is /scsi_vhci
+virtual-device: hsimd0
+hsimd0 is /virtual-devices@100/disk@0
+root on /virtual-devices@100/disk@0:a fstype ufs
+pseudo-device: dld0
+dld0 is /pseudo/dld@0
+cpu0: UltraSPARC-T1 (cpuid 0 clock 5 MHz)
+iscsi0 at root
+iscsi0 is /iscsi
+Hostname: unknown

simulators/gem5/tests/long/fs/80.solaris-boot/test.py

@@ -0,0 +1,29 @@
+# Copyright (c) 2007 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Ali Saidi
+
+root.system.readfile = os.path.join(tests_root, 'halt.sh')

simulators/gem5/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/config.ini

@@ -0,0 +1,231 @@
+[root]
+type=Root
+children=system
+full_system=false
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
+mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
+readfile=
+symbolfile=
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.slave[0]
+
+[system.cpu]
+type=InOrderCPU
+children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
+BTBEntries=4096
+BTBTagSize=16
+RASSize=16
+activity=0
+cachePorts=2
+checker=Null
+choiceCtrBits=2
+choicePredictorSize=8192
+clock=500
+cpu_id=0
+defer_registration=false
+div16Latency=1
+div16RepeatRate=1
+div24Latency=1
+div24RepeatRate=1
+div32Latency=1
+div32RepeatRate=1
+div8Latency=1
+div8RepeatRate=1
+do_checkpoint_insts=true
+do_quiesce=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+fetchBuffSize=4
+functionTrace=false
+functionTraceStart=0
+function_trace=false
+function_trace_start=0
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+instShiftAmt=2
+interrupts=system.cpu.interrupts
+itb=system.cpu.itb
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+memBlockSize=64
+multLatency=1
+multRepeatRate=1
+numThreads=1
+phase=0
+predType=tournament
+profile=0
+progress_interval=0
+stageTracing=false
+stageWidth=4
+system=system
+threadModel=SMT
+tracer=system.cpu.tracer
+workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.dcache]
+type=BaseCache
+addr_ranges=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+prefetch_on_access=false
+prefetcher=Null
+prioritizeRequests=false
+repl=Null
+size=262144
+subblock_size=0
+system=system
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.slave[1]
+
+[system.cpu.dtb]
+type=AlphaTLB
+size=64
+
+[system.cpu.icache]
+type=BaseCache
+addr_ranges=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+prefetch_on_access=false
+prefetcher=Null
+prioritizeRequests=false
+repl=Null
+size=131072
+subblock_size=0
+system=system
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.slave[0]
+
+[system.cpu.interrupts]
+type=AlphaInterrupts
+
+[system.cpu.itb]
+type=AlphaTLB
+size=48
+
+[system.cpu.l2cache]
+type=BaseCache
+addr_ranges=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=false
+latency=10000
+max_miss_count=0
+mshrs=10
+prefetch_on_access=false
+prefetcher=Null
+prioritizeRequests=false
+repl=Null
+size=2097152
+subblock_size=0
+system=system
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.master[0]
+mem_side=system.membus.slave[1]
+
+[system.cpu.toL2Bus]
+type=CoherentBus
+block_size=64
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+master=system.cpu.l2cache.cpu_side
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=gzip input.log 1
+cwd=build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/inorder-timing
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+
+[system.membus]
+type=CoherentBus
+block_size=64
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+master=system.physmem.port[0]
+slave=system.system_port system.cpu.l2cache.mem_side
+
+[system.physmem]
+type=SimpleMemory
+conf_table_reported=false
+file=
+in_addr_map=true
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.membus.master[0]
+

simulators/gem5/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simerr

@@ -0,0 +1,6 @@
+warn: Sockets disabled, not accepting gdb connections
+warn: Prefetch instructions in Alpha do not do anything
+warn: Prefetch instructions in Alpha do not do anything
+warn: Prefetch instructions in Alpha do not do anything
+warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
+hack: be nice to actually delete the event here

simulators/gem5/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simout

@@ -0,0 +1,42 @@
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jun  4 2012 11:50:11
+gem5 started Jun  4 2012 13:43:43
+gem5 executing on zizzer
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/inorder-timing
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0.  Starting simulation...
+info: Increasing stack size by one page.
+spec_init
+Loading Input Data
+Duplicating 262144 bytes
+Duplicating 524288 bytes
+Input data 1048576 bytes in length
+Compressing Input Data, level 1
+Compressed data 108074 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 3
+Compressed data 97831 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 5
+Compressed data 83382 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 7
+Compressed data 76606 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 9
+Compressed data 73189 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Tested 1MB buffer: OK!
+Exiting @ tick 274300226500 because target called exit()

simulators/gem5/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt

@@ -0,0 +1,466 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds                                  0.274300                       # Number of seconds simulated
+sim_ticks                                274300226500                       # Number of ticks simulated
+final_tick                               274300226500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                 112537                       # Simulator instruction rate (inst/s)
+host_op_rate                                   112537                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               51289289                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 215256                       # Number of bytes of host memory used
+host_seconds                                  5348.10                       # Real time elapsed on the host
+sim_insts                                   601856964                       # Number of instructions simulated
+sim_ops                                     601856964                       # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu.inst             54720                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data           5839360                       # Number of bytes read from this memory
+system.physmem.bytes_read::total              5894080                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        54720                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           54720                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      3798144                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           3798144                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst                855                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data              91240                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                 92095                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks           59346                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total                59346                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst               199489                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             21288207                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                21487696                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          199489                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             199489                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks          13846667                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               13846667                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks          13846667                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              199489                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            21288207                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               35334364                       # Total bandwidth to/from this memory (bytes/s)
+system.cpu.dtb.fetch_hits                           0                       # ITB hits
+system.cpu.dtb.fetch_misses                         0                       # ITB misses
+system.cpu.dtb.fetch_acv                            0                       # ITB acv
+system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
+system.cpu.dtb.read_hits                    114517577                       # DTB read hits
+system.cpu.dtb.read_misses                       2631                       # DTB read misses
+system.cpu.dtb.read_acv                             0                       # DTB read access violations
+system.cpu.dtb.read_accesses                114520208                       # DTB read accesses
+system.cpu.dtb.write_hits                    39666608                       # DTB write hits
+system.cpu.dtb.write_misses                      2302                       # DTB write misses
+system.cpu.dtb.write_acv                            0                       # DTB write access violations
+system.cpu.dtb.write_accesses                39668910                       # DTB write accesses
+system.cpu.dtb.data_hits                    154184185                       # DTB hits
+system.cpu.dtb.data_misses                       4933                       # DTB misses
+system.cpu.dtb.data_acv                             0                       # DTB access violations
+system.cpu.dtb.data_accesses                154189118                       # DTB accesses
+system.cpu.itb.fetch_hits                    25020502                       # ITB hits
+system.cpu.itb.fetch_misses                        22                       # ITB misses
+system.cpu.itb.fetch_acv                            0                       # ITB acv
+system.cpu.itb.fetch_accesses                25020524                       # ITB accesses
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.read_acv                             0                       # DTB read access violations
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
+system.cpu.itb.write_acv                            0                       # DTB write access violations
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.data_hits                            0                       # DTB hits
+system.cpu.itb.data_misses                          0                       # DTB misses
+system.cpu.itb.data_acv                             0                       # DTB access violations
+system.cpu.itb.data_accesses                        0                       # DTB accesses
+system.cpu.workload.num_syscalls                   17                       # Number of system calls
+system.cpu.numCycles                        548600454                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.branch_predictor.lookups          86318297                       # Number of BP lookups
+system.cpu.branch_predictor.condPredicted     81372201                       # Number of conditional branches predicted
+system.cpu.branch_predictor.condIncorrect     36359139                       # Number of conditional branches incorrect
+system.cpu.branch_predictor.BTBLookups       52872243                       # Number of BTB lookups
+system.cpu.branch_predictor.BTBHits          34320184                       # Number of BTB hits
+system.cpu.branch_predictor.usedRAS           1197609                       # Number of times the RAS was used to get a target.
+system.cpu.branch_predictor.RASInCorrect            6                       # Number of incorrect RAS predictions.
+system.cpu.branch_predictor.BTBHitPct       64.911534                       # BTB Hit Percentage
+system.cpu.branch_predictor.predictedTaken     36897167                       # Number of Branches Predicted As Taken (True).
+system.cpu.branch_predictor.predictedNotTaken     49421130                       # Number of Branches Predicted As Not Taken (False).
+system.cpu.regfile_manager.intRegFileReads    541659172                       # Number of Reads from Int. Register File
+system.cpu.regfile_manager.intRegFileWrites    463854846                       # Number of Writes to Int. Register File
+system.cpu.regfile_manager.intRegFileAccesses   1005514018                       # Total Accesses (Read+Write) to the Int. Register File
+system.cpu.regfile_manager.floatRegFileReads          161                       # Number of Reads from FP Register File
+system.cpu.regfile_manager.floatRegFileWrites           42                       # Number of Writes to FP Register File
+system.cpu.regfile_manager.floatRegFileAccesses          203                       # Total Accesses (Read+Write) to the FP Register File
+system.cpu.regfile_manager.regForwards      254972528                       # Number of Registers Read Through Forwarding Logic
+system.cpu.agen_unit.agens                  155051949                       # Number of Address Generations
+system.cpu.execution_unit.predictedTakenIncorrect     33760596                       # Number of Branches Incorrectly Predicted As Taken.
+system.cpu.execution_unit.predictedNotTakenIncorrect      2593556                       # Number of Branches Incorrectly Predicted As Not Taken).
+system.cpu.execution_unit.mispredicted       36354152                       # Number of Branches Incorrectly Predicted
+system.cpu.execution_unit.predicted          26193756                       # Number of Branches Incorrectly Predicted
+system.cpu.execution_unit.mispredictPct     58.122091                       # Percentage of Incorrect Branches Predicts
+system.cpu.execution_unit.executions        412334574                       # Number of Instructions Executed.
+system.cpu.mult_div_unit.multiplies              6482                       # Number of Multipy Operations Executed
+system.cpu.mult_div_unit.divides                    0                       # Number of Divide Operations Executed
+system.cpu.contextSwitches                          1                       # Number of context switches
+system.cpu.threadCycles                     538371184                       # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
+system.cpu.smtCycles                                0                       # Total number of cycles that the CPU was in SMT-mode
+system.cpu.timesIdled                          412150                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                        59439534                       # Number of cycles cpu's stages were not processed
+system.cpu.runCycles                        489160920                       # Number of cycles cpu stages are processed.
+system.cpu.activity                         89.165242                       # Percentage of cycles cpu is active
+system.cpu.comLoads                         114514042                       # Number of Load instructions committed
+system.cpu.comStores                         39451321                       # Number of Store instructions committed
+system.cpu.comBranches                       62547159                       # Number of Branches instructions committed
+system.cpu.comNops                           36304520                       # Number of Nop instructions committed
+system.cpu.comNonSpec                              17                       # Number of Non-Speculative instructions committed
+system.cpu.comInts                          349039879                       # Number of Integer instructions committed
+system.cpu.comFloats                               24                       # Number of Floating Point instructions committed
+system.cpu.committedInsts                   601856964                       # Number of Instructions committed (Per-Thread)
+system.cpu.committedOps                     601856964                       # Number of Ops committed (Per-Thread)
+system.cpu.smtCommittedInsts                        0                       # Number of SMT Instructions committed (Per-Thread)
+system.cpu.committedInsts_total             601856964                       # Number of Instructions committed (Total)
+system.cpu.cpi                               0.911513                       # CPI: Cycles Per Instruction (Per-Thread)
+system.cpu.smt_cpi                                nan                       # CPI: Total SMT-CPI
+system.cpu.cpi_total                         0.911513                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.097077                       # IPC: Instructions Per Cycle (Per-Thread)
+system.cpu.smt_ipc                                nan                       # IPC: Total SMT-IPC
+system.cpu.ipc_total                         1.097077                       # IPC: Total IPC of All Threads
+system.cpu.stage0.idleCycles                209725198                       # Number of cycles 0 instructions are processed.
+system.cpu.stage0.runCycles                 338875256                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage0.utilization               61.770867                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage1.idleCycles                237724577                       # Number of cycles 0 instructions are processed.
+system.cpu.stage1.runCycles                 310875877                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage1.utilization               56.667083                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage2.idleCycles                206774969                       # Number of cycles 0 instructions are processed.
+system.cpu.stage2.runCycles                 341825485                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage2.utilization               62.308641                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage3.idleCycles                437071966                       # Number of cycles 0 instructions are processed.
+system.cpu.stage3.runCycles                 111528488                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage3.utilization               20.329638                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage4.idleCycles                201598142                       # Number of cycles 0 instructions are processed.
+system.cpu.stage4.runCycles                 347002312                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage4.utilization               63.252283                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.icache.replacements                     30                       # number of replacements
+system.cpu.icache.tagsinuse                728.232127                       # Cycle average of tags in use
+system.cpu.icache.total_refs                 25019479                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                    855                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs               29262.548538                       # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::cpu.inst     728.232127                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.355582                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.355582                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst     25019479                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        25019479                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      25019479                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         25019479                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     25019479                       # number of overall hits
+system.cpu.icache.overall_hits::total        25019479                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst         1021                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total          1021                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst         1021                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total           1021                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst         1021                       # number of overall misses
+system.cpu.icache.overall_misses::total          1021                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     56709500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     56709500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     56709500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     56709500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     56709500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     56709500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     25020500                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     25020500                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     25020500                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     25020500                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     25020500                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     25020500                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000041                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.000041                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000041                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.000041                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000041                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.000041                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55543.095005                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 55543.095005                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 55543.095005                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 55543.095005                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 55543.095005                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 55543.095005                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets        87500                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               3                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets 29166.666667                       # average number of cycles each access was blocked
+system.cpu.icache.fast_writes                       0                       # number of fast writes performed
+system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst          166                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total          166                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst          166                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total          166                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst          166                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total          166                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst          855                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total          855                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst          855                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total          855                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst          855                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total          855                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     45765000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     45765000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     45765000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     45765000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     45765000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     45765000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000034                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000034                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000034                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.000034                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000034                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.000034                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53526.315789                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53526.315789                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53526.315789                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 53526.315789                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53526.315789                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 53526.315789                       # average overall mshr miss latency
+system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.replacements                 451299                       # number of replacements
+system.cpu.dcache.tagsinuse               4094.124914                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                152394215                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                 455395                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                 334.641827                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle              267632000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data    4094.124914                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.999542                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.999542                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data    114120509                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       114120509                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     38273706                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       38273706                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data     152394215                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        152394215                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    152394215                       # number of overall hits
+system.cpu.dcache.overall_hits::total       152394215                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       393533                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        393533                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      1177615                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      1177615                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data      1571148                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        1571148                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      1571148                       # number of overall misses
+system.cpu.dcache.overall_misses::total       1571148                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data   8150462000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total   8150462000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  25247540000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  25247540000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  33398002000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  33398002000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  33398002000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  33398002000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    114514042                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    114514042                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data     39451321                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total     39451321                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data    153965363                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    153965363                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    153965363                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    153965363                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.003437                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.003437                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.029850                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.029850                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.010205                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.010205                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.010205                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.010205                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20711.000094                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 20711.000094                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 21439.553674                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 21439.553674                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 21257.069353                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 21257.069353                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 21257.069353                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 21257.069353                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs     12006000                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets   3424818500                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs              2777                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets          216268                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs  4323.370544                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 15835.992842                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.writebacks::writebacks       408190                       # number of writebacks
+system.cpu.dcache.writebacks::total            408190                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       192301                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       192301                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data       923452                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total       923452                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data      1115753                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      1115753                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      1115753                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      1115753                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data       201232                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       201232                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       254163                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       254163                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data       455395                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       455395                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       455395                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       455395                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   3562095500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   3562095500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   5466864500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   5466864500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data   9028960000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total   9028960000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data   9028960000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total   9028960000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.001757                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.001757                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.006442                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.006442                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.002958                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.002958                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.002958                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.002958                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17701.436650                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17701.436650                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 21509.285380                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 21509.285380                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19826.655980                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 19826.655980                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19826.655980                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 19826.655980                       # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.l2cache.replacements                 73798                       # number of replacements
+system.cpu.l2cache.tagsinuse             17696.811171                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                  445686                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                 89684                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                  4.969515                       # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::writebacks 16057.614667                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst     28.392088                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data   1610.804416                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks     0.490040                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst     0.000866                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.049158                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.540064                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.data       170049                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total         170049                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks       408190                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total       408190                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data       194106                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       194106                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.data       364155                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total          364155                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.data       364155                       # number of overall hits
+system.cpu.l2cache.overall_hits::total         364155                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst          855                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data        31164                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total        32019                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data        60076                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total        60076                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst          855                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data        91240                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total         92095                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst          855                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data        91240                       # number of overall misses
+system.cpu.l2cache.overall_misses::total        92095                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     44767500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data   1630159000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total   1674926500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   3134429000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   3134429000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     44767500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data   4764588000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total   4809355500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     44767500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data   4764588000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total   4809355500                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst          855                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data       201213                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total       202068                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks       408190                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total       408190                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       254182                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       254182                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst          855                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data       455395                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total       456250                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst          855                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data       455395                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total       456250                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst            1                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.154881                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.158457                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.236350                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.236350                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst            1                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.200354                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.201852                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst            1                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.200354                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.201852                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52359.649123                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52309.042485                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 52310.393829                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52174.395765                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52174.395765                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52359.649123                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52220.385796                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 52221.678701                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52359.649123                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52220.385796                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 52221.678701                       # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs      1278500                       # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs              127                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs 10066.929134                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
+system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
+system.cpu.l2cache.writebacks::writebacks        59346                       # number of writebacks
+system.cpu.l2cache.writebacks::total            59346                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          855                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        31164                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total        32019                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        60076                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total        60076                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst          855                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data        91240                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total        92095                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst          855                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data        91240                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total        92095                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     34345000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   1246682000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total   1281027000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   2406884500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   2406884500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     34345000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   3653566500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total   3687911500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     34345000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   3653566500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total   3687911500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.154881                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.158457                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.236350                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.236350                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.200354                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.201852                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.200354                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.201852                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40169.590643                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40003.914773                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40008.338799                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40063.993941                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40063.993941                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40169.590643                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40043.473257                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40044.644117                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40169.590643                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40043.473257                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40044.644117                       # average overall mshr miss latency
+system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+
+---------- End Simulation Statistics   ----------

simulators/gem5/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/config.ini

@@ -0,0 +1,529 @@
+[root]
+type=Root
+children=system
+full_system=false
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
+mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
+readfile=
+symbolfile=
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.slave[0]
+
+[system.cpu]
+type=DerivO3CPU
+children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
+BTBEntries=4096
+BTBTagSize=16
+LFSTSize=1024
+LQEntries=32
+LSQCheckLoads=true
+LSQDepCheckShift=4
+RASSize=16
+SQEntries=32
+SSITSize=1024
+activity=0
+backComSize=5
+cachePorts=200
+checker=Null
+choiceCtrBits=2
+choicePredictorSize=8192
+clock=500
+commitToDecodeDelay=1
+commitToFetchDelay=1
+commitToIEWDelay=1
+commitToRenameDelay=1
+commitWidth=8
+cpu_id=0
+decodeToFetchDelay=1
+decodeToRenameDelay=1
+decodeWidth=8
+defer_registration=false
+dispatchWidth=8
+do_checkpoint_insts=true
+do_quiesce=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+fetchToDecodeDelay=1
+fetchTrapLatency=1
+fetchWidth=8
+forwardComSize=5
+fuPool=system.cpu.fuPool
+function_trace=false
+function_trace_start=0
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+iewToCommitDelay=1
+iewToDecodeDelay=1
+iewToFetchDelay=1
+iewToRenameDelay=1
+instShiftAmt=2
+interrupts=system.cpu.interrupts
+issueToExecuteDelay=1
+issueWidth=8
+itb=system.cpu.itb
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+needsTSO=false
+numIQEntries=64
+numPhysFloatRegs=256
+numPhysIntRegs=256
+numROBEntries=192
+numRobs=1
+numThreads=1
+phase=0
+predType=tournament
+profile=0
+progress_interval=0
+renameToDecodeDelay=1
+renameToFetchDelay=1
+renameToIEWDelay=2
+renameToROBDelay=1
+renameWidth=8
+smtCommitPolicy=RoundRobin
+smtFetchPolicy=SingleThread
+smtIQPolicy=Partitioned
+smtIQThreshold=100
+smtLSQPolicy=Partitioned
+smtLSQThreshold=100
+smtNumFetchingThreads=1
+smtROBPolicy=Partitioned
+smtROBThreshold=100
+squashWidth=8
+store_set_clear_period=250000
+system=system
+tracer=system.cpu.tracer
+trapLatency=13
+wbDepth=1
+wbWidth=8
+workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.dcache]
+type=BaseCache
+addr_ranges=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+prefetch_on_access=false
+prefetcher=Null
+prioritizeRequests=false
+repl=Null
+size=262144
+subblock_size=0
+system=system
+tgts_per_mshr=20
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.slave[1]
+
+[system.cpu.dtb]
+type=AlphaTLB
+size=64
+
+[system.cpu.fuPool]
+type=FUPool
+children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
+FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
+
+[system.cpu.fuPool.FUList0]
+type=FUDesc
+children=opList
+count=6
+opList=system.cpu.fuPool.FUList0.opList
+
+[system.cpu.fuPool.FUList0.opList]
+type=OpDesc
+issueLat=1
+opClass=IntAlu
+opLat=1
+
+[system.cpu.fuPool.FUList1]
+type=FUDesc
+children=opList0 opList1
+count=2
+opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
+
+[system.cpu.fuPool.FUList1.opList0]
+type=OpDesc
+issueLat=1
+opClass=IntMult
+opLat=3
+
+[system.cpu.fuPool.FUList1.opList1]
+type=OpDesc
+issueLat=19
+opClass=IntDiv
+opLat=20
+
+[system.cpu.fuPool.FUList2]
+type=FUDesc
+children=opList0 opList1 opList2
+count=4
+opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
+
+[system.cpu.fuPool.FUList2.opList0]
+type=OpDesc
+issueLat=1
+opClass=FloatAdd
+opLat=2
+
+[system.cpu.fuPool.FUList2.opList1]
+type=OpDesc
+issueLat=1
+opClass=FloatCmp
+opLat=2
+
+[system.cpu.fuPool.FUList2.opList2]
+type=OpDesc
+issueLat=1
+opClass=FloatCvt
+opLat=2
+
+[system.cpu.fuPool.FUList3]
+type=FUDesc
+children=opList0 opList1 opList2
+count=2
+opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
+
+[system.cpu.fuPool.FUList3.opList0]
+type=OpDesc
+issueLat=1
+opClass=FloatMult
+opLat=4
+
+[system.cpu.fuPool.FUList3.opList1]
+type=OpDesc
+issueLat=12
+opClass=FloatDiv
+opLat=12
+
+[system.cpu.fuPool.FUList3.opList2]
+type=OpDesc
+issueLat=24
+opClass=FloatSqrt
+opLat=24
+
+[system.cpu.fuPool.FUList4]
+type=FUDesc
+children=opList
+count=0
+opList=system.cpu.fuPool.FUList4.opList
+
+[system.cpu.fuPool.FUList4.opList]
+type=OpDesc
+issueLat=1
+opClass=MemRead
+opLat=1
+
+[system.cpu.fuPool.FUList5]
+type=FUDesc
+children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
+count=4
+opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
+
+[system.cpu.fuPool.FUList5.opList00]
+type=OpDesc
+issueLat=1
+opClass=SimdAdd
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList01]
+type=OpDesc
+issueLat=1
+opClass=SimdAddAcc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList02]
+type=OpDesc
+issueLat=1
+opClass=SimdAlu
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList03]
+type=OpDesc
+issueLat=1
+opClass=SimdCmp
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList04]
+type=OpDesc
+issueLat=1
+opClass=SimdCvt
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList05]
+type=OpDesc
+issueLat=1
+opClass=SimdMisc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList06]
+type=OpDesc
+issueLat=1
+opClass=SimdMult
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList07]
+type=OpDesc
+issueLat=1
+opClass=SimdMultAcc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList08]
+type=OpDesc
+issueLat=1
+opClass=SimdShift
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList09]
+type=OpDesc
+issueLat=1
+opClass=SimdShiftAcc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList10]
+type=OpDesc
+issueLat=1
+opClass=SimdSqrt
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList11]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatAdd
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList12]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatAlu
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList13]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatCmp
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList14]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatCvt
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList15]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatDiv
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList16]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatMisc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList17]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatMult
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList18]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatMultAcc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList19]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatSqrt
+opLat=1
+
+[system.cpu.fuPool.FUList6]
+type=FUDesc
+children=opList
+count=0
+opList=system.cpu.fuPool.FUList6.opList
+
+[system.cpu.fuPool.FUList6.opList]
+type=OpDesc
+issueLat=1
+opClass=MemWrite
+opLat=1
+
+[system.cpu.fuPool.FUList7]
+type=FUDesc
+children=opList0 opList1
+count=4
+opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
+
+[system.cpu.fuPool.FUList7.opList0]
+type=OpDesc
+issueLat=1
+opClass=MemRead
+opLat=1
+
+[system.cpu.fuPool.FUList7.opList1]
+type=OpDesc
+issueLat=1
+opClass=MemWrite
+opLat=1
+
+[system.cpu.fuPool.FUList8]
+type=FUDesc
+children=opList
+count=1
+opList=system.cpu.fuPool.FUList8.opList
+
+[system.cpu.fuPool.FUList8.opList]
+type=OpDesc
+issueLat=3
+opClass=IprAccess
+opLat=3
+
+[system.cpu.icache]
+type=BaseCache
+addr_ranges=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+prefetch_on_access=false
+prefetcher=Null
+prioritizeRequests=false
+repl=Null
+size=131072
+subblock_size=0
+system=system
+tgts_per_mshr=20
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.slave[0]
+
+[system.cpu.interrupts]
+type=AlphaInterrupts
+
+[system.cpu.itb]
+type=AlphaTLB
+size=48
+
+[system.cpu.l2cache]
+type=BaseCache
+addr_ranges=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=false
+latency=1000
+max_miss_count=0
+mshrs=10
+prefetch_on_access=false
+prefetcher=Null
+prioritizeRequests=false
+repl=Null
+size=2097152
+subblock_size=0
+system=system
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.master[0]
+mem_side=system.membus.slave[1]
+
+[system.cpu.toL2Bus]
+type=CoherentBus
+block_size=64
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+master=system.cpu.l2cache.cpu_side
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=gzip input.log 1
+cwd=build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/o3-timing
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+
+[system.membus]
+type=CoherentBus
+block_size=64
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+master=system.physmem.port[0]
+slave=system.system_port system.cpu.l2cache.mem_side
+
+[system.physmem]
+type=SimpleMemory
+conf_table_reported=false
+file=
+in_addr_map=true
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.membus.master[0]
+

simulators/gem5/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simerr

@@ -0,0 +1,6 @@
+warn: Sockets disabled, not accepting gdb connections
+warn: Prefetch instructions in Alpha do not do anything
+warn: Prefetch instructions in Alpha do not do anything
+warn: Prefetch instructions in Alpha do not do anything
+warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
+hack: be nice to actually delete the event here

simulators/gem5/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simout

@@ -0,0 +1,42 @@
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jun  4 2012 11:50:11
+gem5 started Jun  4 2012 13:42:45
+gem5 executing on zizzer
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/o3-timing
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0.  Starting simulation...
+info: Increasing stack size by one page.
+spec_init
+Loading Input Data
+Duplicating 262144 bytes
+Duplicating 524288 bytes
+Input data 1048576 bytes in length
+Compressing Input Data, level 1
+Compressed data 108074 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 3
+Compressed data 97831 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 5
+Compressed data 83382 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 7
+Compressed data 76606 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 9
+Compressed data 73189 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Tested 1MB buffer: OK!
+Exiting @ tick 134621123500 because target called exit()

simulators/gem5/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt

@@ -0,0 +1,682 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds                                  0.134621                       # Number of seconds simulated
+sim_ticks                                134621123500                       # Number of ticks simulated
+final_tick                               134621123500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                 192359                       # Simulator instruction rate (inst/s)
+host_op_rate                                   192359                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               45788058                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 216172                       # Number of bytes of host memory used
+host_seconds                                  2940.09                       # Real time elapsed on the host
+sim_insts                                   565552443                       # Number of instructions simulated
+sim_ops                                     565552443                       # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu.inst             64128                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data           5873472                       # Number of bytes read from this memory
+system.physmem.bytes_read::total              5937600                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        64128                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           64128                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      3797952                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           3797952                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst               1002                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data              91773                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                 92775                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks           59343                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total                59343                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst               476359                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             43629646                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                44106005                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          476359                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             476359                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks          28212155                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               28212155                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks          28212155                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              476359                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            43629646                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               72318160                       # Total bandwidth to/from this memory (bytes/s)
+system.cpu.dtb.fetch_hits                           0                       # ITB hits
+system.cpu.dtb.fetch_misses                         0                       # ITB misses
+system.cpu.dtb.fetch_acv                            0                       # ITB acv
+system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
+system.cpu.dtb.read_hits                    123836708                       # DTB read hits
+system.cpu.dtb.read_misses                      23555                       # DTB read misses
+system.cpu.dtb.read_acv                             0                       # DTB read access violations
+system.cpu.dtb.read_accesses                123860263                       # DTB read accesses
+system.cpu.dtb.write_hits                    40831838                       # DTB write hits
+system.cpu.dtb.write_misses                     31545                       # DTB write misses
+system.cpu.dtb.write_acv                            0                       # DTB write access violations
+system.cpu.dtb.write_accesses                40863383                       # DTB write accesses
+system.cpu.dtb.data_hits                    164668546                       # DTB hits
+system.cpu.dtb.data_misses                      55100                       # DTB misses
+system.cpu.dtb.data_acv                             0                       # DTB access violations
+system.cpu.dtb.data_accesses                164723646                       # DTB accesses
+system.cpu.itb.fetch_hits                    66483943                       # ITB hits
+system.cpu.itb.fetch_misses                        37                       # ITB misses
+system.cpu.itb.fetch_acv                            0                       # ITB acv
+system.cpu.itb.fetch_accesses                66483980                       # ITB accesses
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.read_acv                             0                       # DTB read access violations
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
+system.cpu.itb.write_acv                            0                       # DTB write access violations
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.data_hits                            0                       # DTB hits
+system.cpu.itb.data_misses                          0                       # DTB misses
+system.cpu.itb.data_acv                             0                       # DTB access violations
+system.cpu.itb.data_accesses                        0                       # DTB accesses
+system.cpu.workload.num_syscalls                   17                       # Number of system calls
+system.cpu.numCycles                        269242248                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.BPredUnit.lookups                 78494350                       # Number of BP lookups
+system.cpu.BPredUnit.condPredicted           72856279                       # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect            3049613                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups              42772936                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                 41636011                       # Number of BTB hits
+system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.BPredUnit.usedRAS                  1626078                       # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect                 617                       # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles           68428248                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      710832339                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    78494350                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           43262089                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     119193912                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                12932117                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles               71677823                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                   29                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles           965                       # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines                  66483943                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                942005                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples          269174552                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.640786                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.458790                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                149980640     55.72%     55.72% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                 10366067      3.85%     59.57% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 11842490      4.40%     63.97% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 10610817      3.94%     67.91% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  6990702      2.60%     70.51% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                  2664486      0.99%     71.50% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                  3492691      1.30%     72.80% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  3105815      1.15%     73.95% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                 70120844     26.05%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::total            269174552                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.291538                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        2.640122                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 85707948                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              55913414                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 104656914                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles              13023782                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                9872494                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved              3909156                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                  1160                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              702084562                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                  4999                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                9872494                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 93982559                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                12740757                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles           2287                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 104137265                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              48439190                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              690176100                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                   220                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents               36870562                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents               5345683                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands           527299875                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups             906867454                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        906864467                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups              2987                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps             463854889                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                 63444986                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts                171                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts            186                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                 107659132                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            129005013                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            42430995                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads          14679275                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          9584938                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  626474820                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                 120                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 608397310                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            335936                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        60222555                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     33444580                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved            103                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     269174552                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         2.260233                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.839356                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            54646313     20.30%     20.30% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            54798689     20.36%     40.66% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            53375432     19.83%     60.49% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            36717503     13.64%     74.13% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            30865027     11.47%     85.60% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5            24096775      8.95%     94.55% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6            10651297      3.96%     98.51% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7             3344645      1.24%     99.75% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              678871      0.25%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       269174552                       # Number of insts issued each cycle
+system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                 2904763     73.47%     73.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                     39      0.00%     73.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     73.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     73.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     73.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     73.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     73.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     73.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     73.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     73.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     73.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     73.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     73.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     73.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     73.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     73.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     73.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     73.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     73.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     73.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     73.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     73.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     73.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     73.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     73.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     73.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     73.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     73.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     73.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                 634502     16.05%     89.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                414382     10.48%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
+system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             441013335     72.49%     72.49% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                 7329      0.00%     72.49% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     72.49% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                  32      0.00%     72.49% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   5      0.00%     72.49% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   5      0.00%     72.49% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  5      0.00%     72.49% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     72.49% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     72.49% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     72.49% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     72.49% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     72.49% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     72.49% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     72.49% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     72.49% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     72.49% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     72.49% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     72.49% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     72.49% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     72.49% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     72.49% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     72.49% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     72.49% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     72.49% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     72.49% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     72.49% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     72.49% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     72.49% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     72.49% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            126118254     20.73%     93.22% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            41258345      6.78%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::total              608397310                       # Type of FU issued
+system.cpu.iq.rate                           2.259665                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     3953686                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.006499                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         1490254859                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         686699872                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    598814509                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads                3935                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes               2431                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses         1728                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              612349032                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                    1964                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads         12165746                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
+system.cpu.iew.lsq.thread0.squashedLoads     14490971                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        33593                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation         4856                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      2979674                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
+system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
+system.cpu.iew.lsq.thread0.rescheduledLoads         6726                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked         51107                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
+system.cpu.iew.iewSquashCycles                9872494                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                 1561922                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                 98319                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           670401264                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts           1688610                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts             129005013                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             42430995                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts                120                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                  41033                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                 13811                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents           4856                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect        1345444                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect      2209649                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts              3555093                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             602577350                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             123860441                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           5819960                       # Number of squashed instructions skipped in execute
+system.cpu.iew.exec_swp                             0                       # number of swp insts executed
+system.cpu.iew.exec_nop                      43926324                       # number of nop insts executed
+system.cpu.iew.exec_refs                    164740912                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 67006670                       # Number of branches executed
+system.cpu.iew.exec_stores                   40880471                       # Number of stores executed
+system.cpu.iew.exec_rate                     2.238049                       # Inst execution rate
+system.cpu.iew.wb_sent                      600066569                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     598816237                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 417486240                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 531487841                       # num instructions consuming a value
+system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
+system.cpu.iew.wb_rate                       2.224080                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.785505                       # average fanout of values written-back
+system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu.commit.commitCommittedInsts      601856963                       # The number of committed instructions
+system.cpu.commit.commitCommittedOps        601856963                       # The number of committed instructions
+system.cpu.commit.commitSquashedInsts        68396273                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls              17                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts           3048532                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    259302058                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     2.321065                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.702332                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     80379492     31.00%     31.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     72839999     28.09%     59.09% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     26734500     10.31%     69.40% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      8121130      3.13%     72.53% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     10288458      3.97%     76.50% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5     20405541      7.87%     84.37% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      6352213      2.45%     86.82% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      3556041      1.37%     88.19% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     30624684     11.81%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    259302058                       # Number of insts commited each cycle
+system.cpu.commit.committedInsts            601856963                       # Number of instructions committed
+system.cpu.commit.committedOps              601856963                       # Number of ops (including micro ops) committed
+system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
+system.cpu.commit.refs                      153965363                       # Number of memory references committed
+system.cpu.commit.loads                     114514042                       # Number of loads committed
+system.cpu.commit.membars                           0                       # Number of memory barriers committed
+system.cpu.commit.branches                   62547159                       # Number of branches committed
+system.cpu.commit.fp_insts                       1520                       # Number of committed floating point instructions.
+system.cpu.commit.int_insts                 563954763                       # Number of committed integer instructions.
+system.cpu.commit.function_calls              1197610                       # Number of function calls committed.
+system.cpu.commit.bw_lim_events              30624684                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
+system.cpu.rob.rob_reads                    898866221                       # The number of ROB reads
+system.cpu.rob.rob_writes                  1350401622                       # The number of ROB writes
+system.cpu.timesIdled                            2160                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                           67696                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.committedInsts                   565552443                       # Number of Instructions Simulated
+system.cpu.committedOps                     565552443                       # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total             565552443                       # Number of Instructions Simulated
+system.cpu.cpi                               0.476069                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.476069                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               2.100534                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         2.100534                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                848641681                       # number of integer regfile reads
+system.cpu.int_regfile_writes               492726607                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                       387                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                       54                       # number of floating regfile writes
+system.cpu.misc_regfile_reads                       1                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
+system.cpu.icache.replacements                     49                       # number of replacements
+system.cpu.icache.tagsinuse                844.563885                       # Cycle average of tags in use
+system.cpu.icache.total_refs                 66482496                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                   1002                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs               66349.796407                       # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::cpu.inst     844.563885                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.412385                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.412385                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst     66482496                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        66482496                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      66482496                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         66482496                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     66482496                       # number of overall hits
+system.cpu.icache.overall_hits::total        66482496                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst         1447                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total          1447                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst         1447                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total           1447                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst         1447                       # number of overall misses
+system.cpu.icache.overall_misses::total          1447                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     50567500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     50567500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     50567500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     50567500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     50567500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     50567500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     66483943                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     66483943                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     66483943                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     66483943                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     66483943                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     66483943                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000022                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.000022                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000022                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.000022                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000022                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.000022                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34946.440912                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 34946.440912                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 34946.440912                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 34946.440912                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 34946.440912                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 34946.440912                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.icache.fast_writes                       0                       # number of fast writes performed
+system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst          445                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total          445                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst          445                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total          445                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst          445                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total          445                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst         1002                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total         1002                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst         1002                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total         1002                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst         1002                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total         1002                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     35750000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     35750000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     35750000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     35750000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     35750000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     35750000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000015                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000015                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000015                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.000015                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000015                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.000015                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35678.642715                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35678.642715                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35678.642715                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 35678.642715                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35678.642715                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 35678.642715                       # average overall mshr miss latency
+system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.replacements                 460743                       # number of replacements
+system.cpu.dcache.tagsinuse               4093.783086                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                149091432                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                 464839                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                 320.737787                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle              126301000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data    4093.783086                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.999459                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.999459                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data    110940808                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       110940808                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     38150562                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       38150562                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data           62                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total           62                       # number of LoadLockedReq hits
+system.cpu.dcache.demand_hits::cpu.data     149091370                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        149091370                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    149091370                       # number of overall hits
+system.cpu.dcache.overall_hits::total       149091370                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       722352                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        722352                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      1300759                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      1300759                       # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data            1                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total            1                       # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses::cpu.data      2023111                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        2023111                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      2023111                       # number of overall misses
+system.cpu.dcache.overall_misses::total       2023111                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  11755158500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  11755158500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  19630287922                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  19630287922                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data         3500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total         3500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  31385446422                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  31385446422                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  31385446422                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  31385446422                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    111663160                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    111663160                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data     39451321                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total     39451321                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data           63                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total           63                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data    151114481                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    151114481                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    151114481                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    151114481                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.006469                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.006469                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.032971                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.032971                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.015873                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.015873                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.013388                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.013388                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.013388                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.013388                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16273.449094                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 16273.449094                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 15091.410417                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 15091.410417                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data         3500                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total         3500                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 15513.457453                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 15513.457453                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 15513.457453                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 15513.457453                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs       678496                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets       191500                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs               100                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets              11                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs  6784.960000                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 17409.090909                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.writebacks::writebacks       415225                       # number of writebacks
+system.cpu.dcache.writebacks::total            415225                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       512035                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       512035                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1046237                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total      1046237                       # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data            1                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total            1                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data      1558272                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      1558272                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      1558272                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      1558272                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data       210317                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       210317                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       254522                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       254522                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data       464839                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       464839                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       464839                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       464839                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   1619332500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   1619332500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   3028681995                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   3028681995                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data   4648014495                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total   4648014495                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data   4648014495                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total   4648014495                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.001883                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.001883                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.006452                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.006452                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.003076                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.003076                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.003076                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.003076                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data  7699.484588                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total  7699.484588                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 11899.490005                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 11899.490005                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data  9999.192183                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total  9999.192183                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data  9999.192183                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total  9999.192183                       # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.l2cache.replacements                 74480                       # number of replacements
+system.cpu.l2cache.tagsinuse             17651.004599                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                  461925                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                 90375                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                  5.111203                       # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::writebacks 15915.661195                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst     39.497783                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data   1695.845621                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks     0.485707                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst     0.001205                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.051753                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.538666                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.data       178382                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total         178382                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks       415225                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total       415225                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data       194684                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       194684                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.data       373066                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total          373066                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.data       373066                       # number of overall hits
+system.cpu.l2cache.overall_hits::total         373066                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst         1002                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data        31935                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total        32937                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data        59838                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total        59838                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst         1002                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data        91773                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total         92775                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         1002                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data        91773                       # number of overall misses
+system.cpu.l2cache.overall_misses::total        92775                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     34422500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data   1098528500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total   1132951000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   2066830500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   2066830500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     34422500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data   3165359000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total   3199781500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     34422500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data   3165359000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total   3199781500                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst         1002                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data       210317                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total       211319                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks       415225                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total       415225                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       254522                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       254522                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst         1002                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data       464839                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total       465841                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst         1002                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data       464839                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total       465841                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst            1                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.151842                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.155864                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.235100                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.235100                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst            1                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.197430                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.199156                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst            1                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.197430                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.199156                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34353.792415                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34398.888367                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 34397.516471                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34540.434172                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34540.434172                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34353.792415                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34491.179323                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 34489.695500                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34353.792415                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34491.179323                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 34489.695500                       # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs       339500                       # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs               49                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs  6928.571429                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
+system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
+system.cpu.l2cache.writebacks::writebacks        59343                       # number of writebacks
+system.cpu.l2cache.writebacks::total            59343                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         1002                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        31935                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total        32937                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        59838                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total        59838                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         1002                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data        91773                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total        92775                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         1002                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data        91773                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total        92775                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     31203000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data    990467000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total   1021670000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   1878462500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   1878462500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     31203000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   2868929500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total   2900132500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     31203000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   2868929500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total   2900132500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.151842                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.155864                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.235100                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.235100                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.197430                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.199156                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.197430                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.199156                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31140.718563                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31015.093158                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31018.914898                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31392.467997                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31392.467997                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31140.718563                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31261.149794                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31259.849097                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31140.718563                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31261.149794                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31259.849097                       # average overall mshr miss latency
+system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+
+---------- End Simulation Statistics   ----------

simulators/gem5/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/config.ini

@@ -0,0 +1,117 @@
+[root]
+type=Root
+children=system
+full_system=false
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
+mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
+readfile=
+symbolfile=
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.slave[0]
+
+[system.cpu]
+type=AtomicSimpleCPU
+children=dtb interrupts itb tracer workload
+checker=Null
+clock=500
+cpu_id=0
+defer_registration=false
+do_checkpoint_insts=true
+do_quiesce=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+fastmem=false
+function_trace=false
+function_trace_start=0
+interrupts=system.cpu.interrupts
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+phase=0
+profile=0
+progress_interval=0
+simulate_data_stalls=false
+simulate_inst_stalls=false
+system=system
+tracer=system.cpu.tracer
+width=1
+workload=system.cpu.workload
+dcache_port=system.membus.slave[2]
+icache_port=system.membus.slave[1]
+
+[system.cpu.dtb]
+type=AlphaTLB
+size=64
+
+[system.cpu.interrupts]
+type=AlphaInterrupts
+
+[system.cpu.itb]
+type=AlphaTLB
+size=48
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=gzip input.log 1
+cwd=build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/simple-atomic
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+
+[system.membus]
+type=CoherentBus
+block_size=64
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+master=system.physmem.port[0]
+slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
+
+[system.physmem]
+type=SimpleMemory
+conf_table_reported=false
+file=
+in_addr_map=true
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.membus.master[0]
+

simulators/gem5/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/simerr

@@ -0,0 +1,7 @@
+warn: CoherentBus system.membus has no snooping ports attached!
+warn: Sockets disabled, not accepting gdb connections
+warn: Prefetch instructions in Alpha do not do anything
+warn: Prefetch instructions in Alpha do not do anything
+warn: Prefetch instructions in Alpha do not do anything
+warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
+hack: be nice to actually delete the event here

simulators/gem5/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/simout

@@ -0,0 +1,42 @@
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jun  4 2012 11:50:11
+gem5 started Jun  4 2012 14:03:38
+gem5 executing on zizzer
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/simple-atomic
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0.  Starting simulation...
+info: Increasing stack size by one page.
+spec_init
+Loading Input Data
+Duplicating 262144 bytes
+Duplicating 524288 bytes
+Input data 1048576 bytes in length
+Compressing Input Data, level 1
+Compressed data 108074 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 3
+Compressed data 97831 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 5
+Compressed data 83382 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 7
+Compressed data 76606 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 9
+Compressed data 73189 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Tested 1MB buffer: OK!
+Exiting @ tick 300930958000 because target called exit()

simulators/gem5/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt

@@ -0,0 +1,92 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds                                  0.300931                       # Number of seconds simulated
+sim_ticks                                300930958000                       # Number of ticks simulated
+final_tick                               300930958000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                3871430                       # Simulator instruction rate (inst/s)
+host_op_rate                                  3871429                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1935730316                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 206040                       # Number of bytes of host memory used
+host_seconds                                   155.46                       # Real time elapsed on the host
+sim_insts                                   601856964                       # Number of instructions simulated
+sim_ops                                     601856964                       # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu.inst        2407447588                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data         375543340                       # Number of bytes read from this memory
+system.physmem.bytes_read::total           2782990928                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst   2407447588                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total      2407447588                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::cpu.data      152669504                       # Number of bytes written to this memory
+system.physmem.bytes_written::total         152669504                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst          601861897                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data          114514042                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total             716375939                       # Number of read requests responded to by this memory
+system.physmem.num_writes::cpu.data          39451321                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total             39451321                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst           7999999747                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data           1247938539                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              9247938286                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst      7999999747                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total         7999999747                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data           507324022                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total              507324022                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst          7999999747                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data          1755262561                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total             9755262308                       # Total bandwidth to/from this memory (bytes/s)
+system.cpu.dtb.fetch_hits                           0                       # ITB hits
+system.cpu.dtb.fetch_misses                         0                       # ITB misses
+system.cpu.dtb.fetch_acv                            0                       # ITB acv
+system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
+system.cpu.dtb.read_hits                    114514042                       # DTB read hits
+system.cpu.dtb.read_misses                       2631                       # DTB read misses
+system.cpu.dtb.read_acv                             0                       # DTB read access violations
+system.cpu.dtb.read_accesses                114516673                       # DTB read accesses
+system.cpu.dtb.write_hits                    39451321                       # DTB write hits
+system.cpu.dtb.write_misses                      2302                       # DTB write misses
+system.cpu.dtb.write_acv                            0                       # DTB write access violations
+system.cpu.dtb.write_accesses                39453623                       # DTB write accesses
+system.cpu.dtb.data_hits                    153965363                       # DTB hits
+system.cpu.dtb.data_misses                       4933                       # DTB misses
+system.cpu.dtb.data_acv                             0                       # DTB access violations
+system.cpu.dtb.data_accesses                153970296                       # DTB accesses
+system.cpu.itb.fetch_hits                   601861897                       # ITB hits
+system.cpu.itb.fetch_misses                        20                       # ITB misses
+system.cpu.itb.fetch_acv                            0                       # ITB acv
+system.cpu.itb.fetch_accesses               601861917                       # ITB accesses
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.read_acv                             0                       # DTB read access violations
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
+system.cpu.itb.write_acv                            0                       # DTB write access violations
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.data_hits                            0                       # DTB hits
+system.cpu.itb.data_misses                          0                       # DTB misses
+system.cpu.itb.data_acv                             0                       # DTB access violations
+system.cpu.itb.data_accesses                        0                       # DTB accesses
+system.cpu.workload.num_syscalls                   17                       # Number of system calls
+system.cpu.numCycles                        601861917                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.committedInsts                   601856964                       # Number of instructions committed
+system.cpu.committedOps                     601856964                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses             563959696                       # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses                   1520                       # Number of float alu accesses
+system.cpu.num_func_calls                     2395217                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts     58554292                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                    563959696                       # number of integer instructions
+system.cpu.num_fp_insts                          1520                       # number of float instructions
+system.cpu.num_int_register_reads           801088993                       # number of times the integer registers were read
+system.cpu.num_int_register_writes          463854847                       # number of times the integer registers were written
+system.cpu.num_fp_register_reads                  169                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes                  42                       # number of times the floating registers were written
+system.cpu.num_mem_refs                     153970296                       # number of memory refs
+system.cpu.num_load_insts                   114516673                       # Number of load instructions
+system.cpu.num_store_insts                   39453623                       # Number of store instructions
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
+system.cpu.num_busy_cycles                  601861917                       # Number of busy cycles
+system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                            0                       # Percentage of idle cycles
+
+---------- End Simulation Statistics   ----------

simulators/gem5/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/config.ini

@@ -0,0 +1,198 @@
+[root]
+type=Root
+children=system
+full_system=false
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
+mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
+readfile=
+symbolfile=
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.slave[0]
+
+[system.cpu]
+type=TimingSimpleCPU
+children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
+checker=Null
+clock=500
+cpu_id=0
+defer_registration=false
+do_checkpoint_insts=true
+do_quiesce=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+function_trace=false
+function_trace_start=0
+interrupts=system.cpu.interrupts
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+phase=0
+profile=0
+progress_interval=0
+system=system
+tracer=system.cpu.tracer
+workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.dcache]
+type=BaseCache
+addr_ranges=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+prefetch_on_access=false
+prefetcher=Null
+prioritizeRequests=false
+repl=Null
+size=262144
+subblock_size=0
+system=system
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.slave[1]
+
+[system.cpu.dtb]
+type=AlphaTLB
+size=64
+
+[system.cpu.icache]
+type=BaseCache
+addr_ranges=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+prefetch_on_access=false
+prefetcher=Null
+prioritizeRequests=false
+repl=Null
+size=131072
+subblock_size=0
+system=system
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.slave[0]
+
+[system.cpu.interrupts]
+type=AlphaInterrupts
+
+[system.cpu.itb]
+type=AlphaTLB
+size=48
+
+[system.cpu.l2cache]
+type=BaseCache
+addr_ranges=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=false
+latency=10000
+max_miss_count=0
+mshrs=10
+prefetch_on_access=false
+prefetcher=Null
+prioritizeRequests=false
+repl=Null
+size=2097152
+subblock_size=0
+system=system
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.master[0]
+mem_side=system.membus.slave[1]
+
+[system.cpu.toL2Bus]
+type=CoherentBus
+block_size=64
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+master=system.cpu.l2cache.cpu_side
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=gzip input.log 1
+cwd=build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/simple-timing
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+
+[system.membus]
+type=CoherentBus
+block_size=64
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+master=system.physmem.port[0]
+slave=system.system_port system.cpu.l2cache.mem_side
+
+[system.physmem]
+type=SimpleMemory
+conf_table_reported=false
+file=
+in_addr_map=true
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.membus.master[0]
+

simulators/gem5/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/simerr

@@ -0,0 +1,6 @@
+warn: Sockets disabled, not accepting gdb connections
+warn: Prefetch instructions in Alpha do not do anything
+warn: Prefetch instructions in Alpha do not do anything
+warn: Prefetch instructions in Alpha do not do anything
+warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
+hack: be nice to actually delete the event here

simulators/gem5/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/simout

@@ -0,0 +1,42 @@
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jun  4 2012 11:50:11
+gem5 started Jun  4 2012 13:42:36
+gem5 executing on zizzer
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/simple-timing
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0.  Starting simulation...
+info: Increasing stack size by one page.
+spec_init
+Loading Input Data
+Duplicating 262144 bytes
+Duplicating 524288 bytes
+Input data 1048576 bytes in length
+Compressing Input Data, level 1
+Compressed data 108074 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 3
+Compressed data 97831 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 5
+Compressed data 83382 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 7
+Compressed data 76606 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 9
+Compressed data 73189 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Tested 1MB buffer: OK!
+Exiting @ tick 765623032000 because target called exit()

simulators/gem5/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/stats.txt

@@ -0,0 +1,406 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds                                  0.765623                       # Number of seconds simulated
+sim_ticks                                765623032000                       # Number of ticks simulated
+final_tick                               765623032000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                1675799                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1675799                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2131786057                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 214908                       # Number of bytes of host memory used
+host_seconds                                   359.15                       # Real time elapsed on the host
+sim_insts                                   601856964                       # Number of instructions simulated
+sim_ops                                     601856964                       # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu.inst             50880                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data           5839104                       # Number of bytes read from this memory
+system.physmem.bytes_read::total              5889984                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        50880                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           50880                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      3797824                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           3797824                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst                795                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data              91236                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                 92031                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks           59341                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total                59341                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst                66456                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              7626604                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 7693060                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst           66456                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total              66456                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           4960436                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                4960436                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           4960436                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst               66456                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             7626604                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               12653496                       # Total bandwidth to/from this memory (bytes/s)
+system.cpu.dtb.fetch_hits                           0                       # ITB hits
+system.cpu.dtb.fetch_misses                         0                       # ITB misses
+system.cpu.dtb.fetch_acv                            0                       # ITB acv
+system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
+system.cpu.dtb.read_hits                    114514042                       # DTB read hits
+system.cpu.dtb.read_misses                       2631                       # DTB read misses
+system.cpu.dtb.read_acv                             0                       # DTB read access violations
+system.cpu.dtb.read_accesses                114516673                       # DTB read accesses
+system.cpu.dtb.write_hits                    39451321                       # DTB write hits
+system.cpu.dtb.write_misses                      2302                       # DTB write misses
+system.cpu.dtb.write_acv                            0                       # DTB write access violations
+system.cpu.dtb.write_accesses                39453623                       # DTB write accesses
+system.cpu.dtb.data_hits                    153965363                       # DTB hits
+system.cpu.dtb.data_misses                       4933                       # DTB misses
+system.cpu.dtb.data_acv                             0                       # DTB access violations
+system.cpu.dtb.data_accesses                153970296                       # DTB accesses
+system.cpu.itb.fetch_hits                   601861898                       # ITB hits
+system.cpu.itb.fetch_misses                        20                       # ITB misses
+system.cpu.itb.fetch_acv                            0                       # ITB acv
+system.cpu.itb.fetch_accesses               601861918                       # ITB accesses
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.read_acv                             0                       # DTB read access violations
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
+system.cpu.itb.write_acv                            0                       # DTB write access violations
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.data_hits                            0                       # DTB hits
+system.cpu.itb.data_misses                          0                       # DTB misses
+system.cpu.itb.data_acv                             0                       # DTB access violations
+system.cpu.itb.data_accesses                        0                       # DTB accesses
+system.cpu.workload.num_syscalls                   17                       # Number of system calls
+system.cpu.numCycles                       1531246064                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.committedInsts                   601856964                       # Number of instructions committed
+system.cpu.committedOps                     601856964                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses             563959696                       # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses                   1520                       # Number of float alu accesses
+system.cpu.num_func_calls                     2395217                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts     58554292                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                    563959696                       # number of integer instructions
+system.cpu.num_fp_insts                          1520                       # number of float instructions
+system.cpu.num_int_register_reads           801088993                       # number of times the integer registers were read
+system.cpu.num_int_register_writes          463854847                       # number of times the integer registers were written
+system.cpu.num_fp_register_reads                  169                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes                  42                       # number of times the floating registers were written
+system.cpu.num_mem_refs                     153970296                       # number of memory refs
+system.cpu.num_load_insts                   114516673                       # Number of load instructions
+system.cpu.num_store_insts                   39453623                       # Number of store instructions
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
+system.cpu.num_busy_cycles                 1531246064                       # Number of busy cycles
+system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                            0                       # Percentage of idle cycles
+system.cpu.icache.replacements                     24                       # number of replacements
+system.cpu.icache.tagsinuse                673.337154                       # Cycle average of tags in use
+system.cpu.icache.total_refs                601861103                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                    795                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs               757057.991195                       # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::cpu.inst     673.337154                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.328778                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.328778                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst    601861103                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       601861103                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     601861103                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        601861103                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    601861103                       # number of overall hits
+system.cpu.icache.overall_hits::total       601861103                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst          795                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total           795                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst          795                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total            795                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst          795                       # number of overall misses
+system.cpu.icache.overall_misses::total           795                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     44520000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     44520000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     44520000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     44520000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     44520000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     44520000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    601861898                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    601861898                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    601861898                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    601861898                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    601861898                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    601861898                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000001                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.000001                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000001                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.000001                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000001                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.000001                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst        56000                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total        56000                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst        56000                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total        56000                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst        56000                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total        56000                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.icache.fast_writes                       0                       # number of fast writes performed
+system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst          795                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total          795                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst          795                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total          795                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst          795                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total          795                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     42135000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     42135000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     42135000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     42135000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     42135000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     42135000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000001                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000001                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000001                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.000001                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000001                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.000001                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst        53000                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total        53000                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst        53000                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total        53000                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst        53000                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total        53000                       # average overall mshr miss latency
+system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.replacements                 451299                       # number of replacements
+system.cpu.dcache.tagsinuse               4094.170317                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                153509968                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                 455395                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                 337.091905                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle              578392000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data    4094.170317                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.999553                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.999553                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data    114312810                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       114312810                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     39197158                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       39197158                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data     153509968                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        153509968                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    153509968                       # number of overall hits
+system.cpu.dcache.overall_hits::total       153509968                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       201232                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        201232                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       254163                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       254163                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data       455395                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total         455395                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data       455395                       # number of overall misses
+system.cpu.dcache.overall_misses::total        455395                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data   4126262000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total   4126262000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data   6081180000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   6081180000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  10207442000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  10207442000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  10207442000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  10207442000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    114514042                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    114514042                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data     39451321                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total     39451321                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data    153965363                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    153965363                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    153965363                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    153965363                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.001757                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.001757                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.006442                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.006442                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.002958                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.002958                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.002958                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.002958                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20504.999205                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 20504.999205                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 23926.299265                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 23926.299265                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 22414.479737                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 22414.479737                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 22414.479737                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 22414.479737                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.writebacks::writebacks       408190                       # number of writebacks
+system.cpu.dcache.writebacks::total            408190                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data       201232                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       201232                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       254163                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       254163                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data       455395                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       455395                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       455395                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       455395                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   3522566000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   3522566000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   5318691000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   5318691000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data   8841257000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total   8841257000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data   8841257000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total   8841257000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.001757                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.001757                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.006442                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.006442                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.002958                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.002958                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.002958                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.002958                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17504.999205                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17504.999205                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 20926.299265                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 20926.299265                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19414.479737                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 19414.479737                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19414.479737                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 19414.479737                       # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.l2cache.replacements                 73734                       # number of replacements
+system.cpu.l2cache.tagsinuse             17823.514890                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                  445709                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                 89622                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                  4.973210                       # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::writebacks 16101.078831                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst     29.487971                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data   1692.948088                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks     0.491366                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst     0.000900                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.051665                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.543931                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.data       170065                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total         170065                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks       408190                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total       408190                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data       194094                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       194094                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.data       364159                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total          364159                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.data       364159                       # number of overall hits
+system.cpu.l2cache.overall_hits::total         364159                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst          795                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data        31167                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total        31962                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data        60069                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total        60069                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst          795                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data        91236                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total         92031                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst          795                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data        91236                       # number of overall misses
+system.cpu.l2cache.overall_misses::total        92031                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     41340000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data   1620684000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total   1662024000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   3123588000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   3123588000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     41340000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data   4744272000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total   4785612000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     41340000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data   4744272000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total   4785612000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst          795                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data       201232                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total       202027                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks       408190                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total       408190                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       254163                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       254163                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst          795                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data       455395                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total       456190                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst          795                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data       455395                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total       456190                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst            1                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.154881                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.158207                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.236340                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.236340                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst            1                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.200345                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.201738                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst            1                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.200345                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.201738                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst        52000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data        52000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total        52000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data        52000                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total        52000                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data        52000                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total        52000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data        52000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total        52000                       # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
+system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
+system.cpu.l2cache.writebacks::writebacks        59341                       # number of writebacks
+system.cpu.l2cache.writebacks::total            59341                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          795                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        31167                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total        31962                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        60069                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total        60069                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst          795                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data        91236                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total        92031                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst          795                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data        91236                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total        92031                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     31800000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   1246680000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total   1278480000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   2402760000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   2402760000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     31800000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   3649440000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total   3681240000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     31800000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   3649440000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total   3681240000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.154881                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.158207                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.236340                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.236340                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.200345                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.201738                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.200345                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.201738                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst        40000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total        40000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total        40000                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total        40000                       # average overall mshr miss latency
+system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+
+---------- End Simulation Statistics   ----------