Adding gem5 source to svn.
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1819 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
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friemel
161
simulators/gem5/system/alpha/console/paljtoslave.S
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simulators/gem5/system/alpha/console/paljtoslave.S
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/*
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* Copyright (c) 2003-2004 The Regents of The University of Michigan
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* Copyright (c) 1993 The Hewlett-Packard Development Company
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "dc21164FromGasSources.h" // DECchip 21164 specific definitions
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#include "ev5_defs.h"
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#include "fromHudsonOsf.h" // OSF/1 specific definitions
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#include "fromHudsonMacros.h" // Global macro definitions
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/*
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* args:
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* a0: here
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* a1: boot location
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* a2: CSERVE_J_KTOPAL
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* a3: restrart_pv
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* a4: vptb
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* a5: my_rpb
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*
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* SRM Console Architecture III 3-26
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*/
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.global palJToSlave
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.text 3
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palJToSlave:
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ALIGN_BRANCH
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bis a3, zero, pv
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bis zero, zero, t11
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bis zero, zero, ra
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/* Point the Vptbr to a2 */
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mtpr a4, mVptBr // Load Mbox copy
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mtpr a4, iVptBr // Load Ibox copy
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STALL // don't dual issue the load with mtpr -pb
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/* Turn on superpage mapping in the mbox and icsr */
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lda t0, (2<<MCSR_V_SP)(zero) // Get a '10' (binary) in MCSR<SP>
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STALL // don't dual issue the load with mtpr -pb
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mtpr t0, mcsr // Set the super page mode enable bit
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STALL // don't dual issue the load with mtpr -pb
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lda t0, 0(zero)
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mtpr t0, dtbAsn
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mtpr t0, itbAsn
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LDLI (t1,0x20000000)
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STALL // don't dual issue the load with mtpr -pb
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mfpr t0, icsr // Enable superpage mapping
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STALL // don't dual issue the load with mtpr -pb
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bis t0, t1, t0
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mtpr t0, icsr
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STALL // Required stall to update chip ...
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STALL
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STALL
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STALL
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STALL
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ldq_p s0, PCB_Q_PTBR(a5)
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sll s0, VA_S_OFF, s0 // Shift PTBR into position
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STALL // don't dual issue the load with mtpr -pb
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mtpr s0, ptPtbr // PHYSICAL MBOX INST -> MT PT20 IN 0,1
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STALL // don't dual issue the load with mtpr -pb
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ldq_p sp, PCB_Q_KSP(a5)
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mtpr zero, dtbIa // Flush all D-stream TB entries
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mtpr zero, itbIa // Flush all I-stream TB entries
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mtpr a1, excAddr // Load the dispatch address.
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STALL // don't dual issue the load with mtpr -pb
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STALL // don't dual issue the load with mtpr -pb
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mtpr zero, dtbIa // Flush all D-stream TB entries
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mtpr zero, itbIa // Flush all I-stream TB entries
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br zero, 2f
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ALIGN_BLOCK
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2: NOP
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mtpr zero, icFlush // Flush the icache.
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NOP
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NOP
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NOP // Required NOPs ... 1-10
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NOP
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NOP
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NOP
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NOP
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NOP
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NOP
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NOP
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NOP
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NOP
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NOP // Required NOPs ... 11-20
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NOP
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NOP
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NOP
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NOP
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NOP
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NOP
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NOP
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NOP
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NOP
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NOP // Required NOPs ... 21-30
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NOP
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NOP
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NOP
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NOP
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NOP
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NOP
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NOP
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NOP
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NOP
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NOP // Required NOPs ... 31-40
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NOP
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NOP
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NOP
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NOP
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NOP
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NOP
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NOP
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NOP
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NOP
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NOP // Required NOPs ... 41-44
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NOP
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NOP
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NOP
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hw_rei_stall // Dispatch to kernel
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