Adding gem5 source to svn.
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1819 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
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friemel
213
simulators/gem5/system/alpha/console/dbmentry.S
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213
simulators/gem5/system/alpha/console/dbmentry.S
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/*
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* Copyright (c) 2003-2004 The Regents of The University of Michigan
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* Copyright (c) 1993 The Hewlett-Packard Development Company
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Debug Monitor Entry code
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*/
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#include "fromHudsonOsf.h"
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.extern myAlphaAccess
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.text
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/* return address and padding to octaword align */
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#define STARTFRM 16
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.globl _start
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.ent _start, 0
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_start:
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_entry:
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br t0, 2f # get the current PC
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2: ldgp gp, 0(t0) # init gp
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/* Processor 0 start stack frame is begining of physical memory (0)
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Other processors spin here waiting to get their stacks from
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Processor 0, then they can progress as normal.
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*/
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call_pal PAL_WHAMI_ENTRY
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beq v0, cpuz
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ldq t3, m5AlphaAccess
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addq t3,0x70,t3 # *** If offset in console alpha access struct changes
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# This must be changed as well!
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bis zero,8,t4
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mulq t4,v0,t4
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addq t3,t4,t3
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ldah a0, 3(zero) # load arg0 with 65536*3
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cpuwait: .long 0x6000002 # jsr quiesceNs
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ldq t4, 0(t3)
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beq t4, cpuwait
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bis t4,t4,sp
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cpuz: bis sp,sp,s0 /* save sp */
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slave: lda v0,(8*1024)(sp) /* end of page */
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subq zero, 1, t0
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sll t0, 42, t0
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bis t0, v0, sp
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lda sp, -STARTFRM(sp) # Create a stack frame
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stq ra, 0(sp) # Place return address on the stack
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.mask 0x84000000, -8
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.frame sp, STARTFRM, ra
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/*
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* Enable the Floating Point Unit
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*/
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lda a0, 1(zero)
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call_pal PAL_WRFEN_ENTRY
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/*
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* Every good C program has a main()
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*/
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/* If stack pointer was 0, then this is CPU0*/
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beq s0,master
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call_pal PAL_WHAMI_ENTRY
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bis v0,v0,a0
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jsr ra, SlaveLoop
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master:
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jsr ra, main
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/*
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* The Debug Monitor should never return.
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* However, just incase...
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*/
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ldgp gp, 0(ra)
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bsr zero, _exit
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.end _start
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.globl _exit
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.ent _exit, 0
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_exit:
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ldq ra, 0(sp) # restore return address
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lda sp, STARTFRM(sp) # prune back the stack
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ret zero, (ra) # Back from whence we came
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.end _exit
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.globl cServe
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.ent cServe 2
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cServe:
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.option O1
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.frame sp, 0, ra
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call_pal PAL_CSERVE_ENTRY
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ret zero, (ra)
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.end cServe
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.globl wrfen
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.ent wrfen 2
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wrfen:
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.option O1
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.frame sp, 0, ra
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call_pal PAL_WRFEN_ENTRY
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ret zero, (ra)
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.end wrfen
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.globl consoleCallback
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.ent consoleCallback 2
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consoleCallback:
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br t0, 2f # get the current PC
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2: ldgp gp, 0(t0) # init gp
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lda sp,-64(sp)
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stq ra,0(sp)
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jsr CallBackDispatcher
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ldq ra,0(sp)
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lda sp,64(sp)
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ret zero,(ra)
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.end consoleCallback
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.globl consoleFixup
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.ent consoleFixup 2
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consoleFixup:
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br t0, 2f # get the current PC
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2: ldgp gp, 0(t0) # init gp
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lda sp,-64(sp)
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stq ra,0(sp)
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jsr CallBackFixup
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ldq ra,0(sp)
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lda sp,64(sp)
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ret zero,(ra)
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.end consoleFixup
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.globl SpinLock
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.ent SpinLock 2
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SpinLock:
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1:
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ldq_l a1,0(a0) # interlock complete lock state
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subl ra,3,v0 # get calling addr[31:0] + 1
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blbs a1,2f # branch if lock is busy
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stq_c v0,0(a0) # attempt to acquire lock
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beq v0,2f # branch if lost atomicity
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mb # ensure memory coherence
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ret zero,(ra) # return to caller (v0 is 1)
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2:
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br zero,1b
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.end SpinLock
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.globl loadContext
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.ent loadContext 2
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loadContext:
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.option O1
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.frame sp, 0, ra
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call_pal PAL_SWPCTX_ENTRY
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ret zero, (ra)
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.end loadContext
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.globl SlaveSpin # Very carefully spin wait
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.ent SlaveSpin 2 # and swap context without
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SlaveSpin: # using any stack space
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.option O1
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.frame sp, 0, ra
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mov a0, t0 # cpu number
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mov a1, t1 # cpu rpb pointer (virtual)
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mov a2, t2 # what to spin on
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ldah a0, 3(zero) # load arg0 with 65536
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test: .long 0x6000002 # jsr quiesceNs # wait 65us*3
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ldl t3, 0(t2)
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beq t3, test
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zapnot t1,0x1f,a0 # make rpb physical
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call_pal PAL_SWPCTX_ENTRY # switch to pcb
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mov t0, a0 # setup args for SlaveCmd
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mov t1, a1
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jsr SlaveCmd # call SlaveCmd
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ret zero, (ra) # Should never be reached
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.end SlaveSpin
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