Adding gem5 source to svn.
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1819 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
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friemel
406
simulators/gem5/src/sim/system.hh
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406
simulators/gem5/src/sim/system.hh
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/*
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* Copyright (c) 2012 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2002-2005 The Regents of The University of Michigan
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* Copyright (c) 2011 Regents of the University of California
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Steve Reinhardt
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* Lisa Hsu
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* Nathan Binkert
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* Rick Strong
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*/
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#ifndef __SYSTEM_HH__
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#define __SYSTEM_HH__
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#include <string>
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#include <vector>
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#include "base/loader/symtab.hh"
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#include "base/misc.hh"
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#include "base/statistics.hh"
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#include "cpu/pc_event.hh"
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#include "enums/MemoryMode.hh"
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#include "kern/system_events.hh"
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#include "mem/fs_translating_port_proxy.hh"
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#include "mem/mem_object.hh"
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#include "mem/port.hh"
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#include "mem/physical.hh"
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#include "params/System.hh"
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class BaseCPU;
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class BaseRemoteGDB;
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class GDBListener;
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class ObjectFile;
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class Platform;
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class ThreadContext;
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class System : public MemObject
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{
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private:
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/**
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* Private class for the system port which is only used as a
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* master for debug access and for non-structural entities that do
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* not have a port of their own.
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*/
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class SystemPort : public MasterPort
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{
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public:
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/**
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* Create a system port with a name and an owner.
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*/
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SystemPort(const std::string &_name, MemObject *_owner)
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: MasterPort(_name, _owner)
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{ }
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bool recvTimingResp(PacketPtr pkt)
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{ panic("SystemPort does not receive timing!\n"); return false; }
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void recvRetry()
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{ panic("SystemPort does not expect retry!\n"); }
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};
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SystemPort _systemPort;
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public:
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/**
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* After all objects have been created and all ports are
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* connected, check that the system port is connected.
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*/
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virtual void init();
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/**
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* Get a reference to the system port that can be used by
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* non-structural simulation objects like processes or threads, or
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* external entities like loaders and debuggers, etc, to access
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* the memory system.
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*
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* @return a reference to the system port we own
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*/
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MasterPort& getSystemPort() { return _systemPort; }
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/**
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* Additional function to return the Port of a memory object.
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*/
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MasterPort& getMasterPort(const std::string &if_name, int idx = -1);
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static const char *MemoryModeStrings[3];
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Enums::MemoryMode
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getMemoryMode()
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{
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assert(memoryMode);
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return memoryMode;
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}
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/** Change the memory mode of the system. This should only be called by the
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* python!!
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* @param mode Mode to change to (atomic/timing)
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*/
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void setMemoryMode(Enums::MemoryMode mode);
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PCEventQueue pcEventQueue;
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std::vector<ThreadContext *> threadContexts;
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int _numContexts;
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ThreadContext *getThreadContext(ThreadID tid)
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{
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return threadContexts[tid];
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}
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int numContexts()
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{
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assert(_numContexts == (int)threadContexts.size());
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return _numContexts;
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}
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/** Return number of running (non-halted) thread contexts in
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* system. These threads could be Active or Suspended. */
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int numRunningContexts();
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Addr pagePtr;
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uint64_t init_param;
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/** Port to physical memory used for writing object files into ram at
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* boot.*/
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PortProxy physProxy;
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FSTranslatingPortProxy virtProxy;
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/** kernel symbol table */
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SymbolTable *kernelSymtab;
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/** Object pointer for the kernel code */
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ObjectFile *kernel;
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/** Begining of kernel code */
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Addr kernelStart;
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/** End of kernel code */
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Addr kernelEnd;
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/** Entry point in the kernel to start at */
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Addr kernelEntry;
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/** Mask that should be anded for binary/symbol loading.
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* This allows one two different OS requirements for the same ISA to be
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* handled. Some OSes are compiled for a virtual address and need to be
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* loaded into physical memory that starts at address 0, while other
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* bare metal tools generate images that start at address 0.
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*/
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Addr loadAddrMask;
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protected:
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uint64_t nextPID;
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public:
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uint64_t allocatePID()
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{
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return nextPID++;
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}
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/** Get a pointer to access the physical memory of the system */
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PhysicalMemory& getPhysMem() { return physmem; }
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/** Amount of physical memory that is still free */
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Addr freeMemSize() const;
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/** Amount of physical memory that exists */
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Addr memSize() const;
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/**
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* Check if a physical address is within a range of a memory that
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* is part of the global address map.
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*
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* @param addr A physical address
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* @return Whether the address corresponds to a memory
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*/
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bool isMemAddr(Addr addr) const;
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protected:
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PhysicalMemory physmem;
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Enums::MemoryMode memoryMode;
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uint64_t workItemsBegin;
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uint64_t workItemsEnd;
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uint32_t numWorkIds;
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std::vector<bool> activeCpus;
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/** This array is a per-sytem list of all devices capable of issuing a
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* memory system request and an associated string for each master id.
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* It's used to uniquely id any master in the system by name for things
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* like cache statistics.
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*/
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std::vector<std::string> masterIds;
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public:
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/** Request an id used to create a request object in the system. All objects
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* that intend to issues requests into the memory system must request an id
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* in the init() phase of startup. All master ids must be fixed by the
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* regStats() phase that immediately preceeds it. This allows objects in the
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* memory system to understand how many masters may exist and
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* appropriately name the bins of their per-master stats before the stats
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* are finalized
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*/
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MasterID getMasterId(std::string req_name);
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/** Get the name of an object for a given request id.
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*/
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std::string getMasterName(MasterID master_id);
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/** Get the number of masters registered in the system */
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MasterID maxMasters()
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{
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return masterIds.size();
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}
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virtual void regStats();
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/**
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* Called by pseudo_inst to track the number of work items started by this
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* system.
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*/
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uint64_t
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incWorkItemsBegin()
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{
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return ++workItemsBegin;
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}
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/**
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* Called by pseudo_inst to track the number of work items completed by
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* this system.
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*/
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uint64_t
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incWorkItemsEnd()
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{
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return ++workItemsEnd;
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}
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/**
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* Called by pseudo_inst to mark the cpus actively executing work items.
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* Returns the total number of cpus that have executed work item begin or
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* ends.
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*/
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int
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markWorkItem(int index)
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{
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int count = 0;
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assert(index < activeCpus.size());
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activeCpus[index] = true;
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for (std::vector<bool>::iterator i = activeCpus.begin();
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i < activeCpus.end(); i++) {
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if (*i) count++;
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}
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return count;
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}
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inline void workItemBegin(uint32_t tid, uint32_t workid)
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{
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std::pair<uint32_t,uint32_t> p(tid, workid);
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lastWorkItemStarted[p] = curTick();
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}
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void workItemEnd(uint32_t tid, uint32_t workid);
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/**
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* Fix up an address used to match PCs for hooking simulator
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* events on to target function executions. See comment in
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* system.cc for details.
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*/
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virtual Addr fixFuncEventAddr(Addr addr)
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{
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panic("Base fixFuncEventAddr not implemented.\n");
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}
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/**
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* Add a function-based event to the given function, to be looked
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* up in the specified symbol table.
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*/
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template <class T>
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T *addFuncEvent(SymbolTable *symtab, const char *lbl)
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{
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Addr addr = 0; // initialize only to avoid compiler warning
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if (symtab->findAddress(lbl, addr)) {
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T *ev = new T(&pcEventQueue, lbl, fixFuncEventAddr(addr));
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return ev;
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}
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return NULL;
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}
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/** Add a function-based event to kernel code. */
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template <class T>
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T *addKernelFuncEvent(const char *lbl)
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{
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return addFuncEvent<T>(kernelSymtab, lbl);
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}
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public:
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std::vector<BaseRemoteGDB *> remoteGDB;
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std::vector<GDBListener *> gdbListen;
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bool breakpoint();
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public:
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typedef SystemParams Params;
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protected:
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Params *_params;
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public:
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System(Params *p);
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~System();
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void initState();
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const Params *params() const { return (const Params *)_params; }
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public:
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/**
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* Returns the addess the kernel starts at.
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* @return address the kernel starts at
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*/
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Addr getKernelStart() const { return kernelStart; }
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/**
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* Returns the addess the kernel ends at.
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* @return address the kernel ends at
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*/
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Addr getKernelEnd() const { return kernelEnd; }
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/**
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* Returns the addess the entry point to the kernel code.
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* @return entry point of the kernel code
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*/
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Addr getKernelEntry() const { return kernelEntry; }
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/// Allocate npages contiguous unused physical pages
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/// @return Starting address of first page
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Addr allocPhysPages(int npages);
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int registerThreadContext(ThreadContext *tc, int assigned=-1);
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void replaceThreadContext(ThreadContext *tc, int context_id);
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void serialize(std::ostream &os);
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void unserialize(Checkpoint *cp, const std::string §ion);
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virtual void resume();
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public:
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Counter totalNumInsts;
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EventQueue instEventQueue;
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std::map<std::pair<uint32_t,uint32_t>, Tick> lastWorkItemStarted;
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std::map<uint32_t, Stats::Histogram*> workItemStats;
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////////////////////////////////////////////
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//
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// STATIC GLOBAL SYSTEM LIST
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//
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////////////////////////////////////////////
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static std::vector<System *> systemList;
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static int numSystemsRunning;
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static void printSystems();
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};
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#endif // __SYSTEM_HH__
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