Adding gem5 source to svn.
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1819 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
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friemel
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simulators/gem5/src/python/m5/util/dot_writer.py
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179
simulators/gem5/src/python/m5/util/dot_writer.py
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# Copyright (c) 2012 ARM Limited
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# All rights reserved.
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#
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# The license below extends only to copyright in the software and shall
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# not be construed as granting a license to any other intellectual
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# property including but not limited to intellectual property relating
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# to a hardware implementation of the functionality of the software
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# licensed hereunder. You may use the software subject to the license
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# terms below provided that you ensure that this notice is replicated
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# unmodified and in its entirety in all distributions of the software,
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# modified or unmodified, in source code or in binary form.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Andreas Hansson
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# Uri Wiener
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#####################################################################
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#
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# System visualization using DOT
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#
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# While config.ini and config.json provide an almost complete listing
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# of a system's components and connectivity, they lack a birds-eye view.
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# The output generated by do_dot() is a DOT-based figure (pdf) and its
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# source dot code. Nodes are components, and edges represent
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# the memory hierarchy: the edges are directed, from a master to a slave.
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# Initially all nodes are generated, and then all edges are added.
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# do_dot should be called with the top-most SimObject (namely root
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# but not necessarily), the output folder and the output dot source
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# filename. From the given node, both processes (node and edge creation)
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# is performed recursivly, traversing all children of the given root.
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#
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# pydot is required. When missing, no output will be generated.
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#
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#####################################################################
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import m5, os, re
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from m5.SimObject import isRoot, isSimObjectVector
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try:
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import pydot
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except:
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pydot = False
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# need to create all nodes (components) before creating edges (memory channels)
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def dot_create_nodes(simNode, callgraph):
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if isRoot(simNode):
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label = "root"
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else:
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label = simNode._name
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full_path = re.sub('\.', '_', simNode.path())
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# each component is a sub-graph (cluster)
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cluster = dot_create_cluster(simNode, full_path, label)
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# create nodes per port
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for port_name in simNode._ports.keys():
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port = simNode._port_refs.get(port_name, None)
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if port != None:
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full_port_name = full_path + "_" + port_name
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port_node = dot_create_node(simNode, full_port_name, port_name)
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cluster.add_node(port_node)
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# recurse to children
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if simNode._children:
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for c in simNode._children:
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child = simNode._children[c]
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if isSimObjectVector(child):
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for obj in child:
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dot_create_nodes(obj, cluster)
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else:
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dot_create_nodes(child, cluster)
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callgraph.add_subgraph(cluster)
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# create all edges according to memory hierarchy
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def dot_create_edges(simNode, callgraph):
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for port_name in simNode._ports.keys():
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port = simNode._port_refs.get(port_name, None)
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if port != None:
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full_path = re.sub('\.', '_', simNode.path())
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full_port_name = full_path + "_" + port_name
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port_node = dot_create_node(simNode, full_port_name, port_name)
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# create edges
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if type(port) is m5.params.PortRef:
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dot_add_edge(simNode, callgraph, full_port_name, port)
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else:
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for p in port.elements:
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dot_add_edge(simNode, callgraph, full_port_name, p)
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# recurse to children
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if simNode._children:
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for c in simNode._children:
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child = simNode._children[c]
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if isSimObjectVector(child):
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for obj in child:
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dot_create_edges(obj, callgraph)
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else:
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dot_create_edges(child, callgraph)
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def dot_add_edge(simNode, callgraph, full_port_name, peerPort):
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if peerPort.role == "MASTER":
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peer_port_name = re.sub('\.', '_', peerPort.peer.simobj.path() \
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+ "." + peerPort.peer.name)
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callgraph.add_edge(pydot.Edge(full_port_name, peer_port_name))
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def dot_create_cluster(simNode, full_path, label):
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# if you read this, feel free to modify colors / style
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return pydot.Cluster( \
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full_path, \
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shape = "Mrecord", \
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label = label, \
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style = "\"rounded, filled\"", \
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color = "#000000", \
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fillcolor = dot_gen_color(simNode), \
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fontname = "Arial", \
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fontsize = "14", \
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fontcolor = "#000000" \
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)
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def dot_create_node(simNode, full_path, label):
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# if you read this, feel free to modify colors / style.
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# leafs may have a different style => seperate function
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return pydot.Node( \
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full_path, \
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shape = "Mrecord", \
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label = label, \
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style = "\"rounded, filled\"", \
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color = "#000000", \
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fillcolor = "#808080", \
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fontname = "Arial", \
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fontsize = "14", \
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fontcolor = "#000000" \
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)
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# generate color for nodes
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# currently a simple grayscale. placeholder for aesthetic programmers.
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def dot_gen_color(simNode):
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depth = len(simNode.path().split('.'))
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depth = 256 - depth * 16 * 3
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return dot_rgb_to_html(simNode, depth, depth, depth)
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def dot_rgb_to_html(simNode, r, g, b):
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return "#%.2x%.2x%.2x" % (r, g, b)
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def do_dot(root, outdir, dotFilename):
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if not pydot:
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return
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callgraph = pydot.Dot(graph_type='digraph')
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dot_create_nodes(root, callgraph)
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dot_create_edges(root, callgraph)
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dot_filename = os.path.join(outdir, dotFilename)
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callgraph.write(dot_filename)
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try:
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# dot crashes if the figure is extremely wide.
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# So avoid terminating simulation unnecessarily
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callgraph.write_pdf(dot_filename + ".pdf")
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except:
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print "warning: failed to generate pdf output from %s" % dot_filename
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