Adding gem5 source to svn.
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1819 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
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simulators/gem5/src/mem/bus.hh
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simulators/gem5/src/mem/bus.hh
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/*
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* Copyright (c) 2011-2012 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2002-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Ron Dreslinski
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* Ali Saidi
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* Andreas Hansson
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* William Wang
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*/
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/**
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* @file
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* Declaration of an abstract bus base class.
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*/
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#ifndef __MEM_BUS_HH__
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#define __MEM_BUS_HH__
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#include <list>
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#include <set>
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#include "base/range.hh"
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#include "base/range_map.hh"
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#include "base/types.hh"
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#include "mem/mem_object.hh"
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#include "params/BaseBus.hh"
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/**
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* The base bus contains the common elements of the non-coherent and
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* coherent bus. It is an abstract class that does not have any of the
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* functionality relating to the actual reception and transmission of
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* packets, as this is left for the subclasses.
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*
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* The BaseBus is responsible for the basic flow control (busy or
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* not), the administration of retries, and the address decoding.
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*/
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class BaseBus : public MemObject
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{
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protected:
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/** the clock speed for the bus */
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int clock;
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/** cycles of overhead per transaction */
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int headerCycles;
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/** the width of the bus in bytes */
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int width;
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/** the next tick at which the bus will be idle */
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Tick tickNextIdle;
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Event * drainEvent;
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typedef range_map<Addr, PortID>::iterator PortIter;
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range_map<Addr, PortID> portMap;
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AddrRangeList defaultRange;
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/**
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* Determine if the bus is to be considered occupied when being
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* presented with a packet from a specific port. If so, the port
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* in question is also added to the retry list.
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*
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* @param port Source port on the bus presenting the packet
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*
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* @return True if the bus is to be considered occupied
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*/
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bool isOccupied(Port* port);
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/**
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* Deal with a destination port accepting a packet by potentially
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* removing the source port from the retry list (if retrying) and
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* occupying the bus accordingly.
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*
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* @param busy_time Time to spend as a result of a successful send
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*/
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void succeededTiming(Tick busy_time);
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/** Timing function called by port when it is once again able to process
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* requests. */
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void recvRetry();
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/**
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* Function called by the port when the bus is recieving a range change.
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*
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* @param master_port_id id of the port that received the change
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*/
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void recvRangeChange(PortID master_port_id);
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/** Find which port connected to this bus (if any) should be given a packet
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* with this address.
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* @param addr Address to find port for.
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* @return id of port that the packet should be sent out of.
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*/
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PortID findPort(Addr addr);
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// Cache for the findPort function storing recently used ports from portMap
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struct PortCache {
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bool valid;
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PortID id;
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Addr start;
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Addr end;
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};
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PortCache portCache[3];
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// Checks the cache and returns the id of the port that has the requested
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// address within its range
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inline PortID checkPortCache(Addr addr) {
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if (portCache[0].valid && addr >= portCache[0].start &&
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addr < portCache[0].end) {
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return portCache[0].id;
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}
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if (portCache[1].valid && addr >= portCache[1].start &&
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addr < portCache[1].end) {
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return portCache[1].id;
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}
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if (portCache[2].valid && addr >= portCache[2].start &&
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addr < portCache[2].end) {
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return portCache[2].id;
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}
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return InvalidPortID;
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}
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// Clears the earliest entry of the cache and inserts a new port entry
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inline void updatePortCache(short id, Addr start, Addr end) {
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portCache[2].valid = portCache[1].valid;
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portCache[2].id = portCache[1].id;
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portCache[2].start = portCache[1].start;
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portCache[2].end = portCache[1].end;
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portCache[1].valid = portCache[0].valid;
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portCache[1].id = portCache[0].id;
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portCache[1].start = portCache[0].start;
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portCache[1].end = portCache[0].end;
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portCache[0].valid = true;
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portCache[0].id = id;
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portCache[0].start = start;
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portCache[0].end = end;
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}
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// Clears the cache. Needs to be called in constructor.
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inline void clearPortCache() {
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portCache[2].valid = false;
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portCache[1].valid = false;
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portCache[0].valid = false;
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}
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/**
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* Return the address ranges the bus is responsible for.
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*
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* @return a list of non-overlapping address ranges
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*/
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AddrRangeList getAddrRanges();
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/** Calculate the timing parameters for the packet. Updates the
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* firstWordTime and finishTime fields of the packet object.
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* Returns the tick at which the packet header is completed (which
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* will be all that is sent if the target rejects the packet).
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*/
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Tick calcPacketTiming(PacketPtr pkt);
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/** Occupy the bus until until */
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void occupyBus(Tick until);
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/**
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* Release the bus after being occupied and return to an idle
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* state where we proceed to send a retry to any potential waiting
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* port, or drain if asked to do so.
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*/
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void releaseBus();
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/**
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* Send a retry to the port at the head of the retryList. The
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* caller must ensure that the list is not empty.
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*/
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void retryWaiting();
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/**
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* Ask everyone on the bus what their size is
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*
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* @return the max of all the sizes
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*/
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unsigned findBlockSize();
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// event used to schedule a release of the bus
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EventWrapper<BaseBus, &BaseBus::releaseBus> busIdleEvent;
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bool inRetry;
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std::set<PortID> inRecvRangeChange;
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/** The master and slave ports of the bus */
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std::vector<SlavePort*> slavePorts;
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std::vector<MasterPort*> masterPorts;
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/** Convenience typedefs. */
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typedef std::vector<SlavePort*>::iterator SlavePortIter;
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typedef std::vector<MasterPort*>::iterator MasterPortIter;
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typedef std::vector<SlavePort*>::const_iterator SlavePortConstIter;
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typedef std::vector<MasterPort*>::const_iterator MasterPortConstIter;
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/** An array of pointers to ports that retry should be called on because the
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* original send failed for whatever reason.*/
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std::list<Port*> retryList;
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void addToRetryList(Port* port)
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{
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if (!inRetry) {
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// The device wasn't retrying a packet, or wasn't at an
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// appropriate time.
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retryList.push_back(port);
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} else {
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if (!retryList.empty() && port == retryList.front()) {
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// The device was retrying a packet. It didn't work,
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// so we'll leave it at the head of the retry list.
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inRetry = false;
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} else {
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// We are in retry, but not for this port, put it at
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// the end.
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retryList.push_back(port);
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}
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}
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}
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/** Port that handles requests that don't match any of the interfaces.*/
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PortID defaultPortID;
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/** If true, use address range provided by default device. Any
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address not handled by another port and not in default device's
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range will cause a fatal error. If false, just send all
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addresses not handled by another port to default device. */
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bool useDefaultRange;
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unsigned defaultBlockSize;
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unsigned cachedBlockSize;
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bool cachedBlockSizeValid;
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BaseBus(const BaseBusParams *p);
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virtual ~BaseBus();
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public:
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/** A function used to return the port associated with this bus object. */
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virtual MasterPort& getMasterPort(const std::string& if_name, int idx = -1);
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virtual SlavePort& getSlavePort(const std::string& if_name, int idx = -1);
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virtual void startup();
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unsigned int drain(Event *de);
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};
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#endif //__MEM_BUS_HH__
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