Adding gem5 source to svn.

git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1819 8c4709b5-6ec9-48aa-a5cd-a96041d1645a

simulators/gem5/src/dev/sparc/SConscript

@@ -0,0 +1,42 @@
+# -*- mode:python -*-
+
+# Copyright (c) 2006 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Steve Reinhardt
+#          Gabe Black
+
+Import('*')
+
+if env['TARGET_ISA'] == 'sparc':
+    SimObject('T1000.py')
+
+    Source('dtod.cc')
+    Source('iob.cc')
+    Source('t1000.cc')
+    Source('mm_disk.cc')
+
+    DebugFlag('Iob')

simulators/gem5/src/dev/sparc/T1000.py

@@ -0,0 +1,135 @@
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Gabe Black
+
+from m5.params import *
+from m5.proxy import *
+from Device import BasicPioDevice, PioDevice, IsaFake, BadAddr
+from Platform import Platform
+from Terminal import Terminal
+from Uart import Uart8250
+
+
+class MmDisk(BasicPioDevice):
+    type = 'MmDisk'
+    image = Param.DiskImage("Disk Image")
+    pio_addr = 0x1F40000000
+
+class DumbTOD(BasicPioDevice):
+    type = 'DumbTOD'
+    time = Param.Time('01/01/2009', "System time to use ('Now' for real time)")
+    pio_addr = 0xfff0c1fff8
+
+class Iob(PioDevice):
+    type = 'Iob'
+    platform = Param.Platform(Parent.any, "Platform this device is part of.")
+    pio_latency = Param.Latency('1ns', "Programed IO latency in simticks")
+
+
+class T1000(Platform):
+    type = 'T1000'
+    system = Param.System(Parent.any, "system")
+
+    fake_clk = IsaFake(pio_addr=0x9600000000, pio_size=0x100000000)
+            #warn_access="Accessing Clock Unit -- Unimplemented!")
+
+    fake_membnks = IsaFake(pio_addr=0x9700000000, pio_size=16384,
+            ret_data64=0x0000000000000000, update_data=False)
+            #warn_access="Accessing Memory Banks -- Unimplemented!")
+
+    fake_jbi = IsaFake(pio_addr=0x8000000000, pio_size=0x100000000)
+            #warn_access="Accessing JBI -- Unimplemented!")
+
+    fake_l2_1 = IsaFake(pio_addr=0xA900000000, pio_size=0x8,
+            ret_data64=0x0000000000000001, update_data=True)
+            #warn_access="Accessing L2 Cache Banks -- Unimplemented!")
+
+    fake_l2_2 = IsaFake(pio_addr=0xA900000040, pio_size=0x8,
+            ret_data64=0x0000000000000001, update_data=True)
+            #warn_access="Accessing L2 Cache Banks -- Unimplemented!")
+
+    fake_l2_3 = IsaFake(pio_addr=0xA900000080, pio_size=0x8,
+            ret_data64=0x0000000000000001, update_data=True)
+            #warn_access="Accessing L2 Cache Banks -- Unimplemented!")
+
+    fake_l2_4 = IsaFake(pio_addr=0xA9000000C0, pio_size=0x8,
+            ret_data64=0x0000000000000001, update_data=True)
+            #warn_access="Accessing L2 Cache Banks -- Unimplemented!")
+
+    fake_l2esr_1 = IsaFake(pio_addr=0xAB00000000, pio_size=0x8,
+            ret_data64=0x0000000000000000, update_data=True)
+            #warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!")
+
+    fake_l2esr_2 = IsaFake(pio_addr=0xAB00000040, pio_size=0x8,
+            ret_data64=0x0000000000000000, update_data=True)
+            #warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!")
+
+    fake_l2esr_3 = IsaFake(pio_addr=0xAB00000080, pio_size=0x8,
+            ret_data64=0x0000000000000000, update_data=True)
+            #warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!")
+
+    fake_l2esr_4 = IsaFake(pio_addr=0xAB000000C0, pio_size=0x8,
+            ret_data64=0x0000000000000000, update_data=True)
+            #warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!")
+
+    fake_ssi = IsaFake(pio_addr=0xff00000000, pio_size=0x10000000)
+            #warn_access="Accessing SSI -- Unimplemented!")
+
+    hterm = Terminal()
+    hvuart = Uart8250(pio_addr=0xfff0c2c000)
+    htod = DumbTOD()
+
+    pterm = Terminal()
+    puart0 = Uart8250(pio_addr=0x1f10000000)
+
+    iob = Iob()
+    # Attach I/O devices that are on chip
+    def attachOnChipIO(self, bus):
+        self.iob.pio = bus.master
+        self.htod.pio = bus.master
+
+
+    # Attach I/O devices to specified bus object.  Can't do this
+    # earlier, since the bus object itself is typically defined at the
+    # System level.
+    def attachIO(self, bus):
+        self.hvuart.terminal = self.hterm
+        self.puart0.terminal = self.pterm
+        self.fake_clk.pio = bus.master
+        self.fake_membnks.pio = bus.master
+        self.fake_l2_1.pio = bus.master
+        self.fake_l2_2.pio = bus.master
+        self.fake_l2_3.pio = bus.master
+        self.fake_l2_4.pio = bus.master
+        self.fake_l2esr_1.pio = bus.master
+        self.fake_l2esr_2.pio = bus.master
+        self.fake_l2esr_3.pio = bus.master
+        self.fake_l2esr_4.pio = bus.master
+        self.fake_ssi.pio = bus.master
+        self.fake_jbi.pio = bus.master
+        self.puart0.pio = bus.master
+        self.hvuart.pio = bus.master

simulators/gem5/src/dev/sparc/dtod.cc

@@ -0,0 +1,110 @@
+/*
+ * Copyright (c) 2004-2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Ali Saidi
+ */
+
+/** @file
+ * Time of date device implementation
+ */
+#include <sys/time.h>
+
+#include <deque>
+#include <string>
+#include <vector>
+
+#include "base/time.hh"
+#include "base/trace.hh"
+#include "config/the_isa.hh"
+#include "dev/sparc/dtod.hh"
+#include "dev/platform.hh"
+#include "mem/packet_access.hh"
+#include "mem/port.hh"
+#include "sim/system.hh"
+
+using namespace std;
+using namespace TheISA;
+
+DumbTOD::DumbTOD(const Params *p)
+    : BasicPioDevice(p)
+{
+    struct tm tm = p->time;
+    char *tz;
+
+    pioSize = 0x08;
+
+    tz = getenv("TZ");
+    setenv("TZ", "", 1);
+    tzset();
+    todTime = mktime(&tm);
+    if (tz)
+        setenv("TZ", tz, 1);
+    else
+        unsetenv("TZ");
+    tzset();
+
+    DPRINTFN("Real-time clock set to %s\n", asctime(&tm));
+    DPRINTFN("Real-time clock set to %d\n", todTime);
+}
+
+Tick
+DumbTOD::read(PacketPtr pkt)
+{
+    assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
+    assert(pkt->getSize() == 8);
+
+    pkt->allocate();
+    pkt->set(todTime);
+    todTime += 1000;
+
+    pkt->makeAtomicResponse();
+    return pioDelay;
+}
+
+Tick
+DumbTOD::write(PacketPtr pkt)
+{
+    panic("Dumb tod device doesn't support writes\n");
+}
+
+void
+DumbTOD::serialize(std::ostream &os)
+{
+    SERIALIZE_SCALAR(todTime);
+}
+
+void
+DumbTOD::unserialize(Checkpoint *cp, const std::string &section)
+{
+    UNSERIALIZE_SCALAR(todTime);
+}
+
+DumbTOD *
+DumbTODParams::create()
+{
+    return new DumbTOD(this);
+}

simulators/gem5/src/dev/sparc/dtod.hh

@@ -0,0 +1,83 @@
+/*
+ * Copyright (c) 2004-2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Ali Saidi
+ */
+
+/** @file
+ * This device acts as a simple time of date device. It's implemented as a
+ * simple device register read.
+ */
+
+#ifndef __DEV_SPARC_DTOD_HH__
+#define __DEV_SPARC_DTOD_HH__
+
+#include <vector>
+
+#include "base/range.hh"
+#include "dev/io_device.hh"
+#include "params/DumbTOD.hh"
+
+/**
+ * DumbTOD simply returns some idea of time when read.  Until we finish with
+ * legion it starts with the start time and increments itself by 1000 each time.
+ */
+class DumbTOD : public BasicPioDevice
+{
+  private:
+    uint64_t todTime;
+
+  public:
+    typedef DumbTODParams Params;
+    DumbTOD(const Params *p);
+
+    const Params *
+    params() const
+    {
+        return dynamic_cast<const Params *>(_params);
+    }
+
+    virtual Tick read(PacketPtr pkt);
+    virtual Tick write(PacketPtr pkt);
+
+    /**
+     * Serialize this object to the given output stream.
+     * @param os The stream to serialize to.
+     */
+    virtual void serialize(std::ostream &os);
+
+    /**
+     * Reconstruct the state of this object from a checkpoint.
+     * @param cp The checkpoint use.
+     * @param section The section name of this object
+     */
+    virtual void unserialize(Checkpoint *cp, const std::string &section);
+
+
+};
+
+#endif // __DEV_BADDEV_HH__

simulators/gem5/src/dev/sparc/iob.cc

@@ -0,0 +1,379 @@
+/*
+ * Copyright (c) 2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Ali Saidi
+ */
+
+/** @file
+ * This device implemetns the niagara I/O bridge chip. It manages incomming
+ * interrupts and posts them to the CPU when needed. It holds mask registers and
+ * various status registers for CPUs to check what interrupts are pending as
+ * well as facilities to send IPIs to other cpus.
+ */
+
+#include <cstring>
+
+#include "arch/sparc/faults.hh"
+#include "arch/sparc/isa_traits.hh"
+#include "base/bitfield.hh"
+#include "base/trace.hh"
+#include "cpu/intr_control.hh"
+#include "cpu/thread_context.hh"
+#include "debug/Iob.hh"
+#include "dev/sparc/iob.hh"
+#include "dev/platform.hh"
+#include "mem/packet_access.hh"
+#include "mem/port.hh"
+#include "sim/faults.hh"
+#include "sim/system.hh"
+
+Iob::Iob(const Params *p)
+    : PioDevice(p), ic(p->platform->intrctrl)
+{
+    iobManAddr = ULL(0x9800000000);
+    iobManSize = ULL(0x0100000000);
+    iobJBusAddr = ULL(0x9F00000000);
+    iobJBusSize = ULL(0x0100000000);
+    assert (params()->system->threadContexts.size() <= MaxNiagaraProcs);
+
+    pioDelay = p->pio_latency;
+
+    for (int x = 0; x < NumDeviceIds; ++x) {
+        intMan[x].cpu = 0;
+        intMan[x].vector = 0;
+        intCtl[x].mask = true;
+        intCtl[x].pend = false;
+    }
+
+}
+
+Tick
+Iob::read(PacketPtr pkt)
+{
+
+    if (pkt->getAddr() >= iobManAddr && pkt->getAddr() < iobManAddr + iobManSize)
+        readIob(pkt);
+    else if (pkt->getAddr() >= iobJBusAddr && pkt->getAddr() < iobJBusAddr+iobJBusSize)
+        readJBus(pkt);
+    else
+        panic("Invalid address reached Iob\n");
+
+    pkt->makeAtomicResponse();
+    return pioDelay;
+}
+
+void
+Iob::readIob(PacketPtr pkt)
+{
+        Addr accessAddr = pkt->getAddr() - iobManAddr;
+
+        if (accessAddr >= IntManAddr && accessAddr < IntManAddr + IntManSize) {
+            int index = (accessAddr - IntManAddr) >> 3;
+            uint64_t data = intMan[index].cpu << 8 | intMan[index].vector << 0;
+            pkt->set(data);
+            return;
+        }
+
+        if (accessAddr >= IntCtlAddr && accessAddr < IntCtlAddr + IntCtlSize) {
+            int index = (accessAddr - IntCtlAddr) >> 3;
+            uint64_t data = intCtl[index].mask  ? 1 << 2 : 0 |
+                intCtl[index].pend  ? 1 << 0 : 0;
+            pkt->set(data);
+            return;
+        }
+
+        if (accessAddr == JIntVecAddr) {
+            pkt->set(jIntVec);
+            return;
+        }
+
+        panic("Read to unknown IOB offset 0x%x\n", accessAddr);
+}
+
+void
+Iob::readJBus(PacketPtr pkt)
+{
+        Addr accessAddr = pkt->getAddr() - iobJBusAddr;
+        int cpuid = pkt->req->contextId();
+        int index;
+        uint64_t data;
+
+
+
+
+        if (accessAddr >= JIntData0Addr && accessAddr < JIntData1Addr) {
+            index = (accessAddr - JIntData0Addr) >> 3;
+            pkt->set(jBusData0[index]);
+            return;
+        }
+
+        if (accessAddr >= JIntData1Addr && accessAddr < JIntDataA0Addr) {
+            index = (accessAddr - JIntData1Addr) >> 3;
+            pkt->set(jBusData1[index]);
+            return;
+        }
+
+        if (accessAddr == JIntDataA0Addr) {
+            pkt->set(jBusData0[cpuid]);
+            return;
+        }
+
+        if (accessAddr == JIntDataA1Addr) {
+            pkt->set(jBusData1[cpuid]);
+            return;
+        }
+
+        if (accessAddr >= JIntBusyAddr && accessAddr < JIntBusyAddr + JIntBusySize) {
+            index = (accessAddr - JIntBusyAddr) >> 3;
+            data = jIntBusy[index].busy ? 1 << 5 : 0 |
+                   jIntBusy[index].source;
+            pkt->set(data);
+            return;
+        }
+        if (accessAddr == JIntABusyAddr) {
+            data = jIntBusy[cpuid].busy ? 1 << 5 : 0 |
+                   jIntBusy[cpuid].source;
+            pkt->set(data);
+            return;
+        };
+
+        panic("Read to unknown JBus offset 0x%x\n", accessAddr);
+}
+
+Tick
+Iob::write(PacketPtr pkt)
+{
+    if (pkt->getAddr() >= iobManAddr && pkt->getAddr() < iobManAddr + iobManSize)
+        writeIob(pkt);
+    else if (pkt->getAddr() >= iobJBusAddr && pkt->getAddr() < iobJBusAddr+iobJBusSize)
+        writeJBus(pkt);
+    else
+        panic("Invalid address reached Iob\n");
+
+
+    pkt->makeAtomicResponse();
+    return pioDelay;
+}
+
+void
+Iob::writeIob(PacketPtr pkt)
+{
+        Addr accessAddr = pkt->getAddr() - iobManAddr;
+        int index;
+        uint64_t data;
+
+        if (accessAddr >= IntManAddr && accessAddr < IntManAddr + IntManSize) {
+            index = (accessAddr - IntManAddr) >> 3;
+            data = pkt->get<uint64_t>();
+            intMan[index].cpu = bits(data,12,8);
+            intMan[index].vector = bits(data,5,0);
+            DPRINTF(Iob, "Wrote IntMan %d cpu %d, vec %d\n", index,
+                    intMan[index].cpu, intMan[index].vector);
+            return;
+        }
+
+        if (accessAddr >= IntCtlAddr && accessAddr < IntCtlAddr + IntCtlSize) {
+            index = (accessAddr - IntCtlAddr) >> 3;
+            data = pkt->get<uint64_t>();
+            intCtl[index].mask = bits(data,2,2);
+            if (bits(data,1,1))
+                intCtl[index].pend = false;
+            DPRINTF(Iob, "Wrote IntCtl %d pend %d cleared %d\n", index,
+                    intCtl[index].pend, bits(data,2,2));
+            return;
+        }
+
+        if (accessAddr == JIntVecAddr) {
+            jIntVec = bits(pkt->get<uint64_t>(), 5,0);
+            DPRINTF(Iob, "Wrote jIntVec %d\n", jIntVec);
+            return;
+        }
+
+        if (accessAddr >= IntVecDisAddr && accessAddr < IntVecDisAddr + IntVecDisSize) {
+            Type type;
+            int cpu_id;
+            int vector;
+            index = (accessAddr - IntManAddr) >> 3;
+            data = pkt->get<uint64_t>();
+            type = (Type)bits(data,17,16);
+            cpu_id = bits(data, 12,8);
+            vector = bits(data,5,0);
+            generateIpi(type,cpu_id, vector);
+            return;
+        }
+
+        panic("Write to unknown IOB offset 0x%x\n", accessAddr);
+}
+
+void
+Iob::writeJBus(PacketPtr pkt)
+{
+        Addr accessAddr = pkt->getAddr() - iobJBusAddr;
+        int cpuid = pkt->req->contextId();
+        int index;
+        uint64_t data;
+
+        if (accessAddr >= JIntBusyAddr && accessAddr < JIntBusyAddr + JIntBusySize) {
+            index = (accessAddr - JIntBusyAddr) >> 3;
+            data = pkt->get<uint64_t>();
+            jIntBusy[index].busy = bits(data,5,5);
+            DPRINTF(Iob, "Wrote jIntBusy index %d busy: %d\n", index,
+                    jIntBusy[index].busy);
+            return;
+        }
+        if (accessAddr == JIntABusyAddr) {
+            data = pkt->get<uint64_t>();
+            jIntBusy[cpuid].busy = bits(data,5,5);
+            DPRINTF(Iob, "Wrote jIntBusy index %d busy: %d\n", cpuid,
+                    jIntBusy[cpuid].busy);
+            return;
+        };
+
+        panic("Write to unknown JBus offset 0x%x\n", accessAddr);
+}
+
+void
+Iob::receiveDeviceInterrupt(DeviceId devid)
+{
+    assert(devid < NumDeviceIds);
+    if (intCtl[devid].mask)
+        return;
+    intCtl[devid].mask = true;
+    intCtl[devid].pend = true;
+    DPRINTF(Iob, "Receiving Device interrupt: %d for cpu %d vec %d\n",
+            devid, intMan[devid].cpu, intMan[devid].vector);
+    ic->post(intMan[devid].cpu, SparcISA::IT_INT_VEC, intMan[devid].vector);
+}
+
+
+void
+Iob::generateIpi(Type type, int cpu_id, int vector)
+{
+    SparcISA::SparcFault<SparcISA::PowerOnReset> *por = new SparcISA::PowerOnReset();
+    if (cpu_id >= sys->numContexts())
+        return;
+
+    switch (type) {
+      case 0: // interrupt
+        DPRINTF(Iob, "Generating interrupt because of I/O write to cpu: %d vec %d\n",
+                cpu_id, vector);
+        ic->post(cpu_id, SparcISA::IT_INT_VEC, vector);
+        break;
+      case 1: // reset
+        warn("Sending reset to CPU: %d\n", cpu_id);
+        if (vector != por->trapType())
+            panic("Don't know how to set non-POR reset to cpu\n");
+        por->invoke(sys->threadContexts[cpu_id]);
+        sys->threadContexts[cpu_id]->activate();
+        break;
+      case 2: // idle -- this means stop executing and don't wake on interrupts
+        DPRINTF(Iob, "Idling CPU because of I/O write cpu: %d\n", cpu_id);
+        sys->threadContexts[cpu_id]->halt();
+        break;
+      case 3: // resume
+        DPRINTF(Iob, "Resuming CPU because of I/O write cpu: %d\n", cpu_id);
+        sys->threadContexts[cpu_id]->activate();
+        break;
+      default:
+        panic("Invalid type to generate ipi\n");
+    }
+}
+
+bool
+Iob::receiveJBusInterrupt(int cpu_id, int source, uint64_t d0, uint64_t d1)
+{
+    // If we are already dealing with an interrupt for that cpu we can't deal
+    // with another one right now... come back later
+    if (jIntBusy[cpu_id].busy)
+        return false;
+
+    DPRINTF(Iob, "Receiving jBus interrupt: %d for cpu %d vec %d\n",
+            source, cpu_id, jIntVec);
+
+    jIntBusy[cpu_id].busy = true;
+    jIntBusy[cpu_id].source = source;
+    jBusData0[cpu_id] = d0;
+    jBusData1[cpu_id] = d1;
+
+    ic->post(cpu_id, SparcISA::IT_INT_VEC, jIntVec);
+    return true;
+}
+
+AddrRangeList
+Iob::getAddrRanges()
+{
+    AddrRangeList ranges;
+    ranges.push_back(RangeSize(iobManAddr, iobManSize));
+    ranges.push_back(RangeSize(iobJBusAddr, iobJBusSize));
+    return ranges;
+}
+
+
+void
+Iob::serialize(std::ostream &os)
+{
+
+    SERIALIZE_SCALAR(jIntVec);
+    SERIALIZE_ARRAY(jBusData0, MaxNiagaraProcs);
+    SERIALIZE_ARRAY(jBusData1, MaxNiagaraProcs);
+    for (int x = 0; x < NumDeviceIds; x++) {
+        nameOut(os, csprintf("%s.Int%d", name(), x));
+        paramOut(os, "cpu", intMan[x].cpu);
+        paramOut(os, "vector", intMan[x].vector);
+        paramOut(os, "mask", intCtl[x].mask);
+        paramOut(os, "pend", intCtl[x].pend);
+    };
+    for (int x = 0; x < MaxNiagaraProcs; x++) {
+        nameOut(os, csprintf("%s.jIntBusy%d", name(), x));
+        paramOut(os, "busy", jIntBusy[x].busy);
+        paramOut(os, "source", jIntBusy[x].source);
+    };
+}
+
+void
+Iob::unserialize(Checkpoint *cp, const std::string &section)
+{
+    UNSERIALIZE_SCALAR(jIntVec);
+    UNSERIALIZE_ARRAY(jBusData0, MaxNiagaraProcs);
+    UNSERIALIZE_ARRAY(jBusData1, MaxNiagaraProcs);
+    for (int x = 0; x < NumDeviceIds; x++) {
+        paramIn(cp, csprintf("%s.Int%d", name(), x), "cpu", intMan[x].cpu);
+        paramIn(cp, csprintf("%s.Int%d", name(), x), "vector", intMan[x].vector);
+        paramIn(cp, csprintf("%s.Int%d", name(), x), "mask", intCtl[x].mask);
+        paramIn(cp, csprintf("%s.Int%d", name(), x), "pend", intCtl[x].pend);
+    };
+    for (int x = 0; x < MaxNiagaraProcs; x++) {
+        paramIn(cp, csprintf("%s.jIntBusy%d", name(), x), "busy", jIntBusy[x].busy);
+        paramIn(cp, csprintf("%s.jIntBusy%d", name(), x), "source", jIntBusy[x].source);
+    };
+}
+
+Iob *
+IobParams::create()
+{
+    return new Iob(this);
+}

simulators/gem5/src/dev/sparc/iob.hh

@@ -0,0 +1,152 @@
+/*
+ * Copyright (c) 2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Ali Saidi
+ */
+
+/** @file
+ * This device implements the niagara I/O Bridge chip. The device manages
+ * internal (ipi) and external (serial, pci via jbus).
+ */
+
+#ifndef __DEV_SPARC_IOB_HH__
+#define __DEV_SPARC_IOB_HH__
+
+#include "base/range.hh"
+#include "dev/disk_image.hh"
+#include "dev/io_device.hh"
+#include "params/Iob.hh"
+
+class IntrControl;
+
+const int  MaxNiagaraProcs = 32;
+// IOB Managment Addresses
+const Addr IntManAddr       = 0x0000;
+const Addr IntManSize       = 0x0020;
+const Addr IntCtlAddr       = 0x0400;
+const Addr IntCtlSize       = 0x0020;
+const Addr JIntVecAddr      = 0x0A00;
+const Addr IntVecDisAddr    = 0x0800;
+const Addr IntVecDisSize    = 0x0100;
+
+
+// IOB Control Addresses
+const Addr JIntData0Addr   = 0x0400;
+const Addr JIntData1Addr   = 0x0500;
+const Addr JIntDataA0Addr  = 0x0600;
+const Addr JIntDataA1Addr  = 0x0700;
+const Addr JIntBusyAddr    = 0x0900;
+const Addr JIntBusySize    = 0x0100;
+const Addr JIntABusyAddr   = 0x0B00;
+
+
+// IOB Masks
+const uint64_t IntManMask   = 0x01F3F;
+const uint64_t IntCtlMask   = 0x00006;
+const uint64_t JIntVecMask  = 0x0003F;
+const uint64_t IntVecDis    = 0x31F3F;
+const uint64_t JIntBusyMask = 0x0003F;
+
+
+class Iob : public PioDevice
+{
+  private:
+    IntrControl *ic;
+    Addr iobManAddr;
+    Addr iobManSize;
+    Addr iobJBusAddr;
+    Addr iobJBusSize;
+    Tick pioDelay;
+
+    enum DeviceId {
+        Interal = 0,
+        Error = 1,
+        SSI = 2,
+        Reserved = 3,
+        NumDeviceIds
+    };
+
+    struct IntMan {
+        int cpu;
+        int vector;
+    };
+
+    struct IntCtl {
+        bool mask;
+        bool pend;
+    };
+
+    struct IntBusy {
+        bool busy;
+        int source;
+    };
+
+    enum Type {
+        Interrupt,
+        Reset,
+        Idle,
+        Resume
+    };
+
+    IntMan intMan[NumDeviceIds];
+    IntCtl intCtl[NumDeviceIds];
+    uint64_t jIntVec;
+    uint64_t jBusData0[MaxNiagaraProcs];
+    uint64_t jBusData1[MaxNiagaraProcs];
+    IntBusy jIntBusy[MaxNiagaraProcs];
+
+    void writeIob(PacketPtr pkt);
+    void writeJBus(PacketPtr pkt);
+    void readIob(PacketPtr pkt);
+    void readJBus(PacketPtr pkt);
+
+  public:
+    typedef IobParams Params;
+    Iob(const Params *p);
+
+    const Params *
+    params() const
+    {
+        return dynamic_cast<const Params *>(_params);
+    }
+
+    virtual Tick read(PacketPtr pkt);
+    virtual Tick write(PacketPtr pkt);
+    void generateIpi(Type type, int cpu_id, int vector);
+    void receiveDeviceInterrupt(DeviceId devid);
+    bool receiveJBusInterrupt(int cpu_id, int source, uint64_t d0,
+                              uint64_t d1);
+
+    AddrRangeList getAddrRanges();
+
+    virtual void serialize(std::ostream &os);
+    virtual void unserialize(Checkpoint *cp, const std::string &section);
+
+};
+
+#endif //__DEV_SPARC_IOB_HH__
+

simulators/gem5/src/dev/sparc/mm_disk.cc

@@ -0,0 +1,190 @@
+/*
+ * Copyright (c) 2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Ali Saidi
+ */
+
+/** @file
+ * This device acts as a disk similar to the memory mapped disk device
+ * in legion. Any access is translated to an offset in the disk image.
+ */
+
+#include <cstring>
+
+#include "base/trace.hh"
+#include "debug/IdeDisk.hh"
+#include "dev/sparc/mm_disk.hh"
+#include "dev/platform.hh"
+#include "mem/packet_access.hh"
+#include "mem/port.hh"
+#include "sim/byteswap.hh"
+#include "sim/system.hh"
+
+MmDisk::MmDisk(const Params *p)
+    : BasicPioDevice(p), image(p->image), curSector((off_t)-1), dirty(false)
+{
+    std::memset(&diskData, 0, SectorSize);
+    pioSize = image->size() * SectorSize;
+}
+
+Tick
+MmDisk::read(PacketPtr pkt)
+{
+    Addr accessAddr;
+    off_t sector;
+    uint16_t d16;
+    uint32_t d32;
+    uint64_t d64;
+
+    assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
+    accessAddr = pkt->getAddr() - pioAddr;
+
+    sector = accessAddr / SectorSize;
+
+    if (sector != curSector) {
+        if (dirty) {
+#ifndef NDEBUG
+            off_t bytes_written =
+#endif
+                image->write(diskData, curSector);
+            assert(bytes_written == SectorSize);
+        }
+#ifndef NDEBUG
+        off_t bytes_read =
+#endif
+            image->read(diskData, sector);
+        assert(bytes_read == SectorSize);
+        curSector = sector;
+    }
+    switch (pkt->getSize()) {
+      case sizeof(uint8_t):
+        pkt->set(diskData[accessAddr % SectorSize]);
+        DPRINTF(IdeDisk, "reading byte %#x value= %#x\n", accessAddr, diskData[accessAddr %
+                SectorSize]);
+        break;
+      case sizeof(uint16_t):
+        memcpy(&d16, diskData + (accessAddr % SectorSize), 2);
+        pkt->set(htobe(d16));
+        DPRINTF(IdeDisk, "reading word %#x value= %#x\n", accessAddr, d16);
+        break;
+      case sizeof(uint32_t):
+        memcpy(&d32, diskData + (accessAddr % SectorSize), 4);
+        pkt->set(htobe(d32));
+        DPRINTF(IdeDisk, "reading dword %#x value= %#x\n", accessAddr, d32);
+        break;
+      case sizeof(uint64_t):
+        memcpy(&d64, diskData + (accessAddr % SectorSize), 8);
+        pkt->set(htobe(d64));
+        DPRINTF(IdeDisk, "reading qword %#x value= %#x\n", accessAddr, d64);
+        break;
+      default:
+        panic("Invalid access size\n");
+    }
+
+    pkt->makeAtomicResponse();
+    return pioDelay;
+}
+
+Tick
+MmDisk::write(PacketPtr pkt)
+{
+    Addr accessAddr;
+    off_t sector;
+    uint16_t d16;
+    uint32_t d32;
+    uint64_t d64;
+
+    assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
+    accessAddr = pkt->getAddr() - pioAddr;
+
+    sector = accessAddr / SectorSize;
+
+    if (sector != curSector) {
+        if (dirty) {
+#ifndef NDEBUG
+            off_t bytes_written =
+#endif
+                image->write(diskData, curSector);
+            assert(bytes_written == SectorSize);
+        }
+#ifndef NDEBUG
+        off_t bytes_read =
+#endif
+            image->read(diskData,  sector);
+        assert(bytes_read == SectorSize);
+        curSector = sector;
+    }
+    dirty = true;
+
+    switch (pkt->getSize()) {
+      case sizeof(uint8_t):
+        diskData[accessAddr % SectorSize] = htobe(pkt->get<uint8_t>());
+        DPRINTF(IdeDisk, "writing byte %#x value= %#x\n", accessAddr, diskData[accessAddr %
+                SectorSize]);
+        break;
+      case sizeof(uint16_t):
+        d16 = htobe(pkt->get<uint16_t>());
+        memcpy(diskData + (accessAddr % SectorSize), &d16, 2);
+        DPRINTF(IdeDisk, "writing word %#x value= %#x\n", accessAddr, d16);
+        break;
+      case sizeof(uint32_t):
+        d32 = htobe(pkt->get<uint32_t>());
+        memcpy(diskData + (accessAddr % SectorSize), &d32, 4);
+        DPRINTF(IdeDisk, "writing dword %#x value= %#x\n", accessAddr, d32);
+        break;
+      case sizeof(uint64_t):
+        d64 = htobe(pkt->get<uint64_t>());
+        memcpy(diskData + (accessAddr % SectorSize), &d64, 8);
+        DPRINTF(IdeDisk, "writing qword %#x value= %#x\n", accessAddr, d64);
+        break;
+      default:
+        panic("Invalid access size\n");
+    }
+
+    pkt->makeAtomicResponse();
+    return pioDelay;
+}
+
+void
+MmDisk::serialize(std::ostream &os)
+{
+    // just write any dirty changes to the cow layer it will take care of
+    // serialization
+    if (dirty) {
+#ifndef NDEBUG
+        int bytes_read =
+#endif
+            image->write(diskData, curSector);
+        assert(bytes_read == SectorSize);
+    }
+}
+
+MmDisk *
+MmDiskParams::create()
+{
+    return new MmDisk(this);
+}

simulators/gem5/src/dev/sparc/mm_disk.hh

@@ -0,0 +1,69 @@
+/*
+ * Copyright (c) 2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Ali Saidi
+ */
+
+/** @file
+ * This device acts as a disk similar to the memory mapped disk device
+ * in legion. Any access is translated to an offset in the disk image.
+ */
+
+#ifndef __DEV_SPARC_MM_DISK_HH__
+#define __DEV_SPARC_MM_DISK_HH__
+
+#include "base/range.hh"
+#include "dev/disk_image.hh"
+#include "dev/io_device.hh"
+#include "params/MmDisk.hh"
+
+class MmDisk : public BasicPioDevice
+{
+  private:
+    DiskImage *image;
+    off_t curSector;
+    bool dirty;
+    uint8_t diskData[SectorSize];
+
+  public:
+    typedef MmDiskParams Params;
+    MmDisk(const Params *p);
+
+    const Params *
+    params() const
+    {
+        return dynamic_cast<const Params *>(_params);
+    }
+
+    virtual Tick read(PacketPtr pkt);
+    virtual Tick write(PacketPtr pkt);
+
+    virtual void serialize(std::ostream &os);
+};
+
+#endif //__DEV_SPARC_MM_DISK_HH__
+

simulators/gem5/src/dev/sparc/t1000.cc

@@ -0,0 +1,112 @@
+/*
+ * Copyright (c) 2004-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Ali Saidi
+ */
+
+/** @file
+ * Implementation of T1000 platform.
+ */
+
+#include <deque>
+#include <string>
+#include <vector>
+
+#include "config/the_isa.hh"
+#include "cpu/intr_control.hh"
+#include "dev/sparc/t1000.hh"
+#include "dev/terminal.hh"
+#include "sim/system.hh"
+
+using namespace std;
+//Should this be AlphaISA?
+using namespace TheISA;
+
+T1000::T1000(const Params *p)
+    : Platform(p), system(p->system)
+{}
+
+void
+T1000::postConsoleInt()
+{
+    warn_once("Don't know what interrupt to post for console.\n");
+    //panic("Need implementation\n");
+}
+
+void
+T1000::clearConsoleInt()
+{
+    warn_once("Don't know what interrupt to clear for console.\n");
+    //panic("Need implementation\n");
+}
+
+void
+T1000::postPciInt(int line)
+{
+    panic("Need implementation\n");
+}
+
+void
+T1000::clearPciInt(int line)
+{
+    panic("Need implementation\n");
+}
+
+Addr
+T1000::pciToDma(Addr pciAddr) const
+{
+    panic("Need implementation\n");
+    M5_DUMMY_RETURN
+}
+
+
+Addr
+T1000::calcPciConfigAddr(int bus, int dev, int func)
+{
+    panic("Need implementation\n");
+    M5_DUMMY_RETURN
+}
+
+Addr
+T1000::calcPciIOAddr(Addr addr)
+{
+    panic("Need implementation\n");
+    M5_DUMMY_RETURN
+}
+
+Addr
+T1000::calcPciMemAddr(Addr addr)
+{
+    panic("Need implementation\n");
+    M5_DUMMY_RETURN
+}
+
+T1000 *
+T1000Params::create()
+{
+    return new T1000(this);
+}

simulators/gem5/src/dev/sparc/t1000.hh

@@ -0,0 +1,101 @@
+/*
+ * Copyright (c) 2004-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Ali Saidi
+ */
+
+/**
+ * @file
+ * Declaration of top level class for the T1000 platform chips. This class just
+ * retains pointers to all its children so the children can communicate.
+ */
+
+#ifndef __DEV_T1000_HH__
+#define __DEV_T1000_HH__
+
+#include "dev/platform.hh"
+#include "params/T1000.hh"
+
+class IdeController;
+class System;
+
+class T1000 : public Platform
+{
+  public:
+    /** Pointer to the system */
+    System *system;
+
+  public:
+    typedef T1000Params Params;
+    /**
+     * Constructor for the Tsunami Class.
+     * @param name name of the object
+     * @param s system the object belongs to
+     * @param intctrl pointer to the interrupt controller
+     */
+    T1000(const Params *p);
+
+    /**
+     * Cause the cpu to post a serial interrupt to the CPU.
+     */
+    virtual void postConsoleInt();
+
+    /**
+     * Clear a posted CPU interrupt
+     */
+    virtual void clearConsoleInt();
+
+    /**
+     * Cause the chipset to post a cpi interrupt to the CPU.
+     */
+    virtual void postPciInt(int line);
+
+    /**
+     * Clear a posted PCI->CPU interrupt
+     */
+    virtual void clearPciInt(int line);
+
+
+    virtual Addr pciToDma(Addr pciAddr) const;
+
+    /**
+     * Calculate the configuration address given a bus/dev/func.
+     */
+    virtual Addr calcPciConfigAddr(int bus, int dev, int func);
+
+    /**
+     * Calculate the address for an IO location on the PCI bus.
+     */
+    virtual Addr calcPciIOAddr(Addr addr);
+
+    /**
+     * Calculate the address for a memory location on the PCI bus.
+     */
+    virtual Addr calcPciMemAddr(Addr addr);
+};
+
+#endif // __DEV_T1000_HH__