Adding gem5 source to svn.
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1819 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
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friemel
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simulators/gem5/src/dev/pcidev.hh
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simulators/gem5/src/dev/pcidev.hh
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/*
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* Copyright (c) 2004-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Ali Saidi
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* Andrew Schultz
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* Nathan Binkert
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*/
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/* @file
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* Interface for devices using PCI configuration
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*/
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#ifndef __DEV_PCIDEV_HH__
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#define __DEV_PCIDEV_HH__
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#include <cstring>
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#include "dev/dma_device.hh"
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#include "dev/pcireg.h"
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#include "dev/platform.hh"
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#include "params/PciDevice.hh"
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#include "sim/byteswap.hh"
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#define BAR_IO_MASK 0x3
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#define BAR_MEM_MASK 0xF
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#define BAR_IO_SPACE_BIT 0x1
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#define BAR_IO_SPACE(x) ((x) & BAR_IO_SPACE_BIT)
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#define BAR_NUMBER(x) (((x) - PCI0_BASE_ADDR0) >> 0x2);
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/**
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* PCI device, base implementation is only config space.
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*/
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class PciDev : public DmaDevice
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{
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class PciConfigPort : public SimpleTimingPort
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{
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protected:
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PciDev *device;
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virtual Tick recvAtomic(PacketPtr pkt);
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virtual AddrRangeList getAddrRanges();
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Platform *platform;
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int busId;
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int deviceId;
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int functionId;
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Addr configAddr;
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public:
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PciConfigPort(PciDev *dev, int busid, int devid, int funcid,
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Platform *p);
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};
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public:
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typedef PciDeviceParams Params;
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const Params *
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params() const
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{
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return dynamic_cast<const Params *>(_params);
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}
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protected:
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/** The current config space. */
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PCIConfig config;
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/** The size of the BARs */
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uint32_t BARSize[6];
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/** The current address mapping of the BARs */
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Addr BARAddrs[6];
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/** Whether the BARs are really hardwired legacy IO locations. */
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bool legacyIO[6];
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/**
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* Does the given address lie within the space mapped by the given
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* base address register?
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*/
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bool
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isBAR(Addr addr, int bar) const
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{
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assert(bar >= 0 && bar < 6);
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return BARAddrs[bar] <= addr && addr < BARAddrs[bar] + BARSize[bar];
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}
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/**
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* Which base address register (if any) maps the given address?
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* @return The BAR number (0-5 inclusive), or -1 if none.
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*/
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int
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getBAR(Addr addr)
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{
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for (int i = 0; i <= 5; ++i)
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if (isBAR(addr, i))
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return i;
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return -1;
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}
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/**
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* Which base address register (if any) maps the given address?
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* @param addr The address to check.
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* @retval bar The BAR number (0-5 inclusive),
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* only valid if return value is true.
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* @retval offs The offset from the base address,
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* only valid if return value is true.
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* @return True iff address maps to a base address register's region.
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*/
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bool
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getBAR(Addr addr, int &bar, Addr &offs)
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{
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int b = getBAR(addr);
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if (b < 0)
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return false;
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offs = addr - BARAddrs[b];
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bar = b;
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return true;
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}
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protected:
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Platform *platform;
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Tick pioDelay;
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Tick configDelay;
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PciConfigPort configPort;
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/**
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* Write to the PCI config space data that is stored locally. This may be
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* overridden by the device but at some point it will eventually call this
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* for normal operations that it does not need to override.
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* @param pkt packet containing the write the offset into config space
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*/
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virtual Tick writeConfig(PacketPtr pkt);
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/**
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* Read from the PCI config space data that is stored locally. This may be
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* overridden by the device but at some point it will eventually call this
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* for normal operations that it does not need to override.
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* @param pkt packet containing the write the offset into config space
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*/
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virtual Tick readConfig(PacketPtr pkt);
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public:
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Addr pciToDma(Addr pciAddr) const
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{ return platform->pciToDma(pciAddr); }
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void
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intrPost()
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{ platform->postPciInt(letoh(config.interruptLine)); }
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void
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intrClear()
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{ platform->clearPciInt(letoh(config.interruptLine)); }
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uint8_t
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interruptLine()
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{ return letoh(config.interruptLine); }
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/**
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* Determine the address ranges that this device responds to.
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*
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* @return a list of non-overlapping address ranges
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*/
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AddrRangeList getAddrRanges();
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/**
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* Constructor for PCI Dev. This function copies data from the
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* config file object PCIConfigData and registers the device with
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* a PciConfigAll object.
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*/
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PciDev(const Params *params);
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virtual void init();
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/**
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* Serialize this object to the given output stream.
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* @param os The stream to serialize to.
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*/
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virtual void serialize(std::ostream &os);
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/**
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* Reconstruct the state of this object from a checkpoint.
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* @param cp The checkpoint use.
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* @param section The section name of this object
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*/
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virtual void unserialize(Checkpoint *cp, const std::string §ion);
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virtual unsigned int drain(Event *de);
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virtual SlavePort &getSlavePort(const std::string &if_name, int idx = -1)
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{
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if (if_name == "config") {
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return configPort;
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}
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return DmaDevice::getSlavePort(if_name, idx);
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}
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};
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#endif // __DEV_PCIDEV_HH__
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