Adding gem5 source to svn.
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1819 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
This commit is contained in:
friemel
559
simulators/gem5/src/dev/i8254xGBe.hh
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559
simulators/gem5/src/dev/i8254xGBe.hh
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/*
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* Copyright (c) 2006 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
|
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* modification, are permitted provided that the following conditions are
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||||
* met: redistributions of source code must retain the above copyright
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||||
* notice, this list of conditions and the following disclaimer;
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||||
* redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
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* documentation and/or other materials provided with the distribution;
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||||
* neither the name of the copyright holders nor the names of its
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||||
* contributors may be used to endorse or promote products derived from
|
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* this software without specific prior written permission.
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*
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||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Ali Saidi
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*/
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/* @file
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* Device model for Intel's 8254x line of gigabit ethernet controllers.
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*/
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#ifndef __DEV_I8254XGBE_HH__
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#define __DEV_I8254XGBE_HH__
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#include <deque>
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#include <string>
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#include "base/cp_annotate.hh"
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#include "base/inet.hh"
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#include "debug/EthernetDesc.hh"
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#include "debug/EthernetIntr.hh"
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#include "dev/etherdevice.hh"
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#include "dev/etherint.hh"
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#include "dev/etherpkt.hh"
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#include "dev/i8254xGBe_defs.hh"
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#include "dev/pcidev.hh"
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#include "dev/pktfifo.hh"
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#include "params/IGbE.hh"
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#include "sim/eventq.hh"
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class IGbEInt;
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class IGbE : public EtherDevice
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{
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private:
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IGbEInt *etherInt;
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CPA *cpa;
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// device registers
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iGbReg::Regs regs;
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// eeprom data, status and control bits
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int eeOpBits, eeAddrBits, eeDataBits;
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uint8_t eeOpcode, eeAddr;
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uint16_t flash[iGbReg::EEPROM_SIZE];
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// The drain event if we have one
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Event *drainEvent;
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// cached parameters from params struct
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bool useFlowControl;
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// packet fifos
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PacketFifo rxFifo;
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PacketFifo txFifo;
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// Packet that we are currently putting into the txFifo
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EthPacketPtr txPacket;
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// Should to Rx/Tx State machine tick?
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bool rxTick;
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bool txTick;
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bool txFifoTick;
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bool rxDmaPacket;
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// Number of bytes copied from current RX packet
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unsigned pktOffset;
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// Delays in managaging descriptors
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Tick fetchDelay, wbDelay;
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Tick fetchCompDelay, wbCompDelay;
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Tick rxWriteDelay, txReadDelay;
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// Event and function to deal with RDTR timer expiring
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void rdtrProcess() {
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rxDescCache.writeback(0);
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DPRINTF(EthernetIntr,
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"Posting RXT interrupt because RDTR timer expired\n");
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postInterrupt(iGbReg::IT_RXT);
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}
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//friend class EventWrapper<IGbE, &IGbE::rdtrProcess>;
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EventWrapper<IGbE, &IGbE::rdtrProcess> rdtrEvent;
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// Event and function to deal with RADV timer expiring
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void radvProcess() {
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rxDescCache.writeback(0);
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DPRINTF(EthernetIntr,
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"Posting RXT interrupt because RADV timer expired\n");
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postInterrupt(iGbReg::IT_RXT);
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}
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//friend class EventWrapper<IGbE, &IGbE::radvProcess>;
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EventWrapper<IGbE, &IGbE::radvProcess> radvEvent;
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// Event and function to deal with TADV timer expiring
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void tadvProcess() {
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txDescCache.writeback(0);
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DPRINTF(EthernetIntr,
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"Posting TXDW interrupt because TADV timer expired\n");
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postInterrupt(iGbReg::IT_TXDW);
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}
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//friend class EventWrapper<IGbE, &IGbE::tadvProcess>;
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EventWrapper<IGbE, &IGbE::tadvProcess> tadvEvent;
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// Event and function to deal with TIDV timer expiring
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void tidvProcess() {
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txDescCache.writeback(0);
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DPRINTF(EthernetIntr,
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"Posting TXDW interrupt because TIDV timer expired\n");
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postInterrupt(iGbReg::IT_TXDW);
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}
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//friend class EventWrapper<IGbE, &IGbE::tidvProcess>;
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EventWrapper<IGbE, &IGbE::tidvProcess> tidvEvent;
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// Main event to tick the device
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void tick();
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//friend class EventWrapper<IGbE, &IGbE::tick>;
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EventWrapper<IGbE, &IGbE::tick> tickEvent;
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uint64_t macAddr;
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void rxStateMachine();
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void txStateMachine();
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void txWire();
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/** Write an interrupt into the interrupt pending register and check mask
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* and interrupt limit timer before sending interrupt to CPU
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* @param t the type of interrupt we are posting
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* @param now should we ignore the interrupt limiting timer
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*/
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void postInterrupt(iGbReg::IntTypes t, bool now = false);
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/** Check and see if changes to the mask register have caused an interrupt
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* to need to be sent or perhaps removed an interrupt cause.
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*/
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void chkInterrupt();
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/** Send an interrupt to the cpu
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*/
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void delayIntEvent();
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void cpuPostInt();
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// Event to moderate interrupts
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EventWrapper<IGbE, &IGbE::delayIntEvent> interEvent;
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/** Clear the interupt line to the cpu
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*/
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void cpuClearInt();
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Tick intClock() { return SimClock::Int::ns * 1024; }
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/** This function is used to restart the clock so it can handle things like
|
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* draining and resume in one place. */
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void restartClock();
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/** Check if all the draining things that need to occur have occured and
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* handle the drain event if so.
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*/
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void checkDrain();
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void anBegin(std::string sm, std::string st, int flags = CPA::FL_NONE) {
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cpa->hwBegin((CPA::flags)flags, sys, macAddr, sm, st);
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}
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void anQ(std::string sm, std::string q) {
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cpa->hwQ(CPA::FL_NONE, sys, macAddr, sm, q, macAddr);
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}
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void anDq(std::string sm, std::string q) {
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cpa->hwDq(CPA::FL_NONE, sys, macAddr, sm, q, macAddr);
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}
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void anPq(std::string sm, std::string q, int num = 1) {
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cpa->hwPq(CPA::FL_NONE, sys, macAddr, sm, q, macAddr, NULL, num);
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}
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void anRq(std::string sm, std::string q, int num = 1) {
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cpa->hwRq(CPA::FL_NONE, sys, macAddr, sm, q, macAddr, NULL, num);
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}
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void anWe(std::string sm, std::string q) {
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cpa->hwWe(CPA::FL_NONE, sys, macAddr, sm, q, macAddr);
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}
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void anWf(std::string sm, std::string q) {
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cpa->hwWf(CPA::FL_NONE, sys, macAddr, sm, q, macAddr);
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}
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template<class T>
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class DescCache
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{
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protected:
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virtual Addr descBase() const = 0;
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virtual long descHead() const = 0;
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virtual long descTail() const = 0;
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virtual long descLen() const = 0;
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virtual void updateHead(long h) = 0;
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virtual void enableSm() = 0;
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virtual void actionAfterWb() {}
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virtual void fetchAfterWb() = 0;
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typedef std::deque<T *> CacheType;
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CacheType usedCache;
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CacheType unusedCache;
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T *fetchBuf;
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T *wbBuf;
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// Pointer to the device we cache for
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IGbE *igbe;
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// Name of this descriptor cache
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std::string _name;
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// How far we've cached
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int cachePnt;
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// The size of the descriptor cache
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int size;
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// How many descriptors we are currently fetching
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int curFetching;
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// How many descriptors we are currently writing back
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int wbOut;
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// if the we wrote back to the end of the descriptor ring and are going
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// to have to wrap and write more
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bool moreToWb;
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// What the alignment is of the next descriptor writeback
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Addr wbAlignment;
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/** The packet that is currently being dmad to memory if any */
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EthPacketPtr pktPtr;
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/** Shortcut for DMA address translation */
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Addr pciToDma(Addr a) { return igbe->platform->pciToDma(a); }
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public:
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/** Annotate sm*/
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std::string annSmFetch, annSmWb, annUnusedDescQ, annUsedCacheQ,
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annUsedDescQ, annUnusedCacheQ, annDescQ;
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DescCache(IGbE *i, const std::string n, int s);
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virtual ~DescCache();
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std::string name() { return _name; }
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/** If the address/len/head change when we've got descriptors that are
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* dirty that is very bad. This function checks that we don't and if we
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* do panics.
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*/
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void areaChanged();
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void writeback(Addr aMask);
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void writeback1();
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EventWrapper<DescCache, &DescCache::writeback1> wbDelayEvent;
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/** Fetch a chunk of descriptors into the descriptor cache.
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* Calls fetchComplete when the memory system returns the data
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*/
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void fetchDescriptors();
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void fetchDescriptors1();
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EventWrapper<DescCache, &DescCache::fetchDescriptors1> fetchDelayEvent;
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|
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/** Called by event when dma to read descriptors is completed
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*/
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void fetchComplete();
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EventWrapper<DescCache, &DescCache::fetchComplete> fetchEvent;
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/** Called by event when dma to writeback descriptors is completed
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*/
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void wbComplete();
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EventWrapper<DescCache, &DescCache::wbComplete> wbEvent;
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||||
/* Return the number of descriptors left in the ring, so the device has
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* a way to figure out if it needs to interrupt.
|
||||
*/
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unsigned
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descLeft() const
|
||||
{
|
||||
unsigned left = unusedCache.size();
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||||
if (cachePnt > descTail())
|
||||
left += (descLen() - cachePnt + descTail());
|
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else
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||||
left += (descTail() - cachePnt);
|
||||
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||||
return left;
|
||||
}
|
||||
|
||||
/* Return the number of descriptors used and not written back.
|
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*/
|
||||
unsigned descUsed() const { return usedCache.size(); }
|
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/* Return the number of cache unused descriptors we have. */
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unsigned descUnused() const { return unusedCache.size(); }
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||||
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/* Get into a state where the descriptor address/head/etc colud be
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* changed */
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void reset();
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virtual void serialize(std::ostream &os);
|
||||
virtual void unserialize(Checkpoint *cp, const std::string §ion);
|
||||
|
||||
virtual bool hasOutstandingEvents() {
|
||||
return wbEvent.scheduled() || fetchEvent.scheduled();
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}
|
||||
|
||||
};
|
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|
||||
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class RxDescCache : public DescCache<iGbReg::RxDesc>
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{
|
||||
protected:
|
||||
virtual Addr descBase() const { return igbe->regs.rdba(); }
|
||||
virtual long descHead() const { return igbe->regs.rdh(); }
|
||||
virtual long descLen() const { return igbe->regs.rdlen() >> 4; }
|
||||
virtual long descTail() const { return igbe->regs.rdt(); }
|
||||
virtual void updateHead(long h) { igbe->regs.rdh(h); }
|
||||
virtual void enableSm();
|
||||
virtual void fetchAfterWb() {
|
||||
if (!igbe->rxTick && igbe->getState() == SimObject::Running)
|
||||
fetchDescriptors();
|
||||
}
|
||||
|
||||
bool pktDone;
|
||||
|
||||
/** Variable to head with header/data completion events */
|
||||
int splitCount;
|
||||
|
||||
/** Bytes of packet that have been copied, so we know when to
|
||||
set EOP */
|
||||
unsigned bytesCopied;
|
||||
|
||||
public:
|
||||
RxDescCache(IGbE *i, std::string n, int s);
|
||||
|
||||
/** Write the given packet into the buffer(s) pointed to by the
|
||||
* descriptor and update the book keeping. Should only be called when
|
||||
* there are no dma's pending.
|
||||
* @param packet ethernet packet to write
|
||||
* @param pkt_offset bytes already copied from the packet to memory
|
||||
* @return pkt_offset + number of bytes copied during this call
|
||||
*/
|
||||
int writePacket(EthPacketPtr packet, int pkt_offset);
|
||||
|
||||
/** Called by event when dma to write packet is completed
|
||||
*/
|
||||
void pktComplete();
|
||||
|
||||
/** Check if the dma on the packet has completed and RX state machine
|
||||
* can continue
|
||||
*/
|
||||
bool packetDone();
|
||||
|
||||
EventWrapper<RxDescCache, &RxDescCache::pktComplete> pktEvent;
|
||||
|
||||
// Event to handle issuing header and data write at the same time
|
||||
// and only callking pktComplete() when both are completed
|
||||
void pktSplitDone();
|
||||
EventWrapper<RxDescCache, &RxDescCache::pktSplitDone> pktHdrEvent;
|
||||
EventWrapper<RxDescCache, &RxDescCache::pktSplitDone> pktDataEvent;
|
||||
|
||||
virtual bool hasOutstandingEvents();
|
||||
|
||||
virtual void serialize(std::ostream &os);
|
||||
virtual void unserialize(Checkpoint *cp, const std::string §ion);
|
||||
};
|
||||
friend class RxDescCache;
|
||||
|
||||
RxDescCache rxDescCache;
|
||||
|
||||
class TxDescCache : public DescCache<iGbReg::TxDesc>
|
||||
{
|
||||
protected:
|
||||
virtual Addr descBase() const { return igbe->regs.tdba(); }
|
||||
virtual long descHead() const { return igbe->regs.tdh(); }
|
||||
virtual long descTail() const { return igbe->regs.tdt(); }
|
||||
virtual long descLen() const { return igbe->regs.tdlen() >> 4; }
|
||||
virtual void updateHead(long h) { igbe->regs.tdh(h); }
|
||||
virtual void enableSm();
|
||||
virtual void actionAfterWb();
|
||||
virtual void fetchAfterWb() {
|
||||
if (!igbe->txTick && igbe->getState() == SimObject::Running)
|
||||
fetchDescriptors();
|
||||
}
|
||||
|
||||
|
||||
|
||||
bool pktDone;
|
||||
bool isTcp;
|
||||
bool pktWaiting;
|
||||
bool pktMultiDesc;
|
||||
Addr completionAddress;
|
||||
bool completionEnabled;
|
||||
uint32_t descEnd;
|
||||
|
||||
|
||||
// tso variables
|
||||
bool useTso;
|
||||
Addr tsoHeaderLen;
|
||||
Addr tsoMss;
|
||||
Addr tsoTotalLen;
|
||||
Addr tsoUsedLen;
|
||||
Addr tsoPrevSeq;
|
||||
Addr tsoPktPayloadBytes;
|
||||
bool tsoLoadedHeader;
|
||||
bool tsoPktHasHeader;
|
||||
uint8_t tsoHeader[256];
|
||||
Addr tsoDescBytesUsed;
|
||||
Addr tsoCopyBytes;
|
||||
int tsoPkts;
|
||||
|
||||
public:
|
||||
TxDescCache(IGbE *i, std::string n, int s);
|
||||
|
||||
/** Tell the cache to DMA a packet from main memory into its buffer and
|
||||
* return the size the of the packet to reserve space in tx fifo.
|
||||
* @return size of the packet
|
||||
*/
|
||||
unsigned getPacketSize(EthPacketPtr p);
|
||||
void getPacketData(EthPacketPtr p);
|
||||
void processContextDesc();
|
||||
|
||||
/** Return the number of dsecriptors in a cache block for threshold
|
||||
* operations.
|
||||
*/
|
||||
unsigned
|
||||
descInBlock(unsigned num_desc)
|
||||
{
|
||||
return num_desc / igbe->cacheBlockSize() / sizeof(iGbReg::TxDesc);
|
||||
}
|
||||
|
||||
/** Ask if the packet has been transfered so the state machine can give
|
||||
* it to the fifo.
|
||||
* @return packet available in descriptor cache
|
||||
*/
|
||||
bool packetAvailable();
|
||||
|
||||
/** Ask if we are still waiting for the packet to be transfered.
|
||||
* @return packet still in transit.
|
||||
*/
|
||||
bool packetWaiting() { return pktWaiting; }
|
||||
|
||||
/** Ask if this packet is composed of multiple descriptors
|
||||
* so even if we've got data, we need to wait for more before
|
||||
* we can send it out.
|
||||
* @return packet can't be sent out because it's a multi-descriptor
|
||||
* packet
|
||||
*/
|
||||
bool packetMultiDesc() { return pktMultiDesc;}
|
||||
|
||||
/** Called by event when dma to write packet is completed
|
||||
*/
|
||||
void pktComplete();
|
||||
EventWrapper<TxDescCache, &TxDescCache::pktComplete> pktEvent;
|
||||
|
||||
void headerComplete();
|
||||
EventWrapper<TxDescCache, &TxDescCache::headerComplete> headerEvent;
|
||||
|
||||
|
||||
void completionWriteback(Addr a, bool enabled) {
|
||||
DPRINTF(EthernetDesc,
|
||||
"Completion writeback Addr: %#x enabled: %d\n",
|
||||
a, enabled);
|
||||
completionAddress = a;
|
||||
completionEnabled = enabled;
|
||||
}
|
||||
|
||||
virtual bool hasOutstandingEvents();
|
||||
|
||||
void nullCallback() {
|
||||
DPRINTF(EthernetDesc, "Completion writeback complete\n");
|
||||
}
|
||||
EventWrapper<TxDescCache, &TxDescCache::nullCallback> nullEvent;
|
||||
|
||||
virtual void serialize(std::ostream &os);
|
||||
virtual void unserialize(Checkpoint *cp, const std::string §ion);
|
||||
|
||||
};
|
||||
friend class TxDescCache;
|
||||
|
||||
TxDescCache txDescCache;
|
||||
|
||||
public:
|
||||
typedef IGbEParams Params;
|
||||
const Params *
|
||||
params() const {
|
||||
return dynamic_cast<const Params *>(_params);
|
||||
}
|
||||
|
||||
IGbE(const Params *params);
|
||||
~IGbE() {}
|
||||
virtual void init();
|
||||
|
||||
virtual EtherInt *getEthPort(const std::string &if_name, int idx);
|
||||
|
||||
Tick clock;
|
||||
Tick lastInterrupt;
|
||||
inline Tick ticks(int numCycles) const { return numCycles * clock; }
|
||||
|
||||
virtual Tick read(PacketPtr pkt);
|
||||
virtual Tick write(PacketPtr pkt);
|
||||
|
||||
virtual Tick writeConfig(PacketPtr pkt);
|
||||
|
||||
bool ethRxPkt(EthPacketPtr packet);
|
||||
void ethTxDone();
|
||||
|
||||
virtual void serialize(std::ostream &os);
|
||||
virtual void unserialize(Checkpoint *cp, const std::string §ion);
|
||||
virtual unsigned int drain(Event *de);
|
||||
virtual void resume();
|
||||
|
||||
};
|
||||
|
||||
class IGbEInt : public EtherInt
|
||||
{
|
||||
private:
|
||||
IGbE *dev;
|
||||
|
||||
public:
|
||||
IGbEInt(const std::string &name, IGbE *d)
|
||||
: EtherInt(name), dev(d)
|
||||
{ }
|
||||
|
||||
virtual bool recvPacket(EthPacketPtr pkt) { return dev->ethRxPkt(pkt); }
|
||||
virtual void sendDone() { dev->ethTxDone(); }
|
||||
};
|
||||
|
||||
#endif //__DEV_I8254XGBE_HH__
|
||||
Reference in New Issue
Block a user