Adding gem5 source to svn.
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1819 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
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friemel
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simulators/gem5/src/dev/copy_engine.hh
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212
simulators/gem5/src/dev/copy_engine.hh
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/*
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* Copyright (c) 2012 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2008 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Ali Saidi
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*/
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/* @file
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* Device model for Intel's I/O Acceleration Technology (I/OAT).
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* A DMA asyncronous copy engine
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*/
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#ifndef __DEV_COPY_ENGINE_HH__
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#define __DEV_COPY_ENGINE_HH__
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#include <vector>
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#include "base/statistics.hh"
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#include "dev/copy_engine_defs.hh"
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#include "dev/pcidev.hh"
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#include "params/CopyEngine.hh"
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#include "sim/eventq.hh"
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class CopyEngine : public PciDev
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{
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class CopyEngineChannel
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{
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private:
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DmaPort cePort;
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CopyEngine *ce;
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CopyEngineReg::ChanRegs cr;
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int channelId;
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CopyEngineReg::DmaDesc *curDmaDesc;
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uint8_t *copyBuffer;
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bool busy;
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bool underReset;
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bool refreshNext;
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Addr lastDescriptorAddr;
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Addr fetchAddress;
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Tick latBeforeBegin;
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Tick latAfterCompletion;
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uint64_t completionDataReg;
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enum ChannelState {
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Idle,
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AddressFetch,
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DescriptorFetch,
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DMARead,
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DMAWrite,
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CompletionWrite
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};
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ChannelState nextState;
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Event *drainEvent;
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public:
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CopyEngineChannel(CopyEngine *_ce, int cid);
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virtual ~CopyEngineChannel();
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MasterPort &getMasterPort();
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std::string name() { assert(ce); return ce->name() + csprintf("-chan%d", channelId); }
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virtual Tick read(PacketPtr pkt)
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{ panic("CopyEngineChannel has no I/O access\n");}
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virtual Tick write(PacketPtr pkt)
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{ panic("CopyEngineChannel has no I/O access\n"); }
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void channelRead(PacketPtr pkt, Addr daddr, int size);
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void channelWrite(PacketPtr pkt, Addr daddr, int size);
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unsigned int drain(Event *de);
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void resume();
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void serialize(std::ostream &os);
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void unserialize(Checkpoint *cp, const std::string §ion);
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private:
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void fetchDescriptor(Addr address);
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void fetchDescComplete();
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EventWrapper<CopyEngineChannel, &CopyEngineChannel::fetchDescComplete>
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fetchCompleteEvent;
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void fetchNextAddr(Addr address);
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void fetchAddrComplete();
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EventWrapper<CopyEngineChannel, &CopyEngineChannel::fetchAddrComplete>
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addrCompleteEvent;
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void readCopyBytes();
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void readCopyBytesComplete();
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EventWrapper<CopyEngineChannel, &CopyEngineChannel::readCopyBytesComplete>
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readCompleteEvent;
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void writeCopyBytes();
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void writeCopyBytesComplete();
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EventWrapper <CopyEngineChannel, &CopyEngineChannel::writeCopyBytesComplete>
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writeCompleteEvent;
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void writeCompletionStatus();
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void writeStatusComplete();
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EventWrapper <CopyEngineChannel, &CopyEngineChannel::writeStatusComplete>
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statusCompleteEvent;
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void continueProcessing();
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void recvCommand();
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bool inDrain();
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void restartStateMachine();
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inline void anBegin(const char *s)
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{
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CPA::cpa()->hwBegin(CPA::FL_NONE, ce->sys,
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channelId, "CopyEngine", s);
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}
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inline void anWait()
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{
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CPA::cpa()->hwWe(CPA::FL_NONE, ce->sys,
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channelId, "CopyEngine", "DMAUnusedDescQ", channelId);
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}
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inline void anDq()
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{
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CPA::cpa()->hwDq(CPA::FL_NONE, ce->sys,
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channelId, "CopyEngine", "DMAUnusedDescQ", channelId);
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}
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inline void anPq()
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{
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CPA::cpa()->hwDq(CPA::FL_NONE, ce->sys,
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channelId, "CopyEngine", "DMAUnusedDescQ", channelId);
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}
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inline void anQ(const char * s, uint64_t id, int size = 1)
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{
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CPA::cpa()->hwQ(CPA::FL_NONE, ce->sys, channelId,
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"CopyEngine", s, id, NULL, size);
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}
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};
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private:
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Stats::Vector bytesCopied;
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Stats::Vector copiesProcessed;
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// device registers
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CopyEngineReg::Regs regs;
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// Array of channels each one with regs/dma port/etc
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std::vector<CopyEngineChannel*> chan;
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public:
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typedef CopyEngineParams Params;
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const Params *
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params() const
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{
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return dynamic_cast<const Params *>(_params);
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}
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CopyEngine(const Params *params);
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~CopyEngine();
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void regStats();
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virtual MasterPort &getMasterPort(const std::string &if_name,
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int idx = -1);
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virtual Tick read(PacketPtr pkt);
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virtual Tick write(PacketPtr pkt);
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virtual void serialize(std::ostream &os);
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virtual void unserialize(Checkpoint *cp, const std::string §ion);
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virtual unsigned int drain(Event *de);
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virtual void resume();
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};
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#endif //__DEV_COPY_ENGINE_HH__
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