Adding gem5 source to svn.
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1819 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
This commit is contained in:
friemel
561
simulators/gem5/src/cpu/simple/atomic.cc
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561
simulators/gem5/src/cpu/simple/atomic.cc
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@ -0,0 +1,561 @@
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/*
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* Copyright (c) 2012 ARM Limited
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* All rights reserved.
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*
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* The license below extends only to copyright in the software and shall
|
||||
* not be construed as granting a license to any other intellectual
|
||||
* property including but not limited to intellectual property relating
|
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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||||
* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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||||
* Copyright (c) 2002-2005 The Regents of The University of Michigan
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* All rights reserved.
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||||
*
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* Redistribution and use in source and binary forms, with or without
|
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* modification, are permitted provided that the following conditions are
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||||
* met: redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer;
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||||
* redistributions in binary form must reproduce the above copyright
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||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution;
|
||||
* neither the name of the copyright holders nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from
|
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* this software without specific prior written permission.
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||||
*
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||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Steve Reinhardt
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*/
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#include "arch/locked_mem.hh"
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#include "arch/mmapped_ipr.hh"
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#include "arch/utility.hh"
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#include "base/bigint.hh"
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#include "config/the_isa.hh"
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#include "cpu/simple/atomic.hh"
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#include "cpu/exetrace.hh"
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#include "debug/ExecFaulting.hh"
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#include "debug/SimpleCPU.hh"
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#include "mem/packet.hh"
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#include "mem/packet_access.hh"
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#include "mem/physical.hh"
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#include "params/AtomicSimpleCPU.hh"
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#include "sim/faults.hh"
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#include "sim/system.hh"
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#include "sim/full_system.hh"
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using namespace std;
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using namespace TheISA;
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AtomicSimpleCPU::TickEvent::TickEvent(AtomicSimpleCPU *c)
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: Event(CPU_Tick_Pri), cpu(c)
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{
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}
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void
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AtomicSimpleCPU::TickEvent::process()
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{
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cpu->tick();
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}
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const char *
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AtomicSimpleCPU::TickEvent::description() const
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{
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return "AtomicSimpleCPU tick";
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}
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void
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AtomicSimpleCPU::init()
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{
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BaseCPU::init();
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// Initialise the ThreadContext's memory proxies
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tcBase()->initMemProxies(tcBase());
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if (FullSystem && !params()->defer_registration) {
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ThreadID size = threadContexts.size();
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for (ThreadID i = 0; i < size; ++i) {
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ThreadContext *tc = threadContexts[i];
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// initialize CPU, including PC
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TheISA::initCPU(tc, tc->contextId());
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}
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}
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// Atomic doesn't do MT right now, so contextId == threadId
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ifetch_req.setThreadContext(_cpuId, 0); // Add thread ID if we add MT
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data_read_req.setThreadContext(_cpuId, 0); // Add thread ID here too
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data_write_req.setThreadContext(_cpuId, 0); // Add thread ID here too
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}
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AtomicSimpleCPU::AtomicSimpleCPU(AtomicSimpleCPUParams *p)
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: BaseSimpleCPU(p), tickEvent(this), width(p->width), locked(false),
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simulate_data_stalls(p->simulate_data_stalls),
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simulate_inst_stalls(p->simulate_inst_stalls),
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icachePort(name() + "-iport", this), dcachePort(name() + "-iport", this),
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fastmem(p->fastmem)
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{
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_status = Idle;
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}
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AtomicSimpleCPU::~AtomicSimpleCPU()
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{
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if (tickEvent.scheduled()) {
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deschedule(tickEvent);
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}
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}
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void
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AtomicSimpleCPU::serialize(ostream &os)
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{
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SimObject::State so_state = SimObject::getState();
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SERIALIZE_ENUM(so_state);
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SERIALIZE_SCALAR(locked);
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BaseSimpleCPU::serialize(os);
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nameOut(os, csprintf("%s.tickEvent", name()));
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tickEvent.serialize(os);
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}
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void
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AtomicSimpleCPU::unserialize(Checkpoint *cp, const string §ion)
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{
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SimObject::State so_state;
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UNSERIALIZE_ENUM(so_state);
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UNSERIALIZE_SCALAR(locked);
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BaseSimpleCPU::unserialize(cp, section);
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tickEvent.unserialize(cp, csprintf("%s.tickEvent", section));
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}
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void
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AtomicSimpleCPU::resume()
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{
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if (_status == Idle || _status == SwitchedOut)
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return;
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DPRINTF(SimpleCPU, "Resume\n");
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assert(system->getMemoryMode() == Enums::atomic);
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changeState(SimObject::Running);
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if (thread->status() == ThreadContext::Active) {
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if (!tickEvent.scheduled())
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schedule(tickEvent, nextCycle());
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}
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system->totalNumInsts = 0;
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}
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void
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AtomicSimpleCPU::switchOut()
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{
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assert(_status == Running || _status == Idle);
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_status = SwitchedOut;
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tickEvent.squash();
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}
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void
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AtomicSimpleCPU::takeOverFrom(BaseCPU *oldCPU)
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{
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BaseCPU::takeOverFrom(oldCPU);
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assert(!tickEvent.scheduled());
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// if any of this CPU's ThreadContexts are active, mark the CPU as
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// running and schedule its tick event.
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ThreadID size = threadContexts.size();
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for (ThreadID i = 0; i < size; ++i) {
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ThreadContext *tc = threadContexts[i];
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if (tc->status() == ThreadContext::Active && _status != Running) {
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_status = Running;
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schedule(tickEvent, nextCycle());
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break;
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}
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}
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if (_status != Running) {
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_status = Idle;
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}
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assert(threadContexts.size() == 1);
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ifetch_req.setThreadContext(_cpuId, 0); // Add thread ID if we add MT
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data_read_req.setThreadContext(_cpuId, 0); // Add thread ID here too
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data_write_req.setThreadContext(_cpuId, 0); // Add thread ID here too
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}
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void
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AtomicSimpleCPU::activateContext(ThreadID thread_num, int delay)
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{
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DPRINTF(SimpleCPU, "ActivateContext %d (%d cycles)\n", thread_num, delay);
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assert(thread_num == 0);
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assert(thread);
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assert(_status == Idle);
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assert(!tickEvent.scheduled());
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notIdleFraction++;
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numCycles += tickToCycles(thread->lastActivate - thread->lastSuspend);
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//Make sure ticks are still on multiples of cycles
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schedule(tickEvent, nextCycle(curTick() + ticks(delay)));
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_status = Running;
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}
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void
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AtomicSimpleCPU::suspendContext(ThreadID thread_num)
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{
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DPRINTF(SimpleCPU, "SuspendContext %d\n", thread_num);
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assert(thread_num == 0);
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assert(thread);
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if (_status == Idle)
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return;
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assert(_status == Running);
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// tick event may not be scheduled if this gets called from inside
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// an instruction's execution, e.g. "quiesce"
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if (tickEvent.scheduled())
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deschedule(tickEvent);
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notIdleFraction--;
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_status = Idle;
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}
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Fault
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AtomicSimpleCPU::readMem(Addr addr, uint8_t * data,
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unsigned size, unsigned flags)
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{
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// use the CPU's statically allocated read request and packet objects
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Request *req = &data_read_req;
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if (traceData) {
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traceData->setAddr(addr);
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}
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//The block size of our peer.
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unsigned blockSize = dcachePort.peerBlockSize();
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//The size of the data we're trying to read.
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int fullSize = size;
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//The address of the second part of this access if it needs to be split
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//across a cache line boundary.
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Addr secondAddr = roundDown(addr + size - 1, blockSize);
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if (secondAddr > addr)
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size = secondAddr - addr;
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dcache_latency = 0;
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while (1) {
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req->setVirt(0, addr, size, flags, dataMasterId(), thread->pcState().instAddr());
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// translate to physical address
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Fault fault = thread->dtb->translateAtomic(req, tc, BaseTLB::Read);
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// Now do the access.
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if (fault == NoFault && !req->getFlags().isSet(Request::NO_ACCESS)) {
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Packet pkt = Packet(req,
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req->isLLSC() ? MemCmd::LoadLockedReq :
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MemCmd::ReadReq);
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pkt.dataStatic(data);
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if (req->isMmappedIpr())
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dcache_latency += TheISA::handleIprRead(thread->getTC(), &pkt);
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else {
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if (fastmem && system->isMemAddr(pkt.getAddr()))
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system->getPhysMem().access(&pkt);
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else
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dcache_latency += dcachePort.sendAtomic(&pkt);
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}
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dcache_access = true;
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assert(!pkt.isError());
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if (req->isLLSC()) {
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TheISA::handleLockedRead(thread, req);
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}
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}
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//If there's a fault, return it
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if (fault != NoFault) {
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if (req->isPrefetch()) {
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return NoFault;
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} else {
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return fault;
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}
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}
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//If we don't need to access a second cache line, stop now.
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if (secondAddr <= addr)
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{
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if (req->isLocked() && fault == NoFault) {
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assert(!locked);
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locked = true;
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}
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return fault;
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}
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/*
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* Set up for accessing the second cache line.
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*/
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//Move the pointer we're reading into to the correct location.
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data += size;
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//Adjust the size to get the remaining bytes.
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size = addr + fullSize - secondAddr;
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//And access the right address.
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addr = secondAddr;
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}
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}
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Fault
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AtomicSimpleCPU::writeMem(uint8_t *data, unsigned size,
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Addr addr, unsigned flags, uint64_t *res)
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{
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// use the CPU's statically allocated write request and packet objects
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Request *req = &data_write_req;
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if (traceData) {
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traceData->setAddr(addr);
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}
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//The block size of our peer.
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unsigned blockSize = dcachePort.peerBlockSize();
|
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//The size of the data we're trying to read.
|
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int fullSize = size;
|
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|
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//The address of the second part of this access if it needs to be split
|
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//across a cache line boundary.
|
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Addr secondAddr = roundDown(addr + size - 1, blockSize);
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if(secondAddr > addr)
|
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size = secondAddr - addr;
|
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dcache_latency = 0;
|
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while(1) {
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req->setVirt(0, addr, size, flags, dataMasterId(), thread->pcState().instAddr());
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// translate to physical address
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Fault fault = thread->dtb->translateAtomic(req, tc, BaseTLB::Write);
|
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// Now do the access.
|
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if (fault == NoFault) {
|
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MemCmd cmd = MemCmd::WriteReq; // default
|
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bool do_access = true; // flag to suppress cache access
|
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|
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if (req->isLLSC()) {
|
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cmd = MemCmd::StoreCondReq;
|
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do_access = TheISA::handleLockedWrite(thread, req);
|
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} else if (req->isSwap()) {
|
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cmd = MemCmd::SwapReq;
|
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if (req->isCondSwap()) {
|
||||
assert(res);
|
||||
req->setExtraData(*res);
|
||||
}
|
||||
}
|
||||
|
||||
if (do_access && !req->getFlags().isSet(Request::NO_ACCESS)) {
|
||||
Packet pkt = Packet(req, cmd);
|
||||
pkt.dataStatic(data);
|
||||
|
||||
if (req->isMmappedIpr()) {
|
||||
dcache_latency +=
|
||||
TheISA::handleIprWrite(thread->getTC(), &pkt);
|
||||
} else {
|
||||
if (fastmem && system->isMemAddr(pkt.getAddr()))
|
||||
system->getPhysMem().access(&pkt);
|
||||
else
|
||||
dcache_latency += dcachePort.sendAtomic(&pkt);
|
||||
}
|
||||
dcache_access = true;
|
||||
assert(!pkt.isError());
|
||||
|
||||
if (req->isSwap()) {
|
||||
assert(res);
|
||||
memcpy(res, pkt.getPtr<uint8_t>(), fullSize);
|
||||
}
|
||||
}
|
||||
|
||||
if (res && !req->isSwap()) {
|
||||
*res = req->getExtraData();
|
||||
}
|
||||
}
|
||||
|
||||
//If there's a fault or we don't need to access a second cache line,
|
||||
//stop now.
|
||||
if (fault != NoFault || secondAddr <= addr)
|
||||
{
|
||||
if (req->isLocked() && fault == NoFault) {
|
||||
assert(locked);
|
||||
locked = false;
|
||||
}
|
||||
if (fault != NoFault && req->isPrefetch()) {
|
||||
return NoFault;
|
||||
} else {
|
||||
return fault;
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Set up for accessing the second cache line.
|
||||
*/
|
||||
|
||||
//Move the pointer we're reading into to the correct location.
|
||||
data += size;
|
||||
//Adjust the size to get the remaining bytes.
|
||||
size = addr + fullSize - secondAddr;
|
||||
//And access the right address.
|
||||
addr = secondAddr;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void
|
||||
AtomicSimpleCPU::tick()
|
||||
{
|
||||
DPRINTF(SimpleCPU, "Tick\n");
|
||||
|
||||
Tick latency = 0;
|
||||
|
||||
for (int i = 0; i < width || locked; ++i) {
|
||||
numCycles++;
|
||||
|
||||
if (!curStaticInst || !curStaticInst->isDelayedCommit())
|
||||
checkForInterrupts();
|
||||
|
||||
checkPcEventQueue();
|
||||
// We must have just got suspended by a PC event
|
||||
if (_status == Idle)
|
||||
return;
|
||||
|
||||
Fault fault = NoFault;
|
||||
|
||||
TheISA::PCState pcState = thread->pcState();
|
||||
|
||||
bool needToFetch = !isRomMicroPC(pcState.microPC()) &&
|
||||
!curMacroStaticInst;
|
||||
if (needToFetch) {
|
||||
setupFetchRequest(&ifetch_req);
|
||||
fault = thread->itb->translateAtomic(&ifetch_req, tc,
|
||||
BaseTLB::Execute);
|
||||
}
|
||||
|
||||
if (fault == NoFault) {
|
||||
Tick icache_latency = 0;
|
||||
bool icache_access = false;
|
||||
dcache_access = false; // assume no dcache access
|
||||
|
||||
if (needToFetch) {
|
||||
// This is commented out because the decoder would act like
|
||||
// a tiny cache otherwise. It wouldn't be flushed when needed
|
||||
// like the I cache. It should be flushed, and when that works
|
||||
// this code should be uncommented.
|
||||
//Fetch more instruction memory if necessary
|
||||
//if(decoder.needMoreBytes())
|
||||
//{
|
||||
icache_access = true;
|
||||
Packet ifetch_pkt = Packet(&ifetch_req, MemCmd::ReadReq);
|
||||
ifetch_pkt.dataStatic(&inst);
|
||||
|
||||
if (fastmem && system->isMemAddr(ifetch_pkt.getAddr()))
|
||||
system->getPhysMem().access(&ifetch_pkt);
|
||||
else
|
||||
icache_latency = icachePort.sendAtomic(&ifetch_pkt);
|
||||
|
||||
assert(!ifetch_pkt.isError());
|
||||
|
||||
// ifetch_req is initialized to read the instruction directly
|
||||
// into the CPU object's inst field.
|
||||
//}
|
||||
}
|
||||
|
||||
preExecute();
|
||||
|
||||
if (curStaticInst) {
|
||||
fault = curStaticInst->execute(this, traceData);
|
||||
|
||||
// keep an instruction count
|
||||
if (fault == NoFault)
|
||||
countInst();
|
||||
else if (traceData && !DTRACE(ExecFaulting)) {
|
||||
delete traceData;
|
||||
traceData = NULL;
|
||||
}
|
||||
|
||||
postExecute();
|
||||
}
|
||||
|
||||
// @todo remove me after debugging with legion done
|
||||
if (curStaticInst && (!curStaticInst->isMicroop() ||
|
||||
curStaticInst->isFirstMicroop()))
|
||||
instCnt++;
|
||||
|
||||
Tick stall_ticks = 0;
|
||||
if (simulate_inst_stalls && icache_access)
|
||||
stall_ticks += icache_latency;
|
||||
|
||||
if (simulate_data_stalls && dcache_access)
|
||||
stall_ticks += dcache_latency;
|
||||
|
||||
if (stall_ticks) {
|
||||
Tick stall_cycles = stall_ticks / ticks(1);
|
||||
Tick aligned_stall_ticks = ticks(stall_cycles);
|
||||
|
||||
if (aligned_stall_ticks < stall_ticks)
|
||||
aligned_stall_ticks += 1;
|
||||
|
||||
latency += aligned_stall_ticks;
|
||||
}
|
||||
|
||||
}
|
||||
if(fault != NoFault || !stayAtPC)
|
||||
advancePC(fault);
|
||||
}
|
||||
|
||||
// instruction takes at least one cycle
|
||||
if (latency < ticks(1))
|
||||
latency = ticks(1);
|
||||
|
||||
if (_status != Idle)
|
||||
schedule(tickEvent, curTick() + latency);
|
||||
}
|
||||
|
||||
|
||||
void
|
||||
AtomicSimpleCPU::printAddr(Addr a)
|
||||
{
|
||||
dcachePort.printAddr(a);
|
||||
}
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// AtomicSimpleCPU Simulation Object
|
||||
//
|
||||
AtomicSimpleCPU *
|
||||
AtomicSimpleCPUParams::create()
|
||||
{
|
||||
numThreads = 1;
|
||||
if (!FullSystem && workload.size() != 1)
|
||||
panic("only one workload allowed");
|
||||
return new AtomicSimpleCPU(this);
|
||||
}
|
||||
Reference in New Issue
Block a user