Adding gem5 source to svn.
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1819 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
This commit is contained in:
friemel
538
simulators/gem5/src/cpu/o3/inst_queue.hh
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538
simulators/gem5/src/cpu/o3/inst_queue.hh
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/*
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* Copyright (c) 2011 ARM Limited
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* All rights reserved.
|
||||
*
|
||||
* The license below extends only to copyright in the software and shall
|
||||
* not be construed as granting a license to any other intellectual
|
||||
* property including but not limited to intellectual property relating
|
||||
* to a hardware implementation of the functionality of the software
|
||||
* licensed hereunder. You may use the software subject to the license
|
||||
* terms below provided that you ensure that this notice is replicated
|
||||
* unmodified and in its entirety in all distributions of the software,
|
||||
* modified or unmodified, in source code or in binary form.
|
||||
*
|
||||
* Copyright (c) 2004-2006 The Regents of The University of Michigan
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are
|
||||
* met: redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer;
|
||||
* redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution;
|
||||
* neither the name of the copyright holders nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
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||||
* Authors: Kevin Lim
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||||
*/
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||||
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#ifndef __CPU_O3_INST_QUEUE_HH__
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#define __CPU_O3_INST_QUEUE_HH__
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#include <list>
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#include <map>
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#include <queue>
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#include <vector>
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#include "base/statistics.hh"
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#include "base/types.hh"
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#include "cpu/o3/dep_graph.hh"
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#include "cpu/inst_seq.hh"
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#include "cpu/op_class.hh"
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#include "cpu/timebuf.hh"
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#include "sim/eventq.hh"
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struct DerivO3CPUParams;
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class FUPool;
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class MemInterface;
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/**
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* A standard instruction queue class. It holds ready instructions, in
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* order, in seperate priority queues to facilitate the scheduling of
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* instructions. The IQ uses a separate linked list to track dependencies.
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* Similar to the rename map and the free list, it expects that
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* floating point registers have their indices start after the integer
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* registers (ie with 96 int and 96 fp registers, regs 0-95 are integer
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* and 96-191 are fp). This remains true even for both logical and
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* physical register indices. The IQ depends on the memory dependence unit to
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* track when memory operations are ready in terms of ordering; register
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* dependencies are tracked normally. Right now the IQ also handles the
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* execution timing; this is mainly to allow back-to-back scheduling without
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* requiring IEW to be able to peek into the IQ. At the end of the execution
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* latency, the instruction is put into the queue to execute, where it will
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* have the execute() function called on it.
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* @todo: Make IQ able to handle multiple FU pools.
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*/
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template <class Impl>
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class InstructionQueue
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{
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public:
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//Typedefs from the Impl.
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typedef typename Impl::O3CPU O3CPU;
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typedef typename Impl::DynInstPtr DynInstPtr;
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typedef typename Impl::CPUPol::IEW IEW;
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typedef typename Impl::CPUPol::MemDepUnit MemDepUnit;
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typedef typename Impl::CPUPol::IssueStruct IssueStruct;
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typedef typename Impl::CPUPol::TimeStruct TimeStruct;
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// Typedef of iterator through the list of instructions.
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typedef typename std::list<DynInstPtr>::iterator ListIt;
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/** FU completion event class. */
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class FUCompletion : public Event {
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private:
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/** Executing instruction. */
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DynInstPtr inst;
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/** Index of the FU used for executing. */
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int fuIdx;
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/** Pointer back to the instruction queue. */
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InstructionQueue<Impl> *iqPtr;
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/** Should the FU be added to the list to be freed upon
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* completing this event.
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*/
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bool freeFU;
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public:
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/** Construct a FU completion event. */
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FUCompletion(DynInstPtr &_inst, int fu_idx,
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InstructionQueue<Impl> *iq_ptr);
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virtual void process();
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virtual const char *description() const;
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void setFreeFU() { freeFU = true; }
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};
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/** Constructs an IQ. */
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InstructionQueue(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params);
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/** Destructs the IQ. */
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~InstructionQueue();
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/** Returns the name of the IQ. */
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std::string name() const;
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/** Registers statistics. */
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void regStats();
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/** Resets all instruction queue state. */
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void resetState();
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/** Sets active threads list. */
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void setActiveThreads(std::list<ThreadID> *at_ptr);
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/** Sets the timer buffer between issue and execute. */
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void setIssueToExecuteQueue(TimeBuffer<IssueStruct> *i2eQueue);
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/** Sets the global time buffer. */
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void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);
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/** Switches out the instruction queue. */
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void switchOut();
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/** Takes over execution from another CPU's thread. */
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void takeOverFrom();
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|
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/** Returns if the IQ is switched out. */
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bool isSwitchedOut() { return switchedOut; }
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|
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/** Number of entries needed for given amount of threads. */
|
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int entryAmount(ThreadID num_threads);
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|
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/** Resets max entries for all threads. */
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void resetEntries();
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/** Returns total number of free entries. */
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unsigned numFreeEntries();
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/** Returns number of free entries for a thread. */
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unsigned numFreeEntries(ThreadID tid);
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/** Returns whether or not the IQ is full. */
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bool isFull();
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|
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/** Returns whether or not the IQ is full for a specific thread. */
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bool isFull(ThreadID tid);
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/** Returns if there are any ready instructions in the IQ. */
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bool hasReadyInsts();
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/** Inserts a new instruction into the IQ. */
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void insert(DynInstPtr &new_inst);
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/** Inserts a new, non-speculative instruction into the IQ. */
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void insertNonSpec(DynInstPtr &new_inst);
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/** Inserts a memory or write barrier into the IQ to make sure
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* loads and stores are ordered properly.
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*/
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void insertBarrier(DynInstPtr &barr_inst);
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/** Returns the oldest scheduled instruction, and removes it from
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* the list of instructions waiting to execute.
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*/
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DynInstPtr getInstToExecute();
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|
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/** Returns a memory instruction that was referred due to a delayed DTB
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* translation if it is now ready to execute.
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*/
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DynInstPtr getDeferredMemInstToExecute();
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/**
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* Records the instruction as the producer of a register without
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* adding it to the rest of the IQ.
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*/
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void recordProducer(DynInstPtr &inst)
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{ addToProducers(inst); }
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/** Process FU completion event. */
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void processFUCompletion(DynInstPtr &inst, int fu_idx);
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/**
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* Schedules ready instructions, adding the ready ones (oldest first) to
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* the queue to execute.
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*/
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void scheduleReadyInsts();
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/** Schedules a single specific non-speculative instruction. */
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void scheduleNonSpec(const InstSeqNum &inst);
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/**
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* Commits all instructions up to and including the given sequence number,
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* for a specific thread.
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*/
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void commit(const InstSeqNum &inst, ThreadID tid = 0);
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/** Wakes all dependents of a completed instruction. */
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int wakeDependents(DynInstPtr &completed_inst);
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/** Adds a ready memory instruction to the ready list. */
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void addReadyMemInst(DynInstPtr &ready_inst);
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/**
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* Reschedules a memory instruction. It will be ready to issue once
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* replayMemInst() is called.
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*/
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void rescheduleMemInst(DynInstPtr &resched_inst);
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/** Replays a memory instruction. It must be rescheduled first. */
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void replayMemInst(DynInstPtr &replay_inst);
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/** Completes a memory operation. */
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void completeMemInst(DynInstPtr &completed_inst);
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/**
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* Defers a memory instruction when its DTB translation incurs a hw
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* page table walk.
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*/
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void deferMemInst(DynInstPtr &deferred_inst);
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/** Indicates an ordering violation between a store and a load. */
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void violation(DynInstPtr &store, DynInstPtr &faulting_load);
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/**
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* Squashes instructions for a thread. Squashing information is obtained
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* from the time buffer.
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*/
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void squash(ThreadID tid);
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/** Returns the number of used entries for a thread. */
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unsigned getCount(ThreadID tid) { return count[tid]; };
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/** Debug function to print all instructions. */
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void printInsts();
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private:
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/** Does the actual squashing. */
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void doSquash(ThreadID tid);
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/////////////////////////
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// Various pointers
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/////////////////////////
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/** Pointer to the CPU. */
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O3CPU *cpu;
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/** Cache interface. */
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MemInterface *dcacheInterface;
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/** Pointer to IEW stage. */
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IEW *iewStage;
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/** The memory dependence unit, which tracks/predicts memory dependences
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* between instructions.
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*/
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MemDepUnit memDepUnit[Impl::MaxThreads];
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/** The queue to the execute stage. Issued instructions will be written
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* into it.
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*/
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TimeBuffer<IssueStruct> *issueToExecuteQueue;
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/** The backwards time buffer. */
|
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TimeBuffer<TimeStruct> *timeBuffer;
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/** Wire to read information from timebuffer. */
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typename TimeBuffer<TimeStruct>::wire fromCommit;
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/** Function unit pool. */
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FUPool *fuPool;
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//////////////////////////////////////
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// Instruction lists, ready queues, and ordering
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//////////////////////////////////////
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/** List of all the instructions in the IQ (some of which may be issued). */
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std::list<DynInstPtr> instList[Impl::MaxThreads];
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/** List of instructions that are ready to be executed. */
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std::list<DynInstPtr> instsToExecute;
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/** List of instructions waiting for their DTB translation to
|
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* complete (hw page table walk in progress).
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*/
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std::list<DynInstPtr> deferredMemInsts;
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/**
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* Struct for comparing entries to be added to the priority queue.
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* This gives reverse ordering to the instructions in terms of
|
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* sequence numbers: the instructions with smaller sequence
|
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* numbers (and hence are older) will be at the top of the
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* priority queue.
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*/
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struct pqCompare {
|
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bool operator() (const DynInstPtr &lhs, const DynInstPtr &rhs) const
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||||
{
|
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return lhs->seqNum > rhs->seqNum;
|
||||
}
|
||||
};
|
||||
|
||||
typedef std::priority_queue<DynInstPtr, std::vector<DynInstPtr>, pqCompare>
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ReadyInstQueue;
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/** List of ready instructions, per op class. They are separated by op
|
||||
* class to allow for easy mapping to FUs.
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*/
|
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ReadyInstQueue readyInsts[Num_OpClasses];
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/** List of non-speculative instructions that will be scheduled
|
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* once the IQ gets a signal from commit. While it's redundant to
|
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* have the key be a part of the value (the sequence number is stored
|
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* inside of DynInst), when these instructions are woken up only
|
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* the sequence number will be available. Thus it is most efficient to be
|
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* able to search by the sequence number alone.
|
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*/
|
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std::map<InstSeqNum, DynInstPtr> nonSpecInsts;
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||||
|
||||
typedef typename std::map<InstSeqNum, DynInstPtr>::iterator NonSpecMapIt;
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||||
|
||||
/** Entry for the list age ordering by op class. */
|
||||
struct ListOrderEntry {
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||||
OpClass queueType;
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||||
InstSeqNum oldestInst;
|
||||
};
|
||||
|
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/** List that contains the age order of the oldest instruction of each
|
||||
* ready queue. Used to select the oldest instruction available
|
||||
* among op classes.
|
||||
* @todo: Might be better to just move these entries around instead
|
||||
* of creating new ones every time the position changes due to an
|
||||
* instruction issuing. Not sure std::list supports this.
|
||||
*/
|
||||
std::list<ListOrderEntry> listOrder;
|
||||
|
||||
typedef typename std::list<ListOrderEntry>::iterator ListOrderIt;
|
||||
|
||||
/** Tracks if each ready queue is on the age order list. */
|
||||
bool queueOnList[Num_OpClasses];
|
||||
|
||||
/** Iterators of each ready queue. Points to their spot in the age order
|
||||
* list.
|
||||
*/
|
||||
ListOrderIt readyIt[Num_OpClasses];
|
||||
|
||||
/** Add an op class to the age order list. */
|
||||
void addToOrderList(OpClass op_class);
|
||||
|
||||
/**
|
||||
* Called when the oldest instruction has been removed from a ready queue;
|
||||
* this places that ready queue into the proper spot in the age order list.
|
||||
*/
|
||||
void moveToYoungerInst(ListOrderIt age_order_it);
|
||||
|
||||
DependencyGraph<DynInstPtr> dependGraph;
|
||||
|
||||
//////////////////////////////////////
|
||||
// Various parameters
|
||||
//////////////////////////////////////
|
||||
|
||||
/** IQ Resource Sharing Policy */
|
||||
enum IQPolicy {
|
||||
Dynamic,
|
||||
Partitioned,
|
||||
Threshold
|
||||
};
|
||||
|
||||
/** IQ sharing policy for SMT. */
|
||||
IQPolicy iqPolicy;
|
||||
|
||||
/** Number of Total Threads*/
|
||||
ThreadID numThreads;
|
||||
|
||||
/** Pointer to list of active threads. */
|
||||
std::list<ThreadID> *activeThreads;
|
||||
|
||||
/** Per Thread IQ count */
|
||||
unsigned count[Impl::MaxThreads];
|
||||
|
||||
/** Max IQ Entries Per Thread */
|
||||
unsigned maxEntries[Impl::MaxThreads];
|
||||
|
||||
/** Number of free IQ entries left. */
|
||||
unsigned freeEntries;
|
||||
|
||||
/** The number of entries in the instruction queue. */
|
||||
unsigned numEntries;
|
||||
|
||||
/** The total number of instructions that can be issued in one cycle. */
|
||||
unsigned totalWidth;
|
||||
|
||||
/** The number of physical registers in the CPU. */
|
||||
unsigned numPhysRegs;
|
||||
|
||||
/** The number of physical integer registers in the CPU. */
|
||||
unsigned numPhysIntRegs;
|
||||
|
||||
/** The number of floating point registers in the CPU. */
|
||||
unsigned numPhysFloatRegs;
|
||||
|
||||
/** Delay between commit stage and the IQ.
|
||||
* @todo: Make there be a distinction between the delays within IEW.
|
||||
*/
|
||||
unsigned commitToIEWDelay;
|
||||
|
||||
/** Is the IQ switched out. */
|
||||
bool switchedOut;
|
||||
|
||||
/** The sequence number of the squashed instruction. */
|
||||
InstSeqNum squashedSeqNum[Impl::MaxThreads];
|
||||
|
||||
/** A cache of the recently woken registers. It is 1 if the register
|
||||
* has been woken up recently, and 0 if the register has been added
|
||||
* to the dependency graph and has not yet received its value. It
|
||||
* is basically a secondary scoreboard, and should pretty much mirror
|
||||
* the scoreboard that exists in the rename map.
|
||||
*/
|
||||
std::vector<bool> regScoreboard;
|
||||
|
||||
/** Adds an instruction to the dependency graph, as a consumer. */
|
||||
bool addToDependents(DynInstPtr &new_inst);
|
||||
|
||||
/** Adds an instruction to the dependency graph, as a producer. */
|
||||
void addToProducers(DynInstPtr &new_inst);
|
||||
|
||||
/** Moves an instruction to the ready queue if it is ready. */
|
||||
void addIfReady(DynInstPtr &inst);
|
||||
|
||||
/** Debugging function to count how many entries are in the IQ. It does
|
||||
* a linear walk through the instructions, so do not call this function
|
||||
* during normal execution.
|
||||
*/
|
||||
int countInsts();
|
||||
|
||||
/** Debugging function to dump all the list sizes, as well as print
|
||||
* out the list of nonspeculative instructions. Should not be used
|
||||
* in any other capacity, but it has no harmful sideaffects.
|
||||
*/
|
||||
void dumpLists();
|
||||
|
||||
/** Debugging function to dump out all instructions that are in the
|
||||
* IQ.
|
||||
*/
|
||||
void dumpInsts();
|
||||
|
||||
/** Stat for number of instructions added. */
|
||||
Stats::Scalar iqInstsAdded;
|
||||
/** Stat for number of non-speculative instructions added. */
|
||||
Stats::Scalar iqNonSpecInstsAdded;
|
||||
|
||||
Stats::Scalar iqInstsIssued;
|
||||
/** Stat for number of integer instructions issued. */
|
||||
Stats::Scalar iqIntInstsIssued;
|
||||
/** Stat for number of floating point instructions issued. */
|
||||
Stats::Scalar iqFloatInstsIssued;
|
||||
/** Stat for number of branch instructions issued. */
|
||||
Stats::Scalar iqBranchInstsIssued;
|
||||
/** Stat for number of memory instructions issued. */
|
||||
Stats::Scalar iqMemInstsIssued;
|
||||
/** Stat for number of miscellaneous instructions issued. */
|
||||
Stats::Scalar iqMiscInstsIssued;
|
||||
/** Stat for number of squashed instructions that were ready to issue. */
|
||||
Stats::Scalar iqSquashedInstsIssued;
|
||||
/** Stat for number of squashed instructions examined when squashing. */
|
||||
Stats::Scalar iqSquashedInstsExamined;
|
||||
/** Stat for number of squashed instruction operands examined when
|
||||
* squashing.
|
||||
*/
|
||||
Stats::Scalar iqSquashedOperandsExamined;
|
||||
/** Stat for number of non-speculative instructions removed due to a squash.
|
||||
*/
|
||||
Stats::Scalar iqSquashedNonSpecRemoved;
|
||||
// Also include number of instructions rescheduled and replayed.
|
||||
|
||||
/** Distribution of number of instructions in the queue.
|
||||
* @todo: Need to create struct to track the entry time for each
|
||||
* instruction. */
|
||||
// Stats::VectorDistribution queueResDist;
|
||||
/** Distribution of the number of instructions issued. */
|
||||
Stats::Distribution numIssuedDist;
|
||||
/** Distribution of the cycles it takes to issue an instruction.
|
||||
* @todo: Need to create struct to track the ready time for each
|
||||
* instruction. */
|
||||
// Stats::VectorDistribution issueDelayDist;
|
||||
|
||||
/** Number of times an instruction could not be issued because a
|
||||
* FU was busy.
|
||||
*/
|
||||
Stats::Vector statFuBusy;
|
||||
// Stats::Vector dist_unissued;
|
||||
/** Stat for total number issued for each instruction type. */
|
||||
Stats::Vector2d statIssuedInstType;
|
||||
|
||||
/** Number of instructions issued per cycle. */
|
||||
Stats::Formula issueRate;
|
||||
|
||||
/** Number of times the FU was busy. */
|
||||
Stats::Vector fuBusy;
|
||||
/** Number of times the FU was busy per instruction issued. */
|
||||
Stats::Formula fuBusyRate;
|
||||
public:
|
||||
Stats::Scalar intInstQueueReads;
|
||||
Stats::Scalar intInstQueueWrites;
|
||||
Stats::Scalar intInstQueueWakeupAccesses;
|
||||
Stats::Scalar fpInstQueueReads;
|
||||
Stats::Scalar fpInstQueueWrites;
|
||||
Stats::Scalar fpInstQueueWakeupQccesses;
|
||||
|
||||
Stats::Scalar intAluAccesses;
|
||||
Stats::Scalar fpAluAccesses;
|
||||
};
|
||||
|
||||
#endif //__CPU_O3_INST_QUEUE_HH__
|
||||
Reference in New Issue
Block a user