Adding gem5 source to svn.
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1819 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
This commit is contained in:
friemel
761
simulators/gem5/src/cpu/o3/decode_impl.hh
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761
simulators/gem5/src/cpu/o3/decode_impl.hh
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/*
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* Copyright (c) 2004-2006 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Kevin Lim
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*/
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#include "arch/types.hh"
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#include "base/trace.hh"
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#include "config/the_isa.hh"
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#include "cpu/o3/decode.hh"
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#include "cpu/inst_seq.hh"
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#include "debug/Activity.hh"
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#include "debug/Decode.hh"
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#include "params/DerivO3CPU.hh"
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#include "sim/full_system.hh"
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// clang complains about std::set being overloaded with Packet::set if
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// we open up the entire namespace std
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using std::list;
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template<class Impl>
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DefaultDecode<Impl>::DefaultDecode(O3CPU *_cpu, DerivO3CPUParams *params)
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: cpu(_cpu),
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renameToDecodeDelay(params->renameToDecodeDelay),
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iewToDecodeDelay(params->iewToDecodeDelay),
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commitToDecodeDelay(params->commitToDecodeDelay),
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fetchToDecodeDelay(params->fetchToDecodeDelay),
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decodeWidth(params->decodeWidth),
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numThreads(params->numThreads)
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{
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_status = Inactive;
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// Setup status, make sure stall signals are clear.
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for (ThreadID tid = 0; tid < numThreads; ++tid) {
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decodeStatus[tid] = Idle;
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stalls[tid].rename = false;
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stalls[tid].iew = false;
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stalls[tid].commit = false;
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}
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// @todo: Make into a parameter
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skidBufferMax = (fetchToDecodeDelay + 1) * params->fetchWidth;
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}
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template <class Impl>
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std::string
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DefaultDecode<Impl>::name() const
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{
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return cpu->name() + ".decode";
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}
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template <class Impl>
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void
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DefaultDecode<Impl>::regStats()
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{
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decodeIdleCycles
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.name(name() + ".IdleCycles")
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.desc("Number of cycles decode is idle")
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.prereq(decodeIdleCycles);
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decodeBlockedCycles
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.name(name() + ".BlockedCycles")
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.desc("Number of cycles decode is blocked")
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.prereq(decodeBlockedCycles);
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decodeRunCycles
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.name(name() + ".RunCycles")
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.desc("Number of cycles decode is running")
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.prereq(decodeRunCycles);
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decodeUnblockCycles
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.name(name() + ".UnblockCycles")
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.desc("Number of cycles decode is unblocking")
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.prereq(decodeUnblockCycles);
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decodeSquashCycles
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.name(name() + ".SquashCycles")
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.desc("Number of cycles decode is squashing")
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.prereq(decodeSquashCycles);
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decodeBranchResolved
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.name(name() + ".BranchResolved")
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.desc("Number of times decode resolved a branch")
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.prereq(decodeBranchResolved);
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decodeBranchMispred
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.name(name() + ".BranchMispred")
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.desc("Number of times decode detected a branch misprediction")
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.prereq(decodeBranchMispred);
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decodeControlMispred
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.name(name() + ".ControlMispred")
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.desc("Number of times decode detected an instruction incorrectly"
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" predicted as a control")
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.prereq(decodeControlMispred);
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decodeDecodedInsts
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.name(name() + ".DecodedInsts")
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.desc("Number of instructions handled by decode")
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.prereq(decodeDecodedInsts);
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decodeSquashedInsts
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.name(name() + ".SquashedInsts")
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.desc("Number of squashed instructions handled by decode")
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.prereq(decodeSquashedInsts);
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}
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template<class Impl>
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void
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DefaultDecode<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
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{
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timeBuffer = tb_ptr;
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// Setup wire to write information back to fetch.
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toFetch = timeBuffer->getWire(0);
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// Create wires to get information from proper places in time buffer.
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fromRename = timeBuffer->getWire(-renameToDecodeDelay);
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fromIEW = timeBuffer->getWire(-iewToDecodeDelay);
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fromCommit = timeBuffer->getWire(-commitToDecodeDelay);
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}
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template<class Impl>
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void
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DefaultDecode<Impl>::setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr)
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{
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decodeQueue = dq_ptr;
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// Setup wire to write information to proper place in decode queue.
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toRename = decodeQueue->getWire(0);
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}
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template<class Impl>
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void
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DefaultDecode<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr)
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{
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fetchQueue = fq_ptr;
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// Setup wire to read information from fetch queue.
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fromFetch = fetchQueue->getWire(-fetchToDecodeDelay);
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}
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template<class Impl>
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void
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DefaultDecode<Impl>::setActiveThreads(std::list<ThreadID> *at_ptr)
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{
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activeThreads = at_ptr;
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}
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template <class Impl>
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bool
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DefaultDecode<Impl>::drain()
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{
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// Decode is done draining at any time.
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cpu->signalDrained();
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return true;
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}
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template <class Impl>
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void
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DefaultDecode<Impl>::takeOverFrom()
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{
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_status = Inactive;
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// Be sure to reset state and clear out any old instructions.
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for (ThreadID tid = 0; tid < numThreads; ++tid) {
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decodeStatus[tid] = Idle;
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stalls[tid].rename = false;
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stalls[tid].iew = false;
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stalls[tid].commit = false;
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while (!insts[tid].empty())
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insts[tid].pop();
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while (!skidBuffer[tid].empty())
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skidBuffer[tid].pop();
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branchCount[tid] = 0;
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}
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wroteToTimeBuffer = false;
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}
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template<class Impl>
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bool
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DefaultDecode<Impl>::checkStall(ThreadID tid) const
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{
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bool ret_val = false;
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if (stalls[tid].rename) {
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DPRINTF(Decode,"[tid:%i]: Stall fom Rename stage detected.\n", tid);
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ret_val = true;
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} else if (stalls[tid].iew) {
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DPRINTF(Decode,"[tid:%i]: Stall fom IEW stage detected.\n", tid);
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ret_val = true;
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} else if (stalls[tid].commit) {
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DPRINTF(Decode,"[tid:%i]: Stall fom Commit stage detected.\n", tid);
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ret_val = true;
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}
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return ret_val;
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}
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template<class Impl>
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inline bool
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DefaultDecode<Impl>::fetchInstsValid()
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{
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return fromFetch->size > 0;
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}
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template<class Impl>
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bool
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DefaultDecode<Impl>::block(ThreadID tid)
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{
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DPRINTF(Decode, "[tid:%u]: Blocking.\n", tid);
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// Add the current inputs to the skid buffer so they can be
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// reprocessed when this stage unblocks.
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skidInsert(tid);
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// If the decode status is blocked or unblocking then decode has not yet
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// signalled fetch to unblock. In that case, there is no need to tell
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// fetch to block.
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if (decodeStatus[tid] != Blocked) {
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// Set the status to Blocked.
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decodeStatus[tid] = Blocked;
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if (decodeStatus[tid] != Unblocking) {
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toFetch->decodeBlock[tid] = true;
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wroteToTimeBuffer = true;
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}
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return true;
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}
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return false;
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}
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template<class Impl>
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bool
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DefaultDecode<Impl>::unblock(ThreadID tid)
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{
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// Decode is done unblocking only if the skid buffer is empty.
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if (skidBuffer[tid].empty()) {
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DPRINTF(Decode, "[tid:%u]: Done unblocking.\n", tid);
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toFetch->decodeUnblock[tid] = true;
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wroteToTimeBuffer = true;
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decodeStatus[tid] = Running;
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return true;
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}
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DPRINTF(Decode, "[tid:%u]: Currently unblocking.\n", tid);
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return false;
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}
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template<class Impl>
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void
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DefaultDecode<Impl>::squash(DynInstPtr &inst, ThreadID tid)
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{
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DPRINTF(Decode, "[tid:%i]: [sn:%i] Squashing due to incorrect branch "
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"prediction detected at decode.\n", tid, inst->seqNum);
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// Send back mispredict information.
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toFetch->decodeInfo[tid].branchMispredict = true;
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toFetch->decodeInfo[tid].predIncorrect = true;
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toFetch->decodeInfo[tid].mispredictInst = inst;
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toFetch->decodeInfo[tid].squash = true;
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toFetch->decodeInfo[tid].doneSeqNum = inst->seqNum;
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toFetch->decodeInfo[tid].nextPC = inst->branchTarget();
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toFetch->decodeInfo[tid].branchTaken = inst->pcState().branching();
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toFetch->decodeInfo[tid].squashInst = inst;
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if (toFetch->decodeInfo[tid].mispredictInst->isUncondCtrl()) {
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toFetch->decodeInfo[tid].branchTaken = true;
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}
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InstSeqNum squash_seq_num = inst->seqNum;
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// Might have to tell fetch to unblock.
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if (decodeStatus[tid] == Blocked ||
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decodeStatus[tid] == Unblocking) {
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toFetch->decodeUnblock[tid] = 1;
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}
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// Set status to squashing.
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decodeStatus[tid] = Squashing;
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for (int i=0; i<fromFetch->size; i++) {
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if (fromFetch->insts[i]->threadNumber == tid &&
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fromFetch->insts[i]->seqNum > squash_seq_num) {
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fromFetch->insts[i]->setSquashed();
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}
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}
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// Clear the instruction list and skid buffer in case they have any
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// insts in them.
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while (!insts[tid].empty()) {
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insts[tid].pop();
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}
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while (!skidBuffer[tid].empty()) {
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skidBuffer[tid].pop();
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}
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// Squash instructions up until this one
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cpu->removeInstsUntil(squash_seq_num, tid);
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}
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template<class Impl>
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unsigned
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DefaultDecode<Impl>::squash(ThreadID tid)
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{
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DPRINTF(Decode, "[tid:%i]: Squashing.\n",tid);
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if (decodeStatus[tid] == Blocked ||
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decodeStatus[tid] == Unblocking) {
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if (FullSystem) {
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toFetch->decodeUnblock[tid] = 1;
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} else {
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// In syscall emulation, we can have both a block and a squash due
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// to a syscall in the same cycle. This would cause both signals
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// to be high. This shouldn't happen in full system.
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// @todo: Determine if this still happens.
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if (toFetch->decodeBlock[tid])
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toFetch->decodeBlock[tid] = 0;
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else
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toFetch->decodeUnblock[tid] = 1;
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}
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}
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// Set status to squashing.
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decodeStatus[tid] = Squashing;
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// Go through incoming instructions from fetch and squash them.
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unsigned squash_count = 0;
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for (int i=0; i<fromFetch->size; i++) {
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if (fromFetch->insts[i]->threadNumber == tid) {
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fromFetch->insts[i]->setSquashed();
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squash_count++;
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}
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}
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// Clear the instruction list and skid buffer in case they have any
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// insts in them.
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while (!insts[tid].empty()) {
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insts[tid].pop();
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}
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while (!skidBuffer[tid].empty()) {
|
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skidBuffer[tid].pop();
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}
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return squash_count;
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}
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template<class Impl>
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void
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DefaultDecode<Impl>::skidInsert(ThreadID tid)
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{
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DynInstPtr inst = NULL;
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while (!insts[tid].empty()) {
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inst = insts[tid].front();
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insts[tid].pop();
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assert(tid == inst->threadNumber);
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DPRINTF(Decode,"Inserting [sn:%lli] PC: %s into decode skidBuffer %i\n",
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inst->seqNum, inst->pcState(), inst->threadNumber);
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skidBuffer[tid].push(inst);
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}
|
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|
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// @todo: Eventually need to enforce this by not letting a thread
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// fetch past its skidbuffer
|
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assert(skidBuffer[tid].size() <= skidBufferMax);
|
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}
|
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template<class Impl>
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bool
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DefaultDecode<Impl>::skidsEmpty()
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{
|
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list<ThreadID>::iterator threads = activeThreads->begin();
|
||||
list<ThreadID>::iterator end = activeThreads->end();
|
||||
|
||||
while (threads != end) {
|
||||
ThreadID tid = *threads++;
|
||||
if (!skidBuffer[tid].empty())
|
||||
return false;
|
||||
}
|
||||
|
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return true;
|
||||
}
|
||||
|
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template<class Impl>
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void
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||||
DefaultDecode<Impl>::updateStatus()
|
||||
{
|
||||
bool any_unblocking = false;
|
||||
|
||||
list<ThreadID>::iterator threads = activeThreads->begin();
|
||||
list<ThreadID>::iterator end = activeThreads->end();
|
||||
|
||||
while (threads != end) {
|
||||
ThreadID tid = *threads++;
|
||||
|
||||
if (decodeStatus[tid] == Unblocking) {
|
||||
any_unblocking = true;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
// Decode will have activity if it's unblocking.
|
||||
if (any_unblocking) {
|
||||
if (_status == Inactive) {
|
||||
_status = Active;
|
||||
|
||||
DPRINTF(Activity, "Activating stage.\n");
|
||||
|
||||
cpu->activateStage(O3CPU::DecodeIdx);
|
||||
}
|
||||
} else {
|
||||
// If it's not unblocking, then decode will not have any internal
|
||||
// activity. Switch it to inactive.
|
||||
if (_status == Active) {
|
||||
_status = Inactive;
|
||||
DPRINTF(Activity, "Deactivating stage.\n");
|
||||
|
||||
cpu->deactivateStage(O3CPU::DecodeIdx);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
template <class Impl>
|
||||
void
|
||||
DefaultDecode<Impl>::sortInsts()
|
||||
{
|
||||
int insts_from_fetch = fromFetch->size;
|
||||
for (int i = 0; i < insts_from_fetch; ++i) {
|
||||
insts[fromFetch->insts[i]->threadNumber].push(fromFetch->insts[i]);
|
||||
}
|
||||
}
|
||||
|
||||
template<class Impl>
|
||||
void
|
||||
DefaultDecode<Impl>::readStallSignals(ThreadID tid)
|
||||
{
|
||||
if (fromRename->renameBlock[tid]) {
|
||||
stalls[tid].rename = true;
|
||||
}
|
||||
|
||||
if (fromRename->renameUnblock[tid]) {
|
||||
assert(stalls[tid].rename);
|
||||
stalls[tid].rename = false;
|
||||
}
|
||||
|
||||
if (fromIEW->iewBlock[tid]) {
|
||||
stalls[tid].iew = true;
|
||||
}
|
||||
|
||||
if (fromIEW->iewUnblock[tid]) {
|
||||
assert(stalls[tid].iew);
|
||||
stalls[tid].iew = false;
|
||||
}
|
||||
|
||||
if (fromCommit->commitBlock[tid]) {
|
||||
stalls[tid].commit = true;
|
||||
}
|
||||
|
||||
if (fromCommit->commitUnblock[tid]) {
|
||||
assert(stalls[tid].commit);
|
||||
stalls[tid].commit = false;
|
||||
}
|
||||
}
|
||||
|
||||
template <class Impl>
|
||||
bool
|
||||
DefaultDecode<Impl>::checkSignalsAndUpdate(ThreadID tid)
|
||||
{
|
||||
// Check if there's a squash signal, squash if there is.
|
||||
// Check stall signals, block if necessary.
|
||||
// If status was blocked
|
||||
// Check if stall conditions have passed
|
||||
// if so then go to unblocking
|
||||
// If status was Squashing
|
||||
// check if squashing is not high. Switch to running this cycle.
|
||||
|
||||
// Update the per thread stall statuses.
|
||||
readStallSignals(tid);
|
||||
|
||||
// Check squash signals from commit.
|
||||
if (fromCommit->commitInfo[tid].squash) {
|
||||
|
||||
DPRINTF(Decode, "[tid:%u]: Squashing instructions due to squash "
|
||||
"from commit.\n", tid);
|
||||
|
||||
squash(tid);
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
// Check ROB squash signals from commit.
|
||||
if (fromCommit->commitInfo[tid].robSquashing) {
|
||||
DPRINTF(Decode, "[tid:%u]: ROB is still squashing.\n", tid);
|
||||
|
||||
// Continue to squash.
|
||||
decodeStatus[tid] = Squashing;
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
if (checkStall(tid)) {
|
||||
return block(tid);
|
||||
}
|
||||
|
||||
if (decodeStatus[tid] == Blocked) {
|
||||
DPRINTF(Decode, "[tid:%u]: Done blocking, switching to unblocking.\n",
|
||||
tid);
|
||||
|
||||
decodeStatus[tid] = Unblocking;
|
||||
|
||||
unblock(tid);
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
if (decodeStatus[tid] == Squashing) {
|
||||
// Switch status to running if decode isn't being told to block or
|
||||
// squash this cycle.
|
||||
DPRINTF(Decode, "[tid:%u]: Done squashing, switching to running.\n",
|
||||
tid);
|
||||
|
||||
decodeStatus[tid] = Running;
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
// If we've reached this point, we have not gotten any signals that
|
||||
// cause decode to change its status. Decode remains the same as before.
|
||||
return false;
|
||||
}
|
||||
|
||||
template<class Impl>
|
||||
void
|
||||
DefaultDecode<Impl>::tick()
|
||||
{
|
||||
wroteToTimeBuffer = false;
|
||||
|
||||
bool status_change = false;
|
||||
|
||||
toRenameIndex = 0;
|
||||
|
||||
list<ThreadID>::iterator threads = activeThreads->begin();
|
||||
list<ThreadID>::iterator end = activeThreads->end();
|
||||
|
||||
sortInsts();
|
||||
|
||||
//Check stall and squash signals.
|
||||
while (threads != end) {
|
||||
ThreadID tid = *threads++;
|
||||
|
||||
DPRINTF(Decode,"Processing [tid:%i]\n",tid);
|
||||
status_change = checkSignalsAndUpdate(tid) || status_change;
|
||||
|
||||
decode(status_change, tid);
|
||||
}
|
||||
|
||||
if (status_change) {
|
||||
updateStatus();
|
||||
}
|
||||
|
||||
if (wroteToTimeBuffer) {
|
||||
DPRINTF(Activity, "Activity this cycle.\n");
|
||||
|
||||
cpu->activityThisCycle();
|
||||
}
|
||||
}
|
||||
|
||||
template<class Impl>
|
||||
void
|
||||
DefaultDecode<Impl>::decode(bool &status_change, ThreadID tid)
|
||||
{
|
||||
// If status is Running or idle,
|
||||
// call decodeInsts()
|
||||
// If status is Unblocking,
|
||||
// buffer any instructions coming from fetch
|
||||
// continue trying to empty skid buffer
|
||||
// check if stall conditions have passed
|
||||
|
||||
if (decodeStatus[tid] == Blocked) {
|
||||
++decodeBlockedCycles;
|
||||
} else if (decodeStatus[tid] == Squashing) {
|
||||
++decodeSquashCycles;
|
||||
}
|
||||
|
||||
// Decode should try to decode as many instructions as its bandwidth
|
||||
// will allow, as long as it is not currently blocked.
|
||||
if (decodeStatus[tid] == Running ||
|
||||
decodeStatus[tid] == Idle) {
|
||||
DPRINTF(Decode, "[tid:%u]: Not blocked, so attempting to run "
|
||||
"stage.\n",tid);
|
||||
|
||||
decodeInsts(tid);
|
||||
} else if (decodeStatus[tid] == Unblocking) {
|
||||
// Make sure that the skid buffer has something in it if the
|
||||
// status is unblocking.
|
||||
assert(!skidsEmpty());
|
||||
|
||||
// If the status was unblocking, then instructions from the skid
|
||||
// buffer were used. Remove those instructions and handle
|
||||
// the rest of unblocking.
|
||||
decodeInsts(tid);
|
||||
|
||||
if (fetchInstsValid()) {
|
||||
// Add the current inputs to the skid buffer so they can be
|
||||
// reprocessed when this stage unblocks.
|
||||
skidInsert(tid);
|
||||
}
|
||||
|
||||
status_change = unblock(tid) || status_change;
|
||||
}
|
||||
}
|
||||
|
||||
template <class Impl>
|
||||
void
|
||||
DefaultDecode<Impl>::decodeInsts(ThreadID tid)
|
||||
{
|
||||
// Instructions can come either from the skid buffer or the list of
|
||||
// instructions coming from fetch, depending on decode's status.
|
||||
int insts_available = decodeStatus[tid] == Unblocking ?
|
||||
skidBuffer[tid].size() : insts[tid].size();
|
||||
|
||||
if (insts_available == 0) {
|
||||
DPRINTF(Decode, "[tid:%u] Nothing to do, breaking out"
|
||||
" early.\n",tid);
|
||||
// Should I change the status to idle?
|
||||
++decodeIdleCycles;
|
||||
return;
|
||||
} else if (decodeStatus[tid] == Unblocking) {
|
||||
DPRINTF(Decode, "[tid:%u] Unblocking, removing insts from skid "
|
||||
"buffer.\n",tid);
|
||||
++decodeUnblockCycles;
|
||||
} else if (decodeStatus[tid] == Running) {
|
||||
++decodeRunCycles;
|
||||
}
|
||||
|
||||
DynInstPtr inst;
|
||||
|
||||
std::queue<DynInstPtr>
|
||||
&insts_to_decode = decodeStatus[tid] == Unblocking ?
|
||||
skidBuffer[tid] : insts[tid];
|
||||
|
||||
DPRINTF(Decode, "[tid:%u]: Sending instruction to rename.\n",tid);
|
||||
|
||||
while (insts_available > 0 && toRenameIndex < decodeWidth) {
|
||||
assert(!insts_to_decode.empty());
|
||||
|
||||
inst = insts_to_decode.front();
|
||||
|
||||
insts_to_decode.pop();
|
||||
|
||||
DPRINTF(Decode, "[tid:%u]: Processing instruction [sn:%lli] with "
|
||||
"PC %s\n", tid, inst->seqNum, inst->pcState());
|
||||
|
||||
if (inst->isSquashed()) {
|
||||
DPRINTF(Decode, "[tid:%u]: Instruction %i with PC %s is "
|
||||
"squashed, skipping.\n",
|
||||
tid, inst->seqNum, inst->pcState());
|
||||
|
||||
++decodeSquashedInsts;
|
||||
|
||||
--insts_available;
|
||||
|
||||
continue;
|
||||
}
|
||||
|
||||
// Also check if instructions have no source registers. Mark
|
||||
// them as ready to issue at any time. Not sure if this check
|
||||
// should exist here or at a later stage; however it doesn't matter
|
||||
// too much for function correctness.
|
||||
if (inst->numSrcRegs() == 0) {
|
||||
inst->setCanIssue();
|
||||
}
|
||||
|
||||
// This current instruction is valid, so add it into the decode
|
||||
// queue. The next instruction may not be valid, so check to
|
||||
// see if branches were predicted correctly.
|
||||
toRename->insts[toRenameIndex] = inst;
|
||||
|
||||
++(toRename->size);
|
||||
++toRenameIndex;
|
||||
++decodeDecodedInsts;
|
||||
--insts_available;
|
||||
|
||||
#if TRACING_ON
|
||||
inst->decodeTick = curTick() - inst->fetchTick;
|
||||
#endif
|
||||
|
||||
// Ensure that if it was predicted as a branch, it really is a
|
||||
// branch.
|
||||
if (inst->readPredTaken() && !inst->isControl()) {
|
||||
panic("Instruction predicted as a branch!");
|
||||
|
||||
++decodeControlMispred;
|
||||
|
||||
// Might want to set some sort of boolean and just do
|
||||
// a check at the end
|
||||
squash(inst, inst->threadNumber);
|
||||
|
||||
break;
|
||||
}
|
||||
|
||||
// Go ahead and compute any PC-relative branches.
|
||||
if (inst->isDirectCtrl() && inst->isUncondCtrl()) {
|
||||
++decodeBranchResolved;
|
||||
|
||||
if (!(inst->branchTarget() == inst->readPredTarg())) {
|
||||
++decodeBranchMispred;
|
||||
|
||||
// Might want to set some sort of boolean and just do
|
||||
// a check at the end
|
||||
squash(inst, inst->threadNumber);
|
||||
TheISA::PCState target = inst->branchTarget();
|
||||
|
||||
DPRINTF(Decode, "[sn:%i]: Updating predictions: PredPC: %s\n",
|
||||
inst->seqNum, target);
|
||||
//The micro pc after an instruction level branch should be 0
|
||||
inst->setPredTarg(target);
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// If we didn't process all instructions, then we will need to block
|
||||
// and put all those instructions into the skid buffer.
|
||||
if (!insts_to_decode.empty()) {
|
||||
block(tid);
|
||||
}
|
||||
|
||||
// Record that decode has written to the time buffer for activity
|
||||
// tracking.
|
||||
if (toRenameIndex) {
|
||||
wroteToTimeBuffer = true;
|
||||
}
|
||||
}
|
||||
Reference in New Issue
Block a user