Adding gem5 source to svn.
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1819 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
This commit is contained in:
friemel
591
simulators/gem5/src/cpu/legiontrace.cc
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591
simulators/gem5/src/cpu/legiontrace.cc
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@ -0,0 +1,591 @@
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/*
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* Copyright (c) 2001-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Steve Reinhardt
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* Lisa Hsu
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* Nathan Binkert
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* Steve Raasch
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*/
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#include "config/the_isa.hh"
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#if THE_ISA != SPARC_ISA
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#error Legion tracing only works with SPARC simulations!
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#endif
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#include <sys/ipc.h>
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#include <sys/shm.h>
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#include <cstdio>
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#include <iomanip>
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#include "arch/sparc/decoder.hh"
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#include "arch/sparc/registers.hh"
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#include "arch/sparc/utility.hh"
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#include "arch/tlb.hh"
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#include "base/socket.hh"
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#include "cpu/base.hh"
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#include "cpu/legiontrace.hh"
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#include "cpu/static_inst.hh"
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#include "cpu/thread_context.hh"
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#include "sim/full_system.hh"
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#include "sim/system.hh"
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//XXX This is temporary
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#include "cpu/m5legion_interface.h"
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using namespace std;
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using namespace TheISA;
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static int diffcount = 0;
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static bool wasMicro = false;
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namespace Trace {
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SharedData *shared_data = NULL;
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void
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setupSharedData()
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{
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int shmfd = shmget('M' << 24 | getuid(), sizeof(SharedData), 0777);
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if (shmfd < 0)
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fatal("Couldn't get shared memory fd. Is Legion running?");
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shared_data = (SharedData*)shmat(shmfd, NULL, SHM_RND);
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if (shared_data == (SharedData*)-1)
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fatal("Couldn't allocate shared memory");
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if (shared_data->flags != OWN_M5)
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fatal("Shared memory has invalid owner");
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if (shared_data->version != VERSION)
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fatal("Shared Data is wrong version! M5: %d Legion: %d", VERSION,
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shared_data->version);
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// step legion forward one cycle so we can get register values
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shared_data->flags = OWN_LEGION;
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}
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////////////////////////////////////////////////////////////////////////
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//
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// Utility methods for pretty printing a report about a difference
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//
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inline char * genCenteredLabel(int length, char * buffer, const char * label)
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{
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int labelLength = strlen(label);
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assert(labelLength <= length);
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int leftPad = (length - labelLength) / 2;
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int rightPad = length - leftPad - labelLength;
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char format[64];
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sprintf(format, "%%%ds%%s%%%ds", leftPad, rightPad);
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sprintf(buffer, format, "", label, "");
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return buffer;
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}
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inline void printRegPair(ostream & os, char const * title, uint64_t a, uint64_t b)
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{
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ccprintf(os, " %16s | %#018x %s %#-018x \n",
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title, a, (a == b) ? "|" : "X", b);
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}
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inline void printColumnLabels(ostream & os)
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{
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static char * regLabel = genCenteredLabel(16, new char[17], "Register");
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static char * m5Label = genCenteredLabel(18, new char[18], "M5");
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static char * legionLabel = genCenteredLabel(18, new char[18], "Legion");
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ccprintf(os, " %s | %s | %s \n", regLabel, m5Label, legionLabel);
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ccprintf(os, "--------------------+-----------------------+-----------------------\n");
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}
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inline void printSectionHeader(ostream & os, const char * name)
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{
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char sectionString[70];
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genCenteredLabel(69, sectionString, name);
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ccprintf(os, "====================================================================\n");
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ccprintf(os, "%69s\n", sectionString);
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ccprintf(os, "====================================================================\n");
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}
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inline void printLevelHeader(ostream & os, int level)
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{
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char sectionString[70];
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char levelName[70];
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sprintf(levelName, "Trap stack level %d", level);
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genCenteredLabel(69, sectionString, levelName);
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ccprintf(os, "====================================================================\n");
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ccprintf(os, "%69s\n", sectionString);
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ccprintf(os, "====================================================================\n");
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}
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void
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Trace::LegionTraceRecord::dump()
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{
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ostream &outs = Trace::output();
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// Compare
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bool compared = false;
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bool diffPC = false;
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bool diffCC = false;
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bool diffInst = false;
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bool diffIntRegs = false;
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bool diffFpRegs = false;
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bool diffTpc = false;
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bool diffTnpc = false;
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bool diffTstate = false;
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bool diffTt = false;
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bool diffTba M5_VAR_USED = false;
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bool diffHpstate = false;
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bool diffHtstate = false;
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bool diffHtba = false;
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bool diffPstate = false;
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bool diffY = false;
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bool diffFsr = false;
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bool diffCcr = false;
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bool diffTl = false;
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bool diffGl = false;
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bool diffAsi = false;
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bool diffPil = false;
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bool diffCwp = false;
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bool diffCansave = false;
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bool diffCanrestore = false;
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bool diffOtherwin = false;
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bool diffCleanwin = false;
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bool diffTlb = false;
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Addr m5Pc, lgnPc;
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if (!shared_data)
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setupSharedData();
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// We took a trap on a micro-op...
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if (wasMicro && !staticInst->isMicroop())
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{
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// let's skip comparing this tick
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while (!compared)
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if (shared_data->flags == OWN_M5) {
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shared_data->flags = OWN_LEGION;
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compared = true;
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}
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compared = false;
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wasMicro = false;
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}
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if (staticInst->isLastMicroop())
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wasMicro = false;
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else if (staticInst->isMicroop())
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wasMicro = true;
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if(!staticInst->isMicroop() || staticInst->isLastMicroop()) {
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while (!compared) {
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if (shared_data->flags == OWN_M5) {
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m5Pc = pc.instAddr() & SparcISA::PAddrImplMask;
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if (bits(shared_data->pstate,3,3)) {
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m5Pc &= mask(32);
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}
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lgnPc = shared_data->pc & SparcISA::PAddrImplMask;
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if (lgnPc != m5Pc)
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diffPC = true;
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if (shared_data->cycle_count !=
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thread->getCpuPtr()->instCount())
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diffCC = true;
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if (shared_data->instruction !=
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(SparcISA::MachInst)staticInst->machInst) {
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diffInst = true;
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}
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// assume we have %g0 working correctly
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for (int i = 1; i < TheISA::NumIntArchRegs; i++) {
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if (thread->readIntReg(i) != shared_data->intregs[i]) {
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diffIntRegs = true;
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}
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}
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for (int i = 0; i < TheISA::NumFloatRegs/2; i++) {
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if (thread->readFloatRegBits(i*2) !=
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shared_data->fpregs[i]) {
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diffFpRegs = true;
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}
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}
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uint64_t oldTl =
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thread->readMiscRegNoEffect(MISCREG_TL);
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if (oldTl != shared_data->tl)
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diffTl = true;
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for (int i = 1; i <= MaxTL; i++) {
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thread->setMiscRegNoEffect(MISCREG_TL, i);
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if (thread->readMiscRegNoEffect(MISCREG_TPC) !=
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shared_data->tpc[i-1])
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diffTpc = true;
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if (thread->readMiscRegNoEffect(MISCREG_TNPC) !=
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shared_data->tnpc[i-1])
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diffTnpc = true;
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if (thread->readMiscRegNoEffect(MISCREG_TSTATE) !=
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shared_data->tstate[i-1])
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diffTstate = true;
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if (thread->readMiscRegNoEffect(MISCREG_TT) !=
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shared_data->tt[i-1])
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diffTt = true;
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if (thread->readMiscRegNoEffect(MISCREG_HTSTATE) !=
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shared_data->htstate[i-1])
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diffHtstate = true;
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}
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thread->setMiscRegNoEffect(MISCREG_TL, oldTl);
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if(shared_data->tba != thread->readMiscRegNoEffect(MISCREG_TBA))
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diffTba = true;
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//When the hpstate register is read by an instruction,
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//legion has bit 11 set. When it's in storage, it doesn't.
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//Since we don't directly support seperate interpretations
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//of the registers like that, the bit is always set to 1 and
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//we just don't compare it. It's not supposed to matter
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//anyway.
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if((shared_data->hpstate | (1 << 11)) !=
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thread->readMiscRegNoEffect(MISCREG_HPSTATE))
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diffHpstate = true;
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if(shared_data->htba !=
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thread->readMiscRegNoEffect(MISCREG_HTBA))
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diffHtba = true;
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if(shared_data->pstate !=
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thread->readMiscRegNoEffect(MISCREG_PSTATE))
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diffPstate = true;
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//if(shared_data->y !=
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// thread->readMiscRegNoEffect(MISCREG_Y))
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if(shared_data->y !=
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thread->readIntReg(NumIntArchRegs + 1))
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diffY = true;
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if(shared_data->fsr !=
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thread->readMiscRegNoEffect(MISCREG_FSR)) {
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diffFsr = true;
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if (mbits(shared_data->fsr, 63,10) ==
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mbits(thread->readMiscRegNoEffect(MISCREG_FSR),
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63,10)) {
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thread->setMiscRegNoEffect(MISCREG_FSR,
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shared_data->fsr);
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diffFsr = false;
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}
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}
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//if(shared_data->ccr !=
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// thread->readMiscRegNoEffect(MISCREG_CCR))
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if(shared_data->ccr !=
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thread->readIntReg(NumIntArchRegs + 2))
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diffCcr = true;
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if(shared_data->gl !=
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thread->readMiscRegNoEffect(MISCREG_GL))
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diffGl = true;
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if(shared_data->asi !=
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thread->readMiscRegNoEffect(MISCREG_ASI))
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diffAsi = true;
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if(shared_data->pil !=
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thread->readMiscRegNoEffect(MISCREG_PIL))
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diffPil = true;
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if(shared_data->cwp !=
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thread->readMiscRegNoEffect(MISCREG_CWP))
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diffCwp = true;
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//if(shared_data->cansave !=
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// thread->readMiscRegNoEffect(MISCREG_CANSAVE))
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if(shared_data->cansave !=
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thread->readIntReg(NumIntArchRegs + 3))
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diffCansave = true;
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//if(shared_data->canrestore !=
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// thread->readMiscRegNoEffect(MISCREG_CANRESTORE))
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if(shared_data->canrestore !=
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thread->readIntReg(NumIntArchRegs + 4))
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diffCanrestore = true;
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//if(shared_data->otherwin !=
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// thread->readMiscRegNoEffect(MISCREG_OTHERWIN))
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if(shared_data->otherwin !=
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thread->readIntReg(NumIntArchRegs + 6))
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diffOtherwin = true;
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//if(shared_data->cleanwin !=
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// thread->readMiscRegNoEffect(MISCREG_CLEANWIN))
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if(shared_data->cleanwin !=
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thread->readIntReg(NumIntArchRegs + 5))
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diffCleanwin = true;
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for (int i = 0; i < 64; i++) {
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if (shared_data->itb[i] !=
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thread->getITBPtr()->TteRead(i))
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diffTlb = true;
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if (shared_data->dtb[i] !=
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thread->getDTBPtr()->TteRead(i))
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diffTlb = true;
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}
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if (diffPC || diffCC || diffInst ||
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diffIntRegs || diffFpRegs ||
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diffTpc || diffTnpc || diffTstate || diffTt ||
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diffHpstate || diffHtstate || diffHtba ||
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diffPstate || diffY || diffCcr || diffTl || diffFsr ||
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diffGl || diffAsi || diffPil || diffCwp ||
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diffCansave || diffCanrestore ||
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diffOtherwin || diffCleanwin || diffTlb) {
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outs << "Differences found between M5 and Legion:";
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if (diffPC)
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outs << " [PC]";
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if (diffCC)
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outs << " [CC]";
|
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if (diffInst)
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outs << " [Instruction]";
|
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if (diffIntRegs)
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outs << " [IntRegs]";
|
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if (diffFpRegs)
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outs << " [FpRegs]";
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if (diffTpc)
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outs << " [Tpc]";
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if (diffTnpc)
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outs << " [Tnpc]";
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if (diffTstate)
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outs << " [Tstate]";
|
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if (diffTt)
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outs << " [Tt]";
|
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if (diffHpstate)
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outs << " [Hpstate]";
|
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if (diffHtstate)
|
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outs << " [Htstate]";
|
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if (diffHtba)
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outs << " [Htba]";
|
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if (diffPstate)
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outs << " [Pstate]";
|
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if (diffY)
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outs << " [Y]";
|
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if (diffFsr)
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outs << " [FSR]";
|
||||
if (diffCcr)
|
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outs << " [Ccr]";
|
||||
if (diffTl)
|
||||
outs << " [Tl]";
|
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if (diffGl)
|
||||
outs << " [Gl]";
|
||||
if (diffAsi)
|
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outs << " [Asi]";
|
||||
if (diffPil)
|
||||
outs << " [Pil]";
|
||||
if (diffCwp)
|
||||
outs << " [Cwp]";
|
||||
if (diffCansave)
|
||||
outs << " [Cansave]";
|
||||
if (diffCanrestore)
|
||||
outs << " [Canrestore]";
|
||||
if (diffOtherwin)
|
||||
outs << " [Otherwin]";
|
||||
if (diffCleanwin)
|
||||
outs << " [Cleanwin]";
|
||||
if (diffTlb)
|
||||
outs << " [Tlb]";
|
||||
outs << endl << endl;
|
||||
|
||||
outs << right << setfill(' ') << setw(15)
|
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<< "M5 PC: " << "0x"<< setw(16) << setfill('0')
|
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<< hex << m5Pc << endl;
|
||||
outs << setfill(' ') << setw(15)
|
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<< "Legion PC: " << "0x"
|
||||
<< setw(16) << setfill('0') << hex
|
||||
<< lgnPc << endl << endl;
|
||||
|
||||
outs << right << setfill(' ') << setw(15)
|
||||
<< "M5 CC: " << "0x"
|
||||
<< setw(16) << setfill('0') << hex
|
||||
<< thread->getCpuPtr()->instCount() << endl;
|
||||
outs << setfill(' ') << setw(15)
|
||||
<< "Legion CC: " << "0x"
|
||||
<< setw(16) << setfill('0') << hex
|
||||
<< shared_data->cycle_count << endl << endl;
|
||||
|
||||
outs << setfill(' ') << setw(15)
|
||||
<< "M5 Inst: " << "0x"
|
||||
<< setw(8) << setfill('0') << hex
|
||||
<< staticInst->machInst
|
||||
<< staticInst->disassemble(m5Pc, debugSymbolTable)
|
||||
<< endl;
|
||||
|
||||
TheISA::Decoder *decoder = thread->getDecoderPtr();
|
||||
decoder->setTC(thread);
|
||||
decoder->moreBytes(m5Pc, m5Pc, shared_data->instruction);
|
||||
|
||||
assert(decoder->instReady());
|
||||
|
||||
PCState tempPC = pc;
|
||||
StaticInstPtr legionInst = decoder->decode(tempPC);
|
||||
outs << setfill(' ') << setw(15)
|
||||
<< " Legion Inst: "
|
||||
<< "0x" << setw(8) << setfill('0') << hex
|
||||
<< shared_data->instruction
|
||||
<< legionInst->disassemble(lgnPc, debugSymbolTable)
|
||||
<< endl << endl;
|
||||
|
||||
printSectionHeader(outs, "General State");
|
||||
printColumnLabels(outs);
|
||||
printRegPair(outs, "HPstate",
|
||||
thread->readMiscRegNoEffect(MISCREG_HPSTATE),
|
||||
shared_data->hpstate | (1 << 11));
|
||||
printRegPair(outs, "Htba",
|
||||
thread->readMiscRegNoEffect(MISCREG_HTBA),
|
||||
shared_data->htba);
|
||||
printRegPair(outs, "Pstate",
|
||||
thread->readMiscRegNoEffect(MISCREG_PSTATE),
|
||||
shared_data->pstate);
|
||||
printRegPair(outs, "Y",
|
||||
//thread->readMiscRegNoEffect(MISCREG_Y),
|
||||
thread->readIntReg(NumIntArchRegs + 1),
|
||||
shared_data->y);
|
||||
printRegPair(outs, "FSR",
|
||||
thread->readMiscRegNoEffect(MISCREG_FSR),
|
||||
shared_data->fsr);
|
||||
printRegPair(outs, "Ccr",
|
||||
//thread->readMiscRegNoEffect(MISCREG_CCR),
|
||||
thread->readIntReg(NumIntArchRegs + 2),
|
||||
shared_data->ccr);
|
||||
printRegPair(outs, "Tl",
|
||||
thread->readMiscRegNoEffect(MISCREG_TL),
|
||||
shared_data->tl);
|
||||
printRegPair(outs, "Gl",
|
||||
thread->readMiscRegNoEffect(MISCREG_GL),
|
||||
shared_data->gl);
|
||||
printRegPair(outs, "Asi",
|
||||
thread->readMiscRegNoEffect(MISCREG_ASI),
|
||||
shared_data->asi);
|
||||
printRegPair(outs, "Pil",
|
||||
thread->readMiscRegNoEffect(MISCREG_PIL),
|
||||
shared_data->pil);
|
||||
printRegPair(outs, "Cwp",
|
||||
thread->readMiscRegNoEffect(MISCREG_CWP),
|
||||
shared_data->cwp);
|
||||
printRegPair(outs, "Cansave",
|
||||
//thread->readMiscRegNoEffect(MISCREG_CANSAVE),
|
||||
thread->readIntReg(NumIntArchRegs + 3),
|
||||
shared_data->cansave);
|
||||
printRegPair(outs, "Canrestore",
|
||||
//thread->readMiscRegNoEffect(MISCREG_CANRESTORE),
|
||||
thread->readIntReg(NumIntArchRegs + 4),
|
||||
shared_data->canrestore);
|
||||
printRegPair(outs, "Otherwin",
|
||||
//thread->readMiscRegNoEffect(MISCREG_OTHERWIN),
|
||||
thread->readIntReg(NumIntArchRegs + 6),
|
||||
shared_data->otherwin);
|
||||
printRegPair(outs, "Cleanwin",
|
||||
//thread->readMiscRegNoEffect(MISCREG_CLEANWIN),
|
||||
thread->readIntReg(NumIntArchRegs + 5),
|
||||
shared_data->cleanwin);
|
||||
outs << endl;
|
||||
for (int i = 1; i <= MaxTL; i++) {
|
||||
printLevelHeader(outs, i);
|
||||
printColumnLabels(outs);
|
||||
thread->setMiscRegNoEffect(MISCREG_TL, i);
|
||||
printRegPair(outs, "Tpc",
|
||||
thread->readMiscRegNoEffect(MISCREG_TPC),
|
||||
shared_data->tpc[i-1]);
|
||||
printRegPair(outs, "Tnpc",
|
||||
thread->readMiscRegNoEffect(MISCREG_TNPC),
|
||||
shared_data->tnpc[i-1]);
|
||||
printRegPair(outs, "Tstate",
|
||||
thread->readMiscRegNoEffect(MISCREG_TSTATE),
|
||||
shared_data->tstate[i-1]);
|
||||
printRegPair(outs, "Tt",
|
||||
thread->readMiscRegNoEffect(MISCREG_TT),
|
||||
shared_data->tt[i-1]);
|
||||
printRegPair(outs, "Htstate",
|
||||
thread->readMiscRegNoEffect(MISCREG_HTSTATE),
|
||||
shared_data->htstate[i-1]);
|
||||
}
|
||||
thread->setMiscRegNoEffect(MISCREG_TL, oldTl);
|
||||
outs << endl;
|
||||
|
||||
printSectionHeader(outs, "General Purpose Registers");
|
||||
static const char * regtypes[4] =
|
||||
{"%g", "%o", "%l", "%i"};
|
||||
for(int y = 0; y < 4; y++) {
|
||||
for(int x = 0; x < 8; x++) {
|
||||
char label[8];
|
||||
sprintf(label, "%s%d", regtypes[y], x);
|
||||
printRegPair(outs, label,
|
||||
thread->readIntReg(y*8+x),
|
||||
shared_data->intregs[y*8+x]);
|
||||
}
|
||||
}
|
||||
if (diffFpRegs) {
|
||||
for (int x = 0; x < 32; x++) {
|
||||
char label[8];
|
||||
sprintf(label, "%%f%d", x);
|
||||
printRegPair(outs, label,
|
||||
thread->readFloatRegBits(x*2),
|
||||
shared_data->fpregs[x]);
|
||||
}
|
||||
}
|
||||
if (diffTlb) {
|
||||
printColumnLabels(outs);
|
||||
char label[8];
|
||||
for (int x = 0; x < 64; x++) {
|
||||
if (shared_data->itb[x] !=
|
||||
ULL(0xFFFFFFFFFFFFFFFF) ||
|
||||
thread->getITBPtr()->TteRead(x) !=
|
||||
ULL(0xFFFFFFFFFFFFFFFF)) {
|
||||
sprintf(label, "I-TLB:%02d", x);
|
||||
printRegPair(outs, label,
|
||||
thread->getITBPtr()->TteRead(x),
|
||||
shared_data->itb[x]);
|
||||
}
|
||||
}
|
||||
for (int x = 0; x < 64; x++) {
|
||||
if (shared_data->dtb[x] !=
|
||||
ULL(0xFFFFFFFFFFFFFFFF) ||
|
||||
thread->getDTBPtr()->TteRead(x) !=
|
||||
ULL(0xFFFFFFFFFFFFFFFF)) {
|
||||
sprintf(label, "D-TLB:%02d", x);
|
||||
printRegPair(outs, label,
|
||||
thread->getDTBPtr()->TteRead(x),
|
||||
shared_data->dtb[x]);
|
||||
}
|
||||
}
|
||||
thread->getITBPtr()->dumpAll();
|
||||
thread->getDTBPtr()->dumpAll();
|
||||
}
|
||||
|
||||
diffcount++;
|
||||
if (diffcount > 3)
|
||||
fatal("Differences found between Legion and M5\n");
|
||||
} else
|
||||
diffcount = 0;
|
||||
|
||||
compared = true;
|
||||
shared_data->flags = OWN_LEGION;
|
||||
}
|
||||
} // while
|
||||
} // if not microop
|
||||
}
|
||||
|
||||
} // namespace Trace
|
||||
|
||||
////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// ExeTracer Simulation Object
|
||||
//
|
||||
Trace::LegionTrace *
|
||||
LegionTraceParams::create()
|
||||
{
|
||||
if (!FullSystem)
|
||||
panic("Legion tracing only works in full system!");
|
||||
return new Trace::LegionTrace(this);
|
||||
};
|
||||
Reference in New Issue
Block a user