Adding gem5 source to svn.
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1819 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
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friemel
297
simulators/gem5/src/cpu/inorder/thread_context.hh
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297
simulators/gem5/src/cpu/inorder/thread_context.hh
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/*
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* Copyright (c) 2007 MIPS Technologies, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Korey Sewell
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*
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*/
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#ifndef __CPU_INORDER_THREAD_CONTEXT_HH__
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#define __CPU_INORDER_THREAD_CONTEXT_HH__
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#include "config/the_isa.hh"
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#include "cpu/inorder/cpu.hh"
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#include "cpu/inorder/thread_state.hh"
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#include "cpu/exetrace.hh"
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#include "cpu/thread_context.hh"
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#include "arch/kernel_stats.hh"
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class EndQuiesceEvent;
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class CheckerCPU;
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namespace Kernel {
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class Statistics;
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};
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/**
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* Derived ThreadContext class for use with the InOrderCPU. It
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* provides the interface for any external objects to access a
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* single thread's state and some general CPU state. Any time
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* external objects try to update state through this interface,
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* the CPU will create an event to squash all in-flight
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* instructions in order to ensure state is maintained correctly.
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* It must be defined specifically for the InOrderCPU because
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* not all architectural state is located within the O3ThreadState
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* (such as the commit PC, and registers), and specific actions
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* must be taken when using this interface (such as squashing all
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* in-flight instructions when doing a write to this interface).
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*/
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class InOrderThreadContext : public ThreadContext
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{
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public:
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InOrderThreadContext() { }
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/** Pointer to the CPU. */
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InOrderCPU *cpu;
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/** Pointer to the thread state that this TC corrseponds to. */
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InOrderThreadState *thread;
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/** Returns a pointer to the ITB. */
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/** @TODO: PERF: Should we bind this to a pointer in constructor? */
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TheISA::TLB *getITBPtr() { return cpu->getITBPtr(); }
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/** Returns a pointer to the DTB. */
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/** @TODO: PERF: Should we bind this to a pointer in constructor? */
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TheISA::TLB *getDTBPtr() { return cpu->getDTBPtr(); }
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/** Currently InOrder model does not support CheckerCPU, this is
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* merely here for supporting compilation of gem5 with the Checker
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* as a runtime option
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*/
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CheckerCPU *getCheckerCpuPtr() { return NULL; }
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TheISA::Decoder *
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getDecoderPtr()
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{
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return cpu->getDecoderPtr(thread->contextId());
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}
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System *getSystemPtr() { return cpu->system; }
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/** Returns a pointer to this CPU. */
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BaseCPU *getCpuPtr() { return cpu; }
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/** Returns a pointer to this CPU. */
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std::string getCpuName() { return cpu->name(); }
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/** Reads this CPU's ID. */
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int cpuId() { return cpu->cpuId(); }
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int contextId() { return thread->contextId(); }
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void setContextId(int id) { thread->setContextId(id); }
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/** Returns this thread's ID number. */
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int threadId() { return thread->threadId(); }
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void setThreadId(int id) { return thread->setThreadId(id); }
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uint64_t readMicroPC()
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{ return 0; }
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void setMicroPC(uint64_t val) { };
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uint64_t readNextMicroPC()
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{ return 0; }
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void setNextMicroPC(uint64_t val) { };
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/** Returns a pointer to this thread's kernel statistics. */
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TheISA::Kernel::Statistics *getKernelStats()
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{ return thread->kernelStats; }
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PortProxy &getPhysProxy() { return thread->getPhysProxy(); }
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FSTranslatingPortProxy &getVirtProxy();
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void initMemProxies(ThreadContext *tc)
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{ thread->initMemProxies(tc); }
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/** Dumps the function profiling information.
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* @todo: Implement.
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*/
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void dumpFuncProfile();
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/** Reads the last tick that this thread was activated on. */
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Tick readLastActivate();
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/** Reads the last tick that this thread was suspended on. */
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Tick readLastSuspend();
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/** Clears the function profiling information. */
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void profileClear();
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/** Samples the function profiling information. */
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void profileSample();
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/** Returns pointer to the quiesce event. */
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EndQuiesceEvent *getQuiesceEvent()
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{
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return this->thread->quiesceEvent;
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}
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SETranslatingPortProxy &getMemProxy() { return thread->getMemProxy(); }
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/** Returns a pointer to this thread's process. */
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Process *getProcessPtr() { return thread->getProcessPtr(); }
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/** Returns this thread's status. */
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Status status() const { return thread->status(); }
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/** Sets this thread's status. */
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void setStatus(Status new_status)
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{ thread->setStatus(new_status); }
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/** Set the status to Active. Optional delay indicates number of
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* cycles to wait before beginning execution. */
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void activate(int delay = 1);
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/** Set the status to Suspended. */
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void suspend(int delay = 0);
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/** Set the status to Halted. */
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void halt(int delay = 0);
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/** Takes over execution of a thread from another CPU. */
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void takeOverFrom(ThreadContext *old_context);
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/** Registers statistics associated with this TC. */
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void regStats(const std::string &name);
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/** Serializes state. */
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void serialize(std::ostream &os);
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/** Unserializes state. */
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void unserialize(Checkpoint *cp, const std::string §ion);
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/** Returns this thread's ID number. */
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int getThreadNum() { return thread->threadId(); }
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/** Copies the architectural registers from another TC into this TC. */
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void copyArchRegs(ThreadContext *src_tc);
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/** Resets all architectural registers to 0. */
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void clearArchRegs();
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/** Reads an integer register. */
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uint64_t readIntReg(int reg_idx);
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FloatReg readFloatReg(int reg_idx);
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FloatRegBits readFloatRegBits(int reg_idx);
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uint64_t readRegOtherThread(int misc_reg, ThreadID tid);
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/** Sets an integer register to a value. */
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void setIntReg(int reg_idx, uint64_t val);
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void setFloatReg(int reg_idx, FloatReg val);
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void setFloatRegBits(int reg_idx, FloatRegBits val);
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void setRegOtherThread(int misc_reg,
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const MiscReg &val,
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ThreadID tid);
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/** Reads this thread's PC. */
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TheISA::PCState pcState()
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{ return cpu->pcState(thread->threadId()); }
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/** Sets this thread's PC. */
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void pcState(const TheISA::PCState &val)
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{ cpu->pcState(val, thread->threadId()); }
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/** Needs to be implemented for future CheckerCPU support.
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* See O3CPU for examples on how to integrate Checker.
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*/
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void pcStateNoRecord(const TheISA::PCState &val)
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{}
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Addr instAddr()
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{ return cpu->instAddr(thread->threadId()); }
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Addr nextInstAddr()
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{ return cpu->nextInstAddr(thread->threadId()); }
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MicroPC microPC()
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{ return cpu->microPC(thread->threadId()); }
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/** Reads a miscellaneous register. */
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MiscReg readMiscRegNoEffect(int misc_reg)
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{ return cpu->readMiscRegNoEffect(misc_reg, thread->threadId()); }
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/** Reads a misc. register, including any side-effects the
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* read might have as defined by the architecture. */
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MiscReg readMiscReg(int misc_reg)
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{ return cpu->readMiscReg(misc_reg, thread->threadId()); }
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/** Sets a misc. register. */
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void setMiscRegNoEffect(int misc_reg, const MiscReg &val);
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/** Sets a misc. register, including any side-effects the
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* write might have as defined by the architecture. */
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void setMiscReg(int misc_reg, const MiscReg &val);
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int flattenIntIndex(int reg)
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{ return cpu->isa[thread->threadId()].flattenIntIndex(reg); }
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int flattenFloatIndex(int reg)
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{ return cpu->isa[thread->threadId()].flattenFloatIndex(reg); }
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void activateContext(int delay)
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{ cpu->activateContext(thread->threadId(), delay); }
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void deallocateContext()
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{ cpu->deallocateContext(thread->threadId()); }
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/** Returns the number of consecutive store conditional failures. */
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// @todo: Figure out where these store cond failures should go.
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unsigned readStCondFailures()
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{ return thread->storeCondFailures; }
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/** Sets the number of consecutive store conditional failures. */
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void setStCondFailures(unsigned sc_failures)
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{ thread->storeCondFailures = sc_failures; }
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// Only really makes sense for old CPU model. Lots of code
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// outside the CPU still checks this function, so it will
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// always return false to keep everything working.
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/** Checks if the thread is misspeculating. Because it is
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* very difficult to determine if the thread is
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* misspeculating, this is set as false. */
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bool misspeculating() { return false; }
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/** Executes a syscall in SE mode. */
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void syscall(int64_t callnum)
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{ return cpu->syscall(callnum, thread->threadId()); }
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/** Reads the funcExeInst counter. */
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Counter readFuncExeInst() { return thread->funcExeInst; }
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void changeRegFileContext(unsigned param,
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unsigned val)
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{ panic("Not supported!"); }
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};
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#endif
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