Adding gem5 source to svn.
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1819 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
This commit is contained in:
friemel
472
simulators/gem5/src/cpu/inorder/resource_pool.cc
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472
simulators/gem5/src/cpu/inorder/resource_pool.cc
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/*
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* Copyright (c) 2012 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2007 MIPS Technologies, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Korey Sewell
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*
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*/
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#include <list>
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#include <vector>
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#include "cpu/inorder/resources/resource_list.hh"
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#include "cpu/inorder/resource_pool.hh"
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#include "debug/Resource.hh"
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using namespace std;
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using namespace ThePipeline;
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ResourcePool::ResourcePool(InOrderCPU *_cpu, ThePipeline::Params *params)
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: cpu(_cpu), instUnit(NULL), dataUnit(NULL)
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{
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//@todo: use this function to instantiate the resources in resource pool.
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//This will help in the auto-generation of this pipeline model.
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//ThePipeline::addResources(resources, memObjects);
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int stage_width = cpu->stageWidth;
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// Declare Resource Objects
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// name - id - bandwidth - latency - CPU - Parameters
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// --------------------------------------------------
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resources.push_back(new FetchSeqUnit("fetch_seq_unit", FetchSeq,
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stage_width * 2, 0, _cpu, params));
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// Keep track of the instruction fetch unit so we can easily
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// provide a pointer to it in the CPU.
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instUnit = new FetchUnit("icache_port", ICache,
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stage_width * 2 + MaxThreads, 0, _cpu,
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params);
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resources.push_back(instUnit);
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resources.push_back(new DecodeUnit("decode_unit", Decode,
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stage_width, 0, _cpu, params));
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resources.push_back(new BranchPredictor("branch_predictor", BPred,
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stage_width, 0, _cpu, params));
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resources.push_back(new InstBuffer("fetch_buffer_t0", FetchBuff, 4,
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0, _cpu, params));
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resources.push_back(new UseDefUnit("regfile_manager", RegManager,
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stage_width * 3, 0, _cpu,
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params));
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resources.push_back(new AGENUnit("agen_unit", AGEN,
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stage_width, 0, _cpu, params));
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resources.push_back(new ExecutionUnit("execution_unit", ExecUnit,
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stage_width, 0, _cpu, params));
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resources.push_back(new MultDivUnit("mult_div_unit", MDU,
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stage_width * 2,
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0,
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_cpu,
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params));
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// Keep track of the data load/store unit so we can easily provide
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// a pointer to it in the CPU.
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dataUnit = new CacheUnit("dcache_port", DCache,
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stage_width * 2 + MaxThreads, 0, _cpu,
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params);
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resources.push_back(dataUnit);
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gradObjects.push_back(BPred);
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resources.push_back(new GraduationUnit("graduation_unit", Grad,
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stage_width, 0, _cpu,
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params));
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resources.push_back(new InstBuffer("fetch_buffer_t1", FetchBuff2, 4,
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0, _cpu, params));
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}
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ResourcePool::~ResourcePool()
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{
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cout << "Deleting resources ..." << endl;
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for (int i=0; i < resources.size(); i++) {
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DPRINTF(Resource, "Deleting resource: %s.\n", resources[i]->name());
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delete resources[i];
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}
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}
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void
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ResourcePool::init()
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{
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for (int i=0; i < resources.size(); i++) {
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DPRINTF(Resource, "Initializing resource: %s.\n",
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resources[i]->name());
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resources[i]->init();
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}
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}
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string
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ResourcePool::name()
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{
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return cpu->name() + ".ResourcePool";
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}
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void
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ResourcePool::print()
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{
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for (int i=0; i < resources.size(); i++) {
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DPRINTF(InOrderDynInst, "Res:%i %s\n",
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i, resources[i]->name());
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}
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}
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void
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ResourcePool::regStats()
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{
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DPRINTF(Resource, "Registering Stats Throughout Resource Pool.\n");
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int num_resources = resources.size();
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for (int idx = 0; idx < num_resources; idx++) {
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resources[idx]->regStats();
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}
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}
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unsigned
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ResourcePool::getResIdx(const ThePipeline::ResourceId &res_id)
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{
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int num_resources = resources.size();
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for (int idx = 0; idx < num_resources; idx++) {
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if (resources[idx]->getId() == res_id)
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return idx;
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}
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// todo: change return value to int and return a -1 here
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// maybe even have enumerated type
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// panic for now...
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panic("Can't find resource idx for: %i\n", res_id);
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return 0;
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}
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ResReqPtr
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ResourcePool::request(int res_idx, DynInstPtr inst)
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{
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//Make Sure This is a valid resource ID
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assert(res_idx >= 0 && res_idx < resources.size());
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return resources[res_idx]->request(inst);
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}
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void
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ResourcePool::squash(DynInstPtr inst, int res_idx, InstSeqNum done_seq_num,
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ThreadID tid)
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{
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resources[res_idx]->squash(inst, ThePipeline::NumStages-1, done_seq_num,
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tid);
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}
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void
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ResourcePool::trap(Fault fault, ThreadID tid, DynInstPtr inst)
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{
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DPRINTF(Resource, "[tid:%i] Broadcasting Trap to all "
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"resources.\n", tid);
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int num_resources = resources.size();
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for (int idx = 0; idx < num_resources; idx++)
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resources[idx]->trap(fault, tid, inst);
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}
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int
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ResourcePool::slotsAvail(int res_idx)
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{
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return resources[res_idx]->slotsAvail();
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}
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int
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ResourcePool::slotsInUse(int res_idx)
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{
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return resources[res_idx]->slotsInUse();
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}
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//@todo: split this function and call this version schedulePoolEvent
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// and use this scheduleEvent for scheduling a specific event on
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// a resource
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//@todo: For arguments that arent being used in a ResPoolEvent, a dummyParam
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// or some typedef can be used to signify what's important info
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// to the event construction
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void
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ResourcePool::scheduleEvent(InOrderCPU::CPUEventType e_type, DynInstPtr inst,
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int delay, int res_idx, ThreadID tid)
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{
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assert(delay >= 0);
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Tick when = cpu->nextCycle(curTick() + cpu->ticks(delay));
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switch ((int)e_type)
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{
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case ResourcePool::InstGraduated:
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{
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DPRINTF(Resource, "Scheduling Inst-Graduated Resource Pool "
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"Event for tick %i.\n", curTick() + delay);
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ResPoolEventPri grad_pri = ResGrad_Pri;
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ResPoolEvent *res_pool_event =
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new ResPoolEvent(this,
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e_type,
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inst,
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inst->squashingStage,
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inst->seqNum,
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inst->readTid(),
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grad_pri);
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cpu->schedule(res_pool_event, when);
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}
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break;
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case ResourcePool::SquashAll:
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{
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DPRINTF(Resource, "Scheduling Squash Resource Pool Event for "
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"tick %i.\n", curTick() + delay);
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ResPoolEventPri squash_pri = ResSquash_Pri;
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ResPoolEvent *res_pool_event =
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new ResPoolEvent(this,
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e_type,
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inst,
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inst->squashingStage,
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inst->squashSeqNum,
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inst->readTid(),
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squash_pri);
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cpu->schedule(res_pool_event, when);
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}
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break;
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case ResourcePool::UpdateAfterContextSwitch:
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{
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DPRINTF(Resource, "Scheduling UpdatePC Resource Pool Event "
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"for tick %i.\n",
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curTick() + delay);
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ResPoolEvent *res_pool_event = new ResPoolEvent(this,
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e_type,
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inst,
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inst->squashingStage,
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inst->seqNum,
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inst->readTid());
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cpu->schedule(res_pool_event, when);
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}
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break;
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default:
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DPRINTF(Resource, "Ignoring Unrecognized CPU Event (%s).\n",
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InOrderCPU::eventNames[e_type]);
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}
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}
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void
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ResourcePool::unscheduleEvent(int res_idx, DynInstPtr inst)
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{
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resources[res_idx]->unscheduleEvent(inst);
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}
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void
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ResourcePool::squashAll(DynInstPtr inst, int stage_num,
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InstSeqNum done_seq_num, ThreadID tid)
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{
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DPRINTF(Resource, "[tid:%i] Broadcasting Squash All Event "
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" starting w/stage %i for all instructions above [sn:%i].\n",
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tid, stage_num, done_seq_num);
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int num_resources = resources.size();
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for (int idx = 0; idx < num_resources; idx++) {
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resources[idx]->squash(inst, stage_num, done_seq_num, tid);
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}
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}
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void
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ResourcePool::squashDueToMemStall(DynInstPtr inst, int stage_num,
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InstSeqNum done_seq_num, ThreadID tid)
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{
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DPRINTF(Resource, "[tid:%i] Broadcasting SquashDueToMemStall Event"
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" starting w/stage %i for all instructions above [sn:%i].\n",
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tid, stage_num, done_seq_num);
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int num_resources = resources.size();
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for (int idx = 0; idx < num_resources; idx++) {
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resources[idx]->squashDueToMemStall(inst, stage_num, done_seq_num,
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tid);
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}
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}
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void
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ResourcePool::activateThread(ThreadID tid)
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{
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bool do_activate = cpu->threadModel != InOrderCPU::SwitchOnCacheMiss ||
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cpu->numActiveThreads() < 1 ||
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cpu->activeThreadId() == tid;
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if (do_activate) {
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DPRINTF(Resource, "[tid:%i] Broadcasting Thread Activation to all "
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"resources.\n", tid);
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int num_resources = resources.size();
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for (int idx = 0; idx < num_resources; idx++) {
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resources[idx]->activateThread(tid);
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}
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} else {
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DPRINTF(Resource, "[tid:%i] Ignoring Thread Activation to all "
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"resources.\n", tid);
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}
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}
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void
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ResourcePool::deactivateThread(ThreadID tid)
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{
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DPRINTF(Resource, "[tid:%i] Broadcasting Thread Deactivation to all "
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"resources.\n", tid);
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int num_resources = resources.size();
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for (int idx = 0; idx < num_resources; idx++) {
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resources[idx]->deactivateThread(tid);
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}
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}
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void
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ResourcePool::suspendThread(ThreadID tid)
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{
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DPRINTF(Resource, "[tid:%i] Broadcasting Thread Suspension to all "
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"resources.\n", tid);
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int num_resources = resources.size();
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for (int idx = 0; idx < num_resources; idx++) {
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resources[idx]->suspendThread(tid);
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}
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}
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void
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ResourcePool::instGraduated(InstSeqNum seq_num, ThreadID tid)
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{
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DPRINTF(Resource, "[tid:%i] Broadcasting [sn:%i] graduation to "
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"appropriate resources.\n", tid, seq_num);
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int num_resources = gradObjects.size();
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for (int idx = 0; idx < num_resources; idx++) {
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resources[gradObjects[idx]]->instGraduated(seq_num, tid);
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}
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}
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void
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ResourcePool::updateAfterContextSwitch(DynInstPtr inst, ThreadID tid)
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{
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DPRINTF(Resource, "[tid:%i] Broadcasting Update PC to all resources.\n",
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tid);
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int num_resources = resources.size();
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for (int idx = 0; idx < num_resources; idx++) {
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resources[idx]->updateAfterContextSwitch(inst, tid);
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}
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}
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ResourcePool::ResPoolEvent::ResPoolEvent(ResourcePool *_resPool,
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InOrderCPU::CPUEventType e_type,
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DynInstPtr _inst,
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int stage_num,
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InstSeqNum seq_num,
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ThreadID _tid,
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ResPoolEventPri res_pri)
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: Event(res_pri), resPool(_resPool),
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eventType(e_type), inst(_inst), seqNum(seq_num),
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stageNum(stage_num), tid(_tid)
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{ }
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void
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ResourcePool::ResPoolEvent::process()
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{
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switch ((int)eventType)
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{
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case ResourcePool::InstGraduated:
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resPool->instGraduated(seqNum, tid);
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break;
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case ResourcePool::SquashAll:
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resPool->squashAll(inst, stageNum, seqNum, tid);
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break;
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case ResourcePool::UpdateAfterContextSwitch:
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resPool->updateAfterContextSwitch(inst, tid);
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break;
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default:
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fatal("Unrecognized Event Type");
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}
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resPool->cpu->cpuEventRemoveList.push(this);
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}
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const char *
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ResourcePool::ResPoolEvent::description() const
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{
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return "Resource Pool event";
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}
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/** Schedule resource event, regardless of its current state. */
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void
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ResourcePool::ResPoolEvent::scheduleEvent(int delay)
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{
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InOrderCPU *cpu = resPool->cpu;
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assert(!scheduled() || squashed());
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cpu->reschedule(this, cpu->nextCycle(curTick() + cpu->ticks(delay)), true);
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}
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/** Unschedule resource event, regardless of its current state. */
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void
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ResourcePool::ResPoolEvent::unscheduleEvent()
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{
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if (scheduled())
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squash();
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}
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